From 08115aec81c0e00431812c204297127fe9712f7f Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Fri, 8 Dec 2023 18:46:19 +0000 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change?= =?UTF-8?q?s=20to=20main=20this=20commit=20is=20based=20on?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.4 [skip ci] --- .github/workflows/libcxx-build-and-test.yaml | 4 +- .github/workflows/new-prs.yml | 31 +- bolt/lib/Passes/IndirectCallPromotion.cpp | 3 +- bolt/lib/Passes/ReorderAlgorithm.cpp | 4 +- .../Target/AArch64/AArch64MCPlusBuilder.cpp | 6 + bolt/test/AArch64/fp-reg-spill.s | 19 + .../AArch64/instrumentation-ind-call.c | 2 +- clang-tools-extra/clang-tidy/ClangTidy.cpp | 29 +- .../clang-tidy/modernize/CMakeLists.txt | 1 + .../modernize/ModernizeTidyModule.cpp | 3 + .../modernize/UseStdNumbersCheck.cpp | 448 ++ .../clang-tidy/modernize/UseStdNumbersCheck.h | 49 + clang-tools-extra/docs/ReleaseNotes.rst | 7 + .../docs/clang-tidy/checks/list.rst | 1 + .../checks/modernize/use-std-numbers.rst | 74 + .../checkers/modernize/use-std-numbers.cpp | 493 ++ .../Inputs/compilation-database/template.json | 9 +- .../clang-tidy-run-with-database.cpp | 11 +- clang/CMakeLists.txt | 7 +- clang/docs/InternalsManual.rst | 27 +- clang/docs/LanguageExtensions.rst | 2 +- clang/docs/ReleaseNotes.rst | 8 + clang/include/clang/Basic/Attr.td | 8 + clang/include/clang/Basic/AttrDocs.td | 44 + clang/include/clang/Basic/CodeGenOptions.def | 88 +- clang/include/clang/Basic/CodeGenOptions.h | 4 + clang/include/clang/Basic/DebugOptions.def | 146 + .../clang/Basic/DiagnosticParseKinds.td | 2 +- clang/include/clang/Basic/FileEntry.h | 1 + clang/include/clang/Basic/OpenACCKinds.h | 2 +- clang/include/clang/Basic/arm_sme.td | 28 +- clang/include/clang/Basic/arm_sve.td | 68 +- clang/include/clang/Basic/arm_sve_sme_incl.td | 1 + clang/include/clang/Driver/Options.td | 5 +- .../SerializablePathCollection.h | 2 +- clang/include/clang/Lex/PPCallbacks.h | 10 +- clang/include/clang/Parse/Parser.h | 7 +- clang/include/clang/Sema/Sema.h | 2 + clang/include/module.modulemap | 1 + .../FlowSensitive/DataflowEnvironment.cpp | 7 +- clang/lib/Basic/CodeGenOptions.cpp | 35 + clang/lib/Basic/Targets/SystemZ.h | 2 +- clang/lib/CodeGen/CGAtomic.cpp | 8 +- clang/lib/CodeGen/CGBuilder.h | 17 +- clang/lib/CodeGen/CGBuiltin.cpp | 136 +- clang/lib/CodeGen/CGDebugInfo.cpp | 73 - clang/lib/CodeGen/CGDebugInfo.h | 6 - clang/lib/CodeGen/CGExpr.cpp | 34 + clang/lib/CodeGen/CGExprScalar.cpp | 6 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 4 +- clang/lib/CodeGen/CodeGenModule.cpp | 38 +- clang/lib/Driver/Driver.cpp | 6 - clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 10 +- clang/lib/Driver/ToolChains/Flang.cpp | 24 +- .../ObjCPropertyAttributeOrderFixer.cpp | 120 +- .../Format/ObjCPropertyAttributeOrderFixer.h | 4 +- clang/lib/Format/TokenAnnotator.h | 5 + clang/lib/Format/UnwrappedLineFormatter.cpp | 19 +- clang/lib/Frontend/CompilerInvocation.cpp | 13 + clang/lib/Headers/bmiintrin.h | 22 +- .../SerializablePathCollection.cpp | 6 +- clang/lib/Parse/ParseOpenACC.cpp | 194 +- clang/lib/Rewrite/Rewriter.cpp | 13 +- clang/lib/Sema/Sema.cpp | 4 +- clang/lib/Sema/SemaChecking.cpp | 106 +- clang/lib/Sema/SemaDeclAttr.cpp | 3 + .../Checkers/ArrayBoundCheckerV2.cpp | 139 +- .../StaticAnalyzer/Checkers/StreamChecker.cpp | 3 + .../test/Analysis/out-of-bounds-diagnostics.c | 113 +- clang/test/Analysis/out-of-bounds-new.cpp | 26 + .../test/Analysis/taint-diagnostic-visitor.c | 4 +- clang/test/CXX/drs/dr5xx.cpp | 617 +- clang/test/CXX/drs/dr6xx.cpp | 689 +- clang/test/ClangScanDeps/strip-codegen-args.m | 58 + .../CodeGen/SystemZ/atomic_is_lock_free.c | 98 + .../SystemZ/gnu-atomic-builtins-i128-16Al.c | 257 + .../SystemZ/gnu-atomic-builtins-i128-8Al.c | 301 + .../CodeGen/SystemZ/gnu-atomic-builtins-i16.c | 219 + .../CodeGen/SystemZ/gnu-atomic-builtins-i32.c | 219 + .../CodeGen/SystemZ/gnu-atomic-builtins-i64.c | 219 + .../CodeGen/SystemZ/gnu-atomic-builtins-i8.c | 219 + .../aarch64-sme-intrinsics/acle_sme_ld1.c | 32 +- .../acle_sme_ld1_vnum.c | 32 +- .../aarch64-sme-intrinsics/acle_sme_st1.c | 32 +- .../acle_sme_st1_vnum.c | 32 +- .../aarch64-sme2-intrinsics/acle_sme2_cvt.c | 499 ++ .../aarch64-sme2-intrinsics/acle_sme2_cvtn.c | 242 + .../acle_sme2_ldr_str_zt.c | 2 +- .../acle_sme2_luti2_lane_zt.c | 138 + .../acle_sme2_luti2_lane_zt_x2.c | 209 + .../acle_sme2_luti2_lane_zt_x4.c | 280 + .../acle_sme2_luti4_lane_zt.c | 137 + .../acle_sme2_luti4_lane_zt_x2.c | 209 + .../acle_sme2_luti4_lane_zt_x4.c | 233 + .../acle_sve2p1_pfalse.c | 17 +- .../acle_sve2p1_ptrue.c | 16 +- clang/test/CodeGen/atomic-ops.c | 4 +- clang/test/CodeGen/attr-target-clones.c | 34 +- .../CodeGen/bpf-preserve-static-offset-arr.c | 33 + .../bpf-preserve-static-offset-bitfield.c | 31 + .../bpf-preserve-static-offset-lvalue.c | 28 + .../bpf-preserve-static-offset-non-bpf.c | 18 + .../CodeGen/bpf-preserve-static-offset-pai.c | 29 + .../test/CodeGen/ms-intrinsics-underaligned.c | 110 + clang/test/CodeGen/ms-intrinsics.c | 4 +- .../member-function-pointer.cpp | 2 +- clang/test/CodeGenCXX/attr-target-clones.cpp | 27 +- clang/test/CodeGenCXX/debug-info-class.cpp | 12 +- .../debug-info-static-inline-member.cpp | 104 - .../CodeGenCXX/debug-info-static-member.cpp | 20 +- clang/test/Driver/aarch64-thread-pointer.c | 20 +- clang/test/Driver/arc-exceptions.m | 4 +- clang/test/Driver/arm-arch-darwin.c | 8 +- clang/test/Frontend/darwin-eabi.c | 6 +- clang/test/Frontend/sarif-diagnostics.cpp | 4 +- clang/test/Headers/__clang_hip_math.hip | 24 +- clang/test/Headers/arm-neon-header.c | 2 +- ...a-attribute-supported-attributes-list.test | 1 + ...bute_parallel_for_simd_private_codegen.cpp | 60 +- .../distribute_simd_private_codegen.cpp | 60 +- .../OpenMP/parallel_reduction_codegen.cpp | 6 +- .../OpenMP/simd_private_taskloop_codegen.cpp | 2692 ++++++++ ...bute_parallel_for_simd_private_codegen.cpp | 22 +- ..._teams_distribute_simd_private_codegen.cpp | 20 +- ...bute_parallel_for_simd_private_codegen.cpp | 38 +- .../teams_distribute_simd_private_codegen.cpp | 28 +- .../ParserOpenACC/parse-cache-construct.c | 166 + .../ParserOpenACC/parse-cache-construct.cpp | 51 + clang/test/ParserOpenACC/parse-constructs.c | 2 +- clang/test/ParserOpenACC/unimplemented.c | 12 +- clang/test/ParserOpenACC/unimplemented.cpp | 12 +- .../aarch64-sme2-intrinsics/acle_sme2_imm.cpp | 163 +- ...attr-preserve-static-offset-warns-nonbpf.c | 6 + .../bpf-attr-preserve-static-offset-warns.c | 23 + .../Sema/bpf-attr-preserve-static-offset.c | 27 + clang/test/SemaCXX/builtin-dump-struct.cpp | 12 + clang/tools/clang-format/clang-format-diff.py | 4 +- clang/tools/clang-format/git-clang-format | 34 +- .../FlowSensitive/DataflowEnvironmentTest.cpp | 52 + clang/unittests/Basic/FileManagerTest.cpp | 4 + .../ObjCPropertyAttributeOrderFixerTest.cpp | 18 +- clang/utils/TableGen/SveEmitter.cpp | 6 + clang/www/cxx_dr_status.html | 52 +- compiler-rt/CMakeLists.txt | 21 +- compiler-rt/lib/asan/asan_interceptors.cpp | 81 +- compiler-rt/lib/asan/asan_interceptors.h | 8 - compiler-rt/lib/asan/asan_internal.h | 2 +- compiler-rt/lib/asan/asan_lock.h | 0 compiler-rt/lib/asan/asan_malloc_linux.cpp | 7 +- compiler-rt/lib/asan/asan_malloc_mac.cpp | 5 +- compiler-rt/lib/asan/asan_rtl.cpp | 18 +- .../lib/hwasan/hwasan_interceptors.cpp | 13 +- .../sanitizer_common_interceptors.inc | 2 +- .../sanitizer_platform_limits_openbsd.cpp | 0 .../sanitizer_platform_limits_openbsd.h | 0 compiler-rt/lib/scudo/standalone/combined.h | 6 +- .../standalone/include/scudo/interface.h | 3 +- .../scudo/standalone/wrappers_c_bionic.cpp | 13 +- .../test/hwasan/TestCases/Linux/syscalls.cpp | 7 +- .../test/hwasan/TestCases/memset-recover.cpp | 32 + .../Darwin/x86-64/jit-re-dlopen-data-reset.S | 4 +- .../Darwin/x86-64/jit-re-dlopen-trivial.S | 4 +- .../Darwin/x86-64/trivial-jit-dlopen-nested.c | 4 +- .../Darwin/x86-64/trivial-jit-dlopen.c | 4 +- .../TestCases/Linux/ppc64/trivial-atexit.S | 6 + .../TestCases/Linux/x86-64/trivial-atexit.S | 6 + .../Windows/x86-64/trivial-jit-dlopen.c | 4 +- .../include/flang/Frontend/CompilerInstance.h | 23 + .../flang/Frontend/CompilerInvocation.h | 14 +- .../include/flang/Frontend/FrontendActions.h | 4 - flang/include/flang/Lower/Bridge.h | 13 +- .../include/flang/Lower/ConvertExprToHLFIR.h | 6 + flang/include/flang/Lower/ConvertVariable.h | 19 +- .../include/flang/Optimizer/Dialect/FIROps.td | 8 +- .../flang/Optimizer/Support/DataLayout.h | 39 + flang/include/flang/Tools/TargetSetup.h | 40 + flang/lib/Frontend/CompilerInstance.cpp | 134 +- flang/lib/Frontend/CompilerInvocation.cpp | 44 +- flang/lib/Frontend/FrontendActions.cpp | 177 +- flang/lib/Lower/Bridge.cpp | 6 +- flang/lib/Lower/CallInterface.cpp | 2 +- flang/lib/Lower/ConvertCall.cpp | 8 +- flang/lib/Lower/ConvertExprToHLFIR.cpp | 23 +- flang/lib/Lower/ConvertVariable.cpp | 39 +- flang/lib/Lower/OpenMP.cpp | 33 +- flang/lib/Optimizer/CodeGen/CodeGen.cpp | 18 +- flang/lib/Optimizer/Support/CMakeLists.txt | 2 + flang/lib/Optimizer/Support/DataLayout.cpp | 47 + flang/runtime/ISO_Fortran_binding.cpp | 2 +- flang/runtime/exceptions.cpp | 8 +- flang/runtime/unit.cpp | 4 + ...piler_options.f90 => compiler-options.f90} | 2 +- flang/test/Driver/driver-help-hidden.f90 | 2 - flang/test/Driver/driver-help.f90 | 4 - flang/test/Driver/falias-analysis.f90 | 9 +- .../Driver/{fast_math.f90 => fast-math.f90} | 0 .../{flang_f_opts.f90 => flang-f-opts.f90} | 0 ...plicate_main.f90 => no-duplicate-main.f90} | 0 flang/test/Evaluate/fold-nearest.f90 | 4 + flang/test/Fir/convert-to-llvm.fir | 10 +- flang/test/Fir/dispatch.f90 | 51 +- flang/test/Fir/fir-ops.fir | 32 +- flang/test/Fir/tco-default-datalayout.fir | 12 + flang/test/Fir/tco-explicit-datalayout.fir | 13 + flang/test/HLFIR/call_with_poly_dummy.f90 | 2 +- flang/test/Lower/HLFIR/binary-ops.f90 | 4 +- .../Lower/HLFIR/user-defined-assignment.f90 | 2 +- flang/test/Lower/Intrinsics/bessel_jn.f90 | 4 +- flang/test/Lower/Intrinsics/bessel_yn.f90 | 4 +- flang/test/Lower/Intrinsics/dim.f90 | 2 +- flang/test/Lower/Intrinsics/ieee_compare.f90 | 36 +- flang/test/Lower/Intrinsics/ieee_logb.f90 | 2 +- flang/test/Lower/Intrinsics/ieee_max_min.f90 | 64 +- .../test/Lower/Intrinsics/ieee_unordered.f90 | 6 +- flang/test/Lower/Intrinsics/min.f90 | 4 +- flang/test/Lower/Intrinsics/modulo.f90 | 6 +- flang/test/Lower/Intrinsics/nearest.f90 | 10 +- flang/test/Lower/OpenACC/acc-reduction.f90 | 14 +- flang/test/Lower/allocatable-polymorphic.f90 | 251 +- flang/test/Lower/arithmetic-goto.f90 | 4 +- flang/test/Lower/array-elemental-calls-2.f90 | 2 +- flang/test/Lower/array-expression-slice-1.f90 | 18 +- .../test/Lower/array-user-def-assignments.f90 | 6 +- flang/test/Lower/assignment.f90 | 12 +- flang/test/Lower/bbc-host-datalayout.f90 | 9 + flang/test/Lower/bbc-target-datalayout.f90 | 10 + .../Lower/default-initialization-globals.f90 | 6 +- flang/test/Lower/dispatch.f90 | 144 +- flang/test/Lower/forall/forall-construct.f90 | 2 +- flang/test/Lower/forall/forall-where.f90 | 2 +- flang/test/Lower/host-associated.f90 | 2 +- flang/test/Lower/nullify-polymorphic.f90 | 5 +- flang/test/Lower/real-operations-2.f90 | 12 +- flang/test/Lower/where.f90 | 6 +- flang/test/Semantics/kinds04_q10.f90 | 1 + flang/test/Semantics/real10-x86-01.f90 | 1 + flang/test/Semantics/real10-x86-02.f90 | 1 + flang/test/Semantics/realkinds-aarch64-01.f90 | 1 + flang/test/Transforms/simplifyintrinsics.fir | 4 +- flang/tools/bbc/CMakeLists.txt | 3 + flang/tools/bbc/bbc.cpp | 69 +- flang/tools/f18/CMakeLists.txt | 11 +- flang/tools/tco/tco.cpp | 14 +- flang/unittests/Evaluate/real.cpp | 4 + .../unittests/Frontend/FrontendActionTest.cpp | 19 +- flang/unittests/Runtime/CommandTest.cpp | 12 +- flang/unittests/Runtime/MatmulTranspose.cpp | 2 +- .../modules/prepare_libc_gpu_build.cmake | 3 + libc/config/linux/aarch64/entrypoints.txt | 4 +- libc/config/linux/app.h | 4 +- libc/config/linux/arm/entrypoints.txt | 3 + libc/config/linux/riscv/entrypoints.txt | 4 +- libc/config/linux/x86_64/entrypoints.txt | 4 +- libc/docs/dev/undefined_behavior.rst | 7 + libc/include/sys/prctl.h.def | 2 - libc/spec/linux.td | 15 +- libc/spec/spec.td | 2 - libc/src/__support/CMakeLists.txt | 10 +- libc/src/__support/FPUtil/CMakeLists.txt | 2 - libc/src/__support/FPUtil/FPBits.h | 3 +- libc/src/__support/FPUtil/Hypot.h | 11 +- .../__support/FPUtil/generic/CMakeLists.txt | 5 +- libc/src/__support/FPUtil/generic/FMA.h | 8 +- libc/src/__support/FPUtil/generic/FMod.h | 8 +- libc/src/__support/FPUtil/generic/sqrt.h | 13 +- .../FPUtil/generic/sqrt_80_bit_long_double.h | 6 +- libc/src/__support/HashTable/CMakeLists.txt | 11 +- libc/src/__support/HashTable/bitmask.h | 10 +- .../HashTable/generic/bitmask_impl.inc | 15 +- .../__support/HashTable/sse2/bitmask_impl.inc | 13 +- libc/src/__support/HashTable/table.h | 241 +- libc/src/__support/UInt.h | 5 +- libc/src/__support/bit.h | 117 - libc/src/__support/float_to_string.h | 17 +- libc/src/__support/hash.h | 9 +- libc/src/__support/integer_utils.h | 2 +- libc/src/__support/memory_size.h | 17 +- libc/src/__support/str_to_float.h | 5 +- libc/src/__support/threads/linux/thread.cpp | 2 +- libc/src/__support/wctype_utils.h | 6 +- libc/src/math/generic/CMakeLists.txt | 1 - libc/src/math/generic/math_utils.h | 17 +- libc/src/math/generic/powf.cpp | 5 +- libc/src/search/CMakeLists.txt | 3 +- libc/src/search/hcreate.cpp | 6 + libc/src/search/hdestroy.cpp | 4 +- libc/src/search/hsearch.cpp | 21 +- libc/src/search/hsearch_r.cpp | 3 +- .../stdio/printf_core/float_dec_converter.h | 15 +- .../stdio/printf_core/float_hex_converter.h | 6 +- libc/src/stdlib/getenv.cpp | 2 +- libc/src/string/memory_utils/op_aarch64.h | 5 +- libc/src/string/memory_utils/op_builtin.h | 22 +- libc/src/string/memory_utils/utils.h | 47 +- libc/src/sys/CMakeLists.txt | 1 + libc/src/sys/mman/CMakeLists.txt | 7 - libc/src/sys/mman/linux/CMakeLists.txt | 13 - libc/src/sys/mman/linux/mincore.cpp | 28 - libc/src/sys/prctl/CMakeLists.txt | 10 + libc/src/sys/prctl/linux/CMakeLists.txt | 12 + libc/src/sys/prctl/linux/prctl.cpp | 37 + .../src/sys/{mman/mincore.h => prctl/prctl.h} | 13 +- libc/startup/linux/aarch64/start.cpp | 18 +- libc/startup/linux/riscv/start.cpp | 18 +- libc/startup/linux/x86_64/start.cpp | 53 +- libc/test/src/__support/CMakeLists.txt | 13 - .../src/__support/HashTable/CMakeLists.txt | 3 + .../src/__support/HashTable/bitmask_test.cpp | 6 +- .../src/__support/HashTable/table_test.cpp | 82 +- libc/test/src/__support/bit_test.cpp | 67 - libc/test/src/__support/memory_size_test.cpp | 13 +- libc/test/src/search/hsearch_test.cpp | 34 +- .../src/string/memory_utils/utils_test.cpp | 60 - libc/test/src/sys/CMakeLists.txt | 1 + libc/test/src/sys/mman/linux/CMakeLists.txt | 17 - libc/test/src/sys/mman/linux/mincore_test.cpp | 123 - libc/test/src/sys/prctl/CMakeLists.txt | 3 + libc/test/src/sys/prctl/linux/CMakeLists.txt | 14 + libc/test/src/sys/prctl/linux/prctl_test.cpp | 44 + libcxx/docs/Contributing.rst | 1 - libcxx/docs/Hardening.rst | 119 +- libcxx/docs/Status/Cxx23Papers.csv | 2 +- libcxx/include/__algorithm/clamp.h | 2 +- libcxx/include/__algorithm/copy_n.h | 6 +- libcxx/include/__algorithm/equal.h | 4 +- libcxx/include/__algorithm/fill.h | 4 +- libcxx/include/__algorithm/fill_n.h | 2 +- libcxx/include/__algorithm/find_first_of.h | 2 +- libcxx/include/__algorithm/for_each_n.h | 2 +- libcxx/include/__algorithm/generate_n.h | 2 +- libcxx/include/__algorithm/inplace_merge.h | 4 +- libcxx/include/__algorithm/is_heap.h | 2 +- libcxx/include/__algorithm/is_heap_until.h | 2 +- libcxx/include/__algorithm/is_sorted.h | 4 +- libcxx/include/__algorithm/is_sorted_until.h | 4 +- .../__algorithm/lexicographical_compare.h | 4 +- libcxx/include/__algorithm/max.h | 6 +- libcxx/include/__algorithm/max_element.h | 4 +- libcxx/include/__algorithm/merge.h | 8 +- libcxx/include/__algorithm/min.h | 6 +- libcxx/include/__algorithm/min_element.h | 2 +- libcxx/include/__algorithm/next_permutation.h | 2 +- libcxx/include/__algorithm/nth_element.h | 8 +- libcxx/include/__algorithm/partial_sort.h | 2 +- .../include/__algorithm/partial_sort_copy.h | 2 +- libcxx/include/__algorithm/partition_point.h | 6 +- libcxx/include/__algorithm/prev_permutation.h | 2 +- .../include/__algorithm/ranges_rotate_copy.h | 5 +- libcxx/include/__algorithm/remove.h | 4 +- libcxx/include/__algorithm/remove_if.h | 4 +- libcxx/include/__algorithm/rotate.h | 10 +- libcxx/include/__algorithm/rotate_copy.h | 2 +- libcxx/include/__algorithm/sample.h | 4 +- libcxx/include/__algorithm/shift_left.h | 2 +- libcxx/include/__algorithm/shift_right.h | 10 +- libcxx/include/__algorithm/sift_down.h | 2 +- libcxx/include/__algorithm/stable_partition.h | 4 +- libcxx/include/__algorithm/stable_sort.h | 2 +- libcxx/include/__availability | 12 + .../compare_partial_order_fallback.h | 30 +- .../__compare/compare_strong_order_fallback.h | 24 +- libcxx/include/__compare/compare_three_way.h | 4 +- .../__compare/compare_weak_order_fallback.h | 24 +- libcxx/include/__compare/partial_order.h | 24 +- libcxx/include/__compare/strong_order.h | 46 +- libcxx/include/__compare/weak_order.h | 32 +- libcxx/include/__concepts/assignable.h | 2 +- libcxx/include/__concepts/boolean_testable.h | 2 +- libcxx/include/__concepts/invocable.h | 2 +- libcxx/include/__concepts/swappable.h | 16 +- libcxx/include/__config | 6 +- libcxx/include/__coroutine/coroutine_handle.h | 2 +- libcxx/include/__filesystem/directory_entry.h | 6 +- .../include/__filesystem/directory_iterator.h | 6 +- .../include/__filesystem/filesystem_error.h | 2 +- libcxx/include/__filesystem/path.h | 66 +- .../recursive_directory_iterator.h | 6 +- libcxx/include/__filesystem/u8path.h | 6 +- libcxx/include/__format/buffer.h | 42 +- .../include/__format/escaped_output_table.h | 2 + .../extended_grapheme_cluster_table.h | 2 + libcxx/include/__format/format_arg.h | 40 +- libcxx/include/__format/format_context.h | 24 +- libcxx/include/__format/format_functions.h | 124 +- .../__format/formatter_floating_point.h | 62 +- libcxx/include/__format/formatter_integral.h | 22 +- libcxx/include/__format/formatter_output.h | 50 +- .../include/__format/parser_std_format_spec.h | 4 +- libcxx/include/__format/write_escaped.h | 8 +- libcxx/include/__functional/bind.h | 32 +- libcxx/include/__functional/bind_back.h | 12 +- libcxx/include/__functional/bind_front.h | 8 +- libcxx/include/__functional/compose.h | 12 +- libcxx/include/__functional/function.h | 80 +- libcxx/include/__functional/hash.h | 4 +- libcxx/include/__functional/identity.h | 2 +- libcxx/include/__functional/invoke.h | 2 +- libcxx/include/__functional/not_fn.h | 8 +- libcxx/include/__functional/operations.h | 114 +- libcxx/include/__functional/perfect_forward.h | 26 +- .../include/__functional/ranges_operations.h | 24 +- .../include/__functional/reference_wrapper.h | 2 +- .../include/__functional/weak_result_type.h | 2 +- libcxx/include/__hash_table | 96 +- libcxx/include/__iterator/advance.h | 8 +- .../include/__iterator/back_insert_iterator.h | 4 +- libcxx/include/__iterator/common_iterator.h | 54 +- libcxx/include/__iterator/concepts.h | 12 +- libcxx/include/__iterator/counted_iterator.h | 6 +- libcxx/include/__iterator/distance.h | 2 +- .../__iterator/front_insert_iterator.h | 4 +- libcxx/include/__iterator/insert_iterator.h | 4 +- libcxx/include/__iterator/istream_iterator.h | 4 +- libcxx/include/__iterator/iter_swap.h | 24 +- libcxx/include/__iterator/next.h | 2 +- libcxx/include/__iterator/ostream_iterator.h | 4 +- libcxx/include/__iterator/prev.h | 2 +- libcxx/include/__iterator/reverse_access.h | 8 +- libcxx/include/__iterator/wrap_iter.h | 4 +- libcxx/include/__locale | 6 +- .../locale_base_api/locale_guard.h | 2 +- libcxx/include/__memory/allocation_guard.h | 2 +- libcxx/include/__memory/allocator.h | 18 +- libcxx/include/__memory/allocator_arg_t.h | 6 +- libcxx/include/__memory/allocator_traits.h | 2 +- .../include/__memory/builtin_new_allocator.h | 6 +- libcxx/include/__memory/pointer_traits.h | 10 +- libcxx/include/__memory/ranges_construct_at.h | 8 +- .../ranges_uninitialized_algorithms.h | 24 +- .../include/__memory/raw_storage_iterator.h | 4 +- libcxx/include/__memory/shared_ptr.h | 60 +- libcxx/include/__memory/swap_allocator.h | 4 +- libcxx/include/__memory/temporary_buffer.h | 4 +- .../__memory/uninitialized_algorithms.h | 74 +- libcxx/include/__memory/unique_ptr.h | 24 +- libcxx/include/__memory/voidify.h | 2 +- libcxx/include/__mutex/once_flag.h | 4 +- libcxx/include/__node_handle | 18 +- libcxx/include/__numeric/accumulate.h | 4 +- .../include/__numeric/adjacent_difference.h | 8 +- libcxx/include/__numeric/exclusive_scan.h | 6 +- libcxx/include/__numeric/gcd_lcm.h | 6 +- libcxx/include/__numeric/inclusive_scan.h | 4 +- libcxx/include/__numeric/inner_product.h | 4 +- libcxx/include/__numeric/midpoint.h | 2 +- libcxx/include/__numeric/partial_sum.h | 4 +- libcxx/include/__numeric/reduce.h | 4 +- .../__numeric/transform_inclusive_scan.h | 2 +- libcxx/include/__numeric/transform_reduce.h | 4 +- .../include/__random/binomial_distribution.h | 6 +- libcxx/include/__random/cauchy_distribution.h | 2 +- .../include/__random/discard_block_engine.h | 2 +- .../include/__random/discrete_distribution.h | 8 +- .../__random/exponential_distribution.h | 4 +- .../__random/extreme_value_distribution.h | 2 +- libcxx/include/__random/gamma_distribution.h | 10 +- .../__random/independent_bits_engine.h | 2 +- .../include/__random/lognormal_distribution.h | 4 +- .../__random/mersenne_twister_engine.h | 22 +- libcxx/include/__random/normal_distribution.h | 2 +- .../piecewise_constant_distribution.h | 6 +- .../__random/piecewise_linear_distribution.h | 4 +- .../include/__random/poisson_distribution.h | 30 +- libcxx/include/__random/seed_seq.h | 6 +- .../include/__random/shuffle_order_engine.h | 4 +- .../include/__random/student_t_distribution.h | 2 +- .../__random/subtract_with_carry_engine.h | 22 +- .../__random/uniform_real_distribution.h | 2 +- .../include/__random/weibull_distribution.h | 2 +- libcxx/include/__split_buffer | 118 +- libcxx/include/__string/char_traits.h | 4 +- .../include/__string/extern_template_lists.h | 3 + libcxx/include/__thread/thread.h | 18 +- libcxx/include/__threading_support | 4 +- libcxx/include/__tree | 188 +- libcxx/include/__type_traits/invoke.h | 4 +- .../__type_traits/is_nothrow_constructible.h | 2 +- .../__type_traits/is_nothrow_convertible.h | 2 +- libcxx/include/__utility/cmp.h | 12 +- libcxx/include/__utility/exchange.h | 4 +- libcxx/include/__utility/integer_sequence.h | 2 + libcxx/include/__utility/swap.h | 6 +- libcxx/include/__utility/to_underlying.h | 2 +- libcxx/include/any | 36 +- libcxx/include/array | 46 +- libcxx/include/barrier | 4 +- libcxx/include/bitset | 34 +- libcxx/include/chrono | 4 + libcxx/include/complex | 6 +- libcxx/include/condition_variable | 2 +- libcxx/include/deque | 239 +- libcxx/include/experimental/__config | 3 - libcxx/include/experimental/__memory | 8 +- libcxx/include/experimental/iterator | 6 +- libcxx/include/experimental/propagate_const | 154 +- libcxx/include/ext/hash_map | 14 +- libcxx/include/ext/hash_set | 6 +- libcxx/include/forward_list | 40 +- libcxx/include/fstream | 54 +- libcxx/include/future | 154 +- libcxx/include/iomanip | 2 +- libcxx/include/ios | 8 +- libcxx/include/istream | 42 +- libcxx/include/limits | 2 +- libcxx/include/list | 64 +- libcxx/include/locale | 32 +- libcxx/include/map | 152 +- libcxx/include/memory | 4 + libcxx/include/mutex | 6 +- libcxx/include/new | 2 +- libcxx/include/optional | 110 +- libcxx/include/ostream | 22 +- libcxx/include/queue | 70 +- libcxx/include/regex | 212 +- libcxx/include/scoped_allocator | 48 +- libcxx/include/set | 60 +- libcxx/include/shared_mutex | 16 +- libcxx/include/source_location | 6 +- libcxx/include/span | 24 +- libcxx/include/sstream | 36 +- libcxx/include/stack | 18 +- libcxx/include/stdexcept | 8 +- libcxx/include/streambuf | 20 +- libcxx/include/string | 4 + libcxx/include/string_view | 19 +- libcxx/include/strstream | 28 +- libcxx/include/tuple | 142 +- libcxx/include/unordered_map | 116 +- libcxx/include/unordered_set | 50 +- libcxx/include/valarray | 20 +- libcxx/include/variant | 194 +- libcxx/include/vector | 23 +- libcxx/include/version | 4 +- libcxx/src/chrono.cpp | 4 +- libcxx/src/include/to_chars_floating_point.h | 42 +- libcxx/src/ios.cpp | 34 +- libcxx/src/iostream.cpp | 4 +- libcxx/src/locale.cpp | 38 +- libcxx/src/regex.cpp | 4 +- libcxx/src/std_stream.h | 12 +- libcxx/src/strstream.cpp | 12 +- libcxx/src/support/win32/thread_win32.cpp | 2 +- libcxx/src/vector.cpp | 4 +- .../layout_left/assert.conversion.pass.cpp | 2 +- .../layout_left/assert.ctor.extents.pass.cpp | 2 +- .../assert.index_operator.pass.cpp | 12 +- .../mdspan/layout_left/assert.stride.pass.cpp | 2 +- .../layout_right/assert.conversion.pass.cpp | 2 +- .../layout_right/assert.ctor.extents.pass.cpp | 2 +- .../assert.index_operator.pass.cpp | 12 +- .../layout_right/assert.stride.pass.cpp | 2 +- .../layout_stride/assert.conversion.pass.cpp | 14 +- ...ert.ctor.extents_array.non_unique.pass.cpp | 8 +- .../assert.ctor.extents_array.pass.cpp | 8 +- ...sert.ctor.extents_span.non_unique.pass.cpp | 8 +- .../assert.ctor.extents_span.pass.cpp | 9 +- .../assert.index_operator.pass.cpp | 12 +- .../layout_stride/assert.stride.pass.cpp | 2 +- .../mdspan/mdspan/assert.conversion.pass.cpp | 2 +- .../views/mdspan/mdspan/assert.size.pass.cpp | 8 +- .../alg.move/move.pass.cpp | 2 +- .../alg.move/move_backward.pass.cpp | 2 +- .../alg.replace/pstl.replace.pass.cpp | 12 +- .../alg.replace/pstl.replace_copy.pass.cpp | 12 +- .../alg.replace/pstl.replace_copy_if.pass.cpp | 42 +- .../alg.replace/pstl.replace_if.pass.cpp | 14 +- .../alg.rotate/ranges.rotate_copy.pass.cpp | 9 +- .../alg.nonmodifying/alg.count/count.pass.cpp | 2 +- .../alg.sorting/alg.merge/pstl.merge.pass.cpp | 24 +- ...lexicographical_compare_three_way.pass.cpp | 4 +- ...ographical_compare_three_way_comp.pass.cpp | 4 +- .../test/std/containers/from_range_helpers.h | 9 + .../views/mdspan/ConvertibleToIntegral.h | 8 +- .../layout_left/ctor.layout_right.pass.cpp | 4 +- .../layout_left/ctor.layout_stride.pass.cpp | 4 +- .../mdspan/layout_left/ctor.mapping.pass.cpp | 2 +- .../mdspan/layout_left/properties.pass.cpp | 2 +- .../layout_right/ctor.layout_left.pass.cpp | 4 +- .../layout_right/ctor.layout_stride.pass.cpp | 4 +- .../mdspan/layout_right/ctor.mapping.pass.cpp | 2 +- .../mdspan/layout_right/properties.pass.cpp | 2 +- .../mdspan/layout_stride/comparison.pass.cpp | 2 +- .../ctor.strided_mapping.pass.cpp | 2 +- .../mdspan/layout_stride/deduction.pass.cpp | 16 +- .../is_exhaustive_corner_case.pass.cpp | 2 +- .../mdspan/layout_stride/properties.pass.cpp | 2 +- .../views/mdspan/mdspan/assign.pass.cpp | 9 +- .../views/mdspan/mdspan/ctor.copy.pass.cpp | 5 +- .../views/mdspan/mdspan/ctor.default.pass.cpp | 3 +- .../mdspan/mdspan/ctor.dh_array.pass.cpp | 14 +- .../mdspan/mdspan/ctor.dh_extents.pass.cpp | 14 +- .../mdspan/mdspan/ctor.dh_integers.pass.cpp | 14 +- .../views/mdspan/mdspan/ctor.dh_map.pass.cpp | 2 +- .../mdspan/mdspan/ctor.dh_map_acc.pass.cpp | 2 +- .../views/mdspan/mdspan/ctor.dh_span.pass.cpp | 14 +- .../views/mdspan/mdspan/ctor.move.pass.cpp | 5 +- .../views/mdspan/mdspan/mapping.verify.cpp | 2 +- .../views/mdspan/mdspan/move.pass.cpp | 5 +- .../views/mdspan/mdspan/swap.pass.cpp | 2 +- .../span.cons/iterator_sentinel.pass.cpp | 2 +- .../generic_category.pass.cpp | 3 +- .../system_category.pass.cpp | 3 +- .../member_swap_noexcept.pass.cpp | 2 +- .../nonmember_swap_noexcept.pass.cpp | 2 +- .../source_location.version.compile.pass.cpp | 48 +- .../version.version.compile.pass.cpp | 48 +- .../numerics/rand/rand.device/ctor.pass.cpp | 1 + .../range.chunk.by.iter/compare.pass.cpp | 12 +- .../range.chunk.by.iter/decrement.pass.cpp | 62 +- .../range.chunk.by.iter/deref.pass.cpp | 2 +- .../range.chunk.by.iter/increment.pass.cpp | 52 +- .../range.filter/iterator/arrow.pass.cpp | 2 +- .../range.repeat.view/size.pass.cpp | 5 +- .../string.view.comparison/equal.pass.cpp | 4 +- .../string.view.comparison/greater.pass.cpp | 4 +- .../greater_equal.pass.cpp | 4 +- .../string.view.comparison/less.pass.cpp | 4 +- .../less_equal.pass.cpp | 4 +- .../string.view.comparison/not_equal.pass.cpp | 4 +- .../thread.lock.scoped/mutex.pass.cpp | 1 + .../default.pass.cpp | 3 +- libcxx/test/support/container_debug_tests.h | 4 +- .../test/support/msvc_stdlib_force_include.h | 113 +- libcxx/test/support/test_macros.h | 29 +- libcxx/utils/clang-format-merge-driver.sh | 37 + libcxx/utils/generate_escaped_output_table.py | 2 + ...enerate_extended_grapheme_cluster_table.py | 2 + .../generate_feature_test_macro_components.py | 2 - libcxxabi/src/demangle/DemangleConfig.h | 2 +- lld/COFF/Config.h | 7 + lld/COFF/Driver.cpp | 8 + lld/COFF/InputFiles.cpp | 19 +- lld/COFF/Options.td | 5 + lld/COFF/Writer.cpp | 81 +- lld/MinGW/Driver.cpp | 15 + lld/MinGW/Options.td | 4 +- lld/test/COFF/Inputs/loadconfig-arm64ec.s | 4 +- lld/test/COFF/debug-reloc.s | 2 +- lld/test/COFF/lto-imp-prefix.ll | 8 +- lld/test/COFF/pdata-arm64ec.test | 132 + lld/test/COFF/rsds.test | 68 +- lld/test/MinGW/driver.test | 13 + lldb/include/lldb/Core/PluginManager.h | 11 +- .../lldb/Expression/DiagnosticManager.h | 9 + .../include/lldb/Host/netbsd/HostInfoNetBSD.h | 2 +- lldb/source/Core/CoreProperties.td | 2 +- lldb/source/Core/FormatEntity.cpp | 7 +- lldb/source/Core/PluginManager.cpp | 28 +- lldb/source/Host/common/SocketAddress.cpp | 6 +- lldb/source/Host/netbsd/HostInfoNetBSD.cpp | 1 - lldb/source/Host/openbsd/HostInfoOpenBSD.cpp | 14 +- lldb/source/Host/posix/DomainSocket.cpp | 3 +- .../SystemInitializerCommon.cpp | 6 +- .../POSIX-DYLD/DYLDRendezvous.cpp | 1 + .../POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp | 3 +- .../Plugins/Process/Utility/NetBSDSignals.h | 2 +- .../Utility/RegisterContextNetBSD_i386.cpp | 4 +- .../Utility/RegisterContextNetBSD_x86_64.h | 2 +- .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 64 +- .../SymbolFile/DWARF/DWARFASTParserClang.h | 11 - .../SymbolFile/DWARF/SymbolFileDWARF.cpp | 6 +- .../Plugins/SymbolLocator/CMakeLists.txt | 1 + .../SymbolLocator/Debuginfod/CMakeLists.txt | 21 + .../Debuginfod/SymbolLocatorDebuginfod.cpp | 142 + .../Debuginfod/SymbolLocatorDebuginfod.h | 54 + .../SymbolLocatorDebuginfodProperties.td | 7 + lldb/test/API/api/multithreaded/common.h | 3 +- .../TestConstStaticIntegralMember.py | 16 +- .../tools/lldb-server/thread-name/main.cpp | 5 + llvm/docs/GettingStarted.rst | 5 + llvm/docs/GitHub.rst | 9 +- llvm/docs/LangRef.rst | 26 +- llvm/docs/ReleaseNotes.rst | 12 +- .../MyFirstLanguageFrontend/LangImpl08.rst | 7 +- llvm/examples/Kaleidoscope/Chapter8/toy.cpp | 5 +- llvm/include/llvm-c/Core.h | 19 +- .../include/llvm/Analysis/DomConditionCache.h | 56 + llvm/include/llvm/Analysis/SimplifyQuery.h | 6 +- llvm/include/llvm/Analysis/ValueTracking.h | 21 - llvm/include/llvm/Analysis/VectorUtils.h | 30 +- llvm/include/llvm/AsmParser/LLParser.h | 1 + llvm/include/llvm/AsmParser/LLToken.h | 1 + .../llvm/BinaryFormat/ELFRelocs/LoongArch.def | 12 +- llvm/include/llvm/Bitcode/LLVMBitCodes.h | 6 +- llvm/include/llvm/CodeGen/AccelTable.h | 10 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 4 + .../include/llvm/CodeGen/CodeGenPassBuilder.h | 3 +- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 4 + .../llvm/CodeGen/MachinePassRegistry.def | 2 +- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 13 +- llvm/include/llvm/CodeGen/TargetLowering.h | 27 +- llvm/include/llvm/CodeGen/WasmEHPrepare.h | 23 + llvm/include/llvm/Debuginfod/Debuginfod.h | 4 + .../llvm/ExecutionEngine/Orc/MachOPlatform.h | 2 +- .../llvm/Frontend/OpenMP/OMPConstants.h | 10 + .../llvm/Frontend/OpenMP/OMPIRBuilder.h | 28 +- llvm/include/llvm/IR/Constants.h | 23 +- llvm/include/llvm/IR/DerivedTypes.h | 32 - llvm/include/llvm/IR/GlobalObject.h | 1 + llvm/include/llvm/IR/GlobalVariable.h | 27 + llvm/include/llvm/IR/InstrTypes.h | 32 + llvm/include/llvm/IR/IntrinsicInst.h | 12 + llvm/include/llvm/IR/Intrinsics.td | 4 + llvm/include/llvm/IR/IntrinsicsAArch64.td | 31 + llvm/include/llvm/IR/IntrinsicsBPF.td | 39 + llvm/include/llvm/IR/ModuleSummaryIndex.h | 20 +- llvm/include/llvm/IR/PatternMatch.h | 31 + llvm/include/llvm/MC/MCSectionXCOFF.h | 1 + llvm/include/llvm/MC/MCSymbolXCOFF.h | 8 +- llvm/include/llvm/MC/MCXCOFFStreamer.h | 5 +- llvm/include/llvm/Support/Compiler.h | 19 + llvm/include/llvm/Support/Host.h | 18 - .../include/llvm/Target/GlobalISel/Combine.td | 10 +- .../Transforms/InstCombine/InstCombiner.h | 8 +- llvm/include/llvm/XRay/BlockVerifier.h | 1 - llvm/include/module.modulemap | 3 - llvm/lib/Analysis/CMakeLists.txt | 1 + llvm/lib/Analysis/CaptureTracking.cpp | 7 +- llvm/lib/Analysis/DomConditionCache.cpp | 68 + llvm/lib/Analysis/LoopAccessAnalysis.cpp | 9 +- llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | 2 + llvm/lib/Analysis/ScalarEvolution.cpp | 7 +- llvm/lib/Analysis/VFABIDemangling.cpp | 4 +- llvm/lib/Analysis/ValueTracking.cpp | 244 +- llvm/lib/Analysis/VectorUtils.cpp | 3 +- llvm/lib/AsmParser/LLLexer.cpp | 1 + llvm/lib/AsmParser/LLParser.cpp | 64 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 69 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 106 +- llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp | 38 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 15 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 17 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 95 +- .../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 94 + .../CodeGen/GlobalISel/LegalizerHelper.cpp | 10 + llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp | 6 +- llvm/lib/CodeGen/LiveRangeEdit.cpp | 2 +- llvm/lib/CodeGen/MachineScheduler.cpp | 14 +- .../SelectionDAG/FunctionLoweringInfo.cpp | 11 +- .../SelectionDAG/LegalizeIntegerTypes.cpp | 27 +- .../SelectionDAG/SelectionDAGBuilder.cpp | 25 - llvm/lib/CodeGen/TargetInstrInfo.cpp | 2 +- llvm/lib/CodeGen/TargetSchedule.cpp | 2 +- llvm/lib/CodeGen/WasmEHPrepare.cpp | 47 +- llvm/lib/Debuginfod/Debuginfod.cpp | 33 +- .../ExecutionEngine/Orc/ExecutionUtils.cpp | 4 +- .../lib/ExecutionEngine/Orc/MachOPlatform.cpp | 60 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 246 +- llvm/lib/IR/AsmWriter.cpp | 25 + llvm/lib/IR/BasicBlock.cpp | 10 +- llvm/lib/IR/Constants.cpp | 26 + llvm/lib/IR/Core.cpp | 10 + llvm/lib/IR/Globals.cpp | 11 + llvm/lib/IR/Instruction.cpp | 9 +- llvm/lib/IR/Metadata.cpp | 7 +- llvm/lib/MC/MCObjectFileInfo.cpp | 8 +- llvm/lib/MC/MCStreamer.cpp | 5 +- llvm/lib/MC/MCXCOFFStreamer.cpp | 7 + llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/lib/Passes/PassRegistry.def | 1 + .../Target/AArch64/AArch64FrameLowering.cpp | 30 +- .../Target/AArch64/AArch64ISelDAGToDAG.cpp | 68 +- .../Target/AArch64/AArch64ISelLowering.cpp | 19 +- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 3 + llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 5 +- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 2 + .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 4 +- llvm/lib/Target/AArch64/SMEInstrFormats.td | 46 +- llvm/lib/Target/AMDGPU/AMDGPU.td | 2 + llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 11 + .../lib/Target/AMDGPU/AMDGPUMachineFunction.h | 5 + .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 5 +- .../Disassembler/AMDGPUDisassembler.cpp | 14 +- llvm/lib/Target/AMDGPU/SIDefines.h | 24 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 44 +- llvm/lib/Target/AMDGPU/SIISelLowering.h | 3 +- .../lib/Target/AMDGPU/SIInsertHardClauses.cpp | 5 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 + llvm/lib/Target/AMDGPU/SIInstrInfo.h | 2 + .../Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 8 +- llvm/lib/Target/AMDGPU/SMInstructions.td | 57 + llvm/lib/Target/AMDGPU/SOPInstructions.td | 717 +- .../Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp | 42 +- .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 10 + llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 +- llvm/lib/Target/ARM/Thumb1FrameLowering.cpp | 1 - llvm/lib/Target/BPF/BPF.h | 19 + .../Target/BPF/BPFAbstractMemberAccess.cpp | 77 +- llvm/lib/Target/BPF/BPFCORE.h | 4 + llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp | 56 + .../Target/BPF/BPFPreserveStaticOffset.cpp | 680 ++ llvm/lib/Target/BPF/BPFTargetMachine.cpp | 11 + llvm/lib/Target/BPF/CMakeLists.txt | 1 + .../LoongArch/LoongArchISelLowering.cpp | 5 + .../LoongArch/LoongArchLASXInstrInfo.td | 8 + .../Target/LoongArch/LoongArchLSXInstrInfo.td | 8 + llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 53 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 5 +- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 2 + .../Target/RISCV/GISel/RISCVCallLowering.cpp | 89 +- .../RISCV/GISel/RISCVInstructionSelector.cpp | 22 + .../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 11 +- llvm/lib/Target/RISCV/RISCVGISel.td | 10 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 83 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 3 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 8 +- llvm/lib/Target/RISCV/RISCVInstrInfo.h | 2 + llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 8 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 40 +- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 482 +- llvm/lib/Target/RISCV/RISCVScheduleV.td | 16 +- llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp | 3 +- .../Target/SystemZ/SystemZISelLowering.cpp | 6 +- llvm/lib/Target/TargetMachine.cpp | 48 +- llvm/lib/Target/X86/X86CallingConv.td | 3 + llvm/lib/Target/X86/X86ISelLowering.cpp | 30 +- llvm/lib/Target/X86/X86ISelLowering.h | 3 - llvm/lib/Target/X86/X86Instr3DNow.td | 10 - llvm/lib/Target/X86/X86InstrAVX512.td | 283 - llvm/lib/Target/X86/X86InstrArithmetic.td | 24 - llvm/lib/Target/X86/X86InstrCompiler.td | 87 - llvm/lib/Target/X86/X86InstrFPStack.td | 123 +- llvm/lib/Target/X86/X86InstrFormats.td | 706 -- llvm/lib/Target/X86/X86InstrFragments.td | 841 +++ llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 117 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 10 +- llvm/lib/Target/X86/X86InstrInfo.td | 1400 +--- llvm/lib/Target/X86/X86InstrMisc.td | 20 - llvm/lib/Target/X86/X86InstrOperands.td | 497 ++ llvm/lib/Target/X86/X86InstrPredicates.td | 207 + llvm/lib/Target/X86/X86InstrSSE.td | 5 - llvm/lib/Target/X86/X86InstrUtils.td | 1014 +++ llvm/lib/Target/X86/X86InstrVMX.td | 10 + .../X86/X86LoadValueInjectionRetHardening.cpp | 1 - llvm/lib/Target/X86/X86RegisterInfo.cpp | 5 +- llvm/lib/Target/XCore/XCoreISelLowering.cpp | 95 +- llvm/lib/Target/XCore/XCoreISelLowering.h | 17 +- llvm/lib/Transforms/IPO/LowerTypeTests.cpp | 21 +- .../lib/Transforms/IPO/WholeProgramDevirt.cpp | 3 +- .../InstCombine/InstCombineAddSub.cpp | 10 +- .../InstCombine/InstCombineAndOrXor.cpp | 7 +- .../InstCombine/InstCombineCompares.cpp | 19 +- .../InstCombine/InstCombineInternal.h | 5 +- .../InstCombine/InstCombineMulDivRem.cpp | 5 +- .../InstCombine/InstCombineNegator.cpp | 11 +- .../InstCombineSimplifyDemanded.cpp | 2 + .../InstCombine/InstructionCombining.cpp | 1 + .../Transforms/Scalar/CallSiteSplitting.cpp | 9 +- .../Scalar/ConstraintElimination.cpp | 4 +- llvm/lib/Transforms/Scalar/Reassociate.cpp | 9 +- .../Scalar/TailRecursionElimination.cpp | 14 +- llvm/lib/Transforms/Utils/Local.cpp | 11 +- .../Transforms/Utils/LoopRotationUtils.cpp | 40 +- llvm/lib/Transforms/Utils/ModuleUtils.cpp | 3 +- .../Transforms/Vectorize/LoopVectorize.cpp | 4 +- .../Transforms/Vectorize/SLPVectorizer.cpp | 15 +- llvm/lib/Transforms/Vectorize/VPlan.h | 43 +- .../lib/Transforms/Vectorize/VPlanRecipes.cpp | 8 + .../Transforms/Vectorize/VPlanTransforms.cpp | 2 +- llvm/lib/XRay/BlockVerifier.cpp | 2 + .../CostModel/X86/interleaved-load-half.ll | 14 +- .../X86/masked-interleaved-load-i16.ll | 4 +- .../X86/masked-interleaved-store-i16.ll | 4 +- .../Analysis/DependenceAnalysis/ExactRDIV.ll | 2 +- .../Analysis/DependenceAnalysis/ExactSIV.ll | 4 +- llvm/test/Analysis/DependenceAnalysis/GCD.ll | 12 +- .../forward-negative-step.ll | 13 +- .../LoopAccessAnalysis/print-order.ll | 65 + .../stride-access-dependence.ll | 10 +- .../Analysis/ScalarEvolution/add-like-or.ll | 42 +- .../ScalarEvolution/nsw-offset-assume.ll | 4 +- .../Analysis/ScalarEvolution/nsw-offset.ll | 4 +- .../test/Analysis/ScalarEvolution/sext-mul.ll | 8 +- llvm/test/Analysis/StackSafetyAnalysis/ipa.ll | 2 +- .../Assembler/globalvariable-attributes.ll | 10 + llvm/test/Assembler/index-value-order.ll | 25 + llvm/test/Assembler/thinlto-summary.ll | 10 +- llvm/test/Bindings/llvm-c/echo.ll | 3 +- llvm/test/Bitcode/thinlto-alias.ll | 6 +- llvm/test/Bitcode/thinlto-alias2.ll | 4 +- llvm/test/Bitcode/thinlto-asm-noimport.ll | 2 +- ...thinlto-function-summary-callgraph-cast.ll | 6 +- ...allgraph-partial-sample-profile-summary.ll | 18 +- ...ction-summary-callgraph-profile-summary.ll | 14 +- ...ummary-callgraph-sample-profile-summary.ll | 18 +- .../thinlto-function-summary-callgraph.ll | 6 +- .../thinlto-function-summary-functionattrs.ll | 8 +- .../thinlto-function-summary-originalnames.ll | 2 +- .../thinlto-function-summary-paramaccess.ll | 38 +- .../thinlto-function-summary-refgraph.ll | 22 +- llvm/test/Bitcode/thinlto-function-summary.ll | 8 +- .../Bitcode/thinlto-summary-linkage-types.ll | 32 +- llvm/test/Bitcode/thinlto-summary-section.ll | 4 +- .../CodeGen/AArch64/aarch64-sched-store.ll | 6 +- llvm/test/CodeGen/AArch64/arm64-addrmode.ll | 86 + .../AArch64/arm64-indexed-vector-ldst.ll | 58 +- .../AArch64/clear-dead-implicit-def-impdef.ll | 125 + .../clear-dead-implicit-def-impdef.mir | 119 + ...plicit-def-remat-requires-impdef-check.mir | 92 + .../AArch64/sme2-intrinsics-luti2-lane-x2.ll | 65 + .../AArch64/sme2-intrinsics-luti2-lane-x4.ll | 66 + .../AArch64/sme2-intrinsics-luti2-lane.ll | 65 + .../AArch64/sme2-intrinsics-luti4-lane-x2.ll | 65 + .../AArch64/sme2-intrinsics-luti4-lane-x4.ll | 55 + .../AArch64/sme2-intrinsics-luti4-lane.ll | 65 + ...re-swift-async-context-clobber-live-reg.ll | 456 +- .../AMDGPU/GlobalISel/combine-fma-add-mul.ll | 80 +- .../GlobalISel/extractelement-stack-lower.ll | 515 +- .../AMDGPU/GlobalISel/extractelement.i128.ll | 899 +-- .../AMDGPU/GlobalISel/extractelement.i16.ll | 1498 ++-- .../AMDGPU/GlobalISel/extractelement.i8.ll | 1956 +++--- .../AMDGPU/GlobalISel/extractelement.ll | 50 +- ...nfloop-subrange-spill-inspect-subrange.mir | 143 + .../AMDGPU/min-waves-per-eu-not-respected.ll | 16 + .../AMDGPU/promote-constOffset-to-imm.ll | 20 +- .../CodeGen/AMDGPU/regpressure_printer.mir | 115 +- .../CodeGen/AMDGPU/scratch-pointer-sink.ll | 46 + llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll | 6 +- llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll | 6 +- llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll | 6 +- llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll | 6 +- llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll | 6 +- .../test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll | 6 +- .../test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll | 6 +- .../ARM/ParallelDSP/unroll-n-jam-smlad.ll | 30 +- llvm/test/CodeGen/ARM/aapcs-hfa-code.ll | 183 +- llvm/test/CodeGen/ARM/dsp-loop-indexing.ll | 8 +- llvm/test/CodeGen/ARM/fpclamptosat.ll | 4 +- llvm/test/CodeGen/ARM/loop-indexing.ll | 56 +- llvm/test/CodeGen/ARM/shifter_operand.ll | 4 +- .../BPF/preserve-static-offset/load-align.ll | 66 + .../preserve-static-offset/load-arr-pai.ll | 93 + .../BPF/preserve-static-offset/load-atomic.ll | 66 + .../preserve-static-offset/load-chain-2.ll | 82 + .../preserve-static-offset/load-chain-oob.ll | 73 + .../load-chain-u8-oob.ll | 74 + .../load-chain-u8-type-mismatch.ll | 73 + .../preserve-static-offset/load-chain-u8.ll | 71 + .../BPF/preserve-static-offset/load-chain.ll | 68 + .../BPF/preserve-static-offset/load-inline.ll | 85 + .../preserve-static-offset/load-non-const.ll | 75 + .../preserve-static-offset/load-ptr-pai.ll | 114 + .../BPF/preserve-static-offset/load-simple.ll | 71 + .../preserve-static-offset/load-struct-pai.ll | 105 + .../preserve-static-offset/load-undo-align.ll | 67 + .../load-undo-chain-oob.ll | 74 + .../load-undo-chain-u8.ll | 68 + .../preserve-static-offset/load-undo-chain.ll | 73 + .../load-undo-simple.ll | 65 + .../load-undo-volatile.ll | 64 + .../preserve-static-offset/load-union-pai.ll | 110 + .../load-unroll-inline.ll | 108 + .../BPF/preserve-static-offset/load-unroll.ll | 95 + .../preserve-static-offset/load-volatile.ll | 62 + .../BPF/preserve-static-offset/load-zero.ll | 57 + .../BPF/preserve-static-offset/store-align.ll | 59 + .../preserve-static-offset/store-atomic.ll | 60 + .../preserve-static-offset/store-chain-2.ll | 77 + .../preserve-static-offset/store-chain-oob.ll | 67 + .../store-chain-u8-oob.ll | 67 + .../preserve-static-offset/store-chain-u8.ll | 68 + .../BPF/preserve-static-offset/store-chain.ll | 64 + .../BPF/preserve-static-offset/store-pai.ll | 136 + .../preserve-static-offset/store-simple.ll | 60 + .../store-undo-align.ll | 62 + .../store-undo-chain-oob.ll | 67 + .../store-undo-chain-u8.ll | 62 + .../store-undo-chain.ll | 68 + .../store-undo-simple.ll | 61 + .../store-undo-volatile.ll | 61 + .../store-unroll-inline.ll | 104 + .../preserve-static-offset/store-volatile.ll | 56 + .../BPF/preserve-static-offset/store-zero.ll | 51 + .../CodeGen/Hexagon/autohvx/interleave.ll | 2 +- llvm/test/CodeGen/LoongArch/lasx/vselect.ll | 85 + llvm/test/CodeGen/LoongArch/lsx/vselect.ll | 85 + llvm/test/CodeGen/NVPTX/i8x4-instructions.ll | 7 +- llvm/test/CodeGen/NVPTX/vector-stores.ll | 16 - llvm/test/CodeGen/PowerPC/aix-alias.ll | 4 +- ...ix-emit-tracebacktable-clobber-register.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-extern-weak.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-extern.ll | 4 +- llvm/test/CodeGen/PowerPC/aix-func-align.ll | 4 +- .../CodeGen/PowerPC/aix-personality-alias.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-weak.ll | 6 +- llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll | 2 +- .../CodeGen/PowerPC/aix-xcoff-funcsect.ll | 2 + .../PowerPC/aix-xcoff-symbol-rename.ll | 6 +- ...materializable-instruction-machine-licm.ll | 6 +- llvm/test/CodeGen/PowerPC/test_func_desc.ll | 6 +- .../instruction-select/rotate-rv32.mir | 94 + .../instruction-select/rotate-rv64.mir | 206 + .../irtranslator/lower-args-vararg.ll | 252 +- .../legalizer/legalize-rotate-rv32.mir | 82 +- .../legalizer/legalize-rotate-rv64.mir | 180 +- ...calling-conv-ilp32-ilp32f-ilp32d-common.ll | 12 +- .../calling-conv-lp64-lp64f-lp64d-common.ll | 12 +- llvm/test/CodeGen/RISCV/push-pop-popret.ll | 56 +- .../RISCV/reduce-unnecessary-extension.ll | 119 + .../CodeGen/RISCV/riscv-codegenprepare-asm.ll | 2 +- .../CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll | 116 + .../CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll | 116 + llvm/test/CodeGen/RISCV/vararg.ll | 162 +- .../CodeGen/SystemZ/atomicrmw-ops-i128.ll | 496 +- .../test/CodeGen/SystemZ/atomicrmw-xchg-07.ll | 37 +- llvm/test/CodeGen/SystemZ/vec-load-element.ll | 18 +- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 6 +- .../LowOverheadLoops/mve-float-loops.ll | 18 +- .../LowOverheadLoops/mve-tail-data-types.ll | 18 +- .../test/CodeGen/Thumb2/mve-blockplacement.ll | 6 +- .../Thumb2/mve-tailpred-loopinvariant.ll | 30 +- llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll | 6 +- .../WebAssembly/unrolled-mem-indices.ll | 12 +- .../{wasmehprepare.ll => wasm-eh-prepare.ll} | 6 +- llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll | 2 +- .../CodeGen/X86/MergeConsecutiveStores.ll | 2 +- llvm/test/CodeGen/X86/atomic-unordered.ll | 714 +- .../CodeGen/X86/avx512-broadcast-unfold.ll | 1359 ++-- llvm/test/CodeGen/X86/avx512vnni-combine.ll | 8 +- llvm/test/CodeGen/X86/avxvnni-combine.ll | 16 +- .../CodeGen/X86/code-model-elf-sections.ll | 32 + llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll | 164 +- .../test/CodeGen/X86/loop-strength-reduce4.ll | 6 +- llvm/test/CodeGen/X86/lsr-addrecloops.ll | 28 +- llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll | 4 +- llvm/test/CodeGen/X86/merge_store.ll | 6 +- llvm/test/CodeGen/X86/optimize-max-0.ll | 4 +- .../test/CodeGen/X86/preserve_mostcc64_win.ll | 91 + llvm/test/CodeGen/X86/slow-unaligned-mem.ll | 165 +- llvm/test/CodeGen/X86/swifterror.ll | 10 +- llvm/test/CodeGen/X86/unused_stackslots.ll | 16 +- llvm/test/CodeGen/X86/vec_zero_cse.ll | 54 +- llvm/test/CodeGen/X86/zero-remat.ll | 57 +- llvm/test/CodeGen/XCore/atomic.ll | 72 +- .../DebugInfo/Inputs/dwarfdump-test3-decl.h | 0 llvm/test/DebugInfo/Inputs/dwarfdump-test3.cc | 0 llvm/test/DebugInfo/X86/debug-names-types.ll | 100 +- llvm/test/DebugInfo/XCOFF/empty.ll | 10 +- llvm/test/DebugInfo/XCOFF/explicit-section.ll | 5 +- .../test/DebugInfo/XCOFF/function-sections.ll | 3 +- .../JITLink/AArch32/ELF_thumbv7_printf.s | 4 +- .../JITLink/Generic/Inputs/main-ret-0.ll | 4 + .../error-object-passed-as-archive.test | 6 + llvm/test/MC/AMDGPU/gfx12_asm_smem.s | 35 + llvm/test/MC/AMDGPU/gfx12_asm_sop1.s | 4216 ++++++++++++ llvm/test/MC/AMDGPU/gfx12_asm_sop2.s | 6097 +++++++++++++++++ llvm/test/MC/AMDGPU/gfx12_asm_sop2_alias.s | 223 + llvm/test/MC/AMDGPU/gfx12_asm_sopc.s | 2161 ++++++ llvm/test/MC/AMDGPU/gfx12_asm_sopk.s | 244 + llvm/test/MC/AMDGPU/gfx12_asm_sopk_alias.s | 4 + llvm/test/MC/AMDGPU/gfx12_asm_sopp.s | 346 + llvm/test/MC/AMDGPU/gfx12_err.s | 5 + llvm/test/MC/AMDGPU/gfx12_unsupported.s | 11 + .../Disassembler/AMDGPU/gfx12_dasm_smem.txt | 31 + .../Disassembler/AMDGPU/gfx12_dasm_sop1.txt | 3649 ++++++++++ .../Disassembler/AMDGPU/gfx12_dasm_sop2.txt | 5960 ++++++++++++++++ .../Disassembler/AMDGPU/gfx12_dasm_sopc.txt | 2161 ++++++ .../Disassembler/AMDGPU/gfx12_dasm_sopk.txt | 257 + .../Disassembler/AMDGPU/gfx12_dasm_sopp.txt | 268 + llvm/test/MC/Disassembler/X86/apx/invept.txt | 6 + llvm/test/MC/Disassembler/X86/apx/invvpid.txt | 6 + llvm/test/MC/X86/apx/invept-att.s | 8 + llvm/test/MC/X86/apx/invept-intel.s | 5 + llvm/test/MC/X86/apx/invvpid-att.s | 9 + llvm/test/MC/X86/apx/invvpid-intel.s | 5 + llvm/test/ThinLTO/X86/deadstrip.ll | 22 +- llvm/test/ThinLTO/X86/distributed_indexes.ll | 8 +- .../Attributor/nofpclass-implied-by-fcmp.ll | 446 +- .../AArch64/large-offset-gep.ll | 57 +- .../debug-info-on-skipped-selects.ll | 68 + .../Transforms/ConstraintElimination/or.ll | 145 +- llvm/test/Transforms/GVN/captured-before.ll | 18 + .../GlobalOpt/globalvar-code-model.ll | 11 + .../Transforms/IRCE/stride_more_than_1.ll | 6 +- .../IndVarSimplify/ashr-tripcount.ll | 12 +- .../IndVarSimplify/lcssa-preservation.ll | 10 +- .../IndVarSimplify/no-iv-rewrite.ll | 4 +- ...date-scev-when-replacing-congruent-phis.ll | 8 +- .../test/Transforms/IndVarSimplify/pr64891.ll | 2 +- .../InstCombine/2007-10-31-RangeCrash.ll | 7 +- .../2009-02-20-InstCombine-SROA.ll | 4 +- llvm/test/Transforms/InstCombine/add.ll | 60 +- .../test/Transforms/InstCombine/and-or-not.ll | 2 +- llvm/test/Transforms/InstCombine/cast_phi.ll | 2 +- .../test/Transforms/InstCombine/icmp-binop.ll | 3 +- .../Transforms/InstCombine/icmp-mul-zext.ll | 3 +- .../Transforms/InstCombine/icmp-ne-pow2.ll | 12 +- .../Transforms/InstCombine/icmp-of-or-x.ll | 8 +- llvm/test/Transforms/InstCombine/idioms.ll | 11 +- .../Transforms/InstCombine/known-non-zero.ll | 10 +- .../Transforms/InstCombine/logical-select.ll | 6 +- .../InstCombine/masked-merge-add.ll | 22 +- .../Transforms/InstCombine/masked-merge-or.ll | 22 +- .../InstCombine/masked-merge-xor.ll | 22 +- .../Transforms/InstCombine/minmax-of-xor-x.ll | 5 +- llvm/test/Transforms/InstCombine/mul.ll | 22 + llvm/test/Transforms/InstCombine/pr53357.ll | 14 +- llvm/test/Transforms/InstCombine/shift.ll | 8 +- .../InstCombine/sink_instruction.ll | 6 +- .../sub-of-negatible-inseltpoison.ll | 6 +- .../InstCombine/sub-of-negatible.ll | 17 +- .../Transforms/InstCombine/udiv-simplify.ll | 4 +- .../assume-fcmp-constant-implies-class.ll | 270 +- .../AMDGPU/complex-index.ll | 2 +- .../AMDGPU/extended-index.ll | 6 +- .../Transforms/LoopIdiom/unroll-custom-dl.ll | 8 +- llvm/test/Transforms/LoopIdiom/unroll.ll | 8 +- .../Transforms/LoopInterchange/pr57148.ll | 4 +- .../Transforms/LoopReroll/basic32iters.ll | 62 +- .../Transforms/LoopReroll/indvar_with_ext.ll | 6 +- llvm/test/Transforms/LoopReroll/reduction.ll | 18 +- .../Transforms/LoopReroll/reroll_with_dbg.ll | 6 +- .../LoopRotate/delete-dbg-values.ll | 63 + .../LoopStrengthReduce/ARM/complexity.ll | 6 +- .../LoopStrengthReduce/ARM/ivchain-ARM.ll | 6 +- .../LoopStrengthReduce/X86/ivchain-X86.ll | 8 +- .../X86/missing-phi-operand-update.ll | 10 +- .../LoopUnroll/X86/high-cost-expansion.ll | 4 +- .../AArch64/scalable-strict-fadd.ll | 10 +- .../LoopVectorize/AArch64/strict-fadd.ll | 2 +- .../AArch64/sve-interleaved-accesses.ll | 18 +- .../sve-interleaved-masked-accesses.ll | 6 +- .../AArch64/sve-tail-folding-option.ll | 2 +- .../AArch64/sve-vector-reverse.ll | 4 +- .../AArch64/vector-call-linear-args.ll | 253 + .../AArch64/vector-reverse-mask4.ll | 2 +- .../LoopVectorize/ARM/mve-reductions.ll | 42 +- .../X86/drop-poison-generating-flags.ll | 78 + .../LoopVectorize/X86/interleaving.ll | 2 +- .../Transforms/LoopVectorize/X86/pr47437.ll | 18 +- .../LoopVectorize/X86/scatter_crash.ll | 8 +- .../LoopVectorize/X86/small-size.ll | 6 +- .../x86-interleaved-accesses-masked-group.ll | 48 +- ...86-interleaved-store-accesses-with-gaps.ll | 12 +- .../LoopVectorize/float-induction.ll | 80 +- .../LoopVectorize/if-conversion-nest.ll | 6 +- .../Transforms/LoopVectorize/induction.ll | 6 +- .../interleaved-accesses-masked-group.ll | 6 +- .../LoopVectorize/interleaved-accesses.ll | 6 +- llvm/test/Transforms/LoopVectorize/pr39099.ll | 2 +- .../LoopVectorize/preserve-or-disjoint.ll | 71 + .../reduction-with-invariant-store.ll | 10 +- .../Transforms/LoopVectorize/reduction.ll | 44 +- .../Transforms/LoopVectorize/runtime-check.ll | 4 +- ...able-loop-unpredicated-body-scalar-tail.ll | 4 +- .../LoopVectorize/unroll_nonlatch.ll | 38 +- .../LoopVectorize/vplan-printing.ll | 90 + .../LowerTypeTests/aarch64-jumptable.ll | 35 +- .../cfi-nounwind-direct-call.ll | 160 + .../LowerTypeTests/cfi-unwind-direct-call.ll | 228 + .../LowerTypeTests/function-arm-thumb.ll | 4 +- .../LowerTypeTests/function-thumb-bti.ll | 4 +- .../Transforms/LowerTypeTests/function.ll | 16 +- .../LowerTypeTests/x86-jumptable.ll | 2 +- llvm/test/Transforms/PGOProfile/chr.ll | 6 +- .../PhaseOrdering/X86/simplifycfg-late.ll | 2 +- .../test/Transforms/PhaseOrdering/X86/vdiv.ll | 2 +- .../loop-rotation-vs-common-code-hoisting.ll | 2 +- .../Transforms/Reassociate/add-like-or.ll | 12 + .../SLPVectorizer/AArch64/loadorder.ll | 4 +- .../Transforms/SLPVectorizer/NVPTX/v2f16.ll | 12 +- .../SLPVectorizer/X86/compare-reduce.ll | 10 +- .../SLPVectorizer/X86/consecutive-access.ll | 76 +- .../X86/delayed-gather-emission.ll | 7 +- ...gathered-delayed-nodes-with-reused-user.ll | 45 + .../Transforms/SLPVectorizer/X86/hoist.ll | 10 +- .../SLPVectorizer/X86/horizontal.ll | 150 +- .../SLPVectorizer/X86/in-tree-user.ll | 10 +- .../SLPVectorizer/X86/loopinvariant.ll | 26 +- .../Transforms/SLPVectorizer/X86/reduction.ll | 20 +- .../SLPVectorizer/X86/reduction2.ll | 2 +- .../SLPVectorizer/X86/remark_horcost.ll | 34 +- .../SLPVectorizer/X86/remark_not_all_parts.ll | 30 +- .../SLPVectorizer/X86/scheduling.ll | 34 +- .../SLPVectorizer/X86/simple-loop.ll | 52 +- .../SLPVectorizer/X86/slp-throttle.ll | 2 +- .../SimpleLoopUnswitch/2007-08-01-LCSSA.ll | 7 +- .../SimplifyCFG/merge-cond-stores.ll | 5 +- .../TailCallElim/accum_recursion.ll | 40 +- .../TailCallElim/tre-minmax-intrinsic.ll | 305 + .../tools/llvm-mca/RISCV/SiFive7/div-fdiv.s | 65 + .../llvm-mca/RISCV/SiFive7/gpr-bypass-c.s | 4 +- .../tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s | 4 +- .../tools/llvm-mca/RISCV/SiFive7/reductions.s | 422 +- .../llvm-mca/RISCV/SiFive7/strided-load-x0.s | 106 +- .../RISCV/SiFive7/vector-integer-arithmetic.s | 1498 ++-- .../RISCV/different-lmul-instruments.s | 16 +- .../RISCV/different-sew-instruments.s | 18 +- llvm/test/tools/llvm-mca/RISCV/disable-im.s | 40 +- .../llvm-mca/RISCV/fractional-lmul-data.s | 18 +- .../llvm-mca/RISCV/lmul-instrument-at-start.s | 12 +- .../RISCV/lmul-instrument-in-middle.s | 26 +- .../RISCV/lmul-instrument-in-region.s | 12 +- .../RISCV/lmul-instrument-straddles-region.s | 12 +- .../RISCV/multiple-same-lmul-instruments.s | 52 +- .../RISCV/multiple-same-sew-instruments.s | 30 +- .../llvm-mca/RISCV/needs-sew-but-only-lmul.s | 18 +- .../llvm-mca/RISCV/no-vsetvli-to-start.s | 26 +- .../llvm-mca/RISCV/sew-instrument-at-start.s | 12 +- .../llvm-mca/RISCV/sew-instrument-in-middle.s | 18 +- .../llvm-mca/RISCV/sew-instrument-in-region.s | 12 +- .../RISCV/sew-instrument-straddles-region.s | 12 +- llvm/test/tools/llvm-mca/RISCV/vle-vse.s | 814 +-- .../llvm-mca/RISCV/vsetivli-lmul-instrument.s | 16 +- .../RISCV/vsetivli-lmul-sew-instrument.s | 18 +- .../llvm-mca/RISCV/vsetvli-lmul-instrument.s | 16 +- .../RISCV/vsetvli-lmul-sew-instrument.s | 18 +- .../ELF/reloc-types-loongarch64.test | 6 +- llvm/tools/lli/lli.cpp | 2 +- llvm/tools/llvm-c-test/echo.cpp | 2 + llvm/tools/llvm-exegesis/lib/Analysis.cpp | 1 - llvm/tools/llvm-exegesis/lib/Analysis.h | 1 - .../llvm-exegesis/lib/BenchmarkRunner.cpp | 2 - .../lib/SchedClassResolution.cpp | 2 - .../llvm-exegesis/lib/SnippetGenerator.cpp | 1 - .../llvm-exegesis/lib/SnippetRepetitor.cpp | 2 - llvm/tools/llvm-jitlink/llvm-jitlink.cpp | 221 +- llvm/tools/llvm-jitlink/llvm-jitlink.h | 2 + llvm/tools/llvm-reduce/deltas/Delta.cpp | 1 - llvm/tools/llvm-reduce/deltas/Delta.h | 1 - .../llvm-reduce/deltas/ReduceDIMetadata.cpp | 2 - .../vfabi-demangler-fuzzer.cpp | 9 +- llvm/unittests/Analysis/ValueTrackingTest.cpp | 6 +- .../Analysis/VectorFunctionABITest.cpp | 3 +- llvm/unittests/Analysis/VectorUtilsTest.cpp | 6 +- .../Frontend/OpenMPIRBuilderTest.cpp | 71 + llvm/unittests/IR/BasicBlockDbgInfoTest.cpp | 125 + llvm/unittests/IR/DebugInfoTest.cpp | 65 + llvm/unittests/Object/ELFTest.cpp | 6 +- .../Target/RISCV/RISCVInstrInfoTest.cpp | 9 +- .../Mips/SnippetGeneratorTest.cpp | 2 - .../PowerPC/SnippetGeneratorTest.cpp | 2 - llvm/utils/UpdateTestChecks/common.py | 2 +- llvm/utils/git/github-automation.py | 39 + .../clang-tidy/modernize/BUILD.gn | 1 + .../gn/secondary/llvm/lib/Analysis/BUILD.gn | 1 + .../gn/secondary/llvm/lib/Target/BPF/BUILD.gn | 1 + llvm/utils/gn/secondary/llvm/test/BUILD.gn | 1 + mlir/benchmark/python/common.py | 9 +- mlir/docs/Dialects/ArmSME.md | 28 +- .../include/mlir/Dialect/Arith/IR/ArithOps.td | 18 +- .../mlir/Dialect/LLVMIR/LLVMAttrDefs.td | 73 + mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td | 20 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 4 +- mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td | 16 + .../Linalg/TransformOps/LinalgTransformOps.td | 4 +- .../Dialect/Linalg/Transforms/Transforms.h | 3 +- .../include/mlir/Dialect/Shape/IR/ShapeOps.td | 1 - .../mlir/Dialect/SparseTensor/IR/Enums.h | 6 +- .../Transform/IR/TransformInterfaces.h | 33 +- .../mlir/Dialect/Utils/StaticValueUtils.h | 30 +- mlir/include/mlir/Target/LLVMIR/Dialect/All.h | 3 + .../Dialect/SPIRV/SPIRVToLLVMIRTranslation.h | 31 + .../Conversion/ArithToLLVM/ArithToLLVM.cpp | 7 +- .../Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp | 81 +- .../GPUToNVVM/LowerGpuOpsToNVVMOps.cpp | 2 + .../GPUToROCDL/LowerGpuOpsToROCDLOps.cpp | 2 + .../Conversion/TosaToLinalg/TosaToLinalg.cpp | 23 +- .../VectorToArmSME/VectorToArmSME.cpp | 117 +- .../Conversion/VectorToSCF/VectorToSCF.cpp | 14 +- .../Bufferization/IR/BufferizationOps.cpp | 6 +- .../BufferDeallocationSimplification.cpp | 55 +- mlir/lib/Dialect/Complex/IR/ComplexOps.cpp | 31 +- mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp | 65 + mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 16 +- .../TransformOps/LinalgTransformOps.cpp | 51 +- .../Linalg/Transforms/Vectorization.cpp | 77 +- mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp | 17 +- mlir/lib/Dialect/Mesh/IR/CMakeLists.txt | 1 + mlir/lib/Dialect/SCF/IR/SCF.cpp | 2 + mlir/lib/Dialect/Shape/IR/Shape.cpp | 34 +- .../SparseTensor/Transforms/CodegenEnv.cpp | 5 +- .../SparseTensor/Transforms/CodegenEnv.h | 11 +- .../SparseTensor/Transforms/LoopEmitter.h | 43 +- .../Transforms/Sparsification.cpp | 389 +- mlir/lib/Dialect/Tensor/IR/TensorOps.cpp | 17 +- mlir/lib/Dialect/Tosa/IR/TosaOps.cpp | 12 +- .../Transform/IR/TransformInterfaces.cpp | 104 +- mlir/lib/Dialect/Utils/StaticValueUtils.cpp | 27 +- mlir/lib/Dialect/Vector/IR/VectorOps.cpp | 47 +- .../Transforms/VectorTransferOpTransforms.cpp | 79 +- mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp | 5 + mlir/lib/IR/Verifier.cpp | 56 +- mlir/lib/Target/LLVMIR/CMakeLists.txt | 1 + mlir/lib/Target/LLVMIR/DebugImporter.cpp | 9 +- mlir/lib/Target/LLVMIR/DebugTranslation.cpp | 9 +- mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt | 1 + .../LLVMIR/Dialect/GPU/SelectObjectAttr.cpp | 41 +- .../LLVMIR/Dialect/SPIRV/CMakeLists.txt | 13 + .../SPIRV/SPIRVToLLVMIRTranslation.cpp | 31 + mlir/lib/Target/LLVMIR/ModuleImport.cpp | 18 + mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 9 + mlir/python/mlir/_mlir_libs/__init__.py | 1 + mlir/python/mlir/dialects/affine.py | 138 + mlir/test/CMakeLists.txt | 4 + .../Conversion/ArithToLLVM/arith-to-llvm.mlir | 3 + .../ArmSMEToSCF/arm-sme-to-scf.mlir | 19 +- .../GPUCommon/lower-memory-space-attrs.mlir | 37 + .../Conversion/NVVMToLLVM/nvvm-to-llvm.mlir | 9 + .../TosaToLinalg/tosa-to-linalg-resize.mlir | 30 +- mlir/test/Dialect/Arith/ops.mlir | 2 + .../test/Dialect/ArmSME/arith-ops-to-sme.mlir | 14 +- .../Dialect/ArmSME/vector-ops-to-sme.mlir | 7 +- mlir/test/Dialect/Complex/invalid.mlir | 2 +- mlir/test/Dialect/LLVMIR/func.mlir | 6 + mlir/test/Dialect/LLVMIR/roundtrip.mlir | 4 + mlir/test/Dialect/Linalg/transform-ops.mlir | 10 + .../Dialect/Linalg/transform-patterns.mlir | 6 +- .../Linalg/vectorize-convolution-flatten.mlir | 309 + mlir/test/Dialect/MemRef/canonicalize.mlir | 12 + mlir/test/Dialect/Shape/canonicalize.mlir | 12 + mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir | 11 + .../Transform/test-pattern-application.mlir | 30 +- mlir/test/Dialect/Vector/canonicalize.mlir | 12 - .../Vector/vector-transfer-flatten.mlir | 58 + .../GPU/SYCL/gpu-addf32-to-spirv.mlir | 56 + .../GPU/SYCL/gpu-addi64-to-spirv.mlir | 54 + .../GPU/SYCL/gpu-reluf32-to-spirv.mlir | 79 + mlir/test/Integration/GPU/SYCL/lit.local.cfg | 2 + mlir/test/Target/LLVMIR/Import/debug-info.ll | 6 +- .../Target/LLVMIR/Import/frame-pointer.ll | 8 + .../Target/LLVMIR/Import/target-features.ll | 9 + mlir/test/Target/LLVMIR/frame-pointer.mlir | 8 + mlir/test/Target/LLVMIR/gpu.mlir | 19 +- mlir/test/Target/LLVMIR/llvmir-debug.mlir | 42 +- mlir/test/Target/LLVMIR/llvmir-invalid.mlir | 37 + mlir/test/Target/LLVMIR/llvmir.mlir | 14 +- mlir/test/Target/LLVMIR/target-features.mlir | 9 + .../Dialect/Vector/TestVectorTransforms.cpp | 1 + mlir/test/lit.cfg.py | 3 + mlir/test/lit.site.cfg.py.in | 1 + mlir/test/python/dialects/affine.py | 182 +- openmp/libomptarget/CMakeLists.txt | 8 +- openmp/libomptarget/include/PluginManager.h | 108 +- openmp/libomptarget/include/Shared/Debug.h | 7 +- openmp/libomptarget/include/device.h | 26 +- .../plugins-nextgen/amdgpu/src/rtl.cpp | 5 +- .../common/include/GlobalHandler.h | 5 + .../common/src/GlobalHandler.cpp | 20 + .../common/src/PluginInterface.cpp | 17 +- .../plugins-nextgen/common/src/RPC.cpp | 9 +- .../plugins-nextgen/cuda/src/rtl.cpp | 5 +- openmp/libomptarget/src/CMakeLists.txt | 21 + openmp/libomptarget/src/OpenMP/InteropAPI.cpp | 29 +- openmp/libomptarget/src/PluginManager.cpp | 155 +- openmp/libomptarget/src/api.cpp | 108 +- openmp/libomptarget/src/device.cpp | 93 +- openmp/libomptarget/src/interface.cpp | 55 +- openmp/libomptarget/src/omptarget.cpp | 136 +- openmp/libomptarget/src/rtl.cpp | 1 - .../test/Inputs/declare_indirect_func.c | 3 + openmp/libomptarget/test/Inputs/empty.c | 1 + .../test/offloading/barrier_fence.c | 2 + .../libomptarget/test/offloading/bug60119.c | 6 + .../test/offloading/shared_lib_fp_mapping.c | 22 + polly/include/polly/CodeGen/CodegenCleanup.h | 0 .../isl/interface/extract_interface.cc | 2 +- .../CodeGen/MemAccess/create_arrays_heap.ll | 6 +- polly/test/ForwardOpTree/out-of-quota1.ll | 2 +- .../ImportArrays-Negative-size.ll | 6 +- polly/test/ScopInfo/multi-scop.ll | 2 +- .../llvm-project-overlay/clang/BUILD.bazel | 2 +- .../llvm-project-overlay/libc/BUILD.bazel | 21 +- .../libc/test/src/__support/BUILD.bazel | 6 - .../test/src/math/libc_math_test_rules.bzl | 1 - .../llvm-project-overlay/mlir/BUILD.bazel | 15 + .../mlir/test/BUILD.bazel | 1 + 1369 files changed, 66368 insertions(+), 19512 deletions(-) create mode 100644 bolt/test/AArch64/fp-reg-spill.s create mode 100644 clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.cpp create mode 100644 clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.h create mode 100644 clang-tools-extra/docs/clang-tidy/checks/modernize/use-std-numbers.rst create mode 100644 clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-numbers.cpp create mode 100644 clang/include/clang/Basic/DebugOptions.def create mode 100644 clang/test/ClangScanDeps/strip-codegen-args.m create mode 100644 clang/test/CodeGen/SystemZ/atomic_is_lock_free.c create mode 100644 clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-16Al.c create mode 100644 clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-8Al.c create mode 100644 clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i16.c create mode 100644 clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i32.c create mode 100644 clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i64.c create mode 100644 clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i8.c create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-arr.c create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c create mode 100644 clang/test/CodeGen/bpf-preserve-static-offset-pai.c create mode 100644 clang/test/CodeGen/ms-intrinsics-underaligned.c delete mode 100644 clang/test/CodeGenCXX/debug-info-static-inline-member.cpp create mode 100644 clang/test/OpenMP/simd_private_taskloop_codegen.cpp create mode 100644 clang/test/ParserOpenACC/parse-cache-construct.c create mode 100644 clang/test/ParserOpenACC/parse-cache-construct.cpp create mode 100644 clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c create mode 100644 clang/test/Sema/bpf-attr-preserve-static-offset-warns.c create mode 100644 clang/test/Sema/bpf-attr-preserve-static-offset.c delete mode 100644 compiler-rt/lib/asan/asan_lock.h delete mode 100644 compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_openbsd.cpp delete mode 100644 compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_openbsd.h create mode 100644 compiler-rt/test/hwasan/TestCases/memset-recover.cpp create mode 100644 flang/include/flang/Optimizer/Support/DataLayout.h create mode 100644 flang/include/flang/Tools/TargetSetup.h create mode 100644 flang/lib/Optimizer/Support/DataLayout.cpp rename flang/test/Driver/{compiler_options.f90 => compiler-options.f90} (90%) rename flang/test/Driver/{fast_math.f90 => fast-math.f90} (100%) rename flang/test/Driver/{flang_f_opts.f90 => flang-f-opts.f90} (100%) rename flang/test/Driver/{no_duplicate_main.f90 => no-duplicate-main.f90} (100%) create mode 100644 flang/test/Fir/tco-default-datalayout.fir create mode 100644 flang/test/Fir/tco-explicit-datalayout.fir create mode 100644 flang/test/Lower/bbc-host-datalayout.f90 create mode 100644 flang/test/Lower/bbc-target-datalayout.f90 delete mode 100644 libc/src/__support/bit.h delete mode 100644 libc/src/sys/mman/linux/mincore.cpp create mode 100644 libc/src/sys/prctl/CMakeLists.txt create mode 100644 libc/src/sys/prctl/linux/CMakeLists.txt create mode 100644 libc/src/sys/prctl/linux/prctl.cpp rename libc/src/sys/{mman/mincore.h => prctl/prctl.h} (50%) delete mode 100644 libc/test/src/__support/bit_test.cpp delete mode 100644 libc/test/src/sys/mman/linux/mincore_test.cpp create mode 100644 libc/test/src/sys/prctl/CMakeLists.txt create mode 100644 libc/test/src/sys/prctl/linux/CMakeLists.txt create mode 100644 libc/test/src/sys/prctl/linux/prctl_test.cpp create mode 100755 libcxx/utils/clang-format-merge-driver.sh create mode 100644 lld/test/COFF/pdata-arm64ec.test create mode 100644 lldb/source/Plugins/SymbolLocator/Debuginfod/CMakeLists.txt create mode 100644 lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp create mode 100644 lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.h create mode 100644 lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfodProperties.td create mode 100644 llvm/include/llvm/Analysis/DomConditionCache.h create mode 100644 llvm/include/llvm/CodeGen/WasmEHPrepare.h delete mode 100644 llvm/include/llvm/Support/Host.h create mode 100644 llvm/lib/Analysis/DomConditionCache.cpp create mode 100644 llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp create mode 100644 llvm/lib/Target/X86/X86InstrFragments.td create mode 100644 llvm/lib/Target/X86/X86InstrOperands.td create mode 100644 llvm/lib/Target/X86/X86InstrPredicates.td create mode 100644 llvm/lib/Target/X86/X86InstrUtils.td create mode 100644 llvm/test/Analysis/LoopAccessAnalysis/print-order.ll create mode 100644 llvm/test/Assembler/index-value-order.ll create mode 100644 llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.ll create mode 100644 llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir create mode 100644 llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x2.ll create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x4.ll create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane.ll create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x2.ll create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x4.ll create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane.ll create mode 100644 llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir create mode 100644 llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll create mode 100644 llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll create mode 100644 llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll create mode 100644 llvm/test/CodeGen/LoongArch/lasx/vselect.ll create mode 100644 llvm/test/CodeGen/LoongArch/lsx/vselect.ll create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv32.mir create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir create mode 100644 llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll rename llvm/test/CodeGen/WebAssembly/{wasmehprepare.ll => wasm-eh-prepare.ll} (95%) create mode 100644 llvm/test/CodeGen/X86/preserve_mostcc64_win.ll delete mode 100644 llvm/test/DebugInfo/Inputs/dwarfdump-test3-decl.h delete mode 100644 llvm/test/DebugInfo/Inputs/dwarfdump-test3.cc create mode 100644 llvm/test/ExecutionEngine/JITLink/Generic/Inputs/main-ret-0.ll create mode 100644 llvm/test/ExecutionEngine/JITLink/Generic/error-object-passed-as-archive.test create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_smem.s create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_sop1.s create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_sop2.s create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_sop2_alias.s create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_sopc.s create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_sopk.s create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_sopk_alias.s create mode 100644 llvm/test/MC/AMDGPU/gfx12_asm_sopp.s create mode 100644 llvm/test/MC/AMDGPU/gfx12_unsupported.s create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_smem.txt create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/invept.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/invvpid.txt create mode 100644 llvm/test/MC/X86/apx/invept-att.s create mode 100644 llvm/test/MC/X86/apx/invept-intel.s create mode 100644 llvm/test/MC/X86/apx/invvpid-att.s create mode 100644 llvm/test/MC/X86/apx/invvpid-intel.s create mode 100644 llvm/test/Transforms/CodeGenPrepare/debug-info-on-skipped-selects.ll create mode 100644 llvm/test/Transforms/GlobalOpt/globalvar-code-model.ll create mode 100644 llvm/test/Transforms/LoopRotate/delete-dbg-values.ll create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args.ll create mode 100644 llvm/test/Transforms/LoopVectorize/preserve-or-disjoint.ll create mode 100644 llvm/test/Transforms/LowerTypeTests/cfi-nounwind-direct-call.ll create mode 100644 llvm/test/Transforms/LowerTypeTests/cfi-unwind-direct-call.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll create mode 100644 llvm/test/Transforms/TailCallElim/tre-minmax-intrinsic.ll create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s create mode 100644 mlir/include/mlir/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.h create mode 100644 mlir/lib/Target/LLVMIR/Dialect/SPIRV/CMakeLists.txt create mode 100644 mlir/lib/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.cpp create mode 100644 mlir/test/Dialect/Linalg/vectorize-convolution-flatten.mlir create mode 100644 mlir/test/Integration/GPU/SYCL/gpu-addf32-to-spirv.mlir create mode 100644 mlir/test/Integration/GPU/SYCL/gpu-addi64-to-spirv.mlir create mode 100644 mlir/test/Integration/GPU/SYCL/gpu-reluf32-to-spirv.mlir create mode 100644 mlir/test/Integration/GPU/SYCL/lit.local.cfg create mode 100644 mlir/test/Target/LLVMIR/Import/frame-pointer.ll create mode 100644 mlir/test/Target/LLVMIR/Import/target-features.ll create mode 100644 mlir/test/Target/LLVMIR/frame-pointer.mlir create mode 100644 mlir/test/Target/LLVMIR/target-features.mlir create mode 100644 openmp/libomptarget/test/Inputs/declare_indirect_func.c create mode 100644 openmp/libomptarget/test/Inputs/empty.c create mode 100644 openmp/libomptarget/test/offloading/bug60119.c create mode 100644 openmp/libomptarget/test/offloading/shared_lib_fp_mapping.c delete mode 100644 polly/include/polly/CodeGen/CodegenCleanup.h diff --git a/.github/workflows/libcxx-build-and-test.yaml b/.github/workflows/libcxx-build-and-test.yaml index 83786052a539..268e1033387d 100644 --- a/.github/workflows/libcxx-build-and-test.yaml +++ b/.github/workflows/libcxx-build-and-test.yaml @@ -53,7 +53,7 @@ jobs: runs-on: libcxx-runners-8-set continue-on-error: false strategy: - fail-fast: true + fail-fast: false matrix: config: [ 'generic-cxx03', @@ -92,7 +92,7 @@ jobs: needs: [ stage1 ] continue-on-error: false strategy: - fail-fast: true + fail-fast: false matrix: config: [ 'generic-cxx11', diff --git a/.github/workflows/new-prs.yml b/.github/workflows/new-prs.yml index 9ba55d59ff15..18caa408df57 100644 --- a/.github/workflows/new-prs.yml +++ b/.github/workflows/new-prs.yml @@ -15,16 +15,43 @@ on: - synchronize jobs: - automate-prs-labels: + greeter: + runs-on: ubuntu-latest permissions: pull-requests: write + # Only comment on PRs that have been opened for the first time, by someone + # new to LLVM or to GitHub as a whole. + if: >- + (github.repository == 'llvm/llvm-project') && + (github.event.action == 'opened') && + (github.event.pull_request.author_association == 'FIRST_TIME_CONTRIBUTOR' || + github.event.pull_request.author_association == 'FIRST_TIMER') + steps: + - name: Setup Automation Script + run: | + curl -O -L --fail https://raw.githubusercontent.com/"$GITHUB_REPOSITORY"/main/llvm/utils/git/github-automation.py + curl -O -L --fail https://raw.githubusercontent.com/"$GITHUB_REPOSITORY"/main/llvm/utils/git/requirements.txt + chmod a+x github-automation.py + pip install -r requirements.txt + + - name: Greet Author + run: | + ./github-automation.py \ + --token '${{ secrets.GITHUB_TOKEN }}' \ + pr-greeter \ + --issue-number "${{ github.event.pull_request.number }}" + + automate-prs-labels: + # Greet first so that only the author gets that notification. + needs: greeter runs-on: ubuntu-latest # Ignore PRs with more than 10 commits. Pull requests with a lot of # commits tend to be accidents usually when someone made a mistake while trying # to rebase. We want to ignore these pull requests to avoid excessive # notifications. + # always() means that even if greeter is skipped, this job will run. if: > - github.repository == 'llvm/llvm-project' && + always() && github.repository == 'llvm/llvm-project' && github.event.pull_request.draft == false && github.event.pull_request.commits < 10 steps: diff --git a/bolt/lib/Passes/IndirectCallPromotion.cpp b/bolt/lib/Passes/IndirectCallPromotion.cpp index 8b084c3b63d5..f40f5e7acbf3 100644 --- a/bolt/lib/Passes/IndirectCallPromotion.cpp +++ b/bolt/lib/Passes/IndirectCallPromotion.cpp @@ -158,6 +158,7 @@ static cl::opt ICPPeelForInline( } // namespace opts +#ifndef NDEBUG static bool verifyProfile(std::map &BFs) { bool IsValid = true; for (auto &BFI : BFs) { @@ -182,6 +183,7 @@ static bool verifyProfile(std::map &BFs) { } return IsValid; } +#endif namespace llvm { namespace bolt { @@ -1467,7 +1469,6 @@ void IndirectCallPromotion::runOnFunctions(BinaryContext &BC) { std::max(TotalIndexBasedCandidates, 1)) << "%\n"; - (void)verifyProfile; #ifndef NDEBUG verifyProfile(BFs); #endif diff --git a/bolt/lib/Passes/ReorderAlgorithm.cpp b/bolt/lib/Passes/ReorderAlgorithm.cpp index 3c3365e1d3d7..c112e1a8dcea 100644 --- a/bolt/lib/Passes/ReorderAlgorithm.cpp +++ b/bolt/lib/Passes/ReorderAlgorithm.cpp @@ -20,7 +20,7 @@ #include #include -#undef DEBUG_TYPE +#undef DEBUG_TYPE #define DEBUG_TYPE "bolt" using namespace llvm; @@ -425,7 +425,7 @@ void TSPReorderAlgorithm::reorderBasicBlocks(BinaryFunction &BF, } std::vector> DP; - DP.resize(1 << N); + DP.resize(static_cast(1) << N); for (std::vector &Elmt : DP) Elmt.resize(N, -1); diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp index b852b9fbc9c5..d90512e21225 100644 --- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp +++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp @@ -314,6 +314,12 @@ public: bool isRegToRegMove(const MCInst &Inst, MCPhysReg &From, MCPhysReg &To) const override { + if (Inst.getOpcode() == AArch64::FMOVDXr) { + From = Inst.getOperand(1).getReg(); + To = Inst.getOperand(0).getReg(); + return true; + } + if (Inst.getOpcode() != AArch64::ORRXrs) return false; if (Inst.getOperand(1).getReg() != AArch64::XZR) diff --git a/bolt/test/AArch64/fp-reg-spill.s b/bolt/test/AArch64/fp-reg-spill.s new file mode 100644 index 000000000000..65523148edd3 --- /dev/null +++ b/bolt/test/AArch64/fp-reg-spill.s @@ -0,0 +1,19 @@ +# Check that we correctly handle arm64 fp register spills in +# bolt when we are processing jump tables. +# REQUIRES: system-linux +# RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o +# RUN: ld.lld --emit-relocs %t.o -o %t.elf +# RUN: llvm-bolt --jump-tables=move %t.elf -o %t.bolt + +.globl _foo, _start + +_foo: + ret + +_start: + adr x6, _foo + fmov d18,x6 + fmov x5,d18 + ldrb w5, [x5, w1, uxtw] + add x5, x6, w5, sxtb #2 + br x5 diff --git a/bolt/test/runtime/AArch64/instrumentation-ind-call.c b/bolt/test/runtime/AArch64/instrumentation-ind-call.c index 76ee8c05dd29..f9056da333b4 100644 --- a/bolt/test/runtime/AArch64/instrumentation-ind-call.c +++ b/bolt/test/runtime/AArch64/instrumentation-ind-call.c @@ -14,7 +14,7 @@ int main() { /* REQUIRES: system-linux,bolt-runtime -RUN: %clang %cflags %s -o %t.exe -Wl,-q -nopie -fpie +RUN: %clang %cflags %s -o %t.exe -Wl,-q -no-pie -fpie RUN: llvm-bolt %t.exe --instrument --instrumentation-file=%t.fdata \ RUN: -o %t.instrumented diff --git a/clang-tools-extra/clang-tidy/ClangTidy.cpp b/clang-tools-extra/clang-tidy/ClangTidy.cpp index 4b1a67b6dd98..565f044778c9 100644 --- a/clang-tools-extra/clang-tidy/ClangTidy.cpp +++ b/clang-tools-extra/clang-tidy/ClangTidy.cpp @@ -147,7 +147,8 @@ public: Files.makeAbsolutePath(FixAbsoluteFilePath); tooling::Replacement R(FixAbsoluteFilePath, Repl.getOffset(), Repl.getLength(), Repl.getReplacementText()); - Replacements &Replacements = FileReplacements[R.getFilePath()]; + auto &Entry = FileReplacements[R.getFilePath()]; + Replacements &Replacements = Entry.Replaces; llvm::Error Err = Replacements.add(R); if (Err) { // FIXME: Implement better conflict handling. @@ -174,6 +175,7 @@ public: } FixLoc = getLocation(FixAbsoluteFilePath, Repl.getOffset()); FixLocations.push_back(std::make_pair(FixLoc, CanBeApplied)); + Entry.BuildDir = Error.BuildDirectory; } } } @@ -189,9 +191,14 @@ public: void finish() { if (TotalFixes > 0) { - Rewriter Rewrite(SourceMgr, LangOpts); + auto &VFS = Files.getVirtualFileSystem(); + auto OriginalCWD = VFS.getCurrentWorkingDirectory(); + bool AnyNotWritten = false; + for (const auto &FileAndReplacements : FileReplacements) { + Rewriter Rewrite(SourceMgr, LangOpts); StringRef File = FileAndReplacements.first(); + VFS.setCurrentWorkingDirectory(FileAndReplacements.second.BuildDir); llvm::ErrorOr> Buffer = SourceMgr.getFileManager().getBufferForFile(File); if (!Buffer) { @@ -208,8 +215,8 @@ public: continue; } llvm::Expected Replacements = - format::cleanupAroundReplacements(Code, FileAndReplacements.second, - *Style); + format::cleanupAroundReplacements( + Code, FileAndReplacements.second.Replaces, *Style); if (!Replacements) { llvm::errs() << llvm::toString(Replacements.takeError()) << "\n"; continue; @@ -226,13 +233,18 @@ public: if (!tooling::applyAllReplacements(Replacements.get(), Rewrite)) { llvm::errs() << "Can't apply replacements for file " << File << "\n"; } + AnyNotWritten &= Rewrite.overwriteChangedFiles(); } - if (Rewrite.overwriteChangedFiles()) { + + if (AnyNotWritten) { llvm::errs() << "clang-tidy failed to apply suggested fixes.\n"; } else { llvm::errs() << "clang-tidy applied " << AppliedFixes << " of " << TotalFixes << " suggested fixes.\n"; } + + if (OriginalCWD) + VFS.setCurrentWorkingDirectory(*OriginalCWD); } } @@ -289,13 +301,18 @@ private: return CharSourceRange::getCharRange(BeginLoc, EndLoc); } + struct ReplacementsWithBuildDir { + StringRef BuildDir; + Replacements Replaces; + }; + FileManager Files; LangOptions LangOpts; // FIXME: use langopts from each original file IntrusiveRefCntPtr DiagOpts; DiagnosticConsumer *DiagPrinter; DiagnosticsEngine Diags; SourceManager SourceMgr; - llvm::StringMap FileReplacements; + llvm::StringMap FileReplacements; ClangTidyContext &Context; FixBehaviour ApplyFixes; unsigned TotalFixes = 0U; diff --git a/clang-tools-extra/clang-tidy/modernize/CMakeLists.txt b/clang-tools-extra/clang-tidy/modernize/CMakeLists.txt index c40065358d2d..28ca52f46943 100644 --- a/clang-tools-extra/clang-tidy/modernize/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/modernize/CMakeLists.txt @@ -39,6 +39,7 @@ add_clang_library(clangTidyModernizeModule UseNullptrCheck.cpp UseOverrideCheck.cpp UseStartsEndsWithCheck.cpp + UseStdNumbersCheck.cpp UseStdPrintCheck.cpp UseTrailingReturnTypeCheck.cpp UseTransparentFunctorsCheck.cpp diff --git a/clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp b/clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp index e994ffd2a75c..654f4bd0c6ba 100644 --- a/clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp @@ -40,6 +40,7 @@ #include "UseNullptrCheck.h" #include "UseOverrideCheck.h" #include "UseStartsEndsWithCheck.h" +#include "UseStdNumbersCheck.h" #include "UseStdPrintCheck.h" #include "UseTrailingReturnTypeCheck.h" #include "UseTransparentFunctorsCheck.h" @@ -69,6 +70,8 @@ public: CheckFactories.registerCheck("modernize-pass-by-value"); CheckFactories.registerCheck( "modernize-use-starts-ends-with"); + CheckFactories.registerCheck( + "modernize-use-std-numbers"); CheckFactories.registerCheck("modernize-use-std-print"); CheckFactories.registerCheck( "modernize-raw-string-literal"); diff --git a/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.cpp b/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.cpp new file mode 100644 index 000000000000..b299afd540b9 --- /dev/null +++ b/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.cpp @@ -0,0 +1,448 @@ +//===--- UseStdNumbersCheck.cpp - clang_tidy ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX_License_Identifier: Apache_2.0 WITH LLVM_exception +// +//===----------------------------------------------------------------------===// + +#include "UseStdNumbersCheck.h" +#include "../ClangTidyDiagnosticConsumer.h" +#include "clang/AST/ASTContext.h" +#include "clang/AST/Decl.h" +#include "clang/AST/Expr.h" +#include "clang/AST/Stmt.h" +#include "clang/AST/Type.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/ASTMatchers/ASTMatchers.h" +#include "clang/ASTMatchers/ASTMatchersInternal.h" +#include "clang/ASTMatchers/ASTMatchersMacros.h" +#include "clang/Basic/Diagnostic.h" +#include "clang/Basic/LLVM.h" +#include "clang/Basic/LangOptions.h" +#include "clang/Basic/SourceLocation.h" +#include "clang/Basic/SourceManager.h" +#include "clang/Lex/Lexer.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/FormatVariadic.h" +#include "llvm/Support/MathExtras.h" +#include +#include +#include +#include +#include +#include +#include + +namespace { +using namespace clang::ast_matchers; +using clang::ast_matchers::internal::Matcher; +using llvm::StringRef; + +AST_MATCHER_P2(clang::FloatingLiteral, near, double, Value, double, + DiffThreshold) { + return std::abs(Node.getValueAsApproximateDouble() - Value) < DiffThreshold; +} + +AST_MATCHER_P(clang::QualType, hasCanonicalTypeUnqualified, + Matcher, InnerMatcher) { + return !Node.isNull() && + InnerMatcher.matches(Node->getCanonicalTypeUnqualified(), Finder, + Builder); +} + +AST_MATCHER(clang::QualType, isArithmetic) { + return !Node.isNull() && Node->isArithmeticType(); +} +AST_MATCHER(clang::QualType, isFloating) { + return !Node.isNull() && Node->isFloatingType(); +} + +AST_MATCHER_P(clang::Expr, anyOfExhaustive, std::vector>, + Exprs) { + bool FoundMatch = false; + for (const auto &InnerMatcher : Exprs) { + clang::ast_matchers::internal::BoundNodesTreeBuilder Result = *Builder; + if (InnerMatcher.matches(Node, Finder, &Result)) { + *Builder = std::move(Result); + FoundMatch = true; + } + } + return FoundMatch; +} + +// Using this struct to store the 'DiffThreshold' config value to create the +// matchers without the need to pass 'DiffThreshold' into every matcher. +// 'DiffThreshold' is needed in the 'near' matcher, which is used for matching +// the literal of every constant and for formulas' subexpressions that look at +// literals. +struct MatchBuilder { + auto + ignoreParenAndArithmeticCasting(const Matcher Matcher) const { + return expr(hasType(qualType(isArithmetic())), ignoringParenCasts(Matcher)); + } + + auto ignoreParenAndFloatingCasting(const Matcher Matcher) const { + return expr(hasType(qualType(isFloating())), ignoringParenCasts(Matcher)); + } + + auto matchMathCall(const StringRef FunctionName, + const Matcher ArgumentMatcher) const { + return expr(ignoreParenAndFloatingCasting( + callExpr(callee(functionDecl(hasName(FunctionName), + hasParameter(0, hasType(isArithmetic())))), + hasArgument(0, ArgumentMatcher)))); + } + + auto matchSqrt(const Matcher ArgumentMatcher) const { + return matchMathCall("sqrt", ArgumentMatcher); + } + + // Used for top-level matchers (i.e. the match that replaces Val with its + // constant). + // + // E.g. The matcher of `std::numbers::pi` uses this matcher to look for + // floatLiterals that have the value of pi. + // + // If the match is for a top-level match, we only care about the literal. + auto matchFloatLiteralNear(const StringRef Constant, const double Val) const { + return expr(ignoreParenAndFloatingCasting( + floatLiteral(near(Val, DiffThreshold)).bind(Constant))); + } + + // Used for non-top-level matchers (i.e. matchers that are used as inner + // matchers for top-level matchers). + // + // E.g.: The matcher of `std::numbers::log2e` uses this matcher to check if + // `e` of `log2(e)` is declared constant and initialized with the value for + // eulers number. + // + // Here, we do care about literals and about DeclRefExprs to variable + // declarations that are constant and initialized with `Val`. This allows + // top-level matchers to see through declared constants for their inner + // matches like the `std::numbers::log2e` matcher. + auto matchFloatValueNear(const double Val) const { + const auto Float = floatLiteral(near(Val, DiffThreshold)); + + const auto Dref = declRefExpr( + to(varDecl(hasType(qualType(isConstQualified(), isFloating())), + hasInitializer(ignoreParenAndFloatingCasting(Float))))); + return expr(ignoreParenAndFloatingCasting(anyOf(Float, Dref))); + } + + auto matchValue(const int64_t ValInt) const { + const auto Int = + expr(ignoreParenAndArithmeticCasting(integerLiteral(equals(ValInt)))); + const auto Float = expr(ignoreParenAndFloatingCasting( + matchFloatValueNear(static_cast(ValInt)))); + const auto Dref = declRefExpr(to(varDecl( + hasType(qualType(isConstQualified(), isArithmetic())), + hasInitializer(expr(anyOf(ignoringImplicit(Int), + ignoreParenAndFloatingCasting(Float))))))); + return expr(anyOf(Int, Float, Dref)); + } + + auto match1Div(const Matcher Match) const { + return binaryOperator(hasOperatorName("/"), hasLHS(matchValue(1)), + hasRHS(Match)); + } + + auto matchEuler() const { + return expr(anyOf(matchFloatValueNear(llvm::numbers::e), + matchMathCall("exp", matchValue(1)))); + } + auto matchEulerTopLevel() const { + return expr(anyOf(matchFloatLiteralNear("e_literal", llvm::numbers::e), + matchMathCall("exp", matchValue(1)).bind("e_pattern"))) + .bind("e"); + } + + auto matchLog2Euler() const { + return expr( + anyOf( + matchFloatLiteralNear("log2e_literal", llvm::numbers::log2e), + matchMathCall("log2", matchEuler()).bind("log2e_pattern"))) + .bind("log2e"); + } + + auto matchLog10Euler() const { + return expr( + anyOf( + matchFloatLiteralNear("log10e_literal", + llvm::numbers::log10e), + matchMathCall("log10", matchEuler()).bind("log10e_pattern"))) + .bind("log10e"); + } + + auto matchPi() const { return matchFloatValueNear(llvm::numbers::pi); } + auto matchPiTopLevel() const { + return matchFloatLiteralNear("pi_literal", llvm::numbers::pi).bind("pi"); + } + + auto matchEgamma() const { + return matchFloatLiteralNear("egamma_literal", llvm::numbers::egamma) + .bind("egamma"); + } + + auto matchInvPi() const { + return expr(anyOf(matchFloatLiteralNear("inv_pi_literal", + llvm::numbers::inv_pi), + match1Div(matchPi()).bind("inv_pi_pattern"))) + .bind("inv_pi"); + } + + auto matchInvSqrtPi() const { + return expr(anyOf( + matchFloatLiteralNear("inv_sqrtpi_literal", + llvm::numbers::inv_sqrtpi), + match1Div(matchSqrt(matchPi())).bind("inv_sqrtpi_pattern"))) + .bind("inv_sqrtpi"); + } + + auto matchLn2() const { + return expr(anyOf(matchFloatLiteralNear("ln2_literal", llvm::numbers::ln2), + matchMathCall("log", matchValue(2)).bind("ln2_pattern"))) + .bind("ln2"); + } + + auto machterLn10() const { + return expr( + anyOf(matchFloatLiteralNear("ln10_literal", llvm::numbers::ln10), + matchMathCall("log", matchValue(10)).bind("ln10_pattern"))) + .bind("ln10"); + } + + auto matchSqrt2() const { + return expr(anyOf(matchFloatLiteralNear("sqrt2_literal", + llvm::numbers::sqrt2), + matchSqrt(matchValue(2)).bind("sqrt2_pattern"))) + .bind("sqrt2"); + } + + auto matchSqrt3() const { + return expr(anyOf(matchFloatLiteralNear("sqrt3_literal", + llvm::numbers::sqrt3), + matchSqrt(matchValue(3)).bind("sqrt3_pattern"))) + .bind("sqrt3"); + } + + auto matchInvSqrt3() const { + return expr(anyOf(matchFloatLiteralNear("inv_sqrt3_literal", + llvm::numbers::inv_sqrt3), + match1Div(matchSqrt(matchValue(3))) + .bind("inv_sqrt3_pattern"))) + .bind("inv_sqrt3"); + } + + auto matchPhi() const { + const auto PhiFormula = binaryOperator( + hasOperatorName("/"), + hasLHS(binaryOperator( + hasOperatorName("+"), hasEitherOperand(matchValue(1)), + hasEitherOperand(matchMathCall("sqrt", matchValue(5))))), + hasRHS(matchValue(2))); + return expr(anyOf(PhiFormula.bind("phi_pattern"), + matchFloatLiteralNear("phi_literal", llvm::numbers::phi))) + .bind("phi"); + } + + double DiffThreshold; +}; + +std::string getCode(const StringRef Constant, const bool IsFloat, + const bool IsLongDouble) { + if (IsFloat) { + return ("std::numbers::" + Constant + "_v").str(); + } + if (IsLongDouble) { + return ("std::numbers::" + Constant + "_v").str(); + } + return ("std::numbers::" + Constant).str(); +} + +bool isRangeOfCompleteMacro(const clang::SourceRange &Range, + const clang::SourceManager &SM, + const clang::LangOptions &LO) { + if (!Range.getBegin().isMacroID()) { + return false; + } + if (!clang::Lexer::isAtStartOfMacroExpansion(Range.getBegin(), SM, LO)) { + return false; + } + + if (!Range.getEnd().isMacroID()) { + return false; + } + + if (!clang::Lexer::isAtEndOfMacroExpansion(Range.getEnd(), SM, LO)) { + return false; + } + + return true; +} + +} // namespace + +namespace clang::tidy::modernize { +UseStdNumbersCheck::UseStdNumbersCheck(const StringRef Name, + ClangTidyContext *const Context) + : ClangTidyCheck(Name, Context), + IncludeInserter(Options.getLocalOrGlobal("IncludeStyle", + utils::IncludeSorter::IS_LLVM), + areDiagsSelfContained()), + DiffThresholdString{Options.get("DiffThreshold", "0.001")} { + if (DiffThresholdString.getAsDouble(DiffThreshold)) { + configurationDiag( + "Invalid DiffThreshold config value: '%0', expected a double") + << DiffThresholdString; + DiffThreshold = 0.001; + } +} + +void UseStdNumbersCheck::registerMatchers(MatchFinder *const Finder) { + const auto Matches = MatchBuilder{DiffThreshold}; + std::vector> ConstantMatchers = { + Matches.matchLog2Euler(), Matches.matchLog10Euler(), + Matches.matchEulerTopLevel(), Matches.matchEgamma(), + Matches.matchInvSqrtPi(), Matches.matchInvPi(), + Matches.matchPiTopLevel(), Matches.matchLn2(), + Matches.machterLn10(), Matches.matchSqrt2(), + Matches.matchInvSqrt3(), Matches.matchSqrt3(), + Matches.matchPhi(), + }; + + Finder->addMatcher( + expr( + anyOfExhaustive(std::move(ConstantMatchers)), + unless(hasParent(explicitCastExpr(hasDestinationType(isFloating())))), + hasType(qualType(hasCanonicalTypeUnqualified( + anyOf(qualType(asString("float")).bind("float"), + qualType(asString("double")), + qualType(asString("long double")).bind("long double")))))), + this); +} + +void UseStdNumbersCheck::check(const MatchFinder::MatchResult &Result) { + /* + List of all math constants in the `` header + + e + + log2e + + log10e + + pi + + inv_pi + + inv_sqrtpi + + ln2 + + ln10 + + sqrt2 + + sqrt3 + + inv_sqrt3 + + egamma + + phi + */ + + // The ordering determines what constants are looked at first. + // E.g. look at 'inv_sqrt3' before 'sqrt3' to be able to replace the larger + // expression + constexpr auto Constants = std::array, 13>{ + std::pair{StringRef{"log2e"}, llvm::numbers::log2e}, + std::pair{StringRef{"log10e"}, llvm::numbers::log10e}, + std::pair{StringRef{"e"}, llvm::numbers::e}, + std::pair{StringRef{"egamma"}, llvm::numbers::egamma}, + std::pair{StringRef{"inv_sqrtpi"}, llvm::numbers::inv_sqrtpi}, + std::pair{StringRef{"inv_pi"}, llvm::numbers::inv_pi}, + std::pair{StringRef{"pi"}, llvm::numbers::pi}, + std::pair{StringRef{"ln2"}, llvm::numbers::ln2}, + std::pair{StringRef{"ln10"}, llvm::numbers::ln10}, + std::pair{StringRef{"sqrt2"}, llvm::numbers::sqrt2}, + std::pair{StringRef{"inv_sqrt3"}, llvm::numbers::inv_sqrt3}, + std::pair{StringRef{"sqrt3"}, llvm::numbers::sqrt3}, + std::pair{StringRef{"phi"}, llvm::numbers::phi}, + }; + + auto MatchedLiterals = + llvm::SmallVector>{}; + + const auto &SM = *Result.SourceManager; + const auto &LO = Result.Context->getLangOpts(); + + const auto IsFloat = Result.Nodes.getNodeAs("float") != nullptr; + const auto IsLongDouble = + Result.Nodes.getNodeAs("long double") != nullptr; + + for (const auto &[ConstantName, ConstantValue] : Constants) { + const auto *const Match = Result.Nodes.getNodeAs(ConstantName); + if (Match == nullptr) { + continue; + } + + const auto Range = Match->getSourceRange(); + + const auto IsMacro = Range.getBegin().isMacroID(); + + // We do not want to emit a diagnostic when we are matching a macro, but the + // match inside of the macro does not cover the whole macro. + if (IsMacro && !isRangeOfCompleteMacro(Range, SM, LO)) { + continue; + } + + if (const auto PatternBindString = (ConstantName + "_pattern").str(); + Result.Nodes.getNodeAs(PatternBindString) != nullptr) { + const auto Code = getCode(ConstantName, IsFloat, IsLongDouble); + diag(Range.getBegin(), "prefer '%0' to this %select{formula|macro}1") + << Code << IsMacro << FixItHint::CreateReplacement(Range, Code); + return; + } + + const auto LiteralBindString = (ConstantName + "_literal").str(); + if (const auto *const Literal = + Result.Nodes.getNodeAs(LiteralBindString)) { + MatchedLiterals.emplace_back( + ConstantName, + std::abs(Literal->getValueAsApproximateDouble() - ConstantValue), + Match); + } + } + + // We may have had no matches with literals, but a match with a pattern that + // was a part of a macro which was therefore skipped. + if (MatchedLiterals.empty()) { + return; + } + + llvm::sort(MatchedLiterals, [](const auto &LHS, const auto &RHS) { + return std::get<1>(LHS) < std::get<1>(RHS); + }); + + const auto &[Constant, Diff, Node] = MatchedLiterals.front(); + + const auto Range = Node->getSourceRange(); + const auto IsMacro = Range.getBegin().isMacroID(); + + // We do not want to emit a diagnostic when we are matching a macro, but the + // match inside of the macro does not cover the whole macro. + if (IsMacro && !isRangeOfCompleteMacro(Range, SM, LO)) { + return; + } + + const auto Code = getCode(Constant, IsFloat, IsLongDouble); + diag(Range.getBegin(), + "prefer '%0' to this %select{literal|macro}1, differs by '%2'") + << Code << IsMacro << llvm::formatv("{0:e2}", Diff).str() + << FixItHint::CreateReplacement(Range, Code) + << IncludeInserter.createIncludeInsertion( + Result.SourceManager->getFileID(Range.getBegin()), ""); +} + +void UseStdNumbersCheck::registerPPCallbacks( + const SourceManager &SM, Preprocessor *const PP, + Preprocessor *const ModuleExpanderPP) { + IncludeInserter.registerPreprocessor(PP); +} + +void UseStdNumbersCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { + Options.store(Opts, "IncludeStyle", IncludeInserter.getStyle()); + Options.store(Opts, "DiffThreshold", DiffThresholdString); +} +} // namespace clang::tidy::modernize diff --git a/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.h b/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.h new file mode 100644 index 000000000000..05fc5ada14b8 --- /dev/null +++ b/clang-tools-extra/clang-tidy/modernize/UseStdNumbersCheck.h @@ -0,0 +1,49 @@ +//===--- UseStdNumbersCheck.h - clang-tidy ----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MODERNIZE_USESTDNUMBERSCHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MODERNIZE_USESTDNUMBERSCHECK_H + +#include "../ClangTidyCheck.h" +#include "../utils/IncludeInserter.h" + +namespace clang::tidy::modernize { + +/// Finds constants and function calls to math functions that can be replaced +/// with c++20's mathematical constants from the ``numbers`` header and +/// offers fix-it hints. +/// Does not match the use of variables with that value, and instead, +/// offers a replacement at the definition of those variables. +/// +/// For the user-facing documentation see: +/// http://clang.llvm.org/extra/clang-tidy/checks/modernize/use-std-numbers.html +class UseStdNumbersCheck : public ClangTidyCheck { +public: + UseStdNumbersCheck(StringRef Name, ClangTidyContext *Context); + + bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { + return LangOpts.CPlusPlus20; + } + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + void registerPPCallbacks(const SourceManager &SM, Preprocessor *PP, + Preprocessor *ModuleExpanderPP) override; + void storeOptions(ClangTidyOptions::OptionMap &Opts) override; + std::optional getCheckTraversalKind() const override { + return TK_IgnoreUnlessSpelledInSource; + } + +private: + utils::IncludeInserter IncludeInserter; + StringRef DiffThresholdString; + double DiffThreshold; +}; + +} // namespace clang::tidy::modernize + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MODERNIZE_USESTDNUMBERSCHECK_H diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 4ff4494cef56..9262f9bbfe62 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -193,6 +193,13 @@ New checks replacing with ``starts_with`` when the method exists in the class. Notably, this will work with ``std::string`` and ``std::string_view``. +- New :doc:`modernize-use-std-numbers + ` check. + + Finds constants and function calls to math functions that can be replaced + with C++20's mathematical constants from the ``numbers`` header and + offers fix-it hints. + - New :doc:`performance-enum-size ` check. diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index df2d5d15238d..e6c02fe48fbf 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -293,6 +293,7 @@ Clang-Tidy Checks :doc:`modernize-use-nullptr `, "Yes" :doc:`modernize-use-override `, "Yes" :doc:`modernize-use-starts-ends-with `, "Yes" + :doc:`modernize-use-std-numbers `, "Yes" :doc:`modernize-use-std-print `, "Yes" :doc:`modernize-use-trailing-return-type `, "Yes" :doc:`modernize-use-transparent-functors `, "Yes" diff --git a/clang-tools-extra/docs/clang-tidy/checks/modernize/use-std-numbers.rst b/clang-tools-extra/docs/clang-tidy/checks/modernize/use-std-numbers.rst new file mode 100644 index 000000000000..207e9c00e74b --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/modernize/use-std-numbers.rst @@ -0,0 +1,74 @@ +.. title:: clang-tidy - modernize-use-std-numbers + +modernize-use-std-numbers +========================= + +Finds constants and function calls to math functions that can be replaced +with C++20's mathematical constants from the ``numbers`` header and offers +fix-it hints. +Does not match the use of variables with that value, and instead, +offers a replacement for the definition of those variables. +Function calls that match the pattern of how the constant is calculated are +matched and replaced with the ``std::numbers`` constant. +The use of macros gets replaced with the corresponding ``std::numbers`` +constant, instead of changing the macro definition. + +The following list of constants from the ``numbers`` header are supported: + +* ``e`` +* ``log2e`` +* ``log10e`` +* ``pi`` +* ``inv_pi`` +* ``inv_sqrtpi`` +* ``ln2`` +* ``ln10`` +* ``sqrt2`` +* ``sqrt3`` +* ``inv_sqrt3`` +* ``egamma`` +* ``phi`` + +The list currently includes all constants as of C++20. + +The replacements use the type of the matched constant and can remove explicit +casts, i.e., switching between ``std::numbers::e``, +``std::numbers::e_v`` and ``std::numbers::e_v`` where +appropriate. + +.. code-block:: c++ + + double sqrt(double); + double log2(double); + void sink(auto&&) {} + void floatSink(float); + + #define MY_PI 3.1415926 + + void foo() { + const double Pi = 3.141592653589; // const double Pi = std::numbers::pi + const auto Use = Pi / 2; // no match for Pi + static constexpr double Euler = 2.7182818; // static constexpr double Euler = std::numbers::e; + + log2(exp(1)); // std::numbers::log2e; + log2(Euler); // std::numbers::log2e; + 1 / sqrt(MY_PI); // std::numbers::inv_sqrtpi; + sink(MY_PI); // sink(std::numbers::pi); + floatSink(MY_PI); // floatSink(std::numbers::pi); + floatSink(static_cast(MY_PI)); // floatSink(std::numbers::pi_v); + } + +Options +------- + +.. option:: DiffThreshold + + A floating point value that sets the detection threshold for when literals + match a constant. A literal matches a constant if + ``abs(literal - constant) < DiffThreshold`` evaluates to ``true``. Default + is `0.001`. + +.. option:: IncludeStyle + + A string specifying which include-style is used, `llvm` or `google`. Default + is `llvm`. diff --git a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-numbers.cpp b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-numbers.cpp new file mode 100644 index 000000000000..6c5762da5e2e --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-numbers.cpp @@ -0,0 +1,493 @@ +// RUN: %check_clang_tidy -check-suffix=ALL -std=c++20 %s modernize-use-std-numbers %t +// RUN: %check_clang_tidy -check-suffix=ALL,IMPRECISE -std=c++20 %s modernize-use-std-numbers %t -- -config="{CheckOptions: { modernize-use-std-numbers.DiffThreshold: 0.01 }}" + +// CHECK-FIXES-ALL: #include + +namespace bar { + double sqrt(double Arg); + float sqrt(float Arg); + template + auto sqrt(T val) { return sqrt(static_cast(val)); } + + static constexpr double e = 2.718281828459045235360287471352662497757247093; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:33: warning: prefer 'std::numbers::e' to this literal, differs by '0.00e+00' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr double e = std::numbers::e; +} + +double exp(double Arg); +double log(double Arg); + +double log2(double Arg); +float log2(float Arg); +template +auto log2(T val) { return log2(static_cast(val)); } + +double log10(double Arg); + +template +void sink(T&&) { } + +void floatSink(float) {} + +#define MY_PI 3.1415926 + +#define INV_SQRT3 1 / bar::sqrt(3) +#define NOT_INV_SQRT3 1 / bar::sqrt(3) + 1 + +using my_double = double; +using my_float = float; + +void foo(){ + static constexpr double Pi = 3.1415926; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:34: warning: prefer 'std::numbers::pi' to this literal, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr double Pi = std::numbers::pi; + + static constexpr double Euler = 2.7182818; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:37: warning: prefer 'std::numbers::e' to this literal, differs by '2.85e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr double Euler = std::numbers::e; + + static constexpr double Phi = 1.6180339; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:35: warning: prefer 'std::numbers::phi' to this literal, differs by '8.87e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr double Phi = std::numbers::phi; + + static constexpr double PiCopy = Pi; + static constexpr double PiDefineFromMacro = MY_PI; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:49: warning: prefer 'std::numbers::pi' to this macro, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr double PiDefineFromMacro = std::numbers::pi; + + static constexpr double Pi2 = 3.14; + // CHECK-MESSAGES-IMPRECISE: :[[@LINE-1]]:35: warning: prefer 'std::numbers::pi' to this literal, differs by '1.59e-03' [modernize-use-std-numbers] + // CHECK-FIXES-IMPRECISE: static constexpr double Pi2 = std::numbers::pi; + static constexpr double Euler2 = 2.71; + // CHECK-MESSAGES-IMPRECISE: :[[@LINE-1]]:38: warning: prefer 'std::numbers::e' to this literal, differs by '8.28e-03' [modernize-use-std-numbers] + // CHECK-FIXES-IMPRECISE: static constexpr double Euler2 = std::numbers::e; + static constexpr double Phi2 = 1.61; + // CHECK-MESSAGES-IMPRECISE: :[[@LINE-1]]:36: warning: prefer 'std::numbers::phi' to this literal, differs by '8.03e-03' [modernize-use-std-numbers] + // CHECK-FIXES-IMPRECISE: static constexpr double Phi2 = std::numbers::phi; + + static constexpr double Pi3 = 3.1415926L; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:35: warning: prefer 'std::numbers::pi_v' to this literal, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr double Pi3 = std::numbers::pi_v; + + static constexpr double Euler3 = 2.7182818L; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:38: warning: prefer 'std::numbers::e_v' to this literal, differs by '2.85e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr double Euler3 = std::numbers::e_v; + + static constexpr double Phi3 = 1.6180339L; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:36: warning: prefer 'std::numbers::phi_v' to this literal, differs by '8.87e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr double Phi3 = std::numbers::phi_v; + + static constexpr long double Pi4 = 3.1415926L; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:40: warning: prefer 'std::numbers::pi_v' to this literal, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr long double Pi4 = std::numbers::pi_v; + + static constexpr long double Euler4 = 2.7182818L; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:43: warning: prefer 'std::numbers::e_v' to this literal, differs by '2.85e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr long double Euler4 = std::numbers::e_v; + + static constexpr long double Phi4 = 1.6180339L; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:41: warning: prefer 'std::numbers::phi_v' to this literal, differs by '8.87e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr long double Phi4 = std::numbers::phi_v; + + static constexpr my_double Euler5 = 2.7182818; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:41: warning: prefer 'std::numbers::e' to this literal, differs by '2.85e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr my_double Euler5 = std::numbers::e; + + static constexpr my_float Euler6 = 2.7182818; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:40: warning: prefer 'std::numbers::e' to this literal, differs by '2.85e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr my_float Euler6 = std::numbers::e; + + static constexpr int NotEuler7 = 2.7182818; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:38: warning: prefer 'std::numbers::e' to this literal, differs by '2.85e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr int NotEuler7 = std::numbers::e; + + static constexpr double InvPi = 1.0 / Pi; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:37: warning: prefer 'std::numbers::inv_pi' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr double InvPi = std::numbers::inv_pi; + + static constexpr my_float Actually2MyFloat = 2; + bar::sqrt(Actually2MyFloat); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2_v' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2_v; + + sink(MY_PI); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::pi' to this macro, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::pi); + + auto X = 42.0; + auto Y = X * 3.14; + // CHECK-MESSAGES-IMPRECISE: :[[@LINE-1]]:18: warning: prefer 'std::numbers::pi' to this literal, differs by '1.59e-03' [modernize-use-std-numbers] + // CHECK-FIXES-IMPRECISE: auto Y = X * std::numbers::pi; + + constexpr static auto One = 1; + constexpr static auto Two = 2; + + bar::sqrt(2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2; + + bar::sqrt(Two); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2; + + bar::sqrt(2.0); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2; + + auto Not2 = 2; + Not2 = 42; + bar::sqrt(Not2); + + const auto Actually2 = 2; + bar::sqrt(Actually2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2; + + exp(1); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::e; + + exp(One); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::e; + + exp(1.00000000000001); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::e; + + log2(exp(1)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log2e' to this formula [modernize-use-std-numbers] + // CHECK-MESSAGES-ALL: :[[@LINE-2]]:10: warning: prefer 'std::numbers::e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log2e; + + log2(Euler); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log2e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log2e; + + log2(bar::e); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log2e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log2e; + + log2(Euler5); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log2e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log2e; + + log2(Euler6); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log2e_v' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log2e_v; + + log2(NotEuler7); + + auto log2e = 1.4426950; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:18: warning: prefer 'std::numbers::log2e' to this literal, differs by '4.09e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: auto log2e = std::numbers::log2e; + + floatSink(log2(Euler)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:15: warning: prefer 'std::numbers::log2e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(std::numbers::log2e); + + floatSink(static_cast(log2(Euler))); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:15: warning: prefer 'std::numbers::log2e_v' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(std::numbers::log2e_v); + + floatSink(1.4426950); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:15: warning: prefer 'std::numbers::log2e' to this literal, differs by '4.09e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(std::numbers::log2e); + + floatSink(static_cast(1.4426950)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:15: warning: prefer 'std::numbers::log2e_v' to this literal, differs by '4.09e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(std::numbers::log2e_v); + + floatSink(log2(static_cast(Euler))); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:15: warning: prefer 'std::numbers::log2e_v' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(std::numbers::log2e_v); + + floatSink(static_cast(log2(static_cast(Euler)))); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:15: warning: prefer 'std::numbers::log2e_v' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(std::numbers::log2e_v); + + floatSink(static_cast(log2(static_cast(Euler)))); + + floatSink(static_cast(log2(static_cast(Euler)))); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:32: warning: prefer 'std::numbers::log2e_v' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(static_cast(std::numbers::log2e_v)); + + floatSink(1.4426950F); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:15: warning: prefer 'std::numbers::log2e_v' to this literal, differs by '1.93e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(std::numbers::log2e_v); + + floatSink(static_cast(1.4426950F)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:15: warning: prefer 'std::numbers::log2e' to this literal, differs by '1.93e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(std::numbers::log2e); + + floatSink(static_cast(1.4426950F)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:32: warning: prefer 'std::numbers::log2e_v' to this literal, differs by '1.93e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: floatSink(static_cast(std::numbers::log2e_v)); + + log10(exp(1)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log10e' to this formula [modernize-use-std-numbers] + // CHECK-MESSAGES-ALL: :[[@LINE-2]]:11: warning: prefer 'std::numbers::e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log10e; + + log10(Euler); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log10e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log10e; + + log10(bar::e); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log10e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log10e; + + auto log10e = .434294; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:19: warning: prefer 'std::numbers::log10e' to this literal, differs by '4.82e-07' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: auto log10e = std::numbers::log10e; + + auto egamma = 0.5772156 * 42; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:19: warning: prefer 'std::numbers::egamma' to this literal, differs by '6.49e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: auto egamma = std::numbers::egamma * 42; + + sink(InvPi); + + sink(1 / Pi); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::inv_pi' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::inv_pi); + + sink(1 / bar::sqrt(Pi)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::inv_sqrtpi' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::inv_sqrtpi); + + sink(1 / bar::sqrt(MY_PI)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::inv_sqrtpi' to this formula [modernize-use-std-numbers] + // CHECK-MESSAGES-ALL: :[[@LINE-2]]:24: warning: prefer 'std::numbers::pi' to this macro, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::inv_sqrtpi); + + log(2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::ln2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::ln2; + + log(10); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::ln10' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::ln10; + + bar::sqrt(2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2; + + sink(1 / bar::sqrt(3)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::inv_sqrt3' to this formula [modernize-use-std-numbers] + // CHECK-MESSAGES-ALL: :[[@LINE-2]]:14: warning: prefer 'std::numbers::sqrt3' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::inv_sqrt3); + + sink(INV_SQRT3); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::inv_sqrt3' to this macro [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::inv_sqrt3); + + sink(NOT_INV_SQRT3); + + const auto inv_sqrt3f = .577350269F; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:29: warning: prefer 'std::numbers::inv_sqrt3_v' to this literal, differs by '1.04e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: const auto inv_sqrt3f = std::numbers::inv_sqrt3_v; + + bar::sqrt(3); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt3' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt3; + + auto somePhi = 1.6180339; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:20: warning: prefer 'std::numbers::phi' to this literal, differs by '8.87e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: auto somePhi = std::numbers::phi; + + sink(Phi); + + sink((42 + bar::sqrt(5)) / 2); + + sink((1 + bar::sqrt(5)) / 2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::phi' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::phi); + + sink((bar::sqrt(5.0F) + 1) / 2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::phi_v' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::phi_v); +} + + + +template +void baz(){ + static constexpr T Pi = 3.1415926; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:29: warning: prefer 'std::numbers::pi' to this literal, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr T Pi = std::numbers::pi; + + static constexpr T Euler = 2.7182818; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:32: warning: prefer 'std::numbers::e' to this literal, differs by '2.85e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr T Euler = std::numbers::e; + + static constexpr T Phi = 1.6180339; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:30: warning: prefer 'std::numbers::phi' to this literal, differs by '8.87e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr T Phi = std::numbers::phi; + + static constexpr T PiCopy = Pi; + static constexpr T PiDefineFromMacro = MY_PI; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:44: warning: prefer 'std::numbers::pi' to this macro, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr T PiDefineFromMacro = std::numbers::pi; + + static constexpr T Pi2 = 3.14; + // CHECK-MESSAGES-IMPRECISE: :[[@LINE-1]]:30: warning: prefer 'std::numbers::pi' to this literal, differs by '1.59e-03' [modernize-use-std-numbers] + // CHECK-FIXES-IMPRECISE: static constexpr T Pi2 = std::numbers::pi; + static constexpr T Euler2 = 2.71; + // CHECK-MESSAGES-IMPRECISE: :[[@LINE-1]]:33: warning: prefer 'std::numbers::e' to this literal, differs by '8.28e-03' [modernize-use-std-numbers] + // CHECK-FIXES-IMPRECISE: static constexpr T Euler2 = std::numbers::e; + static constexpr T Phi2 = 1.61; + // CHECK-MESSAGES-IMPRECISE: :[[@LINE-1]]:31: warning: prefer 'std::numbers::phi' to this literal, differs by '8.03e-03' [modernize-use-std-numbers] + // CHECK-FIXES-IMPRECISE: static constexpr T Phi2 = std::numbers::phi; + + static constexpr T Pi3 = 3.1415926L; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:30: warning: prefer 'std::numbers::pi_v' to this literal, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr T Pi3 = std::numbers::pi_v; + + static constexpr T Euler3 = 2.7182818L; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:33: warning: prefer 'std::numbers::e_v' to this literal, differs by '2.85e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr T Euler3 = std::numbers::e_v; + + static constexpr T Phi3 = 1.6180339L; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:31: warning: prefer 'std::numbers::phi_v' to this literal, differs by '8.87e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: static constexpr T Phi3 = std::numbers::phi_v; + + static constexpr my_float Actually2MyFloat = 2; + bar::sqrt(Actually2MyFloat); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2_v' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2_v; + + constexpr static T One = 1; + constexpr static T Two = 2; + + bar::sqrt(2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2; + + bar::sqrt(Two); + + bar::sqrt(2.0); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2; + + T Not2 = 2; + Not2 = 42; + bar::sqrt(Not2); + + const T Actually2 = 2; + bar::sqrt(Actually2); + + exp(1); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::e; + + exp(One); + + exp(1.00000000000001); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::e; + + log2(exp(1)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log2e' to this formula [modernize-use-std-numbers] + // CHECK-MESSAGES-ALL: :[[@LINE-2]]:10: warning: prefer 'std::numbers::e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log2e; + + log2(Euler); + + log2(bar::e); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log2e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log2e; + + T log2e = 1.4426950; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:15: warning: prefer 'std::numbers::log2e' to this literal, differs by '4.09e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: T log2e = std::numbers::log2e; + + log10(exp(1)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log10e' to this formula [modernize-use-std-numbers] + // CHECK-MESSAGES-ALL: :[[@LINE-2]]:11: warning: prefer 'std::numbers::e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log10e; + + log10(Euler); + + log10(bar::e); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::log10e' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::log10e; + + T log10e = .434294; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:16: warning: prefer 'std::numbers::log10e' to this literal, differs by '4.82e-07' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: T log10e = std::numbers::log10e; + + T egamma = 0.5772156 * 42; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:16: warning: prefer 'std::numbers::egamma' to this literal, differs by '6.49e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: T egamma = std::numbers::egamma * 42; + + sink(1 / Pi); + + sink(1 / bar::sqrt(Pi)); + + sink(1 / bar::sqrt(MY_PI)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::inv_sqrtpi' to this formula [modernize-use-std-numbers] + // CHECK-MESSAGES-ALL: :[[@LINE-2]]:24: warning: prefer 'std::numbers::pi' to this macro, differs by '5.36e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::inv_sqrtpi); + + + log(2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::ln2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::ln2; + + log(10); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::ln10' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::ln10; + + bar::sqrt(2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt2' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt2; + + sink(1 / bar::sqrt(3)); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::inv_sqrt3' to this formula [modernize-use-std-numbers] + // CHECK-MESSAGES-ALL: :[[@LINE-2]]:14: warning: prefer 'std::numbers::sqrt3' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::inv_sqrt3); + + bar::sqrt(3); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:5: warning: prefer 'std::numbers::sqrt3' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: std::numbers::sqrt3; + + T phi = 1.6180339; + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:13: warning: prefer 'std::numbers::phi' to this literal, differs by '8.87e-08' [modernize-use-std-numbers] + // CHECK-FIXES-ALL: T phi = std::numbers::phi; + + sink((42 + bar::sqrt(5)) / 2); + + sink((1 + bar::sqrt(5)) / 2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::phi' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::phi); + + sink((bar::sqrt(5.0F) + 1) / 2); + // CHECK-MESSAGES-ALL: :[[@LINE-1]]:10: warning: prefer 'std::numbers::phi_v' to this formula [modernize-use-std-numbers] + // CHECK-FIXES-ALL: sink(std::numbers::phi_v); +} + +template +void foobar(){ + const T Two = 2; + bar::sqrt(Two); +} +void use_templates() { + foobar(); + foobar(); + + baz(); + baz(); +} + +#define BIG_MARCO \ + struct InvSqrt3 { \ + template static T get() { return 1 / bar::sqrt(3); } \ + } + +BIG_MARCO; + +void use_BIG_MACRO() { +InvSqrt3 f{}; +f.get(); +f.get(); +} diff --git a/clang-tools-extra/test/clang-tidy/infrastructure/Inputs/compilation-database/template.json b/clang-tools-extra/test/clang-tidy/infrastructure/Inputs/compilation-database/template.json index 74275d953727..53ee3fa7a98d 100644 --- a/clang-tools-extra/test/clang-tidy/infrastructure/Inputs/compilation-database/template.json +++ b/clang-tools-extra/test/clang-tidy/infrastructure/Inputs/compilation-database/template.json @@ -20,10 +20,15 @@ "file": "test_dir/b/c.cpp" }, { - "directory": "test_dir/b", - "command": "clang++ -I../include -o test.o ../b/d.cpp", + "directory": "test_dir/", + "command": "clang++ -o test.o ./b/d.cpp", "file": "test_dir/b/d.cpp" }, +{ + "directory": "test_dir/b", + "command": "clang++ -I../include -o test.o ../include.cpp", + "file": "test_dir/include.cpp" +}, { "directory": "test_dir/", "command": "clang++ -o test.o test_dir/b/not-exist.cpp", diff --git a/clang-tools-extra/test/clang-tidy/infrastructure/clang-tidy-run-with-database.cpp b/clang-tools-extra/test/clang-tidy/infrastructure/clang-tidy-run-with-database.cpp index f8c05a3f69e9..3c4e8494a4ae 100644 --- a/clang-tools-extra/test/clang-tidy/infrastructure/clang-tidy-run-with-database.cpp +++ b/clang-tools-extra/test/clang-tidy/infrastructure/clang-tidy-run-with-database.cpp @@ -5,8 +5,9 @@ // RUN: echo 'int *AB = 0;' > %T/compilation-database-test/a/b.cpp // RUN: echo 'int *BB = 0;' > %T/compilation-database-test/b/b.cpp // RUN: echo 'int *BC = 0;' > %T/compilation-database-test/b/c.cpp +// RUN: echo 'int *BD = 0;' > %T/compilation-database-test/b/d.cpp // RUN: echo 'int *HP = 0;' > %T/compilation-database-test/include/header.h -// RUN: echo '#include "header.h"' > %T/compilation-database-test/b/d.cpp +// RUN: echo '#include "header.h"' > %T/compilation-database-test/include.cpp // RUN: sed 's|test_dir|%/T/compilation-database-test|g' %S/Inputs/compilation-database/template.json > %T/compile_commands.json // Regression test: shouldn't crash. @@ -15,15 +16,17 @@ // CHECK-NOT-EXIST: unable to handle compilation // CHECK-NOT-EXIST: Found compiler error -// RUN: clang-tidy --checks=-*,modernize-use-nullptr -p %T %T/compilation-database-test/a/a.cpp %T/compilation-database-test/a/b.cpp %T/compilation-database-test/b/b.cpp %T/compilation-database-test/b/c.cpp %T/compilation-database-test/b/d.cpp -header-filter=.* -fix +// RUN: clang-tidy --checks=-*,modernize-use-nullptr -p %T %T/compilation-database-test/a/a.cpp %T/compilation-database-test/a/b.cpp %T/compilation-database-test/b/b.cpp %T/compilation-database-test/b/c.cpp %T/compilation-database-test/b/d.cpp %T/compilation-database-test/include.cpp -header-filter=.* -fix // RUN: FileCheck -input-file=%T/compilation-database-test/a/a.cpp %s -check-prefix=CHECK-FIX1 // RUN: FileCheck -input-file=%T/compilation-database-test/a/b.cpp %s -check-prefix=CHECK-FIX2 // RUN: FileCheck -input-file=%T/compilation-database-test/b/b.cpp %s -check-prefix=CHECK-FIX3 // RUN: FileCheck -input-file=%T/compilation-database-test/b/c.cpp %s -check-prefix=CHECK-FIX4 -// RUN: FileCheck -input-file=%T/compilation-database-test/include/header.h %s -check-prefix=CHECK-FIX5 +// RUN: FileCheck -input-file=%T/compilation-database-test/b/d.cpp %s -check-prefix=CHECK-FIX5 +// RUN: FileCheck -input-file=%T/compilation-database-test/include/header.h %s -check-prefix=CHECK-FIX6 // CHECK-FIX1: int *AA = nullptr; // CHECK-FIX2: int *AB = nullptr; // CHECK-FIX3: int *BB = nullptr; // CHECK-FIX4: int *BC = nullptr; -// CHECK-FIX5: int *HP = nullptr; +// CHECK-FIX5: int *BD = nullptr; +// CHECK-FIX6: int *HP = nullptr; diff --git a/clang/CMakeLists.txt b/clang/CMakeLists.txt index 9b52c58be41e..2ca6db02e587 100644 --- a/clang/CMakeLists.txt +++ b/clang/CMakeLists.txt @@ -290,8 +290,10 @@ endif() if(NOT DEFINED CLANG_VERSION_PATCHLEVEL) set(CLANG_VERSION_PATCHLEVEL ${LLVM_VERSION_PATCH}) endif() -# Unlike PACKAGE_VERSION, CLANG_VERSION does not include LLVM_VERSION_SUFFIX. -set(CLANG_VERSION "${CLANG_VERSION_MAJOR}.${CLANG_VERSION_MINOR}.${CLANG_VERSION_PATCHLEVEL}") +if(NOT DEFINED CLANG_VERSION_SUFFIX) + set(CLANG_VERSION_SUFFIX ${LLVM_VERSION_SUFFIX}) +endif() +set(CLANG_VERSION "${CLANG_VERSION_MAJOR}.${CLANG_VERSION_MINOR}.${CLANG_VERSION_PATCHLEVEL}${CLANG_VERSION_SUFFIX}") message(STATUS "Clang version: ${CLANG_VERSION}") # Configure the Version.inc file. @@ -650,6 +652,7 @@ if (CLANG_ENABLE_BOOTSTRAP) CLANG_VERSION_MAJOR CLANG_VERSION_MINOR CLANG_VERSION_PATCHLEVEL + CLANG_VERSION_SUFFIX CLANG_VENDOR LLVM_VERSION_SUFFIX LLVM_BINUTILS_INCDIR diff --git a/clang/docs/InternalsManual.rst b/clang/docs/InternalsManual.rst index f8e3da5f9736..05fadf5a0344 100644 --- a/clang/docs/InternalsManual.rst +++ b/clang/docs/InternalsManual.rst @@ -477,9 +477,8 @@ mode. Instead of formatting and printing out the diagnostics, this implementation just captures and remembers the diagnostics as they fly by. Then ``-verify`` compares the list of produced diagnostics to the list of expected ones. If they disagree, it prints out its own output. Full -documentation for the ``-verify`` mode can be found in the Clang API -documentation for `VerifyDiagnosticConsumer -`_. +documentation for the ``-verify`` mode can be found at +:ref:`verifying-diagnostics`. There are many other possible implementations of this interface, and this is why we prefer diagnostics to pass down rich structured information in @@ -3314,6 +3313,8 @@ Testing All functional changes to Clang should come with test coverage demonstrating the change in behavior. +.. _verifying-diagnostics: + Verifying Diagnostics ^^^^^^^^^^^^^^^^^^^^^ Clang ``-cc1`` supports the ``-verify`` command line option as a way to @@ -3375,7 +3376,7 @@ truncated text instead.) Here's an example of the most commonly used way to specify expected diagnostics: -.. code-block: c++ +.. code-block:: c++ int A = B; // expected-error {{use of undeclared identifier 'B'}} @@ -3385,7 +3386,7 @@ more readable, you can use slash-newline to separate out the diagnostics. Alternatively, it is possible to specify the line on which the diagnostic should appear by appending ``@`` to ``expected-``, for example: -.. code-block: c++ +.. code-block:: c++ #warning some text // expected-warning@10 {{some text}} @@ -3398,7 +3399,7 @@ header file, it may be beneficial to be able to declare the file in which the diagnostic will appear, rather than placing the ``expected-*`` directive in the actual file itself. This can be done using the following syntax: -.. code-block: c++ +.. code-block:: c++ // expected-error@path/include.h:15 {{error message}} @@ -3413,7 +3414,7 @@ diagnostic can instead be indicated by a marker of the form ``#``. Markers are specified by including them in a comment, and then referenced by appending the marker to the diagnostic with ``@#``, as with: -.. code-block: c++ +.. code-block:: c++ #warning some text // #1 // ... other code ... @@ -3428,14 +3429,14 @@ syntax is ``expected- {{diag text}}``, where ```` is one of integer. This allows the diagnostic to appear as many times as specified. For example: -.. code-block: c++ +.. code-block:: c++ void f(); // expected-note 2 {{previous declaration is here}} Where the diagnostic is expected to occur a minimum number of times, this can be specified by appending a ``+`` to the number. For example: -.. code-block: c++ +.. code-block:: c++ void f(); // expected-note 0+ {{previous declaration is here}} void g(); // expected-note 1+ {{previous declaration is here}} @@ -3445,13 +3446,13 @@ swallowed if it occurs, but will not generate an error if it does not occur. In the second example, the diagnostic must occur at least once. As a short-hand, "one or more" can be specified simply by ``+``. For example: -.. code-block: c++ +.. code-block:: c++ void g(); // expected-note + {{previous declaration is here}} A range can also be specified by ``-``. For example: -.. code-block: c++ +.. code-block:: c++ void f(); // expected-note 0-1 {{previous declaration is here}} @@ -3460,13 +3461,13 @@ In this example, the diagnostic may appear only once, if at all. Regex matching mode may be selected by appending ``-re`` to the diagnostic type and including regexes wrapped in double curly braces in the directive, such as: -.. code-block: c++ +.. code-block:: text expected-error-re {{format specifies type 'wchar_t **' (aka '{{.+}}')}} Examples matching error: "variable has incomplete type 'struct s'" -.. code-block: c++ +.. code-block:: c++ // expected-error {{variable has incomplete type 'struct s'}} // expected-error {{variable has incomplete type}} diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 8e01ef6cbb39..286405850900 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -2821,7 +2821,7 @@ Example output: The ``__builtin_dump_struct`` function is used to print the fields of a simple structure and their values for debugging purposes. The first argument of the -builtin should be a pointer to the struct to dump. The second argument ``f`` +builtin should be a pointer to a complete record type to dump. The second argument ``f`` should be some callable expression, and can be a function object or an overload set. The builtin calls ``f``, passing any further arguments ``args...`` followed by a ``printf``-compatible format string and the corresponding diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 683d0026bb34..89ea2f0930ce 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -651,6 +651,11 @@ Bug Fixes in This Version - Fixed false positive error emitted by clang when performing qualified name lookup and the current class instantiation has dependent bases. Fixes (`#13826 `_) +- Fix the name of the ifunc symbol emitted for multiversion functions declared with the + ``target_clones`` attribute. This addresses a linker error that would otherwise occur + when these functions are referenced from other TUs. +- Fixes compile error that double colon operator cannot resolve macro with parentheses. + Fixes (`#64467 `_) - Clang's ``-Wchar-subscripts`` no longer warns on chars whose values are known non-negative constants. Fixes (`#18763 `_) @@ -794,6 +799,9 @@ Bug Fixes to C++ Support Fixes: (`#68769 `_) +- Clang now rejects incomplete types for ``__builtin_dump_struct``. Fixes: + (`#63506 `_) + - Fixed a crash for C++98/03 while checking an ill-formed ``_Static_assert`` expression. Fixes: (`#72025 `_) diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 1800f584c7e1..121ed203829c 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -2024,6 +2024,14 @@ def BPFPreserveAccessIndex : InheritableAttr, let LangOpts = [COnly]; } +def BPFPreserveStaticOffset : InheritableAttr, + TargetSpecificAttr { + let Spellings = [Clang<"preserve_static_offset">]; + let Subjects = SubjectList<[Record], ErrorDiag>; + let Documentation = [BPFPreserveStaticOffsetDocs]; + let LangOpts = [COnly]; +} + def BTFDeclTag : InheritableAttr { let Spellings = [Clang<"btf_decl_tag">]; let Args = [StringArgument<"BTFDeclTag">]; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index b45ec6bbb8d3..bbe4de94cbab 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -2199,6 +2199,43 @@ preserving struct or union member access debuginfo indices of this struct or union, similar to clang ``__builtin_preserve_access_index()``. }]; } + +def BPFPreserveStaticOffsetDocs : Documentation { + let Category = DocCatFunction; + let Content = [{ +Clang supports the ``__attribute__((preserve_static_offset))`` +attribute for the BPF target. This attribute may be attached to a +struct or union declaration. Reading or writing fields of types having +such annotation is guaranteed to generate LDX/ST/STX instruction with +offset corresponding to the field. + +For example: + +.. code-block:: c + + struct foo { + int a; + int b; + }; + + struct bar { + int a; + struct foo b; + } __attribute__((preserve_static_offset)); + + void buz(struct bar *g) { + g->b.a = 42; + } + +The assignment to ``g``'s field would produce an ST instruction with +offset 8: ``*(u32)(r1 + 8) = 42;``. + +Without this attribute generated instructions might be different, +depending on optimizations behavior. E.g. the example above could be +rewritten as ``r1 += 8; *(u32)(r1 + 0) = 42;``. + }]; +} + def BTFDeclTagDocs : Documentation { let Category = DocCatFunction; let Content = [{ @@ -2515,6 +2552,13 @@ example, the following will emit 4 versions of the function: __attribute__((target_clones("arch=atom,avx2","arch=ivybridge","default"))) void foo() {} +For targets that support the GNU indirect function (IFUNC) feature, dispatch +is performed by emitting an indirect function that is resolved to the appropriate +target clone at load time. The indirect function is given the name the +multiversioned function would have if it had been declared without the attribute. +For backward compatibility with earlier Clang releases, a function alias with an +``.ifunc`` suffix is also emitted. The ``.ifunc`` suffixed symbol is a deprecated +feature and support for it may be removed in the future. }]; } diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index 675645cd534e..0acb5ae134ea 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -28,12 +28,8 @@ CODEGENOPT(Name, Bits, Default) #endif CODEGENOPT(DisableIntegratedAS, 1, 0) ///< -no-integrated-as -ENUM_CODEGENOPT(CompressDebugSections, llvm::DebugCompressionType, 2, - llvm::DebugCompressionType::None) CODEGENOPT(RelaxELFRelocations, 1, 1) ///< -Wa,-mrelax-relocations={yes,no} CODEGENOPT(AsmVerbose , 1, 0) ///< -dA, -fverbose-asm. -CODEGENOPT(Dwarf64 , 1, 0) ///< -gdwarf64. -CODEGENOPT(Dwarf32 , 1, 1) ///< -gdwarf32. CODEGENOPT(PreserveAsmComments, 1, 1) ///< -dA, -fno-preserve-as-comments. CODEGENOPT(AssumeSaneOperatorNew , 1, 1) ///< implicit __attribute__((malloc)) operator new CODEGENOPT(AssumeUniqueVTables , 1, 1) ///< Assume a class has only one vtable. @@ -73,10 +69,6 @@ CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug information for the new CODEGENOPT(DisableRedZone , 1, 0) ///< Set when -mno-red-zone is enabled. CODEGENOPT(EmitCallSiteInfo, 1, 0) ///< Emit call site info only in the case of ///< '-g' + 'O>0' level. -CODEGENOPT(EnableDIPreservationVerify, 1, 0) ///< Enable di preservation verify - ///< each (it means check - ///< the original debug info - ///< metadata preservation). CODEGENOPT(IndirectTlsSegRefs, 1, 0) ///< Set when -mno-tls-direct-seg-refs ///< is specified. CODEGENOPT(DisableTailCalls , 1, 0) ///< Do not emit tail calls. @@ -113,16 +105,10 @@ CODEGENOPT(IndirectBranchCSPrefix, 1, 0) ///< if -mindirect-branch-cs-prefix CODEGENOPT(XRayInstrumentFunctions , 1, 0) ///< Set when -fxray-instrument is ///< enabled. CODEGENOPT(StackSizeSection , 1, 0) ///< Set when -fstack-size-section is enabled. -CODEGENOPT(ForceDwarfFrameSection , 1, 0) ///< Set when -fforce-dwarf-frame is - ///< enabled. ///< Set when -femit-compact-unwind-non-canonical is enabled. CODEGENOPT(EmitCompactUnwindNonCanonical, 1, 0) -///< Set when -femit-dwarf-unwind is passed. -ENUM_CODEGENOPT(EmitDwarfUnwind, llvm::EmitDwarfUnwindType, 2, - llvm::EmitDwarfUnwindType::Default) - ///< Set when -fxray-always-emit-customevents is enabled. CODEGENOPT(XRayAlwaysEmitCustomEvents , 1, 0) @@ -178,8 +164,6 @@ CODEGENOPT(IncrementalLinkerCompatible, 1, 0) ///< Emit an object file which can CODEGENOPT(MergeAllConstants , 1, 1) ///< Merge identical constants. CODEGENOPT(MergeFunctions , 1, 0) ///< Set when -fmerge-functions is enabled. CODEGENOPT(NoCommon , 1, 0) ///< Set when -fno-common or C++ is enabled. -CODEGENOPT(NoDwarfDirectoryAsm , 1, 0) ///< Set when -fno-dwarf-directory-asm is - ///< enabled. CODEGENOPT(NoExecStack , 1, 0) ///< Set when -Wa,--noexecstack is enabled. CODEGENOPT(FatalWarnings , 1, 0) ///< Set when -Wa,--fatal-warnings is ///< enabled. @@ -187,8 +171,6 @@ CODEGENOPT(NoWarn , 1, 0) ///< Set when -Wa,--no-warn is enabled. CODEGENOPT(NoTypeCheck , 1, 0) ///< Set when -Wa,--no-type-check is enabled. CODEGENOPT(MisExpect , 1, 0) ///< Set when -Wmisexpect is enabled CODEGENOPT(EnableSegmentedStacks , 1, 0) ///< Set when -fsplit-stack is enabled. -CODEGENOPT(NoInlineLineTables, 1, 0) ///< Whether debug info should contain - ///< inline line tables. CODEGENOPT(StackClashProtector, 1, 0) ///< Set when -fstack-clash-protection is enabled. CODEGENOPT(NoImplicitFloat , 1, 0) ///< Set when -mno-implicit-float is enabled. CODEGENOPT(NullPointerIsValid , 1, 0) ///< Assume Null pointer deference is defined. @@ -341,37 +323,6 @@ VALUE_CODEGENOPT(StackProbeSize , 32, 4096) ///< Overrides default stack ///< probe size, even if 0. VALUE_CODEGENOPT(WarnStackSize , 32, UINT_MAX) ///< Set via -fwarn-stack-size. CODEGENOPT(NoStackArgProbe, 1, 0) ///< Set when -mno-stack-arg-probe is used -CODEGENOPT(DebugStrictDwarf, 1, 1) ///< Whether or not to use strict DWARF info. - -/// Control the Assignment Tracking debug info feature. -ENUM_CODEGENOPT(AssignmentTrackingMode, AssignmentTrackingOpts, 2, AssignmentTrackingOpts::Disabled) - -CODEGENOPT(DebugColumnInfo, 1, 0) ///< Whether or not to use column information - ///< in debug info. - -CODEGENOPT(DebugTypeExtRefs, 1, 0) ///< Whether or not debug info should contain - ///< external references to a PCH or module. - -CODEGENOPT(DebugExplicitImport, 1, 0) ///< Whether or not debug info should - ///< contain explicit imports for - ///< anonymous namespaces - -/// Set debug info source file hashing algorithm. -ENUM_CODEGENOPT(DebugSrcHash, DebugSrcHashKind, 2, DSH_MD5) - -CODEGENOPT(SplitDwarfInlining, 1, 1) ///< Whether to include inlining info in the - ///< skeleton CU to allow for symbolication - ///< of inline stack frames without .dwo files. -CODEGENOPT(DebugFwdTemplateParams, 1, 0) ///< Whether to emit complete - ///< template parameter descriptions in - ///< forward declarations (versus just - ///< including them in the name). -ENUM_CODEGENOPT(DebugSimpleTemplateNames, llvm::codegenoptions::DebugTemplateNamesKind, 2, llvm::codegenoptions::DebugTemplateNamesKind::Full) ///< Whether to emit template parameters - ///< in the textual names of template - ///< specializations. - ///< Implies DebugFwdTemplateNames to - ///< allow decorated names to be - ///< reconstructed when needed. CODEGENOPT(EmitLLVMUseLists, 1, 0) ///< Control whether to serialize use-lists. CODEGENOPT(WholeProgramVTables, 1, 0) ///< Whether to apply whole-program @@ -395,30 +346,6 @@ VALUE_CODEGENOPT(SmallDataLimit, 32, 0) /// The lower bound for a buffer to be considered for stack protection. VALUE_CODEGENOPT(SSPBufferSize, 32, 0) -/// The kind of generated debug info. -ENUM_CODEGENOPT(DebugInfo, llvm::codegenoptions::DebugInfoKind, 4, llvm::codegenoptions::NoDebugInfo) - -/// Whether to generate macro debug info. -CODEGENOPT(MacroDebugInfo, 1, 0) - -/// Tune the debug info for this debugger. -ENUM_CODEGENOPT(DebuggerTuning, llvm::DebuggerKind, 3, - llvm::DebuggerKind::Default) - -/// Dwarf version. Version zero indicates to LLVM that no DWARF should be -/// emitted. -VALUE_CODEGENOPT(DwarfVersion, 3, 0) - -/// Whether we should emit CodeView debug information. It's possible to emit -/// CodeView and DWARF into the same object. -CODEGENOPT(EmitCodeView, 1, 0) - -/// Whether to emit the .debug$H section containing hashes of CodeView types. -CODEGENOPT(CodeViewGHash, 1, 0) - -/// Whether to emit the compiler path and command line into the CodeView debug information. -CODEGENOPT(CodeViewCommandLine, 1, 0) - /// The kind of inlining to perform. ENUM_CODEGENOPT(Inlining, InliningMethod, 2, NormalInlining) @@ -451,26 +378,14 @@ CODEGENOPT(DirectAccessExternalData, 1, 0) /// paths that reach the end of a function without executing a required return. CODEGENOPT(StrictReturn, 1, 1) -/// Whether emit extra debug info for sample pgo profile collection. -CODEGENOPT(DebugInfoForProfiling, 1, 0) - /// Whether emit pseudo probes for sample pgo profile collection. CODEGENOPT(PseudoProbeForProfiling, 1, 0) /// Whether 3-component vector type is preserved. CODEGENOPT(PreserveVec3Type, 1, 0) -/// Whether to emit .debug_gnu_pubnames section instead of .debug_pubnames. -CODEGENOPT(DebugNameTable, 2, 0) - -/// Whether to use DWARF base address specifiers in .debug_ranges. -CODEGENOPT(DebugRangesBaseAddress, 1, 0) - CODEGENOPT(NoPLT, 1, 0) -/// Whether to embed source in DWARF debug line section. -CODEGENOPT(EmbedSource, 1, 0) - /// Whether to emit all vtables CODEGENOPT(ForceEmitVTables, 1, 0) @@ -515,6 +430,9 @@ ENUM_CODEGENOPT(ZeroCallUsedRegs, llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind, /// non-deleting destructors. (No effect on Microsoft ABI.) CODEGENOPT(CtorDtorReturnThis, 1, 0) +/// FIXME: Make DebugOptions its own top-level .def file. +#include "DebugOptions.def" + #undef CODEGENOPT #undef ENUM_CODEGENOPT #undef VALUE_CODEGENOPT diff --git a/clang/include/clang/Basic/CodeGenOptions.h b/clang/include/clang/Basic/CodeGenOptions.h index b202d01af0ed..6952b48e898a 100644 --- a/clang/include/clang/Basic/CodeGenOptions.h +++ b/clang/include/clang/Basic/CodeGenOptions.h @@ -530,6 +530,10 @@ public: return SanitizeBinaryMetadataCovered || SanitizeBinaryMetadataAtomics || SanitizeBinaryMetadataUAR; } + + /// Reset all of the options that are not considered when building a + /// module. + void resetNonModularOptions(StringRef ModuleFormat); }; } // end namespace clang diff --git a/clang/include/clang/Basic/DebugOptions.def b/clang/include/clang/Basic/DebugOptions.def new file mode 100644 index 000000000000..7cd3edf08a17 --- /dev/null +++ b/clang/include/clang/Basic/DebugOptions.def @@ -0,0 +1,146 @@ +//===--- DebugOptions.def - Debug option database ----------------- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines debug-specific codegen options. Users of this file +// must define the CODEGENOPT macro to make use of this information. +// Optionally, the user may also define DEBUGOPT (for flags), ENUM_DEBUGOPT (for +// options that have enumeration type), and VALUE_DEBUGOPT (is a debug option +// that describes a value rather than a flag). +// +// BENIGN_ variants of the macros are used to describe options that do not +// affect the generated PCM. +// +//===----------------------------------------------------------------------===// +#ifndef DEBUGOPT +#define DEBUGOPT(Name, Bits, Default) \ +CODEGENOPT(Name, Bits, Default) +#endif + +#ifndef VALUE_DEBUGOPT +# define VALUE_DEBUGOPT(Name, Bits, Default) \ +VALUE_CODEGENOPT(Name, Bits, Default) +#endif + +#ifndef ENUM_DEBUGOPT +# define ENUM_DEBUGOPT(Name, Type, Bits, Default) \ +ENUM_CODEGENOPT(Name, Type, Bits, Default) +#endif + +#ifndef BENIGN_DEBUGOPT +#define BENIGN_DEBUGOPT(Name, Bits, Default) \ +DEBUGOPT(Name, Bits, Default) +#endif + +#ifndef BENIGN_VALUE_DEBUGOPT +# define BENIGN_VALUE_DEBUGOPT(Name, Bits, Default) \ +VALUE_DEBUGOPT(Name, Bits, Default) +#endif + +#ifndef BENIGN_ENUM_DEBUGOPT +# define BENIGN_ENUM_DEBUGOPT(Name, Type, Bits, Default) \ +ENUM_DEBUGOPT(Name, Type, Bits, Default) +#endif + +BENIGN_ENUM_DEBUGOPT(CompressDebugSections, llvm::DebugCompressionType, 2, + llvm::DebugCompressionType::None) +DEBUGOPT(Dwarf64, 1, 0) ///< -gdwarf64. +BENIGN_DEBUGOPT(EnableDIPreservationVerify, 1, 0) ///< Enable di preservation + ///< verify each (it means + ///< check the original debug + ///< info metadata + ///< preservation). +BENIGN_DEBUGOPT(ForceDwarfFrameSection , 1, 0) ///< Set when -fforce-dwarf-frame + ///< is enabled. + +///< Set when -femit-dwarf-unwind is passed. +BENIGN_ENUM_DEBUGOPT(EmitDwarfUnwind, llvm::EmitDwarfUnwindType, 2, + llvm::EmitDwarfUnwindType::Default) + +BENIGN_DEBUGOPT(NoDwarfDirectoryAsm , 1, 0) ///< Set when -fno-dwarf-directory-asm + ///< is enabled. + +BENIGN_DEBUGOPT(NoInlineLineTables, 1, 0) ///< Whether debug info should contain + ///< inline line tables. + +DEBUGOPT(DebugStrictDwarf, 1, 1) ///< Whether or not to use strict DWARF info. + +/// Control the Assignment Tracking debug info feature. +BENIGN_ENUM_DEBUGOPT(AssignmentTrackingMode, AssignmentTrackingOpts, 2, + AssignmentTrackingOpts::Disabled) + +DEBUGOPT(DebugColumnInfo, 1, 0) ///< Whether or not to use column information + ///< in debug info. + +DEBUGOPT(DebugTypeExtRefs, 1, 0) ///< Whether or not debug info should contain + ///< external references to a PCH or module. + +DEBUGOPT(DebugExplicitImport, 1, 0) ///< Whether or not debug info should + ///< contain explicit imports for + ///< anonymous namespaces + +/// Set debug info source file hashing algorithm. +ENUM_DEBUGOPT(DebugSrcHash, DebugSrcHashKind, 2, DSH_MD5) + +DEBUGOPT(SplitDwarfInlining, 1, 1) ///< Whether to include inlining info in the + ///< skeleton CU to allow for symbolication + ///< of inline stack frames without .dwo files. +DEBUGOPT(DebugFwdTemplateParams, 1, 0) ///< Whether to emit complete + ///< template parameter descriptions in + ///< forward declarations (versus just + ///< including them in the name). +ENUM_DEBUGOPT(DebugSimpleTemplateNames, + llvm::codegenoptions::DebugTemplateNamesKind, 2, + llvm::codegenoptions::DebugTemplateNamesKind::Full) + ///< Whether to emit template parameters in the textual names of + ///< template specializations. + ///< Implies DebugFwdTemplateNames to allow decorated names to be + ///< reconstructed when needed. + +/// The kind of generated debug info. +ENUM_DEBUGOPT(DebugInfo, llvm::codegenoptions::DebugInfoKind, 4, + llvm::codegenoptions::NoDebugInfo) + +/// Whether to generate macro debug info. +DEBUGOPT(MacroDebugInfo, 1, 0) + +/// Tune the debug info for this debugger. +ENUM_DEBUGOPT(DebuggerTuning, llvm::DebuggerKind, 3, + llvm::DebuggerKind::Default) + +/// Dwarf version. Version zero indicates to LLVM that no DWARF should be +/// emitted. +VALUE_DEBUGOPT(DwarfVersion, 3, 0) + +/// Whether we should emit CodeView debug information. It's possible to emit +/// CodeView and DWARF into the same object. +DEBUGOPT(EmitCodeView, 1, 0) + +/// Whether to emit the .debug$H section containing hashes of CodeView types. +DEBUGOPT(CodeViewGHash, 1, 0) + +/// Whether to emit the compiler path and command line into the CodeView debug information. +DEBUGOPT(CodeViewCommandLine, 1, 0) + +/// Whether emit extra debug info for sample pgo profile collection. +DEBUGOPT(DebugInfoForProfiling, 1, 0) + +/// Whether to emit .debug_gnu_pubnames section instead of .debug_pubnames. +DEBUGOPT(DebugNameTable, 2, 0) + +/// Whether to use DWARF base address specifiers in .debug_ranges. +DEBUGOPT(DebugRangesBaseAddress, 1, 0) + +/// Whether to embed source in DWARF debug line section. +DEBUGOPT(EmbedSource, 1, 0) + +#undef DEBUGOPT +#undef ENUM_DEBUGOPT +#undef VALUE_DEBUGOPT +#undef BENIGN_DEBUGOPT +#undef BENIGN_ENUM_DEBUGOPT +#undef BENIGN_VALUE_DEBUGOPT diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index 21fe6066d587..e0e199e0d730 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -1362,7 +1362,7 @@ def warn_pragma_acc_unimplemented_clause_parsing : Warning<"OpenACC clause parsing not yet implemented">, InGroup; def err_acc_invalid_directive - : Error<"invalid OpenACC directive '%select{%1|%1 %2}0'">; + : Error<"invalid OpenACC directive %select{%1|'%1 %2'}0">; def err_acc_missing_directive : Error<"expected OpenACC directive">; def err_acc_invalid_open_paren : Error<"expected clause-list or newline in OpenACC directive">; diff --git a/clang/include/clang/Basic/FileEntry.h b/clang/include/clang/Basic/FileEntry.h index bc6546373548..6351aeae92e2 100644 --- a/clang/include/clang/Basic/FileEntry.h +++ b/clang/include/clang/Basic/FileEntry.h @@ -394,6 +394,7 @@ class FileEntry { public: ~FileEntry(); + LLVM_DEPRECATED("Use FileEntryRef::getName() instead.", "") StringRef getName() const { return LastRef->getName(); } StringRef tryGetRealPathName() const { return RealPathName; } diff --git a/clang/include/clang/Basic/OpenACCKinds.h b/clang/include/clang/Basic/OpenACCKinds.h index 1a5bf7e0e831..449a75638b43 100644 --- a/clang/include/clang/Basic/OpenACCKinds.h +++ b/clang/include/clang/Basic/OpenACCKinds.h @@ -34,7 +34,7 @@ enum class OpenACCDirectiveKind { // Misc. Loop, - // FIXME: 'cache' + Cache, // Combined Constructs. ParallelLoop, diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 34dbfff6c4c8..fcff6fe35b7b 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -319,11 +319,37 @@ let TargetGuard = "sme2" in { // Spill and fill of ZT0 // let TargetGuard = "sme2" in { - def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>; + def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA], [ImmCheck<0, ImmCheck0_0>]>; def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>; +} // // Zero ZT0 // +let TargetGuard = "sme2" in { def SVZERO_ZT : Inst<"svzero_zt", "vi", "", MergeNone, "aarch64_sme_zero_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA], [ImmCheck<0, ImmCheck0_0>]>; } + +// +// lookup table expand four contiguous registers +// +let TargetGuard = "sme2" in { + def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; + def SVLUTI4_LANE_ZT_X4 : Inst<"svluti4_lane_zt_{d}_x4", "4.di[i", "sUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_1>]>; +} + +// +// lookup table expand one register +// +let TargetGuard = "sme2" in { + def SVLUTI2_LANE_ZT : Inst<"svluti2_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>; + def SVLUTI4_LANE_ZT : Inst<"svluti4_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; +} + +// +// lookup table expand two contiguous registers +// +let TargetGuard = "sme2" in { + def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; + def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; +} diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index 3f69a3df9e61..896c6f6e8033 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -1925,8 +1925,6 @@ def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", MergeNone, "aarch64_sv let TargetGuard = "sve2p1" in { def SVFCLAMP : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone, "aarch64_sve_fclamp", [], []>; -def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, "aarch64_sve_ptrue_{d}", [IsOverloadNone], []>; -def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "", [IsOverloadNone]>; def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>; def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>; @@ -2045,6 +2043,12 @@ def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, "aarch64_sv defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">; } +let TargetGuard = "sve2p1|sme2" in { + //FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when available + def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, "aarch64_sve_ptrue_{d}", [IsOverloadNone, IsStreamingCompatible], []>; + + def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "", [IsOverloadNone, IsStreamingCompatible]>; +} let TargetGuard = "sve2p1,b16b16" in { defm SVMUL_BF : SInstZPZZ<"svmul", "b", "aarch64_sve_fmul", "aarch64_sve_fmul_u">; @@ -2164,3 +2168,63 @@ let TargetGuard = "sve2p1" in { defm SVPMOV_TO_VEC_LANE_S : PMOV_TO_VEC<"svpmov", "iUi", "aarch64_sve_pmov_to_vector_lane", [], ImmCheck1_3>; defm SVPMOV_TO_VEC_LANE_D : PMOV_TO_VEC<"svpmov", "lUl", "aarch64_sve_pmov_to_vector_lane" ,[], ImmCheck1_7>; } + +// +// Multi-vector convert to/from floating-point. +// +let TargetGuard = "sme2" in { + def SVCVT_F16_X2 : SInst<"svcvt_f16[_f32_x2]", "e2", "f", MergeNone, "aarch64_sve_fcvt_x2", [IsStreaming],[]>; + def SVCVT_BF16_X2 : SInst<"svcvt_bf16[_f32_x2]", "$2", "f", MergeNone, "aarch64_sve_bfcvt_x2", [IsOverloadNone, IsStreaming],[]>; + + def SVCVT_F32_U32_X2 : SInst<"svcvt_{d}[_u32_x2]", "2.d2.u", "f", MergeNone, "aarch64_sve_fcvtu_x2", [IsStreaming], []>; + def SVCVT_U32_F32_X2 : SInst<"svcvt_u32[_{d}_x2]", "2.u2.d", "f", MergeNone, "aarch64_sve_ucvtf_x2", [IsStreaming], []>; + def SVCVT_F32_S32_X2 : SInst<"svcvt_{d}[_s32_x2]", "2.d2.x", "f", MergeNone, "aarch64_sve_fcvts_x2", [IsStreaming], []>; + def SVCVT_S32_F32_X2 : SInst<"svcvt_s32[_{d}_x2]", "2.x2.d", "f", MergeNone, "aarch64_sve_scvtf_x2", [IsStreaming], []>; + + def SVCVT_F32_U32_X4 : SInst<"svcvt_{d}[_u32_x4]", "4.d4.u", "f", MergeNone, "aarch64_sve_fcvtu_x4", [IsStreaming], []>; + def SVCVT_U32_F32_X4 : SInst<"svcvt_u32[_{d}_x4]", "4.u4.d", "f", MergeNone, "aarch64_sve_ucvtf_x4", [IsStreaming], []>; + def SVCVT_F32_S32_X4 : SInst<"svcvt_{d}[_s32_x4]", "4.d4.x", "f", MergeNone, "aarch64_sve_fcvts_x4", [IsStreaming], []>; + def SVCVT_S32_F32_X4 : SInst<"svcvt_s32[_{d}_x4]", "4.x4.d", "f", MergeNone, "aarch64_sve_scvtf_x4", [IsStreaming], []>; +} + +// +// Multi-vector floating-point convert from single-precision to interleaved half-precision/BFloat16 +// +let TargetGuard = "sme2" in { + def SVCVTN_F16_X2 : SInst<"svcvtn_f16[_f32_x2]", "e2", "f", MergeNone, "aarch64_sve_fcvtn_x2", [IsStreaming],[]>; + def SVCVTN_BF16_X2 : SInst<"svcvtn_bf16[_f32_x2]", "$2", "f", MergeNone, "aarch64_sve_bfcvtn_x2", [IsOverloadNone, IsStreaming],[]>; +} + +// +// Multi-vector saturating extract narrow +// +let TargetGuard = "sme2" in { + def SVQCVT_S16_S32_X2 : SInst<"svqcvt_s16[_{d}_x2]", "h2.d", "i", MergeNone, "aarch64_sve_sqcvt_x2", [IsStreaming], []>; + def SVQCVT_U16_U32_X2 : SInst<"svqcvt_u16[_{d}_x2]", "e2.d", "Ui", MergeNone, "aarch64_sve_uqcvt_x2", [IsStreaming], []>; + def SVQCVT_U16_S32_X2 : SInst<"svqcvt_u16[_{d}_x2]", "e2.d", "i", MergeNone, "aarch64_sve_sqcvtu_x2", [IsStreaming], []>; + + def SVQCVT_S8_S32_X4 : SInst<"svqcvt_s8[_{d}_x4]", "q4.d", "i", MergeNone, "aarch64_sve_sqcvt_x4", [IsStreaming], []>; + def SVQCVT_U8_U32_X4 : SInst<"svqcvt_u8[_{d}_x4]", "b4.d", "Ui", MergeNone, "aarch64_sve_uqcvt_x4", [IsStreaming], []>; + def SVQCVT_U8_S32_X4 : SInst<"svqcvt_u8[_{d}_x4]", "b4.d", "i", MergeNone, "aarch64_sve_sqcvtu_x4", [IsStreaming], []>; + + def SVQCVT_S16_S64_X4 : SInst<"svqcvt_s16[_{d}_x4]", "q4.d", "l", MergeNone, "aarch64_sve_sqcvt_x4", [IsStreaming], []>; + def SVQCVT_U16_U64_X4 : SInst<"svqcvt_u16[_{d}_x4]", "b4.d", "Ul", MergeNone, "aarch64_sve_uqcvt_x4", [IsStreaming], []>; + def SVQCVT_U16_S64_X4 : SInst<"svqcvt_u16[_{d}_x4]", "b4.d", "l", MergeNone, "aarch64_sve_sqcvtu_x4", [IsStreaming], []>; +} + +// +// Multi-vector saturating extract narrow and interleave +// +let TargetGuard = "sme2" in { + def SVQCVTN_S16_S32_X2 : SInst<"svqcvtn_s16[_{d}_x2]", "h2.d", "i", MergeNone, "aarch64_sve_sqcvtn_x2", [IsStreamingCompatible], []>; + def SVQCVTN_U16_U32_X2 : SInst<"svqcvtn_u16[_{d}_x2]", "e2.d", "Ui", MergeNone, "aarch64_sve_uqcvtn_x2", [IsStreamingCompatible], []>; + def SVQCVTN_U16_S32_X2 : SInst<"svqcvtn_u16[_{d}_x2]", "e2.d", "i", MergeNone, "aarch64_sve_sqcvtun_x2", [IsStreamingCompatible], []>; + + def SVQCVTN_S8_S32_X4 : SInst<"svqcvtn_s8[_{d}_x4]", "q4.d", "i", MergeNone, "aarch64_sve_sqcvtn_x4", [IsStreaming], []>; + def SVQCVTN_U8_U32_X4 : SInst<"svqcvtn_u8[_{d}_x4]", "b4.d", "Ui", MergeNone, "aarch64_sve_uqcvtn_x4", [IsStreaming], []>; + def SVQCVTN_U8_S32_X4 : SInst<"svqcvtn_u8[_{d}_x4]", "b4.d", "i", MergeNone, "aarch64_sve_sqcvtun_x4", [IsStreaming], []>; + + def SVQCVTN_S16_S64_X4 : SInst<"svqcvtn_s16[_{d}_x4]", "q4.d", "l", MergeNone, "aarch64_sve_sqcvtn_x4", [IsStreaming], []>; + def SVQCVTN_U16_U64_X4 : SInst<"svqcvtn_u16[_{d}_x4]", "b4.d", "Ul", MergeNone, "aarch64_sve_uqcvtn_x4", [IsStreaming], []>; + def SVQCVTN_U16_S64_X4 : SInst<"svqcvtn_u16[_{d}_x4]", "b4.d", "l", MergeNone, "aarch64_sve_sqcvtun_x4", [IsStreaming], []>; +} diff --git a/clang/include/clang/Basic/arm_sve_sme_incl.td b/clang/include/clang/Basic/arm_sve_sme_incl.td index 21dac067ab66..040ce95a57de 100644 --- a/clang/include/clang/Basic/arm_sve_sme_incl.td +++ b/clang/include/clang/Basic/arm_sve_sme_incl.td @@ -93,6 +93,7 @@ // m: uint32_t // n: uint64_t +// [: svuint8_t // t: svint32_t // z: svuint32_t // g: svuint64_t diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 1d04e4f6e7e6..0eec2b352637 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -994,7 +994,7 @@ def all__load : Flag<["-"], "all_load">; def allowable__client : Separate<["-"], "allowable_client">; def ansi : Flag<["-", "--"], "ansi">, Group; def arch__errors__fatal : Flag<["-"], "arch_errors_fatal">; -def arch : Separate<["-"], "arch">, Flags<[NoXarchOption]>; +def arch : Separate<["-"], "arch">, Flags<[NoXarchOption,TargetSpecific]>; def arch__only : Separate<["-"], "arch_only">; def autocomplete : Joined<["--"], "autocomplete=">; def bind__at__load : Flag<["-"], "bind_at_load">; @@ -6344,9 +6344,6 @@ defm stack_arrays : BoolOptionWithoutMarshalling<"f", "stack-arrays", defm loop_versioning : BoolOptionWithoutMarshalling<"f", "version-loops-for-stride", PosFlag, NegFlag>; -defm alias_analysis : BoolOptionWithoutMarshalling<"f", "alias-analysis", - PosFlag, - NegFlag>; } // let Visibility = [FC1Option, FlangOption] def J : JoinedOrSeparate<["-"], "J">, diff --git a/clang/include/clang/IndexSerialization/SerializablePathCollection.h b/clang/include/clang/IndexSerialization/SerializablePathCollection.h index 06948db6fc95..6337a8119668 100644 --- a/clang/include/clang/IndexSerialization/SerializablePathCollection.h +++ b/clang/include/clang/IndexSerialization/SerializablePathCollection.h @@ -110,7 +110,7 @@ public: /// Stores path to \p FE if it hasn't been stored yet. /// \returns index to array exposed by getPathsBuffer(). - size_t tryStoreFilePath(const clang::FileEntry &FE); + size_t tryStoreFilePath(FileEntryRef FE); private: /// Stores \p Path if it is non-empty. diff --git a/clang/include/clang/Lex/PPCallbacks.h b/clang/include/clang/Lex/PPCallbacks.h index 94f96cf9c512..e3942af7be28 100644 --- a/clang/include/clang/Lex/PPCallbacks.h +++ b/clang/include/clang/Lex/PPCallbacks.h @@ -22,11 +22,11 @@ #include "llvm/ADT/StringRef.h" namespace clang { - class Token; - class IdentifierInfo; - class MacroDefinition; - class MacroDirective; - class MacroArgs; +class Token; +class IdentifierInfo; +class MacroDefinition; +class MacroDirective; +class MacroArgs; /// This interface provides a way to observe the actions of the /// preprocessor as it does its thing. diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h index ca29ce46873e..32d0b76c35b0 100644 --- a/clang/include/clang/Parse/Parser.h +++ b/clang/include/clang/Parse/Parser.h @@ -3538,7 +3538,12 @@ public: private: void ParseOpenACCDirective(); - ExprResult ParseOpenACCRoutineName(); + /// Helper that parses an ID Expression based on the language options. + ExprResult ParseOpenACCIDExpression(); + /// Parses the variable list for the `cache` construct. + void ParseOpenACCCacheVarList(); + /// Parses a single variable in a variable list for the 'cache' construct. + bool ParseOpenACCCacheVar(); private: //===--------------------------------------------------------------------===// diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index e745c01ae0ae..26f4e38a46e8 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -13841,6 +13841,8 @@ private: CallExpr *TheCall); bool CheckMVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall); bool CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall); + bool ParseSVEImmChecks(CallExpr *TheCall, + SmallVector, 3> &ImmChecks); bool CheckCDEBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, CallExpr *TheCall); bool CheckARMCoprocessorImmediate(const TargetInfo &TI, const Expr *CoprocArg, diff --git a/clang/include/module.modulemap b/clang/include/module.modulemap index 7dbb7cf02b4f..52395ee9b0fc 100644 --- a/clang/include/module.modulemap +++ b/clang/include/module.modulemap @@ -68,6 +68,7 @@ module Clang_Basic { textual header "clang/Basic/BuiltinsX86_64.def" textual header "clang/Basic/BuiltinsXCore.def" textual header "clang/Basic/CodeGenOptions.def" + textual header "clang/Basic/DebugOptions.def" textual header "clang/Basic/DiagnosticOptions.def" textual header "clang/Basic/Features.def" textual header "clang/Basic/FPOptions.def" diff --git a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp index 042402a129d1..b98037b73645 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp @@ -300,9 +300,12 @@ static void insertIfFunction(const Decl &D, } static MemberExpr *getMemberForAccessor(const CXXMemberCallExpr &C) { - if (!C.getMethodDecl()) + // Use getCalleeDecl instead of getMethodDecl in order to handle + // pointer-to-member calls. + const auto *MethodDecl = dyn_cast_or_null(C.getCalleeDecl()); + if (!MethodDecl) return nullptr; - auto *Body = dyn_cast_or_null(C.getMethodDecl()->getBody()); + auto *Body = dyn_cast_or_null(MethodDecl->getBody()); if (!Body || Body->size() != 1) return nullptr; if (auto *RS = dyn_cast(*Body->body_begin())) diff --git a/clang/lib/Basic/CodeGenOptions.cpp b/clang/lib/Basic/CodeGenOptions.cpp index 0c609cfa61de..182d0a2fa4d8 100644 --- a/clang/lib/Basic/CodeGenOptions.cpp +++ b/clang/lib/Basic/CodeGenOptions.cpp @@ -20,4 +20,39 @@ CodeGenOptions::CodeGenOptions() { memcpy(CoverageVersion, "408*", 4); } +void CodeGenOptions::resetNonModularOptions(StringRef ModuleFormat) { + // First reset all CodeGen options only. The Debug options are handled later. +#define DEBUGOPT(Name, Bits, Default) +#define VALUE_DEBUGOPT(Name, Bits, Default) +#define ENUM_DEBUGOPT(Name, Type, Bits, Default) +#define CODEGENOPT(Name, Bits, Default) Name = Default; +#define ENUM_CODEGENOPT(Name, Type, Bits, Default) set##Name(Default); +#include "clang/Basic/CodeGenOptions.def" + + // Next reset all debug options that can always be reset, because they never + // affect the PCM. +#define DEBUGOPT(Name, Bits, Default) +#define VALUE_DEBUGOPT(Name, Bits, Default) +#define ENUM_DEBUGOPT(Name, Type, Bits, Default) +#define BENIGN_DEBUGOPT(Name, Bits, Default) Name = Default; +#define BENIGN_VALUE_DEBUGOPT(Name, Bits, Default) Name = Default; +#define BENIGN_ENUM_DEBUGOPT(Name, Type, Bits, Default) set##Name(Default); +#include "clang/Basic/DebugOptions.def" + + // Conditionally reset debug options that only matter when the debug info is + // emitted into the PCM (-gmodules). + if (ModuleFormat == "raw" && !DebugTypeExtRefs) { +#define DEBUGOPT(Name, Bits, Default) Name = Default; +#define VALUE_DEBUGOPT(Name, Bits, Default) Name = Default; +#define ENUM_DEBUGOPT(Name, Type, Bits, Default) set##Name(Default); +#define BENIGN_DEBUGOPT(Name, Bits, Default) +#define BENIGN_VALUE_DEBUGOPT(Name, Bits, Default) +#define BENIGN_ENUM_DEBUGOPT(Name, Type, Bits, Default) +#include "clang/Basic/DebugOptions.def" + } + + RelocationModel = llvm::Reloc::PIC_; + memcpy(CoverageVersion, "408*", 4); +} + } // end namespace clang diff --git a/clang/lib/Basic/Targets/SystemZ.h b/clang/lib/Basic/Targets/SystemZ.h index 9ba255745cf2..e4ec338880f2 100644 --- a/clang/lib/Basic/Targets/SystemZ.h +++ b/clang/lib/Basic/Targets/SystemZ.h @@ -60,7 +60,7 @@ public: resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" "-v128:64-a:8:16-n32:64"); } - MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 128; HasStrictFP = true; } diff --git a/clang/lib/CodeGen/CGAtomic.cpp b/clang/lib/CodeGen/CGAtomic.cpp index 6005d5c51c0e..379c833af32a 100644 --- a/clang/lib/CodeGen/CGAtomic.cpp +++ b/clang/lib/CodeGen/CGAtomic.cpp @@ -383,8 +383,7 @@ static void emitAtomicCmpXchg(CodeGenFunction &CGF, AtomicExpr *E, bool IsWeak, llvm::Value *Desired = CGF.Builder.CreateLoad(Val2); llvm::AtomicCmpXchgInst *Pair = CGF.Builder.CreateAtomicCmpXchg( - Ptr.getPointer(), Expected, Desired, SuccessOrder, FailureOrder, - Scope); + Ptr, Expected, Desired, SuccessOrder, FailureOrder, Scope); Pair->setVolatile(E->isVolatile()); Pair->setWeak(IsWeak); @@ -699,7 +698,7 @@ static void EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, Address Dest, llvm::Value *LoadVal1 = CGF.Builder.CreateLoad(Val1); llvm::AtomicRMWInst *RMWI = - CGF.Builder.CreateAtomicRMW(Op, Ptr.getPointer(), LoadVal1, Order, Scope); + CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order, Scope); RMWI->setVolatile(E->isVolatile()); // For __atomic_*_fetch operations, perform the operation again to @@ -1740,8 +1739,7 @@ std::pair AtomicInfo::EmitAtomicCompareExchangeOp( llvm::AtomicOrdering Success, llvm::AtomicOrdering Failure, bool IsWeak) { // Do the atomic store. Address Addr = getAtomicAddressAsAtomicIntPointer(); - auto *Inst = CGF.Builder.CreateAtomicCmpXchg(Addr.getPointer(), - ExpectedVal, DesiredVal, + auto *Inst = CGF.Builder.CreateAtomicCmpXchg(Addr, ExpectedVal, DesiredVal, Success, Failure); // Other decoration. Inst->setVolatile(LVal.isVolatileQualified()); diff --git a/clang/lib/CodeGen/CGBuilder.h b/clang/lib/CodeGen/CGBuilder.h index 68535920088c..bf5ab171d720 100644 --- a/clang/lib/CodeGen/CGBuilder.h +++ b/clang/lib/CodeGen/CGBuilder.h @@ -126,25 +126,22 @@ public: return CreateAlignedStore(getInt1(Value), Addr, CharUnits::One()); } - // Temporarily use old signature; clang will be updated to an Address overload - // in a subsequent patch. llvm::AtomicCmpXchgInst * - CreateAtomicCmpXchg(llvm::Value *Ptr, llvm::Value *Cmp, llvm::Value *New, + CreateAtomicCmpXchg(Address Addr, llvm::Value *Cmp, llvm::Value *New, llvm::AtomicOrdering SuccessOrdering, llvm::AtomicOrdering FailureOrdering, llvm::SyncScope::ID SSID = llvm::SyncScope::System) { return CGBuilderBaseTy::CreateAtomicCmpXchg( - Ptr, Cmp, New, llvm::MaybeAlign(), SuccessOrdering, FailureOrdering, - SSID); + Addr.getPointer(), Cmp, New, Addr.getAlignment().getAsAlign(), + SuccessOrdering, FailureOrdering, SSID); } - // Temporarily use old signature; clang will be updated to an Address overload - // in a subsequent patch. llvm::AtomicRMWInst * - CreateAtomicRMW(llvm::AtomicRMWInst::BinOp Op, llvm::Value *Ptr, - llvm::Value *Val, llvm::AtomicOrdering Ordering, + CreateAtomicRMW(llvm::AtomicRMWInst::BinOp Op, Address Addr, llvm::Value *Val, + llvm::AtomicOrdering Ordering, llvm::SyncScope::ID SSID = llvm::SyncScope::System) { - return CGBuilderBaseTy::CreateAtomicRMW(Op, Ptr, Val, llvm::MaybeAlign(), + return CGBuilderBaseTy::CreateAtomicRMW(Op, Addr.getPointer(), Val, + Addr.getAlignment().getAsAlign(), Ordering, SSID); } diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index a0f417200261..0d8b3e4aaad4 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -188,8 +188,7 @@ static Value *EmitFromInt(CodeGenFunction &CGF, llvm::Value *V, return V; } -static llvm::Value *CheckAtomicAlignment(CodeGenFunction &CGF, - const CallExpr *E) { +static Address CheckAtomicAlignment(CodeGenFunction &CGF, const CallExpr *E) { ASTContext &Ctx = CGF.getContext(); Address Ptr = CGF.EmitPointerWithAlignment(E->getArg(0)); unsigned Bytes = Ptr.getElementType()->isPointerTy() @@ -199,8 +198,10 @@ static llvm::Value *CheckAtomicAlignment(CodeGenFunction &CGF, if (Align % Bytes != 0) { DiagnosticsEngine &Diags = CGF.CGM.getDiags(); Diags.Report(E->getBeginLoc(), diag::warn_sync_op_misaligned); + // Force address to be at least naturally-aligned. + return Ptr.withAlignment(CharUnits::fromQuantity(Bytes)); } - return Ptr.getPointer(); + return Ptr; } /// Utility to insert an atomic instruction based on Intrinsic::ID @@ -215,19 +216,17 @@ static Value *MakeBinaryAtomicValue( E->getArg(0)->getType()->getPointeeType())); assert(CGF.getContext().hasSameUnqualifiedType(T, E->getArg(1)->getType())); - llvm::Value *DestPtr = CheckAtomicAlignment(CGF, E); + Address DestAddr = CheckAtomicAlignment(CGF, E); llvm::IntegerType *IntType = llvm::IntegerType::get( CGF.getLLVMContext(), CGF.getContext().getTypeSize(T)); - llvm::Value *Args[2]; - Args[0] = DestPtr; - Args[1] = CGF.EmitScalarExpr(E->getArg(1)); - llvm::Type *ValueType = Args[1]->getType(); - Args[1] = EmitToInt(CGF, Args[1], T, IntType); + llvm::Value *Val = CGF.EmitScalarExpr(E->getArg(1)); + llvm::Type *ValueType = Val->getType(); + Val = EmitToInt(CGF, Val, T, IntType); - llvm::Value *Result = CGF.Builder.CreateAtomicRMW( - Kind, Args[0], Args[1], Ordering); + llvm::Value *Result = + CGF.Builder.CreateAtomicRMW(Kind, DestAddr, Val, Ordering); return EmitFromInt(CGF, Result, T, ValueType); } @@ -270,20 +269,18 @@ static RValue EmitBinaryAtomicPost(CodeGenFunction &CGF, E->getArg(0)->getType()->getPointeeType())); assert(CGF.getContext().hasSameUnqualifiedType(T, E->getArg(1)->getType())); - llvm::Value *DestPtr = CheckAtomicAlignment(CGF, E); + Address DestAddr = CheckAtomicAlignment(CGF, E); llvm::IntegerType *IntType = llvm::IntegerType::get( CGF.getLLVMContext(), CGF.getContext().getTypeSize(T)); - llvm::Value *Args[2]; - Args[1] = CGF.EmitScalarExpr(E->getArg(1)); - llvm::Type *ValueType = Args[1]->getType(); - Args[1] = EmitToInt(CGF, Args[1], T, IntType); - Args[0] = DestPtr; + llvm::Value *Val = CGF.EmitScalarExpr(E->getArg(1)); + llvm::Type *ValueType = Val->getType(); + Val = EmitToInt(CGF, Val, T, IntType); llvm::Value *Result = CGF.Builder.CreateAtomicRMW( - Kind, Args[0], Args[1], llvm::AtomicOrdering::SequentiallyConsistent); - Result = CGF.Builder.CreateBinOp(Op, Result, Args[1]); + Kind, DestAddr, Val, llvm::AtomicOrdering::SequentiallyConsistent); + Result = CGF.Builder.CreateBinOp(Op, Result, Val); if (Invert) Result = CGF.Builder.CreateBinOp(llvm::Instruction::Xor, Result, @@ -309,20 +306,18 @@ static RValue EmitBinaryAtomicPost(CodeGenFunction &CGF, static Value *MakeAtomicCmpXchgValue(CodeGenFunction &CGF, const CallExpr *E, bool ReturnBool) { QualType T = ReturnBool ? E->getArg(1)->getType() : E->getType(); - llvm::Value *DestPtr = CheckAtomicAlignment(CGF, E); + Address DestAddr = CheckAtomicAlignment(CGF, E); llvm::IntegerType *IntType = llvm::IntegerType::get( CGF.getLLVMContext(), CGF.getContext().getTypeSize(T)); - Value *Args[3]; - Args[0] = DestPtr; - Args[1] = CGF.EmitScalarExpr(E->getArg(1)); - llvm::Type *ValueType = Args[1]->getType(); - Args[1] = EmitToInt(CGF, Args[1], T, IntType); - Args[2] = EmitToInt(CGF, CGF.EmitScalarExpr(E->getArg(2)), T, IntType); + Value *Cmp = CGF.EmitScalarExpr(E->getArg(1)); + llvm::Type *ValueType = Cmp->getType(); + Cmp = EmitToInt(CGF, Cmp, T, IntType); + Value *New = EmitToInt(CGF, CGF.EmitScalarExpr(E->getArg(2)), T, IntType); Value *Pair = CGF.Builder.CreateAtomicCmpXchg( - Args[0], Args[1], Args[2], llvm::AtomicOrdering::SequentiallyConsistent, + DestAddr, Cmp, New, llvm::AtomicOrdering::SequentiallyConsistent, llvm::AtomicOrdering::SequentiallyConsistent); if (ReturnBool) // Extract boolean success flag and zext it to int. @@ -358,7 +353,8 @@ Value *EmitAtomicCmpXchgForMSIntrin(CodeGenFunction &CGF, const CallExpr *E, assert(CGF.getContext().hasSameUnqualifiedType(E->getType(), E->getArg(2)->getType())); - auto *Destination = CGF.EmitScalarExpr(E->getArg(0)); + Address DestAddr = CheckAtomicAlignment(CGF, E); + auto *Comparand = CGF.EmitScalarExpr(E->getArg(2)); auto *Exchange = CGF.EmitScalarExpr(E->getArg(1)); @@ -372,8 +368,7 @@ Value *EmitAtomicCmpXchgForMSIntrin(CodeGenFunction &CGF, const CallExpr *E, // _Interlocked* operations in the future, we will have to remove the volatile // marker. auto *Result = CGF.Builder.CreateAtomicCmpXchg( - Destination, Comparand, Exchange, - SuccessOrdering, FailureOrdering); + DestAddr, Comparand, Exchange, SuccessOrdering, FailureOrdering); Result->setVolatile(true); return CGF.Builder.CreateExtractValue(Result, 0); } @@ -386,29 +381,34 @@ Value *EmitAtomicCmpXchgForMSIntrin(CodeGenFunction &CGF, const CallExpr *E, // __int64 _ExchangeHigh, // __int64 _ExchangeLow, // __int64 * _ComparandResult); +// +// Note that Destination is assumed to be at least 16-byte aligned, despite +// being typed int64. + static Value *EmitAtomicCmpXchg128ForMSIntrin(CodeGenFunction &CGF, const CallExpr *E, AtomicOrdering SuccessOrdering) { assert(E->getNumArgs() == 4); - llvm::Value *Destination = CGF.EmitScalarExpr(E->getArg(0)); + llvm::Value *DestPtr = CGF.EmitScalarExpr(E->getArg(0)); llvm::Value *ExchangeHigh = CGF.EmitScalarExpr(E->getArg(1)); llvm::Value *ExchangeLow = CGF.EmitScalarExpr(E->getArg(2)); - llvm::Value *ComparandPtr = CGF.EmitScalarExpr(E->getArg(3)); + Address ComparandAddr = CGF.EmitPointerWithAlignment(E->getArg(3)); - assert(Destination->getType()->isPointerTy()); + assert(DestPtr->getType()->isPointerTy()); assert(!ExchangeHigh->getType()->isPointerTy()); assert(!ExchangeLow->getType()->isPointerTy()); - assert(ComparandPtr->getType()->isPointerTy()); // For Release ordering, the failure ordering should be Monotonic. auto FailureOrdering = SuccessOrdering == AtomicOrdering::Release ? AtomicOrdering::Monotonic : SuccessOrdering; - // Convert to i128 pointers and values. + // Convert to i128 pointers and values. Alignment is also overridden for + // destination pointer. llvm::Type *Int128Ty = llvm::IntegerType::get(CGF.getLLVMContext(), 128); - Address ComparandResult(ComparandPtr, Int128Ty, - CGF.getContext().toCharUnitsFromBits(128)); + Address DestAddr(DestPtr, Int128Ty, + CGF.getContext().toCharUnitsFromBits(128)); + ComparandAddr = ComparandAddr.withElementType(Int128Ty); // (((i128)hi) << 64) | ((i128)lo) ExchangeHigh = CGF.Builder.CreateZExt(ExchangeHigh, Int128Ty); @@ -418,9 +418,9 @@ static Value *EmitAtomicCmpXchg128ForMSIntrin(CodeGenFunction &CGF, llvm::Value *Exchange = CGF.Builder.CreateOr(ExchangeHigh, ExchangeLow); // Load the comparand for the instruction. - llvm::Value *Comparand = CGF.Builder.CreateLoad(ComparandResult); + llvm::Value *Comparand = CGF.Builder.CreateLoad(ComparandAddr); - auto *CXI = CGF.Builder.CreateAtomicCmpXchg(Destination, Comparand, Exchange, + auto *CXI = CGF.Builder.CreateAtomicCmpXchg(DestAddr, Comparand, Exchange, SuccessOrdering, FailureOrdering); // The atomic instruction is marked volatile for consistency with MSVC. This @@ -431,7 +431,7 @@ static Value *EmitAtomicCmpXchg128ForMSIntrin(CodeGenFunction &CGF, // Store the result as an outparameter. CGF.Builder.CreateStore(CGF.Builder.CreateExtractValue(CXI, 0), - ComparandResult); + ComparandAddr); // Get the success boolean and zero extend it to i8. Value *Success = CGF.Builder.CreateExtractValue(CXI, 1); @@ -443,24 +443,21 @@ static Value *EmitAtomicIncrementValue(CodeGenFunction &CGF, const CallExpr *E, assert(E->getArg(0)->getType()->isPointerType()); auto *IntTy = CGF.ConvertType(E->getType()); + Address DestAddr = CheckAtomicAlignment(CGF, E); auto *Result = CGF.Builder.CreateAtomicRMW( - AtomicRMWInst::Add, - CGF.EmitScalarExpr(E->getArg(0)), - ConstantInt::get(IntTy, 1), - Ordering); + AtomicRMWInst::Add, DestAddr, ConstantInt::get(IntTy, 1), Ordering); return CGF.Builder.CreateAdd(Result, ConstantInt::get(IntTy, 1)); } -static Value *EmitAtomicDecrementValue(CodeGenFunction &CGF, const CallExpr *E, +static Value *EmitAtomicDecrementValue( + CodeGenFunction &CGF, const CallExpr *E, AtomicOrdering Ordering = AtomicOrdering::SequentiallyConsistent) { assert(E->getArg(0)->getType()->isPointerType()); auto *IntTy = CGF.ConvertType(E->getType()); + Address DestAddr = CheckAtomicAlignment(CGF, E); auto *Result = CGF.Builder.CreateAtomicRMW( - AtomicRMWInst::Sub, - CGF.EmitScalarExpr(E->getArg(0)), - ConstantInt::get(IntTy, 1), - Ordering); + AtomicRMWInst::Sub, DestAddr, ConstantInt::get(IntTy, 1), Ordering); return CGF.Builder.CreateSub(Result, ConstantInt::get(IntTy, 1)); } @@ -1215,8 +1212,7 @@ static llvm::Value *EmitBitTestIntrinsic(CodeGenFunction &CGF, Mask = CGF.Builder.CreateNot(Mask); RMWOp = llvm::AtomicRMWInst::And; } - OldByte = CGF.Builder.CreateAtomicRMW(RMWOp, ByteAddr.getPointer(), Mask, - Ordering); + OldByte = CGF.Builder.CreateAtomicRMW(RMWOp, ByteAddr, Mask, Ordering); } else { // Emit a plain load for the non-interlocked intrinsics. OldByte = CGF.Builder.CreateLoad(ByteAddr, "bittest.byte"); @@ -4456,14 +4452,13 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, case Builtin::BI__sync_lock_release_4: case Builtin::BI__sync_lock_release_8: case Builtin::BI__sync_lock_release_16: { - Value *Ptr = CheckAtomicAlignment(*this, E); + Address Ptr = CheckAtomicAlignment(*this, E); QualType ElTy = E->getArg(0)->getType()->getPointeeType(); - CharUnits StoreSize = getContext().getTypeSizeInChars(ElTy); - llvm::Type *ITy = - llvm::IntegerType::get(getLLVMContext(), StoreSize.getQuantity() * 8); + + llvm::Type *ITy = llvm::IntegerType::get(getLLVMContext(), + getContext().getTypeSize(ElTy)); llvm::StoreInst *Store = - Builder.CreateAlignedStore(llvm::Constant::getNullValue(ITy), Ptr, - StoreSize); + Builder.CreateStore(llvm::Constant::getNullValue(ITy), Ptr); Store->setAtomic(llvm::AtomicOrdering::Release); return RValue::get(nullptr); } @@ -4514,7 +4509,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, bool Volatile = PtrTy->castAs()->getPointeeType().isVolatileQualified(); - Value *Ptr = EmitScalarExpr(E->getArg(0)); + Address Ptr = + EmitPointerWithAlignment(E->getArg(0)).withElementType(Int8Ty); + Value *NewVal = Builder.getInt8(1); Value *Order = EmitScalarExpr(E->getArg(1)); if (isa(Order)) { @@ -5035,7 +5032,7 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, llvm::IntegerType *IntType = IntegerType::get( getLLVMContext(), getContext().getTypeSize(E->getType())); - llvm::Value *Destination = EmitScalarExpr(E->getArg(0)); + Address DestAddr = CheckAtomicAlignment(*this, E); llvm::Value *Exchange = EmitScalarExpr(E->getArg(1)); RTy = Exchange->getType(); @@ -5048,7 +5045,7 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, BuiltinID == Builtin::BI_InterlockedCompareExchangePointer_nf ? AtomicOrdering::Monotonic : AtomicOrdering::SequentiallyConsistent; - auto Result = Builder.CreateAtomicCmpXchg(Destination, Comparand, Exchange, + auto Result = Builder.CreateAtomicCmpXchg(DestAddr, Comparand, Exchange, Ordering, Ordering); Result->setVolatile(true); @@ -11901,12 +11898,12 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID, } case clang::AArch64::BI_InterlockedAdd: { - Value *Arg0 = EmitScalarExpr(E->getArg(0)); - Value *Arg1 = EmitScalarExpr(E->getArg(1)); - AtomicRMWInst *RMWI = Builder.CreateAtomicRMW( - AtomicRMWInst::Add, Arg0, Arg1, - llvm::AtomicOrdering::SequentiallyConsistent); - return Builder.CreateAdd(RMWI, Arg1); + Address DestAddr = CheckAtomicAlignment(*this, E); + Value *Val = EmitScalarExpr(E->getArg(1)); + AtomicRMWInst *RMWI = + Builder.CreateAtomicRMW(AtomicRMWInst::Add, DestAddr, Val, + llvm::AtomicOrdering::SequentiallyConsistent); + return Builder.CreateAdd(RMWI, Val); } } @@ -18219,7 +18216,7 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, break; } - Value *Ptr = EmitScalarExpr(E->getArg(0)); + Address Ptr = CheckAtomicAlignment(*this, E); Value *Val = EmitScalarExpr(E->getArg(1)); ProcessOrderScopeAMDGCN(EmitScalarExpr(E->getArg(2)), @@ -19108,9 +19105,10 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, case NVPTX::BI__nvvm_atom_add_gen_f: case NVPTX::BI__nvvm_atom_add_gen_d: { - Value *Ptr = EmitScalarExpr(E->getArg(0)); + Address DestAddr = EmitPointerWithAlignment(E->getArg(0)); Value *Val = EmitScalarExpr(E->getArg(1)); - return Builder.CreateAtomicRMW(llvm::AtomicRMWInst::FAdd, Ptr, Val, + + return Builder.CreateAtomicRMW(llvm::AtomicRMWInst::FAdd, DestAddr, Val, AtomicOrdering::SequentiallyConsistent); } diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp index 602e325e560f..7cf661994a29 100644 --- a/clang/lib/CodeGen/CGDebugInfo.cpp +++ b/clang/lib/CodeGen/CGDebugInfo.cpp @@ -69,29 +69,6 @@ static uint32_t getDeclAlignIfRequired(const Decl *D, const ASTContext &Ctx) { return D->hasAttr() ? D->getMaxAlignment() : 0; } -/// Given a VarDecl corresponding to either the definition or -/// declaration of a C++ static data member, if it has a constant -/// initializer and is evaluatable, return the evaluated value. -/// Returns std::nullopt otherwise. -static std::optional -evaluateConstantInitializer(const clang::VarDecl *VD, - const clang::ASTContext &Ctx) { - assert(VD != nullptr); - - if (!VD->isStaticDataMember()) - return std::nullopt; - - if (!VD->isUsableInConstantExpressions(Ctx)) - return std::nullopt; - - auto const *InitExpr = VD->getAnyInitializer(); - Expr::EvalResult Result; - if (!InitExpr->EvaluateAsConstantExpr(Result, Ctx)) - return std::nullopt; - - return Result.Val; -} - CGDebugInfo::CGDebugInfo(CodeGenModule &CGM) : CGM(CGM), DebugKind(CGM.getCodeGenOpts().getDebugInfo()), DebugTypeExtRefs(CGM.getCodeGenOpts().DebugTypeExtRefs), @@ -1724,7 +1701,6 @@ CGDebugInfo::CreateRecordStaticField(const VarDecl *Var, llvm::DIType *RecordTy, llvm::DIDerivedType *GV = DBuilder.createStaticMemberType( RecordTy, VName, VUnit, LineNumber, VTy, Flags, C, Tag, Align); StaticDataMemberCache[Var->getCanonicalDecl()].reset(GV); - StaticDataMemberDefinitionsToEmit.push_back(Var->getCanonicalDecl()); return GV; } @@ -5628,41 +5604,6 @@ void CGDebugInfo::EmitGlobalVariable(const ValueDecl *VD, const APValue &Init) { TemplateParameters, Align)); } -void CGDebugInfo::EmitGlobalVariable(const VarDecl *VD) { - assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); - if (VD->hasAttr()) - return; - - const auto CacheIt = DeclCache.find(VD); - if (CacheIt != DeclCache.end()) - return; - - const auto InitVal = evaluateConstantInitializer(VD, CGM.getContext()); - if (!InitVal) - return; - - llvm::DIFile *Unit = nullptr; - llvm::DIScope *DContext = nullptr; - unsigned LineNo; - StringRef DeclName, LinkageName; - QualType T; - llvm::MDTuple *TemplateParameters = nullptr; - collectVarDeclProps(VD, Unit, LineNo, T, DeclName, LinkageName, - TemplateParameters, DContext); - - auto Align = getDeclAlignIfRequired(VD, CGM.getContext()); - llvm::DINodeArray Annotations = CollectBTFDeclTagAnnotations(VD); - llvm::DIExpression *InitExpr = createConstantValueExpression(VD, *InitVal); - - // Omit linkage name for variable definitions that represent constants. - // There hasn't been a need from consumers yet to have it attached. - DeclCache[VD].reset(DBuilder.createGlobalVariableExpression( - TheCU, DeclName, /* LinkageName */ {}, Unit, LineNo, - getOrCreateType(T, Unit), true, true, InitExpr, - getOrCreateStaticDataMemberDeclarationOrNull(VD), TemplateParameters, - Align, Annotations)); -} - void CGDebugInfo::EmitExternalVariable(llvm::GlobalVariable *Var, const VarDecl *D) { assert(CGM.getCodeGenOpts().hasReducedDebugInfo()); @@ -5867,20 +5808,6 @@ void CGDebugInfo::setDwoId(uint64_t Signature) { } void CGDebugInfo::finalize() { - // We can't use a for-each here because `EmitGlobalVariable` - // may push new decls into `StaticDataMemberDefinitionsToEmit`, - // which would invalidate any iterator. - for (size_t i = 0; i < StaticDataMemberDefinitionsToEmit.size(); ++i) { - auto const *VD = StaticDataMemberDefinitionsToEmit[i]; - - assert(VD && VD->isStaticDataMember()); - - if (DeclCache.contains(VD)) - continue; - - EmitGlobalVariable(VD); - } - // Creating types might create further types - invalidating the current // element and the size(), so don't cache/reference them. for (size_t i = 0; i != ObjCInterfaceCache.size(); ++i) { diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h index 3e4c133b7f2b..7b60e94555d0 100644 --- a/clang/lib/CodeGen/CGDebugInfo.h +++ b/clang/lib/CodeGen/CGDebugInfo.h @@ -161,9 +161,6 @@ class CGDebugInfo { llvm::DenseMap> StaticDataMemberCache; - /// Keeps track of static data members for which we should emit a definition. - std::vector StaticDataMemberDefinitionsToEmit; - using ParamDecl2StmtTy = llvm::DenseMap; using Param2DILocTy = llvm::DenseMap; @@ -529,9 +526,6 @@ public: /// Emit a constant global variable's debug info. void EmitGlobalVariable(const ValueDecl *VD, const APValue &Init); - /// Emit debug-info for a variable with a constant initializer. - void EmitGlobalVariable(const VarDecl *VD); - /// Emit information about an external variable. void EmitExternalVariable(llvm::GlobalVariable *GV, const VarDecl *Decl); diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 9d1f1a58f9e1..69cf7f76be9a 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -3833,6 +3833,33 @@ static QualType getFixedSizeElementType(const ASTContext &ctx, return eltType; } +static bool hasBPFPreserveStaticOffset(const RecordDecl *D) { + return D && D->hasAttr(); +} + +static bool hasBPFPreserveStaticOffset(const Expr *E) { + if (!E) + return false; + QualType PointeeType = E->getType()->getPointeeType(); + if (PointeeType.isNull()) + return false; + if (const auto *BaseDecl = PointeeType->getAsRecordDecl()) + return hasBPFPreserveStaticOffset(BaseDecl); + return false; +} + +// Wraps Addr with a call to llvm.preserve.static.offset intrinsic. +static Address wrapWithBPFPreserveStaticOffset(CodeGenFunction &CGF, + Address &Addr) { + if (!CGF.getTarget().getTriple().isBPF()) + return Addr; + + llvm::Function *Fn = + CGF.CGM.getIntrinsic(llvm::Intrinsic::preserve_static_offset); + llvm::CallInst *Call = CGF.Builder.CreateCall(Fn, {Addr.getPointer()}); + return Address(Call, Addr.getElementType(), Addr.getAlignment()); +} + /// Given an array base, check whether its member access belongs to a record /// with preserve_access_index attribute or not. static bool IsPreserveAIArrayBase(CodeGenFunction &CGF, const Expr *ArrayBase) { @@ -3894,6 +3921,9 @@ static Address emitArraySubscriptGEP(CodeGenFunction &CGF, Address addr, CharUnits eltAlign = getArrayElementAlign(addr.getAlignment(), indices.back(), eltSize); + if (hasBPFPreserveStaticOffset(Base)) + addr = wrapWithBPFPreserveStaticOffset(CGF, addr); + llvm::Value *eltPtr; auto LastIndex = dyn_cast(indices.back()); if (!LastIndex || @@ -4522,6 +4552,8 @@ LValue CodeGenFunction::EmitLValueForField(LValue base, Address Addr = base.getAddress(*this); unsigned Idx = RL.getLLVMFieldNo(field); const RecordDecl *rec = field->getParent(); + if (hasBPFPreserveStaticOffset(rec)) + Addr = wrapWithBPFPreserveStaticOffset(*this, Addr); if (!UseVolatile) { if (!IsInPreservedAIRegion && (!getDebugInfo() || !rec->hasAttr())) { @@ -4594,6 +4626,8 @@ LValue CodeGenFunction::EmitLValueForField(LValue base, } Address addr = base.getAddress(*this); + if (hasBPFPreserveStaticOffset(rec)) + addr = wrapWithBPFPreserveStaticOffset(*this, addr); if (auto *ClassDef = dyn_cast(rec)) { if (CGM.getCodeGenOpts().StrictVTablePointers && ClassDef->isDynamicClass()) { diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 378437364767..41ad2ddac30d 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -2571,7 +2571,7 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, // For atomic bool increment, we just store true and return it for // preincrement, do an atomic swap with true for postincrement return Builder.CreateAtomicRMW( - llvm::AtomicRMWInst::Xchg, LV.getPointer(CGF), True, + llvm::AtomicRMWInst::Xchg, LV.getAddress(CGF), True, llvm::AtomicOrdering::SequentiallyConsistent); } // Special case for atomic increment / decrement on integers, emit @@ -2589,7 +2589,7 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, llvm::Value *amt = CGF.EmitToMemory( llvm::ConstantInt::get(ConvertType(type), 1, true), type); llvm::Value *old = - Builder.CreateAtomicRMW(aop, LV.getPointer(CGF), amt, + Builder.CreateAtomicRMW(aop, LV.getAddress(CGF), amt, llvm::AtomicOrdering::SequentiallyConsistent); return isPre ? Builder.CreateBinOp(op, old, amt) : old; } @@ -3314,7 +3314,7 @@ LValue ScalarExprEmitter::EmitCompoundAssignLValue( E->getExprLoc()), LHSTy); Value *OldVal = Builder.CreateAtomicRMW( - AtomicOp, LHSLV.getPointer(CGF), Amt, + AtomicOp, LHSLV.getAddress(CGF), Amt, llvm::AtomicOrdering::SequentiallyConsistent); // Since operation is atomic, the result type is guaranteed to be the diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp index 90c7ed450e54..ed426098ac69 100644 --- a/clang/lib/CodeGen/CGStmtOpenMP.cpp +++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp @@ -2558,9 +2558,9 @@ static void emitOMPSimdRegion(CodeGenFunction &CGF, const OMPLoopDirective &S, (void)CGF.EmitOMPLinearClauseInit(S); { CodeGenFunction::OMPPrivateScope LoopScope(CGF); + CGF.EmitOMPPrivateClause(S, LoopScope); CGF.EmitOMPPrivateLoopCounters(S, LoopScope); CGF.EmitOMPLinearClause(S, LoopScope); - CGF.EmitOMPPrivateClause(S, LoopScope); CGF.EmitOMPReductionClauseInit(S, LoopScope); CGOpenMPRuntime::LastprivateConditionalRAII LPCRegion( CGF, S, CGF.EmitLValue(S.getIterationVariable())); @@ -6206,7 +6206,7 @@ static std::pair emitOMPAtomicRMW(CodeGenFunction &CGF, LValue X, X.getAddress(CGF).getElementType()); } llvm::Value *Res = - CGF.Builder.CreateAtomicRMW(RMWOp, X.getPointer(CGF), UpdateVal, AO); + CGF.Builder.CreateAtomicRMW(RMWOp, X.getAddress(CGF), UpdateVal, AO); return std::make_pair(true, RValue::get(Res)); } diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index dea58a7ff414..6a20723bf2bc 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -4178,8 +4178,29 @@ void CodeGenModule::emitMultiVersionFunctions() { } llvm::Constant *ResolverConstant = GetOrCreateMultiVersionResolver(GD); - if (auto *IFunc = dyn_cast(ResolverConstant)) + if (auto *IFunc = dyn_cast(ResolverConstant)) { ResolverConstant = IFunc->getResolver(); + // In Aarch64, default versions of multiversioned functions are mangled to + // their 'normal' assembly name. This deviates from other targets which + // append a '.default' string. As a result we need to continue appending + // .ifunc in Aarch64. + // FIXME: Should Aarch64 mangling for 'default' multiversion function and + // in turn ifunc function match that of other targets? + if (FD->isTargetClonesMultiVersion() && + !getTarget().getTriple().isAArch64()) { + const CGFunctionInfo &FI = getTypes().arrangeGlobalDeclaration(GD); + llvm::FunctionType *DeclTy = getTypes().GetFunctionType(FI); + std::string MangledName = getMangledNameImpl( + *this, GD, FD, /*OmitMultiVersionMangling=*/true); + // In prior versions of Clang, the mangling for ifuncs incorrectly + // included an .ifunc suffix. This alias is generated for backward + // compatibility. It is deprecated, and may be removed in the future. + auto *Alias = llvm::GlobalAlias::create( + DeclTy, 0, getMultiversionLinkage(*this, GD), + MangledName + ".ifunc", IFunc, &getModule()); + SetCommonAttributes(FD, Alias); + } + } llvm::Function *ResolverFunc = cast(ResolverConstant); ResolverFunc->setLinkage(getMultiversionLinkage(*this, GD)); @@ -4346,10 +4367,19 @@ llvm::Constant *CodeGenModule::GetOrCreateMultiVersionResolver(GlobalDecl GD) { // Holds the name of the resolver, in ifunc mode this is the ifunc (which has // a separate resolver). std::string ResolverName = MangledName; - if (getTarget().supportsIFunc()) - ResolverName += ".ifunc"; - else if (FD->isTargetMultiVersion()) + if (getTarget().supportsIFunc()) { + // In Aarch64, default versions of multiversioned functions are mangled to + // their 'normal' assembly name. This deviates from other targets which + // append a '.default' string. As a result we need to continue appending + // .ifunc in Aarch64. + // FIXME: Should Aarch64 mangling for 'default' multiversion function and + // in turn ifunc function match that of other targets? + if (!FD->isTargetClonesMultiVersion() || + getTarget().getTriple().isAArch64()) + ResolverName += ".ifunc"; + } else if (FD->isTargetMultiVersion()) { ResolverName += ".resolver"; + } // If the resolver has already been created, just return it. if (llvm::GlobalValue *ResolverGV = GetGlobalValue(ResolverName)) diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 6f5ff8141032..e241706b9082 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -1940,12 +1940,6 @@ int Driver::ExecuteCompilation( void Driver::PrintHelp(bool ShowHidden) const { llvm::opt::Visibility VisibilityMask = getOptionVisibilityMask(); - // TODO: We're overriding the mask for flang here to keep this NFC for the - // option refactoring, but what we really need to do is annotate the flags - // that Flang uses. - if (IsFlangMode()) - VisibilityMask = llvm::opt::Visibility(options::FlangOption); - std::string Usage = llvm::formatv("{0} [options] file...", Name).str(); getOpts().printHelp(llvm::outs(), Usage.c_str(), DriverTitle.c_str(), ShowHidden, /*ShowAllAliases=*/false, diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp index 1f77c9870517..097258b16924 100644 --- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -57,9 +57,8 @@ std::string aarch64::getAArch64TargetCPU(const ArgList &Args, if (Triple.isArm64e()) return "apple-a12"; - // Make sure we pick the appropriate Apple CPU if -arch is used or when - // targetting a Darwin OS. - if (Args.getLastArg(options::OPT_arch) || Triple.isOSDarwin()) + // Make sure we pick the appropriate Apple CPU when targetting a Darwin OS. + if (Triple.isOSDarwin()) return Triple.getArch() == llvm::Triple::aarch64_32 ? "apple-s4" : "apple-a7"; @@ -274,7 +273,7 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, success = getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Features); else if ((A = Args.getLastArg(options::OPT_mcpu_EQ))) success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Features); - else if (Args.hasArg(options::OPT_arch) || isCPUDeterminedByTriple(Triple)) + else if (isCPUDeterminedByTriple(Triple)) success = getAArch64ArchFeaturesFromMcpu( D, getAArch64TargetCPU(Args, Triple, A), Args, Features); else @@ -287,8 +286,7 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, else if (success && (A = Args.getLastArg(options::OPT_mcpu_EQ))) success = getAArch64MicroArchFeaturesFromMcpu(D, A->getValue(), Args, Features); - else if (success && - (Args.hasArg(options::OPT_arch) || isCPUDeterminedByTriple(Triple))) + else if (success && isCPUDeterminedByTriple(Triple)) success = getAArch64MicroArchFeaturesFromMcpu( D, getAArch64TargetCPU(Args, Triple, A), Args, Features); diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 9db19e30a9f1..9b21fe952af7 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -143,33 +143,11 @@ void Flang::addCodegenOptions(const ArgList &Args, if (shouldLoopVersion(Args)) CmdArgs.push_back("-fversion-loops-for-stride"); - Arg *aliasAnalysis = Args.getLastArg(options::OPT_falias_analysis, - options::OPT_fno_alias_analysis); - // only pass on the argument if it does not match that implied by the - // optimization level: so if optimization is requested, only forward - // -fno-alias-analysis. If optimization is not requested, only forward - // -falias-analysis. - Arg *optLevel = - Args.getLastArg(options::OPT_Ofast, options::OPT_O, options::OPT_O4); - if (aliasAnalysis) { - bool faliasAnalysis = - aliasAnalysis->getOption().matches(options::OPT_falias_analysis); - if (optLevel && !faliasAnalysis) { - CmdArgs.push_back("-fno-alias-analysis"); - } else { - if (faliasAnalysis) - // requested alias analysis but no optimization enabled - CmdArgs.push_back("-falias-analysis"); - } - } - Args.addAllArgs(CmdArgs, {options::OPT_flang_experimental_hlfir, options::OPT_flang_deprecated_no_hlfir, options::OPT_flang_experimental_polymorphism, options::OPT_fno_ppc_native_vec_elem_order, - options::OPT_fppc_native_vec_elem_order, - options::OPT_falias_analysis, - options::OPT_fno_alias_analysis}); + options::OPT_fppc_native_vec_elem_order}); } void Flang::addPicOptions(const ArgList &Args, ArgStringList &CmdArgs) const { diff --git a/clang/lib/Format/ObjCPropertyAttributeOrderFixer.cpp b/clang/lib/Format/ObjCPropertyAttributeOrderFixer.cpp index 20108306f103..c91d6251425e 100644 --- a/clang/lib/Format/ObjCPropertyAttributeOrderFixer.cpp +++ b/clang/lib/Format/ObjCPropertyAttributeOrderFixer.cpp @@ -15,8 +15,6 @@ #include "ObjCPropertyAttributeOrderFixer.h" -#include "llvm/ADT/Sequence.h" - #include namespace clang { @@ -25,26 +23,20 @@ namespace format { ObjCPropertyAttributeOrderFixer::ObjCPropertyAttributeOrderFixer( const Environment &Env, const FormatStyle &Style) : TokenAnalyzer(Env, Style) { - // Create an "order priority" map to use to sort properties. - unsigned index = 0; + unsigned Index = 0; for (const auto &Property : Style.ObjCPropertyAttributeOrder) - SortOrderMap[Property] = index++; + SortOrderMap[Property] = Index++; } struct ObjCPropertyEntry { - StringRef Attribute; // eg, "readwrite" - StringRef Value; // eg, the "foo" of the attribute "getter=foo" + StringRef Attribute; // eg, `readwrite` + StringRef Value; // eg, the `foo` of the attribute `getter=foo` }; -static bool isObjCPropertyAttribute(const FormatToken *Tok) { - // Most attributes look like identifiers, but `class` is a keyword. - return Tok->isOneOf(tok::identifier, tok::kw_class); -} - void ObjCPropertyAttributeOrderFixer::sortPropertyAttributes( const SourceManager &SourceMgr, tooling::Replacements &Fixes, - const FormatToken *BeginTok, const FormatToken *EndTok) const { + const FormatToken *BeginTok, const FormatToken *EndTok) { assert(BeginTok); assert(EndTok); assert(EndTok->Previous); @@ -53,8 +45,16 @@ void ObjCPropertyAttributeOrderFixer::sortPropertyAttributes( if (BeginTok == EndTok || BeginTok->Next == EndTok) return; + // Use a set to sort attributes and remove duplicates. + std::set Ordinals; + + // Create a "remapping index" on how to reorder the attributes. + SmallVector Indices; + // Collect the attributes. - SmallVector PropertyAttributes; + SmallVector PropertyAttributes; + bool HasDuplicates = false; + int Index = 0; for (auto Tok = BeginTok; Tok != EndTok; Tok = Tok->Next) { assert(Tok); if (Tok->is(tok::comma)) { @@ -62,13 +62,14 @@ void ObjCPropertyAttributeOrderFixer::sortPropertyAttributes( continue; } - if (!isObjCPropertyAttribute(Tok)) { + // Most attributes look like identifiers, but `class` is a keyword. + if (!Tok->isOneOf(tok::identifier, tok::kw_class)) { // If we hit any other kind of token, just bail. return; } - // Memoize the attribute. (Note that 'class' is a legal attribute!) - PropertyAttributes.push_back({Tok->TokenText, StringRef{}}); + const StringRef Attribute{Tok->TokenText}; + StringRef Value; // Also handle `getter=getFoo` attributes. // (Note: no check needed against `EndTok`, since its type is not @@ -82,49 +83,66 @@ void ObjCPropertyAttributeOrderFixer::sortPropertyAttributes( return; } Tok = Tok->Next; - PropertyAttributes.back().Value = Tok->TokenText; + Value = Tok->TokenText; + } + + auto It = SortOrderMap.find(Attribute); + if (It == SortOrderMap.end()) + It = SortOrderMap.insert({Attribute, SortOrderMap.size()}).first; + + // Sort the indices based on the priority stored in `SortOrderMap`. + const auto Ordinal = It->second; + if (!Ordinals.insert(Ordinal).second) { + HasDuplicates = true; + continue; } + + if (Ordinal >= Indices.size()) + Indices.resize(Ordinal + 1); + Indices[Ordinal] = Index++; + + // Memoize the attribute. + PropertyAttributes.push_back({Attribute, Value}); } - // There's nothing to do unless there's more than one attribute. - if (PropertyAttributes.size() < 2) - return; + if (!HasDuplicates) { + // There's nothing to do unless there's more than one attribute. + if (PropertyAttributes.size() < 2) + return; - // Create a "remapping index" on how to reorder the attributes. - SmallVector Indices = - llvm::to_vector<8>(llvm::seq(0, PropertyAttributes.size())); - - // Sort the indices based on the priority stored in 'SortOrderMap'; use Max - // for missing values. - const auto SortOrderMax = Style.ObjCPropertyAttributeOrder.size(); - auto SortIndex = [&](const StringRef &Needle) -> unsigned { - auto I = SortOrderMap.find(Needle); - return (I == SortOrderMap.end()) ? SortOrderMax : I->getValue(); - }; - llvm::stable_sort(Indices, [&](unsigned LHSI, unsigned RHSI) { - return SortIndex(PropertyAttributes[LHSI].Attribute) < - SortIndex(PropertyAttributes[RHSI].Attribute); - }); - - // If the property order is already correct, then no fix-up is needed. - if (llvm::is_sorted(Indices)) - return; + int PrevIndex = -1; + bool IsSorted = true; + for (const auto Ordinal : Ordinals) { + const auto Index = Indices[Ordinal]; + if (Index < PrevIndex) { + IsSorted = false; + break; + } + assert(Index > PrevIndex); + PrevIndex = Index; + } + + // If the property order is already correct, then no fix-up is needed. + if (IsSorted) + return; + } // Generate the replacement text. std::string NewText; - const auto AppendAttribute = [&](const ObjCPropertyEntry &PropertyEntry) { + bool IsFirst = true; + for (const auto Ordinal : Ordinals) { + if (IsFirst) + IsFirst = false; + else + NewText += ", "; + + const auto &PropertyEntry = PropertyAttributes[Indices[Ordinal]]; NewText += PropertyEntry.Attribute; - if (!PropertyEntry.Value.empty()) { - NewText += "="; - NewText += PropertyEntry.Value; + if (const auto Value = PropertyEntry.Value; !Value.empty()) { + NewText += '='; + NewText += Value; } - }; - - AppendAttribute(PropertyAttributes[Indices[0]]); - for (unsigned Index : llvm::drop_begin(Indices)) { - NewText += ", "; - AppendAttribute(PropertyAttributes[Index]); } auto Range = CharSourceRange::getCharRange( @@ -139,7 +157,7 @@ void ObjCPropertyAttributeOrderFixer::sortPropertyAttributes( void ObjCPropertyAttributeOrderFixer::analyzeObjCPropertyDecl( const SourceManager &SourceMgr, const AdditionalKeywords &Keywords, - tooling::Replacements &Fixes, const FormatToken *Tok) const { + tooling::Replacements &Fixes, const FormatToken *Tok) { assert(Tok); // Expect `property` to be the very next token or else just bail early. diff --git a/clang/lib/Format/ObjCPropertyAttributeOrderFixer.h b/clang/lib/Format/ObjCPropertyAttributeOrderFixer.h index 99f0dd338f60..d9ce85d144af 100644 --- a/clang/lib/Format/ObjCPropertyAttributeOrderFixer.h +++ b/clang/lib/Format/ObjCPropertyAttributeOrderFixer.h @@ -28,12 +28,12 @@ class ObjCPropertyAttributeOrderFixer : public TokenAnalyzer { void analyzeObjCPropertyDecl(const SourceManager &SourceMgr, const AdditionalKeywords &Keywords, tooling::Replacements &Fixes, - const FormatToken *Tok) const; + const FormatToken *Tok); void sortPropertyAttributes(const SourceManager &SourceMgr, tooling::Replacements &Fixes, const FormatToken *BeginTok, - const FormatToken *EndTok) const; + const FormatToken *EndTok); std::pair analyze(TokenAnnotator &Annotator, diff --git a/clang/lib/Format/TokenAnnotator.h b/clang/lib/Format/TokenAnnotator.h index 58e2cf79f488..05a6daa87d80 100644 --- a/clang/lib/Format/TokenAnnotator.h +++ b/clang/lib/Format/TokenAnnotator.h @@ -156,6 +156,11 @@ public: return First->is(tok::comment) ? First->getNextNonComment() : First; } + FormatToken *getLastNonComment() const { + assert(Last); + return Last->is(tok::comment) ? Last->getPreviousNonComment() : Last; + } + FormatToken *First; FormatToken *Last; diff --git a/clang/lib/Format/UnwrappedLineFormatter.cpp b/clang/lib/Format/UnwrappedLineFormatter.cpp index 40730cd53529..b4930c2e4621 100644 --- a/clang/lib/Format/UnwrappedLineFormatter.cpp +++ b/clang/lib/Format/UnwrappedLineFormatter.cpp @@ -346,14 +346,10 @@ private: return false; // Check if the found line starts a record. - const FormatToken *LastNonComment = Line->Last; + const auto *LastNonComment = Line->getLastNonComment(); + // There must be another token (usually `{`), because we chose a + // non-PPDirective and non-comment line that has a smaller level. assert(LastNonComment); - if (LastNonComment->is(tok::comment)) { - LastNonComment = LastNonComment->getPreviousNonComment(); - // There must be another token (usually `{`), because we chose a - // non-PPDirective and non-comment line that has a smaller level. - assert(LastNonComment); - } return isRecordLBrace(*LastNonComment); } } @@ -363,12 +359,9 @@ private: bool MergeShortFunctions = ShouldMergeShortFunctions(); - const FormatToken *FirstNonComment = TheLine->First; - if (FirstNonComment->is(tok::comment)) { - FirstNonComment = FirstNonComment->getNextNonComment(); - if (!FirstNonComment) - return 0; - } + const auto *FirstNonComment = TheLine->getFirstNonComment(); + if (!FirstNonComment) + return 0; // FIXME: There are probably cases where we should use FirstNonComment // instead of TheLine->First. diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index be0d4963a209..56de0f75928c 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -4787,6 +4787,18 @@ std::string CompilerInvocation::getModuleHash() const { if (getCodeGenOpts().DebugTypeExtRefs) HBuilder.addRange(getCodeGenOpts().DebugPrefixMap); + // Extend the signature with the affecting debug options. + if (getHeaderSearchOpts().ModuleFormat == "obj") { +#define DEBUGOPT(Name, Bits, Default) HBuilder.add(CodeGenOpts->Name); +#define VALUE_DEBUGOPT(Name, Bits, Default) HBuilder.add(CodeGenOpts->Name); +#define ENUM_DEBUGOPT(Name, Type, Bits, Default) \ + HBuilder.add(static_cast(CodeGenOpts->get##Name())); +#define BENIGN_DEBUGOPT(Name, Bits, Default) +#define BENIGN_VALUE_DEBUGOPT(Name, Bits, Default) +#define BENIGN_ENUM_DEBUGOPT(Name, Type, Bits, Default) +#include "clang/Basic/DebugOptions.def" + } + // Extend the signature with the enabled sanitizers, if at least one is // enabled. Sanitizers which cannot affect AST generation aren't hashed. SanitizerSet SanHash = getLangOpts().Sanitize; @@ -4833,6 +4845,7 @@ std::vector CompilerInvocationBase::getCC1CommandLine() const { void CompilerInvocation::resetNonModularOptions() { getLangOpts().resetNonModularOptions(); getPreprocessorOpts().resetNonModularOptions(); + getCodeGenOpts().resetNonModularOptions(getHeaderSearchOpts().ModuleFormat); } void CompilerInvocation::clearImplicitModuleBuildOptions() { diff --git a/clang/lib/Headers/bmiintrin.h b/clang/lib/Headers/bmiintrin.h index ffb94bea639a..bc7c8a03c5e2 100644 --- a/clang/lib/Headers/bmiintrin.h +++ b/clang/lib/Headers/bmiintrin.h @@ -19,7 +19,7 @@ to use it as a potentially faster version of BSF. */ #define __RELAXED_FN_ATTRS __attribute__((__always_inline__, __nodebug__)) -#define _tzcnt_u16(a) (__tzcnt_u16((a))) +#define _tzcnt_u16 __tzcnt_u16 /// Counts the number of trailing zero bits in the operand. /// @@ -71,7 +71,7 @@ _mm_tzcnt_32(unsigned int __X) return (int)__builtin_ia32_tzcnt_u32(__X); } -#define _tzcnt_u32(a) (__tzcnt_u32((a))) +#define _tzcnt_u32 __tzcnt_u32 #ifdef __x86_64__ @@ -109,7 +109,7 @@ _mm_tzcnt_64(unsigned long long __X) return (long long)__builtin_ia32_tzcnt_u64(__X); } -#define _tzcnt_u64(a) (__tzcnt_u64((a))) +#define _tzcnt_u64 __tzcnt_u64 #endif /* __x86_64__ */ @@ -121,14 +121,14 @@ _mm_tzcnt_64(unsigned long long __X) /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("bmi"))) -#define _andn_u32(a, b) (__andn_u32((a), (b))) +#define _andn_u32 __andn_u32 /* _bextr_u32 != __bextr_u32 */ -#define _blsi_u32(a) (__blsi_u32((a))) +#define _blsi_u32 __blsi_u32 -#define _blsmsk_u32(a) (__blsmsk_u32((a))) +#define _blsmsk_u32 __blsmsk_u32 -#define _blsr_u32(a) (__blsr_u32((a))) +#define _blsr_u32 __blsr_u32 /// Performs a bitwise AND of the second operand with the one's /// complement of the first operand. @@ -272,14 +272,14 @@ __blsr_u32(unsigned int __X) #ifdef __x86_64__ -#define _andn_u64(a, b) (__andn_u64((a), (b))) +#define _andn_u64 __andn_u64 /* _bextr_u64 != __bextr_u64 */ -#define _blsi_u64(a) (__blsi_u64((a))) +#define _blsi_u64 __blsi_u64 -#define _blsmsk_u64(a) (__blsmsk_u64((a))) +#define _blsmsk_u64 __blsmsk_u64 -#define _blsr_u64(a) (__blsr_u64((a))) +#define _blsr_u64 __blsr_u64 /// Performs a bitwise AND of the second operand with the one's /// complement of the first operand. diff --git a/clang/lib/IndexSerialization/SerializablePathCollection.cpp b/clang/lib/IndexSerialization/SerializablePathCollection.cpp index 34663738088e..bd5f861bf482 100644 --- a/clang/lib/IndexSerialization/SerializablePathCollection.cpp +++ b/clang/lib/IndexSerialization/SerializablePathCollection.cpp @@ -45,8 +45,8 @@ SerializablePathCollection::SerializablePathCollection( SysRootPath(Paths.addDirPath(SysRoot)), OutputFilePath(Paths.addDirPath(OutputFile)) {} -size_t SerializablePathCollection::tryStoreFilePath(const FileEntry &FE) { - auto FileIt = UniqueFiles.find(&FE); +size_t SerializablePathCollection::tryStoreFilePath(FileEntryRef FE) { + auto FileIt = UniqueFiles.find(FE); if (FileIt != UniqueFiles.end()) return FileIt->second; @@ -54,7 +54,7 @@ size_t SerializablePathCollection::tryStoreFilePath(const FileEntry &FE) { const auto FileIdx = Paths.addFilePath(Dir.Root, Dir.Path, sys::path::filename(FE.getName())); - UniqueFiles.try_emplace(&FE, FileIdx); + UniqueFiles.try_emplace(FE, FileIdx); return FileIdx; } diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index 4021d5031856..71cb665a5632 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -36,15 +36,19 @@ enum class OpenACCDirectiveKindEx { // identifies the first token), and doesn't fully handle 'enter data', 'exit // data', nor any of the 'atomic' variants, just the first token of each. So // this should only be used by `ParseOpenACCDirectiveKind`. -OpenACCDirectiveKindEx getOpenACCDirectiveKind(StringRef Name) { +OpenACCDirectiveKindEx getOpenACCDirectiveKind(Token Tok) { + if (!Tok.is(tok::identifier)) + return OpenACCDirectiveKindEx::Invalid; OpenACCDirectiveKind DirKind = - llvm::StringSwitch(Name) + llvm::StringSwitch( + Tok.getIdentifierInfo()->getName()) .Case("parallel", OpenACCDirectiveKind::Parallel) .Case("serial", OpenACCDirectiveKind::Serial) .Case("kernels", OpenACCDirectiveKind::Kernels) .Case("data", OpenACCDirectiveKind::Data) .Case("host_data", OpenACCDirectiveKind::HostData) .Case("loop", OpenACCDirectiveKind::Loop) + .Case("cache", OpenACCDirectiveKind::Cache) .Case("atomic", OpenACCDirectiveKind::Atomic) .Case("routine", OpenACCDirectiveKind::Routine) .Case("declare", OpenACCDirectiveKind::Declare) @@ -57,7 +61,8 @@ OpenACCDirectiveKindEx getOpenACCDirectiveKind(StringRef Name) { if (DirKind != OpenACCDirectiveKind::Invalid) return static_cast(DirKind); - return llvm::StringSwitch(Name) + return llvm::StringSwitch( + Tok.getIdentifierInfo()->getName()) .Case("enter", OpenACCDirectiveKindEx::Enter) .Case("exit", OpenACCDirectiveKindEx::Exit) .Default(OpenACCDirectiveKindEx::Invalid); @@ -65,8 +70,11 @@ OpenACCDirectiveKindEx getOpenACCDirectiveKind(StringRef Name) { // Since 'atomic' is effectively a compound directive, this will decode the // second part of the directive. -OpenACCAtomicKind getOpenACCAtomicKind(StringRef Name) { - return llvm::StringSwitch(Name) +OpenACCAtomicKind getOpenACCAtomicKind(Token Tok) { + if (!Tok.is(tok::identifier)) + return OpenACCAtomicKind::Invalid; + return llvm::StringSwitch( + Tok.getIdentifierInfo()->getName()) .Case("read", OpenACCAtomicKind::Read) .Case("write", OpenACCAtomicKind::Write) .Case("update", OpenACCAtomicKind::Update) @@ -74,20 +82,25 @@ OpenACCAtomicKind getOpenACCAtomicKind(StringRef Name) { .Default(OpenACCAtomicKind::Invalid); } -bool isOpenACCDirectiveKind(OpenACCDirectiveKind Kind, StringRef Tok) { +bool isOpenACCDirectiveKind(OpenACCDirectiveKind Kind, Token Tok) { + if (!Tok.is(tok::identifier)) + return false; + switch (Kind) { case OpenACCDirectiveKind::Parallel: - return Tok == "parallel"; + return Tok.getIdentifierInfo()->isStr("parallel"); case OpenACCDirectiveKind::Serial: - return Tok == "serial"; + return Tok.getIdentifierInfo()->isStr("serial"); case OpenACCDirectiveKind::Kernels: - return Tok == "kernels"; + return Tok.getIdentifierInfo()->isStr("kernels"); case OpenACCDirectiveKind::Data: - return Tok == "data"; + return Tok.getIdentifierInfo()->isStr("data"); case OpenACCDirectiveKind::HostData: - return Tok == "host_data"; + return Tok.getIdentifierInfo()->isStr("host_data"); case OpenACCDirectiveKind::Loop: - return Tok == "loop"; + return Tok.getIdentifierInfo()->isStr("loop"); + case OpenACCDirectiveKind::Cache: + return Tok.getIdentifierInfo()->isStr("cache"); case OpenACCDirectiveKind::ParallelLoop: case OpenACCDirectiveKind::SerialLoop: @@ -97,19 +110,19 @@ bool isOpenACCDirectiveKind(OpenACCDirectiveKind Kind, StringRef Tok) { return false; case OpenACCDirectiveKind::Atomic: - return Tok == "atomic"; + return Tok.getIdentifierInfo()->isStr("atomic"); case OpenACCDirectiveKind::Routine: - return Tok == "routine"; + return Tok.getIdentifierInfo()->isStr("routine"); case OpenACCDirectiveKind::Declare: - return Tok == "declare"; + return Tok.getIdentifierInfo()->isStr("declare"); case OpenACCDirectiveKind::Init: - return Tok == "init"; + return Tok.getIdentifierInfo()->isStr("init"); case OpenACCDirectiveKind::Shutdown: - return Tok == "shutdown"; + return Tok.getIdentifierInfo()->isStr("shutdown"); case OpenACCDirectiveKind::Set: - return Tok == "set"; + return Tok.getIdentifierInfo()->isStr("set"); case OpenACCDirectiveKind::Update: - return Tok == "update"; + return Tok.getIdentifierInfo()->isStr("update"); case OpenACCDirectiveKind::Invalid: return false; } @@ -118,20 +131,22 @@ bool isOpenACCDirectiveKind(OpenACCDirectiveKind Kind, StringRef Tok) { OpenACCDirectiveKind ParseOpenACCEnterExitDataDirective(Parser &P, Token FirstTok, - StringRef FirstTokSpelling, OpenACCDirectiveKindEx ExtDirKind) { Token SecondTok = P.getCurToken(); if (SecondTok.isAnnotation()) { - P.Diag(FirstTok, diag::err_acc_invalid_directive) << 0 << FirstTokSpelling; + P.Diag(FirstTok, diag::err_acc_invalid_directive) + << 0 << FirstTok.getIdentifierInfo(); return OpenACCDirectiveKind::Invalid; } - std::string SecondTokSpelling = P.getPreprocessor().getSpelling(SecondTok); - - if (!isOpenACCDirectiveKind(OpenACCDirectiveKind::Data, SecondTokSpelling)) { - P.Diag(FirstTok, diag::err_acc_invalid_directive) - << 1 << FirstTokSpelling << SecondTokSpelling; + if (!isOpenACCDirectiveKind(OpenACCDirectiveKind::Data, SecondTok)) { + if (!SecondTok.is(tok::identifier)) + P.Diag(SecondTok, diag::err_expected) << tok::identifier; + else + P.Diag(FirstTok, diag::err_acc_invalid_directive) + << 1 << FirstTok.getIdentifierInfo()->getName() + << SecondTok.getIdentifierInfo()->getName(); return OpenACCDirectiveKind::Invalid; } @@ -149,9 +164,7 @@ OpenACCAtomicKind ParseOpenACCAtomicKind(Parser &P) { if (AtomicClauseToken.isAnnotation()) return OpenACCAtomicKind::Update; - std::string AtomicClauseSpelling = - P.getPreprocessor().getSpelling(AtomicClauseToken); - OpenACCAtomicKind AtomicKind = getOpenACCAtomicKind(AtomicClauseSpelling); + OpenACCAtomicKind AtomicKind = getOpenACCAtomicKind(AtomicClauseToken); // If we don't know what this is, treat it as 'nothing', and treat the rest of // this as a clause list, which, despite being invalid, is likely what the @@ -175,9 +188,8 @@ OpenACCDirectiveKind ParseOpenACCDirectiveKind(Parser &P) { } P.ConsumeToken(); - std::string FirstTokSpelling = P.getPreprocessor().getSpelling(FirstTok); - OpenACCDirectiveKindEx ExDirKind = getOpenACCDirectiveKind(FirstTokSpelling); + OpenACCDirectiveKindEx ExDirKind = getOpenACCDirectiveKind(FirstTok); // OpenACCDirectiveKindEx is meant to be an extended list // over OpenACCDirectiveKind, so any value below Invalid is one of the @@ -187,14 +199,17 @@ OpenACCDirectiveKind ParseOpenACCDirectiveKind(Parser &P) { // immediately cast it and use it as that. if (ExDirKind >= OpenACCDirectiveKindEx::Invalid) { switch (ExDirKind) { - case OpenACCDirectiveKindEx::Invalid: - P.Diag(FirstTok, diag::err_acc_invalid_directive) - << 0 << FirstTokSpelling; + case OpenACCDirectiveKindEx::Invalid: { + if (!FirstTok.is(tok::identifier)) + P.Diag(FirstTok, diag::err_expected) << tok::identifier; + else + P.Diag(FirstTok, diag::err_acc_invalid_directive) + << 0 << FirstTok.getIdentifierInfo(); return OpenACCDirectiveKind::Invalid; + } case OpenACCDirectiveKindEx::Enter: case OpenACCDirectiveKindEx::Exit: - return ParseOpenACCEnterExitDataDirective(P, FirstTok, FirstTokSpelling, - ExDirKind); + return ParseOpenACCEnterExitDataDirective(P, FirstTok, ExDirKind); } } @@ -205,8 +220,7 @@ OpenACCDirectiveKind ParseOpenACCDirectiveKind(Parser &P) { // clause. Token SecondTok = P.getCurToken(); if (!SecondTok.isAnnotation() && - isOpenACCDirectiveKind(OpenACCDirectiveKind::Loop, - P.getPreprocessor().getSpelling(SecondTok))) { + isOpenACCDirectiveKind(OpenACCDirectiveKind::Loop, SecondTok)) { switch (DirKind) { default: // Nothing to do except in the below cases, as they should be diagnosed as @@ -237,10 +251,7 @@ void ParseOpenACCClauseList(Parser &P) { } // namespace -// Routine has an optional paren-wrapped name of a function in the local scope. -// We parse the name, emitting any diagnostics -ExprResult Parser::ParseOpenACCRoutineName() { - +ExprResult Parser::ParseOpenACCIDExpression() { ExprResult Res; if (getLangOpts().CPlusPlus) { Res = ParseCXXIdExpression(/*isAddressOfOperand=*/false); @@ -248,8 +259,10 @@ ExprResult Parser::ParseOpenACCRoutineName() { // There isn't anything quite the same as ParseCXXIdExpression for C, so we // need to get the identifier, then call into Sema ourselves. - if (expectIdentifier()) + if (Tok.isNot(tok::identifier)) { + Diag(Tok, diag::err_expected) << tok::identifier; return ExprError(); + } Token FuncName = getCurToken(); UnqualifiedId Name; @@ -268,6 +281,86 @@ ExprResult Parser::ParseOpenACCRoutineName() { return getActions().CorrectDelayedTyposInExpr(Res); } +/// OpenACC 3.3, section 2.10: +/// A 'var' in a cache directive must be a single array element or a simple +/// subarray. In C and C++, a simple subarray is an array name followed by an +/// extended array range specification in brackets, with a start and length such +/// as: +/// +/// arr[lower:length] +/// +bool Parser::ParseOpenACCCacheVar() { + ExprResult ArrayName = ParseOpenACCIDExpression(); + if (ArrayName.isInvalid()) + return true; + + // If the expression is invalid, just continue parsing the brackets, there + // is likely other useful diagnostics we can emit inside of those. + + BalancedDelimiterTracker SquareBrackets(*this, tok::l_square, + tok::annot_pragma_openacc_end); + + // Square brackets are required, so error here, and try to recover by moving + // until the next comma, or the close paren/end of pragma. + if (SquareBrackets.expectAndConsume()) { + SkipUntil(tok::comma, tok::r_paren, tok::annot_pragma_openacc_end, + Parser::StopBeforeMatch); + return true; + } + + ExprResult Lower = getActions().CorrectDelayedTyposInExpr(ParseExpression()); + if (Lower.isInvalid()) + return true; + + // The 'length' expression is optional, as this could be a single array + // element. If there is no colon, we can treat it as that. + if (getCurToken().is(tok::colon)) { + ConsumeToken(); + ExprResult Length = + getActions().CorrectDelayedTyposInExpr(ParseExpression()); + if (Length.isInvalid()) + return true; + } + + // Diagnose the square bracket being in the wrong place and continue. + return SquareBrackets.consumeClose(); +} + +/// OpenACC 3.3, section 2.10: +/// In C and C++, the syntax of the cache directive is: +/// +/// #pragma acc cache ([readonly:]var-list) new-line +void Parser::ParseOpenACCCacheVarList() { + // If this is the end of the line, just return 'false' and count on the close + // paren diagnostic to catch the issue. + if (getCurToken().isAnnotation()) + return; + + // The VarList is an optional `readonly:` followed by a list of a variable + // specifications. First, see if we have `readonly:`, else we back-out and + // treat it like the beginning of a reference to a potentially-existing + // `readonly` variable. + if (getCurToken().is(tok::identifier) && + getCurToken().getIdentifierInfo()->isStr("readonly") && + NextToken().is(tok::colon)) { + // Consume both tokens. + ConsumeToken(); + ConsumeToken(); + // FIXME: Record that this is a 'readonly' so that we can use that during + // Sema/AST generation. + } + + bool FirstArray = true; + while (!getCurToken().isOneOf(tok::r_paren, tok::annot_pragma_openacc_end)) { + if (!FirstArray) + ExpectAndConsume(tok::comma); + FirstArray = false; + if (ParseOpenACCCacheVar()) + SkipUntil(tok::r_paren, tok::annot_pragma_openacc_end, tok::comma, + StopBeforeMatch); + } +} + void Parser::ParseOpenACCDirective() { OpenACCDirectiveKind DirKind = ParseOpenACCDirectiveKind(*this); @@ -289,7 +382,9 @@ void Parser::ParseOpenACCDirective() { T.skipToEnd(); break; case OpenACCDirectiveKind::Routine: { - ExprResult RoutineName = ParseOpenACCRoutineName(); + // Routine has an optional paren-wrapped name of a function in the local + // scope. We parse the name, emitting any diagnostics + ExprResult RoutineName = ParseOpenACCIDExpression(); // If the routine name is invalid, just skip until the closing paren to // recover more gracefully. if (RoutineName.isInvalid()) @@ -298,7 +393,18 @@ void Parser::ParseOpenACCDirective() { T.consumeClose(); break; } + case OpenACCDirectiveKind::Cache: + ParseOpenACCCacheVarList(); + // The ParseOpenACCCacheVarList function manages to recover from failures, + // so we can always consume the close. + T.consumeClose(); + break; } + } else if (DirKind == OpenACCDirectiveKind::Cache) { + // Cache's paren var-list is required, so error here if it isn't provided. + // We know that the consumeOpen above left the first non-paren here, so + // diagnose, then continue as if it was completely omitted. + Diag(Tok, diag::err_expected) << tok::l_paren; } // Parses the list of clauses, if present. diff --git a/clang/lib/Rewrite/Rewriter.cpp b/clang/lib/Rewrite/Rewriter.cpp index ef2858990dd9..0896221dd0bd 100644 --- a/clang/lib/Rewrite/Rewriter.cpp +++ b/clang/lib/Rewrite/Rewriter.cpp @@ -412,12 +412,13 @@ bool Rewriter::overwriteChangedFiles() { unsigned OverwriteFailure = Diag.getCustomDiagID( DiagnosticsEngine::Error, "unable to overwrite file %0: %1"); for (buffer_iterator I = buffer_begin(), E = buffer_end(); I != E; ++I) { - const FileEntry *Entry = getSourceMgr().getFileEntryForID(I->first); - if (auto Error = - llvm::writeToOutput(Entry->getName(), [&](llvm::raw_ostream &OS) { - I->second.write(OS); - return llvm::Error::success(); - })) { + OptionalFileEntryRef Entry = getSourceMgr().getFileEntryRefForID(I->first); + llvm::SmallString<128> Path(Entry->getName()); + getSourceMgr().getFileManager().makeAbsolutePath(Path); + if (auto Error = llvm::writeToOutput(Path, [&](llvm::raw_ostream &OS) { + I->second.write(OS); + return llvm::Error::success(); + })) { Diag.Report(OverwriteFailure) << Entry->getName() << llvm::toString(std::move(Error)); AllWritten = false; diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index 9771aaa2f3b0..2c7ecf4610de 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -2084,8 +2084,8 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) { if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) { llvm::StringMap CallerFeatureMap; Context.getFunctionFeatureMap(CallerFeatureMap, FD); - if (!Builtin::evaluateRequiredTargetFeatures( - "sve", CallerFeatureMap)) + if (!Builtin::evaluateRequiredTargetFeatures("sve", CallerFeatureMap) && + !Builtin::evaluateRequiredTargetFeatures("sme", CallerFeatureMap)) Diag(D->getLocation(), diag::err_sve_vector_in_non_sve_target) << Ty; } }; diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 77c8334f3ca2..fc6ee6b2c5ab 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -712,8 +712,13 @@ static ExprResult SemaBuiltinDumpStruct(Sema &S, CallExpr *TheCall) { << 1 << TheCall->getDirectCallee() << PtrArgType; return ExprError(); } - const RecordDecl *RD = PtrArgType->getPointeeType()->getAsRecordDecl(); - + QualType Pointee = PtrArgType->getPointeeType(); + const RecordDecl *RD = Pointee->getAsRecordDecl(); + // Try to instantiate the class template as appropriate; otherwise, access to + // its data() may lead to a crash. + if (S.RequireCompleteType(PtrArgResult.get()->getBeginLoc(), Pointee, + diag::err_incomplete_type)) + return ExprError(); // Second argument is a callable, but we can't fully validate it until we try // calling it. QualType FnArgType = TheCall->getArg(1)->getType(); @@ -2995,58 +3000,15 @@ static QualType getNeonEltType(NeonTypeFlags Flags, ASTContext &Context, enum ArmStreamingType { ArmNonStreaming, ArmStreaming, ArmStreamingCompatible }; -static ArmStreamingType getArmStreamingFnType(const FunctionDecl *FD) { - if (FD->hasAttr()) - return ArmStreaming; - if (const auto *T = FD->getType()->getAs()) { - if (T->getAArch64SMEAttributes() & FunctionType::SME_PStateSMEnabledMask) - return ArmStreaming; - if (T->getAArch64SMEAttributes() & FunctionType::SME_PStateSMCompatibleMask) - return ArmStreamingCompatible; - } - return ArmNonStreaming; -} - -static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall, - const FunctionDecl *FD, - ArmStreamingType BuiltinType) { - ArmStreamingType FnType = getArmStreamingFnType(FD); - - if (FnType == ArmStreaming && BuiltinType == ArmNonStreaming) { - S.Diag(TheCall->getBeginLoc(), diag::warn_attribute_arm_sm_incompat_builtin) - << TheCall->getSourceRange() << "streaming"; - } - - if (FnType == ArmStreamingCompatible && - BuiltinType != ArmStreamingCompatible) { - S.Diag(TheCall->getBeginLoc(), diag::warn_attribute_arm_sm_incompat_builtin) - << TheCall->getSourceRange() << "streaming compatible"; - return; - } -} - -bool Sema::CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { - // Range check SVE intrinsics that take immediate values. - SmallVector, 3> ImmChecks; - - switch (BuiltinID) { - default: - return false; -#define GET_SVE_IMMEDIATE_CHECK -#include "clang/Basic/arm_sve_sema_rangechecks.inc" -#undef GET_SVE_IMMEDIATE_CHECK -#define GET_SME_IMMEDIATE_CHECK -#include "clang/Basic/arm_sme_sema_rangechecks.inc" -#undef GET_SME_IMMEDIATE_CHECK - } - +bool Sema::ParseSVEImmChecks( + CallExpr *TheCall, SmallVector, 3> &ImmChecks) { // Perform all the immediate checks for this builtin call. bool HasError = false; for (auto &I : ImmChecks) { int ArgNum, CheckTy, ElementSizeInBits; std::tie(ArgNum, CheckTy, ElementSizeInBits) = I; - typedef bool(*OptionSetCheckFnTy)(int64_t Value); + typedef bool (*OptionSetCheckFnTy)(int64_t Value); // Function that checks whether the operand (ArgNum) is an immediate // that is one of the predefined values. @@ -3178,6 +3140,54 @@ bool Sema::CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return HasError; } +static ArmStreamingType getArmStreamingFnType(const FunctionDecl *FD) { + if (FD->hasAttr()) + return ArmStreaming; + if (const auto *T = FD->getType()->getAs()) { + if (T->getAArch64SMEAttributes() & FunctionType::SME_PStateSMEnabledMask) + return ArmStreaming; + if (T->getAArch64SMEAttributes() & FunctionType::SME_PStateSMCompatibleMask) + return ArmStreamingCompatible; + } + return ArmNonStreaming; +} + +static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall, + const FunctionDecl *FD, + ArmStreamingType BuiltinType) { + ArmStreamingType FnType = getArmStreamingFnType(FD); + + if (FnType == ArmStreaming && BuiltinType == ArmNonStreaming) { + S.Diag(TheCall->getBeginLoc(), diag::warn_attribute_arm_sm_incompat_builtin) + << TheCall->getSourceRange() << "streaming"; + } + + if (FnType == ArmStreamingCompatible && + BuiltinType != ArmStreamingCompatible) { + S.Diag(TheCall->getBeginLoc(), diag::warn_attribute_arm_sm_incompat_builtin) + << TheCall->getSourceRange() << "streaming compatible"; + return; + } +} + +bool Sema::CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { + // Range check SVE intrinsics that take immediate values. + SmallVector, 3> ImmChecks; + + switch (BuiltinID) { + default: + return false; +#define GET_SVE_IMMEDIATE_CHECK +#include "clang/Basic/arm_sve_sema_rangechecks.inc" +#undef GET_SVE_IMMEDIATE_CHECK +#define GET_SME_IMMEDIATE_CHECK +#include "clang/Basic/arm_sme_sema_rangechecks.inc" +#undef GET_SME_IMMEDIATE_CHECK + } + + return ParseSVEImmChecks(TheCall, ImmChecks); +} + bool Sema::CheckNeonBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, CallExpr *TheCall) { if (const FunctionDecl *FD = getCurFunctionDecl()) { diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 87c78d742d0f..a345978bb870 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -9036,6 +9036,9 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, case ParsedAttr::AT_BPFPreserveAccessIndex: handleBPFPreserveAccessIndexAttr(S, D, AL); break; + case ParsedAttr::AT_BPFPreserveStaticOffset: + handleSimpleAttribute(S, D, AL); + break; case ParsedAttr::AT_BTFDeclTag: handleBTFDeclTagAttr(S, D, AL); break; diff --git a/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp b/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp index ffc7236d1e25..6c7a1601402e 100644 --- a/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "clang/AST/CharUnits.h" +#include "clang/AST/ParentMapContext.h" #include "clang/StaticAnalyzer/Checkers/BuiltinCheckerRegistration.h" #include "clang/StaticAnalyzer/Checkers/Taint.h" #include "clang/StaticAnalyzer/Core/BugReporter/BugType.h" @@ -34,20 +35,46 @@ using llvm::formatv; namespace { enum OOB_Kind { OOB_Precedes, OOB_Exceeds, OOB_Taint }; -class ArrayBoundCheckerV2 : - public Checker { +struct Messages { + std::string Short, Full; +}; + +// NOTE: The `ArraySubscriptExpr` and `UnaryOperator` callbacks are `PostStmt` +// instead of `PreStmt` because the current implementation passes the whole +// expression to `CheckerContext::getSVal()` which only works after the +// symbolic evaluation of the expression. (To turn them into `PreStmt` +// callbacks, we'd need to duplicate the logic that evaluates these +// expressions.) The `MemberExpr` callback would work as `PreStmt` but it's +// defined as `PostStmt` for the sake of consistency with the other callbacks. +class ArrayBoundCheckerV2 : public Checker, + check::PostStmt, + check::PostStmt> { BugType BT{this, "Out-of-bound access"}; BugType TaintBT{this, "Out-of-bound access", categories::TaintedData}; + void performCheck(const Expr *E, CheckerContext &C) const; + void reportOOB(CheckerContext &C, ProgramStateRef ErrorState, OOB_Kind Kind, - NonLoc Offset, std::string RegName, std::string Msg) const; + NonLoc Offset, Messages Msgs) const; static bool isFromCtypeMacro(const Stmt *S, ASTContext &AC); + static bool isInAddressOf(const Stmt *S, ASTContext &AC); + public: - void checkLocation(SVal l, bool isLoad, const Stmt *S, - CheckerContext &C) const; + void checkPostStmt(const ArraySubscriptExpr *E, CheckerContext &C) const { + performCheck(E, C); + } + void checkPostStmt(const UnaryOperator *E, CheckerContext &C) const { + if (E->getOpcode() == UO_Deref) + performCheck(E, C); + } + void checkPostStmt(const MemberExpr *E, CheckerContext &C) const { + if (E->isArrow()) + performCheck(E->getBase(), C); + } }; + } // anonymous namespace /// For a given Location that can be represented as a symbolic expression @@ -149,9 +176,11 @@ getSimplifiedOffsets(NonLoc offset, nonloc::ConcreteInt extent, // where the first one corresponds to "value below threshold" and the second // corresponds to "value at or above threshold". Returns {nullptr, nullptr} in // the case when the evaluation fails. +// If the optional argument CheckEquality is true, then use BO_EQ instead of +// the default BO_LT after consistently applying the same simplification steps. static std::pair compareValueToThreshold(ProgramStateRef State, NonLoc Value, NonLoc Threshold, - SValBuilder &SVB) { + SValBuilder &SVB, bool CheckEquality = false) { if (auto ConcreteThreshold = Threshold.getAs()) { std::tie(Value, Threshold) = getSimplifiedOffsets(Value, *ConcreteThreshold, SVB); } @@ -167,8 +196,10 @@ compareValueToThreshold(ProgramStateRef State, NonLoc Value, NonLoc Threshold, return {nullptr, State}; } } + const BinaryOperatorKind OpKind = CheckEquality ? BO_EQ : BO_LT; auto BelowThreshold = - SVB.evalBinOpNN(State, BO_LT, Value, Threshold, SVB.getConditionType()).getAs(); + SVB.evalBinOpNN(State, OpKind, Value, Threshold, SVB.getConditionType()) + .getAs(); if (BelowThreshold) return State->assume(*BelowThreshold); @@ -217,16 +248,19 @@ static std::string getShortMsg(OOB_Kind Kind, std::string RegName) { return formatv(ShortMsgTemplates[Kind], RegName); } -static std::string getPrecedesMsg(std::string RegName, NonLoc Offset) { +static Messages getPrecedesMsgs(const SubRegion *Region, NonLoc Offset) { + std::string RegName = getRegionName(Region); SmallString<128> Buf; llvm::raw_svector_ostream Out(Buf); Out << "Access of " << RegName << " at negative byte offset"; if (auto ConcreteIdx = Offset.getAs()) Out << ' ' << ConcreteIdx->getValue(); - return std::string(Buf); + return {getShortMsg(OOB_Precedes, RegName), std::string(Buf)}; } -static std::string getExceedsMsg(ASTContext &ACtx, std::string RegName, - NonLoc Offset, NonLoc Extent, SVal Location) { + +static Messages getExceedsMsgs(ASTContext &ACtx, const SubRegion *Region, + NonLoc Offset, NonLoc Extent, SVal Location) { + std::string RegName = getRegionName(Region); const auto *EReg = Location.getAsRegion()->getAs(); assert(EReg && "this checker only handles element access"); QualType ElemType = EReg->getElementType(); @@ -273,20 +307,18 @@ static std::string getExceedsMsg(ASTContext &ACtx, std::string RegName, Out << "s"; } - return std::string(Buf); -} -static std::string getTaintMsg(std::string RegName) { - SmallString<128> Buf; - llvm::raw_svector_ostream Out(Buf); - Out << "Access of " << RegName - << " with a tainted offset that may be too large"; - return std::string(Buf); + return {getShortMsg(OOB_Exceeds, RegName), std::string(Buf)}; } -void ArrayBoundCheckerV2::checkLocation(SVal Location, bool IsLoad, - const Stmt *LoadS, - CheckerContext &C) const { +static Messages getTaintMsgs(const SubRegion *Region, const char *OffsetName) { + std::string RegName = getRegionName(Region); + return {formatv("Potential out of bound access to {0} with tainted {1}", + RegName, OffsetName), + formatv("Access of {0} with a tainted {1} that may be too large", + RegName, OffsetName)}; +} +void ArrayBoundCheckerV2::performCheck(const Expr *E, CheckerContext &C) const { // NOTE: Instead of using ProgramState::assumeInBound(), we are prototyping // some new logic here that reasons directly about memory region extents. // Once that logic is more mature, we can bring it back to assumeInBound() @@ -297,12 +329,14 @@ void ArrayBoundCheckerV2::checkLocation(SVal Location, bool IsLoad, // have some flexibility in defining the base region, we can achieve // various levels of conservatism in our buffer overflow checking. + const SVal Location = C.getSVal(E); + // The header ctype.h (from e.g. glibc) implements the isXXXXX() macros as // #define isXXXXX(arg) (LOOKUP_TABLE[arg] & BITMASK_FOR_XXXXX) // and incomplete analysis of these leads to false positives. As even // accurate reports would be confusing for the users, just disable reports // from these macros: - if (isFromCtypeMacro(LoadS, C.getASTContext())) + if (isFromCtypeMacro(E, C.getASTContext())) return; ProgramStateRef State = C.getState(); @@ -331,9 +365,8 @@ void ArrayBoundCheckerV2::checkLocation(SVal Location, bool IsLoad, if (PrecedesLowerBound && !WithinLowerBound) { // We know that the index definitely precedes the lower bound. - std::string RegName = getRegionName(Reg); - std::string Msg = getPrecedesMsg(RegName, ByteOffset); - reportOOB(C, PrecedesLowerBound, OOB_Precedes, ByteOffset, RegName, Msg); + Messages Msgs = getPrecedesMsgs(Reg, ByteOffset); + reportOOB(C, PrecedesLowerBound, OOB_Precedes, ByteOffset, Msgs); return; } @@ -350,17 +383,38 @@ void ArrayBoundCheckerV2::checkLocation(SVal Location, bool IsLoad, if (ExceedsUpperBound) { if (!WithinUpperBound) { // We know that the index definitely exceeds the upper bound. - std::string RegName = getRegionName(Reg); - std::string Msg = getExceedsMsg(C.getASTContext(), RegName, ByteOffset, - *KnownSize, Location); - reportOOB(C, ExceedsUpperBound, OOB_Exceeds, ByteOffset, RegName, Msg); + if (isa(E) && isInAddressOf(E, C.getASTContext())) { + // ...but this is within an addressof expression, so we need to check + // for the exceptional case that `&array[size]` is valid. + auto [EqualsToThreshold, NotEqualToThreshold] = + compareValueToThreshold(ExceedsUpperBound, ByteOffset, *KnownSize, + SVB, /*CheckEquality=*/true); + if (EqualsToThreshold && !NotEqualToThreshold) { + // We are definitely in the exceptional case, so return early + // instead of reporting a bug. + C.addTransition(EqualsToThreshold); + return; + } + } + Messages Msgs = getExceedsMsgs(C.getASTContext(), Reg, ByteOffset, + *KnownSize, Location); + reportOOB(C, ExceedsUpperBound, OOB_Exceeds, ByteOffset, Msgs); return; } if (isTainted(State, ByteOffset)) { - // Both cases are possible, but the index is tainted, so report. + // Both cases are possible, but the offset is tainted, so report. std::string RegName = getRegionName(Reg); - std::string Msg = getTaintMsg(RegName); - reportOOB(C, ExceedsUpperBound, OOB_Taint, ByteOffset, RegName, Msg); + + // Diagnostic detail: "tainted offset" is always correct, but the + // common case is that 'idx' is tainted in 'arr[idx]' and then it's + // nicer to say "tainted index". + const char *OffsetName = "offset"; + if (const auto *ASE = dyn_cast(E)) + if (isTainted(State, ASE->getIdx(), C.getLocationContext())) + OffsetName = "index"; + + Messages Msgs = getTaintMsgs(Reg, OffsetName); + reportOOB(C, ExceedsUpperBound, OOB_Taint, ByteOffset, Msgs); return; } } @@ -374,17 +428,14 @@ void ArrayBoundCheckerV2::checkLocation(SVal Location, bool IsLoad, void ArrayBoundCheckerV2::reportOOB(CheckerContext &C, ProgramStateRef ErrorState, OOB_Kind Kind, - NonLoc Offset, std::string RegName, - std::string Msg) const { + NonLoc Offset, Messages Msgs) const { ExplodedNode *ErrorNode = C.generateErrorNode(ErrorState); if (!ErrorNode) return; - std::string ShortMsg = getShortMsg(Kind, RegName); - auto BR = std::make_unique( - Kind == OOB_Taint ? TaintBT : BT, ShortMsg, Msg, ErrorNode); + Kind == OOB_Taint ? TaintBT : BT, Msgs.Short, Msgs.Full, ErrorNode); // Track back the propagation of taintedness. if (Kind == OOB_Taint) @@ -413,6 +464,18 @@ bool ArrayBoundCheckerV2::isFromCtypeMacro(const Stmt *S, ASTContext &ACtx) { (MacroName == "isupper") || (MacroName == "isxdigit")); } +bool ArrayBoundCheckerV2::isInAddressOf(const Stmt *S, ASTContext &ACtx) { + ParentMapContext &ParentCtx = ACtx.getParentMapContext(); + do { + const DynTypedNodeList Parents = ParentCtx.getParents(*S); + if (Parents.empty()) + return false; + S = Parents[0].get(); + } while (isa_and_nonnull(S)); + const auto *UnaryOp = dyn_cast_or_null(S); + return UnaryOp && UnaryOp->getOpcode() == UO_AddrOf; +} + void ento::registerArrayBoundCheckerV2(CheckerManager &mgr) { mgr.registerChecker(); } diff --git a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp index a4799b5f762c..925fc90e3554 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp @@ -1072,6 +1072,9 @@ void StreamChecker::evalFtell(const FnDescription *Desc, const CallEvent &Call, ProgramStateRef StateFailed = State->BindExpr( CE, C.getLocationContext(), SVB.makeIntVal(-1, C.getASTContext().LongTy)); + // This function does not affect the stream state. + // Still we add success and failure state with the appropriate return value. + // StdLibraryFunctionsChecker can change these states (set the 'errno' state). C.addTransition(StateNotFailed); C.addTransition(StateFailed); } diff --git a/clang/test/Analysis/out-of-bounds-diagnostics.c b/clang/test/Analysis/out-of-bounds-diagnostics.c index da1573665fa7..769a8954f796 100644 --- a/clang/test/Analysis/out-of-bounds-diagnostics.c +++ b/clang/test/Analysis/out-of-bounds-diagnostics.c @@ -9,6 +9,14 @@ void arrayUnderflow(void) { // expected-note@-2 {{Access of 'array' at negative byte offset -12}} } +int underflowWithDeref(void) { + int *p = array; + --p; + return *p; + // expected-warning@-1 {{Out of bound access to memory preceding 'array'}} + // expected-note@-2 {{Access of 'array' at negative byte offset -4}} +} + int scanf(const char *restrict fmt, ...); void taintedIndex(void) { @@ -17,6 +25,38 @@ void taintedIndex(void) { // expected-note@-1 {{Taint originated here}} // expected-note@-2 {{Taint propagated to the 2nd argument}} array[index] = 5; + // expected-warning@-1 {{Potential out of bound access to 'array' with tainted index}} + // expected-note@-2 {{Access of 'array' with a tainted index that may be too large}} +} + +int *taintedIndexAfterTheEndPtr(void) { + // NOTE: Technically speaking, this testcase does not trigger any UB because + // &array[10] is the after-the-end pointer which is well-defined; but this is + // a bug-prone situation and far from the idiomatic use of `&array[size]`, so + // it's better to report an error. This report can be easily silenced by + // writing array+index instead of &array[index]. + int index; + scanf("%d", &index); + // expected-note@-1 {{Taint originated here}} + // expected-note@-2 {{Taint propagated to the 2nd argument}} + if (index < 0 || index > 10) + return array; + // expected-note@-2 {{Assuming 'index' is >= 0}} + // expected-note@-3 {{Left side of '||' is false}} + // expected-note@-4 {{Assuming 'index' is <= 10}} + // expected-note@-5 {{Taking false branch}} + return &array[index]; + // expected-warning@-1 {{Potential out of bound access to 'array' with tainted index}} + // expected-note@-2 {{Access of 'array' with a tainted index that may be too large}} +} + +void taintedOffset(void) { + int index; + scanf("%d", &index); + // expected-note@-1 {{Taint originated here}} + // expected-note@-2 {{Taint propagated to the 2nd argument}} + int *p = array + index; + p[0] = 5; // expected-warning@-1 {{Potential out of bound access to 'array' with tainted offset}} // expected-note@-2 {{Access of 'array' with a tainted offset that may be too large}} } @@ -27,6 +67,47 @@ void arrayOverflow(void) { // expected-note@-2 {{Access of 'array' at index 12, while it holds only 10 'int' elements}} } +void flippedOverflow(void) { + 12[array] = 5; + // expected-warning@-1 {{Out of bound access to memory after the end of 'array'}} + // expected-note@-2 {{Access of 'array' at index 12, while it holds only 10 'int' elements}} +} + +int *afterTheEndPtr(void) { + // This is an unusual but standard-compliant way of writing (array + 10). + return &array[10]; // no-warning +} + +int useAfterTheEndPtr(void) { + // ... but dereferencing the after-the-end pointer is still invalid. + return *afterTheEndPtr(); + // expected-warning@-1 {{Out of bound access to memory after the end of 'array'}} + // expected-note@-2 {{Access of 'array' at index 10, while it holds only 10 'int' elements}} +} + +int *afterAfterTheEndPtr(void) { + // This is UB, it's invalid to form an after-after-the-end pointer. + return &array[11]; + // expected-warning@-1 {{Out of bound access to memory after the end of 'array'}} + // expected-note@-2 {{Access of 'array' at index 11, while it holds only 10 'int' elements}} +} + +int *potentialAfterTheEndPtr(int idx) { + if (idx < 10) { /* ...do something... */ } + // expected-note@-1 {{Assuming 'idx' is >= 10}} + // expected-note@-2 {{Taking false branch}} + return &array[idx]; + // expected-warning@-1 {{Out of bound access to memory after the end of 'array'}} + // expected-note@-2 {{Access of 'array' at an overflowing index, while it holds only 10 'int' elements}} + // NOTE: On the idx >= 10 branch the normal "optimistic" behavior would've + // been continuing with the assumption that idx == 10 and the return value is + // a legitimate after-the-end pointer. The checker deviates from this by + // reporting an error because this situation is very suspicious and far from + // the idiomatic `&array[size]` expressions. If the report is FP, the + // developer can easily silence it by writing array+idx instead of + // &array[idx]. +} + int scalar; int scalarOverflow(void) { return (&scalar)[1]; @@ -41,12 +122,6 @@ int oneElementArrayOverflow(void) { // expected-note@-2 {{Access of 'oneElementArray' at index 1, while it holds only a single 'int' element}} } -short convertedArray(void) { - return ((short*)array)[47]; - // expected-warning@-1 {{Out of bound access to memory after the end of 'array'}} - // expected-note@-2 {{Access of 'array' at index 47, while it holds only 20 'short' elements}} -} - struct vec { int len; double elems[64]; @@ -64,6 +139,28 @@ double arrayInStructPtr(struct vec *pv) { // expected-note@-2 {{Access of the field 'elems' at index 64, while it holds only 64 'double' elements}} } +struct item { + int a, b; +} itemArray[20] = {0}; + +int arrayOfStructs(void) { + return itemArray[35].a; + // expected-warning@-1 {{Out of bound access to memory after the end of 'itemArray'}} + // expected-note@-2 {{Access of 'itemArray' at index 35, while it holds only 20 'struct item' elements}} +} + +int arrayOfStructsArrow(void) { + return (itemArray + 35)->b; + // expected-warning@-1 {{Out of bound access to memory after the end of 'itemArray'}} + // expected-note@-2 {{Access of 'itemArray' at index 35, while it holds only 20 'struct item' elements}} +} + +short convertedArray(void) { + return ((short*)array)[47]; + // expected-warning@-1 {{Out of bound access to memory after the end of 'array'}} + // expected-note@-2 {{Access of 'array' at index 47, while it holds only 20 'short' elements}} +} + struct two_bytes { char lo, hi; }; @@ -85,7 +182,9 @@ int intFromString(void) { } int intFromStringDivisible(void) { - // However, this is reported with indices/elements, because the extent happens to be a multiple of 4. + // However, this is reported with indices/elements, because the extent + // (of the string that consists of 'a', 'b', 'c' and '\0') happens to be a + // multiple of 4 bytes (= sizeof(int)). return ((const int*)"abc")[20]; // expected-warning@-1 {{Out of bound access to memory after the end of the string literal}} // expected-note@-2 {{Access of the string literal at index 20, while it holds only a single 'int' element}} diff --git a/clang/test/Analysis/out-of-bounds-new.cpp b/clang/test/Analysis/out-of-bounds-new.cpp index af4ec47d8358..f541bdf810d7 100644 --- a/clang/test/Analysis/out-of-bounds-new.cpp +++ b/clang/test/Analysis/out-of-bounds-new.cpp @@ -154,3 +154,29 @@ void test_dynamic_size2(unsigned m,unsigned n){ unsigned *U = nullptr; U = new unsigned[m + n + 1]; } + +//Test creating invalid references, which break the invariant that a reference +//is always holding a value, and could lead to nasty runtime errors. +//(This is not related to operator new, but placed in this file because the +//other test files are not C++.) +int array[10] = {0}; + +void test_after_the_end_reference() { + int &ref = array[10]; // expected-warning{{Out of bound access to memory}} +} + +void test_after_after_the_end_reference() { + int &ref = array[11]; // expected-warning{{Out of bound access to memory}} +} + +int test_reference_that_might_be_after_the_end(int idx) { + // This TC produces no warning because separate analysis of (idx == 10) is + // only introduced _after_ the creation of the reference ref. + if (idx < 0 || idx > 10) + return -2; + int &ref = array[idx]; + if (idx == 10) + return -1; + return ref; +} + diff --git a/clang/test/Analysis/taint-diagnostic-visitor.c b/clang/test/Analysis/taint-diagnostic-visitor.c index 67dc67e627b3..a3fa1639bffe 100644 --- a/clang/test/Analysis/taint-diagnostic-visitor.c +++ b/clang/test/Analysis/taint-diagnostic-visitor.c @@ -29,8 +29,8 @@ int taintDiagnosticOutOfBound(void) { int Array[] = {1, 2, 3, 4, 5}; scanf("%d", &index); // expected-note {{Taint originated here}} // expected-note@-1 {{Taint propagated to the 2nd argument}} - return Array[index]; // expected-warning {{Potential out of bound access to 'Array' with tainted offset}} - // expected-note@-1 {{Access of 'Array' with a tainted offset that may be too large}} + return Array[index]; // expected-warning {{Potential out of bound access to 'Array' with tainted index}} + // expected-note@-1 {{Access of 'Array' with a tainted index that may be too large}} } int taintDiagnosticDivZero(int operand) { diff --git a/clang/test/CXX/drs/dr5xx.cpp b/clang/test/CXX/drs/dr5xx.cpp index a3563481eac6..21a6646d4abc 100644 --- a/clang/test/CXX/drs/dr5xx.cpp +++ b/clang/test/CXX/drs/dr5xx.cpp @@ -1,20 +1,21 @@ -// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -// RUN: %clang_cc1 -std=c++23 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++98 %s -verify=expected,cxx98-11,cxx98-14,cxx98-17,cxx98 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++11 %s -verify=expected,cxx98-11,cxx98-14,cxx98-17,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++14 %s -verify=expected,cxx98-14,cxx98-17,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++17 %s -verify=expected,since-cxx17,cxx98-17,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++20 %s -verify=expected,since-cxx20,since-cxx17,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++23 %s -verify=expected,since-cxx23,since-cxx20,since-cxx17,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors // FIXME: This is included to avoid a diagnostic with no source location // pointing at the implicit operator new. We can't match such a diagnostic // with -verify. __extension__ typedef __SIZE_TYPE__ size_t; -void *operator new(size_t); // expected-error 0-1{{missing exception spec}} expected-note{{candidate}} +void *operator new(size_t); // #dr5xx-global-operator-new +// cxx98-error@-1 {{'operator new' is missing exception specification 'throw(std::bad_alloc)'}} #if __cplusplus > 201402L namespace std { enum class align_val_t : size_t {}; } -void *operator new(size_t, std::align_val_t); // expected-note{{candidate}} +void *operator new(size_t, std::align_val_t); // #dr5xx-global-operator-new-aligned #endif namespace dr500 { // dr500: dup 372 @@ -33,7 +34,8 @@ namespace dr501 { // dr501: yes struct A { friend void f() {} void g() { - void (*p)() = &f; // expected-error {{undeclared identifier}} + void (*p)() = &f; + // expected-error@-1 {{use of undeclared identifier 'f'}} } }; } @@ -45,7 +47,8 @@ namespace dr502 { // dr502: yes void q1() { f(e); } void q2() { Q arr[sizeof(E)]; f(arr); } void q3() { Q arr[e]; f(arr); } - void sanity() { Q arr[1]; f(arr); } // expected-error {{undeclared identifier 'f'}} + void sanity() { Q arr[1]; f(arr); } + // expected-error@-1 {{use of undeclared identifier 'f'}} }; int f(A::E); template int f(Q (&)[N]); @@ -53,14 +56,22 @@ namespace dr502 { // dr502: yes } namespace dr505 { // dr505: yes - const char *exts = "\e\(\{\[\%"; // expected-error 5{{use of non-standard escape}} - const char *unknown = "\Q"; // expected-error {{unknown escape sequence}} + const char *exts = "\e\(\{\[\%"; + // expected-error@-1 {{use of non-standard escape character '\e'}} + // expected-error@-2 {{use of non-standard escape character '\('}} + // expected-error@-3 {{use of non-standard escape character '\{'}} + // expected-error@-4 {{use of non-standard escape character '\['}} + // expected-error@-5 {{use of non-standard escape character '\%'}} + const char *unknown = "\Q"; + // expected-error@-1 {{unknown escape sequence '\Q'}} } namespace dr506 { // dr506: yes struct NonPod { ~NonPod(); }; void f(...); - void g(NonPod np) { f(np); } // expected-error {{cannot pass}} + void g(NonPod np) { f(np); } + // cxx98-error@-1 {{cannot pass object of non-POD type 'NonPod' through variadic function; call will abort at runtime}} + // since-cxx11-error@-2 {{cannot pass object of non-trivial type 'NonPod' through variadic function; call will abort at runtime}} } // FIXME: Add tests here once DR260 is resolved. @@ -71,15 +82,13 @@ namespace dr506 { // dr506: yes // dr510: na namespace dr512 { // dr512: yes - struct A { - A(int); + struct A { // #dr512-A + A(int); // #dr512-A-ctor }; union U { A a; }; -#if __cplusplus < 201103L - // expected-error@-2 {{has a non-trivial default constructor}} - // expected-note@-6 {{no default constructor}} - // expected-note@-6 {{suppressed by user-declared constructor}} -#endif + // cxx98-error@-1 {{union member 'a' has a non-trivial default constructor}} + // cxx98-note@#dr512-A {{because type 'dr512::A' has no default constructor}} + // cxx98-note@#dr512-A-ctor {{implicit default constructor suppressed by user-declared constructor}} } // dr513: na @@ -101,9 +110,7 @@ namespace dr515 { // dr515: sup 1017 struct A { int a; }; struct B { void f() { int k = sizeof(A::a); } }; -#if __cplusplus < 201103L - // expected-error@-2 {{invalid use of non-static data member}} -#endif + // cxx98-error@-1 {{invalid use of non-static data member 'a'}} } // dr516: na @@ -111,7 +118,8 @@ namespace dr515 { // dr515: sup 1017 namespace dr517 { // dr517: no // This is NDR, but we should diagnose it anyway. template struct S {}; - template int v = 0; // expected-error 0-1{{extension}} + template int v = 0; + // cxx98-11-error@-1 {{variable templates are a C++14 extension}} template struct S; template int v; @@ -121,18 +129,16 @@ namespace dr517 { // dr517: no // FIXME: These are both ill-formed. template struct S {}; - template int v = 0; // expected-error 0-1{{extension}} + template int v = 0; // FIXME: These are both ill-formed. template struct S {}; - template int v = 0; // expected-error 0-1{{extension}} + template int v = 0; } namespace dr518 { // dr518: yes c++11 enum E { e, }; -#if __cplusplus < 201103L - // expected-error@-2 {{C++11 extension}} -#endif + // cxx98-error@-1 {{commas at the end of enumerator lists are a C++11 extension}} } namespace dr519 { // dr519: yes @@ -156,7 +162,7 @@ namespace dr522 { // dr522: yes template void b2(volatile T * const *); template void b2(volatile T * const S::*); template void b2(volatile T * const S::* const *); - template void b2a(volatile T *S::* const *); // expected-note {{candidate template ignored: deduced type 'volatile int *dr522::S::*const *' of 1st parameter does not match adjusted type 'int *dr522::S::**' of argument}} + template void b2a(volatile T *S::* const *); // #dr522-b2a template struct Base {}; struct Derived : Base {}; @@ -174,22 +180,27 @@ namespace dr522 { // dr522: yes b2(pm); b2(a); b2(am); - b2a(am); // expected-error {{no matching function}} + b2a(am); + // expected-error@-1 {{no matching function for call to 'b2a'}} + // expected-note@#dr522-b2a {{candidate template ignored: deduced type 'volatile int *dr522::S::*const *' of 1st parameter does not match adjusted type 'int *dr522::S::**' of argument}} b3(d); b3(cd); } } namespace dr524 { // dr524: yes - template void f(T a, T b) { operator+(a, b); } // expected-error {{call}} + template void f(T a, T b) { operator+(a, b); } + // expected-error@-1 {{call to function 'operator+' that is neither visible in the template definition nor found by argument-dependent lookup}} + // expected-note@#dr524-f-N-S {{in instantiation of function template specialization 'dr524::f' requested here}} + // expected-note@#dr524-operator-plus {{'operator+' should be declared prior to the call site or in namespace 'dr524::N'}} struct S {}; void operator+(S, S); template void f(S, S); namespace N { struct S {}; } - void operator+(N::S, N::S); // expected-note {{should be declared}} - template void f(N::S, N::S); // expected-note {{instantiation}} + void operator+(N::S, N::S); // #dr524-operator-plus + template void f(N::S, N::S); // #dr524-f-N-S } namespace dr525 { // dr525: yes @@ -202,9 +213,11 @@ namespace dr525 { // dr525: yes } } namespace after { - template struct D { typename T::error e; }; // expected-error {{prior to '::'}} + template struct D { typename T::error e; }; + // expected-error@-1 {{type 'double' cannot be used prior to '::' because it has no members}} + // expected-note@#dr525-ppp {{in instantiation of template class 'dr525::after::D' requested here}} void g(D *ppp) { - delete ppp; // expected-note {{instantiation of}} + delete ppp; // #dr525-ppp } } } @@ -212,30 +225,36 @@ namespace dr525 { // dr525: yes namespace dr526 { // dr526: yes template struct S {}; template void f1(S s); - template void f2(S<(N)> s); // expected-note {{couldn't infer}} - template void f3(S<+N> s); // expected-note {{couldn't infer}} + template void f2(S<(N)> s); // #dr526-f2 + template void f3(S<+N> s); // #dr526-f3 template void g1(int (&)[N]); - template void g2(int (&)[(N)]); // expected-note {{couldn't infer}} - template void g3(int (&)[+N]); // expected-note {{couldn't infer}} + template void g2(int (&)[(N)]); // #dr526-g2 + template void g3(int (&)[+N]); // #dr526-g3 void test(int (&a)[3], S<3> s) { f1(s); - f2(s); // expected-error {{no matching}} - f3(s); // expected-error {{no matching}} + f2(s); + // expected-error@-1 {{no matching function for call to 'f2'}} + // expected-note@#dr526-f2 {{candidate template ignored: couldn't infer template argument 'N'}} + f3(s); + // expected-error@-1 {{no matching function for call to 'f3'}} + // expected-note@#dr526-f3 {{candidate template ignored: couldn't infer template argument 'N'}} g1(a); - g2(a); // expected-error {{no matching}} - g3(a); // expected-error {{no matching}} + g2(a); + // expected-error@-1 {{no matching function for call to 'g2'}} + // expected-note@#dr526-g2 {{candidate template ignored: couldn't infer template argument 'N'}} + g3(a); + // expected-error@-1 {{no matching function for call to 'g3'}} + // expected-note@#dr526-g3 {{candidate template ignored: couldn't infer template argument 'N'}} } template struct X { typedef int type; X::type v1; X<(N)>::type v2; + // cxx98-17-error@-1 {{missing 'typename' prior to dependent type name X<(N)>::type; implicit 'typename' is a C++20 extension}} X<+N>::type v3; -#if __cplusplus <= 201703L - // expected-error@-3 {{implicit 'typename' is a C++20 extension}} - // expected-error@-3 {{implicit 'typename' is a C++20 extension}} -#endif + // cxx98-17-error@-1 {{missing 'typename' prior to dependent type name X<+N>::type; implicit 'typename' is a C++20 extension}} }; } @@ -307,32 +326,48 @@ namespace dr531 { // dr531: partial void f(T) { T::error; } template void g(T, U) { T::error; } struct B { typename T::error error; }; - template struct C { typename T::error error; }; // expected-note {{here}} + template struct C { typename T::error error; }; // #dr531-C static T n; }; template T A::n = T::error; - void A::f(int) {} // expected-error {{requires 'template<>'}} - template void A::g(int, U) {} // expected-error {{should be empty}} - struct A::B {}; // expected-error {{requires 'template<>'}} - template struct A::C {}; // expected-error {{should be empty}} expected-error {{different kind of symbol}} - int A::n = 0; // expected-error {{requires 'template<>'}} - - template<> struct A { // expected-note 2{{here}} + void A::f(int) {} + // expected-error@-1 {{template specialization requires 'template<>'}} + template void A::g(int, U) {} + // expected-error@-1 {{template parameter list matching the non-templated nested type 'dr531::bad::A' should be empty}} + struct A::B {}; + // expected-error@-1 {{template specialization requires 'template<>'}} + template struct A::C {}; + // expected-error@-1 {{template parameter list matching the non-templated nested type 'dr531::bad::A' should be empty}} + // expected-error@-2 {{redefinition of 'C' as different kind of symbol}} + // expected-note@#dr531-C {{previous definition is here}} + int A::n = 0; + // expected-error@-1 {{template specialization requires 'template<>'}} + + template<> struct A { // #dr531-A-char void f(char); template void g(char, U); - struct B; // expected-note {{here}} + struct B; // #dr531-B template struct C; static char n; }; - template<> void A::f(char) {} // expected-error {{no function template matches}} + template<> void A::f(char) {} + // expected-error@-1 {{no function template matches function template specialization 'f'}} // FIXME: This is ill-formed; -pedantic-errors should reject. - template<> template void A::g(char, U) {} // expected-warning {{extraneous template parameter list}} - template<> struct A::B {}; // expected-error {{extraneous 'template<>'}} expected-error {{does not specialize}} + template<> template void A::g(char, U) {} + // expected-warning@-1 {{extraneous template parameter list in template specialization}} + // expected-note@#dr531-A-char {{'template<>' header not required for explicitly-specialized class 'dr531::bad::A' declared here}} + template<> struct A::B {}; + // expected-error@-1 {{extraneous 'template<>' in declaration of struct 'B'}} + // expected-error@-2 {{specialization of member 'dr531::bad::A::B' does not specialize an instantiated member}} + // expected-note@#dr531-B {{attempt to specialize declaration here}} // FIXME: This is ill-formed; -pedantic-errors should reject. - template<> template struct A::C {}; // expected-warning {{extraneous template parameter list}} - template<> char A::n = 0; // expected-error {{extraneous 'template<>'}} + template<> template struct A::C {}; + // expected-warning@-1 {{extraneous template parameter list in template specialization}} + // expected-note@#dr531-A-char {{'template<>' header not required for explicitly-specialized class 'dr531::bad::A' declared here}} + template<> char A::n = 0; + // expected-error@-1 {{extraneous 'template<>' in declaration of variable 'n'}} } namespace nested { @@ -346,10 +381,12 @@ namespace dr531 { // dr531: partial template void i(); }; template<> template void A::B::f() {} - template void A::B::g() {} // expected-error {{should be empty}} + template void A::B::g() {} + // expected-error@-1 {{template parameter list matching the non-templated nested type 'dr531::nested::A' should be empty ('template<>')}} template<> template template void A::B::h() {} - template template void A::B::i() {} // expected-error {{should be empty}} + template template void A::B::i() {} + // expected-error@-1 {{template parameter list matching the non-templated nested type 'dr531::nested::A' should be empty ('template<>')}} #if __cplusplus <= 201703L // FIXME: All of those declarations shouldn't crash in C++20 mode. @@ -357,8 +394,10 @@ namespace dr531 { // dr531: partial template<> template<> template void A::B::h() {} template<> template<> template<> void A::B::h() {} - template<> void A::B::f() {} // expected-error {{requires 'template<>'}} - template<> template void A::B::h() {} // expected-error {{should be empty}} + template<> void A::B::f() {} + // cxx98-17-error@-1 {{template specialization requires 'template<>'}} + template<> template void A::B::h() {} + // cxx98-17-error@-1 {{template parameter list matching the non-templated nested type 'dr531::nested::A::B' should be empty ('template<>')}} #endif } } @@ -381,10 +420,11 @@ namespace dr532 { // dr532: 3.5 // dr533: na -namespace dr534 { // dr534: yes +namespace dr534 { // dr534: 2.9 struct S {}; template void operator+(S, T); - template void operator+(S, T*) {} // expected-error {{function template partial spec}} + template void operator+(S, T*) {} + // expected-error@-1 {{function template partial specialization is not allowed}} } namespace dr535 { // dr535: yes @@ -423,43 +463,70 @@ namespace dr535 { // dr535: yes // dr538: na // dr539: yes -const dr539( // expected-error {{a type specifier is required}} - const a) { // expected-error {{unknown type name 'a'}} - const b; // expected-error {{a type specifier is required}} - new const; // expected-error {{expected a type}} - try {} catch (const n) {} // expected-error {{unknown type name 'n'}} - try {} catch (const) {} // expected-error {{expected a type}} - if (const n = 0) {} // expected-error {{a type specifier is required}} - switch (const n = 0) {} // expected-error {{a type specifier is required}} - while (const n = 0) {} // expected-error {{a type specifier is required}} - for (const n = 0; // expected-error {{a type specifier is required}} - const m = 0; ) {} // expected-error {{a type specifier is required}} - sizeof(const); // expected-error {{a type specifier is required}} +const dr539( +// expected-error@-1 {{a type specifier is required for all declarations}} + const a) { + // expected-error@-1 {{unknown type name 'a'}} + const b; + // expected-error@-1 {{a type specifier is required for all declarations}} + new const; + // expected-error@-1 {{expected a type}} + try {} catch (const n) {} + // expected-error@-1 {{unknown type name 'n'}} + try {} catch (const) {} + // expected-error@-1 {{expected a type}} + if (const n = 0) {} + // expected-error@-1 {{a type specifier is required for all declarations}} + switch (const n = 0) {} + // expected-error@-1 {{a type specifier is required for all declarations}} + while (const n = 0) {} + // expected-error@-1 {{a type specifier is required for all declarations}} + for (const n = 0; + // expected-error@-1 {{a type specifier is required for all declarations}} + const m = 0; ) {} + // expected-error@-1 {{a type specifier is required for all declarations}} + sizeof(const); + // expected-error@-1 {{a type specifier is required for all declarations}} struct S { - const n; // expected-error {{a type specifier is required}} - operator const(); // expected-error {{expected a type}} + const n; + // expected-error@-1 {{a type specifier is required for all declarations}} + operator const(); + // expected-error@-1 {{expected a type}} }; #if __cplusplus >= 201103L int arr[3]; // FIXME: The extra braces here are to avoid the parser getting too // badly confused when recovering here. We should fix this recovery. - { for (const n // expected-error {{unknown type name 'n'}} expected-note {{}} - : arr) ; {} } // expected-error +{{}} - (void) [](const) {}; // expected-error {{a type specifier is required}} - (void) [](const n) {}; // expected-error {{unknown type name 'n'}} - enum E : const {}; // expected-error {{expected a type}} - using T = const; // expected-error {{expected a type}} - auto f() -> const; // expected-error {{expected a type}} + { for (const n + // since-cxx11-error@-1 {{unknown type name 'n'}} + // since-cxx11-note@-2 {{}} + : arr) ; {} } + // since-cxx11-error@-1 +{{}} + (void) [](const) {}; + // since-cxx11-error@-1 {{a type specifier is required for all declarations}} + (void) [](const n) {}; + // since-cxx11-error@-1 {{unknown type name 'n'}} + enum E : const {}; + // since-cxx11-error@-1 {{expected a type}} + using T = const; + // since-cxx11-error@-1 {{expected a type}} + auto f() -> const; + // since-cxx11-error@-1 {{expected a type}} #endif } namespace dr540 { // dr540: yes typedef int &a; - typedef const a &a; // expected-warning {{has no effect}} + typedef const a &a; + // expected-warning@-1 {{'const' qualifier on reference type 'a' (aka 'int &') has no effect}} typedef const int &b; typedef b &b; - typedef const a &c; // expected-note {{previous}} expected-warning {{has no effect}} - typedef const b &c; // expected-error {{different}} expected-warning {{has no effect}} + typedef const a &c; // #dr540-typedef-a-c + // expected-warning@-1 {{'const' qualifier on reference type 'a' (aka 'int &') has no effect}} + typedef const b &c; // #dr540-typedef-b-c + // expected-error@#dr540-typedef-b-c {{typedef redefinition with different types ('const int &' vs 'int &')}} + // expected-note@#dr540-typedef-a-c {{previous definition is here}} + // expected-warning@#dr540-typedef-b-c {{'const' qualifier on reference type 'b' (aka 'const int &') has no effect}} } namespace dr541 { // dr541: yes @@ -476,9 +543,15 @@ namespace dr541 { // dr541: yes void x() { // These are type-dependent expressions, even though we could // determine that all calls have type 'int'. - X::type a; // expected-error +{{}} - X::type b; // expected-error +{{}} - X::type b; // expected-error +{{}} + X::type a; + // expected-error@-1 {{expected ';' after expression}} + // expected-error@-2 {{use of undeclared identifier 'a'}} + X::type b; + // expected-error@-1 {{expected ';' after expression}} + // expected-error@-2 {{use of undeclared identifier 'b'}} + X::type b; + // expected-error@-1 {{expected ';' after expression}} + // expected-error@-2 {{use of undeclared identifier 'b'}} typename X::type a; typename X::type b; @@ -490,28 +563,25 @@ namespace dr542 { // dr542: yes #if __cplusplus >= 201103L // In C++20 A and B are no longer aggregates and thus the constructor is // called, which fails. - struct A { A() = delete; int n; }; - A a[32] = {}; // ok, constructor not called -#if __cplusplus > 201703L - // expected-error@-2 {{call to deleted constructor}} - // expected-note@-3 {{in implicit initialization}} - // expected-note@-5 {{marked deleted here}} -#endif + struct A { A() = delete; int n; }; // #dr542-A + // ok, constructor not called + A a[32] = {}; // #dr542-a + // since-cxx20-error@-1 {{call to deleted constructor of 'A'}} + // since-cxx20-note@#dr542-A {{'A' has been explicitly marked deleted here}} + // since-cxx20-note@#dr542-a {{in implicit initialization of array element 0 with omitted initializer}} struct B { int n; private: - B() = default; + B() = default; // #dr542-B-ctor }; B b[32] = {}; // ok, constructor not called -#if __cplusplus > 201703L - // expected-error@-2 {{calling a private constructor}} - // expected-note@-5 {{declared private here}} -#endif + // since-cxx20-error@-1 {{calling a private constructor of class 'dr542::B'}} + // since-cxx20-note@#dr542-B-ctor {{declared private here}} #endif } -namespace dr543 { // dr543: yes +namespace dr543 { // dr543: 3.0 // In C++98+DR543, this is valid because value-initialization doesn't call a // trivial default constructor, so we never notice that defining the // constructor would be ill-formed. @@ -520,13 +590,11 @@ namespace dr543 { // dr543: yes // deleted, and value-initialization *does* call a deleted default // constructor, even if it is trivial. struct A { - const int n; + const int n; // #dr543-A-n }; A a = A(); -#if __cplusplus >= 201103L - // expected-error@-2 {{deleted}} - // expected-note@-5 {{would not be initialized}} -#endif + // since-cxx11-error@-1 {{call to implicitly-deleted default constructor of 'A'}} + // since-cxx11-note@#dr543-A-n {{default constructor of 'A' is implicitly deleted because field 'n' of const-qualified type 'const int' would not be initialized}} } namespace dr544 { // dr544: yes @@ -544,7 +612,7 @@ namespace dr546 { // dr546: yes template void A::f() { T::error; } } -namespace dr547 { // dr547: yes +namespace dr547 { // dr547: 3.2 template struct X; template struct X {}; template X f(T C::*) { return X(); } @@ -564,23 +632,17 @@ namespace dr551 { // dr551: yes c++11 // FIXME: This obviously should apply in C++98 mode too. template void f() {} template inline void f(); -#if __cplusplus >= 201103L - // expected-error@-2 {{cannot be 'inline'}} -#endif + // since-cxx11-error@-1 {{explicit instantiation cannot be 'inline'}} template inline void g() {} template inline void g(); -#if __cplusplus >= 201103L - // expected-error@-2 {{cannot be 'inline'}} -#endif + // since-cxx11-error@-1 {{explicit instantiation cannot be 'inline'}} template struct X { void f() {} }; template inline void X::f(); -#if __cplusplus >= 201103L - // expected-error@-2 {{cannot be 'inline'}} -#endif + // since-cxx11-error@-1 {{explicit instantiation cannot be 'inline'}} } namespace dr552 { // dr552: yes @@ -597,17 +659,21 @@ namespace dr553 { // Contrary to the apparent intention of the DR, operator new is not actually // looked up with a lookup mechanism that performs ADL; the standard says it // "is looked up in global scope", where it is not visible. - void *p = new (c) int; // expected-error {{no matching function}} + void *p = new (c) int; + // expected-error@-1 {{no matching function for call to 'operator new'}} + // since-cxx17-note@#dr5xx-global-operator-new-aligned {{candidate function not viable: no known conversion from 'dr553_class' to 'std::align_val_t' for 2nd argument}} + // expected-note@#dr5xx-global-operator-new {{candidate function not viable: requires 1 argument, but 2 were provided}} struct namespace_scope { - friend void *operator new(size_t, namespace_scope); // expected-error {{cannot be declared inside a namespace}} + friend void *operator new(size_t, namespace_scope); + // expected-error@-1 {{'operator new' cannot be declared inside a namespace}} }; } // dr554: na // dr556: na -namespace dr557 { // dr557: yes +namespace dr557 { // dr557: 3.1 template struct S { friend void f(S *); friend void g(S > *); @@ -618,12 +684,14 @@ namespace dr557 { // dr557: yes } } -namespace dr558 { // dr558: yes +namespace dr558 { // dr558: 2.9 wchar_t a = L'\uD7FF'; wchar_t b = L'\xD7FF'; - wchar_t c = L'\uD800'; // expected-error {{invalid universal character}} + wchar_t c = L'\uD800'; + // expected-error@-1 {{invalid universal character}} wchar_t d = L'\xD800'; - wchar_t e = L'\uDFFF'; // expected-error {{invalid universal character}} + wchar_t e = L'\uDFFF'; + // expected-error@-1 {{invalid universal character}} wchar_t f = L'\xDFFF'; wchar_t g = L'\uE000'; wchar_t h = L'\xE000'; @@ -656,14 +724,18 @@ namespace dr564 { // dr564: yes namespace dr565 { // dr565: yes namespace N { - template int f(T); // expected-note {{target}} + template int f(T); // #dr565-f } - using N::f; // expected-note {{using}} + using N::f; // #dr565-using template int f(T*); template void f(T); - template int f(T); // expected-error 0-1{{extension}} + template int f(T); + // cxx98-error@-1 {{default template arguments for a function template are a C++11 extension}} template int f(T, int = 0); - template int f(T); // expected-error {{conflicts with}} + template int f(T); + // expected-error@-1 {{declaration conflicts with target of using declaration already in scope}} + // expected-note@#dr565-f {{target of using declaration}} + // expected-note@#dr565-using {{using declaration}} } namespace dr566 { // dr566: yes @@ -674,7 +746,7 @@ namespace dr566 { // dr566: yes // dr567: na -namespace dr568 { // dr568: yes c++11 +namespace dr568 { // dr568: 3.0 c++11 // FIXME: This is a DR issue against C++98, so should probably apply there // too. struct x { int y; }; @@ -704,17 +776,13 @@ namespace dr568 { // dr568: yes c++11 void f(...); void g(trivial t) { f(t); } -#if __cplusplus < 201103L - // expected-error@-2 {{non-POD}} -#endif + // cxx98-error@-1 {{cannot pass object of non-POD type 'trivial' through variadic function; call will abort at runtime}} void jump() { goto x; -#if __cplusplus < 201103L - // expected-error@-2 {{cannot jump}} - // expected-note@+2 {{non-POD}} -#endif - trivial t; + // cxx98-error@-1 {{cannot jump from this goto statement to its label}} + // cxx98-note@#dr568-t {{jump bypasses initialization of non-POD variable}} + trivial t; // #dr568-t x: ; } } @@ -723,22 +791,24 @@ namespace dr569 { // dr569: yes c++11 // FIXME: This is a DR issue against C++98, so should probably apply there // too. ;;;;; -#if __cplusplus < 201103L - // expected-error@-2 {{C++11 extension}} -#endif + // cxx98-error@-1 {{C++11 extension}} } namespace dr570 { // dr570: dup 633 int n; - int &r = n; // expected-note {{previous}} - int &r = n; // expected-error {{redefinition}} + int &r = n; // #dr570-r + int &r = n; + // expected-error@-1 {{redefinition of 'r'}} + // expected-note@#dr570-r {{previous definition is here}} } namespace dr571 { // dr571 unknown // FIXME: Add a codegen test. typedef int &ir; int n; - const ir r = n; // expected-warning {{has no effect}} FIXME: Test if this has internal linkage. + // FIXME: Test if this has internal linkage. + const ir r = n; + // expected-warning@-1 {{'const' qualifier on reference type 'ir' (aka 'int &') has no effect}} } namespace dr572 { // dr572: yes @@ -750,76 +820,94 @@ namespace dr573 { // dr573: no void *a; int *b = reinterpret_cast(a); void (*c)() = reinterpret_cast(a); + // cxx98-error@-1 {{cast between pointer-to-function and pointer-to-object is an extension}} void *d = reinterpret_cast(c); -#if __cplusplus < 201103L - // expected-error@-3 {{extension}} - // expected-error@-3 {{extension}} -#endif - void f() { delete a; } // expected-error {{cannot delete}} - int n = d - a; // expected-error {{arithmetic on pointers to void}} + // cxx98-error@-1 {{cast between pointer-to-function and pointer-to-object is an extension}} + void f() { delete a; } + // expected-error@-1 {{cannot delete expression with pointer-to-'void' type 'void *'}} + int n = d - a; + // expected-error@-1 {{arithmetic on pointers to void}} // FIXME: This is ill-formed. template struct S; template struct T; } -namespace dr574 { // dr574: yes +namespace dr574 { // dr574: 3.0 struct A { - A &operator=(const A&) const; // expected-note {{different qualifiers}} + A &operator=(const A&) const; // #dr574-A-copy-assign }; struct B { - B &operator=(const B&) volatile; // expected-note {{different qualifiers}} + B &operator=(const B&) volatile; // #dr574-B-copy-assign }; #if __cplusplus >= 201103L struct C { - C &operator=(const C&) &; // #574-overload1 \ - // expected-note {{not viable}} \ - // expected-note {{here}} - + C &operator=(const C&) &; // #dr574-C-copy-assign }; struct D { - D &operator=(const D&) &&; // #574-overload2 \ - // expected-note {{not viable}} \ - // expected-note {{here}} + D &operator=(const D&) &&; // #dr574-D-copy-assign }; void test(C c, D d) { c = c; - C() = c; // expected-error {{no viable}} - d = d; // expected-error {{no viable}} + C() = c; + // since-cxx11-error@-1 {{no viable overloaded '='}} + // since-cxx11-note@#dr574-C-copy-assign {{candidate function not viable: expects an lvalue for object argument}} + d = d; + // since-cxx11-error@-1 {{no viable overloaded '='}} + // since-cxx11-note@#dr574-D-copy-assign {{candidate function not viable: expects an rvalue for object argument}} D() = d; } #endif struct Test { - friend A &A::operator=(const A&); // expected-error {{does not match}} - friend B &B::operator=(const B&); // expected-error {{does not match}} + friend A &A::operator=(const A&); + // expected-error@-1 {{friend declaration of 'operator=' does not match any declaration in 'dr574::A'}} + // expected-note@#dr574-A-copy-assign {{candidate function has different qualifiers (expected unqualified but found 'const')}} + friend B &B::operator=(const B&); + // expected-error@-1 {{friend declaration of 'operator=' does not match any declaration in 'dr574::B'}} + // expected-note@#dr574-B-copy-assign {{candidate function has different qualifiers (expected unqualified but found 'volatile')}} #if __cplusplus >= 202302L - friend C &C::operator=(const C&); // expected-error {{conflicting types for 'operator='}} - friend D &D::operator=(const D&); // expected-error {{conflicting types for 'operator='}} __cplusplus >= 201103L + friend C &C::operator=(const C&); + // since-cxx23-error@-1 {{conflicting types for 'operator='}} + // since-cxx23-note@#dr574-C-copy-assign {{previous declaration is here}} + friend D &D::operator=(const D&); + // since-cxx23-error@-1 {{conflicting types for 'operator='}} + // since-cxx23-note@#dr574-D-copy-assign {{previous declaration is here}} #elif __cplusplus >= 201103L // FIXME: We shouldn't produce the 'cannot overload' diagnostics here. - friend C &C::operator=(const C&); // expected-error {{does not match}} \ - // expected-error {{cannot overload}} \ - // expected-note@#574-overload1 {{candidate}} - friend D &D::operator=(const D&); // expected-error {{does not match}} \ - // expected-error {{cannot overload}} \ - // expected-note@#574-overload2 {{candidate}} + friend C &C::operator=(const C&); // #dr574-test-C + // since-cxx11-error@#dr574-test-C {{cannot overload}} + // since-cxx11-note@#dr574-C-copy-assign {{previous declaration is here}} + // since-cxx11-error@#dr574-test-C {{friend declaration of 'operator=' does not match any declaration in 'dr574::C'}} + // since-cxx11-note@#dr574-C-copy-assign {{candidate function}} + friend D &D::operator=(const D&); // #dr574-test-D + // since-cxx11-error@#dr574-test-D {{cannot overload a member function without a ref-qualifier with a member function with ref-qualifier '&&'}} + // since-cxx11-note@#dr574-D-copy-assign {{previous declaration is here}} + // since-cxx11-error@#dr574-test-D {{friend declaration of 'operator=' does not match any declaration in 'dr574::D'}} + // since-cxx11-note@#dr574-D-copy-assign {{candidate function}} #endif }; } namespace dr575 { // dr575: yes - template void a(T); void a(...); // expected-error 0-1{{extension}} - template void b(T); void b(...); // expected-error 0-1{{extension}} - template void c(T); void c(...); // expected-error 0-1{{extension}} - template void d(T, int = T::value); void d(...); // expected-error {{cannot be used prior to '::'}} + template void a(T); void a(...); + // cxx98-error@-1 {{default template arguments for a function template are a C++11 extension}} + template void b(T); void b(...); + // cxx98-error@-1 {{default template arguments for a function template are a C++11 extension}} + template void c(T); void c(...); + // cxx98-error@-1 {{default template arguments for a function template are a C++11 extension}} + template void d(T, int = T::value); void d(...); + // expected-error@-1 {{type 'int' cannot be used prior to '::' because it has no members}} + // expected-note@#dr575-d {{in instantiation of default function argument expression for 'd' required here}} void x() { a(0); b(0); c(0); - d(0); // expected-note {{in instantiation of default function argument}} + d(0); // #dr575-d } - template void f(T* = 0); // expected-error 0-1{{extension}} - template void f(T = 0); // expected-error 0-1{{extension}} + template void f(T* = 0); + // cxx98-error@-1 {{default template arguments for a function template are a C++11 extension}} + template void f(T = 0); + // cxx98-error@-1 {{default template arguments for a function template are a C++11 extension}} void g() { f<>(); } template T &h(T *); @@ -827,32 +915,46 @@ namespace dr575 { // dr575: yes void *p = h((void*)0); } -namespace dr576 { // dr576: yes - typedef void f() {} // expected-error {{function definition declared 'typedef'}} - void f(typedef int n); // expected-error {{invalid storage class}} +namespace dr576 { // dr576: 3.5 + typedef void f() {} + // expected-error@-1 {{function definition declared 'typedef'}} + void f(typedef int n); + // expected-error@-1 {{invalid storage class specifier in function declarator}} void f(char c) { typedef int n; } } -namespace dr577 { // dr577: yes +namespace dr577 { // dr577: 3.5 typedef void V; typedef const void CV; void a(void); - void b(const void); // expected-error {{qualifiers}} + void b(const void); + // expected-error@-1 {{'void' as parameter must not have type qualifiers}} void c(V); - void d(CV); // expected-error {{qualifiers}} + void d(CV); + // expected-error@-1 {{'void' as parameter must not have type qualifiers}} void (*e)(void) = c; - void (*f)(const void); // expected-error {{qualifiers}} + void (*f)(const void); + // expected-error@-1 {{'void' as parameter must not have type qualifiers}} void (*g)(V) = a; - void (*h)(CV); // expected-error {{qualifiers}} - template void i(T); // expected-note 2{{requires 1 arg}} - template void j(void (*)(T)); // expected-note 2{{argument may not have 'void' type}} + void (*h)(CV); + // expected-error@-1 {{'void' as parameter must not have type qualifiers}} + template void i(T); // #dr577-i + template void j(void (*)(T)); // #dr577-j void k() { a(); c(); - i(); // expected-error {{no match}} - i(); // expected-error {{no match}} - j(0); // expected-error {{no match}} - j(0); // expected-error {{no match}} + i(); + // expected-error@-1 {{no matching function for call to 'i'}} + // expected-note@#dr577-i {{candidate function template not viable: requires 1 argument, but 0 were provided}} + i(); + // expected-error@-1 {{no matching function for call to 'i'}} + // expected-note@#dr577-i {{candidate function template not viable: requires 1 argument, but 0 were provided}} + j(0); + // expected-error@-1 {{no matching function for call to 'j'}} + // expected-note@#dr577-j {{candidate template ignored: substitution failure [with T = void]: argument may not have 'void' type}} + j(0); + // expected-error@-1 {{no matching function for call to 'j'}} + // expected-note@#dr577-j {{candidate template ignored: substitution failure [with T = const void]: argument may not have 'void' type}} } } @@ -861,10 +963,10 @@ namespace dr580 { // dr580: partial struct A { static C c; }; struct B { static C c; }; class C { - C(); // expected-note {{here}} - ~C(); // expected-note {{here}} + C(); // #dr580-C-ctor + ~C(); // #dr580-C-dtor - typedef int I; // expected-note 2{{here}} + typedef int I; // #dr580-I template struct X; template friend struct Y; template void f(); @@ -874,7 +976,9 @@ namespace dr580 { // dr580: partial template struct C::X {}; template struct Y {}; - template struct Z {}; // expected-error {{private}} + template struct Z {}; + // expected-error@-1 {{'I' is a private member of 'dr580::C'}} + // expected-note@#dr580-I {{implicitly declared private here}} struct C2 { class X { @@ -883,18 +987,25 @@ namespace dr580 { // dr580: partial friend struct A; }; class Y { - template struct A {}; // FIXME: We incorrectly accept this - // because we think C2::Y::A<...> might - // instantiate to C2::X::A + // FIXME: We incorrectly accept this + // because we think C2::Y::A<...> might + // instantiate to C2::X::A + template struct A {}; }; }; template void C::f() {} template void g() {} - template void h() {} // expected-error {{private}} + template void h() {} + // expected-error@-1 {{'I' is a private member of 'dr580::C'}} + // expected-note@#dr580-I {{implicitly declared private here}} C A::c; - C B::c; // expected-error 2{{private}} + C B::c; // #dr580-c + // expected-error@#dr580-c {{calling a private constructor of class 'dr580::C'}} + // expected-note@#dr580-C-ctor {{implicitly declared private here}} + // expected-error@#dr580-c {{variable of type 'C' has private destructor}} + // expected-note@#dr580-C-dtor {{implicitly declared private here}} } // dr582: na @@ -902,43 +1013,45 @@ namespace dr580 { // dr580: partial namespace dr583 { // dr583: 4 // see n3624 int *p; - bool b1 = p < 0; // expected-error {{ordered comparison between pointer and zero}} - bool b2 = p > 0; // expected-error {{ordered comparison between pointer and zero}} - bool b3 = p <= 0; // expected-error {{ordered comparison between pointer and zero}} - bool b4 = p >= 0; // expected-error {{ordered comparison between pointer and zero}} + bool b1 = p < 0; + // expected-error@-1 {{ordered comparison between pointer and zero ('int *' and 'int')}} + bool b2 = p > 0; + // expected-error@-1 {{ordered comparison between pointer and zero ('int *' and 'int')}} + bool b3 = p <= 0; + // expected-error@-1 {{ordered comparison between pointer and zero ('int *' and 'int')}} + bool b4 = p >= 0; + // expected-error@-1 {{ordered comparison between pointer and zero ('int *' and 'int')}} } // dr584: na -namespace dr585 { // dr585: yes - template struct T; +namespace dr585 { // dr585: 3.0 + template struct T; // #dr585-struct-T struct A { friend T; -#if __cplusplus <= 201402L - // expected-error@-2 {{a type specifier is required}} expected-error@-2 {{can only be classes or functions}} -#else - // expected-error@-4 {{use of class template 'T' requires template arguments; argument deduction not allowed in friend declaration}} - // expected-note@-7 {{here}} -#endif + // cxx98-14-error@-1 {{a type specifier is required for all declarations}} + // cxx98-14-error@-2 {{friends can only be classes or functions}} + // since-cxx17-error@-3 {{use of class template 'T' requires template arguments; argument deduction not allowed in friend declaration}} + // since-cxx17-note@#dr585-struct-T {{template is declared here}} // FIXME: It's not clear whether the standard allows this or what it means, // but the DR585 writeup suggests it as an alternative. - template friend T; // expected-error {{must use an elaborated type}} + template friend T; + // expected-error@-1 {{friend type templates must use an elaborated type}} }; - template class T> struct B { + template class T> struct B { // #dr585-template-T friend T; -#if __cplusplus <= 201402L - // expected-error@-2 {{a type specifier is required}} expected-error@-2 {{can only be classes or functions}} -#else - // expected-error@-4 {{use of template template parameter 'T' requires template arguments; argument deduction not allowed in friend declaration}} - // expected-note@-6 {{here}} -#endif - template friend T; // expected-error {{must use an elaborated type}} + // cxx98-14-error@-1 {{a type specifier is required for all declarations}} + // cxx98-14-error@-2 {{friends can only be classes or functions}} + // since-cxx17-error@-3 {{use of template template parameter 'T' requires template arguments; argument deduction not allowed in friend declaration}} + // since-cxx17-note@#dr585-template-T {{template is declared here}} + template friend T; + // expected-error@-1 {{friend type templates must use an elaborated type}} }; } // dr586: na -namespace dr587 { // dr587: yes +namespace dr587 { // dr587: 3.2 template void f(bool b, const T x, T y) { const T *p = &(b ? x : y); } @@ -948,14 +1061,18 @@ namespace dr587 { // dr587: yes } namespace dr588 { // dr588: yes - struct A { int n; }; // expected-note {{ambiguous}} + struct A { int n; }; // #dr588-A template int f() { struct S : A, T { int f() { return n; } } s; int a = s.f(); - int b = s.n; // expected-error {{found in multiple}} + int b = s.n; + // expected-error@-1 {{member 'n' found in multiple base classes of different types}} + // expected-note@#dr588-k {{in instantiation of function template specialization 'dr588::f' requested here}} + // expected-note@#dr588-A {{member found by ambiguous name lookup}} + // expected-note@#dr588-B {{member found by ambiguous name lookup}} } - struct B { int n; }; // expected-note {{ambiguous}} - int k = f(); // expected-note {{here}} + struct B { int n; }; // #dr588-B + int k = f(); // #dr588-k } namespace dr589 { // dr589: yes @@ -964,8 +1081,10 @@ namespace dr589 { // dr589: yes D f(); extern const B &b; bool a; - const B *p = &(a ? f() : b); // expected-error {{temporary}} - const B *q = &(a ? D() : b); // expected-error {{temporary}} + const B *p = &(a ? f() : b); + // expected-error@-1 {{taking the address of a temporary object of type 'const B'}} + const B *q = &(a ? D() : b); + // expected-error@-1 {{taking the address of a temporary object of type 'const B'}} } namespace dr590 { // dr590: yes @@ -990,7 +1109,8 @@ namespace dr591 { // dr591: no template struct A::B::C : A { // FIXME: Should find member of non-dependent base class A. - M m; // expected-error {{incomplete type 'M' (aka 'void'}} + M m; + // expected-error@-1 {{field has incomplete type 'M' (aka 'void'}} }; } @@ -1001,9 +1121,8 @@ namespace dr591 { // dr591: no namespace dr595 { // dr595: dup 1330 template struct X { void f() throw(T) {} -#if __cplusplus > 201402L - // expected-error@-2 {{ISO C++17 does not allow}} expected-note@-2 {{use 'noexcept}} -#endif + // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} + // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} }; struct S { X xs; @@ -1029,7 +1148,8 @@ namespace dr598 { // dr598: yes } int &g(void(*)(char)); int &r = g(N::f); - int &s = h(N::f); // expected-error {{undeclared}} + int &s = h(N::f); + // expected-error@-1 {{use of undeclared identifier 'h'}} int &t = h(N::i); } @@ -1037,16 +1157,23 @@ namespace dr599 { // dr599: partial typedef int Fn(); struct S { operator void*(); }; struct T { operator Fn*(); }; - struct U { operator int*(); operator void*(); }; // expected-note 2{{conversion}} + struct U { operator int*(); operator void*(); }; // #dr599-U struct V { operator int*(); operator Fn*(); }; void f(void *p, void (*q)(), S s, T t, U u, V v) { - delete p; // expected-error {{cannot delete}} - delete q; // expected-error {{cannot delete}} - delete s; // expected-error {{cannot delete}} - delete t; // expected-error {{cannot delete}} + delete p; + // expected-error@-1 {{cannot delete expression with pointer-to-'void' type 'void *'}} + delete q; + // expected-error@-1 {{cannot delete expression of type 'void (*)()'}} + delete s; + // expected-error@-1 {{cannot delete expression with pointer-to-'void' type 'void *'}} + delete t; + // expected-error@-1 {{cannot delete expression of type 'T'}} // FIXME: This is valid, but is rejected due to a non-conforming GNU // extension allowing deletion of pointers to void. - delete u; // expected-error {{ambiguous}} + delete u; + // expected-error@-1 {{ambiguous conversion of delete expression of type 'U' to a pointer}} + // expected-note@#dr599-U {{conversion to pointer type 'int *'}} + // expected-note@#dr599-U {{conversion to pointer type 'void *'}} delete v; } } diff --git a/clang/test/CXX/drs/dr6xx.cpp b/clang/test/CXX/drs/dr6xx.cpp index c5cd478c5e33..78604d480aa1 100644 --- a/clang/test/CXX/drs/dr6xx.cpp +++ b/clang/test/CXX/drs/dr6xx.cpp @@ -1,22 +1,24 @@ -// RUN: %clang_cc1 -std=c++98 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -// RUN: %clang_cc1 -std=c++11 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -// RUN: %clang_cc1 -std=c++14 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -// RUN: %clang_cc1 -std=c++17 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -// RUN: %clang_cc1 -std=c++20 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking -// RUN: %clang_cc1 -std=c++23 %s -verify -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking - -namespace dr600 { // dr600: yes +// RUN: %clang_cc1 -std=c++98 %s -verify=expected,cxx98-17,cxx98-14,cxx98 -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking +// RUN: %clang_cc1 -std=c++11 %s -verify=expected,cxx98-17,cxx11-17,cxx98-14,since-cxx11,cxx11 -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking +// RUN: %clang_cc1 -std=c++14 %s -verify=expected,cxx98-17,cxx11-17,cxx98-14,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking +// RUN: %clang_cc1 -std=c++17 %s -verify=expected,cxx98-17,cxx11-17,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking +// RUN: %clang_cc1 -std=c++20 %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking +// RUN: %clang_cc1 -std=c++23 %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors -fno-spell-checking + +namespace dr600 { // dr600: 2.8 struct S { void f(int); private: - void f(double); // expected-note {{declared private here}} + void f(double); // #dr600-f-double }; void g(S *sp) { sp->f(2); // access control is applied after overload resolution - sp->f(2.2); // expected-error {{is a private member}} + sp->f(2.2); + // expected-error@-1 {{'f' is a private member of 'dr600::S'}} + // expected-note@#dr600-f-double {{declared private here}} } } // namespace dr600 @@ -41,7 +43,8 @@ namespace dr601 { // dr601: yes #endif #if __INT_MAX__ == 0x7FFFFFFF -_Static_assert(0x80000000 < -1, "0x80000000 should be unsigned"); // expected-error {{C11}} +_Static_assert(0x80000000 < -1, "0x80000000 should be unsigned"); +// expected-error@-1 {{'_Static_assert' is a C11 extension}} #endif #if MAX > 0xFFFFFFFFFFFFFFFF && 0x8000000000000000 < -1 @@ -49,7 +52,7 @@ _Static_assert(0x80000000 < -1, "0x80000000 should be unsigned"); // expected-er #endif #if __cplusplus >= 201103L && __LLONG_MAX__ == 0x7FFFFFFFFFFFFFFF -static_assert(0x8000000000000000 < -1, "0x8000000000000000 should be unsigned"); // expected-error {{C11}} +static_assert(0x8000000000000000 < -1, "0x8000000000000000 should be unsigned"); #endif #undef MAX @@ -74,25 +77,27 @@ namespace dr603 { // dr603: yes template struct S {}; typedef S<'\001'> S1; typedef S<(1ul << __CHAR_BIT__) + 1> S1; -#if __cplusplus >= 201103L - // expected-error@-2 {{cannot be narrowed}} -#endif + // since-cxx11-error@-1 {{cannot be narrowed}} } // dr604: na // dr605 needs IRGen test -namespace dr606 { // dr606: yes +namespace dr606 { // dr606: 3.0 #if __cplusplus >= 201103L template struct S {}; - template void f(S &&); // expected-note {{expects an rvalue}} + template void f(S &&); // #dr606-f template void g(T &&); - template void h(const T &&); // expected-note {{expects an rvalue}} + template void h(const T &&); // #dr606-h void test(S s) { - f(s); // expected-error {{no match}} + f(s); + // since-cxx11-error@-1 {{no matching function for call to 'f'}} + // since-cxx11-note@#dr606-f {{candidate function [with T = int] not viable: expects an rvalue for 1st argument}} g(s); - h(s); // expected-error {{no match}} + h(s); + // since-cxx11-error@-1 {{no matching function for call to 'h'}} + // since-cxx11-note@#dr606-h {{candidate function [with T = dr606::S] not viable: expects an rvalue for 1st argument}} g(test); h(test); // ok, an rvalue reference can bind to a function lvalue @@ -152,33 +157,32 @@ namespace dr613 { // dr613: yes c++11 B &g(int); int an1 = sizeof(A::n); + // cxx98-error@-1 {{invalid use of non-static data member 'n'}} int an2 = sizeof(A::n + 1); // valid per dr850 + // cxx98-error@-1 {{invalid use of non-static data member 'n'}} int an3 = sizeof A::n; + // cxx98-error@-1 {{invalid use of non-static data member 'n'}} int an4 = sizeof(f(A::n)); + // cxx98-error@-1 {{invalid use of non-static data member 'n'}} int an5 = sizeof(g(A::n)); + // cxx98-error@-1 {{invalid use of non-static data member 'n'}} const std::type_info &an6 = typeid(A::n); + // cxx98-error@-1 {{invalid use of non-static data member 'n'}} const std::type_info &an7 = typeid(A::n + 1); + // cxx98-error@-1 {{invalid use of non-static data member 'n'}} const std::type_info &an8 = typeid(f(A::n)); - const std::type_info &an9 = typeid(g(A::n)); // expected-error {{non-static}} -#if __cplusplus < 201103L - // expected-error@-10 {{non-static}} - // expected-error@-10 {{non-static}} - // expected-error@-10 {{non-static}} - // expected-error@-10 {{non-static}} - // expected-error@-10 {{non-static}} - // expected-error@-10 {{non-static}} - // expected-error@-10 {{non-static}} - // expected-error@-10 {{non-static}} -#endif + // cxx98-error@-1 {{invalid use of non-static data member 'n'}} + const std::type_info &an9 = typeid(g(A::n)); + // expected-error@-1 {{invalid use of non-static data member 'n'}} void A::f() { int an1 = sizeof n; + // cxx98-error@-1 {{invalid use of member 'n' in static member function}} const std::type_info &an2 = typeid(n + 1); -#if __cplusplus < 201103L - // expected-error@-3 {{static}} - // expected-error@-3 {{static}} -#endif - const std::type_info &an3 = typeid(g(n)); // expected-error {{static}} + // cxx98-error@-1 {{invalid use of member 'n' in static member function}} + const std::type_info &an3 = typeid(g(n)); + // cxx98-error@-1 {{invalid use of member 'n' in static member function}} + // since-cxx11-error@-2 {{invalid use of non-static data member 'n'}} } } @@ -219,16 +223,20 @@ namespace dr619 { // dr619: yes struct S { static int x[10]; }; int x[]; - _Static_assert(sizeof(x) == sizeof(int) * 10, ""); // expected-error {{C11}} + _Static_assert(sizeof(x) == sizeof(int) * 10, ""); + // expected-error@-1 {{'_Static_assert' is a C11 extension}} extern int x[]; - _Static_assert(sizeof(x) == sizeof(int) * 10, ""); // expected-error {{C11}} + _Static_assert(sizeof(x) == sizeof(int) * 10, ""); + // expected-error@-1 {{'_Static_assert' is a C11 extension}} int S::x[]; - _Static_assert(sizeof(S::x) == sizeof(int) * 10, ""); // expected-error {{C11}} + _Static_assert(sizeof(S::x) == sizeof(int) * 10, ""); + // expected-error@-1 {{'_Static_assert' is a C11 extension}} void f() { extern int x[]; - sizeof(x); // expected-error {{incomplete}} + sizeof(x); + // expected-error@-1 {{invalid application of 'sizeof' to an incomplete type 'int[]'}} } } @@ -236,8 +244,10 @@ namespace dr619 { // dr619: yes namespace dr621 { // dr621: yes template T f(); - template<> int f() {} // expected-note {{previous}} - template<> int f() {} // expected-error {{redefinition}} + template<> int f() {} // #dr621-f + template<> int f() {} + // expected-error@-1 {{redefinition of 'f'}} + // expected-note@#dr621-f {{previous definition is here}} } // dr623: na @@ -247,40 +257,44 @@ namespace dr621 { // dr621: yes namespace dr625 { // dr625: yes template struct A {}; - A x = A(); // expected-error {{'auto' not allowed in template argument}} expected-error 0-1{{extension}} + A x = A(); + // cxx98-error@-1 {{'auto' type specifier is a C++11 extension}} + // expected-error@-2 {{'auto' not allowed in template argument}} void f(int); - void (*p)(auto) = f; // expected-error {{'auto' not allowed in function prototype}} expected-error 0-1{{extension}} + void (*p)(auto) = f; + // cxx98-error@-1 {{'auto' type specifier is a C++11 extension}} + // expected-error@-2 {{'auto' not allowed in function prototype}} } namespace dr626 { // dr626: yes #define STR(x) #x char c[2] = STR(c); // ok, type matches - wchar_t w[2] = STR(w); // expected-error {{initializing wide char array with non-wide string literal}} + wchar_t w[2] = STR(w); + // expected-error@-1 {{initializing wide char array with non-wide string literal}} } namespace dr627 { // dr627: yes void f() { - true a = 0; // expected-error +{{}} expected-warning {{unused}} + // FIXME: emitted diagnostic have a room for improvement + true a = 0; + // expected-error@-1 {{expected ';' after expression}} + // expected-error@-2 {{use of undeclared identifier 'a'}} + // expected-warning@-3 {{expression result unused}} } } // dr628: na -namespace dr629 { // dr629: yes +namespace dr629 { // dr629: 2.9 typedef int T; int n = 1; void f() { - auto T = 2; -#if __cplusplus < 201103L - // expected-error@-2 {{expected unqualified-id}} -#else - // expected-note@-4 {{previous}} -#endif + auto T = 2; // #dr629-T + // cxx98-error@-1 {{expected unqualified-id}} auto T(n); -#if __cplusplus >= 201103L - // expected-error@-2 {{redefinition of 'T'}} -#endif + // since-cxx11-error@-1 {{redefinition of 'T'}} + // since-cxx11-note@#dr629-T {{previous definition is here}} } } @@ -311,17 +325,20 @@ const bool MB_EQ_WC = ',' == L',' && '\\' == L'\\' && '"' == L'"' && '\'' == L'\''; #if __STDC_MB_MIGHT_NEQ_WC__ #ifndef __FreeBSD__ // PR22208, FreeBSD expects us to give a bad (but conforming) answer here. -_Static_assert(!MB_EQ_WC, "__STDC_MB_MIGHT_NEQ_WC__ but all basic source characters have same representation"); // expected-error {{C11}} +_Static_assert(!MB_EQ_WC, "__STDC_MB_MIGHT_NEQ_WC__ but all basic source characters have same representation"); +// expected-error@-1 {{'_Static_assert' is a C11 extension}} #endif #else -_Static_assert(MB_EQ_WC, "!__STDC_MB_MIGHT_NEQ_WC__ but some character differs"); // expected-error {{C11}} +_Static_assert(MB_EQ_WC, "!__STDC_MB_MIGHT_NEQ_WC__ but some character differs"); +// expected-error@-1 {{'_Static_assert' is a C11 extension}} #endif } // dr631: na namespace dr632 { // dr632: yes - struct S { int n; } s = {{5}}; // expected-warning {{braces}} + struct S { int n; } s = {{5}}; + // expected-warning@-1 {{braces around scalar initializer}} } // dr633: na @@ -334,12 +351,15 @@ namespace dr634 { // dr634: yes template int (&g(T))[sizeof f(T())]; int (&a)[sizeof(int)] = g(S()); int (&b)[1] = g(0); - int k = f(S()); // expected-error {{cannot pass}} + int k = f(S()); + // cxx98-error@-1 {{cannot pass object of non-POD type 'S' through variadic function; call will abort at runtime}} + // since-cxx11-error@-2 {{cannot pass object of non-trivial type 'S' through variadic function; call will abort at runtime}} } namespace dr635 { // dr635: yes template struct A { A(); ~A(); }; - template A::A() {} // expected-error {{cannot have template arguments}} + template A::A() {} + // expected-error@-1 {{out-of-line constructor for 'A' cannot have template arguments}} template A::~A() {} template struct B { B(); ~B(); }; @@ -349,22 +369,25 @@ namespace dr635 { // dr635: yes struct C { template C(); C(); }; template C::C() {} C::C() {} - template<> C::C() {} // expected-error {{constructor name}} expected-error {{unqualified-id}} + template<> C::C() {} + // expected-error@-1 {{qualified reference to 'C' is a constructor name rather than a type in this context}} + // expected-error@-2 {{expected unqualified-id}} /*FIXME: needed for error recovery:*/; template struct D { template D(); D(); }; - template D::D() {} // expected-note {{previous}} + template D::D() {} // #dr635-D template template D::D() {} - template D::D() {} // expected-error {{redefinition}} expected-error {{cannot have template arg}} + template D::D() {} // #dr635-D-T + // expected-error@#dr635-D-T {{out-of-line constructor for 'D' cannot have template arguments}} + // expected-error@#dr635-D-T {{redefinition of 'D'}} + // expected-note@#dr635-D {{previous definition is here}} } namespace dr637 { // dr637: yes void f(int i) { i = ++i + 1; i = i++ + 1; -#if __cplusplus < 201703L - // expected-warning@-2 {{unsequenced}} -#endif + // cxx98-14-warning@-1 {{multiple unsequenced modifications to 'i'}} } } @@ -380,10 +403,14 @@ namespace dr638 { // dr638: no class X { typedef int type; - template friend struct A::B; // expected-warning {{not supported}} - template friend void A::f(); // expected-warning {{not supported}} - template friend void A::g(); // expected-warning {{not supported}} - template friend void A::C::h(); // expected-warning {{not supported}} + template friend struct A::B; + // expected-warning@-1 {{dependent nested name specifier 'A::' for friend class declaration is not supported; turning off access control for 'X'}} + template friend void A::f(); + // expected-warning@-1 {{dependent nested name specifier 'A::' for friend class declaration is not supported; turning off access control for 'X'}} + template friend void A::g(); + // expected-warning@-1 {{dependent nested name specifier 'A::' for friend class declaration is not supported; turning off access control for 'X'}} + template friend void A::C::h(); + // expected-warning@-1 {{dependent nested name specifier 'A::C::' for friend class declaration is not supported; turning off access control for 'X'}} }; template<> struct A { @@ -399,9 +426,10 @@ namespace dr638 { // dr638: no }; } -namespace dr639 { // dr639: yes +namespace dr639 { // dr639: 3.3 void f(int i) { - void((i = 0) + (i = 0)); // expected-warning {{unsequenced}} + void((i = 0) + (i = 0)); + // expected-warning@-1 {{multiple unsequenced modifications to 'i'}} } } @@ -410,36 +438,46 @@ namespace dr641 { // dr641: yes struct abc; struct xyz { - xyz(); // expected-note 0-1{{candidate}} - xyz(xyz &); // expected-note 0-1{{candidate}} - - operator xyz &() = delete; // expected-error 0-1{{extension}} expected-warning {{will never be used}} - operator abc &() = delete; // expected-error 0-1{{extension}} + xyz(); // #dr641-xyz-ctor + xyz(xyz &); // #dr641-xyz-copy-ctor + + operator xyz &() = delete; + // expected-warning@-1 {{conversion function converting 'dr641::std_example::xyz' to itself will never be used}} + // cxx98-error@-2 {{deleted function definitions are a C++11 extension}} + operator abc &() = delete; + // cxx98-error@-1 {{deleted function definitions are a C++11 extension}} }; struct abc : xyz {}; template - void use(T &); // expected-note {{expects an lvalue}} + void use(T &); // #dr641-use void test() { - use(xyz()); // expected-error {{no match}} + use(xyz()); + // expected-error@-1 {{no matching function for call to 'use'}} + // expected-note@#dr641-use {{candidate function template not viable: expects an lvalue for 1st argument}} use(xyz()); -#if __cplusplus < 201103L - // expected-error-re@-2 {{no viable constructor copying parameter of type '{{.*}}xyz'}} -#endif + // cxx98-error@-1 {{no viable constructor copying parameter of type 'xyz'; C++98 requires a copy constructor when binding a reference to a temporary}} + // cxx98-note@#dr641-xyz-copy-ctor {{candidate constructor not viable: expects an lvalue for 1st argument}} + // cxx98-note@#dr641-xyz-ctor {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} } } template struct error { typedef typename T::error type; }; struct A { - template::type = 0> operator T() const; // expected-error 0-1{{extension}} + template::type = 0> operator T() const; + // cxx98-error@-1 {{default template arguments for a function template are a C++11 extension}} }; A a; - void f(A&); // expected-note 2{{candidate}} + void f(A&); // #dr641-f void g(const A ca) { - f(A()); // expected-error {{no match}} - f(ca); // expected-error {{no match}} + f(A()); + // expected-error@-1 {{no matching function for call to 'f'}} + // expected-note@#dr641-f {{candidate function not viable: expects an lvalue for 1st argument}} + f(ca); + // expected-error@-1 {{no matching function for call to 'f'}} + // expected-note@#dr641-f {{candidate function not viable: 1st argument ('const A') would lose const qualifier}} (void)A(); (void)ca; } @@ -450,7 +488,8 @@ namespace dr642 { // dr642: yes const int i = 2; { char i[i]; - _Static_assert(sizeof(i) == 2, ""); // expected-error {{C11}} + _Static_assert(sizeof(i) == 2, ""); + // expected-error@-1 {{'_Static_assert' is a C11 extension}} } } @@ -462,15 +501,18 @@ namespace dr642 { // dr642: yes } #if __cplusplus >= 201103L -namespace dr643 { // dr643: yes +namespace dr643 { // dr643: 3.2 struct A { int x; auto f() -> decltype(this->x); auto f(A &a) -> decltype(a.x); auto g() -> decltype(x); - auto h() -> decltype(this->y); // expected-error {{no member named 'y'}} - auto h(A &a) -> decltype(a.y); // expected-error {{no member named 'y'}} - auto i() -> decltype(y); // expected-error {{undeclared identifier 'y'}} + auto h() -> decltype(this->y); + // since-cxx11-error@-1 {{no member named 'y' in 'dr643::A'}} + auto h(A &a) -> decltype(a.y); + // since-cxx11-error@-1 {{no member named 'y' in 'dr643::A'}} + auto i() -> decltype(y); + // since-cxx11-error@-1 {{use of undeclared identifier 'y'}} int y; }; } @@ -522,45 +564,37 @@ namespace dr646 { // dr646: sup 981 #endif #if __cplusplus >= 201103L -namespace dr647 { // dr647: yes +namespace dr647 { // dr647: 3.1 // This is partially superseded by dr1358. struct A { constexpr virtual void f() const; constexpr virtual void g() const {} -#if __cplusplus <= 201703L - // expected-error@-2 {{virtual function cannot be constexpr}} -#endif + // cxx11-17-error@-1 {{virtual function cannot be constexpr}} }; - struct X { virtual void f() const; }; -#if __cplusplus <= 201703L - // expected-note@-2 {{overridden}} -#endif + struct X { virtual void f() const; }; // #dr647-f struct B : X { constexpr void f() const {} -#if __cplusplus <= 201703L - // expected-error@-2 {{virtual function cannot be constexpr}} -#endif + // cxx11-17-error@-1 {{virtual function cannot be constexpr}} + // cxx11-17-note@#dr647-f {{overridden virtual function is here}} }; - struct NonLiteral { NonLiteral() {} }; // expected-note {{not an aggregate and has no constexpr constructors}} + struct NonLiteral { NonLiteral() {} }; // #dr647-NonLiteral struct C { constexpr C(NonLiteral); - constexpr C(NonLiteral, int) {} // expected-error {{not a literal type}} + constexpr C(NonLiteral, int) {} + // since-cxx11-error@-1 {{constexpr constructor's 1st parameter type 'NonLiteral' is not a literal type}} + // since-cxx11-note@#dr647-NonLiteral {{'NonLiteral' is not literal because it is not an aggregate and has no constexpr constructors other than copy or move constructors}} constexpr C() try {} catch (...) {} -#if __cplusplus <= 201703L - // expected-error@-2 {{function try block in constexpr constructor is a C++20 extension}} -#endif -#if __cplusplus < 201402L - // expected-error@-5 {{use of this statement in a constexpr constructor is a C++14 extension}} -#endif + // cxx11-17-error@-1 {{function try block in constexpr constructor is a C++20 extension}} + // cxx11-error@-2 {{use of this statement in a constexpr constructor is a C++14 extension}} }; struct D { operator int() const; constexpr D(int) {} - D(float); // expected-note 2{{declared here}} + D(float); // #dr647-D-float-ctor }; constexpr int get(); struct E { @@ -574,12 +608,18 @@ namespace dr647 { // dr647: yes : n(D(0)), d(0) {} - constexpr E(int) // expected-error {{never produces a constant expression}} + constexpr E(int) + // since-cxx11-error@-1 {{constexpr constructor never produces a constant expression}} + // since-cxx11-note@#dr647-int-d {{non-constexpr constructor 'D' cannot be used in a constant expression}} + // since-cxx11-note@#dr647-D-float-ctor {{declared here}} : n(0), - d(0.0f) {} // expected-note {{non-constexpr constructor}} - constexpr E(float f) // expected-error {{never produces a constant expression}} + d(0.0f) {} // #dr647-int-d + constexpr E(float f) + // since-cxx11-error@-1 {{never produces a constant expression}} + // since-cxx11-note@#dr647-float-d {{non-constexpr constructor}} + // since-cxx11-note@#dr647-D-float-ctor {{declared here}} : n(get()), - d(D(0) + f) {} // expected-note {{non-constexpr constructor}} + d(D(0) + f) {} // #dr647-float-d }; } #endif @@ -594,11 +634,15 @@ namespace dr648 { // dr648: yes #endif #if __cplusplus >= 201103L -namespace dr649 { // dr649: yes -alignas(0x200000000) int n; // expected-error {{requested alignment}}1 -struct alignas(0x200000000) X {}; // expected-error {{requested alignment}} +namespace dr649 { // dr649: 3.5 +// Maximum alignment is 8192 bytes for Windows, and 4 GB for Linux +alignas(0x200000000) int n; +// since-cxx11-error-re@-1 {{{{requested alignment must be (8192|4294967296) bytes or smaller}}}} +struct alignas(0x200000000) X {}; +// since-cxx11-error-re@-1 {{{{requested alignment must be (8192|4294967296) bytes or smaller}}}} struct Y { - int n alignas(0x200000000); // expected-error {{requested alignment}} + int n alignas(0x200000000); + // since-cxx11-error-re@-1 {{{{requested alignment must be (8192|4294967296) bytes or smaller}}}} }; struct alignas(256) Z {}; // This part is superseded by dr2130 and eventually by aligned allocation support. @@ -633,17 +677,24 @@ namespace dr652 { // dr652: yes #if __cplusplus >= 201103L namespace dr654 { // dr654: sup 1423 void f() { - if (nullptr) {} // expected-warning {{implicit conversion of nullptr constant to 'bool'}} - bool b = nullptr; // expected-error {{cannot initialize a variable of type 'bool' with an rvalue of type 'std::nullptr_t'}} + if (nullptr) {} + // since-cxx11-warning@-1 {{implicit conversion of nullptr constant to 'bool'}} + bool b = nullptr; + // since-cxx11-error@-1 {{cannot initialize a variable of type 'bool' with an rvalue of type 'std::nullptr_t'}} if (nullptr == 0) {} if (nullptr != 0) {} - if (nullptr <= 0) {} // expected-error {{invalid operands}} - if (nullptr == 1) {} // expected-error {{invalid operands}} - if (!nullptr) {} // expected-warning {{implicit conversion of nullptr constant to 'bool'}} + if (nullptr <= 0) {} + // since-cxx11-error@-1 {{invalid operands to binary expression ('std::nullptr_t' and 'int')}} + if (nullptr == 1) {} + // since-cxx11-error@-1 {{invalid operands to binary expression ('std::nullptr_t' and 'int')}} + if (!nullptr) {} + // since-cxx11-warning@-1 {{implicit conversion of nullptr constant to 'bool'}} decltype(nullptr) n = 0; - static_cast(nullptr); // expected-error {{not allowed}} + static_cast(nullptr); + // since-cxx11-error@-1 {{static_cast from 'std::nullptr_t' to 'int' is not allowed}} (void)static_cast(0); - static_cast(1); // expected-error {{not allowed}} + static_cast(1); + // since-cxx11-error@-1 {{static_cast from 'int' to 'decltype(nullptr)' (aka 'std::nullptr_t') is not allowed}} void(true ? nullptr : 0); void(true ? 0 : nullptr); } @@ -651,47 +702,66 @@ namespace dr654 { // dr654: sup 1423 #endif namespace dr655 { // dr655: yes - struct A { A(int); }; // expected-note 2-3{{not viable}} - // expected-note@-1 {{'dr655::A' declared here}} + struct A { A(int); }; // #dr655-A struct B : A { - A a; // expected-note {{member is declared here}} + A a; // #dr655-a B(); - B(int) : B() {} // expected-error 0-1 {{C++11}} - B(int*) : A() {} // expected-error {{no matching constructor}} - // expected-error@-1 {{must explicitly initialize the member 'a'}} + B(int) : B() {} + // cxx98-error@-1 {{delegating constructors are permitted only in C++11}} + B(int*) : A() {} // #dr655-delegating-to-A + // expected-error@-1 {{no matching constructor for initialization of 'A'}} + // expected-note@#dr655-A {{candidate constructor not viable: requires 1 argument, but 0 were provided}} + // expected-note@#dr655-A {{candidate constructor (the implicit copy constructor) not viable: requires 1 argument, but 0 were provided}} + // since-cxx11-note@#dr655-A {{candidate constructor (the implicit move constructor) not viable: requires 1 argument, but 0 were provided}} + // expected-error@#dr655-delegating-to-A {{constructor for 'dr655::B' must explicitly initialize the member 'a' which does not have a default constructor}} + // expected-note@#dr655-a {{member is declared here}} + // expected-note@#dr655-A {{'dr655::A' declared here}} }; } namespace dr656 { // dr656: yes - struct A { A(const A&) = delete; }; // expected-error 0-1 {{C++11}} + struct A { A(const A&) = delete; }; + // cxx98-error@-1 {{deleted function definitions are a C++11 extension}} struct B : A {}; struct X { operator B(); } x; const A &r = x; - struct Y : private A { // expected-note 2{{here}} expected-note 2{{candidate}} + struct Y : private A { // #dr656-Y operator B() volatile; }; extern Y y; extern volatile Y vy; // Conversion not considered due to reference-related types. - const A &s = y; // expected-error {{private base class}} - const A &t = vy; // expected-error {{drops 'volatile'}} + const A &s = y; + // expected-error@-1 {{cannot cast 'const Y' to its private base class 'const A'}} + // expected-note@#dr656-Y {{declared private here}} + const A &t = vy; + // expected-error@-1 {{binding reference of type 'const A' to value of type 'volatile Y' drops 'volatile' qualifier}} struct C { operator struct D(); } c; struct D : C {}; const D &d = c; // ok, D not reference-related to C - template void accept(T); // expected-note {{candidate}} - template void accept(...) = delete; // expected-error 0-1 {{C++11}} expected-note {{candidate}} + template void accept(T); // #dr656-accept-T + template void accept(...) = delete; // #dr656-accept-var + // cxx98-error@-1 {{deleted function definitions are a C++11 extension}} void f() { accept(x); - accept(y); // expected-error {{private base class}} - accept(vy); // expected-error {{call to deleted}} expected-error {{no matching constructor}} + accept(y); + // expected-error@-1 {{cannot cast 'const Y' to its private base class 'const dr656::A'}} + // expected-note@#dr656-Y {{declared private here}} + accept(vy); // #dr656-vy + // expected-error@-1 {{call to deleted function 'accept'}} + // expected-note@#dr656-accept-var {{candidate function [with T = const dr656::A &] has been explicitly deleted}} + // expected-note@#dr656-accept-T {{candidate function template not viable: no known conversion from 'volatile Y' to 'const A &' for 1st argument}} + // expected-error@#dr656-vy {{no matching constructor for initialization of 'volatile Y'}} + // expected-note@#dr656-Y {{candidate constructor (the implicit copy constructor) not viable: 1st argument ('volatile Y') would lose volatile qualifier}} + // expected-note@#dr656-Y {{candidate constructor (the implicit default constructor) not viable: requires 0 arguments, but 1 was provided}} accept(c); } } namespace dr657 { // dr657: partial - struct Abs { virtual void x() = 0; }; // expected-note {{unimplemented pure virtual method 'x' in 'Abs'}} + struct Abs { virtual void x() = 0; }; // #dr657-Abs struct Der : public Abs { virtual void x(); }; struct Cnvt { template Cnvt(F); }; @@ -707,8 +777,11 @@ namespace dr657 { // dr657: partial // FIXME: The following examples demonstrate that we might be accepting the // above cases for the wrong reason. - struct C { C(Abs) {} }; // expected-error {{parameter type 'Abs' is an abstract class}} - struct Q { operator Abs() { __builtin_unreachable(); } } q; // expected-error {{return type 'Abs' is an abstract class}} + struct C { C(Abs) {} }; + // expected-error@-1 {{parameter type 'Abs' is an abstract class}} + // expected-note@#dr657-Abs {{unimplemented pure virtual method 'x' in 'Abs'}} + struct Q { operator Abs() { __builtin_unreachable(); } } q; + // expected-error@-1 {{return type 'Abs' is an abstract class}} #if __cplusplus >= 201703L // FIXME: We should *definitely* reject this. C c = Q().operator Abs(); @@ -728,24 +801,29 @@ namespace dr657 { // dr657: partial // dr658 FIXME: add codegen test #if __cplusplus >= 201103L -namespace dr659 { // dr659: yes +namespace dr659 { // dr659: 3.0 static_assert(alignof(char) == alignof(char&), ""); static_assert(alignof(int) == alignof(int&), ""); - int n = alignof(int(&)()); // expected-error {{application of 'alignof' to a function type}} - struct A; // expected-note {{forward}} - int m = alignof(A&); // expected-error {{application of 'alignof' to an incomplete type}} + int n = alignof(int(&)()); + // since-cxx11-error@-1 {{invalid application of 'alignof' to a function type}} + struct A; // #dr659-A + int m = alignof(A&); + // since-cxx11-error@-1 {{invalid application of 'alignof' to an incomplete type 'A'}} + // since-cxx11-note@#dr659-A {{forward declaration of 'dr659::A'}} } #endif #if __cplusplus >= 201103L -namespace dr660 { // dr660: yes +namespace dr660 { // dr660: 3.0 enum : int { a }; - enum class { b }; // expected-error {{requires a name}} + enum class { b }; + // since-cxx11-error@-1 {{scoped enumeration requires a name}} auto x = a; struct X { enum : int { a }; - enum class { b }; // expected-error {{requires a name}} + enum class { b }; + // since-cxx11-error@-1 {{scoped enumeration requires a name}} }; auto y = X::a; } @@ -756,12 +834,14 @@ namespace dr660 { // dr660: yes namespace dr662 { // dr662: yes template void f(T t) { T &tr = t; - T *tp = &t; // expected-error {{pointer to a reference}} + T *tp = &t; + // expected-error@-1 {{'tp' declared as a pointer to a reference of type 'int &'}} + // expected-note@#dr662-f-call {{in instantiation of function template specialization 'dr662::f' requested here}} #if __cplusplus >= 201103L auto *ap = &t; #endif } - void g(int n) { f(n); } // expected-note {{instantiation of}} + void g(int n) { f(n); } // #dr662-f-call } namespace dr663 { // dr663: sup P1949 @@ -779,47 +859,61 @@ namespace dr664 { // dr664: yes } #endif -namespace dr665 { // dr665: yes +namespace dr665 { // dr665: 2.8 struct A { virtual ~A(); }; struct B : A {} *b; - struct C : private A {} *c; // expected-note {{here}} + struct C : private A {} *c; // #dr665-C struct D : B, C {} *d; struct VB : virtual A {} *vb; - struct VC : private virtual A {} *vc; // expected-note {{here}} + struct VC : private virtual A {} *vc; // #dr665-VC struct VD : VB, VC {} *vd; void f() { (void)dynamic_cast(b); - (void)dynamic_cast(c); // expected-error {{private}} - (void)dynamic_cast(d); // expected-error {{ambiguous}} + (void)dynamic_cast(c); + // expected-error@-1 {{cannot cast 'dr665::C' to its private base class 'dr665::A'}} + // expected-note@#dr665-C {{declared private here}} + (void)dynamic_cast(d); + /* expected-error@-1 {{ambiguous conversion from derived class 'dr665::D' to base class 'dr665::A': + struct dr665::D -> B -> A + struct dr665::D -> C -> A}} */ (void)dynamic_cast(vb); - (void)dynamic_cast(vc); // expected-error {{private}}, even though it could be valid at runtime + (void)dynamic_cast(vc); // emitting diagnostic, even though it could be valid at runtime + // expected-error@-1 {{cannot cast 'dr665::VC' to its private base class 'dr665::A'}} + // expected-note@#dr665-VC {{declared private here}} (void)dynamic_cast(vd); } } -namespace dr666 { // dr666: yes +namespace dr666 { // dr666: 2.8 struct P { friend P operator*(P, P); P(int); } p(0); template int f(); template int f() { - T::type *p = 0; // expected-error {{missing 'typename'}} - int a(T::type); // expected-error {{missing 'typename'}} - return f(); // expected-error {{missing 'typename'}} + T::type *p = 0; + // expected-error@-1 {{missing 'typename' prior to dependent type name 'Y::type'}} + // expected-note@#dr666-f-Y {{in instantiation of function template specialization 'dr666::f' requested here}} + int a(T::type); + // expected-error@-1 {{missing 'typename' prior to dependent type name 'Y::type'}} + return f(); + // expected-error@-1 {{missing 'typename' prior to dependent type name 'Y::type'}} } struct X { static const int type = 0; }; struct Y { typedef int type; }; int a = f(); - int b = f(); // expected-note {{instantiation of}} + int b = f(); // #dr666-f-Y } // Triviality is entirely different in C++98. #if __cplusplus >= 201103L -namespace dr667 { // dr667: yes +namespace dr667 { // dr667: 8 struct A { - A() = default; // expected-warning {{explicitly defaulted default constructor is implicitly deleted}} expected-note{{replace 'default'}} - int &r; // expected-note {{because field 'r' of reference type 'int &' would not be initialized}} + A() = default; // #dr667-A-ctor + // since-cxx11-warning@-1 {{explicitly defaulted default constructor is implicitly deleted}} + // since-cxx11-note@#dr667-r {{default constructor of 'A' is implicitly deleted because field 'r' of reference type 'int &' would not be initialized}} + // since-cxx11-note@#dr667-A-ctor {{replace 'default' with 'delete'}} + int &r; // #dr667-r }; static_assert(!__is_trivially_constructible(A), ""); @@ -868,11 +962,13 @@ namespace dr669 { // dr669: yes } #endif -namespace dr671 { // dr671: yes - enum class E { e }; // expected-error 0-1 {{C++11}} +namespace dr671 { // dr671: 2.9 + enum class E { e }; + // cxx98-error@-1 {{scoped enumerations are a C++11 extension}} E e = static_cast(0); - int n = static_cast(E::e); // expected-error 0-1 {{C++11}} - int m = static_cast(e); // expected-error 0-1 {{C++11}} + int n = static_cast(E::e); + // cxx98-error@-1 {{use of enumeration in a nested name specifier is a C++11 extension}} + int m = static_cast(e); } // dr672 FIXME: add codegen test @@ -891,7 +987,8 @@ namespace dr673 { // dr673: yes C *c; D *d; E *e; - F *f; // expected-error {{unknown type name}} + F *f; + // expected-error@-1 {{unknown type name 'F'}} } namespace dr674 { // dr674: 8 @@ -907,17 +1004,22 @@ namespace dr674 { // dr674: 8 friend int dr674::f(int); friend int dr674::g(int); friend int dr674::h<>(int); - int n; // expected-note 2{{private}} + int n; // #dr674-X-n }; template int f(T) { return X().n; } int g(int) { return X().n; } - template int g(T) { return X().n; } // expected-error {{private}} - int h(int) { return X().n; } // expected-error {{private}} + template int g(T) { return X().n; } + // expected-error@-1 {{'n' is a private member of 'dr674::X'}} + // expected-note@#dr674-g-int {{in instantiation of function template specialization 'dr674::g' requested here}} + // expected-note@#dr674-X-n {{implicitly declared private here}} + int h(int) { return X().n; } + // expected-error@-1 {{'n' is a private member of 'dr674::X'}} + // expected-note@#dr674-X-n {{implicitly declared private here}} template int h(T) { return X().n; } template int f(int); - template int g(int); // expected-note {{in instantiation of}} + template int g(int); // #dr674-g-int template int h(int); @@ -935,27 +1037,35 @@ namespace dr674 { // dr674: 8 friend int Y::f(int); friend int Y::g(int); friend int Y::h<>(int); - int n; // expected-note 2{{private}} + int n; // #dr674-Z-n }; template int Y::f(T) { return Z().n; } int Y::g(int) { return Z().n; } - template int Y::g(T) { return Z().n; } // expected-error {{private}} - int Y::h(int) { return Z().n; } // expected-error {{private}} + template int Y::g(T) { return Z().n; } + // expected-error@-1 {{'n' is a private member of 'dr674::Z'}} + // expected-note@#dr674-Y-g-int {{in instantiation of function template specialization 'dr674::Y::g' requested here}} + // expected-note@#dr674-Z-n {{implicitly declared private here}} + int Y::h(int) { return Z().n; } + // expected-error@-1 {{'n' is a private member of 'dr674::Z'}} + // expected-note@#dr674-Z-n {{implicitly declared private here}} template int Y::h(T) { return Z().n; } // FIXME: Should the <> be required here? template int Y::f<>(int); - template int Y::g<>(int); // expected-note {{in instantiation of}} + template int Y::g<>(int); // #dr674-Y-g-int template int Y::h<>(int); } namespace dr675 { // dr675: dup 739 template struct A { T n : 1; }; #if __cplusplus >= 201103L - static_assert(A{1}.n < 0, ""); // expected-warning {{implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1}} - static_assert(A{1}.n < 0, ""); // expected-warning {{implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1}} - static_assert(A{1}.n < 0, ""); // expected-warning {{implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1}} + static_assert(A{1}.n < 0, ""); + // since-cxx11-warning@-1 {{implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1}} + static_assert(A{1}.n < 0, ""); + // since-cxx11-warning@-1 {{implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1}} + static_assert(A{1}.n < 0, ""); + // since-cxx11-warning@-1 {{implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1}} #endif } @@ -964,17 +1074,25 @@ namespace dr675 { // dr675: dup 739 namespace dr677 { // dr677: no struct A { void *operator new(std::size_t); - void operator delete(void*) = delete; // expected-error 0-1{{C++11}} expected-note {{deleted}} + void operator delete(void*) = delete; // #dr677-A-delete + // cxx98-error@-1 {{deleted function definitions are a C++11 extension}} }; struct B { void *operator new(std::size_t); - void operator delete(void*) = delete; // expected-error 0-1{{C++11}} expected-note 2{{deleted}} + void operator delete(void*) = delete; // #dr677-B-delete + // cxx98-error@-1 {{deleted function definitions are a C++11 extension}} virtual ~B(); }; - void f(A *p) { delete p; } // expected-error {{deleted}} + void f(A *p) { delete p; } + // expected-error@-1 {{attempt to use a deleted function}} + // expected-note@#dr677-A-delete {{'operator delete' has been explicitly marked deleted here}} // FIXME: This appears to be valid; we shouldn't even be looking up the 'operator delete' here. - void f(B *p) { delete p; } // expected-error {{deleted}} - B::~B() {} // expected-error {{deleted}} + void f(B *p) { delete p; } + // expected-error@-1 {{attempt to use a deleted function}} + // expected-note@#dr677-B-delete {{'operator delete' has been explicitly marked deleted here}} + B::~B() {} + // expected-error@-1 {{attempt to use a deleted function}} + // expected-note@#dr677-B-delete {{'operator delete' has been explicitly marked deleted here}} } // dr678 FIXME: check that the modules ODR check catches this @@ -982,24 +1100,31 @@ namespace dr677 { // dr677: no namespace dr679 { // dr679: yes struct X {}; template void operator+(X, X); - template<> void operator+<0>(X, X) {} // expected-note {{previous}} - template<> void operator+<0>(X, X) {} // expected-error {{redefinition}} + template<> void operator+<0>(X, X) {} // #dr679-def + template<> void operator+<0>(X, X) {} + // expected-error@-1 {{redefinition of 'operator+<0>'}} + // expected-note@#dr679-def {{previous definition is here}} } // dr680: na #if __cplusplus >= 201103L namespace dr681 { // dr681: partial - auto *a() -> int; // expected-error {{must specify return type 'auto', not 'auto *'}} + auto *a() -> int; + // since-cxx11-error@-1 {{function with trailing return type must specify return type 'auto', not 'auto *'}} auto (*b)() -> int; // FIXME: The errors here aren't great. - auto (*c()) -> int; // expected-error {{expected function body}} - auto ((*d)()) -> int; // expected-error {{expected ';'}} expected-error {{requires an initializer}} + auto (*c()) -> int; + // since-cxx11-error@-1 {{expected function body after function declarator}} + auto ((*d)()) -> int; + // since-cxx11-error@-1 {{declaration of variable 'd' with deduced type 'auto ((*)())' requires an initializer}} + // since-cxx11-error@-2 {{expected ';' after top level declarator}} // FIXME: This is definitely wrong. This should be // "function of () returning pointer to function of () returning int" // not a function with a deduced return type. - auto (*e())() -> int; // expected-error 0-1{{C++14}} + auto (*e())() -> int; + // cxx11-error@-1 {{'auto' return without trailing return type; deduced return types are a C++14 extension}} auto f() -> int (*)(); auto g() -> auto (*)() -> int; @@ -1027,25 +1152,24 @@ namespace dr683 { // dr683: yes #if __cplusplus >= 201103L namespace dr684 { // dr684: sup 1454 void f() { - int a; // expected-note {{here}} - constexpr int *p = &a; // expected-error {{constant expression}} expected-note {{pointer to 'a'}} + int a; // #dr684-a + constexpr int *p = &a; + // expected-error@-1 {{constexpr variable 'p' must be initialized by a constant expression}} + // expected-note@-2 {{pointer to 'a' is not a constant expression}} + // expected-note@#dr684-a {{here}} } } #endif namespace dr685 { // dr685: yes enum E : long { e }; -#if __cplusplus < 201103L - // expected-error@-2 {{enumeration types with a fixed underlying type are a C++11 extension}} -#endif + // cxx98-error@-1 {{enumeration types with a fixed underlying type are a C++11 extension}} void f(int); int f(long); int a = f(e); enum G : short { g }; -#if __cplusplus < 201103L - // expected-error@-2 {{enumeration types with a fixed underlying type are a C++11 extension}} -#endif + // cxx98-error@-1 {{enumeration types with a fixed underlying type are a C++11 extension}} int h(short); void h(long); int b = h(g); @@ -1054,9 +1178,12 @@ namespace dr685 { // dr685: yes void i(long); int c = i(g); - int j(unsigned int); // expected-note {{candidate}} - void j(long); // expected-note {{candidate}} - int d = j(g); // expected-error {{ambiguous}} + int j(unsigned int); // #dr685-j-uint + void j(long); // #dr685-j-long + int d = j(g); + // expected-error@-1 {{call to 'j' is ambiguous}} + // expected-note@#dr685-j-uint {{candidate function}} + // expected-note@#dr685-j-long {{candidate function}} // Valid per dr1601 int k(short); @@ -1064,61 +1191,83 @@ namespace dr685 { // dr685: yes int x = k(g); } -namespace dr686 { // dr686: yes +namespace dr686 { // dr686: 3.0 void f() { - (void)dynamic_cast(0); // expected-error {{incomplete}} expected-note {{forward}} - (void)dynamic_cast(0); // expected-error {{cannot be defined in a type specifier}} + (void)dynamic_cast(0); + // expected-error@-1 {{'A' is an incomplete type}} + // expected-note@-2 {{forward declaration of 'A'}} + (void)dynamic_cast(0); + // expected-error@-1 {{'A' cannot be defined in a type specifier}} (void)typeid(struct B*); - (void)typeid(struct B{}*); // expected-error {{cannot be defined in a type specifier}} + (void)typeid(struct B{}*); + // expected-error@-1 {{'B' cannot be defined in a type specifier}} (void)static_cast(0); - (void)static_cast(0); // expected-error {{cannot be defined in a type specifier}} + (void)static_cast(0); + // expected-error@-1 {{'C' cannot be defined in a type specifier}} (void)reinterpret_cast(0); - (void)reinterpret_cast(0); // expected-error {{cannot be defined in a type specifier}} - (void)const_cast(0); // expected-error {{not allowed}} - (void)const_cast(0); // expected-error {{cannot be defined in a type specifier}} + (void)reinterpret_cast(0); + // expected-error@-1 {{'D' cannot be defined in a type specifier}} + (void)const_cast(0); + // expected-error@-1 {{const_cast from 'int' to 'struct E *' is not allowed}} + (void)const_cast(0); + // expected-error@-1 {{'E' cannot be defined in a type specifier}} (void)sizeof(struct F*); - (void)sizeof(struct F{}*); // expected-error {{cannot be defined in a type specifier}} - (void)new struct G*; // expected-note {{forward}} - (void)new struct G{}*; // expected-error {{incomplete}} + (void)sizeof(struct F{}*); + // expected-error@-1 {{'F' cannot be defined in a type specifier}} + (void)new struct G*; // #dr686-G + (void)new struct G{}*; // #dr686-G-def + // expected-error@-1 {{allocation of incomplete type 'struct G'}} + // expected-note@#dr686-G {{forward declaration of 'G'}} + // since-cxx11-error@#dr686-G-def {{expected expression}} #if __cplusplus >= 201103L - // expected-error@-2 {{expected expression}} (void)alignof(struct H*); - (void)alignof(struct H{}*); // expected-error {{cannot be defined in a type specifier}} + (void)alignof(struct H{}*); + // since-cxx11-error@-1 {{'H' cannot be defined in a type specifier}} #endif (void)(struct I*)0; - (void)(struct I{}*)0; // expected-error {{cannot be defined in a type specifier}} + (void)(struct I{}*)0; + // expected-error@-1 {{'I' cannot be defined in a type specifier}} if (struct J *p = 0) {} - if (struct J {} *p = 0) {} // expected-error {{cannot be defined in a condition}} + if (struct J {} *p = 0) {} + // expected-error@-1 {{'J' cannot be defined in a condition}} for (struct K *p = 0; struct L *q = 0; ) {} - for (struct K {} *p = 0; struct L {} *q = 0; ) {} // expected-error {{'L' cannot be defined in a condition}} + for (struct K {} *p = 0; struct L {} *q = 0; ) {} + // expected-error@-1 {{'L' cannot be defined in a condition}} #if __cplusplus >= 201103L using M = struct {}; #endif struct N { - operator struct O{}(){}; // expected-error {{cannot be defined in a type specifier}} + operator struct O{}(){}; + // expected-error@-1 {{'N::O' cannot be defined in a type specifier}} }; try {} - catch (struct P *) {} // expected-error {{incomplete}} expected-note {{forward}} - catch (struct P {} *) {} // expected-error {{cannot be defined in a type specifier}} + catch (struct P *) {} + // expected-error@-1 {{cannot catch pointer to incomplete type 'struct P'}} + // expected-note@-2 {{forward declaration of 'P'}} + catch (struct P {} *) {} + // expected-error@-1 {{'P' cannot be defined in a type specifier}} #if __cplusplus < 201703L - void g() throw(struct Q); // expected-error {{incomplete}} expected-note {{forward}} - void h() throw(struct Q {}); // expected-error {{cannot be defined in a type specifier}} + void g() throw(struct Q); + // cxx98-17-error@-1 {{incomplete type 'struct Q' is not allowed in exception specification}} + // cxx98-17-note@-2 {{forward declaration of 'Q'}} + void h() throw(struct Q {}); + // cxx98-17-error@-1 {{'Q' cannot be defined in a type specifier}} #endif } template struct X; - template struct Y; // expected-error {{cannot be defined in a type specifier}} + template struct Y; + // expected-error@-1 {{'dr686::R' cannot be defined in a type specifier}} } namespace dr687 { // dr687 (9 c++20, but the issue is still considered open) template void f(T a) { // This is valid in C++20. g(a); -#if __cplusplus <= 201703L - // expected-error@-2 {{C++20 extension}} -#endif + // cxx98-17-error@-1 {{use of function template name with no prior declaration in function call with explicit template arguments is a C++20 extension}} // This is not. - template g(a); // expected-error {{expected expression}} + template g(a); + // expected-error@-1 {{expected expression}} } } @@ -1126,16 +1275,24 @@ namespace dr692 { // dr692: 16 // Also see dr1395. namespace temp_func_order_example2 { - template struct A1 {}; // expected-error 0-1{{C++11}} - template struct A2 {}; // expected-error 0-1{{C++11}} - template void e1(A1) = delete; // expected-error 0-2{{C++11}} + template struct A1 {}; + // cxx98-error@-1 {{variadic templates are a C++11 extension}} + template struct A2 {}; + // cxx98-error@-1 {{variadic templates are a C++11 extension}} + template void e1(A1) = delete; + // cxx98-error@-1 {{variadic templates are a C++11 extension}} + // cxx98-error@-2 {{deleted function definitions are a C++11 extension}} template void e1(A1); - template void e2(A2) = delete; // expected-error 0-2{{C++11}} + template void e2(A2) = delete; + // cxx98-error@-1 {{variadic templates are a C++11 extension}} + // cxx98-error@-2 {{deleted function definitions are a C++11 extension}} template void e2(A2); - template void f(U, A1 *p = 0) = delete; // expected-note {{candidate}} expected-error 0-1{{C++11}} - template int &f(U, A1 *p = 0); // expected-note {{candidate}} - template void g(T, T = T()); // expected-note {{candidate}} - template void g(T, U...); // expected-note {{candidate}} expected-error 0-1{{C++11}} + template void f(U, A1 *p = 0) = delete; // #dr692-f-deleted + // cxx98-error@-1 {{deleted function definitions are a C++11 extension}} + template int &f(U, A1 *p = 0); // #dr692-f + template void g(T, T = T()); // #dr692-g + template void g(T, U...); // #dr692-g-variadic + // cxx98-error@-1 {{variadic templates are a C++11 extension}} void h() { A1 a; int &r = f(42, &a); @@ -1143,15 +1300,23 @@ namespace dr692 { // dr692: 16 e1(b1); A2 b2; e2(b2); - f(42); // expected-error {{ambiguous}} - g(42); // expected-error {{ambiguous}} + f(42); + // expected-error@-1 {{call to 'f' is ambiguous}} + // expected-note@#dr692-f-deleted {{candidate function [with T = int, U = int] has been explicitly deleted}} + // expected-note@#dr692-f {{candidate function [with U = int]}} + g(42); + // expected-error@-1 {{ambiguous}} + // expected-note@#dr692-g {{candidate function [with T = int]}} + // expected-note@#dr692-g-variadic {{candidate function [with T = int, U = <>]}} } } namespace temp_func_order_example3 { - template void f(T, U...); // expected-error 0-1{{C++11}} + template void f(T, U...); + // cxx98-error@-1 {{variadic templates are a C++11 extension}} template void f(T); - template int &g(T *, U...); // expected-error 0-1{{C++11}} + template int &g(T *, U...); + // cxx98-error@-1 {{variadic templates are a C++11 extension}} template void g(T); void h(int i) { // This is made ambiguous by dr692, but made valid again by dr1395. @@ -1161,8 +1326,10 @@ namespace dr692 { // dr692: 16 } namespace temp_deduct_partial_example { - template char &f(Args... args); // expected-error 0-1{{C++11}} - template short &f(T1 a1, Args... args); // expected-error 0-1{{C++11}} + template char &f(Args... args); + // cxx98-error@-1 {{variadic templates are a C++11 extension}} + template short &f(T1 a1, Args... args); + // cxx98-error@-1 {{variadic templates are a C++11 extension}} template int &f(T1 a1, T2 a2); void g() { char &a = f(); @@ -1172,37 +1339,51 @@ namespace dr692 { // dr692: 16 } namespace temp_deduct_type_example1 { - template class S; // expected-error 0-1{{C++11}} - template class S; // expected-error 0-1{{C++11}} + template class S; + // cxx98-error@-1 {{variadic templates are a C++11 extension}} + template class S; + // cxx98-error@-1 {{variadic templates are a C++11 extension}} template class S {}; S s; - template struct A; // expected-error 0-1{{C++11}} - template struct A {}; // expected-error 0-1{{C++11}} + template struct A; + // cxx98-error@-1 {{variadic templates are a C++11 extension}} + template struct A {}; + // cxx98-error@-1 {{variadic templates are a C++11 extension}} template struct A; template struct A; } namespace temp_deduct_type_example3 { - template void f(T*, U...){} // expected-error 0-1{{C++11}} + template void f(T*, U...){} + // cxx98-error@-1 {{variadic templates are a C++11 extension}} template void f(T){} template void f(int*); } } -namespace dr696 { // dr696: yes +namespace dr696 { // dr696: 3.1 void f(const int*); void g() { - const int N = 10; // expected-note 1+{{here}} + const int N = 10; // #dr696-N struct A { void h() { int arr[N]; (void)arr; - f(&N); // expected-error {{declared in enclosing}} + f(&N); + // expected-error@-1 {{reference to local variable 'N' declared in enclosing function 'dr696::g'}} + // expected-note@#dr696-N {{'N' declared here}} } }; #if __cplusplus >= 201103L (void) [] { int arr[N]; (void)arr; }; - (void)[] { f(&N); }; // expected-error {{cannot be implicitly captured}} expected-note {{here}} expected-note 2 {{capture 'N' by}} expected-note 2 {{default capture by}} + (void)[] { f(&N); }; + // since-cxx11-error@-1 {{variable 'N' cannot be implicitly captured in a lambda with no capture-default specified}} + // since-cxx11-note@#dr696-N {{'N' declared here}} + // since-cxx11-note@-3 {{lambda expression begins here}} + // since-cxx11-note@-4 {{capture 'N' by value}} + // since-cxx11-note@-5 {{capture 'N' by reference}} + // since-cxx11-note@-6 {{default capture by value}} + // since-cxx11-note@-7 {{default capture by reference}} #endif } } diff --git a/clang/test/ClangScanDeps/strip-codegen-args.m b/clang/test/ClangScanDeps/strip-codegen-args.m new file mode 100644 index 000000000000..bb7e76e86aa2 --- /dev/null +++ b/clang/test/ClangScanDeps/strip-codegen-args.m @@ -0,0 +1,58 @@ +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: sed -e "s|DIR|%/t|g" %t/cdb1.json.template > %t/cdb1.json + +// RUN: clang-scan-deps -compilation-database %t/cdb1.json -format experimental-full > %t/result1.txt +// RUN: FileCheck %s -input-file %t/result1.txt + +// This tests that codegen option that do not affect the AST or generation of a module are removed. + +// CHECK: "modules": [ +// CHECK-NEXT: { +// CHECK: "command-line": [ +// CHECK-NOT: "-flto" +// CHECK-NOT: "-fno-autolink" +// CHECK-NOT: "-mrelax-relocations=no" +// CHECK: ] +// CHECK: "name": "A" +// CHECK: } +// CHECK-NOT: "name": "A" +// CHECK: "translation-units" + +//--- cdb1.json.template +[ + { + "directory": "DIR", + "command": "clang -Imodules/A -fmodules -fmodules-cache-path=DIR/module-cache -fimplicit-modules -flto -fno-autolink -Xclang -mrelax-relocations=no -fsyntax-only DIR/t1.m", + "file": "DIR/t1.m" + }, + { + "directory": "DIR", + "command": "clang -Imodules/A -fmodules -fmodules-cache-path=DIR/module-cache -fimplicit-modules -flto=thin -fautolink -fsyntax-only DIR/t2.m", + "file": "DIR/t2.m" + }, + { + "directory": "DIR", + "command": "clang -Imodules/A -fmodules -fmodules-cache-path=DIR/module-cache -fimplicit-modules -flto=full -fsyntax-only DIR/t3.m", + "file": "DIR/t2.m" + } +] + +//--- modules/A/module.modulemap + +module A { + umbrella header "A.h" +} + +//--- modules/A/A.h + +typedef int A_t; + +//--- t1.m +@import A; + +//--- t2.m +@import A; + +//--- t3.m +@import A; diff --git a/clang/test/CodeGen/SystemZ/atomic_is_lock_free.c b/clang/test/CodeGen/SystemZ/atomic_is_lock_free.c new file mode 100644 index 000000000000..32c436eaf36d --- /dev/null +++ b/clang/test/CodeGen/SystemZ/atomic_is_lock_free.c @@ -0,0 +1,98 @@ +// RUN: %clang_cc1 -triple s390x-linux-gnu -O1 -emit-llvm %s -o - | FileCheck %s +// +// Test __atomic_is_lock_free() and friends. + +#include +#include + +typedef __attribute__((aligned(16))) __int128 __int128_Al16; + +_Atomic __int128 Int128_Atomic; +__int128_Al16 Int128_Al16; +__int128 Int128; +struct { int I[3]; } _Atomic AtomicStruct; +_Atomic long double Atomic_fp128; // Also check the alignment of this. + +// Check alignments of the variables. @AtomicStruct gets padded and its size +// and alignment becomes 16. Only a power-of-2 size is considered, so 16 (not +// 12) needs to be specified with the intrinsics below. +// +// CHECK: %struct.anon = type { [3 x i32] } +// CHECK: @Int128 = {{.*}} i128 0, align 8 +// CHECK: @Int128_Atomic = {{.*}} i128 0, align 16 +// CHECK: @Int128_Al16 = {{.*}} i128 0, align 16 +// CHECK: @AtomicStruct = {{.*}} { %struct.anon, [4 x i8] } zeroinitializer, align 16 +// CHECK: @Atomic_fp128 = {{.*}} fp128 0xL00000000000000000000000000000000, align 16 + + +// CHECK-LABEL: @fun0 +// CHECK: ret i1 true +_Bool fun0() { + return __atomic_is_lock_free(16, &Int128_Atomic); +} + +// CHECK-LABEL: @fun1 +// CHECK: ret i1 true +_Bool fun1() { + return __atomic_always_lock_free(16, &Int128_Atomic); +} + +// CHECK-LABEL: @fun2 +// CHECK: ret i1 true +_Bool fun2() { + return __atomic_is_lock_free(16, &Int128_Al16); +} + +// CHECK-LABEL: @fun3 +// CHECK: ret i1 true +_Bool fun3() { + return __atomic_always_lock_free(16, &Int128_Al16); +} + +// CHECK-LABEL: @fun4 +// CHECK: call zeroext i1 @__atomic_is_lock_free +_Bool fun4() { + return __atomic_is_lock_free(16, &Int128); +} + +// CHECK-LABEL: @fun5 +// CHECK: ret i1 false +_Bool fun5() { + return __atomic_always_lock_free(16, &Int128); +} + +// CHECK-LABEL: @fun6 +// CHECK: ret i1 true +_Bool fun6() { + return __atomic_is_lock_free(16, 0); +} + +// CHECK-LABEL: @fun7 +// CHECK: ret i1 true +_Bool fun7() { + return __atomic_always_lock_free(16, 0); +} + +// CHECK-LABEL: @fun8 +// CHECK: ret i1 true +_Bool fun8() { + return __atomic_is_lock_free(16, &AtomicStruct); +} + +// CHECK-LABEL: @fun9 +// CHECK: ret i1 true +_Bool fun9() { + return __atomic_always_lock_free(16, &AtomicStruct); +} + +// CHECK-LABEL: @fun10 +// CHECK: ret i1 true +_Bool fun10() { + return atomic_is_lock_free(&Int128_Atomic); +} + +// CHECK-LABEL: @fun11 +// CHECK: ret i1 true +_Bool fun11() { + return __c11_atomic_is_lock_free(16); +} diff --git a/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-16Al.c b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-16Al.c new file mode 100644 index 000000000000..e3db2063312d --- /dev/null +++ b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-16Al.c @@ -0,0 +1,257 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple s390x-linux-gnu -O1 -emit-llvm %s -o - | FileCheck %s +// +// Test GNU atomic builtins for __int128 aligned to 16 bytes, which should be +// expanded to LLVM I/R by the front end. + +#include +#include + +__int128 Ptr __attribute__((aligned(16))); +__int128 Ret __attribute__((aligned(16))); +__int128 Val __attribute__((aligned(16))); +__int128 Exp __attribute__((aligned(16))); +__int128 Des __attribute__((aligned(16))); + +// CHECK-LABEL: @f1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i128, ptr @Ptr seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP0]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2:![0-9]+]] +// CHECK-NEXT: ret void +// +__int128 f1() { + return __atomic_load_n(&Ptr, memory_order_seq_cst); +} + +// CHECK-LABEL: @f2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i128, ptr @Ptr seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP0]], ptr @Ret, align 16 +// CHECK-NEXT: store i128 [[TMP0]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f2() { + __atomic_load(&Ptr, &Ret, memory_order_seq_cst); + return Ret; +} + +// CHECK-LABEL: @f3( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: store atomic i128 [[TMP0]], ptr @Ptr seq_cst, align 16 +// CHECK-NEXT: ret void +// +void f3() { + __atomic_store_n(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16 +// CHECK-NEXT: store atomic i128 [[TMP0]], ptr @Ptr seq_cst, align 16 +// CHECK-NEXT: ret void +// +void f4() { + __atomic_store(&Ptr, &Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f5( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f5() { + return __atomic_exchange_n(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f6( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16 +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP1]], ptr @Ret, align 16 +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f6() { + __atomic_exchange(&Ptr, &Val, &Ret, memory_order_seq_cst); + return Ret; +} + +// CHECK-LABEL: @f7( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Des, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr @Exp, align 16 +// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr @Ptr, i128 [[TMP1]], i128 [[TMP0]] seq_cst seq_cst, align 16 +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i128, i1 } [[TMP2]], 1 +// CHECK-NEXT: br i1 [[TMP3]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i128, i1 } [[TMP2]], 0 +// CHECK-NEXT: store i128 [[TMP4]], ptr @Exp, align 16 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP3]] +// +_Bool f7() { + return __atomic_compare_exchange_n(&Ptr, &Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Exp, align 16 +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr @Des, align 16 +// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr @Ptr, i128 [[TMP0]], i128 [[TMP1]] seq_cst seq_cst, align 16 +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i128, i1 } [[TMP2]], 1 +// CHECK-NEXT: br i1 [[TMP3]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i128, i1 } [[TMP2]], 0 +// CHECK-NEXT: store i128 [[TMP4]], ptr @Exp, align 16 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP3]] +// +_Bool f8() { + return __atomic_compare_exchange(&Ptr, &Exp, &Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f9( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw add ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: [[TMP2:%.*]] = add i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f9() { + return __atomic_add_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f10( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw sub ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: [[TMP2:%.*]] = sub i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f10() { + return __atomic_sub_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f11( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw and ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: [[TMP2:%.*]] = and i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f11() { + return __atomic_and_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f12( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xor ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: [[TMP2:%.*]] = xor i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f12() { + return __atomic_xor_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f13( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw or ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: [[TMP2:%.*]] = or i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f13() { + return __atomic_or_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f14( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw nand ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: [[TMP2:%.*]] = and i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: [[TMP3:%.*]] = xor i128 [[TMP2]], -1 +// CHECK-NEXT: store i128 [[TMP3]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f14() { + return __atomic_nand_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f15( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw add ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f15() { + return __atomic_fetch_add(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw sub ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f16() { + return __atomic_fetch_sub(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f17( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw and ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f17() { + return __atomic_fetch_and(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f18( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xor ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f18() { + return __atomic_fetch_xor(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f19( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw or ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f19() { + return __atomic_fetch_or(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f20( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 16, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw nand ptr @Ptr, i128 [[TMP0]] seq_cst, align 16 +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f20() { + return __atomic_fetch_nand(&Ptr, Val, memory_order_seq_cst); +} diff --git a/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-8Al.c b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-8Al.c new file mode 100644 index 000000000000..e38e6572bd58 --- /dev/null +++ b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i128-8Al.c @@ -0,0 +1,301 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple s390x-linux-gnu -O1 -emit-llvm %s -o - | FileCheck %s +// +// Test GNU atomic builtins for __int128 (with default alignment of 8 bytes +// only), resulting in libcalls. + +#include +#include + +__int128 Ptr; +__int128 Ret; +__int128 Val; +__int128 Exp; +__int128 Des; + +// TODO: This test and several more below have the unnecessary use of an alloca +// remaining. This is due to 369c9b7, which changes the behavior of the MemCpyOpt +// pass. It seems that a 'writable' attribute should now be added to the argument +// in order for this optimization to proceed. + +// CHECK-LABEL: @f1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: call void @__atomic_load(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull [[ATOMIC_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 8, !tbaa [[TBAA2:![0-9]+]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f1() { + return __atomic_load_n(&Ptr, memory_order_seq_cst); +} + +// CHECK-LABEL: @f2( +// CHECK-NEXT: entry: +// CHECK-NEXT: tail call void @__atomic_load(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull @Ret, i32 noundef signext 5) +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Ret, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f2() { + __atomic_load(&Ptr, &Ret, memory_order_seq_cst); + return Ret; +} + +// CHECK-LABEL: @f3( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[DOTATOMICTMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_store(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull [[DOTATOMICTMP]], i32 noundef signext 5) +// CHECK-NEXT: ret void +// +void f3() { + __atomic_store_n(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f4( +// CHECK-NEXT: entry: +// CHECK-NEXT: tail call void @__atomic_store(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull @Val, i32 noundef signext 5) +// CHECK-NEXT: ret void +// +void f4() { + __atomic_store(&Ptr, &Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f5( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[DOTATOMICTMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_exchange(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull [[DOTATOMICTMP]], ptr noundef nonnull [[ATOMIC_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[ATOMIC_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f5() { + return __atomic_exchange_n(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f6( +// CHECK-NEXT: entry: +// CHECK-NEXT: tail call void @__atomic_exchange(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull @Val, ptr noundef nonnull @Ret, i32 noundef signext 5) +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Ret, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f6() { + __atomic_exchange(&Ptr, &Val, &Ret, memory_order_seq_cst); + return Ret; +} + +// CHECK-LABEL: @f7( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Des, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[DOTATOMICTMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull @Exp, ptr noundef nonnull [[DOTATOMICTMP]], i32 noundef signext 5, i32 noundef signext 5) +// CHECK-NEXT: ret i1 [[CALL]] +// +_Bool f7() { + return __atomic_compare_exchange_n(&Ptr, &Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[CALL:%.*]] = tail call zeroext i1 @__atomic_compare_exchange(i64 noundef 16, ptr noundef nonnull @Ptr, ptr noundef nonnull @Exp, ptr noundef nonnull @Des, i32 noundef signext 5, i32 noundef signext 5) +// CHECK-NEXT: ret i1 [[CALL]] +// +_Bool f8() { + return __atomic_compare_exchange(&Ptr, &Exp, &Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f9( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_add_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP2:%.*]] = add i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f9() { + return __atomic_add_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f10( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_sub_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP2:%.*]] = sub i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f10() { + return __atomic_sub_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f11( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_and_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP2:%.*]] = and i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f11() { + return __atomic_and_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f12( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_xor_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP2:%.*]] = xor i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f12() { + return __atomic_xor_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f13( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_or_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP2:%.*]] = or i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: store i128 [[TMP2]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f13() { + return __atomic_or_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f14( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_nand_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP2:%.*]] = and i128 [[TMP1]], [[TMP0]] +// CHECK-NEXT: [[TMP3:%.*]] = xor i128 [[TMP2]], -1 +// CHECK-NEXT: store i128 [[TMP3]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f14() { + return __atomic_nand_fetch(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f15( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_add_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f15() { + return __atomic_fetch_add(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_sub_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f16() { + return __atomic_fetch_sub(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f17( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_and_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f17() { + return __atomic_fetch_and(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f18( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_xor_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f18() { + return __atomic_fetch_xor(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f19( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_or_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f19() { + return __atomic_fetch_or(&Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f20( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca i128, align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr @Val, align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP0]], ptr [[INDIRECT_ARG_TEMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: call void @__atomic_fetch_nand_16(ptr nonnull sret(i128) align 8 [[TMP]], ptr noundef nonnull @Ptr, ptr noundef nonnull [[INDIRECT_ARG_TEMP]], i32 noundef signext 5) +// CHECK-NEXT: [[TMP1:%.*]] = load i128, ptr [[TMP]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: store i128 [[TMP1]], ptr [[AGG_RESULT:%.*]], align 8, !tbaa [[TBAA2]] +// CHECK-NEXT: ret void +// +__int128 f20() { + return __atomic_fetch_nand(&Ptr, Val, memory_order_seq_cst); +} diff --git a/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i16.c b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i16.c new file mode 100644 index 000000000000..7c6a82f14197 --- /dev/null +++ b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i16.c @@ -0,0 +1,219 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple s390x-linux-gnu -O1 -emit-llvm %s -o - | FileCheck %s +// +// Test GNU atomic builtins for int16_t. + +#include +#include + +// CHECK-LABEL: @f1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[PTR:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret i16 [[TMP0]] +// +int16_t f1(int16_t *Ptr) { + return __atomic_load_n(Ptr, memory_order_seq_cst); +} + +// CHECK-LABEL: @f2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[PTR:%.*]] seq_cst, align 2 +// CHECK-NEXT: store i16 [[TMP0]], ptr [[RET:%.*]], align 2 +// CHECK-NEXT: ret i16 [[TMP0]] +// +int16_t f2(int16_t *Ptr, int16_t *Ret) { + __atomic_load(Ptr, Ret, memory_order_seq_cst); + return *Ret; +} + +// CHECK-LABEL: @f3( +// CHECK-NEXT: entry: +// CHECK-NEXT: store atomic i16 [[VAL:%.*]], ptr [[PTR:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret void +// +void f3(int16_t *Ptr, int16_t Val) { + __atomic_store_n(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[VAL:%.*]], align 2 +// CHECK-NEXT: store atomic i16 [[TMP0]], ptr [[PTR:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret void +// +void f4(int16_t *Ptr, int16_t *Val) { + __atomic_store(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f5( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret i16 [[TMP0]] +// +int16_t f5(int16_t *Ptr, int16_t Val) { + return __atomic_exchange_n(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f6( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[VAL:%.*]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i16 [[TMP0]] seq_cst, align 2 +// CHECK-NEXT: store i16 [[TMP1]], ptr [[RET:%.*]], align 2 +// CHECK-NEXT: ret i16 [[TMP1]] +// +int16_t f6(int16_t *Ptr, int16_t *Val, int16_t *Ret) { + __atomic_exchange(Ptr, Val, Ret, memory_order_seq_cst); + return *Ret; +} + +// CHECK-LABEL: @f7( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[EXP:%.*]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[PTR:%.*]], i16 [[TMP0]], i16 [[DES:%.*]] seq_cst seq_cst, align 2 +// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1 +// CHECK-NEXT: br i1 [[TMP2]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i16, i1 } [[TMP1]], 0 +// CHECK-NEXT: store i16 [[TMP3]], ptr [[EXP]], align 2 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP2]] +// +_Bool f7(int16_t *Ptr, int16_t *Exp, int16_t Des) { + return __atomic_compare_exchange_n(Ptr, Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[EXP:%.*]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[DES:%.*]], align 2 +// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[PTR:%.*]], i16 [[TMP0]], i16 [[TMP1]] seq_cst seq_cst, align 2 +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i16, i1 } [[TMP2]], 1 +// CHECK-NEXT: br i1 [[TMP3]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i16, i1 } [[TMP2]], 0 +// CHECK-NEXT: store i16 [[TMP4]], ptr [[EXP]], align 2 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP3]] +// +_Bool f8(int16_t *Ptr, int16_t *Exp, int16_t *Des) { + return __atomic_compare_exchange(Ptr, Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f9( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: [[TMP1:%.*]] = add i16 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i16 [[TMP1]] +// +int16_t f9(int16_t *Ptr, int16_t Val) { + return __atomic_add_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f10( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i16 [[TMP1]] +// +int16_t f10(int16_t *Ptr, int16_t Val) { + return __atomic_sub_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f11( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: [[TMP1:%.*]] = and i16 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i16 [[TMP1]] +// +int16_t f11(int16_t *Ptr, int16_t Val) { + return __atomic_and_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f12( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: [[TMP1:%.*]] = xor i16 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i16 [[TMP1]] +// +int16_t f12(int16_t *Ptr, int16_t Val) { + return __atomic_xor_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f13( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: [[TMP1:%.*]] = or i16 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i16 [[TMP1]] +// +int16_t f13(int16_t *Ptr, int16_t Val) { + return __atomic_or_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f14( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: [[TMP1:%.*]] = and i16 [[TMP0]], [[VAL]] +// CHECK-NEXT: [[TMP2:%.*]] = xor i16 [[TMP1]], -1 +// CHECK-NEXT: ret i16 [[TMP2]] +// +int16_t f14(int16_t *Ptr, int16_t Val) { + return __atomic_nand_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f15( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret i16 [[TMP0]] +// +int16_t f15(int16_t *Ptr, int16_t Val) { + return __atomic_fetch_add(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret i16 [[TMP0]] +// +int16_t f16(int16_t *Ptr, int16_t Val) { + return __atomic_fetch_sub(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f17( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret i16 [[TMP0]] +// +int16_t f17(int16_t *Ptr, int16_t Val) { + return __atomic_fetch_and(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f18( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret i16 [[TMP0]] +// +int16_t f18(int16_t *Ptr, int16_t Val) { + return __atomic_fetch_xor(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f19( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret i16 [[TMP0]] +// +int16_t f19(int16_t *Ptr, int16_t Val) { + return __atomic_fetch_or(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f20( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i16 [[VAL:%.*]] seq_cst, align 2 +// CHECK-NEXT: ret i16 [[TMP0]] +// +int16_t f20(int16_t *Ptr, int16_t Val) { + return __atomic_fetch_nand(Ptr, Val, memory_order_seq_cst); +} diff --git a/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i32.c b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i32.c new file mode 100644 index 000000000000..ba630e7c952e --- /dev/null +++ b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i32.c @@ -0,0 +1,219 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple s390x-linux-gnu -O1 -emit-llvm %s -o - | FileCheck %s +// +// Test GNU atomic builtins for int32_t. + +#include +#include + +// CHECK-LABEL: @f1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[PTR:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret i32 [[TMP0]] +// +int32_t f1(int32_t *Ptr) { + return __atomic_load_n(Ptr, memory_order_seq_cst); +} + +// CHECK-LABEL: @f2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[PTR:%.*]] seq_cst, align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[RET:%.*]], align 4 +// CHECK-NEXT: ret i32 [[TMP0]] +// +int32_t f2(int32_t *Ptr, int32_t *Ret) { + __atomic_load(Ptr, Ret, memory_order_seq_cst); + return *Ret; +} + +// CHECK-LABEL: @f3( +// CHECK-NEXT: entry: +// CHECK-NEXT: store atomic i32 [[VAL:%.*]], ptr [[PTR:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret void +// +void f3(int32_t *Ptr, int32_t Val) { + __atomic_store_n(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL:%.*]], align 4 +// CHECK-NEXT: store atomic i32 [[TMP0]], ptr [[PTR:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret void +// +void f4(int32_t *Ptr, int32_t *Val) { + __atomic_store(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f5( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret i32 [[TMP0]] +// +int32_t f5(int32_t *Ptr, int32_t Val) { + return __atomic_exchange_n(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f6( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL:%.*]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i32 [[TMP0]] seq_cst, align 4 +// CHECK-NEXT: store i32 [[TMP1]], ptr [[RET:%.*]], align 4 +// CHECK-NEXT: ret i32 [[TMP1]] +// +int32_t f6(int32_t *Ptr, int32_t *Val, int32_t *Ret) { + __atomic_exchange(Ptr, Val, Ret, memory_order_seq_cst); + return *Ret; +} + +// CHECK-LABEL: @f7( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[EXP:%.*]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[PTR:%.*]], i32 [[TMP0]], i32 [[DES:%.*]] seq_cst seq_cst, align 4 +// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1 +// CHECK-NEXT: br i1 [[TMP2]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP1]], 0 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[EXP]], align 4 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP2]] +// +_Bool f7(int32_t *Ptr, int32_t *Exp, int32_t Des) { + return __atomic_compare_exchange_n(Ptr, Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[EXP:%.*]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[DES:%.*]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[PTR:%.*]], i32 [[TMP0]], i32 [[TMP1]] seq_cst seq_cst, align 4 +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1 +// CHECK-NEXT: br i1 [[TMP3]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[EXP]], align 4 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP3]] +// +_Bool f8(int32_t *Ptr, int32_t *Exp, int32_t *Des) { + return __atomic_compare_exchange(Ptr, Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f9( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i32 [[TMP1]] +// +int32_t f9(int32_t *Ptr, int32_t Val) { + return __atomic_add_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f10( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i32 [[TMP1]] +// +int32_t f10(int32_t *Ptr, int32_t Val) { + return __atomic_sub_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f11( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i32 [[TMP1]] +// +int32_t f11(int32_t *Ptr, int32_t Val) { + return __atomic_and_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f12( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i32 [[TMP1]] +// +int32_t f12(int32_t *Ptr, int32_t Val) { + return __atomic_xor_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f13( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i32 [[TMP1]] +// +int32_t f13(int32_t *Ptr, int32_t Val) { + return __atomic_or_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f14( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], [[VAL]] +// CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1 +// CHECK-NEXT: ret i32 [[TMP2]] +// +int32_t f14(int32_t *Ptr, int32_t Val) { + return __atomic_nand_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f15( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret i32 [[TMP0]] +// +int32_t f15(int32_t *Ptr, int32_t Val) { + return __atomic_fetch_add(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret i32 [[TMP0]] +// +int32_t f16(int32_t *Ptr, int32_t Val) { + return __atomic_fetch_sub(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f17( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret i32 [[TMP0]] +// +int32_t f17(int32_t *Ptr, int32_t Val) { + return __atomic_fetch_and(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f18( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret i32 [[TMP0]] +// +int32_t f18(int32_t *Ptr, int32_t Val) { + return __atomic_fetch_xor(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f19( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret i32 [[TMP0]] +// +int32_t f19(int32_t *Ptr, int32_t Val) { + return __atomic_fetch_or(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f20( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i32 [[VAL:%.*]] seq_cst, align 4 +// CHECK-NEXT: ret i32 [[TMP0]] +// +int32_t f20(int32_t *Ptr, int32_t Val) { + return __atomic_fetch_nand(Ptr, Val, memory_order_seq_cst); +} diff --git a/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i64.c b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i64.c new file mode 100644 index 000000000000..25c69ee8c54b --- /dev/null +++ b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i64.c @@ -0,0 +1,219 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple s390x-linux-gnu -O1 -emit-llvm %s -o - | FileCheck %s +// +// Test GNU atomic builtins for int64_t. + +#include +#include + +// CHECK-LABEL: @f1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[PTR:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret i64 [[TMP0]] +// +int64_t f1(int64_t *Ptr) { + return __atomic_load_n(Ptr, memory_order_seq_cst); +} + +// CHECK-LABEL: @f2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[PTR:%.*]] seq_cst, align 8 +// CHECK-NEXT: store i64 [[TMP0]], ptr [[RET:%.*]], align 8 +// CHECK-NEXT: ret i64 [[TMP0]] +// +int64_t f2(int64_t *Ptr, int64_t *Ret) { + __atomic_load(Ptr, Ret, memory_order_seq_cst); + return *Ret; +} + +// CHECK-LABEL: @f3( +// CHECK-NEXT: entry: +// CHECK-NEXT: store atomic i64 [[VAL:%.*]], ptr [[PTR:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret void +// +void f3(int64_t *Ptr, int64_t Val) { + __atomic_store_n(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VAL:%.*]], align 8 +// CHECK-NEXT: store atomic i64 [[TMP0]], ptr [[PTR:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret void +// +void f4(int64_t *Ptr, int64_t *Val) { + __atomic_store(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f5( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret i64 [[TMP0]] +// +int64_t f5(int64_t *Ptr, int64_t Val) { + return __atomic_exchange_n(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f6( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[VAL:%.*]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i64 [[TMP0]] seq_cst, align 8 +// CHECK-NEXT: store i64 [[TMP1]], ptr [[RET:%.*]], align 8 +// CHECK-NEXT: ret i64 [[TMP1]] +// +int64_t f6(int64_t *Ptr, int64_t *Val, int64_t *Ret) { + __atomic_exchange(Ptr, Val, Ret, memory_order_seq_cst); + return *Ret; +} + +// CHECK-LABEL: @f7( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[EXP:%.*]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[PTR:%.*]], i64 [[TMP0]], i64 [[DES:%.*]] seq_cst seq_cst, align 8 +// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1 +// CHECK-NEXT: br i1 [[TMP2]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP1]], 0 +// CHECK-NEXT: store i64 [[TMP3]], ptr [[EXP]], align 8 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP2]] +// +_Bool f7(int64_t *Ptr, int64_t *Exp, int64_t Des) { + return __atomic_compare_exchange_n(Ptr, Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[EXP:%.*]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[DES:%.*]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[PTR:%.*]], i64 [[TMP0]], i64 [[TMP1]] seq_cst seq_cst, align 8 +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1 +// CHECK-NEXT: br i1 [[TMP3]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0 +// CHECK-NEXT: store i64 [[TMP4]], ptr [[EXP]], align 8 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP3]] +// +_Bool f8(int64_t *Ptr, int64_t *Exp, int64_t *Des) { + return __atomic_compare_exchange(Ptr, Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f9( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i64 [[TMP1]] +// +int64_t f9(int64_t *Ptr, int64_t Val) { + return __atomic_add_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f10( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i64 [[TMP1]] +// +int64_t f10(int64_t *Ptr, int64_t Val) { + return __atomic_sub_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f11( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i64 [[TMP1]] +// +int64_t f11(int64_t *Ptr, int64_t Val) { + return __atomic_and_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f12( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i64 [[TMP1]] +// +int64_t f12(int64_t *Ptr, int64_t Val) { + return __atomic_xor_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f13( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = or i64 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i64 [[TMP1]] +// +int64_t f13(int64_t *Ptr, int64_t Val) { + return __atomic_or_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f14( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], [[VAL]] +// CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], -1 +// CHECK-NEXT: ret i64 [[TMP2]] +// +int64_t f14(int64_t *Ptr, int64_t Val) { + return __atomic_nand_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f15( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret i64 [[TMP0]] +// +int64_t f15(int64_t *Ptr, int64_t Val) { + return __atomic_fetch_add(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret i64 [[TMP0]] +// +int64_t f16(int64_t *Ptr, int64_t Val) { + return __atomic_fetch_sub(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f17( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret i64 [[TMP0]] +// +int64_t f17(int64_t *Ptr, int64_t Val) { + return __atomic_fetch_and(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f18( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret i64 [[TMP0]] +// +int64_t f18(int64_t *Ptr, int64_t Val) { + return __atomic_fetch_xor(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f19( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret i64 [[TMP0]] +// +int64_t f19(int64_t *Ptr, int64_t Val) { + return __atomic_fetch_or(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f20( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i64 [[VAL:%.*]] seq_cst, align 8 +// CHECK-NEXT: ret i64 [[TMP0]] +// +int64_t f20(int64_t *Ptr, int64_t Val) { + return __atomic_fetch_nand(Ptr, Val, memory_order_seq_cst); +} diff --git a/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i8.c b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i8.c new file mode 100644 index 000000000000..1f4b455bc026 --- /dev/null +++ b/clang/test/CodeGen/SystemZ/gnu-atomic-builtins-i8.c @@ -0,0 +1,219 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple s390x-linux-gnu -O1 -emit-llvm %s -o - | FileCheck %s +// +// Test GNU atomic builtins for int8_t. + +#include +#include + +// CHECK-LABEL: @f1( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[PTR:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret i8 [[TMP0]] +// +int8_t f1(int8_t *Ptr) { + return __atomic_load_n(Ptr, memory_order_seq_cst); +} + +// CHECK-LABEL: @f2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[PTR:%.*]] seq_cst, align 1 +// CHECK-NEXT: store i8 [[TMP0]], ptr [[RET:%.*]], align 1 +// CHECK-NEXT: ret i8 [[TMP0]] +// +int8_t f2(int8_t *Ptr, int8_t *Ret) { + __atomic_load(Ptr, Ret, memory_order_seq_cst); + return *Ret; +} + +// CHECK-LABEL: @f3( +// CHECK-NEXT: entry: +// CHECK-NEXT: store atomic i8 [[VAL:%.*]], ptr [[PTR:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret void +// +void f3(int8_t *Ptr, int8_t Val) { + __atomic_store_n(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[VAL:%.*]], align 1 +// CHECK-NEXT: store atomic i8 [[TMP0]], ptr [[PTR:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret void +// +void f4(int8_t *Ptr, int8_t *Val) { + __atomic_store(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f5( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret i8 [[TMP0]] +// +int8_t f5(int8_t *Ptr, int8_t Val) { + return __atomic_exchange_n(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f6( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[VAL:%.*]], align 1 +// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i8 [[TMP0]] seq_cst, align 1 +// CHECK-NEXT: store i8 [[TMP1]], ptr [[RET:%.*]], align 1 +// CHECK-NEXT: ret i8 [[TMP1]] +// +int8_t f6(int8_t *Ptr, int8_t *Val, int8_t *Ret) { + __atomic_exchange(Ptr, Val, Ret, memory_order_seq_cst); + return *Ret; +} + +// CHECK-LABEL: @f7( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[EXP:%.*]], align 1 +// CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[PTR:%.*]], i8 [[TMP0]], i8 [[DES:%.*]] seq_cst seq_cst, align 1 +// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1 +// CHECK-NEXT: br i1 [[TMP2]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i8, i1 } [[TMP1]], 0 +// CHECK-NEXT: store i8 [[TMP3]], ptr [[EXP]], align 1 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP2]] +// +_Bool f7(int8_t *Ptr, int8_t *Exp, int8_t Des) { + return __atomic_compare_exchange_n(Ptr, Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[EXP:%.*]], align 1 +// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[DES:%.*]], align 1 +// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[PTR:%.*]], i8 [[TMP0]], i8 [[TMP1]] seq_cst seq_cst, align 1 +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i8, i1 } [[TMP2]], 1 +// CHECK-NEXT: br i1 [[TMP3]], label [[CMPXCHG_CONTINUE:%.*]], label [[CMPXCHG_STORE_EXPECTED:%.*]] +// CHECK: cmpxchg.store_expected: +// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i8, i1 } [[TMP2]], 0 +// CHECK-NEXT: store i8 [[TMP4]], ptr [[EXP]], align 1 +// CHECK-NEXT: br label [[CMPXCHG_CONTINUE]] +// CHECK: cmpxchg.continue: +// CHECK-NEXT: ret i1 [[TMP3]] +// +_Bool f8(int8_t *Ptr, int8_t *Exp, int8_t *Des) { + return __atomic_compare_exchange(Ptr, Exp, Des, 0, + memory_order_seq_cst, memory_order_seq_cst); +} + +// CHECK-LABEL: @f9( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: [[TMP1:%.*]] = add i8 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i8 [[TMP1]] +// +int8_t f9(int8_t *Ptr, int8_t Val) { + return __atomic_add_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f10( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i8 [[TMP1]] +// +int8_t f10(int8_t *Ptr, int8_t Val) { + return __atomic_sub_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f11( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i8 [[TMP1]] +// +int8_t f11(int8_t *Ptr, int8_t Val) { + return __atomic_and_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f12( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i8 [[TMP1]] +// +int8_t f12(int8_t *Ptr, int8_t Val) { + return __atomic_xor_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f13( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: [[TMP1:%.*]] = or i8 [[TMP0]], [[VAL]] +// CHECK-NEXT: ret i8 [[TMP1]] +// +int8_t f13(int8_t *Ptr, int8_t Val) { + return __atomic_or_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f14( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[VAL]] +// CHECK-NEXT: [[TMP2:%.*]] = xor i8 [[TMP1]], -1 +// CHECK-NEXT: ret i8 [[TMP2]] +// +int8_t f14(int8_t *Ptr, int8_t Val) { + return __atomic_nand_fetch(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f15( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw add ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret i8 [[TMP0]] +// +int8_t f15(int8_t *Ptr, int8_t Val) { + return __atomic_fetch_add(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw sub ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret i8 [[TMP0]] +// +int8_t f16(int8_t *Ptr, int8_t Val) { + return __atomic_fetch_sub(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f17( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw and ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret i8 [[TMP0]] +// +int8_t f17(int8_t *Ptr, int8_t Val) { + return __atomic_fetch_and(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f18( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw xor ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret i8 [[TMP0]] +// +int8_t f18(int8_t *Ptr, int8_t Val) { + return __atomic_fetch_xor(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f19( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw or ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret i8 [[TMP0]] +// +int8_t f19(int8_t *Ptr, int8_t Val) { + return __atomic_fetch_or(Ptr, Val, memory_order_seq_cst); +} + +// CHECK-LABEL: @f20( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = atomicrmw nand ptr [[PTR:%.*]], i8 [[VAL:%.*]] seq_cst, align 1 +// CHECK-NEXT: ret i8 [[TMP0]] +// +int8_t f20(int8_t *Ptr, int8_t Val) { + return __atomic_fetch_nand(Ptr, Val, memory_order_seq_cst); +} diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c index 72d159b19118..5622568c4cd7 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c @@ -1,17 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s #include -#ifdef DISABLE_SME_ATTRIBUTES -#define ARM_STREAMING_ATTR -#else -#define ARM_STREAMING_ATTR __attribute__((arm_streaming)) -#endif - // CHECK-C-LABEL: define dso_local void @test_svld1_hor_za8( // CHECK-C-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], ptr noundef [[PTR:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-C-NEXT: entry: @@ -28,7 +22,7 @@ // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[PTR]], i32 0, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_za8(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_hor_za8(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_hor_za8(0, slice_base, pg, ptr); svld1_hor_za8(0, slice_base + 15, pg, ptr); } @@ -51,7 +45,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_za8(uint32_t slice_base, svbool_t pg, con // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1h.horiz( [[TMP0]], ptr [[PTR]], i32 1, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_za16(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_hor_za16(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_hor_za16(0, slice_base, pg, ptr); svld1_hor_za16(1, slice_base + 7, pg, ptr); } @@ -74,7 +68,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_za16(uint32_t slice_base, svbool_t pg, co // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1w.horiz( [[TMP0]], ptr [[PTR]], i32 3, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_za32(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_hor_za32(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_hor_za32(0, slice_base, pg, ptr); svld1_hor_za32(3, slice_base + 3, pg, ptr); } @@ -97,7 +91,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_za32(uint32_t slice_base, svbool_t pg, co // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1d.horiz( [[TMP0]], ptr [[PTR]], i32 7, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_za64(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_hor_za64(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_hor_za64(0, slice_base, pg, ptr); svld1_hor_za64(7, slice_base + 1, pg, ptr); } @@ -118,7 +112,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_za64(uint32_t slice_base, svbool_t pg, co // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1q.horiz( [[TMP0]], ptr [[PTR]], i32 15, i32 [[SLICE_BASE]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_za128(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_hor_za128(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_hor_za128(0, slice_base, pg, ptr); svld1_hor_za128(15, slice_base, pg, ptr); } @@ -139,7 +133,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_za128(uint32_t slice_base, svbool_t pg, c // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1b.vert( [[PG]], ptr [[PTR]], i32 0, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_za8(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_ver_za8(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_ver_za8(0, slice_base, pg, ptr); svld1_ver_za8(0, slice_base + 15, pg, ptr); } @@ -162,7 +156,7 @@ ARM_STREAMING_ATTR void test_svld1_ver_za8(uint32_t slice_base, svbool_t pg, con // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1h.vert( [[TMP0]], ptr [[PTR]], i32 1, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_za16(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_ver_za16(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_ver_za16(0, slice_base, pg, ptr); svld1_ver_za16(1, slice_base + 7, pg, ptr); } @@ -185,7 +179,7 @@ ARM_STREAMING_ATTR void test_svld1_ver_za16(uint32_t slice_base, svbool_t pg, co // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1w.vert( [[TMP0]], ptr [[PTR]], i32 3, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_za32(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_ver_za32(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_ver_za32(0, slice_base, pg, ptr); svld1_ver_za32(3, slice_base + 3, pg, ptr); } @@ -208,7 +202,7 @@ ARM_STREAMING_ATTR void test_svld1_ver_za32(uint32_t slice_base, svbool_t pg, co // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1d.vert( [[TMP0]], ptr [[PTR]], i32 7, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_za64(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_ver_za64(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_ver_za64(0, slice_base, pg, ptr); svld1_ver_za64(7, slice_base + 1, pg, ptr); } @@ -229,7 +223,7 @@ ARM_STREAMING_ATTR void test_svld1_ver_za64(uint32_t slice_base, svbool_t pg, co // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1q.vert( [[TMP0]], ptr [[PTR]], i32 15, i32 [[SLICE_BASE]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_za128(uint32_t slice_base, svbool_t pg, const void *ptr) { +void test_svld1_ver_za128(uint32_t slice_base, svbool_t pg, const void *ptr) __arm_streaming { svld1_ver_za128(0, slice_base, pg, ptr); svld1_ver_za128(15, slice_base, pg, ptr); } diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c index cf49f62664ee..0fe7dcfc0a79 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c @@ -1,17 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s #include -#ifdef DISABLE_SME_ATTRIBUTES -#define ARM_STREAMING_ATTR -#else -#define ARM_STREAMING_ATTR __attribute__((arm_streaming)) -#endif - // CHECK-C-LABEL: define dso_local void @test_svld1_hor_vnum_za8( // CHECK-C-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], ptr noundef [[PTR:%.*]], i64 noundef [[VNUM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-C-NEXT: entry: @@ -34,7 +28,7 @@ // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_vnum_za8(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_hor_vnum_za8(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_hor_vnum_za8(0, slice_base, pg, ptr, vnum); svld1_hor_vnum_za8(0, slice_base + 15, pg, ptr, vnum); } @@ -63,7 +57,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_vnum_za8(uint32_t slice_base, svbool_t pg // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1h.horiz( [[TMP0]], ptr [[TMP2]], i32 1, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_vnum_za16(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_hor_vnum_za16(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_hor_vnum_za16(0, slice_base, pg, ptr, vnum); svld1_hor_vnum_za16(1, slice_base + 7, pg, ptr, vnum); } @@ -92,7 +86,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_vnum_za16(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1w.horiz( [[TMP0]], ptr [[TMP2]], i32 3, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_vnum_za32(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_hor_vnum_za32(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_hor_vnum_za32(0, slice_base, pg, ptr, vnum); svld1_hor_vnum_za32(3, slice_base + 3, pg, ptr, vnum); } @@ -121,7 +115,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_vnum_za32(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1d.horiz( [[TMP0]], ptr [[TMP2]], i32 7, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_vnum_za64(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_hor_vnum_za64(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_hor_vnum_za64(0, slice_base, pg, ptr, vnum); svld1_hor_vnum_za64(7, slice_base + 1, pg, ptr, vnum); } @@ -148,7 +142,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_vnum_za64(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1q.horiz( [[TMP0]], ptr [[TMP2]], i32 15, i32 [[SLICE_BASE]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_hor_vnum_za128(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_hor_vnum_za128(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_hor_vnum_za128(0, slice_base, pg, ptr, vnum); svld1_hor_vnum_za128(15, slice_base, pg, ptr, vnum); } @@ -175,7 +169,7 @@ ARM_STREAMING_ATTR void test_svld1_hor_vnum_za128(uint32_t slice_base, svbool_t // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1b.vert( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_hor_za8(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_ver_hor_za8(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_ver_vnum_za8(0, slice_base, pg, ptr, vnum); svld1_ver_vnum_za8(0, slice_base + 15, pg, ptr, vnum); } @@ -204,7 +198,7 @@ ARM_STREAMING_ATTR void test_svld1_ver_hor_za8(uint32_t slice_base, svbool_t pg, // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1h.vert( [[TMP0]], ptr [[TMP2]], i32 1, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_vnum_za16(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_ver_vnum_za16(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_ver_vnum_za16(0, slice_base, pg, ptr, vnum); svld1_ver_vnum_za16(1, slice_base + 7, pg, ptr, vnum); } @@ -233,7 +227,7 @@ ARM_STREAMING_ATTR void test_svld1_ver_vnum_za16(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1w.vert( [[TMP0]], ptr [[TMP2]], i32 3, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_vnum_za32(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_ver_vnum_za32(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_ver_vnum_za32(0, slice_base, pg, ptr, vnum); svld1_ver_vnum_za32(3, slice_base + 3, pg, ptr, vnum); } @@ -262,7 +256,7 @@ ARM_STREAMING_ATTR void test_svld1_ver_vnum_za32(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1d.vert( [[TMP0]], ptr [[TMP2]], i32 7, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_vnum_za64(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_ver_vnum_za64(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_ver_vnum_za64(0, slice_base, pg, ptr, vnum); svld1_ver_vnum_za64(7, slice_base + 1, pg, ptr, vnum); } @@ -289,7 +283,7 @@ ARM_STREAMING_ATTR void test_svld1_ver_vnum_za64(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.ld1q.vert( [[TMP0]], ptr [[TMP2]], i32 15, i32 [[SLICE_BASE]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svld1_ver_vnum_za128(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) { +void test_svld1_ver_vnum_za128(uint32_t slice_base, svbool_t pg, const void *ptr, int64_t vnum) __arm_streaming { svld1_ver_vnum_za128(0, slice_base, pg, ptr, vnum); svld1_ver_vnum_za128(15, slice_base, pg, ptr, vnum); } diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c index 9ea5fa10c1bb..9ed158aedf7e 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c @@ -1,17 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s #include -#ifdef DISABLE_SME_ATTRIBUTES -#define ARM_STREAMING_ATTR -#else -#define ARM_STREAMING_ATTR __attribute__((arm_streaming)) -#endif - // CHECK-C-LABEL: define dso_local void @test_svst1_hor_za8( // CHECK-C-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], ptr noundef [[PTR:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-C-NEXT: entry: @@ -28,7 +22,7 @@ // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1b.horiz( [[PG]], ptr [[PTR]], i32 0, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_za8(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_hor_za8(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_hor_za8(0, slice_base, pg, ptr); svst1_hor_za8(0, slice_base + 15, pg, ptr); } @@ -51,7 +45,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_za8(uint32_t slice_base, svbool_t pg, voi // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1h.horiz( [[TMP0]], ptr [[PTR]], i32 1, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_za16(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_hor_za16(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_hor_za16(0, slice_base, pg, ptr); svst1_hor_za16(1, slice_base + 7, pg, ptr); } @@ -74,7 +68,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_za16(uint32_t slice_base, svbool_t pg, vo // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1w.horiz( [[TMP0]], ptr [[PTR]], i32 3, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_za32(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_hor_za32(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_hor_za32(0, slice_base, pg, ptr); svst1_hor_za32(3, slice_base + 3, pg, ptr); } @@ -97,7 +91,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_za32(uint32_t slice_base, svbool_t pg, vo // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1d.horiz( [[TMP0]], ptr [[PTR]], i32 7, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_za64(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_hor_za64(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_hor_za64(0, slice_base, pg, ptr); svst1_hor_za64(7, slice_base + 1, pg, ptr); } @@ -118,7 +112,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_za64(uint32_t slice_base, svbool_t pg, vo // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1q.horiz( [[TMP0]], ptr [[PTR]], i32 15, i32 [[SLICE_BASE]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_za128(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_hor_za128(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_hor_za128(0, slice_base, pg, ptr); svst1_hor_za128(15, slice_base, pg, ptr); } @@ -139,7 +133,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_za128(uint32_t slice_base, svbool_t pg, v // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1b.vert( [[PG]], ptr [[PTR]], i32 0, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_za8(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_ver_za8(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_ver_za8(0, slice_base, pg, ptr); svst1_ver_za8(0, slice_base + 15, pg, ptr); } @@ -162,7 +156,7 @@ ARM_STREAMING_ATTR void test_svst1_ver_za8(uint32_t slice_base, svbool_t pg, voi // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1h.vert( [[TMP0]], ptr [[PTR]], i32 1, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_za16(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_ver_za16(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_ver_za16(0, slice_base, pg, ptr); svst1_ver_za16(1, slice_base + 7, pg, ptr); } @@ -185,7 +179,7 @@ ARM_STREAMING_ATTR void test_svst1_ver_za16(uint32_t slice_base, svbool_t pg, vo // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1w.vert( [[TMP0]], ptr [[PTR]], i32 3, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_za32(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_ver_za32(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_ver_za32(0, slice_base, pg, ptr); svst1_ver_za32(3, slice_base + 3, pg, ptr); } @@ -208,7 +202,7 @@ ARM_STREAMING_ATTR void test_svst1_ver_za32(uint32_t slice_base, svbool_t pg, vo // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1d.vert( [[TMP0]], ptr [[PTR]], i32 7, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_za64(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_ver_za64(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_ver_za64(0, slice_base, pg, ptr); svst1_ver_za64(7, slice_base + 1, pg, ptr); } @@ -229,7 +223,7 @@ ARM_STREAMING_ATTR void test_svst1_ver_za64(uint32_t slice_base, svbool_t pg, vo // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1q.vert( [[TMP0]], ptr [[PTR]], i32 15, i32 [[SLICE_BASE]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_za128(uint32_t slice_base, svbool_t pg, void *ptr) { +void test_svst1_ver_za128(uint32_t slice_base, svbool_t pg, void *ptr) __arm_streaming { svst1_ver_za128(0, slice_base, pg, ptr); svst1_ver_za128(15, slice_base, pg, ptr); } diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c index 6b534f25a1f8..627098d9365b 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c @@ -1,17 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s #include -#ifdef DISABLE_SME_ATTRIBUTES -#define ARM_STREAMING_ATTR -#else -#define ARM_STREAMING_ATTR __attribute__((arm_streaming)) -#endif - // CHECK-C-LABEL: define dso_local void @test_svst1_hor_vnum_za8( // CHECK-C-SAME: i32 noundef [[SLICE_BASE:%.*]], [[PG:%.*]], ptr noundef [[PTR:%.*]], i64 noundef [[VNUM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-C-NEXT: entry: @@ -34,7 +28,7 @@ // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_vnum_za8(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_hor_vnum_za8(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_hor_vnum_za8(0, slice_base, pg, ptr, vnum); svst1_hor_vnum_za8(0, slice_base + 15, pg, ptr, vnum); } @@ -63,7 +57,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_vnum_za8(uint32_t slice_base, svbool_t pg // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1h.horiz( [[TMP0]], ptr [[TMP2]], i32 1, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_vnum_za16(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_hor_vnum_za16(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_hor_vnum_za16(0, slice_base, pg, ptr, vnum); svst1_hor_vnum_za16(1, slice_base + 7, pg, ptr, vnum); } @@ -92,7 +86,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_vnum_za16(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1w.horiz( [[TMP0]], ptr [[TMP2]], i32 3, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_vnum_za32(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_hor_vnum_za32(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_hor_vnum_za32(0, slice_base, pg, ptr, vnum); svst1_hor_vnum_za32(3, slice_base + 3, pg, ptr, vnum); } @@ -121,7 +115,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_vnum_za32(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1d.horiz( [[TMP0]], ptr [[TMP2]], i32 7, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_vnum_za64(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_hor_vnum_za64(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_hor_vnum_za64(0, slice_base, pg, ptr, vnum); svst1_hor_vnum_za64(7, slice_base + 1, pg, ptr, vnum); } @@ -148,7 +142,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_vnum_za64(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1q.horiz( [[TMP0]], ptr [[TMP2]], i32 15, i32 [[SLICE_BASE]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_hor_vnum_za128(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_hor_vnum_za128(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_hor_vnum_za128(0, slice_base, pg, ptr, vnum); svst1_hor_vnum_za128(15, slice_base, pg, ptr, vnum); } @@ -175,7 +169,7 @@ ARM_STREAMING_ATTR void test_svst1_hor_vnum_za128(uint32_t slice_base, svbool_t // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1b.vert( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_vnum_za8(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_ver_vnum_za8(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_ver_vnum_za8(0, slice_base, pg, ptr, vnum); svst1_ver_vnum_za8(0, slice_base + 15, pg, ptr, vnum); } @@ -204,7 +198,7 @@ ARM_STREAMING_ATTR void test_svst1_ver_vnum_za8(uint32_t slice_base, svbool_t pg // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1h.vert( [[TMP0]], ptr [[TMP2]], i32 1, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_vnum_za16(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_ver_vnum_za16(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_ver_vnum_za16(0, slice_base, pg, ptr, vnum); svst1_ver_vnum_za16(1, slice_base + 7, pg, ptr, vnum); } @@ -233,7 +227,7 @@ ARM_STREAMING_ATTR void test_svst1_ver_vnum_za16(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1w.vert( [[TMP0]], ptr [[TMP2]], i32 3, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_vnum_za32(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_ver_vnum_za32(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_ver_vnum_za32(0, slice_base, pg, ptr, vnum); svst1_ver_vnum_za32(3, slice_base + 3, pg, ptr, vnum); } @@ -262,7 +256,7 @@ ARM_STREAMING_ATTR void test_svst1_ver_vnum_za32(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1d.vert( [[TMP0]], ptr [[TMP2]], i32 7, i32 [[ADD]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_vnum_za64(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_ver_vnum_za64(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_ver_vnum_za64(0, slice_base, pg, ptr, vnum); svst1_ver_vnum_za64(7, slice_base + 1, pg, ptr, vnum); } @@ -289,7 +283,7 @@ ARM_STREAMING_ATTR void test_svst1_ver_vnum_za64(uint32_t slice_base, svbool_t p // CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.st1q.vert( [[TMP0]], ptr [[TMP2]], i32 15, i32 [[SLICE_BASE]]) // CHECK-CXX-NEXT: ret void // -ARM_STREAMING_ATTR void test_svst1_ver_vnum_za128(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) { +void test_svst1_ver_vnum_za128(uint32_t slice_base, svbool_t pg, void *ptr, int64_t vnum) __arm_streaming { svst1_ver_vnum_za128(0, slice_base, pg, ptr, vnum); svst1_ver_vnum_za128(15, slice_base, pg, ptr, vnum); } diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c new file mode 100644 index 000000000000..a3ee7d2092f7 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c @@ -0,0 +1,499 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +// CHECK-LABEL: @test_cvt_f16_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcvt.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z15test_cvt_f16_x213svfloat32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcvt.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svfloat16_t test_cvt_f16_x2(svfloat32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_f16,_f32_x2,,)(zn); +} + +// CHECK-LABEL: @test_cvt_bf16_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bfcvt.x2( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z16test_cvt_bf16_x213svfloat32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bfcvt.x2( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svbfloat16_t test_cvt_bf16_x2(svfloat32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_bf16,_f32_x2,,)(zn); +} + + +// x2 +// CHECK-LABEL: @test_svcvt_f32_u32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call { , } @llvm.aarch64.sve.fcvtu.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP2]], 0 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP3]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[TMP2]], 1 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP4]], [[TMP5]], i64 4) +// CHECK-NEXT: ret [[TMP6]] +// +// CPP-CHECK-LABEL: @_Z21test_svcvt_f32_u32_x212svuint32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call { , } @llvm.aarch64.sve.fcvtu.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP2]], 0 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP3]], i64 0) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[TMP2]], 1 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP4]], [[TMP5]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP6]] +// +svfloat32x2_t test_svcvt_f32_u32_x2(svuint32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_f32,_u32_x2,,)(zn); +} + +// CHECK-LABEL: @test_svcvt_f32_s32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call { , } @llvm.aarch64.sve.fcvts.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP2]], 0 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP3]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[TMP2]], 1 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP4]], [[TMP5]], i64 4) +// CHECK-NEXT: ret [[TMP6]] +// +// CPP-CHECK-LABEL: @_Z21test_svcvt_f32_s32_x211svint32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call { , } @llvm.aarch64.sve.fcvts.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP2]], 0 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP3]], i64 0) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[TMP2]], 1 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP4]], [[TMP5]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP6]] +// +svfloat32x2_t test_svcvt_f32_s32_x2(svint32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_f32,_s32_x2,,)(zn); +} + +// CHECK-LABEL: @test_svcvt_u32_f32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP2]], 0 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP3]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[TMP2]], 1 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP4]], [[TMP5]], i64 4) +// CHECK-NEXT: ret [[TMP6]] +// +// CPP-CHECK-LABEL: @_Z21test_svcvt_u32_f32_x213svfloat32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP2]], 0 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP3]], i64 0) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[TMP2]], 1 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP4]], [[TMP5]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP6]] +// +svuint32x2_t test_svcvt_u32_f32_x2(svfloat32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_u32,_f32_x2,,)(zn); +} + +// CHECK-LABEL: @test_svcvt_s32_f32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP2]], 0 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP3]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[TMP2]], 1 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP4]], [[TMP5]], i64 4) +// CHECK-NEXT: ret [[TMP6]] +// +// CPP-CHECK-LABEL: @_Z21test_svcvt_s32_f32_x213svfloat32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP2]], 0 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP3]], i64 0) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[TMP2]], 1 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP4]], [[TMP5]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP6]] +// +svint32x2_t test_svcvt_s32_f32_x2(svfloat32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_s32,_f32_x2,,)(zn); +} + +// x4 +// CHECK-LABEL: @test_svcvt_f32_u32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call { , , , } @llvm.aarch64.sve.fcvtu.x4.nxv4f32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP4]], 0 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( poison, [[TMP5]], i64 0) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP4]], 1 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP6]], [[TMP7]], i64 4) +// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { , , , } [[TMP4]], 2 +// CHECK-NEXT: [[TMP10:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP8]], [[TMP9]], i64 8) +// CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , , , } [[TMP4]], 3 +// CHECK-NEXT: [[TMP12:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP10]], [[TMP11]], i64 12) +// CHECK-NEXT: ret [[TMP12]] +// +// CPP-CHECK-LABEL: @_Z21test_svcvt_f32_u32_x412svuint32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call { , , , } @llvm.aarch64.sve.fcvtu.x4.nxv4f32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP4]], 0 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( poison, [[TMP5]], i64 0) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP4]], 1 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP6]], [[TMP7]], i64 4) +// CPP-CHECK-NEXT: [[TMP9:%.*]] = extractvalue { , , , } [[TMP4]], 2 +// CPP-CHECK-NEXT: [[TMP10:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP8]], [[TMP9]], i64 8) +// CPP-CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , , , } [[TMP4]], 3 +// CPP-CHECK-NEXT: [[TMP12:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP10]], [[TMP11]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP12]] +// +svfloat32x4_t test_svcvt_f32_u32_x4(svuint32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_f32,_u32_x4,,)(zn); +} + +// CHECK-LABEL: @test_svcvt_f32_s32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call { , , , } @llvm.aarch64.sve.fcvts.x4.nxv4f32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP4]], 0 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( poison, [[TMP5]], i64 0) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP4]], 1 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP6]], [[TMP7]], i64 4) +// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { , , , } [[TMP4]], 2 +// CHECK-NEXT: [[TMP10:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP8]], [[TMP9]], i64 8) +// CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , , , } [[TMP4]], 3 +// CHECK-NEXT: [[TMP12:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP10]], [[TMP11]], i64 12) +// CHECK-NEXT: ret [[TMP12]] +// +// CPP-CHECK-LABEL: @_Z21test_svcvt_f32_s32_x411svint32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call { , , , } @llvm.aarch64.sve.fcvts.x4.nxv4f32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP4]], 0 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( poison, [[TMP5]], i64 0) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP4]], 1 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP6]], [[TMP7]], i64 4) +// CPP-CHECK-NEXT: [[TMP9:%.*]] = extractvalue { , , , } [[TMP4]], 2 +// CPP-CHECK-NEXT: [[TMP10:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP8]], [[TMP9]], i64 8) +// CPP-CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , , , } [[TMP4]], 3 +// CPP-CHECK-NEXT: [[TMP12:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP10]], [[TMP11]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP12]] +// +svfloat32x4_t test_svcvt_f32_s32_x4(svint32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_f32,_s32_x4,,)(zn); +} + +// CHECK-LABEL: @test_svcvt_u32_f32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call { , , , } @llvm.aarch64.sve.ucvtf.x4.nxv4f32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP4]], 0 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP5]], i64 0) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP4]], 1 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 4) +// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { , , , } [[TMP4]], 2 +// CHECK-NEXT: [[TMP10:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP8]], [[TMP9]], i64 8) +// CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , , , } [[TMP4]], 3 +// CHECK-NEXT: [[TMP12:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP10]], [[TMP11]], i64 12) +// CHECK-NEXT: ret [[TMP12]] +// +// CPP-CHECK-LABEL: @_Z21test_svcvt_u32_f32_x413svfloat32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call { , , , } @llvm.aarch64.sve.ucvtf.x4.nxv4f32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP4]], 0 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP5]], i64 0) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP4]], 1 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 4) +// CPP-CHECK-NEXT: [[TMP9:%.*]] = extractvalue { , , , } [[TMP4]], 2 +// CPP-CHECK-NEXT: [[TMP10:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP8]], [[TMP9]], i64 8) +// CPP-CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , , , } [[TMP4]], 3 +// CPP-CHECK-NEXT: [[TMP12:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP10]], [[TMP11]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP12]] +// +svuint32x4_t test_svcvt_u32_f32_x4(svfloat32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_u32,_f32_x4,,)(zn); +} + +// CHECK-LABEL: @test_svcvt_s32_f32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call { , , , } @llvm.aarch64.sve.scvtf.x4.nxv4f32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP4]], 0 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP5]], i64 0) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP4]], 1 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 4) +// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { , , , } [[TMP4]], 2 +// CHECK-NEXT: [[TMP10:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP8]], [[TMP9]], i64 8) +// CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , , , } [[TMP4]], 3 +// CHECK-NEXT: [[TMP12:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP10]], [[TMP11]], i64 12) +// CHECK-NEXT: ret [[TMP12]] +// +// CPP-CHECK-LABEL: @_Z21test_svcvt_s32_f32_x413svfloat32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv16f32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call { , , , } @llvm.aarch64.sve.scvtf.x4.nxv4f32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP4]], 0 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP5]], i64 0) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP4]], 1 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 4) +// CPP-CHECK-NEXT: [[TMP9:%.*]] = extractvalue { , , , } [[TMP4]], 2 +// CPP-CHECK-NEXT: [[TMP10:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP8]], [[TMP9]], i64 8) +// CPP-CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , , , } [[TMP4]], 3 +// CPP-CHECK-NEXT: [[TMP12:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP10]], [[TMP11]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP12]] +// +svint32x4_t test_svcvt_s32_f32_x4(svfloat32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvt_s32,_f32_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvt_s16_s32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqcvt.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z20test_qcvt_s16_s32_x211svint32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqcvt.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svint16_t test_qcvt_s16_s32_x2(svint32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvt_s16,_s32_x2,,)(zn); +} + +// CHECK-LABEL: @test_qcvt_u16_u32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqcvt.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z20test_qcvt_u16_u32_x212svuint32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqcvt.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svuint16_t test_qcvt_u16_u32_x2(svuint32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvt_u16,_u32_x2,,)(zn); +} + +// CHECK-LABEL: @test_qcvt_u16_s32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqcvtu.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z20test_qcvt_u16_s32_x211svint32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqcvtu.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svuint16_t test_qcvt_u16_s32_x2(svint32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvt_u16,_s32_x2,,)(zn); +} + +// CHECK-LABEL: @test_qcvt_u8_u32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.uqcvt.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z19test_qcvt_u8_u32_x412svuint32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.uqcvt.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint8_t test_qcvt_u8_u32_x4(svuint32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvt_u8,_u32_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvt_u16_u64_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.uqcvt.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z20test_qcvt_u16_u64_x412svuint64x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.uqcvt.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint16_t test_qcvt_u16_u64_x4(svuint64x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvt_u16,_u64_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvt_s8_s32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvt.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z19test_qcvt_s8_s32_x411svint32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvt.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint8_t test_qcvt_s8_s32_x4(svint32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvt_s8,_s32_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvt_s16_s64_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvt.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z20test_qcvt_s16_s64_x411svint64x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvt.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint16_t test_qcvt_s16_s64_x4(svint64x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvt_s16,_s64_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvt_u8_s32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtu.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z19test_qcvt_u8_s32_x411svint32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtu.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint8_t test_qcvt_u8_s32_x4(svint32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvt_u8,_s32_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvt_u16_s64_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtu.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z20test_qcvt_u16_s64_x411svint64x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtu.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint16_t test_qcvt_u16_s64_x4(svint64x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvt_u16,_s64_x4,,)(zn); +} diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c new file mode 100644 index 000000000000..84aa6764ba38 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c @@ -0,0 +1,242 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +// CHECK-LABEL: @test_cvtn_f16_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcvtn.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z16test_cvtn_f16_x213svfloat32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.fcvtn.x2.nxv4f32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svfloat16_t test_cvtn_f16_x2(svfloat32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvtn_f16,_f32_x2,,)(zn); +} + +// CHECK-LABEL: @test_cvtn_bf16_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bfcvtn.x2( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z17test_cvtn_bf16_x213svfloat32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4f32.nxv8f32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.bfcvtn.x2( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svbfloat16_t test_cvtn_bf16_x2(svfloat32x2_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svcvtn_bf16,_f32_x2,,)(zn); +} + +// CHECK-LABEL: @test_qcvtn_s16_s32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqcvtn.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z21test_qcvtn_s16_s32_x211svint32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqcvtn.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svint16_t test_qcvtn_s16_s32_x2(svint32x2_t zn) __arm_streaming_compatible { + return SVE_ACLE_FUNC(svqcvtn_s16,_s32_x2,,)(zn); +} + +// CHECK-LABEL: @test_qcvtn_u16_u32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqcvtn.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z21test_qcvtn_u16_u32_x212svuint32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.uqcvtn.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svuint16_t test_qcvtn_u16_u32_x2(svuint32x2_t zn) __arm_streaming_compatible { + return SVE_ACLE_FUNC(svqcvtn_u16,_u32_x2,,)(zn); +} + +// CHECK-LABEL: @test_qcvtn_u16_s32_x2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqcvtun.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CHECK-NEXT: ret [[TMP2]] +// +// CPP-CHECK-LABEL: @_Z21test_qcvtn_u16_s32_x211svint32x2_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv8i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.sqcvtun.x2.nxv4i32( [[TMP0]], [[TMP1]]) +// CPP-CHECK-NEXT: ret [[TMP2]] +// +svuint16_t test_qcvtn_u16_s32_x2(svint32x2_t zn) __arm_streaming_compatible { + return SVE_ACLE_FUNC(svqcvtn_u16,_s32_x2,,)(zn); +} + +// CHECK-LABEL: @test_qcvtn_u8_u32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.uqcvtn.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z20test_qcvtn_u8_u32_x412svuint32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.uqcvtn.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint8_t test_qcvtn_u8_u32_x4(svuint32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvtn_u8,_u32_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvtn_u16_u64_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.uqcvtn.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z21test_qcvtn_u16_u64_x412svuint64x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.uqcvtn.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint16_t test_qcvtn_u16_u64_x4(svuint64x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvtn_u16,_u64_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvtn_s8_s32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtn.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z20test_qcvtn_s8_s32_x411svint32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtn.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint8_t test_qcvtn_s8_s32_x4(svint32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvtn_s8,_s32_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvtn_s16_s64_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtn.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z21test_qcvtn_s16_s64_x411svint64x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtn.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint16_t test_qcvtn_s16_s64_x4(svint64x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvtn_s16,_s64_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvtn_u8_32_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtun.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z19test_qcvtn_u8_32_x411svint32x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 8) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv4i32.nxv16i32( [[ZN]], i64 12) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtun.x4.nxv4i32( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint8_t test_qcvtn_u8_32_x4(svint32x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvtn_u8,_s32_x4,,)(zn); +} + +// CHECK-LABEL: @test_qcvtn_u16_s64_x4( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtun.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z21test_qcvtn_u16_s64_x411svint64x4_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN:%.*]], i64 0) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 2) +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 4) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv2i64.nxv8i64( [[ZN]], i64 6) +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.aarch64.sve.sqcvtun.x4.nxv2i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint16_t test_qcvtn_u16_s64_x4(svint64x4_t zn) __arm_streaming { + return SVE_ACLE_FUNC(svqcvtn_u16,_s64_x4,,)(zn); +} + + diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c index 126a4fc10458..83fbd6e5855c 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c @@ -20,7 +20,7 @@ // CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr [[BASE:%.*]]) // CPP-CHECK-NEXT: ret void // -void test_svldr_zt(const void *base) __arm_streaming_compatible __arm_shared_za __arm_preserves_za { +void test_svldr_zt(const void *base) __arm_streaming_compatible __arm_shared_za { svldr_zt(0, base); } diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c new file mode 100644 index 000000000000..cb34db3695b2 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c @@ -0,0 +1,138 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +#include + + +// CHECK-LABEL: @test_svluti2_lane_zt_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, [[ZN:%.*]], i32 15) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti2_lane_zt_u8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, [[ZN:%.*]], i32 15) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svuint8_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_u8(0, zn, 15); +} + + +// CHECK-LABEL: @test_svluti2_lane_zt_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, [[ZN:%.*]], i32 15) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti2_lane_zt_s8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, [[ZN:%.*]], i32 15) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svint8_t test_svluti2_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_s8(0, zn, 15); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, [[ZN:%.*]], i32 15) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_u16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, [[ZN:%.*]], i32 15) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svuint16_t test_svluti2_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_u16(0, zn, 15); +} + + +// CHECK-LABEL: @test_svluti2_lane_zt_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, [[ZN:%.*]], i32 15) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_s16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, [[ZN:%.*]], i32 15) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svint16_t test_svluti2_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_s16(0, zn, 15); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, [[ZN:%.*]], i32 15) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, [[ZN:%.*]], i32 15) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svfloat16_t test_svluti2_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f16(0, zn, 15); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_bf16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, [[ZN:%.*]], i32 15) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z25test_svluti2_lane_zt_bf16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, [[ZN:%.*]], i32 15) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svbfloat16_t test_svluti2_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_bf16(0, zn, 15); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, [[ZN:%.*]], i32 15) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_u32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, [[ZN:%.*]], i32 15) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svuint32_t test_svluti2_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_u32(0, zn, 15); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, [[ZN:%.*]], i32 15) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_s32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, [[ZN:%.*]], i32 15) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svint32_t test_svluti2_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_s32(0, zn, 15); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, [[ZN:%.*]], i32 15) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, [[ZN:%.*]], i32 15) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svfloat32_t test_svluti2_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f32(0, zn, 15); +} diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c new file mode 100644 index 000000000000..04f37af46767 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c @@ -0,0 +1,209 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +#include + +// CHECK-LABEL: @test_svluti2_lane_zt_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti2_lane_zt_u8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint8x2_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_u8_x2(0, zn, 7); +} + + +// CHECK-LABEL: @test_svluti2_lane_zt_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti2_lane_zt_s8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint8x2_t test_svluti2_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_s8_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_u16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint16x2_t test_svluti2_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_u16_x2(0, zn, 7); +} + + +// CHECK-LABEL: @test_svluti2_lane_zt_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_s16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint16x2_t test_svluti2_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_s16_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svfloat16x2_t test_svluti2_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f16_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_bf16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z25test_svluti2_lane_zt_bf16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svbfloat16x2_t test_svluti2_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_bf16_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_u32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint32x2_t test_svluti2_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_u32_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_s32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint32x2_t test_svluti2_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_s32_x2(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svfloat32x2_t test_svluti2_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f32_x2(0, zn, 7); +} diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c new file mode 100644 index 000000000000..8c38d829a7f4 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c @@ -0,0 +1,280 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +#include + +// CHECK-LABEL: @test_svluti2_lane_zt_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP4]], [[TMP5]], i64 32) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP6]], [[TMP7]], i64 48) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti2_lane_zt_u8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP4]], [[TMP5]], i64 32) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP6]], [[TMP7]], i64 48) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svuint8x4_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_u8_x4(0, zn, 3); +} + + +// CHECK-LABEL: @test_svluti2_lane_zt_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP4]], [[TMP5]], i64 32) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP6]], [[TMP7]], i64 48) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti2_lane_zt_s8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP4]], [[TMP5]], i64 32) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv64i8.nxv16i8( [[TMP6]], [[TMP7]], i64 48) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svint8x4_t test_svluti2_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_s8_x4(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP4]], [[TMP5]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP6]], [[TMP7]], i64 24) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_u16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP4]], [[TMP5]], i64 16) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP6]], [[TMP7]], i64 24) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svuint16x4_t test_svluti2_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_u16_x4(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP4]], [[TMP5]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP6]], [[TMP7]], i64 24) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_s16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP4]], [[TMP5]], i64 16) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP6]], [[TMP7]], i64 24) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svint16x4_t test_svluti2_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_s16_x4(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP4]], [[TMP5]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP6]], [[TMP7]], i64 24) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP4]], [[TMP5]], i64 16) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP6]], [[TMP7]], i64 24) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svfloat16x4_t test_svluti2_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f16_x4(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_bf16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP4]], [[TMP5]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP6]], [[TMP7]], i64 24) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: @_Z25test_svluti2_lane_zt_bf16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP4]], [[TMP5]], i64 16) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP6]], [[TMP7]], i64 24) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svbfloat16x4_t test_svluti2_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_bf16_x4(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP4]], [[TMP5]], i64 8) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 12) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_u32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP4]], [[TMP5]], i64 8) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svuint32x4_t test_svluti2_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_u32_x4(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP4]], [[TMP5]], i64 8) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 12) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_s32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP4]], [[TMP5]], i64 8) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svint32x4_t test_svluti2_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_s32_x4(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti2_lane_zt_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP4]], [[TMP5]], i64 8) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP6]], [[TMP7]], i64 12) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti2_lane_zt_f32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP4]], [[TMP5]], i64 8) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP6]], [[TMP7]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svfloat32x4_t test_svluti2_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti2_lane_zt_f32_x4(0, zn, 3); +} diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c new file mode 100644 index 000000000000..9815b0e825b3 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c @@ -0,0 +1,137 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +#include + + +// CHECK-LABEL: @test_svluti4_lane_zt_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti4_lane_zt_u8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svuint8_t test_svluti4_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_u8(0, zn, 7); +} + + +// CHECK-LABEL: @test_svluti4_lane_zt_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti4_lane_zt_s8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svint8_t test_svluti4_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_s8(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_u16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svuint16_t test_svluti4_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_u16(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_s16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svint16_t test_svluti4_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_s16(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_f16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svfloat16_t test_svluti4_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_f16(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_bf16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z25test_svluti4_lane_zt_bf16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svbfloat16_t test_svluti4_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_bf16(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_u32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svuint32_t test_svluti4_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_u32(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_s32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svint32_t test_svluti4_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_s32(0, zn, 7); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, [[ZN:%.*]], i32 7) +// CHECK-NEXT: ret [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_f32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, [[ZN:%.*]], i32 7) +// CPP-CHECK-NEXT: ret [[TMP0]] +// +svfloat32_t test_svluti4_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_f32(0, zn, 7); +} diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c new file mode 100644 index 000000000000..4c181dd9123c --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c @@ -0,0 +1,209 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +#include + +// CHECK-LABEL: @test_svluti4_lane_zt_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti4_lane_zt_u8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint8x2_t test_svluti4_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_u8_x2(0, zn, 3); +} + + +// CHECK-LABEL: @test_svluti4_lane_zt_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z23test_svluti4_lane_zt_s8u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i8.nxv16i8( [[TMP2]], [[TMP3]], i64 16) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint8x2_t test_svluti4_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_s8_x2(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_u16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint16x2_t test_svluti4_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_u16_x2(0, zn, 3); +} + + +// CHECK-LABEL: @test_svluti4_lane_zt_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_s16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint16x2_t test_svluti4_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_s16_x2(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_f16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svfloat16x2_t test_svluti4_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_f16_x2(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_bf16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z25test_svluti4_lane_zt_bf16u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svbfloat16x2_t test_svluti4_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_bf16_x2(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_u32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svuint32x2_t test_svluti4_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_u32_x2(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_s32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svint32x2_t test_svluti4_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_s32_x2(0, zn, 3); +} + +// CHECK-LABEL: @test_svluti4_lane_zt_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, [[ZN:%.*]], i32 3) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: ret [[TMP4]] +// +// CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_f32u11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, [[ZN:%.*]], i32 3) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: ret [[TMP4]] +// +svfloat32x2_t test_svluti4_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_f32_x2(0, zn, 3); +} diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c new file mode 100644 index 000000000000..9baccef888d5 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c @@ -0,0 +1,233 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 + +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s + +#include + +// CHECK-LABEL: define dso_local @test_svluti4_lane_zt_u16 +// CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, [[ZN]], i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP4]], [[TMP5]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP6]], [[TMP7]], i64 24) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: define dso_local @_Z24test_svluti4_lane_zt_u16u11__SVUint8_t +// CPP-CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0:[0-9]+]] { +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, [[ZN]], i32 1) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP4]], [[TMP5]], i64 16) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP6]], [[TMP7]], i64 24) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svuint16x4_t test_svluti4_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_u16_x4(0, zn, 1); +} + +// CHECK-LABEL: define dso_local @test_svluti4_lane_zt_f16 +// CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, [[ZN]], i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP4]], [[TMP5]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP6]], [[TMP7]], i64 24) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: define dso_local @_Z24test_svluti4_lane_zt_f16u11__SVUint8_t +// CPP-CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, [[ZN]], i32 1) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP4]], [[TMP5]], i64 16) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32f16.nxv8f16( [[TMP6]], [[TMP7]], i64 24) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svfloat16x4_t test_svluti4_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_f16_x4(0, zn, 1); +} + +// CHECK-LABEL: define dso_local @test_svluti4_lane_zt_bf16 +// CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, [[ZN]], i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP4]], [[TMP5]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP6]], [[TMP7]], i64 24) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: define dso_local @_Z25test_svluti4_lane_zt_bf16u11__SVUint8_t +// CPP-CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, [[ZN]], i32 1) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP4]], [[TMP5]], i64 16) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP6]], [[TMP7]], i64 24) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svbfloat16x4_t test_svluti4_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_bf16_x4(0, zn, 1); +} + +// CHECK-LABEL: define dso_local @test_svluti4_lane_zt_s16 +// CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, [[ZN]], i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP4]], [[TMP5]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP6]], [[TMP7]], i64 24) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: define dso_local @_Z24test_svluti4_lane_zt_s16u11__SVUint8_t +// CPP-CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, [[ZN]], i32 1) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP2]], [[TMP3]], i64 8) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP4]], [[TMP5]], i64 16) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv32i16.nxv8i16( [[TMP6]], [[TMP7]], i64 24) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svint16x4_t test_svluti4_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_s16_x4(0, zn, 1); +} + +// CHECK-LABEL: define dso_local @test_svluti4_lane_zt_u32 +// CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, [[ZN]], i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP4]], [[TMP5]], i64 8) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 12) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: define dso_local @_Z24test_svluti4_lane_zt_u32u11__SVUint8_t +// CPP-CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, [[ZN]], i32 1) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP4]], [[TMP5]], i64 8) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svuint32x4_t test_svluti4_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_u32_x4(0, zn, 1); +} + +// CHECK-LABEL: define dso_local @test_svluti4_lane_zt_s32 +// CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, [[ZN]], i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP4]], [[TMP5]], i64 8) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 12) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: define dso_local @_Z24test_svluti4_lane_zt_s32u11__SVUint8_t +// CPP-CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, [[ZN]], i32 1) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP4]], [[TMP5]], i64 8) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16i32.nxv4i32( [[TMP6]], [[TMP7]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svint32x4_t test_svluti4_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_s32_x4(0, zn, 1); +} + +// CHECK-LABEL: define dso_local @test_svluti4_lane_zt_f32 +// CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, [[ZN]], i32 1) +// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( poison, [[TMP1]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP4]], [[TMP5]], i64 8) +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP6]], [[TMP7]], i64 12) +// CHECK-NEXT: ret [[TMP8]] +// +// CPP-CHECK-LABEL: define dso_local @_Z24test_svluti4_lane_zt_f32u11__SVUint8_t +// CPP-CHECK-SAME: ( [[ZN:%.*]]) #[[ATTR0]] { +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, [[ZN]], i32 1) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( poison, [[TMP1]], i64 0) +// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP2]], [[TMP3]], i64 4) +// CPP-CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CPP-CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP4]], [[TMP5]], i64 8) +// CPP-CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CPP-CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.vector.insert.nxv16f32.nxv4f32( [[TMP6]], [[TMP7]], i64 12) +// CPP-CHECK-NEXT: ret [[TMP8]] +// +svfloat32x4_t test_svluti4_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + return svluti4_lane_zt_f32_x4(0, zn, 1); +} diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c index 5432862dcf52..19993e541812 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c @@ -1,18 +1,13 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -#include +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -#ifdef SVE_OVERLOADED_FORMS -// A simple used,unused... macro, long enough to represent any SVE builtin. -#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 -#else -#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 -#endif +#include // CHECK-LABEL: @test_svpfalse_c( // CHECK-NEXT: entry: @@ -24,7 +19,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt( zeroinitializer) // CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] // -svcount_t test_svpfalse_c() +svcount_t test_svpfalse_c(void) __arm_streaming_compatible { - return SVE_ACLE_FUNC(svpfalse_c,,,)(); + return svpfalse_c(); } diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c index c8fd84350056..7f9d60a3d320 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c @@ -1,10 +1,18 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -DTEST_SME2 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DTEST_SME2 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK #include +#ifndef TEST_SME2 +#define ATTR +#else +#define ATTR __arm_streaming +#endif + // CHECK-LABEL: @test_svptrue_c8( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8() @@ -15,7 +23,7 @@ // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8() // CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] // -svcount_t test_svptrue_c8(void) { +svcount_t test_svptrue_c8(void) ATTR { return svptrue_c8(); } @@ -29,7 +37,7 @@ svcount_t test_svptrue_c8(void) { // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c16() // CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] // -svcount_t test_svptrue_c16(void) { +svcount_t test_svptrue_c16(void) ATTR { return svptrue_c16(); } @@ -43,7 +51,7 @@ svcount_t test_svptrue_c16(void) { // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c32() // CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] // -svcount_t test_svptrue_c32(void) { +svcount_t test_svptrue_c32(void) ATTR { return svptrue_c32(); } @@ -57,6 +65,6 @@ svcount_t test_svptrue_c32(void) { // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c64() // CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] // -svcount_t test_svptrue_c64(void) { +svcount_t test_svptrue_c64(void) ATTR { return svptrue_c64(); } diff --git a/clang/test/CodeGen/atomic-ops.c b/clang/test/CodeGen/atomic-ops.c index 1295786524a0..9ac05d270b97 100644 --- a/clang/test/CodeGen/atomic-ops.c +++ b/clang/test/CodeGen/atomic-ops.c @@ -697,9 +697,9 @@ void test_underaligned(void) { __atomic_load(&aligned_a, &aligned_b, memory_order_seq_cst); // CHECK: store atomic i64 {{.*}}, align 16 __atomic_store(&aligned_a, &aligned_b, memory_order_seq_cst); - // CHECK: atomicrmw xchg ptr {{.*}}, align 8 + // CHECK: atomicrmw xchg ptr {{.*}}, align 16 __atomic_exchange(&aligned_a, &aligned_b, &aligned_c, memory_order_seq_cst); - // CHECK: cmpxchg weak ptr {{.*}}, align 8 + // CHECK: cmpxchg weak ptr {{.*}}, align 16 __atomic_compare_exchange(&aligned_a, &aligned_b, &aligned_c, 1, memory_order_seq_cst, memory_order_seq_cst); } diff --git a/clang/test/CodeGen/attr-target-clones.c b/clang/test/CodeGen/attr-target-clones.c index 98ffea40f56d..4b99914031b1 100644 --- a/clang/test/CodeGen/attr-target-clones.c +++ b/clang/test/CodeGen/attr-target-clones.c @@ -16,13 +16,23 @@ // LINUX: @__cpu_model = external dso_local global { i32, i32, i32, [1 x i32] } // LINUX: @__cpu_features2 = external dso_local global [3 x i32] -// LINUX: @internal.ifunc = internal ifunc i32 (), ptr @internal.resolver -// LINUX: @foo.ifunc = weak_odr ifunc i32 (), ptr @foo.resolver -// LINUX: @foo_dupes.ifunc = weak_odr ifunc void (), ptr @foo_dupes.resolver -// LINUX: @unused.ifunc = weak_odr ifunc void (), ptr @unused.resolver -// LINUX: @foo_inline.ifunc = weak_odr ifunc i32 (), ptr @foo_inline.resolver -// LINUX: @foo_inline2.ifunc = weak_odr ifunc i32 (), ptr @foo_inline2.resolver -// LINUX: @foo_used_no_defn.ifunc = weak_odr ifunc i32 (), ptr @foo_used_no_defn.resolver +// LINUX: @internal.ifunc = internal alias i32 (), ptr @internal +// LINUX: @foo.ifunc = weak_odr alias i32 (), ptr @foo +// LINUX: @foo_dupes.ifunc = weak_odr alias void (), ptr @foo_dupes +// LINUX: @unused.ifunc = weak_odr alias void (), ptr @unused +// LINUX: @foo_inline.ifunc = weak_odr alias i32 (), ptr @foo_inline +// LINUX: @foo_inline2.ifunc = weak_odr alias i32 (), ptr @foo_inline2 +// LINUX: @foo_used_no_defn.ifunc = weak_odr alias i32 (), ptr @foo_used_no_defn +// LINUX: @isa_level.ifunc = weak_odr alias i32 (i32), ptr @isa_level + +// LINUX: @internal = internal ifunc i32 (), ptr @internal.resolver +// LINUX: @foo = weak_odr ifunc i32 (), ptr @foo.resolver +// LINUX: @foo_dupes = weak_odr ifunc void (), ptr @foo_dupes.resolver +// LINUX: @unused = weak_odr ifunc void (), ptr @unused.resolver +// LINUX: @foo_inline = weak_odr ifunc i32 (), ptr @foo_inline.resolver +// LINUX: @foo_inline2 = weak_odr ifunc i32 (), ptr @foo_inline2.resolver +// LINUX: @foo_used_no_defn = weak_odr ifunc i32 (), ptr @foo_used_no_defn.resolver +// LINUX: @isa_level = weak_odr ifunc i32 (i32), ptr @isa_level.resolver static int __attribute__((target_clones("sse4.2, default"))) internal(void) { return 0; } int use(void) { return internal(); } @@ -60,7 +70,7 @@ void bar2(void) { // LINUX: define {{.*}}void @bar2() // WINDOWS: define dso_local void @bar2() foo_dupes(); - // LINUX: call void @foo_dupes.ifunc() + // LINUX: call void @foo_dupes() // WINDOWS: call void @foo_dupes() } @@ -68,7 +78,7 @@ int bar(void) { // LINUX: define {{.*}}i32 @bar() #[[DEF:[0-9]+]] // WINDOWS: define dso_local i32 @bar() #[[DEF:[0-9]+]] return foo(); - // LINUX: call i32 @foo.ifunc() + // LINUX: call i32 @foo() // WINDOWS: call i32 @foo() } @@ -95,8 +105,8 @@ int bar3(void) { // LINUX: define {{.*}}i32 @bar3() // WINDOWS: define dso_local i32 @bar3() return foo_inline() + foo_inline2(); - // LINUX: call i32 @foo_inline.ifunc() - // LINUX: call i32 @foo_inline2.ifunc() + // LINUX: call i32 @foo_inline() + // LINUX: call i32 @foo_inline2() // WINDOWS: call i32 @foo_inline() // WINDOWS: call i32 @foo_inline2() } @@ -134,7 +144,7 @@ int test_foo_used_no_defn(void) { // LINUX: define {{.*}}i32 @test_foo_used_no_defn() // WINDOWS: define dso_local i32 @test_foo_used_no_defn() return foo_used_no_defn(); - // LINUX: call i32 @foo_used_no_defn.ifunc() + // LINUX: call i32 @foo_used_no_defn() // WINDOWS: call i32 @foo_used_no_defn() } diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-arr.c b/clang/test/CodeGen/bpf-preserve-static-offset-arr.c new file mode 100644 index 000000000000..295bd2919fc6 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-arr.c @@ -0,0 +1,33 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: bpf-registered-target +// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Check that call to preserve.static.offset is generated when array +// member of a struct marked with __attribute__((preserve_static_offset)) +// is accessed. + +#define __ctx __attribute__((preserve_static_offset)) + +struct foo { + struct { + int a; + } b[7]; +} __ctx; + +// CHECK-LABEL: define dso_local i32 @arr_access +// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) +// CHECK-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [7 x %struct.anon], ptr [[B]], i64 0, i64 2 +// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +// CHECK-NEXT: ret i32 [[TMP2]] +// +int arr_access(struct foo *p) { + return p->b[2].a; +} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c b/clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c new file mode 100644 index 000000000000..5983e6d27721 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-bitfield.c @@ -0,0 +1,31 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: bpf-registered-target +// RUN: %clang -cc1 -triple bpfel -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Check that call to preserve.static.offset is generated when bitfield +// from a struct marked with __attribute__((preserve_static_offset)) is +// accessed. + +#define __ctx __attribute__((preserve_static_offset)) + +struct foo { + unsigned a:1; +} __ctx; + +// CHECK-LABEL: define dso_local void @lvalue_bitfield +// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) +// CHECK-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[TMP1]], align 4 +// CHECK-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -2 +// CHECK-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 1 +// CHECK-NEXT: store i8 [[BF_SET]], ptr [[TMP1]], align 4 +// CHECK-NEXT: ret void +// +void lvalue_bitfield(struct foo *p) { + p->a = 1; +} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c b/clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c new file mode 100644 index 000000000000..4f0c359366f5 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-lvalue.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: bpf-registered-target +// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Check that call to preserve.static.offset is generated when field of +// a struct marked with __attribute__((preserve_static_offset)) is accessed. + +#define __ctx __attribute__((preserve_static_offset)) + +struct foo { + int a; +} __ctx; + +// CHECK-LABEL: define dso_local void @lvalue +// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) +// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: store i32 42, ptr [[A]], align 4 +// CHECK-NEXT: ret void +// +void lvalue(struct foo *p) { + p->a = 42; +} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c b/clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c new file mode 100644 index 000000000000..3fe8d2517fe3 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-non-bpf.c @@ -0,0 +1,18 @@ +// REQUIRES: x86-registered-target +// RUN: %clang -cc1 -triple x86_64 -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Verify that __attribute__((preserve_static_offset)) +// has no effect for non-BPF target. + +#define __ctx __attribute__((preserve_static_offset)) + +struct foo { + int a; +} __ctx; + +// CHECK-NOT: @llvm_preserve_static_offset + +int bar(struct foo *p) { + return p->a; +} diff --git a/clang/test/CodeGen/bpf-preserve-static-offset-pai.c b/clang/test/CodeGen/bpf-preserve-static-offset-pai.c new file mode 100644 index 000000000000..df1f33b1a664 --- /dev/null +++ b/clang/test/CodeGen/bpf-preserve-static-offset-pai.c @@ -0,0 +1,29 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: bpf-registered-target +// RUN: %clang -cc1 -triple bpf -disable-llvm-passes -S -emit-llvm -o - %s \ +// RUN: | FileCheck %s + +// Verify that preserve_static_offset does not interfere with +// preserve_access_index at IR generation stage. + +#define __ctx __attribute__((preserve_static_offset)) +#define __pai __attribute__((preserve_access_index)) + +struct foo { + int a; +} __ctx __pai; + +// CHECK-LABEL: define dso_local i32 @bar +// CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.preserve.static.offset(ptr [[TMP0]]) +// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 +// CHECK-NEXT: ret i32 [[TMP2]] +// +int bar(struct foo *p) { + return p->a; +} diff --git a/clang/test/CodeGen/ms-intrinsics-underaligned.c b/clang/test/CodeGen/ms-intrinsics-underaligned.c new file mode 100644 index 000000000000..e1f0d2cba8e2 --- /dev/null +++ b/clang/test/CodeGen/ms-intrinsics-underaligned.c @@ -0,0 +1,110 @@ +// RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ +// RUN: -triple x86_64--windows -Oz -emit-llvm -target-feature +cx16 %s -o - \ +// RUN: | FileCheck %s --check-prefixes=CHECK + +// RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ +// RUN: -triple aarch64--windows -Oz -emit-llvm %s -o - \ +// RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-AARCH64 + +// Ensure that we emit _Interlocked atomic operations specifying natural +// alignment, even when clang's usual alignment derivation would result in a +// lower alignment value. + +// intrin.h needs size_t, but -ffreestanding prevents us from getting it from +// stddef.h. Work around it with this typedef. +typedef __SIZE_TYPE__ size_t; + +#include + +#pragma pack(1) +typedef struct { + char a; + short b; + long c; + long long d; + void *p; +} X; + +_Static_assert(sizeof(X) == 23, ""); +_Static_assert(__alignof__(X) == 1, ""); + +// CHECK-LABEL: @test_InterlockedExchangePointer( +// CHECK: atomicrmw {{.*}} align 8 +void *test_InterlockedExchangePointer(X *x) { + return _InterlockedExchangePointer(&x->p, 0); +} + +// CHECK-LABEL: @test_InterlockedExchange8( +// CHECK: atomicrmw {{.*}} align 1 +char test_InterlockedExchange8(X *x) { + return _InterlockedExchange8(&x->a, 0); +} + +// CHECK-LABEL: @test_InterlockedExchange16( +// CHECK: atomicrmw {{.*}} align 2 +short test_InterlockedExchange16(X *x) { + return _InterlockedExchange16(&x->b, 0); +} + +// CHECK-LABEL: @test_InterlockedExchange( +// CHECK: atomicrmw {{.*}} align 4 +long test_InterlockedExchange(X *x) { + return _InterlockedExchange(&x->c, 0); +} + +// CHECK-LABEL: @test_InterlockedExchange64( +// CHECK: atomicrmw {{.*}} align 8 +long long test_InterlockedExchange64(X *x) { + return _InterlockedExchange64(&x->d, 0); +} + +// CHECK-LABEL: @test_InterlockedIncrement( +// CHECK: atomicrmw {{.*}} align 4 +long test_InterlockedIncrement(X *x) { + return _InterlockedIncrement(&x->c); +} + +// CHECK-LABEL: @test_InterlockedDecrement16( +// CHECK: atomicrmw {{.*}} align 2 +short test_InterlockedDecrement16(X *x) { + return _InterlockedDecrement16(&x->b); +} + + +// CHECK-LABEL: @test_InterlockedCompareExchangePointer( +// CHECK: cmpxchg {{.*}} align 8 +void *test_InterlockedCompareExchangePointer(X *x) { + return _InterlockedCompareExchangePointer(&x->p, 0, 0); +} + +// CHECK-LABEL: @test_InterlockedCompareExchange8( +// CHECK: cmpxchg {{.*}} align 1 +char test_InterlockedCompareExchange8(X *x) { + return _InterlockedCompareExchange8(&x->a, 0, 0); +} + +// CHECK-LABEL: @test_InterlockedCompareExchange16( +// CHECK: cmpxchg {{.*}} align 2 +short test_InterlockedCompareExchange16(X *x) { + return _InterlockedCompareExchange16(&x->b, 0, 0); +} + +// CHECK-LABEL: @test_InterlockedCompareExchange( +// CHECK: cmpxchg {{.*}} align 4 +long test_InterlockedCompareExchange(X *x) { + return _InterlockedCompareExchange(&x->c, 0, 0); +} + +// CHECK-LABEL: @test_InterlockedCompareExchange64( +// CHECK: cmpxchg {{.*}} align 8 +long long test_InterlockedCompareExchange64(X *x) { + return _InterlockedCompareExchange64(&x->d, 0, 0); +} + +#ifdef __aarch64__ +// CHECK-AARCH64-LABEL: @test_InterlockedAdd( +// CHECK-AARCH64: atomicrmw {{.*}} align 4 +long test_InterlockedAdd(X *x) { + return _InterlockedAdd(&x->c, 4); +} +#endif diff --git a/clang/test/CodeGen/ms-intrinsics.c b/clang/test/CodeGen/ms-intrinsics.c index debc84404aed..ffab8b998d8b 100644 --- a/clang/test/CodeGen/ms-intrinsics.c +++ b/clang/test/CodeGen/ms-intrinsics.c @@ -445,10 +445,10 @@ unsigned char test_InterlockedCompareExchange128( // CHECK-64: [[EL:%[0-9]+]] = zext i64 %inc1 to i128 // CHECK-64: [[EHS:%[0-9]+]] = shl nuw i128 [[EH]], 64 // CHECK-64: [[EXP:%[0-9]+]] = or disjoint i128 [[EHS]], [[EL]] -// CHECK-64: [[ORG:%[0-9]+]] = load i128, ptr %incdec.ptr2, align 16 +// CHECK-64: [[ORG:%[0-9]+]] = load i128, ptr %incdec.ptr2, align 8 // CHECK-64: [[RES:%[0-9]+]] = cmpxchg volatile ptr %incdec.ptr, i128 [[ORG]], i128 [[EXP]] seq_cst seq_cst, align 16 // CHECK-64: [[OLD:%[0-9]+]] = extractvalue { i128, i1 } [[RES]], 0 -// CHECK-64: store i128 [[OLD]], ptr %incdec.ptr2, align 16 +// CHECK-64: store i128 [[OLD]], ptr %incdec.ptr2, align 8 // CHECK-64: [[SUC1:%[0-9]+]] = extractvalue { i128, i1 } [[RES]], 1 // CHECK-64: [[SUC8:%[0-9]+]] = zext i1 [[SUC1]] to i8 // CHECK-64: ret i8 [[SUC8]] diff --git a/clang/test/CodeGenCXX/RelativeVTablesABI/member-function-pointer.cpp b/clang/test/CodeGenCXX/RelativeVTablesABI/member-function-pointer.cpp index 24f884a8d23b..000568b3b6bf 100644 --- a/clang/test/CodeGenCXX/RelativeVTablesABI/member-function-pointer.cpp +++ b/clang/test/CodeGenCXX/RelativeVTablesABI/member-function-pointer.cpp @@ -14,7 +14,7 @@ // The loading of the virtual function here should be replaced with a llvm.load.relative() call. // CHECK-NEXT: [[vtable:%.+]] = load ptr, ptr [[this_adj]], align 8 -// CHECK-NEXT: [[offset:%.+]] = add i64 [[fn_ptr]], -1 +// CHECK-NEXT: [[offset:%.+]] = add nsw i64 [[fn_ptr]], -1 // CHECK-NEXT: [[ptr:%.+]] = tail call ptr @llvm.load.relative.i64(ptr [[vtable]], i64 [[offset]]) // CHECK-NEXT: br label %[[memptr_end:.+]] // CHECK: [[nonvirt]]: diff --git a/clang/test/CodeGenCXX/attr-target-clones.cpp b/clang/test/CodeGenCXX/attr-target-clones.cpp index 86293b98dbbd..fd2d38062a71 100644 --- a/clang/test/CodeGenCXX/attr-target-clones.cpp +++ b/clang/test/CodeGenCXX/attr-target-clones.cpp @@ -1,13 +1,20 @@ // RUN: %clang_cc1 -std=c++11 -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=LINUX // RUN: %clang_cc1 -std=c++11 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s --check-prefix=WINDOWS +// Aliases for ifuncs +// LINUX: @_Z10overloadedi.ifunc = weak_odr alias i32 (i32), ptr @_Z10overloadedi +// LINUX: @_Z10overloadedPKc.ifunc = weak_odr alias i32 (ptr), ptr @_Z10overloadedPKc +// LINUX: @_ZN1CIssE3fooEv.ifunc = weak_odr alias i32 (ptr), ptr @_ZN1CIssE3fooEv +// LINUX: @_ZN1CIisE3fooEv.ifunc = weak_odr alias i32 (ptr), ptr @_ZN1CIisE3fooEv +// LINUX: @_ZN1CIdfE3fooEv.ifunc = weak_odr alias i32 (ptr), ptr @_ZN1CIdfE3fooEv + // Overloaded ifuncs -// LINUX: @_Z10overloadedi.ifunc = weak_odr ifunc i32 (i32), ptr @_Z10overloadedi.resolver -// LINUX: @_Z10overloadedPKc.ifunc = weak_odr ifunc i32 (ptr), ptr @_Z10overloadedPKc.resolver +// LINUX: @_Z10overloadedi = weak_odr ifunc i32 (i32), ptr @_Z10overloadedi.resolver +// LINUX: @_Z10overloadedPKc = weak_odr ifunc i32 (ptr), ptr @_Z10overloadedPKc.resolver // struct 'C' ifuncs, note the 'float, U' one doesn't get one. -// LINUX: @_ZN1CIssE3fooEv.ifunc = weak_odr ifunc i32 (ptr), ptr @_ZN1CIssE3fooEv.resolver -// LINUX: @_ZN1CIisE3fooEv.ifunc = weak_odr ifunc i32 (ptr), ptr @_ZN1CIisE3fooEv.resolver -// LINUX: @_ZN1CIdfE3fooEv.ifunc = weak_odr ifunc i32 (ptr), ptr @_ZN1CIdfE3fooEv.resolver +// LINUX: @_ZN1CIssE3fooEv = weak_odr ifunc i32 (ptr), ptr @_ZN1CIssE3fooEv.resolver +// LINUX: @_ZN1CIisE3fooEv = weak_odr ifunc i32 (ptr), ptr @_ZN1CIisE3fooEv.resolver +// LINUX: @_ZN1CIdfE3fooEv = weak_odr ifunc i32 (ptr), ptr @_ZN1CIdfE3fooEv.resolver int __attribute__((target_clones("sse4.2", "default"))) overloaded(int) { return 1; } // LINUX: define {{.*}}i32 @_Z10overloadedi.sse4.2.0(i32{{.+}}) @@ -37,10 +44,10 @@ int __attribute__((target_clones("arch=ivybridge", "default"))) overloaded(const void use_overloaded() { overloaded(1); - // LINUX: call noundef i32 @_Z10overloadedi.ifunc + // LINUX: call noundef i32 @_Z10overloadedi // WINDOWS: call noundef i32 @"?overloaded@@YAHH@Z" overloaded(nullptr); - // LINUX: call noundef i32 @_Z10overloadedPKc.ifunc + // LINUX: call noundef i32 @_Z10overloadedPKc // WINDOWS: call noundef i32 @"?overloaded@@YAHPEBD@Z" } @@ -64,11 +71,11 @@ int __attribute__((target_clones("sse4.2", "default"))) foo(){ return 3;} void uses_specialized() { C c; c.foo(); - // LINUX: call noundef i32 @_ZN1CIssE3fooEv.ifunc(ptr + // LINUX: call noundef i32 @_ZN1CIssE3fooEv(ptr // WINDOWS: call noundef i32 @"?foo@?$C@FF@@QEAAHXZ"(ptr C c2; c2.foo(); - // LINUX: call noundef i32 @_ZN1CIisE3fooEv.ifunc(ptr + // LINUX: call noundef i32 @_ZN1CIisE3fooEv(ptr // WINDOWS: call noundef i32 @"?foo@?$C@HF@@QEAAHXZ"(ptr C c3; c3.foo(); @@ -77,7 +84,7 @@ void uses_specialized() { // WINDOWS: call noundef i32 @"?foo@?$C@MF@@QEAAHXZ"(ptr C c4; c4.foo(); - // LINUX: call noundef i32 @_ZN1CIdfE3fooEv.ifunc(ptr + // LINUX: call noundef i32 @_ZN1CIdfE3fooEv(ptr // WINDOWS: call noundef i32 @"?foo@?$C@NM@@QEAAHXZ"(ptr } diff --git a/clang/test/CodeGenCXX/debug-info-class.cpp b/clang/test/CodeGenCXX/debug-info-class.cpp index a3111cd7c364..8d610ca68a9d 100644 --- a/clang/test/CodeGenCXX/debug-info-class.cpp +++ b/clang/test/CodeGenCXX/debug-info-class.cpp @@ -117,18 +117,11 @@ int main(int argc, char **argv) { // CHECK-NOT: identifier: // CHECK-SAME: ){{$}} -// CHECK: !DIGlobalVariableExpression(var: ![[HDR_VAR:[0-9]+]], expr: !DIExpression(DW_OP_constu, 52, DW_OP_stack_value)) -// CHECK: ![[HDR_VAR]] = distinct !DIGlobalVariable(name: "HdrSize", -// CHECK-SAME: isLocal: true, isDefinition: true, declaration: ![[HDR_VAR_DECL:[0-9]+]]) -// CHECK: ![[INT:[0-9]+]] = !DIBasicType(name: "int" -// CHECK: ![[HDR_VAR_DECL]] = !DIDerivedType(tag: DW_TAG_member, name: "HdrSize" - -// CHECK: !DICompositeType(tag: DW_TAG_structure_type, name: "A" - // CHECK: !DICompositeType(tag: DW_TAG_structure_type, name: "I" // CHECK-NOT: DIFlagFwdDecl // CHECK-SAME: ){{$}} +// CHECK: ![[INT:[0-9]+]] = !DIBasicType(name: "int" // CHECK: !DICompositeType(tag: DW_TAG_structure_type, name: "foo" // CHECK: !DICompositeType(tag: DW_TAG_class_type, name: "bar" // CHECK: !DICompositeType(tag: DW_TAG_union_type, name: "baz" @@ -194,5 +187,8 @@ int main(int argc, char **argv) { // CHECK: [[G_INNER_I]] = !DIDerivedType(tag: DW_TAG_member, name: "j" // CHECK-SAME: baseType: ![[INT]] +// CHECK: !DICompositeType(tag: DW_TAG_structure_type, name: "A" +// CHECK: !DIDerivedType(tag: DW_TAG_member, name: "HdrSize" + // CHECK: ![[EXCEPTLOC]] = !DILocation(line: 100, // CHECK: ![[RETLOC]] = !DILocation(line: 99, diff --git a/clang/test/CodeGenCXX/debug-info-static-inline-member.cpp b/clang/test/CodeGenCXX/debug-info-static-inline-member.cpp deleted file mode 100644 index 3230b0e0c9c6..000000000000 --- a/clang/test/CodeGenCXX/debug-info-static-inline-member.cpp +++ /dev/null @@ -1,104 +0,0 @@ -// RUN: %clangxx -target arm64-apple-macosx11.0.0 -g -gdwarf-4 -debug-info-kind=standalone %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK %s -// RUN: %clangxx -target arm64-apple-macosx11.0.0 -g -gdwarf-4 -debug-info-kind=limited %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK %s - -enum class Enum : int { - VAL = -1 -}; - -struct Empty {}; -struct Fwd; - -constexpr auto func() { return 25; } - -struct Foo { - static constexpr int cexpr_int_with_addr = func(); - static constexpr int cexpr_int2 = func() + 1; - static constexpr float cexpr_float = 2.0 + 1.0; - static constexpr Enum cexpr_enum = Enum::VAL; - static constexpr Empty cexpr_struct_with_addr{}; - - template - static constexpr auto cexpr_template = V; - - static const auto empty_templated = cexpr_template; -}; - -int main() { - Foo f; - //Bar b; - - // Force global variable definitions to be emitted. - (void)&Foo::cexpr_int_with_addr; - (void)&Foo::cexpr_struct_with_addr; - - return Foo::cexpr_int_with_addr + Foo::cexpr_float - + (int)Foo::cexpr_enum + Foo::cexpr_template - + Foo::empty_templated; -} - -// CHECK: @{{.*}}cexpr_int_with_addr{{.*}} = -// CHECK-SAME: !dbg ![[INT_GLOBAL:[0-9]+]] - -// CHECK: @{{.*}}cexpr_struct_with_addr{{.*}} = -// CHECK-SAME !dbg ![[EMPTY_GLOBAL:[0-9]+]] - -// CHECK: !DIGlobalVariableExpression(var: ![[INT_VAR:[0-9]+]], expr: !DIExpression()) -// CHECK: ![[INT_VAR]] = distinct !DIGlobalVariable(name: "cexpr_int_with_addr", linkageName: -// CHECK-SAME: isLocal: false, isDefinition: true, declaration: ![[INT_DECL:[0-9]+]]) - -// CHECK: ![[INT_DECL]] = !DIDerivedType(tag: DW_TAG_member, name: "cexpr_int_with_addr", -// CHECK-SAME: flags: DIFlagStaticMember -// CHECK-SAME: extraData: i32 25 - -// CHECK: ![[INT_DECL2:[0-9]+]] = !DIDerivedType(tag: DW_TAG_member, name: "cexpr_int2", -// CHECK-SAME: flags: DIFlagStaticMember -// CHECK-SAME: extraData: i32 26 - -// CHECK: ![[FLOAT_DECL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_member, name: "cexpr_float", -// CHECK-SAME: flags: DIFlagStaticMember -// CHECK-SAME: extraData: float - -// CHECK: ![[ENUM_DECL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_member, name: "cexpr_enum", -// CHECK-SAME: flags: DIFlagStaticMember -// CHECK-SAME: extraData: i32 -1 - -// CHECK: ![[EMPTY_DECL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_member, name: "cexpr_struct_with_addr", -// CHECK-SAME: flags: DIFlagStaticMember -// CHECK-NOT: extraData: - -// CHECK: ![[EMPTY_TEMPLATED_DECL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_member, name: "empty_templated", -// CHECK-SAME: flags: DIFlagStaticMember -// CHECK-SAME: extraData: i32 1 - -// CHECK: ![[TEMPLATE_DECL:[0-9]+]] = !DIDerivedType(tag: DW_TAG_member, name: "cexpr_template", -// CHECK-SAME: flags: DIFlagStaticMember -// CHECK-SAME: extraData: i32 1 - -// CHECK: !DIGlobalVariableExpression(var: ![[EMPTY_VAR:[0-9]+]], expr: !DIExpression()) -// CHECK: ![[EMPTY_VAR]] = distinct !DIGlobalVariable(name: "cexpr_struct_with_addr", linkageName: -// CHECK-SAME: isLocal: false, isDefinition: true, declaration: ![[EMPTY_DECL]]) - -// CHECK: !DIGlobalVariableExpression(var: ![[INT_VAR2:[0-9]+]], expr: !DIExpression(DW_OP_constu, 26, DW_OP_stack_value)) -// CHECK: ![[INT_VAR2]] = distinct !DIGlobalVariable(name: "cexpr_int2" -// CHECK-NOT: linkageName: -// CHECK-SAME: isLocal: true, isDefinition: true, declaration: ![[INT_DECL2]]) - -// CHECK: !DIGlobalVariableExpression(var: ![[FLOAT_VAR:[0-9]+]], expr: !DIExpression(DW_OP_constu, {{.*}}, DW_OP_stack_value)) -// CHECK: ![[FLOAT_VAR]] = distinct !DIGlobalVariable(name: "cexpr_float" -// CHECK-NOT: linkageName: -// CHECK-SAME: isLocal: true, isDefinition: true, declaration: ![[FLOAT_DECL]]) - -// CHECK: !DIGlobalVariableExpression(var: ![[ENUM_VAR:[0-9]+]], expr: !DIExpression(DW_OP_constu, {{.*}}, DW_OP_stack_value)) -// CHECK: ![[ENUM_VAR]] = distinct !DIGlobalVariable(name: "cexpr_enum" -// CHECK-NOT: linkageName: -// CHECK-SAME: isLocal: true, isDefinition: true, declaration: ![[ENUM_DECL]]) - -// CHECK: !DIGlobalVariableExpression(var: ![[EMPTY_TEMPLATED_VAR:[0-9]+]], expr: !DIExpression(DW_OP_constu, 1, DW_OP_stack_value)) -// CHECK: ![[EMPTY_TEMPLATED_VAR]] = distinct !DIGlobalVariable(name: "empty_templated" -// CHECK-NOT: linkageName: -// CHECK-SAME: isLocal: true, isDefinition: true, declaration: ![[EMPTY_TEMPLATED_DECL]]) - -// CHECK: !DIGlobalVariableExpression(var: ![[TEMPLATE_VAR:[0-9]+]], expr: !DIExpression(DW_OP_constu, 5, DW_OP_stack_value)) -// CHECK: ![[TEMPLATE_VAR]] = distinct !DIGlobalVariable(name: "cexpr_template" -// CHECK-NOT: linkageName: -// CHECK-SAME: isLocal: true, isDefinition: true, declaration: ![[TEMPLATE_DECL]], templateParams: ![[TEMPLATE_PARMS_2:[0-9]+]]) diff --git a/clang/test/CodeGenCXX/debug-info-static-member.cpp b/clang/test/CodeGenCXX/debug-info-static-member.cpp index a111dc84b6e6..972ca62d7b26 100644 --- a/clang/test/CodeGenCXX/debug-info-static-member.cpp +++ b/clang/test/CodeGenCXX/debug-info-static-member.cpp @@ -1,8 +1,8 @@ -// RUN: %clangxx -target x86_64-unknown-unknown -g -gdwarf-4 %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK,DWARF4,CPP11,NOT-MS %s +// RUN: %clangxx -target x86_64-unknown-unknown -g -gdwarf-4 %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK,DWARF4,NOT-MS %s // RUN: %clangxx -target x86_64-unknown-unknown -g -gdwarf-4 -std=c++98 %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK,DWARF4,NOT-MS %s -// RUN: %clangxx -target x86_64-unknown-unknown -g -gdwarf-4 -std=c++11 %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK,DWARF4,CPP11,NOT-MS %s -// RUN: %clangxx -target x86_64-unknown-unknown -g -gdwarf-5 -std=c++11 %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK,DWARF5,CPP11 %s -// RUN: %clangxx -target x86_64-windows-msvc -g -gdwarf-4 %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK,DWARF4,CPP11 %s +// RUN: %clangxx -target x86_64-unknown-unknown -g -gdwarf-4 -std=c++11 %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK,DWARF4,NOT-MS %s +// RUN: %clangxx -target x86_64-unknown-unknown -g -gdwarf-5 -std=c++11 %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK,DWARF5 %s +// RUN: %clangxx -target x86_64-windows-msvc -g -gdwarf-4 %s -emit-llvm -S -o - | FileCheck --check-prefixes=CHECK,DWARF4 %s // PR14471 // CHECK: @{{.*}}a{{.*}} = dso_local global i32 4, align 4, !dbg [[A:![0-9]+]] @@ -166,15 +166,3 @@ struct y { }; int y::z; } - -// CHECK: !DIGlobalVariableExpression(var: ![[CONST_A_VAR:[0-9]+]], expr: !DIExpression(DW_OP_constu, 1, DW_OP_stack_value)) -// CHECK: ![[CONST_A_VAR]] = distinct !DIGlobalVariable(name: "const_a" -// CHECK-SAME: isLocal: true, isDefinition: true, declaration: ![[CONST_A_DECL]]) - -// CPP11: !DIGlobalVariableExpression(var: ![[CONST_B_VAR:[0-9]+]], expr: !DIExpression(DW_OP_constu, {{.*}}, DW_OP_stack_value)) -// CPP11: ![[CONST_B_VAR]] = distinct !DIGlobalVariable(name: "const_b" -// CPP11-SAME: isLocal: true, isDefinition: true, declaration: ![[CONST_B_DECL]]) - -// CHECK: !DIGlobalVariableExpression(var: ![[CONST_C_VAR:[0-9]+]], expr: !DIExpression(DW_OP_constu, 18, DW_OP_stack_value)) -// CHECK: ![[CONST_C_VAR]] = distinct !DIGlobalVariable(name: "const_c" -// CHECK-SAME: isLocal: true, isDefinition: true, declaration: ![[CONST_C_DECL]]) diff --git a/clang/test/Driver/aarch64-thread-pointer.c b/clang/test/Driver/aarch64-thread-pointer.c index 6a5d4ba0852e..b1c6df4ac5e5 100644 --- a/clang/test/Driver/aarch64-thread-pointer.c +++ b/clang/test/Driver/aarch64-thread-pointer.c @@ -1,45 +1,45 @@ // Test of the AArch64 values of -mtp=, checking that each one maps to // the right target features. -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL0 %s -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a -mtp=el0 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s -mtp=el0 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL0 %s -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a -mtp=tpidr_el0 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s -mtp=tpidr_el0 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL0 %s // ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidrro-el0" // ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidr-el1" // ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidr-el2" // ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidr-el3" -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a -mtp=tpidrro_el0 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s -mtp=tpidrro_el0 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_ROEL0 %s // ARMv8_THREAD_POINTER_ROEL0: "-target-feature" "+tpidrro-el0" // ARMv8_THREAD_POINTER_ROEL0-NOT: "-target-feature" "+tpidr-el1" // ARMv8_THREAD_POINTER_ROEL0-NOT: "-target-feature" "+tpidr-el2" // ARMv8_THREAD_POINTER_ROEL0-NOT: "-target-feature" "+tpidr-el3" -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a -mtp=el1 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s -mtp=el1 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL1 %s -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a -mtp=tpidr_el1 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s -mtp=tpidr_el1 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL1 %s // ARMv8_THREAD_POINTER_EL1-NOT: "-target-feature" "+tpidrro-el0" // ARMv8_THREAD_POINTER_EL1: "-target-feature" "+tpidr-el1" // ARMv8_THREAD_POINTER_EL1-NOT: "-target-feature" "+tpidr-el2" // ARMv8_THREAD_POINTER_EL1-NOT: "-target-feature" "+tpidr-el3" -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a -mtp=el2 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s -mtp=el2 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL2 %s -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a -mtp=tpidr_el2 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s -mtp=tpidr_el2 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL2 %s // ARMv8_THREAD_POINTER_EL2-NOT: "-target-feature" "+tpidrro-el0" // ARMv8_THREAD_POINTER_EL2-NOT: "-target-feature" "+tpidr-el1" // ARMv8_THREAD_POINTER_EL2: "-target-feature" "+tpidr-el2" // ARMv8_THREAD_POINTER_EL2-NOT: "-target-feature" "+tpidr-el3" -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a -mtp=el3 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s -mtp=el3 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL3 %s -// RUN: %clang --target=aarch64-linux -### -S %s -arch armv8a -mtp=tpidr_el3 2>&1 | \ +// RUN: %clang --target=aarch64-linux -### -S %s -mtp=tpidr_el3 2>&1 | \ // RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL3 %s // ARMv8_THREAD_POINTER_EL3-NOT: "-target-feature" "+tpidrro-el0" // ARMv8_THREAD_POINTER_EL3-NOT: "-target-feature" "+tpidr-el1" diff --git a/clang/test/Driver/arc-exceptions.m b/clang/test/Driver/arc-exceptions.m index 4501ccd07382..c1dd02d59988 100644 --- a/clang/test/Driver/arc-exceptions.m +++ b/clang/test/Driver/arc-exceptions.m @@ -1,5 +1,5 @@ -// RUN: %clang -### -x objective-c -arch x86_64 -fobjc-arc -fsyntax-only %s 2> %t.log +// RUN: %clang -### -x objective-c --target=x86_64-apple-macos10.6 -fobjc-arc -fsyntax-only %s 2> %t.log // RUN: grep objective-c %t.log // RUN: not grep "fobjc-arc-exceptions" %t.log -// RUN: %clang -### -x objective-c++ -arch x86_64 -fobjc-arc -fsyntax-only %s 2> %t.log +// RUN: %clang -### -x objective-c++ --target=x86_64-apple-macos10.6 -fobjc-arc -fsyntax-only %s 2> %t.log // RUN: grep "fobjc-arc-exceptions" %t.log diff --git a/clang/test/Driver/arm-arch-darwin.c b/clang/test/Driver/arm-arch-darwin.c index 55089619d1e7..f6d3f88a3f8d 100644 --- a/clang/test/Driver/arm-arch-darwin.c +++ b/clang/test/Driver/arm-arch-darwin.c @@ -1,6 +1,10 @@ // On Darwin, arch should override CPU for triple purposes // RUN: %clang -target armv7m-apple-darwin -arch armv7m -mcpu=cortex-m4 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V7M-DARWIN %s // CHECK-V7M-DARWIN: "-cc1"{{.*}} "-triple" "thumbv7m-{{.*}} "-target-cpu" "cortex-m4" -// RUN: %clang -target armv7m -arch armv7m -mcpu=cortex-m4 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V7M-OVERRIDDEN %s -// CHECK-V7M-OVERRIDDEN: "-cc1"{{.*}} "-triple" "thumbv7em-{{.*}} "-target-cpu" "cortex-m4" +/// -arch is unsupported for non-Darwin targets. +// RUN: not %clang --target=armv7m -arch armv7m -mcpu=cortex-m4 -### -c %s 2>&1 | FileCheck -check-prefix=ERR %s +// ERR: unsupported option '-arch' for target 'armv7m' + +// RUN: not %clang --target=aarch64-linux-gnu -arch arm64 -### -c %s 2>&1 | FileCheck -check-prefix=ERR2 %s +// ERR2: unsupported option '-arch' for target 'aarch64-linux-gnu' diff --git a/clang/test/Frontend/darwin-eabi.c b/clang/test/Frontend/darwin-eabi.c index 27471e6cfb0e..9d62632891cb 100644 --- a/clang/test/Frontend/darwin-eabi.c +++ b/clang/test/Frontend/darwin-eabi.c @@ -1,6 +1,6 @@ -// RUN: %clang -arch armv6m -dM -E %s | FileCheck %s -// RUN: %clang -arch armv7m -dM -E %s | FileCheck %s -// RUN: %clang -arch armv7em -dM -E %s | FileCheck %s +// RUN: %clang --target=armv6m-apple-darwin -dM -E %s | FileCheck %s +// RUN: %clang --target=armv7m-apple-darwin -dM -E %s | FileCheck %s +// RUN: %clang --target=armv7em-apple-darwin -dM -E %s | FileCheck %s // RUN: %clang_cc1 -triple thumbv7m-apple-unknown-macho -dM -E %s | FileCheck %s // CHECK-NOT: __ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__ diff --git a/clang/test/Frontend/sarif-diagnostics.cpp b/clang/test/Frontend/sarif-diagnostics.cpp index 9a4e686389a2..767c5802ca13 100644 --- a/clang/test/Frontend/sarif-diagnostics.cpp +++ b/clang/test/Frontend/sarif-diagnostics.cpp @@ -64,5 +64,5 @@ void f1(t1 x, t1 y) { // CHECK: {"enabled":true,"level":"error","rank":50},"fullDescription":{"text":""},"id":"{{[0-9]+}}","name":""},{"defaultConfiguration": // CHECK: {"enabled":true,"level":"error","rank":50},"fullDescription":{"text":""},"id":"{{[0-9]+}}","name":""},{"defaultConfiguration": // CHECK: {"enabled":true,"level":"error","rank":50},"fullDescription": -// CHECK: {"text":""},"id":"{{[0-9]+}}","name":""}],"version":"{{[0-9]+\.[0-9]+\.[0-9]+}}"}}}],"version":"2.1.0"} -// CHECK: 2 warnings and 6 errors generated. \ No newline at end of file +// CHECK: {"text":""},"id":"{{[0-9]+}}","name":""}],"version":"{{[0-9]+\.[0-9]+\.[0-9]+[^" ]*}}"}}}],"version":"2.1.0"} +// CHECK: 2 warnings and 6 errors generated. diff --git a/clang/test/Headers/__clang_hip_math.hip b/clang/test/Headers/__clang_hip_math.hip index 68cbf86041e3..fa13ddba425b 100644 --- a/clang/test/Headers/__clang_hip_math.hip +++ b/clang/test/Headers/__clang_hip_math.hip @@ -43,7 +43,7 @@ typedef unsigned long long uint64_t; // CHECK-NEXT: br i1 [[OR_COND_I]], label [[IF_THEN_I:%.*]], label [[CLEANUP_I]] // CHECK: if.then.i: // CHECK-NEXT: [[MUL_I:%.*]] = shl i64 [[__R_0_I]], 3 -// CHECK-NEXT: [[CONV5_I:%.*]] = sext i8 [[TMP0]] to i64 +// CHECK-NEXT: [[CONV5_I:%.*]] = zext nneg i8 [[TMP0]] to i64 // CHECK-NEXT: [[ADD_I:%.*]] = add i64 [[MUL_I]], -48 // CHECK-NEXT: [[SUB_I:%.*]] = add i64 [[ADD_I]], [[CONV5_I]] // CHECK-NEXT: [[INCDEC_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I]], i64 1 @@ -75,7 +75,7 @@ extern "C" __device__ uint64_t test___make_mantissa_base8(const char *p) { // CHECK-NEXT: br i1 [[OR_COND_I]], label [[IF_THEN_I:%.*]], label [[CLEANUP_I]] // CHECK: if.then.i: // CHECK-NEXT: [[MUL_I:%.*]] = mul i64 [[__R_0_I]], 10 -// CHECK-NEXT: [[CONV5_I:%.*]] = sext i8 [[TMP0]] to i64 +// CHECK-NEXT: [[CONV5_I:%.*]] = zext nneg i8 [[TMP0]] to i64 // CHECK-NEXT: [[ADD_I:%.*]] = add i64 [[MUL_I]], -48 // CHECK-NEXT: [[SUB_I:%.*]] = add i64 [[ADD_I]], [[CONV5_I]] // CHECK-NEXT: [[INCDEC_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I]], i64 1 @@ -116,7 +116,7 @@ extern "C" __device__ uint64_t test___make_mantissa_base10(const char *p) { // CHECK: if.end31.i: // CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I]] ], [ -87, [[IF_ELSE_I]] ], [ -55, [[IF_ELSE17_I]] ] // CHECK-NEXT: [[MUL24_I:%.*]] = shl i64 [[__R_0_I]], 4 -// CHECK-NEXT: [[CONV25_I:%.*]] = sext i8 [[TMP0]] to i64 +// CHECK-NEXT: [[CONV25_I:%.*]] = zext nneg i8 [[TMP0]] to i64 // CHECK-NEXT: [[ADD26_I:%.*]] = add i64 [[MUL24_I]], [[DOTSINK]] // CHECK-NEXT: [[ADD28_I:%.*]] = add i64 [[ADD26_I]], [[CONV25_I]] // CHECK-NEXT: [[INCDEC_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I]], i64 1 @@ -169,7 +169,7 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // CHECK: if.end31.i.i: // CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I34_I]] ], [ -87, [[IF_ELSE_I_I]] ], [ -55, [[IF_ELSE17_I_I]] ] // CHECK-NEXT: [[MUL24_I_I:%.*]] = shl i64 [[__R_0_I32_I]], 4 -// CHECK-NEXT: [[CONV25_I_I:%.*]] = sext i8 [[TMP2]] to i64 +// CHECK-NEXT: [[CONV25_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 // CHECK-NEXT: [[ADD26_I_I:%.*]] = add i64 [[MUL24_I_I]], [[DOTSINK]] // CHECK-NEXT: [[ADD28_I_I:%.*]] = add i64 [[ADD26_I_I]], [[CONV25_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I40_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I]], i64 1 @@ -191,7 +191,7 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // CHECK-NEXT: br i1 [[OR_COND_I_I]], label [[IF_THEN_I_I:%.*]], label [[CLEANUP_I_I]] // CHECK: if.then.i.i: // CHECK-NEXT: [[MUL_I_I:%.*]] = shl i64 [[__R_0_I_I]], 3 -// CHECK-NEXT: [[CONV5_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[CONV5_I_I:%.*]] = zext nneg i8 [[TMP6]] to i64 // CHECK-NEXT: [[ADD_I_I:%.*]] = add i64 [[MUL_I_I]], -48 // CHECK-NEXT: [[SUB_I_I:%.*]] = add i64 [[ADD_I_I]], [[CONV5_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I_I]], i64 1 @@ -212,7 +212,7 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // CHECK-NEXT: br i1 [[OR_COND_I19_I]], label [[IF_THEN_I24_I:%.*]], label [[CLEANUP_I20_I]] // CHECK: if.then.i24.i: // CHECK-NEXT: [[MUL_I25_I:%.*]] = mul i64 [[__R_0_I16_I]], 10 -// CHECK-NEXT: [[CONV5_I26_I:%.*]] = sext i8 [[TMP8]] to i64 +// CHECK-NEXT: [[CONV5_I26_I:%.*]] = zext nneg i8 [[TMP8]] to i64 // CHECK-NEXT: [[ADD_I27_I:%.*]] = add i64 [[MUL_I25_I]], -48 // CHECK-NEXT: [[SUB_I28_I:%.*]] = add i64 [[ADD_I27_I]], [[CONV5_I26_I]] // CHECK-NEXT: [[INCDEC_PTR_I29_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I15_I]], i64 1 @@ -2395,7 +2395,7 @@ extern "C" __device__ double test_modf(double x, double* y) { // CHECK: if.end31.i.i.i: // CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I34_I_I]] ], [ -87, [[IF_ELSE_I_I_I]] ], [ -55, [[IF_ELSE17_I_I_I]] ] // CHECK-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I32_I_I]], 4 -// CHECK-NEXT: [[CONV25_I_I_I:%.*]] = sext i8 [[TMP2]] to i64 +// CHECK-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 // CHECK-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] // CHECK-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I40_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1 @@ -2417,7 +2417,7 @@ extern "C" __device__ double test_modf(double x, double* y) { // CHECK-NEXT: br i1 [[OR_COND_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[CLEANUP_I_I_I]] // CHECK: if.then.i.i.i: // CHECK-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3 -// CHECK-NEXT: [[CONV5_I_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP6]] to i64 // CHECK-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 // CHECK-NEXT: [[SUB_I_I_I:%.*]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I_I_I]], i64 1 @@ -2438,7 +2438,7 @@ extern "C" __device__ double test_modf(double x, double* y) { // CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[IF_THEN_I24_I_I:%.*]], label [[CLEANUP_I20_I_I]] // CHECK: if.then.i24.i.i: // CHECK-NEXT: [[MUL_I25_I_I:%.*]] = mul i64 [[__R_0_I16_I_I]], 10 -// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = sext i8 [[TMP8]] to i64 +// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = zext nneg i8 [[TMP8]] to i64 // CHECK-NEXT: [[ADD_I27_I_I:%.*]] = add i64 [[MUL_I25_I_I]], -48 // CHECK-NEXT: [[SUB_I28_I_I:%.*]] = add i64 [[ADD_I27_I_I]], [[CONV5_I26_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I29_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I15_I_I]], i64 1 @@ -2494,7 +2494,7 @@ extern "C" __device__ float test_nanf(const char *tag) { // CHECK: if.end31.i.i.i: // CHECK-NEXT: [[DOTSINK:%.*]] = phi i64 [ -48, [[WHILE_BODY_I34_I_I]] ], [ -87, [[IF_ELSE_I_I_I]] ], [ -55, [[IF_ELSE17_I_I_I]] ] // CHECK-NEXT: [[MUL24_I_I_I:%.*]] = shl i64 [[__R_0_I32_I_I]], 4 -// CHECK-NEXT: [[CONV25_I_I_I:%.*]] = sext i8 [[TMP2]] to i64 +// CHECK-NEXT: [[CONV25_I_I_I:%.*]] = zext nneg i8 [[TMP2]] to i64 // CHECK-NEXT: [[ADD26_I_I_I:%.*]] = add i64 [[MUL24_I_I_I]], [[DOTSINK]] // CHECK-NEXT: [[ADD28_I_I_I:%.*]] = add i64 [[ADD26_I_I_I]], [[CONV25_I_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I40_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1 @@ -2516,7 +2516,7 @@ extern "C" __device__ float test_nanf(const char *tag) { // CHECK-NEXT: br i1 [[OR_COND_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[CLEANUP_I_I_I]] // CHECK: if.then.i.i.i: // CHECK-NEXT: [[MUL_I_I_I:%.*]] = shl i64 [[__R_0_I_I_I]], 3 -// CHECK-NEXT: [[CONV5_I_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[CONV5_I_I_I:%.*]] = zext nneg i8 [[TMP6]] to i64 // CHECK-NEXT: [[ADD_I_I_I:%.*]] = add i64 [[MUL_I_I_I]], -48 // CHECK-NEXT: [[SUB_I_I_I:%.*]] = add i64 [[ADD_I_I_I]], [[CONV5_I_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I_I_I]], i64 1 @@ -2537,7 +2537,7 @@ extern "C" __device__ float test_nanf(const char *tag) { // CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[IF_THEN_I24_I_I:%.*]], label [[CLEANUP_I20_I_I]] // CHECK: if.then.i24.i.i: // CHECK-NEXT: [[MUL_I25_I_I:%.*]] = mul i64 [[__R_0_I16_I_I]], 10 -// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = sext i8 [[TMP8]] to i64 +// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = zext nneg i8 [[TMP8]] to i64 // CHECK-NEXT: [[ADD_I27_I_I:%.*]] = add i64 [[MUL_I25_I_I]], -48 // CHECK-NEXT: [[SUB_I28_I_I:%.*]] = add i64 [[ADD_I27_I_I]], [[CONV5_I26_I_I]] // CHECK-NEXT: [[INCDEC_PTR_I29_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I15_I_I]], i64 1 diff --git a/clang/test/Headers/arm-neon-header.c b/clang/test/Headers/arm-neon-header.c index 7e98d03dfc19..89bd5aaa2542 100644 --- a/clang/test/Headers/arm-neon-header.c +++ b/clang/test/Headers/arm-neon-header.c @@ -22,7 +22,7 @@ // RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-none-elf -march=armv8.2-a+fp16fml+crypto+dotprod -std=c11 -xc --sysroot=%S/Inputs -flax-vector-conversions=none %s // RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64_be-none-elf -march=armv8.2-a+fp16fml+crypto+dotprod -std=c11 -xc --sysroot=%S/Inputs -flax-vector-conversions=none %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=arm64-linux-gnu -arch +neon -std=c11 -xc --sysroot=%S/Inputs -flax-vector-conversions=none %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=arm64-linux-gnu -std=c11 -xc --sysroot=%S/Inputs -flax-vector-conversions=none %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test index dd91f4f88ad6..707fc8875089 100644 --- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test +++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test @@ -23,6 +23,7 @@ // CHECK-NEXT: Availability ((SubjectMatchRule_record, SubjectMatchRule_enum, SubjectMatchRule_enum_constant, SubjectMatchRule_field, SubjectMatchRule_function, SubjectMatchRule_namespace, SubjectMatchRule_objc_category, SubjectMatchRule_objc_implementation, SubjectMatchRule_objc_interface, SubjectMatchRule_objc_method, SubjectMatchRule_objc_property, SubjectMatchRule_objc_protocol, SubjectMatchRule_record, SubjectMatchRule_type_alias, SubjectMatchRule_variable)) // CHECK-NEXT: AvailableOnlyInDefaultEvalMethod (SubjectMatchRule_type_alias) // CHECK-NEXT: BPFPreserveAccessIndex (SubjectMatchRule_record) +// CHECK-NEXT: BPFPreserveStaticOffset (SubjectMatchRule_record) // CHECK-NEXT: BTFDeclTag (SubjectMatchRule_variable, SubjectMatchRule_function, SubjectMatchRule_record, SubjectMatchRule_field, SubjectMatchRule_type_alias) // CHECK-NEXT: BuiltinAlias (SubjectMatchRule_function) // CHECK-NEXT: CFAuditedTransfer (SubjectMatchRule_function) diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp index 6bbde2f72870..4ebcfa73d1bd 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp @@ -903,7 +903,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK9-SAME: () #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1303,7 +1303,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) // CHECK9-NEXT: ret void @@ -1643,7 +1643,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK11-SAME: () #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -2037,7 +2037,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) // CHECK11-NEXT: ret void @@ -2059,13 +2059,13 @@ int main() { // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK13-NEXT: store ptr [[G]], ptr [[G1]], align 8 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -2126,14 +2126,14 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -2145,11 +2145,11 @@ int main() { // CHECK13: arraydestroy.body13: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13: arraydestroy.done17: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP11]] // @@ -2183,12 +2183,12 @@ int main() { // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK13-SAME: () #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -2201,12 +2201,12 @@ int main() { // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) @@ -2265,14 +2265,14 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -2283,11 +2283,11 @@ int main() { // CHECK13: arraydestroy.body13: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13: arraydestroy.done17: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP11]] // @@ -2355,7 +2355,7 @@ int main() { // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2409,13 +2409,13 @@ int main() { // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store ptr [[G]], ptr [[G1]], align 4 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -2474,14 +2474,14 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -2493,11 +2493,11 @@ int main() { // CHECK15: arraydestroy.body12: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK15: arraydestroy.done16: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP11]] // @@ -2531,12 +2531,12 @@ int main() { // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK15-SAME: () #[[ATTR1]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -2549,12 +2549,12 @@ int main() { // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) @@ -2611,14 +2611,14 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -2629,11 +2629,11 @@ int main() { // CHECK15: arraydestroy.body12: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK15: arraydestroy.done16: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP11]] // @@ -2701,7 +2701,7 @@ int main() { // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // diff --git a/clang/test/OpenMP/distribute_simd_private_codegen.cpp b/clang/test/OpenMP/distribute_simd_private_codegen.cpp index bd586046faba..3e00b98518c8 100644 --- a/clang/test/OpenMP/distribute_simd_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_private_codegen.cpp @@ -735,7 +735,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK9-SAME: () #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1024,7 +1024,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK9-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) // CHECK9-NEXT: ret void @@ -1386,7 +1386,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK11-SAME: () #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1673,7 +1673,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg -// CHECK11-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK11-SAME: () #[[ATTR5:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) // CHECK11-NEXT: ret void @@ -1695,13 +1695,13 @@ int main() { // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I12:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[_TMP13:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_LB14:%.*]] = alloca i32, align 4 @@ -1768,14 +1768,14 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -1812,11 +1812,11 @@ int main() { // CHECK13: arraydestroy.body28: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST29:%.*]] = phi ptr [ [[TMP15]], [[OMP_INNER_FOR_END26]] ], [ [[ARRAYDESTROY_ELEMENT30:%.*]], [[ARRAYDESTROY_BODY28]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT30]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST29]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT30]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT30]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE31:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT30]], [[ARRAY_BEGIN27]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE31]], label [[ARRAYDESTROY_DONE32:%.*]], label [[ARRAYDESTROY_BODY28]] // CHECK13: arraydestroy.done32: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP16]] // @@ -1850,12 +1850,12 @@ int main() { // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK13-SAME: () #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1868,12 +1868,12 @@ int main() { // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) @@ -1932,14 +1932,14 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -1950,11 +1950,11 @@ int main() { // CHECK13: arraydestroy.body13: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13: arraydestroy.done17: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP11]] // @@ -2022,7 +2022,7 @@ int main() { // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2076,13 +2076,13 @@ int main() { // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I11:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[_TMP12:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_LB13:%.*]] = alloca i32, align 4 @@ -2147,14 +2147,14 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -2191,11 +2191,11 @@ int main() { // CHECK15: arraydestroy.body27: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST28:%.*]] = phi ptr [ [[TMP15]], [[OMP_INNER_FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT29:%.*]], [[ARRAYDESTROY_BODY27]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT29]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST28]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT29]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT29]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE30:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT29]], [[ARRAY_BEGIN26]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE30]], label [[ARRAYDESTROY_DONE31:%.*]], label [[ARRAYDESTROY_BODY27]] // CHECK15: arraydestroy.done31: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP16]] // @@ -2229,12 +2229,12 @@ int main() { // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { +// CHECK15-SAME: () #[[ATTR1]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -2247,12 +2247,12 @@ int main() { // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) @@ -2309,14 +2309,14 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -2327,11 +2327,11 @@ int main() { // CHECK15: arraydestroy.body12: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK15: arraydestroy.done16: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP11]] // @@ -2399,7 +2399,7 @@ int main() { // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // diff --git a/clang/test/OpenMP/parallel_reduction_codegen.cpp b/clang/test/OpenMP/parallel_reduction_codegen.cpp index 552d969d0b3e..88a10a16615d 100644 --- a/clang/test/OpenMP/parallel_reduction_codegen.cpp +++ b/clang/test/OpenMP/parallel_reduction_codegen.cpp @@ -1350,7 +1350,7 @@ int main() { // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR2]], align 128 -// CHECK1-NEXT: [[TMP22:%.*]] = atomicrmw add ptr [[TMP1]], i32 [[TMP21]] monotonic, align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = atomicrmw add ptr [[TMP1]], i32 [[TMP21]] monotonic, align 128 // CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB2]], i32 [[TMP12]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP3]], ptr align 4 [[CALL10]], i64 4, i1 false) @@ -1371,7 +1371,7 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP11]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB2]], i32 [[TMP12]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR15]], align 128 -// CHECK1-NEXT: [[TMP25:%.*]] = atomicrmw min ptr [[TMP5]], i32 [[TMP24]] monotonic, align 4 +// CHECK1-NEXT: [[TMP25:%.*]] = atomicrmw min ptr [[TMP5]], i32 [[TMP24]] monotonic, align 128 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] @@ -2368,7 +2368,7 @@ int main() { // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK4: .omp.reduction.case2: // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[G1]], align 128 -// CHECK4-NEXT: [[TMP11:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP10]] monotonic, align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP10]] monotonic, align 128 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK4: .omp.reduction.default: // CHECK4-NEXT: ret void diff --git a/clang/test/OpenMP/simd_private_taskloop_codegen.cpp b/clang/test/OpenMP/simd_private_taskloop_codegen.cpp new file mode 100644 index 000000000000..50726b201523 --- /dev/null +++ b/clang/test/OpenMP/simd_private_taskloop_codegen.cpp @@ -0,0 +1,2692 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 + +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 + +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 + +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 +// expected-no-diagnostics +#ifndef HEADER +#define HEADER + +template +struct S { + T f; + S(T a) : f(a) {} + S() : f() {} + operator T() { return T(); } + ~S() {} +}; + +template +T tmain() { + S test; + T t_var = T(); + T vec[] = {1, 2}; + S s_arr[] = {1, 2}; + S &var = test; +#pragma omp taskloop simd private(t_var, vec, s_arr, s_arr, var, var) + for (int i = 0; i < 2; ++i) { + vec[i] = t_var; + s_arr[i] = var; + } + return T(); +} + +int main() { + static int svar; + volatile double g; + volatile double &g1 = g; + + #ifdef LAMBDA + [&]() { + static float sfvar; + +#pragma omp taskloop simd private(g, g1, svar, sfvar) + for (int i = 0; i < 2; ++i) { + g = 1; + g1 = 1; + svar = 3; + sfvar = 4.0; + [&]() { + g = 2; + g1 = 2; + svar = 4; + sfvar = 8.0; + + }(); + } + }(); + return 0; + #else + S test; + int t_var = 0; + int vec[] = {1, 2}; + S s_arr[] = {1, 2}; + S &var = test; + +#pragma omp taskloop simd private(t_var, vec, s_arr, s_arr, var, var, svar) + for (int i = 0; i < 2; ++i) { + vec[i] = t_var; + s_arr[i] = var; + } + int i; + +#pragma omp taskloop simd + for (i = 0; i < 2; ++i) { + ; + } + return tmain(); + #endif +} + + + + + + +#endif +// CHECK1-LABEL: define {{[^@]+}}@main +// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK1-NEXT: entry: +// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[G:%.*]] = alloca double, align 8 +// CHECK1-NEXT: [[G1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK1-NEXT: store ptr [[G]], ptr [[G1]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 +// CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) +// CHECK1-NEXT: ret i32 0 +// +// +// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-NEXT: entry: +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 +// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3 +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 +// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 +// CHECK1-NEXT: ret void +// +// +// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-NEXT: entry: +// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[TMP_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[TMP5_I:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[I_I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[REF_TMP_I:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTPRIV_PTR_ADDR_I]], ptr [[DOTPRIV_PTR_ADDR1_I]], ptr [[DOTPRIV_PTR_ADDR2_I]], ptr [[DOTPRIV_PTR_ADDR3_I]]) #[[ATTR2:[0-9]+]] +// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: store ptr undef, ptr [[TMP5_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32 +// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] +// CHECK1: omp.inner.for.cond.i: +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK1-NEXT: [[CONV6_I:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK1-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV6_I]], [[TMP28]] +// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] +// CHECK1: omp.inner.for.body.i: +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP30]], align 8, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: store i32 3, ptr [[TMP24]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: store float 4.000000e+00, ptr [[TMP25]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: store ptr [[TMP22]], ptr [[REF_TMP_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1 +// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: store ptr [[TMP32]], ptr [[TMP31]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP33]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP34]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK1-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1: .omp_outlined..exit: +// CHECK1-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@main +// CHECK3-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[G:%.*]] = alloca double, align 8 +// CHECK3-NEXT: [[G1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK3-NEXT: store ptr [[G]], ptr [[G1]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 4 +// CHECK3-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4 +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4 +// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3 +// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 4 +// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 4 +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK3-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[TMP_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[TMP5_I:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[I_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[REF_TMP_I:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META15:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META15]] +// CHECK3-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META15]] +// CHECK3-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META15]] +// CHECK3-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTPRIV_PTR_ADDR_I]], ptr [[DOTPRIV_PTR_ADDR1_I]], ptr [[DOTPRIV_PTR_ADDR2_I]], ptr [[DOTPRIV_PTR_ADDR3_I]]) #[[ATTR2:[0-9]+]] +// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: store ptr [[TMP23]], ptr [[TMP_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: store ptr undef, ptr [[TMP5_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META15]] +// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32 +// CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] +// CHECK3: omp.inner.for.cond.i: +// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK3-NEXT: [[CONV6_I:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK3-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV6_I]], [[TMP28]] +// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] +// CHECK3: omp.inner.for.body.i: +// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP30]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: store i32 3, ptr [[TMP24]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: store float 4.000000e+00, ptr [[TMP25]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: store ptr [[TMP22]], ptr [[REF_TMP_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: store ptr [[TMP32]], ptr [[TMP31]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP24]], ptr [[TMP33]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP34]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK3-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK3: .omp_outlined..exit: +// CHECK3-NEXT: ret i32 0 +// +// +// CHECK5-LABEL: define {{[^@]+}}@main +// CHECK5-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK5-NEXT: entry: +// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 +// CHECK5-NEXT: [[G1:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 +// CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK5-NEXT: store ptr [[G]], ptr [[G1]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) +// CHECK5-NEXT: ret i32 0 +// +// +// CHECK7-LABEL: define {{[^@]+}}@main +// CHECK7-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK7-NEXT: entry: +// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 +// CHECK7-NEXT: [[G1:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 +// CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK7-NEXT: store ptr [[G]], ptr [[G1]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 +// CHECK7-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 +// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) +// CHECK7-NEXT: ret i32 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@main +// CHECK9-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 +// CHECK9-NEXT: [[G1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1 +// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) +// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK9-NEXT: store ptr [[G]], ptr [[G1]], align 8 +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) +// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 +// CHECK9-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 9, i64 112, i64 1, ptr @.omp_task_entry.) +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 3 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK9: arrayctor.loop: +// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK9: arrayctor.cont: +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP2]], i32 0, i32 3 +// CHECK9-NEXT: store ptr @.omp_task_destructor., ptr [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 5 +// CHECK9-NEXT: store i64 0, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 6 +// CHECK9-NEXT: store i64 1, ptr [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 7 +// CHECK9-NEXT: store i64 1, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 9 +// CHECK9-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 8, i1 false) +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK9-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 0, i64 0, ptr @.omp_task_dup.) +// CHECK9-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 80, i64 1, ptr @.omp_task_entry..2) +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP12]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 5 +// CHECK9-NEXT: store i64 0, ptr [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 6 +// CHECK9-NEXT: store i64 1, ptr [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 7 +// CHECK9-NEXT: store i64 1, ptr [[TMP16]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 9 +// CHECK9-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP17]], i8 0, i64 8, i1 false) +// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP16]], align 8 +// CHECK9-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP12]], i32 1, ptr [[TMP14]], ptr [[TMP15]], i64 [[TMP18]], i32 1, i32 0, i64 0, ptr null) +// CHECK9-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2 +// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK9: arraydestroy.body: +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done5: +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK9-NEXT: ret i32 [[TMP20]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK9-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]], ptr noalias noundef [[TMP5:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// CHECK9-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 +// CHECK9-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 +// CHECK9-NEXT: store ptr [[TMP5]], ptr [[DOTADDR5]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP6]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 +// CHECK9-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 +// CHECK9-NEXT: store ptr [[TMP13]], ptr [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR5]], align 8 +// CHECK9-NEXT: store ptr [[TMP15]], ptr [[TMP16]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK9-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIV_PTR_ADDR4_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[TMP_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[TMP6_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[I_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] +// CHECK9-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK9-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTPRIV_PTR_ADDR_I]], ptr [[DOTPRIV_PTR_ADDR1_I]], ptr [[DOTPRIV_PTR_ADDR2_I]], ptr [[DOTPRIV_PTR_ADDR3_I]], ptr [[DOTPRIV_PTR_ADDR4_I]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store ptr [[TMP25]], ptr [[TMP_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: store ptr undef, ptr [[TMP6_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK9-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32 +// CHECK9-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] +// CHECK9: omp.inner.for.cond.i: +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK9-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK9-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP29]] +// CHECK9-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] +// CHECK9: omp.inner.for.body.i: +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP22]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[TMP32:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP32]] to i64 +// CHECK9-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP23]], i64 0, i64 [[IDXPROM_I]] +// CHECK9-NEXT: store i32 [[TMP31]], ptr [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[IDXPROM8_I:%.*]] = sext i32 [[TMP34]] to i64 +// CHECK9-NEXT: [[ARRAYIDX9_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP24]], i64 0, i64 [[IDXPROM8_I]] +// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9_I]], ptr align 4 [[TMP33]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[ADD10_I:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK9-NEXT: store i32 [[ADD10_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK9: .omp_outlined..exit: +// CHECK9-NEXT: ret i32 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_dup. +// CHECK9-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef signext [[TMP2:%.*]]) #[[ATTR6]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP4]], i32 0, i32 3 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP6]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK9: arrayctor.loop: +// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK9: arrayctor.cont: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_destructor. +// CHECK9-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 3 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK9: arraydestroy.body: +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done2: +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK9-NEXT: ret i32 [[TMP7]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_entry..2 +// CHECK9-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[I_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META30:![0-9]+]] +// CHECK9-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META30]] +// CHECK9-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META30]] +// CHECK9-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32 +// CHECK9-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META30]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] +// CHECK9: omp.inner.for.cond.i: +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META30]], !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK9-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META30]], !llvm.access.group [[ACC_GRP31]] +// CHECK9-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]] +// CHECK9-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK9: omp.inner.for.body.i: +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META30]], !llvm.access.group [[ACC_GRP31]] +// CHECK9-NEXT: store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META30]], !llvm.access.group [[ACC_GRP31]] +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META30]], !llvm.access.group [[ACC_GRP31]] +// CHECK9-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK9-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META30]], !llvm.access.group [[ACC_GRP31]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK9: .omp_outlined..1.exit: +// CHECK9-NEXT: ret i32 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK9-SAME: () #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_2:%.*]], align 4 +// CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.2], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 1 +// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) +// CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[S_ARR]], i64 0, i64 0 +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 +// CHECK9-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 9, i64 104, i64 1, ptr @.omp_task_entry..5) +// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]]) +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP3]], i32 0, i32 3 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK9: arrayctor.loop: +// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK9: arrayctor.cont: +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP2]], i32 0, i32 3 +// CHECK9-NEXT: store ptr @.omp_task_destructor..7, ptr [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 5 +// CHECK9-NEXT: store i64 0, ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 6 +// CHECK9-NEXT: store i64 1, ptr [[TMP8]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 7 +// CHECK9-NEXT: store i64 1, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 9 +// CHECK9-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 8, i1 false) +// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK9-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 0, i64 0, ptr @.omp_task_dup..6) +// CHECK9-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN2]], i64 2 +// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK9: arraydestroy.body: +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done3: +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK9-NEXT: ret i32 [[TMP13]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 +// CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_privates_map..4 +// CHECK9-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// CHECK9-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 +// CHECK9-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 +// CHECK9-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP5]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP5]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// CHECK9-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP5]], i32 0, i32 3 +// CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 +// CHECK9-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_entry..5 +// CHECK9-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK9-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[TMP_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[TMP5_I:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[I_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4]], ptr [[TMP3]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]]) +// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META45:![0-9]+]] +// CHECK9-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store ptr @.omp_task_privates_map..4, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META45]] +// CHECK9-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTPRIV_PTR_ADDR_I]], ptr [[DOTPRIV_PTR_ADDR1_I]], ptr [[DOTPRIV_PTR_ADDR2_I]], ptr [[DOTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store ptr [[TMP25]], ptr [[TMP_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: store ptr undef, ptr [[TMP5_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META45]] +// CHECK9-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32 +// CHECK9-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META45]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] +// CHECK9: omp.inner.for.cond.i: +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META45]], !llvm.access.group [[ACC_GRP46:![0-9]+]] +// CHECK9-NEXT: [[CONV6_I:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK9-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META45]], !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV6_I]], [[TMP28]] +// CHECK9-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] +// CHECK9: omp.inner.for.body.i: +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META45]], !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias [[META45]], !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP22]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META45]], !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP31]] to i64 +// CHECK9-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP23]], i64 0, i64 [[IDXPROM_I]] +// CHECK9-NEXT: store i32 [[TMP30]], ptr [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP_I]], align 8, !noalias [[META45]], !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META45]], !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: [[IDXPROM7_I:%.*]] = sext i32 [[TMP33]] to i64 +// CHECK9-NEXT: [[ARRAYIDX8_I:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP24]], i64 0, i64 [[IDXPROM7_I]] +// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8_I]], ptr align 4 [[TMP32]], i64 4, i1 false), !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META45]], !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP34]], 1 +// CHECK9-NEXT: store i32 [[ADD9_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META45]], !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK9: .omp_outlined..3.exit: +// CHECK9-NEXT: ret i32 0 +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_dup..6 +// CHECK9-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef signext [[TMP2:%.*]]) #[[ATTR6]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4:%.*]], ptr [[TMP3]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP4]], i32 0, i32 3 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP6]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK9: arrayctor.loop: +// CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK9: arrayctor.cont: +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@.omp_task_destructor..7 +// CHECK9-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4:%.*]], ptr [[TMP2]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP3]], i32 0, i32 3 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK9: arraydestroy.body: +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK9: arraydestroy.done2: +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]]) #[[ATTR3]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK9-NEXT: ret i32 [[TMP7]] +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: store i32 0, ptr [[F]], align 4 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 +// CHECK9-NEXT: ret void +// +// +// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-NEXT: entry: +// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK9-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@main +// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 +// CHECK11-NEXT: [[G1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1 +// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) +// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK11-NEXT: store ptr [[G]], ptr [[G1]], align 4 +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) +// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1 +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 +// CHECK11-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: store ptr undef, ptr [[_TMP1]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 9, i32 80, i32 1, ptr @.omp_task_entry.) +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK11: arrayctor.loop: +// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK11: arrayctor.cont: +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 3 +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP2]], i32 0, i32 3 +// CHECK11-NEXT: store ptr @.omp_task_destructor., ptr [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 5 +// CHECK11-NEXT: store i64 0, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 6 +// CHECK11-NEXT: store i64 1, ptr [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 7 +// CHECK11-NEXT: store i64 1, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 9 +// CHECK11-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[TMP10]], i8 0, i32 4, i1 false) +// CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 4 +// CHECK11-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 0, i64 0, ptr @.omp_task_dup.) +// CHECK11-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 52, i32 1, ptr @.omp_task_entry..2) +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP12]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 5 +// CHECK11-NEXT: store i64 0, ptr [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 6 +// CHECK11-NEXT: store i64 1, ptr [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 7 +// CHECK11-NEXT: store i64 1, ptr [[TMP16]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 9 +// CHECK11-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[TMP17]], i8 0, i32 4, i1 false) +// CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP16]], align 4 +// CHECK11-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP12]], i32 1, ptr [[TMP14]], ptr [[TMP15]], i64 [[TMP18]], i32 1, i32 0, i64 0, ptr null) +// CHECK11-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 +// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK11: arraydestroy.body: +// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] +// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK11: arraydestroy.done5: +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK11-NEXT: ret i32 [[TMP20]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK11-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]], ptr noalias noundef [[TMP5:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK11-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 4 +// CHECK11-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 4 +// CHECK11-NEXT: store ptr [[TMP5]], ptr [[DOTADDR5]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP6]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR2]], align 4 +// CHECK11-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTADDR3]], align 4 +// CHECK11-NEXT: store ptr [[TMP11]], ptr [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTADDR4]], align 4 +// CHECK11-NEXT: store ptr [[TMP13]], ptr [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR5]], align 4 +// CHECK11-NEXT: store ptr [[TMP15]], ptr [[TMP16]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK11-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIV_PTR_ADDR4_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[TMP_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[TMP6_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[I_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META15:![0-9]+]] +// CHECK11-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META15]] +// CHECK11-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META15]] +// CHECK11-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META15]] +// CHECK11-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTPRIV_PTR_ADDR_I]], ptr [[DOTPRIV_PTR_ADDR1_I]], ptr [[DOTPRIV_PTR_ADDR2_I]], ptr [[DOTPRIV_PTR_ADDR3_I]], ptr [[DOTPRIV_PTR_ADDR4_I]]) #[[ATTR3]] +// CHECK11-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: store ptr [[TMP25]], ptr [[TMP_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR4_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: store ptr undef, ptr [[TMP6_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META15]] +// CHECK11-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32 +// CHECK11-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] +// CHECK11: omp.inner.for.cond.i: +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16:![0-9]+]] +// CHECK11-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK11-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP29]] +// CHECK11-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] +// CHECK11: omp.inner.for.body.i: +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP22]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: [[TMP32:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP23]], i32 0, i32 [[TMP32]] +// CHECK11-NEXT: store i32 [[TMP31]], ptr [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: [[ARRAYIDX8_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP24]], i32 0, i32 [[TMP34]] +// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8_I]], ptr align 4 [[TMP33]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP35]], 1 +// CHECK11-NEXT: store i32 [[ADD9_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK11: .omp_outlined..exit: +// CHECK11-NEXT: ret i32 0 +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_dup. +// CHECK11-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR6]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK11: arrayctor.loop: +// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK11: arrayctor.cont: +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP4]], i32 0, i32 3 +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_destructor. +// CHECK11-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 3 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR3]] +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK11: arraydestroy.body: +// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK11: arraydestroy.done2: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK11-NEXT: ret i32 [[TMP7]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_entry..2 +// CHECK11-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[I_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4 +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META31:![0-9]+]] +// CHECK11-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META31]] +// CHECK11-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META31]] +// CHECK11-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META31]] +// CHECK11-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META31]] +// CHECK11-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]] +// CHECK11-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]] +// CHECK11-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META31]] +// CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]] +// CHECK11-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 4, !noalias [[META31]] +// CHECK11-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META31]] +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META31]] +// CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]] +// CHECK11-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32 +// CHECK11-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] +// CHECK11: omp.inner.for.cond.i: +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32:![0-9]+]] +// CHECK11-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK11-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]] +// CHECK11-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]] +// CHECK11-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] +// CHECK11: omp.inner.for.body.i: +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]] +// CHECK11-NEXT: store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]] +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]] +// CHECK11-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK11-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]] +// CHECK11: .omp_outlined..1.exit: +// CHECK11-NEXT: ret i32 0 +// +// +// CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK11-SAME: () #[[ATTR1]] comdat { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_2:%.*]], align 4 +// CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.2], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 1 +// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) +// CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYINIT_BEGIN]], i32 1 +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 +// CHECK11-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: store ptr undef, ptr [[_TMP1]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 9, i32 76, i32 1, ptr @.omp_task_entry..5) +// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4]], ptr [[TMP1]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK11: arrayctor.loop: +// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK11: arrayctor.cont: +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP3]], i32 0, i32 3 +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP2]], i32 0, i32 3 +// CHECK11-NEXT: store ptr @.omp_task_destructor..7, ptr [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 5 +// CHECK11-NEXT: store i64 0, ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 6 +// CHECK11-NEXT: store i64 1, ptr [[TMP8]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 7 +// CHECK11-NEXT: store i64 1, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP2]], i32 0, i32 9 +// CHECK11-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[TMP10]], i8 0, i32 4, i1 false) +// CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 4 +// CHECK11-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 0, i64 0, ptr @.omp_task_dup..6) +// CHECK11-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) +// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN2]], i32 2 +// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK11: arraydestroy.body: +// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] +// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK11: arraydestroy.done3: +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK11-NEXT: ret i32 [[TMP13]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: store float 0.000000e+00, ptr [[F]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 +// CHECK11-NEXT: store float [[TMP0]], ptr [[F]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_privates_map..4 +// CHECK11-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK11-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 4 +// CHECK11-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP5]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4 +// CHECK11-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP5]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4 +// CHECK11-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP5]], i32 0, i32 3 +// CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 4 +// CHECK11-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_entry..5 +// CHECK11-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 +// CHECK11-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[TMP_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[TMP5_I:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[I_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4]], ptr [[TMP3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK11-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK11-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4 +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK11-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]]) +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META46:![0-9]+]] +// CHECK11-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: store ptr @.omp_task_privates_map..4, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META46]] +// CHECK11-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META46]] +// CHECK11-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META46]] +// CHECK11-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTPRIV_PTR_ADDR_I]], ptr [[DOTPRIV_PTR_ADDR1_I]], ptr [[DOTPRIV_PTR_ADDR2_I]], ptr [[DOTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] +// CHECK11-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTPRIV_PTR_ADDR3_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: store ptr [[TMP25]], ptr [[TMP_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: store ptr undef, ptr [[TMP5_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META46]] +// CHECK11-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32 +// CHECK11-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META46]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] +// CHECK11: omp.inner.for.cond.i: +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META46]], !llvm.access.group [[ACC_GRP47:![0-9]+]] +// CHECK11-NEXT: [[CONV6_I:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK11-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META46]], !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV6_I]], [[TMP28]] +// CHECK11-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]] +// CHECK11: omp.inner.for.body.i: +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META46]], !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias [[META46]], !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP22]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META46]], !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP23]], i32 0, i32 [[TMP31]] +// CHECK11-NEXT: store i32 [[TMP30]], ptr [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP_I]], align 4, !noalias [[META46]], !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META46]], !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: [[ARRAYIDX7_I:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP24]], i32 0, i32 [[TMP33]] +// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7_I]], ptr align 4 [[TMP32]], i32 4, i1 false), !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META46]], !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: [[ADD8_I:%.*]] = add nsw i32 [[TMP34]], 1 +// CHECK11-NEXT: store i32 [[ADD8_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META46]], !llvm.access.group [[ACC_GRP47]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP48:![0-9]+]] +// CHECK11: .omp_outlined..3.exit: +// CHECK11-NEXT: ret i32 0 +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_dup..6 +// CHECK11-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR6]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4:%.*]], ptr [[TMP3]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK11: arrayctor.loop: +// CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK11: arrayctor.cont: +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP4]], i32 0, i32 3 +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]]) +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@.omp_task_destructor..7 +// CHECK11-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK11-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_4:%.*]], ptr [[TMP2]], i32 0, i32 1 +// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_5]], ptr [[TMP3]], i32 0, i32 3 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR3]] +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK11: arraydestroy.body: +// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK11: arraydestroy.done2: +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK11-NEXT: ret i32 [[TMP7]] +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: store i32 0, ptr [[F]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-NEXT: entry: +// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK11-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@main +// CHECK13-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 +// CHECK13-NEXT: [[G1:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I13:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[_TMP14:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[DOTOMP_LB15:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_UB16:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV17:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[I19:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK13-NEXT: store ptr [[G]], ptr [[G1]], align 8 +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) +// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 +// CHECK13-NEXT: store ptr undef, ptr [[_TMP1]], align 8 +// CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: store i64 1, ptr [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK13: arrayctor.loop: +// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK13: arrayctor.cont: +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) +// CHECK13-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] +// CHECK13-NEXT: [[CONV7:%.*]] = sext i32 [[TMP1]] to i64 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV7]], [[TMP2]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK13: omp.inner.for.cond.cleanup: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP7]] to i64 +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK13-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: store i32 2, ptr [[I]], align 4 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 +// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK13: arraydestroy.body: +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK13: arraydestroy.done12: +// CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB15]], align 8 +// CHECK13-NEXT: store i64 1, ptr [[DOTOMP_UB16]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_LB15]], align 8 +// CHECK13-NEXT: [[CONV18:%.*]] = trunc i64 [[TMP10]] to i32 +// CHECK13-NEXT: store i32 [[CONV18]], ptr [[DOTOMP_IV17]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND20:%.*]] +// CHECK13: omp.inner.for.cond20: +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] +// CHECK13-NEXT: [[CONV21:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK13-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB16]], align 8, !llvm.access.group [[ACC_GRP6]] +// CHECK13-NEXT: [[CMP22:%.*]] = icmp ule i64 [[CONV21]], [[TMP12]] +// CHECK13-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] +// CHECK13: omp.inner.for.body23: +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK13-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] +// CHECK13-NEXT: store i32 [[ADD25]], ptr [[I19]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] +// CHECK13: omp.body.continue26: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] +// CHECK13: omp.inner.for.inc27: +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV17]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK13-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_IV17]], align 4, !llvm.access.group [[ACC_GRP6]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK13: omp.inner.for.end29: +// CHECK13-NEXT: store i32 2, ptr [[I13]], align 4 +// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// CHECK13-NEXT: [[ARRAY_BEGIN30:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN30]], i64 2 +// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY31:%.*]] +// CHECK13: arraydestroy.body31: +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST32:%.*]] = phi ptr [ [[TMP15]], [[OMP_INNER_FOR_END29]] ], [ [[ARRAYDESTROY_ELEMENT33:%.*]], [[ARRAYDESTROY_BODY31]] ] +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT33]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST32]], i64 -1 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT33]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAYDESTROY_DONE34:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT33]], [[ARRAY_BEGIN30]] +// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE34]], label [[ARRAYDESTROY_DONE35:%.*]], label [[ARRAYDESTROY_BODY31]] +// CHECK13: arraydestroy.done35: +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK13-NEXT: ret i32 [[TMP16]] +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK13-SAME: () #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 +// CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) +// CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 +// CHECK13-NEXT: store ptr undef, ptr [[_TMP1]], align 8 +// CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: store i64 1, ptr [[DOTOMP_UB]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK13: arrayctor.loop: +// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK13: arrayctor.cont: +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) +// CHECK13-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK13: omp.inner.for.cond: +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] +// CHECK13-NEXT: [[CONV7:%.*]] = sext i32 [[TMP1]] to i64 +// CHECK13-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV7]], [[TMP2]] +// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK13: omp.inner.for.cond.cleanup: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK13: omp.inner.for.body: +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP7]] to i64 +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: +// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK13: omp.inner.for.inc: +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK13-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK13: omp.inner.for.end: +// CHECK13-NEXT: store i32 2, ptr [[I]], align 4 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 +// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK13: arraydestroy.body: +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] +// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK13: arraydestroy.done12: +// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 +// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY14:%.*]] +// CHECK13: arraydestroy.body14: +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST15]], i64 -1 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] +// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] +// CHECK13: arraydestroy.done18: +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK13-NEXT: ret i32 [[TMP11]] +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 +// CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: store i32 0, ptr [[F]], align 4 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 +// CHECK13-NEXT: ret void +// +// +// CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-NEXT: entry: +// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK13-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@main +// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 +// CHECK15-NEXT: [[G1:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I12:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[_TMP13:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[DOTOMP_LB14:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_UB15:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[I18:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK15-NEXT: store ptr [[G]], ptr [[G1]], align 4 +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) +// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1 +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 +// CHECK15-NEXT: store ptr undef, ptr [[_TMP1]], align 4 +// CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: store i64 1, ptr [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK15-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK15: arrayctor.loop: +// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK15: arrayctor.cont: +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) +// CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] +// CHECK15-NEXT: [[CONV7:%.*]] = sext i32 [[TMP1]] to i64 +// CHECK15-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV7]], [[TMP2]] +// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK15: omp.inner.for.cond.cleanup: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK15-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: store i32 2, ptr [[I]], align 4 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 +// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK15: arraydestroy.body: +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK15: arraydestroy.done11: +// CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB14]], align 8 +// CHECK15-NEXT: store i64 1, ptr [[DOTOMP_UB15]], align 8 +// CHECK15-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_LB14]], align 8 +// CHECK15-NEXT: [[CONV17:%.*]] = trunc i64 [[TMP10]] to i32 +// CHECK15-NEXT: store i32 [[CONV17]], ptr [[DOTOMP_IV16]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND19:%.*]] +// CHECK15: omp.inner.for.cond19: +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] +// CHECK15-NEXT: [[CONV20:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK15-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB15]], align 8, !llvm.access.group [[ACC_GRP7]] +// CHECK15-NEXT: [[CMP21:%.*]] = icmp ule i64 [[CONV20]], [[TMP12]] +// CHECK15-NEXT: br i1 [[CMP21]], label [[OMP_INNER_FOR_BODY22:%.*]], label [[OMP_INNER_FOR_END28:%.*]] +// CHECK15: omp.inner.for.body22: +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK15-NEXT: [[MUL23:%.*]] = mul nsw i32 [[TMP13]], 1 +// CHECK15-NEXT: [[ADD24:%.*]] = add nsw i32 0, [[MUL23]] +// CHECK15-NEXT: store i32 [[ADD24]], ptr [[I18]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE25:%.*]] +// CHECK15: omp.body.continue25: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC26:%.*]] +// CHECK15: omp.inner.for.inc26: +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK15-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK15-NEXT: store i32 [[ADD27]], ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]] +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND19]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK15: omp.inner.for.end28: +// CHECK15-NEXT: store i32 2, ptr [[I12]], align 4 +// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// CHECK15-NEXT: [[ARRAY_BEGIN29:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN29]], i32 2 +// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY30:%.*]] +// CHECK15: arraydestroy.body30: +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST31:%.*]] = phi ptr [ [[TMP15]], [[OMP_INNER_FOR_END28]] ], [ [[ARRAYDESTROY_ELEMENT32:%.*]], [[ARRAYDESTROY_BODY30]] ] +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT32]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST31]], i32 -1 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT32]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAYDESTROY_DONE33:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT32]], [[ARRAY_BEGIN29]] +// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE33]], label [[ARRAYDESTROY_DONE34:%.*]], label [[ARRAYDESTROY_BODY30]] +// CHECK15: arraydestroy.done34: +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK15-NEXT: ret i32 [[TMP16]] +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v +// CHECK15-SAME: () #[[ATTR1]] comdat { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 +// CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) +// CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1 +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 +// CHECK15-NEXT: store ptr undef, ptr [[_TMP1]], align 4 +// CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: store i64 1, ptr [[DOTOMP_UB]], align 8 +// CHECK15-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// CHECK15-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// CHECK15-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK15: arrayctor.loop: +// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 +// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK15: arrayctor.cont: +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) +// CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK15: omp.inner.for.cond: +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] +// CHECK15-NEXT: [[CONV7:%.*]] = sext i32 [[TMP1]] to i64 +// CHECK15-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV7]], [[TMP2]] +// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] +// CHECK15: omp.inner.for.cond.cleanup: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] +// CHECK15: omp.inner.for.body: +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 +// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK15: omp.body.continue: +// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK15: omp.inner.for.inc: +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK15-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK15: omp.inner.for.end: +// CHECK15-NEXT: store i32 2, ptr [[I]], align 4 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 +// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK15: arraydestroy.body: +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] +// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK15: arraydestroy.done11: +// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 +// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] +// CHECK15: arraydestroy.body13: +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i32 -1 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] +// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] +// CHECK15: arraydestroy.done17: +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK15-NEXT: ret i32 [[TMP11]] +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: store float 0.000000e+00, ptr [[F]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 +// CHECK15-NEXT: store float [[TMP0]], ptr [[F]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: store i32 0, ptr [[F]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 +// CHECK15-NEXT: ret void +// +// +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp index 6fcbb8def798..48ead1c3e43c 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp @@ -564,7 +564,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { +// CHECK1-SAME: () #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1326,7 +1326,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { +// CHECK3-SAME: () #[[ATTR1]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1828,14 +1828,14 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: () #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1909,7 +1909,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2103,12 +2103,12 @@ int main() { // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2177,7 +2177,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-SAME: () #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -2190,12 +2190,12 @@ int main() { // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) @@ -2481,12 +2481,12 @@ int main() { // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2553,7 +2553,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK9-SAME: () #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -2566,12 +2566,12 @@ int main() { // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 +// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) diff --git a/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp index d754a33dc8d0..bf38e4bace5a 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp @@ -395,7 +395,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { +// CHECK1-SAME: () #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -942,7 +942,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { +// CHECK3-SAME: () #[[ATTR1]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1295,12 +1295,12 @@ int main() { // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1369,7 +1369,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-SAME: () #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1382,12 +1382,12 @@ int main() { // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) @@ -1673,12 +1673,12 @@ int main() { // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1745,7 +1745,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-SAME: () #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1758,12 +1758,12 @@ int main() { // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) @@ -2089,14 +2089,14 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK9-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: () #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp index 14c7f4f2365b..8ad19077ed73 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp @@ -309,7 +309,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -407,7 +407,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -528,7 +528,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat { +// CHECK1-SAME: () #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -628,7 +628,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -729,7 +729,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1077,7 +1077,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1173,7 +1173,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1290,7 +1290,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat { +// CHECK3-SAME: () #[[ATTR1]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1390,7 +1390,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1489,7 +1489,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1750,12 +1750,12 @@ int main() { // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1824,7 +1824,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-SAME: () #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1837,12 +1837,12 @@ int main() { // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) @@ -2128,12 +2128,12 @@ int main() { // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2200,7 +2200,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-SAME: () #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -2213,12 +2213,12 @@ int main() { // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) @@ -2544,7 +2544,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 @@ -2555,7 +2555,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2629,7 +2629,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR6]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 diff --git a/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp index bfe5d360ed30..1e629933d739 100644 --- a/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp @@ -288,7 +288,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -399,7 +399,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat { +// CHECK1-SAME: () #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -499,7 +499,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -837,7 +837,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -946,7 +946,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat { +// CHECK3-SAME: () #[[ATTR1]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1046,7 +1046,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 @@ -1299,12 +1299,12 @@ int main() { // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1373,7 +1373,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK5-SAME: () #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1386,12 +1386,12 @@ int main() { // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 +// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) @@ -1677,12 +1677,12 @@ int main() { // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1749,7 +1749,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v -// CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { +// CHECK7-SAME: () #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 @@ -1762,12 +1762,12 @@ int main() { // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 +// CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) @@ -2093,7 +2093,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 @@ -2104,7 +2104,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 diff --git a/clang/test/ParserOpenACC/parse-cache-construct.c b/clang/test/ParserOpenACC/parse-cache-construct.c new file mode 100644 index 000000000000..10976627ca95 --- /dev/null +++ b/clang/test/ParserOpenACC/parse-cache-construct.c @@ -0,0 +1,166 @@ +// RUN: %clang_cc1 %s -verify -fopenacc + +char *getArrayPtr(); +void func() { + char Array[10]; + char *ArrayPtr = getArrayPtr(); + int *readonly; + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+3{{expected '('}} + // expected-warning@+2{{OpenACC clause parsing not yet implemented}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache clause list + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache() + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+2{{OpenACC clause parsing not yet implemented}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache() clause-list + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache( + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+4{{use of undeclared identifier 'invalid'}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(invalid + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+4{{expected '['}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(ArrayPtr + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{use of undeclared identifier 'invalid'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(invalid) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected '['}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(ArrayPtr) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(ArrayPtr[ + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(ArrayPtr[, 5) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Array[) + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Array[*readonly]) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(Array[*readonly: + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected '['}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected '['}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected expression}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr[5:]) + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr[5:*readonly]) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected '['}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr[5:*readonly], Array) + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr[5:*readonly], Array[*readonly:3]) + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr[5 + i:*readonly], Array[*readonly + i:3]) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+4{{expected identifier}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr[5:*readonly], + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{expected identifier}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr[5:*readonly],) + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+2{{left operand of comma operator has no effect}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr[5,6:*readonly]) + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+2{{left operand of comma operator has no effect}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(readonly:ArrayPtr[5:3, *readonly], ArrayPtr[0]) + } + +} diff --git a/clang/test/ParserOpenACC/parse-cache-construct.cpp b/clang/test/ParserOpenACC/parse-cache-construct.cpp new file mode 100644 index 000000000000..3b2230cabae3 --- /dev/null +++ b/clang/test/ParserOpenACC/parse-cache-construct.cpp @@ -0,0 +1,51 @@ +// RUN: %clang_cc1 %s -verify -fopenacc + +namespace NS { + static char* NSArray;// expected-note{{declared here}} + static int NSInt;// expected-note 2{{declared here}} +} +char *getArrayPtr(); +template +void func() { + char *ArrayPtr = getArrayPtr(); + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(ArrayPtr[T::value + I:I + 5], T::array[(i + T::value, 5): 6]) + } + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(NS::NSArray[NS::NSInt]) + } + + for (int i = 0; i < 10; ++i) { + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(NS::NSArray[NS::NSInt : NS::NSInt]) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{use of undeclared identifier 'NSArray'; did you mean 'NS::NSArray'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(NSArray[NS::NSInt : NS::NSInt]) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{use of undeclared identifier 'NSInt'; did you mean 'NS::NSInt'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(NS::NSArray[NSInt : NS::NSInt]) + } + + for (int i = 0; i < 10; ++i) { + // expected-error@+2{{use of undeclared identifier 'NSInt'; did you mean 'NS::NSInt'}} + // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} + #pragma acc cache(NS::NSArray[NS::NSInt : NSInt]) + } +} + +struct S { + static constexpr int value = 5; + static constexpr char array[] ={1,2,3,4,5}; +}; + +void use() { + func(); +} diff --git a/clang/test/ParserOpenACC/parse-constructs.c b/clang/test/ParserOpenACC/parse-constructs.c index f0f9d75ade1f..b745f54bd715 100644 --- a/clang/test/ParserOpenACC/parse-constructs.c +++ b/clang/test/ParserOpenACC/parse-constructs.c @@ -61,7 +61,7 @@ void func() { // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc enter for(;;){} - // expected-error@+3{{invalid OpenACC directive 'exit }'}} + // expected-error@+3{{expected identifier}} // expected-warning@+2{{OpenACC clause parsing not yet implemented}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} #pragma acc exit } diff --git a/clang/test/ParserOpenACC/unimplemented.c b/clang/test/ParserOpenACC/unimplemented.c index dd2e8bea7470..2927e685d30b 100644 --- a/clang/test/ParserOpenACC/unimplemented.c +++ b/clang/test/ParserOpenACC/unimplemented.c @@ -1,26 +1,26 @@ // RUN: %clang_cc1 %s -verify -fopenacc // Parser::ParseExternalDeclaration -// expected-error@+3{{invalid OpenACC directive 'not'}} +// expected-error@+3{{invalid OpenACC directive 'havent'}} // expected-warning@+2{{OpenACC clause parsing not yet implemented}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} -#pragma acc not yet implemented +#pragma acc havent implemented int foo; struct S { // Parser::ParseStructUnionBody -// expected-error@+3{{invalid OpenACC directive 'not'}} +// expected-error@+3{{invalid OpenACC directive 'havent'}} // expected-warning@+2{{OpenACC clause parsing not yet implemented}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} -#pragma acc not yet implemented +#pragma acc havent implemented int foo; }; void func() { // Parser::ParseStmtOrDeclarationAfterAttributes -// expected-error@+3{{invalid OpenACC directive 'not'}} +// expected-error@+3{{invalid OpenACC directive 'havent'}} // expected-warning@+2{{OpenACC clause parsing not yet implemented}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} -#pragma acc not yet implemented +#pragma acc havent implemented while(0) {} } diff --git a/clang/test/ParserOpenACC/unimplemented.cpp b/clang/test/ParserOpenACC/unimplemented.cpp index 4f6c5a649065..77619c9ae655 100644 --- a/clang/test/ParserOpenACC/unimplemented.cpp +++ b/clang/test/ParserOpenACC/unimplemented.cpp @@ -1,26 +1,26 @@ // RUN: %clang_cc1 %s -verify -fopenacc // Parser::ParseExternalDeclaration -// expected-error@+3{{invalid OpenACC directive 'not'}} +// expected-error@+3{{invalid OpenACC directive 'havent'}} // expected-warning@+2{{OpenACC clause parsing not yet implemented}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} -#pragma acc not yet implemented +#pragma acc havent implemented int foo; struct S { // Parser::ParseCXXClassMemberDeclarationWithPragmas -// expected-error@+3{{invalid OpenACC directive 'not'}} +// expected-error@+3{{invalid OpenACC directive 'havent'}} // expected-warning@+2{{OpenACC clause parsing not yet implemented}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} -#pragma acc not yet implemented +#pragma acc havent implemented int foo; }; void func() { // Parser::ParseStmtOrDeclarationAfterAttributes -// expected-error@+3{{invalid OpenACC directive 'not'}} +// expected-error@+3{{invalid OpenACC directive 'havent'}} // expected-warning@+2{{OpenACC clause parsing not yet implemented}} // expected-warning@+1{{OpenACC directives not yet implemented, pragma ignored}} -#pragma acc not yet implemented +#pragma acc havent implemented while(false) {} } diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp index 70987ad395f7..3750045fd8df 100644 --- a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp +++ b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp @@ -20,7 +20,168 @@ void test_outer_product(svbool_t pred, svint16_t s16, svuint16_t u16, svint32_t svbmops_za32_s32_m(4, pred, pred, s32, s32); // expected-error {{argument value 4 is outside the valid range [0, 3]}} } -void test_ldr_str_zt(const void *const_base, void *base) __arm_streaming_compatible __arm_shared_za __arm_preserves_za { +void test_ldr_zt(const void *const_base) __arm_streaming_compatible __arm_shared_za { svldr_zt(1, const_base); // expected-error {{argument value 1 is outside the valid range [0, 0]}} +} + +void test_str_zt(void *base) __arm_streaming_compatible __arm_shared_za __arm_preserves_za { svstr_zt(1, base); // expected-error {{argument value 1 is outside the valid range [0, 0]}} } + +void test_svluti2_lane_zt_x4(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + // Test Reg Offset + svluti2_lane_zt_u8_x4(1, zn, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_u8_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti2_lane_zt_u16_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_u16_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti2_lane_zt_u32_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_u32_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti2_lane_zt_f16_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_f16_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti2_lane_zt_bf16_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_bf16_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti2_lane_zt_f32_x4(1, zn, 3); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_f32_x4(0, zn, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} +} + +void test_svluti4_lane_zt_x4(svuint8_t zn) __arm_streaming __arm_shared_za __arm_preserves_za { + // Test Reg Offset + svluti4_lane_zt_u16_x4(1, zn, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_u16_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} + // Test Reg Offset + svluti4_lane_zt_u32_x4(1, zn, 1); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_u32_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} + // Test Reg Offset + svluti4_lane_zt_f16_x4(1, zn, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_f16_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} + // Test Reg Offset + svluti4_lane_zt_bf16_x4(1, zn, 0); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_bf16_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} + // Test Reg Offset + svluti4_lane_zt_f32_x4(1, zn, 1); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_f32_x4(0, zn, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}} +} + +void test_svluti2_lane_zt(svuint8_t zn_u8) __arm_streaming __arm_shared_za __arm_preserves_za { + // Test Reg Offset + svluti2_lane_zt_u8(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_u8(0, zn_u8, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} + // Test Reg Offset + svluti2_lane_zt_u16(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_u16(0, zn_u8, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} + // Test Reg Offset + svluti2_lane_zt_f16(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_f16(0, zn_u8, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} + // Test Reg Offset + svluti2_lane_zt_bf16(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_bf16(0, zn_u8, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} + // Test Reg Offset + svluti2_lane_zt_u32(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_u32(0, zn_u8, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} + // Test Reg Offset + svluti2_lane_zt_f32(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_f32(0, zn_u8, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} +} + +void test_svluti4_lane_zt(svuint8_t zn_u8) __arm_streaming __arm_shared_za __arm_preserves_za { + // Test Reg Offset + svluti4_lane_zt_u8(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_u8(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti4_lane_zt_u16(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_u16(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti4_lane_zt_f16(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_f16(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti4_lane_zt_bf16(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_bf16(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti4_lane_zt_u32(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_u32(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti4_lane_zt_f32(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_f32(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} +} + +void test_svluti2_lane_zt_x2(svuint8_t zn_u8) __arm_streaming __arm_shared_za __arm_preserves_za { + // Test Reg Offset + svluti2_lane_zt_u8_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_u8_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti2_lane_zt_u16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_u16_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti2_lane_zt_u32_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_u32_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti2_lane_zt_f16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_f16_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti2_lane_zt_bf16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_bf16_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} + // Test Reg Offset + svluti2_lane_zt_f32_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti2_lane_zt_f32_x2(0, zn_u8, 8); // expected-error {{argument value 8 is outside the valid range [0, 7]}} +} + +void test_svluti4_lane_zt_x2(svuint8_t zn_u8) __arm_streaming __arm_shared_za __arm_preserves_za { + // Test Reg Offset + svluti4_lane_zt_u8_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_u8_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti4_lane_zt_u16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_u16_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti4_lane_zt_u32_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_u32_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti4_lane_zt_f16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_f16_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti4_lane_zt_bf16_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_bf16_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} + // Test Reg Offset + svluti4_lane_zt_f32_x2(1, zn_u8, 2); // expected-error {{argument value 1 is outside the valid range [0, 0]}} + // Test index value range + svluti4_lane_zt_f32_x2(0, zn_u8, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}} +} diff --git a/clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c b/clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c new file mode 100644 index 000000000000..d543e6f99952 --- /dev/null +++ b/clang/test/Sema/bpf-attr-preserve-static-offset-warns-nonbpf.c @@ -0,0 +1,6 @@ +// RUN: %clang_cc1 -fsyntax-only -verify %s + +#define __pso __attribute__((preserve_static_offset)) + +struct foo { int a; } __pso; // expected-warning{{unknown attribute}} +union quux { int a; } __pso; // expected-warning{{unknown attribute}} diff --git a/clang/test/Sema/bpf-attr-preserve-static-offset-warns.c b/clang/test/Sema/bpf-attr-preserve-static-offset-warns.c new file mode 100644 index 000000000000..1067ebe8f82b --- /dev/null +++ b/clang/test/Sema/bpf-attr-preserve-static-offset-warns.c @@ -0,0 +1,23 @@ +// RUN: %clang_cc1 -fsyntax-only -verify -triple bpf-pc-linux-gnu %s + +#define __pso __attribute__((preserve_static_offset)) + +// These are correct usages. +struct foo { int a; } __pso; +union quux { int a; } __pso; +struct doug { int a; } __pso __attribute__((packed)); + +// Rest are incorrect usages. +typedef int bar __pso; // expected-error{{attribute only applies to}} +struct goo { + int a __pso; // expected-error{{attribute only applies to}} +}; +int g __pso; // expected-error{{attribute only applies to}} +__pso void ffunc1(void); // expected-error{{attribute only applies to}} +void ffunc2(int a __pso); // expected-error{{attribute only applies to}} +void ffunc3(void) { + int a __pso; // expected-error{{attribute only applies to}} +} + +struct buz { int a; } __attribute__((preserve_static_offset("hello"))); // \ + expected-error{{attribute takes no arguments}} diff --git a/clang/test/Sema/bpf-attr-preserve-static-offset.c b/clang/test/Sema/bpf-attr-preserve-static-offset.c new file mode 100644 index 000000000000..5f53469869f3 --- /dev/null +++ b/clang/test/Sema/bpf-attr-preserve-static-offset.c @@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -fsyntax-only -ast-dump -triple bpf-pc-linux-gnu %s | FileCheck %s + +// The 'preserve_static_offset' attribute should be propagated to +// inline declarations (foo's 'b', 'bb', 'c' but not 'd'). +// +// CHECK: RecordDecl {{.*}} struct foo definition +// CHECK-NEXT: BPFPreserveStaticOffsetAttr +// CHECK-NEXT: FieldDecl {{.*}} a +// CHECK-NEXT: RecordDecl {{.*}} struct definition +// CHECK-NEXT: FieldDecl {{.*}} aa +// CHECK-NEXT: FieldDecl {{.*}} b +// CHECK-NEXT: RecordDecl {{.*}} union bar definition +// CHECK-NEXT: BPFPreserveStaticOffsetAttr +// CHECK-NEXT: FieldDecl {{.*}} a +// CHECK-NEXT: FieldDecl {{.*}} b + +struct foo { + int a; + struct { + int aa; + } b; +} __attribute__((preserve_static_offset)); + +union bar { + int a; + long b; +} __attribute__((preserve_static_offset)); diff --git a/clang/test/SemaCXX/builtin-dump-struct.cpp b/clang/test/SemaCXX/builtin-dump-struct.cpp index b3d2a2d808ce..91ffa7c8c05b 100644 --- a/clang/test/SemaCXX/builtin-dump-struct.cpp +++ b/clang/test/SemaCXX/builtin-dump-struct.cpp @@ -149,7 +149,15 @@ B { } )"[1]); +class Incomplete; // #incomplete-type + +template +class Class { + T value = {}; +}; + void errors(B b) { + ConstexprString cs; __builtin_dump_struct(); // expected-error {{too few arguments to function call, expected 2, have 0}} __builtin_dump_struct(1); // expected-error {{too few arguments to function call, expected 2, have 1}} __builtin_dump_struct(1, 2); // expected-error {{expected pointer to struct as 1st argument to '__builtin_dump_struct', found 'int'}} @@ -157,6 +165,10 @@ void errors(B b) { __builtin_dump_struct(&b, Format, 0); // expected-error {{no matching function for call to 'Format'}} // expected-note@-1 {{in call to printing function with arguments '(0, "%s", "B")' while dumping struct}} // expected-note@#Format {{no known conversion from 'int' to 'ConstexprString &' for 1st argument}} + __builtin_dump_struct((Incomplete *)nullptr, Format, cs); // expected-error {{incomplete type 'Incomplete' where a complete type is required}} + // expected-note@#incomplete-type {{forward declaration of 'Incomplete'}} + // Ensure the Class gets instantiated; otherwise crash happens. + __builtin_dump_struct((Class *)nullptr, Format, cs); } #endif diff --git a/clang/tools/clang-format/clang-format-diff.py b/clang/tools/clang-format/clang-format-diff.py index b25ee8f43375..0a2c24743678 100755 --- a/clang/tools/clang-format/clang-format-diff.py +++ b/clang/tools/clang-format/clang-format-diff.py @@ -25,7 +25,6 @@ from __future__ import absolute_import, division, print_function import argparse import difflib -import os import re import subprocess import sys @@ -37,9 +36,8 @@ else: def main(): - basename = os.path.basename(sys.argv[0]) parser = argparse.ArgumentParser( - description=__doc__.format(clang_format_diff=basename), + description=__doc__.format(clang_format_diff="%(prog)s"), formatter_class=argparse.RawDescriptionHelpFormatter, ) parser.add_argument( diff --git a/clang/tools/clang-format/git-clang-format b/clang/tools/clang-format/git-clang-format index 6e827e17b4ee..d33fd478d77f 100755 --- a/clang/tools/clang-format/git-clang-format +++ b/clang/tools/clang-format/git-clang-format @@ -132,6 +132,10 @@ def main(): help='passed to clang-format'), p.add_argument('-v', '--verbose', action='count', default=0, help='print extra information') + p.add_argument('--diff_from_common_commit', action='store_true', + help=('diff from the last common commit for commits in ' + 'separate branches rather than the exact point of the ' + 'commits')) # We gather all the remaining positional arguments into 'args' since we need # to use some heuristics to determine whether or not was present. # However, to print pretty messages, we make use of metavar and help. @@ -145,16 +149,23 @@ def main(): del opts.quiet commits, files = interpret_args(opts.args, dash_dash, opts.commit) - if len(commits) > 1: + if len(commits) > 2: + die('at most two commits allowed; %d given' % len(commits)) + if len(commits) == 2: if opts.staged: die('--staged is not allowed when two commits are given') if not opts.diff: die('--diff is required when two commits are given') - else: - if len(commits) > 2: - die('at most two commits allowed; %d given' % len(commits)) - opts.binary=os.path.abspath(opts.binary) - changed_lines = compute_diff_and_extract_lines(commits, files, opts.staged) + elif opts.diff_from_common_commit: + die('--diff_from_common_commit is only allowed when two commits are given') + + if os.path.dirname(opts.binary): + opts.binary = os.path.abspath(opts.binary) + + changed_lines = compute_diff_and_extract_lines(commits, + files, + opts.staged, + opts.diff_from_common_commit) if opts.verbose >= 1: ignored_files = set(changed_lines) filter_by_extension(changed_lines, opts.extensions.lower().split(',')) @@ -302,9 +313,9 @@ def get_object_type(value): return convert_string(stdout.strip()) -def compute_diff_and_extract_lines(commits, files, staged): +def compute_diff_and_extract_lines(commits, files, staged, diff_common_commit): """Calls compute_diff() followed by extract_lines().""" - diff_process = compute_diff(commits, files, staged) + diff_process = compute_diff(commits, files, staged, diff_common_commit) changed_lines = extract_lines(diff_process.stdout) diff_process.stdout.close() diff_process.wait() @@ -314,7 +325,7 @@ def compute_diff_and_extract_lines(commits, files, staged): return changed_lines -def compute_diff(commits, files, staged): +def compute_diff(commits, files, staged, diff_common_commit): """Return a subprocess object producing the diff from `commits`. The return value's `stdin` file object will produce a patch with the @@ -324,10 +335,13 @@ def compute_diff(commits, files, staged): Zero context lines are used in the patch.""" git_tool = 'diff-index' extra_args = [] - if len(commits) > 1: + if len(commits) == 2: git_tool = 'diff-tree' + if diff_common_commit: + commits = [f'{commits[0]}...{commits[1]}'] elif staged: extra_args += ['--cached'] + cmd = ['git', git_tool, '-p', '-U0'] + extra_args + commits + ['--'] cmd.extend(files) p = subprocess.Popen(cmd, stdin=subprocess.PIPE, stdout=subprocess.PIPE) diff --git a/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp b/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp index 3569b0eac700..003434a58b10 100644 --- a/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp @@ -25,6 +25,7 @@ namespace { using namespace clang; using namespace dataflow; using ::clang::dataflow::test::getFieldValue; +using ::testing::Contains; using ::testing::IsNull; using ::testing::NotNull; @@ -311,6 +312,57 @@ TEST_F(EnvironmentTest, InitGlobalVarsConstructor) { EXPECT_THAT(Env.getValue(*Var), NotNull()); } +// Pointers to Members are a tricky case of accessor calls, complicated further +// when using templates where the pointer to the member is a template argument. +// This is a repro of a failure case seen in the wild. +TEST_F(EnvironmentTest, + ModelMemberForAccessorUsingMethodPointerThroughTemplate) { + using namespace ast_matchers; + + std::string Code = R"cc( + struct S { + int accessor() {return member;} + + int member = 0; + }; + + template + int Target(S* S) { + return (S->*method)(); + } + + // We want to analyze the instantiation of Target for the accessor. + int Instantiator () {S S; return Target<&S::accessor>(&S); } + )cc"; + + auto Unit = + // C++17 for the simplifying use of auto in the template declaration. + tooling::buildASTFromCodeWithArgs(Code, {"-fsyntax-only", "-std=c++17"}); + auto &Context = Unit->getASTContext(); + + ASSERT_EQ(Context.getDiagnostics().getClient()->getNumErrors(), 0U); + + auto Results = match( + decl(anyOf(functionDecl(hasName("Target"), isTemplateInstantiation()) + .bind("target"), + fieldDecl(hasName("member")).bind("member"), + recordDecl(hasName("S")).bind("struct"))), + Context); + const auto *Fun = selectFirst("target", Results); + const auto *Struct = selectFirst("struct", Results); + const auto *Member = selectFirst("member", Results); + ASSERT_THAT(Fun, NotNull()); + ASSERT_THAT(Struct, NotNull()); + ASSERT_THAT(Member, NotNull()); + + // Verify that `member` is modeled for `S` when we analyze + // `Target<&S::accessor>`. + Environment Env(DAContext, *Fun); + Env.initialize(); + EXPECT_THAT(DAContext.getModeledFields(QualType(Struct->getTypeForDecl(), 0)), + Contains(Member)); +} + TEST_F(EnvironmentTest, RefreshRecordValue) { using namespace ast_matchers; diff --git a/clang/unittests/Basic/FileManagerTest.cpp b/clang/unittests/Basic/FileManagerTest.cpp index bf30fabb7cd8..43339676c4a6 100644 --- a/clang/unittests/Basic/FileManagerTest.cpp +++ b/clang/unittests/Basic/FileManagerTest.cpp @@ -284,7 +284,9 @@ TEST_F(FileManagerTest, getFileRefReturnsCorrectNameForDifferentStatPath) { ASSERT_FALSE(!F1Alias); ASSERT_FALSE(!F1Alias2); EXPECT_EQ("dir/f1.cpp", F1->getName()); + LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_PUSH EXPECT_EQ("dir/f1.cpp", F1->getFileEntry().getName()); + LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_POP EXPECT_EQ("dir/f1.cpp", F1Alias->getName()); EXPECT_EQ("dir/f1.cpp", F1Alias2->getName()); EXPECT_EQ(&F1->getFileEntry(), &F1Alias->getFileEntry()); @@ -303,7 +305,9 @@ TEST_F(FileManagerTest, getFileRefReturnsCorrectNameForDifferentStatPath) { ASSERT_FALSE(!F2Alias); ASSERT_FALSE(!F2Alias2); EXPECT_EQ("dir/f2.cpp", F2->getName()); + LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_PUSH EXPECT_EQ("dir/f2.cpp", F2->getFileEntry().getName()); + LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_POP EXPECT_EQ("dir/f2.cpp", F2Alias->getName()); EXPECT_EQ("dir/f2.cpp", F2Alias2->getName()); EXPECT_EQ(&F2->getFileEntry(), &F2Alias->getFileEntry()); diff --git a/clang/unittests/Format/ObjCPropertyAttributeOrderFixerTest.cpp b/clang/unittests/Format/ObjCPropertyAttributeOrderFixerTest.cpp index 109eaa785ca5..79ded6673591 100644 --- a/clang/unittests/Format/ObjCPropertyAttributeOrderFixerTest.cpp +++ b/clang/unittests/Format/ObjCPropertyAttributeOrderFixerTest.cpp @@ -171,18 +171,18 @@ TEST_F(ObjCPropertyAttributeOrderFixerTest, HandlesDuplicatedAttributes) { Style.ObjCPropertyAttributeOrder = {"a", "b", "c"}; // Just a dup and nothing else. - verifyFormat("@property(a, a) int p;", Style); + verifyFormat("@property(a) int p;", "@property(a, a) int p;", Style); // A dup and something else. - verifyFormat("@property(a, a, b) int p;", "@property(a, b, a) int p;", Style); + verifyFormat("@property(a, b) int p;", "@property(a, b, a) int p;", Style); - // Duplicates using `=`: stable-sort irrespective of their value. - verifyFormat("@property(a=A, a=A, b=X, b=Y) int p;", + // Duplicates using `=`. + verifyFormat("@property(a=A, b=X) int p;", "@property(a=A, b=X, a=A, b=Y) int p;", Style); - verifyFormat("@property(a=A, a=A, b=Y, b=X) int p;", + verifyFormat("@property(a=A, b=Y) int p;", "@property(a=A, b=Y, a=A, b=X) int p;", Style); - verifyFormat("@property(a, a=A, b=B, b) int p;", - "@property(a, b=B, a=A, b) int p;", Style); + verifyFormat("@property(a, b=B) int p;", "@property(a, b=B, a=A, b) int p;", + Style); } TEST_F(ObjCPropertyAttributeOrderFixerTest, SortsInPPDirective) { @@ -200,7 +200,7 @@ TEST_F(ObjCPropertyAttributeOrderFixerTest, SortsInPPDirective) { } TEST_F(ObjCPropertyAttributeOrderFixerTest, HandlesAllAttributes) { - // 'class' is the only attribute that is a keyword, so make sure it works too. + // `class` is the only attribute that is a keyword, so make sure it works too. FormatStyle Style = getLLVMStyle(); Style.Language = FormatStyle::LK_ObjC; Style.ObjCPropertyAttributeOrder = {"FIRST", @@ -282,7 +282,7 @@ TEST_F(ObjCPropertyAttributeOrderFixerTest, HandlesAllAttributes) { verifyFormat("@property(FIRST, null_resettable, LAST) int p;", Style); verifyFormat("@property(FIRST, null_unspecified, LAST) int p;", Style); - // Reorder: put 'FIRST' and/or 'LAST' in the wrong spot. + // Reorder: put `FIRST` and/or `LAST` in the wrong spot. verifyFormat("@property(class, LAST) int p;", "@property(LAST, class) int p;", Style); verifyFormat("@property(direct, LAST) int p;", diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp index b380bd9dfe66..b8a1fb4bab0f 100644 --- a/clang/utils/TableGen/SveEmitter.cpp +++ b/clang/utils/TableGen/SveEmitter.cpp @@ -744,6 +744,12 @@ void SVEType::applyModifier(char Mod) { BFloat = false; ElementBitwidth = 64; break; + case '[': + Signed = false; + Float = false; + BFloat = false; + ElementBitwidth = 8; + break; case 't': Signed = true; Float = false; diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index 4d918224ded4..aafed2b6869e 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -3243,7 +3243,7 @@ of class templates 534 CD1 template-names and operator-function-ids - Yes + Clang 2.9 535 @@ -3299,7 +3299,7 @@ and POD class 543 CD1 Value initialization and default constructors - Yes + Clang 3.0 544 @@ -3323,7 +3323,7 @@ and POD class 547 C++11 Partial specialization on member function types - Yes + Clang 3.2 548 @@ -3383,13 +3383,13 @@ and POD class 557 CD1 Does argument-dependent lookup cause template instantiation? - Yes + Clang 3.1 558 CD1 Excluded characters in universal character names - Yes + Clang 2.9 559 @@ -3449,7 +3449,7 @@ and POD class 568 CD1 Definition of POD is too strict - Yes (C++11 onwards) + Clang 3.0 (C++11 onwards) 569 @@ -3485,7 +3485,7 @@ and POD class 574 NAD Definition of “copy assignment operator” - Yes + Clang 3.0 575 @@ -3497,13 +3497,13 @@ and POD class 576 CD2 Typedefs in function definitions - Yes + Clang 3.5 577 CD3 void in an empty parameter list - Yes + Clang 3.5 578 @@ -3551,7 +3551,7 @@ and POD class 585 NAD Friend template template parameters - Yes + Clang 3.0 586 @@ -3563,7 +3563,7 @@ and POD class 587 CD2 Lvalue operands of a conditional expression differing only in cv-qualification - Yes + Clang 3.2 588 @@ -3641,7 +3641,7 @@ and POD class 600 CD6 Does access control apply to members or to names? - Yes + Clang 2.8 601 @@ -3677,7 +3677,7 @@ and POD class 606 CD1 Template argument deduction for rvalue references - Yes + Clang 3.0 607 @@ -3815,7 +3815,7 @@ and POD class 629 CD1 auto parsing ambiguity - Yes + Clang 2.9 630 @@ -3875,7 +3875,7 @@ and POD class 639 CD1 What makes side effects “different” from one another? - Yes + Clang 3.3 640 @@ -3899,7 +3899,7 @@ and POD class 643 NAD Use of decltype in a class member-specification - Yes + Clang 3.2 644 @@ -3923,7 +3923,7 @@ and POD class 647 CD1 Non-constexpr instances of constexpr constructor templates - Yes + Clang 3.1 648 @@ -3935,7 +3935,7 @@ and POD class 649 CD1 Optionally ill-formed extended alignment requests - Yes + Clang 3.5 650 @@ -3995,13 +3995,13 @@ and POD class 659 CD1 Alignment of function types - Yes + Clang 3.0 660 CD1 Unnamed scoped enumerations - Yes + Clang 3.0 661 @@ -4031,19 +4031,19 @@ and POD class 665 CD2 Problems in the specification of dynamic_cast - Yes + Clang 2.8 666 CD1 Dependent qualified-ids without the typename keyword - Yes + Clang 2.8 667 CD2 Trivial special member functions that cannot be implicitly defined - Yes + Clang 8 668 @@ -4067,7 +4067,7 @@ and POD class 671 CD1 Explicit conversion from a scoped enumeration type to integral type - Yes + Clang 2.9 672 @@ -4157,7 +4157,7 @@ and POD class 686 CD1 Type declarations/definitions in type-specifier-seqs and type-ids - Yes + Clang 3.0 687 @@ -4217,7 +4217,7 @@ and POD class 696 C++11 Use of block-scope constants in local classes - Yes + Clang 3.1 697 diff --git a/compiler-rt/CMakeLists.txt b/compiler-rt/CMakeLists.txt index 1a46f5b33480..bbb4e8d7c333 100644 --- a/compiler-rt/CMakeLists.txt +++ b/compiler-rt/CMakeLists.txt @@ -678,9 +678,24 @@ endif() append_list_if(COMPILER_RT_DEBUG -DSANITIZER_DEBUG=1 COMPILER_RT_UNITTEST_CFLAGS) append_list_if(COMPILER_RT_HAS_WCOVERED_SWITCH_DEFAULT_FLAG -Wno-covered-switch-default COMPILER_RT_UNITTEST_CFLAGS) append_list_if(COMPILER_RT_HAS_WSUGGEST_OVERRIDE_FLAG -Wno-suggest-override COMPILER_RT_UNITTEST_CFLAGS) - -if(MSVC) - # gtest use a lot of stuff marked as deprecated on Windows. +# Detect if the compiler toolchain includes gcc-toolset-12. +if ("${CMAKE_CXX_COMPILER_ID}" MATCHES "Clang" OR + "${CMAKE_CXX_COMPILER_ID}" MATCHES "GNU") + execute_process(COMMAND ${CMAKE_CXX_COMPILER} -v + RESULT_VARIABLE compiler_info_rc + OUTPUT_VARIABLE compiler_info + ERROR_VARIABLE compiler_info) + if(compiler_info MATCHES ".*gcc-toolset-12.*") + set(USING_GCC_TOOLSET_12 TRUE) + endif() +endif() +if(MSVC OR (LINUX AND DEFINED USING_GCC_TOOLSET_12 AND + CMAKE_CXX_STANDARD EQUAL 17)) + # gtest use a lot of stuff marked as deprecated on Windows or if using + # gcc-toolset-12 in the compiler toolchain on Linux; all of the + # deprecated declarations in gcc-toolset-12 used in Google Tests have been + # observed to be _GLIBCXX17_DEPRECATED and should go away once + # CMAKE_CXX_STANDARD is greater than 17. list(APPEND COMPILER_RT_GTEST_CFLAGS -Wno-deprecated-declarations) endif() diff --git a/compiler-rt/lib/asan/asan_interceptors.cpp b/compiler-rt/lib/asan/asan_interceptors.cpp index e80f66142b7a..4de2fa356374 100644 --- a/compiler-rt/lib/asan/asan_interceptors.cpp +++ b/compiler-rt/lib/asan/asan_interceptors.cpp @@ -96,14 +96,16 @@ DECLARE_REAL_AND_INTERCEPTOR(void, free, void *) ASAN_WRITE_RANGE(ctx, ptr, size) #define COMMON_INTERCEPTOR_READ_RANGE(ctx, ptr, size) \ ASAN_READ_RANGE(ctx, ptr, size) -# define COMMON_INTERCEPTOR_ENTER(ctx, func, ...) \ - ASAN_INTERCEPTOR_ENTER(ctx, func); \ - do { \ - if (AsanInitIsRunning()) \ - return REAL(func)(__VA_ARGS__); \ - if (SANITIZER_APPLE && UNLIKELY(!AsanInited())) \ - return REAL(func)(__VA_ARGS__); \ - ENSURE_ASAN_INITED(); \ +# define COMMON_INTERCEPTOR_ENTER(ctx, func, ...) \ + ASAN_INTERCEPTOR_ENTER(ctx, func); \ + do { \ + if constexpr (SANITIZER_APPLE) { \ + if (UNLIKELY(!AsanInited())) \ + return REAL(func)(__VA_ARGS__); \ + } else { \ + if (!TryAsanInitFromRtl()) \ + return REAL(func)(__VA_ARGS__); \ + } \ } while (false) #define COMMON_INTERCEPTOR_DIR_ACQUIRE(ctx, path) \ do { \ @@ -194,7 +196,10 @@ static int munmap_interceptor(Munmap real_munmap, void *addr, SIZE_T length) { __lsan::ScopedInterceptorDisabler disabler #endif -# define SIGNAL_INTERCEPTOR_ENTER() ENSURE_ASAN_INITED() +# define SIGNAL_INTERCEPTOR_ENTER() \ + do { \ + AsanInitFromRtl(); \ + } while (false) # include "sanitizer_common/sanitizer_common_interceptors.inc" # include "sanitizer_common/sanitizer_signal_interceptors.inc" @@ -494,7 +499,7 @@ DEFINE_REAL(char*, index, const char *string, int c) INTERCEPTOR(char *, strcat, char *to, const char *from) { void *ctx; ASAN_INTERCEPTOR_ENTER(ctx, strcat); - ENSURE_ASAN_INITED(); + AsanInitFromRtl(); if (flags()->replace_str) { uptr from_length = internal_strlen(from); ASAN_READ_RANGE(ctx, from, from_length + 1); @@ -515,7 +520,7 @@ DEFINE_REAL(char*, index, const char *string, int c) INTERCEPTOR(char*, strncat, char *to, const char *from, uptr size) { void *ctx; ASAN_INTERCEPTOR_ENTER(ctx, strncat); - ENSURE_ASAN_INITED(); + AsanInitFromRtl(); if (flags()->replace_str) { uptr from_length = MaybeRealStrnlen(from, size); uptr copy_length = Min(size, from_length + 1); @@ -534,16 +539,16 @@ INTERCEPTOR(char*, strncat, char *to, const char *from, uptr size) { INTERCEPTOR(char *, strcpy, char *to, const char *from) { void *ctx; ASAN_INTERCEPTOR_ENTER(ctx, strcpy); -#if SANITIZER_APPLE - if (UNLIKELY(!AsanInited())) - return REAL(strcpy)(to, from); -#endif - // strcpy is called from malloc_default_purgeable_zone() - // in __asan::ReplaceSystemAlloc() on Mac. - if (AsanInitIsRunning()) { - return REAL(strcpy)(to, from); + if constexpr (SANITIZER_APPLE) { + // strcpy is called from malloc_default_purgeable_zone() + // in __asan::ReplaceSystemAlloc() on Mac. + if (UNLIKELY(!AsanInited())) + return REAL(strcpy)(to, from); + } else { + if (!TryAsanInitFromRtl()) + return REAL(strcpy)(to, from); } - ENSURE_ASAN_INITED(); + if (flags()->replace_str) { uptr from_size = internal_strlen(from) + 1; CHECK_RANGES_OVERLAP("strcpy", to, from_size, from, from_size); @@ -556,9 +561,8 @@ INTERCEPTOR(char *, strcpy, char *to, const char *from) { INTERCEPTOR(char*, strdup, const char *s) { void *ctx; ASAN_INTERCEPTOR_ENTER(ctx, strdup); - if (UNLIKELY(!AsanInited())) + if (UNLIKELY(!TryAsanInitFromRtl())) return internal_strdup(s); - ENSURE_ASAN_INITED(); uptr length = internal_strlen(s); if (flags()->replace_str) { ASAN_READ_RANGE(ctx, s, length + 1); @@ -575,9 +579,8 @@ INTERCEPTOR(char*, strdup, const char *s) { INTERCEPTOR(char*, __strdup, const char *s) { void *ctx; ASAN_INTERCEPTOR_ENTER(ctx, strdup); - if (UNLIKELY(!AsanInited())) + if (UNLIKELY(!TryAsanInitFromRtl())) return internal_strdup(s); - ENSURE_ASAN_INITED(); uptr length = internal_strlen(s); if (flags()->replace_str) { ASAN_READ_RANGE(ctx, s, length + 1); @@ -594,7 +597,7 @@ INTERCEPTOR(char*, __strdup, const char *s) { INTERCEPTOR(char*, strncpy, char *to, const char *from, uptr size) { void *ctx; ASAN_INTERCEPTOR_ENTER(ctx, strncpy); - ENSURE_ASAN_INITED(); + AsanInitFromRtl(); if (flags()->replace_str) { uptr from_size = Min(size, MaybeRealStrnlen(from, size) + 1); CHECK_RANGES_OVERLAP("strncpy", to, from_size, from, from_size); @@ -620,7 +623,7 @@ static ALWAYS_INLINE auto StrtolImpl(void *ctx, Fn real, const char *nptr, INTERCEPTOR(ret_type, func, const char *nptr, char **endptr, int base) { \ void *ctx; \ ASAN_INTERCEPTOR_ENTER(ctx, func); \ - ENSURE_ASAN_INITED(); \ + AsanInitFromRtl(); \ return StrtolImpl(ctx, REAL(func), nptr, endptr, base); \ } @@ -635,11 +638,9 @@ INTERCEPTOR_STRTO_BASE(long long, __isoc23_strtoll) INTERCEPTOR(int, atoi, const char *nptr) { void *ctx; ASAN_INTERCEPTOR_ENTER(ctx, atoi); -#if SANITIZER_APPLE - if (UNLIKELY(!AsanInited())) + if (SANITIZER_APPLE && UNLIKELY(!AsanInited())) return REAL(atoi)(nptr); -# endif - ENSURE_ASAN_INITED(); + AsanInitFromRtl(); if (!flags()->replace_str) { return REAL(atoi)(nptr); } @@ -657,11 +658,9 @@ INTERCEPTOR(int, atoi, const char *nptr) { INTERCEPTOR(long, atol, const char *nptr) { void *ctx; ASAN_INTERCEPTOR_ENTER(ctx, atol); -#if SANITIZER_APPLE - if (UNLIKELY(!AsanInited())) + if (SANITIZER_APPLE && UNLIKELY(!AsanInited())) return REAL(atol)(nptr); -# endif - ENSURE_ASAN_INITED(); + AsanInitFromRtl(); if (!flags()->replace_str) { return REAL(atol)(nptr); } @@ -675,7 +674,7 @@ INTERCEPTOR(long, atol, const char *nptr) { INTERCEPTOR(long long, atoll, const char *nptr) { void *ctx; ASAN_INTERCEPTOR_ENTER(ctx, atoll); - ENSURE_ASAN_INITED(); + AsanInitFromRtl(); if (!flags()->replace_str) { return REAL(atoll)(nptr); } @@ -696,12 +695,10 @@ static void AtCxaAtexit(void *unused) { #if ASAN_INTERCEPT___CXA_ATEXIT INTERCEPTOR(int, __cxa_atexit, void (*func)(void *), void *arg, void *dso_handle) { -#if SANITIZER_APPLE - if (UNLIKELY(!AsanInited())) + if (SANITIZER_APPLE && UNLIKELY(!AsanInited())) return REAL(__cxa_atexit)(func, arg, dso_handle); -# endif - ENSURE_ASAN_INITED(); -#if CAN_SANITIZE_LEAKS + AsanInitFromRtl(); +# if CAN_SANITIZE_LEAKS __lsan::ScopedInterceptorDisabler disabler; #endif int res = REAL(__cxa_atexit)(func, arg, dso_handle); @@ -712,8 +709,8 @@ INTERCEPTOR(int, __cxa_atexit, void (*func)(void *), void *arg, #if ASAN_INTERCEPT_ATEXIT INTERCEPTOR(int, atexit, void (*func)()) { - ENSURE_ASAN_INITED(); -#if CAN_SANITIZE_LEAKS + AsanInitFromRtl(); +# if CAN_SANITIZE_LEAKS __lsan::ScopedInterceptorDisabler disabler; #endif // Avoid calling real atexit as it is unreachable on at least on Linux. diff --git a/compiler-rt/lib/asan/asan_interceptors.h b/compiler-rt/lib/asan/asan_interceptors.h index e355c1258a9f..826b45f5ada8 100644 --- a/compiler-rt/lib/asan/asan_interceptors.h +++ b/compiler-rt/lib/asan/asan_interceptors.h @@ -24,14 +24,6 @@ namespace __asan { void InitializeAsanInterceptors(); void InitializePlatformInterceptors(); -#define ENSURE_ASAN_INITED() \ - do { \ - CHECK(!AsanInitIsRunning()); \ - if (UNLIKELY(!AsanInited())) { \ - AsanInitFromRtl(); \ - } \ - } while (0) - } // namespace __asan // There is no general interception at all on Fuchsia. diff --git a/compiler-rt/lib/asan/asan_internal.h b/compiler-rt/lib/asan/asan_internal.h index e2b1e9800f5b..5b97e77882cd 100644 --- a/compiler-rt/lib/asan/asan_internal.h +++ b/compiler-rt/lib/asan/asan_internal.h @@ -60,6 +60,7 @@ class AsanThread; using __sanitizer::StackTrace; void AsanInitFromRtl(); +bool TryAsanInitFromRtl(); // asan_win.cpp void InitializePlatformExceptionHandlers(); @@ -131,7 +132,6 @@ void InstallAtExitCheckLeaks(); __asan_on_error() bool AsanInited(); -bool AsanInitIsRunning(); // Used to avoid infinite recursion in __asan_init(). extern bool replace_intrin_cached; extern void (*death_callback)(void); // These magic values are written to shadow for better error diff --git a/compiler-rt/lib/asan/asan_lock.h b/compiler-rt/lib/asan/asan_lock.h deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/compiler-rt/lib/asan/asan_malloc_linux.cpp b/compiler-rt/lib/asan/asan_malloc_linux.cpp index 0ba74c5d7143..d426b923c94e 100644 --- a/compiler-rt/lib/asan/asan_malloc_linux.cpp +++ b/compiler-rt/lib/asan/asan_malloc_linux.cpp @@ -31,7 +31,7 @@ using namespace __asan; struct DlsymAlloc : public DlSymAllocator { - static bool UseImpl() { return AsanInitIsRunning(); } + static bool UseImpl() { return !TryAsanInitFromRtl(); } static void OnAllocate(const void *ptr, uptr size) { # if CAN_SANITIZE_LEAKS // Suppress leaks from dlerror(). Previously dlsym hack on global array was @@ -65,7 +65,6 @@ INTERCEPTOR(void, cfree, void *ptr) { INTERCEPTOR(void*, malloc, uptr size) { if (DlsymAlloc::Use()) return DlsymAlloc::Allocate(size); - ENSURE_ASAN_INITED(); GET_STACK_TRACE_MALLOC; return asan_malloc(size, &stack); } @@ -73,7 +72,6 @@ INTERCEPTOR(void*, malloc, uptr size) { INTERCEPTOR(void*, calloc, uptr nmemb, uptr size) { if (DlsymAlloc::Use()) return DlsymAlloc::Callocate(nmemb, size); - ENSURE_ASAN_INITED(); GET_STACK_TRACE_MALLOC; return asan_calloc(nmemb, size, &stack); } @@ -81,14 +79,13 @@ INTERCEPTOR(void*, calloc, uptr nmemb, uptr size) { INTERCEPTOR(void*, realloc, void *ptr, uptr size) { if (DlsymAlloc::Use() || DlsymAlloc::PointerIsMine(ptr)) return DlsymAlloc::Realloc(ptr, size); - ENSURE_ASAN_INITED(); GET_STACK_TRACE_MALLOC; return asan_realloc(ptr, size, &stack); } #if SANITIZER_INTERCEPT_REALLOCARRAY INTERCEPTOR(void*, reallocarray, void *ptr, uptr nmemb, uptr size) { - ENSURE_ASAN_INITED(); + AsanInitFromRtl(); GET_STACK_TRACE_MALLOC; return asan_reallocarray(ptr, nmemb, size, &stack); } diff --git a/compiler-rt/lib/asan/asan_malloc_mac.cpp b/compiler-rt/lib/asan/asan_malloc_mac.cpp index d2380ee62bf3..f25d7e190153 100644 --- a/compiler-rt/lib/asan/asan_malloc_mac.cpp +++ b/compiler-rt/lib/asan/asan_malloc_mac.cpp @@ -22,7 +22,10 @@ using namespace __asan; #define COMMON_MALLOC_ZONE_NAME "asan" -#define COMMON_MALLOC_ENTER() ENSURE_ASAN_INITED() +# define COMMON_MALLOC_ENTER() \ + do { \ + AsanInitFromRtl(); \ + } while (false) # define COMMON_MALLOC_SANITIZER_INITIALIZED AsanInited() # define COMMON_MALLOC_FORCE_LOCK() asan_mz_force_lock() # define COMMON_MALLOC_FORCE_UNLOCK() asan_mz_force_unlock() diff --git a/compiler-rt/lib/asan/asan_rtl.cpp b/compiler-rt/lib/asan/asan_rtl.cpp index d8bd19d8b79d..04ecd20821fa 100644 --- a/compiler-rt/lib/asan/asan_rtl.cpp +++ b/compiler-rt/lib/asan/asan_rtl.cpp @@ -74,13 +74,13 @@ static void CheckUnwind() { static int asan_inited = 0; static int asan_init_is_running = 0; -static void SetAsanInited(u32 val) { asan_inited = val; } +static void SetAsanInited() { asan_inited = 1; } static void SetAsanInitIsRunning(u32 val) { asan_init_is_running = val; } bool AsanInited() { return asan_inited == 1; } -bool AsanInitIsRunning() { return asan_init_is_running == 1; } +static bool AsanInitIsRunning() { return asan_init_is_running == 1; } bool replace_intrin_cached; @@ -470,7 +470,7 @@ static void AsanInitInternal() { // On Linux AsanThread::ThreadStart() calls malloc() that's why asan_inited // should be set to 1 prior to initializing the threads. replace_intrin_cached = flags()->replace_intrin; - SetAsanInited(1); + SetAsanInited(); SetAsanInitIsRunning(0); if (flags()->atexit) @@ -520,7 +520,17 @@ static void AsanInitInternal() { // Initialize as requested from some part of ASan runtime library (interceptors, // allocator, etc). void AsanInitFromRtl() { - AsanInitInternal(); + CHECK(!AsanInitIsRunning()); + if (UNLIKELY(!AsanInited())) + AsanInitInternal(); +} + +bool TryAsanInitFromRtl() { + if (UNLIKELY(AsanInitIsRunning())) + return false; + if (UNLIKELY(!AsanInited())) + AsanInitInternal(); + return true; } #if ASAN_DYNAMIC diff --git a/compiler-rt/lib/hwasan/hwasan_interceptors.cpp b/compiler-rt/lib/hwasan/hwasan_interceptors.cpp index 46c08f8268c0..96df4dd0c24d 100644 --- a/compiler-rt/lib/hwasan/hwasan_interceptors.cpp +++ b/compiler-rt/lib/hwasan/hwasan_interceptors.cpp @@ -36,10 +36,10 @@ struct HWAsanInterceptorContext { const char *interceptor_name; }; -# define ACCESS_MEMORY_RANGE(offset, size, access) \ - do { \ - __hwasan::CheckAddressSized((uptr)offset, \ - size); \ +# define ACCESS_MEMORY_RANGE(offset, size, access) \ + do { \ + __hwasan::CheckAddressSized((uptr)offset, \ + size); \ } while (0) # define HWASAN_READ_RANGE(offset, size) \ @@ -74,9 +74,8 @@ struct HWAsanInterceptorContext { # if HWASAN_WITH_INTERCEPTORS -# define COMMON_SYSCALL_PRE_READ_RANGE(p, s) __hwasan_loadN((uptr)p, (uptr)s) -# define COMMON_SYSCALL_PRE_WRITE_RANGE(p, s) \ - __hwasan_storeN((uptr)p, (uptr)s) +# define COMMON_SYSCALL_PRE_READ_RANGE(p, s) HWASAN_READ_RANGE(p, s) +# define COMMON_SYSCALL_PRE_WRITE_RANGE(p, s) HWASAN_WRITE_RANGE(p, s) # define COMMON_SYSCALL_POST_READ_RANGE(p, s) \ do { \ (void)(p); \ diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc index 607ecae6808b..ba4670751697 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc @@ -6327,7 +6327,7 @@ INTERCEPTOR(void*, dlopen, const char *filename, int flag) { VPrintf(1, "dlopen interceptor: DladdrSelfFName: %p %s\n", (void *)SelfFName, SelfFName); - if (internal_strcmp(SelfFName, filename) == 0) { + if (SelfFName && internal_strcmp(SelfFName, filename) == 0) { // It's possible they copied the string from dladdr, so // we do a string comparison rather than pointer comparison. VPrintf(1, "dlopen interceptor: replacing %s because it matches %s\n", diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_openbsd.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_openbsd.cpp deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_openbsd.h b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_openbsd.h deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/compiler-rt/lib/scudo/standalone/combined.h b/compiler-rt/lib/scudo/standalone/combined.h index 72e5caa026e4..25ad11dbf7ee 100644 --- a/compiler-rt/lib/scudo/standalone/combined.h +++ b/compiler-rt/lib/scudo/standalone/combined.h @@ -522,6 +522,9 @@ public: NOINLINE void deallocate(void *Ptr, Chunk::Origin Origin, uptr DeleteSize = 0, UNUSED uptr Alignment = MinAlignment) { + if (UNLIKELY(!Ptr)) + return; + // For a deallocation, we only ensure minimal initialization, meaning thread // local data will be left uninitialized for now (when using ELF TLS). The // fallback cache will be used instead. This is a workaround for a situation @@ -530,9 +533,6 @@ public: // being destroyed properly. Any other heap operation will do a full init. initThreadMaybe(/*MinimalInit=*/true); - if (UNLIKELY(!Ptr)) - return; - #ifdef GWP_ASAN_HOOKS if (UNLIKELY(GuardedAlloc.pointerIsMine(Ptr))) { GuardedAlloc.deallocate(Ptr); diff --git a/compiler-rt/lib/scudo/standalone/include/scudo/interface.h b/compiler-rt/lib/scudo/standalone/include/scudo/interface.h index 260f1a7bd84b..a664b9825f20 100644 --- a/compiler-rt/lib/scudo/standalone/include/scudo/interface.h +++ b/compiler-rt/lib/scudo/standalone/include/scudo/interface.h @@ -72,7 +72,8 @@ typedef void (*iterate_callback)(uintptr_t base, size_t size, void *arg); // pointer. void __scudo_get_error_info(struct scudo_error_info *error_info, uintptr_t fault_addr, const char *stack_depot, - const char *region_info, const char *ring_buffer, + size_t stack_depot_size, const char *region_info, + const char *ring_buffer, size_t ring_buffer_size, const char *memory, const char *memory_tags, uintptr_t memory_addr, size_t memory_size); diff --git a/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp b/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp index 4fed44779b90..f203615ab360 100644 --- a/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp +++ b/compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp @@ -38,12 +38,13 @@ static scudo::Allocator // TODO(kostyak): support both allocators. INTERFACE void __scudo_print_stats(void) { Allocator.printStats(); } -INTERFACE void -__scudo_get_error_info(struct scudo_error_info *error_info, - uintptr_t fault_addr, const char *stack_depot, - const char *region_info, const char *ring_buffer, - const char *memory, const char *memory_tags, - uintptr_t memory_addr, size_t memory_size) { +INTERFACE void __scudo_get_error_info( + struct scudo_error_info *error_info, uintptr_t fault_addr, + const char *stack_depot, size_t stack_depot_size, const char *region_info, + const char *ring_buffer, size_t ring_buffer_size, const char *memory, + const char *memory_tags, uintptr_t memory_addr, size_t memory_size) { + (void)(stack_depot_size); + (void)(ring_buffer_size); Allocator.getErrorInfo(error_info, fault_addr, stack_depot, region_info, ring_buffer, memory, memory_tags, memory_addr, memory_size); diff --git a/compiler-rt/test/hwasan/TestCases/Linux/syscalls.cpp b/compiler-rt/test/hwasan/TestCases/Linux/syscalls.cpp index d7bc34ef324f..154b69898993 100644 --- a/compiler-rt/test/hwasan/TestCases/Linux/syscalls.cpp +++ b/compiler-rt/test/hwasan/TestCases/Linux/syscalls.cpp @@ -1,5 +1,6 @@ -// RUN: %clangxx_hwasan -O0 %s -o %t && not %env_hwasan_opts=symbolize=0 %run %t 2>&1 | FileCheck %s -// RUN: %clangxx_hwasan -O3 %s -o %t && not %env_hwasan_opts=symbolize=0 %run %t 2>&1 | FileCheck %s +// RUN: %clangxx_hwasan -O0 %s -o %t && not %env_hwasan_opts=symbolize=0 %run %t 2>&1 | FileCheck %s --implicit-check-not=RETURN_FROM_TEST +// RUN: %clangxx_hwasan -O3 %s -o %t && not %env_hwasan_opts=symbolize=0 %run %t 2>&1 | FileCheck %s --implicit-check-not=RETURN_FROM_TEST +// RUN: %clangxx_hwasan -O0 %s -o %t && not %env_hwasan_opts=halt_on_error=0:symbolize=0 %run %t 2>&1 | FileCheck %s --implicit-check-not=RETURN_FROM_TEST --check-prefixes=CHECK,RECOVER // UNSUPPORTED: android @@ -29,5 +30,7 @@ int main(int argc, char *argv[]) { // CHECK: [[PTR]] is located 1 bytes before a 1000-byte region free(buf); + fprintf(stderr, "RETURN_FROM_TEST\n"); + // RECOVER: RETURN_FROM_TEST return 0; } diff --git a/compiler-rt/test/hwasan/TestCases/memset-recover.cpp b/compiler-rt/test/hwasan/TestCases/memset-recover.cpp new file mode 100644 index 000000000000..093a0179347b --- /dev/null +++ b/compiler-rt/test/hwasan/TestCases/memset-recover.cpp @@ -0,0 +1,32 @@ +// RUN: %clangxx_hwasan %s -o %t +// RUN: %env_hwasan_opts=halt_on_error=0 not %run %t 2>&1 | FileCheck %s --implicit-check-not=RETURN_FROM_TEST --check-prefixes=CHECK,RECOVER +// RUN: %env_hwasan_opts=halt_on_error=1 not %run %t 2>&1 | FileCheck %s --implicit-check-not=RETURN_FROM_TEST + +#include +#include +#include +#include +#include + +__attribute__((no_sanitize("hwaddress"))) void +ForceCallInterceptor(void *p, int c, size_t size) { + memset(p, c, size) == nullptr; +} + +int main(int argc, char **argv) { + __hwasan_enable_allocator_tagging(); + char a[] = {static_cast(argc), 2, 3, 4}; + int size = sizeof(a); + char *volatile p = (char *)malloc(size); + void *volatile p2 = p; + for (int i = 0; p2 == p; p2 = __hwasan_tag_pointer(p, ++i)) { + } + ForceCallInterceptor(p2, 0, size); + free(p); + fprintf(stderr, "RETURN_FROM_TEST\n"); + return 0; + // CHECK: HWAddressSanitizer: tag-mismatch on address + // CHECK: WRITE of size 4 + // CHECK: #{{[[:digit:]]+}} 0x{{[[:xdigit:]]+}} in main {{.*}}memset-recover.cpp:[[@LINE-28]] + // RECOVER: RETURN_FROM_TEST +} diff --git a/compiler-rt/test/orc/TestCases/Darwin/x86-64/jit-re-dlopen-data-reset.S b/compiler-rt/test/orc/TestCases/Darwin/x86-64/jit-re-dlopen-data-reset.S index 8582c9ecad75..6b8e17ded7af 100644 --- a/compiler-rt/test/orc/TestCases/Darwin/x86-64/jit-re-dlopen-data-reset.S +++ b/compiler-rt/test/orc/TestCases/Darwin/x86-64/jit-re-dlopen-data-reset.S @@ -3,8 +3,8 @@ // RUN: %clang -c -o %t.main.o %p/Inputs/dlopen-dlclose-x2.S // RUN: %clang -c -o %t.inits.o %s // RUN: %llvm_jitlink \ -// RUN: -alias _dlopen=___orc_rt_macho_jit_dlopen \ -// RUN: -alias _dlclose=___orc_rt_macho_jit_dlclose \ +// RUN: -alias Platform:_dlopen=___orc_rt_macho_jit_dlopen \ +// RUN: -alias Platform:_dlclose=___orc_rt_macho_jit_dlclose \ // RUN: %t.main.o -jd inits %t.inits.o -lmain | FileCheck %s // CHECK: entering main diff --git a/compiler-rt/test/orc/TestCases/Darwin/x86-64/jit-re-dlopen-trivial.S b/compiler-rt/test/orc/TestCases/Darwin/x86-64/jit-re-dlopen-trivial.S index e8f48cac9c97..adc63f9e5c4b 100644 --- a/compiler-rt/test/orc/TestCases/Darwin/x86-64/jit-re-dlopen-trivial.S +++ b/compiler-rt/test/orc/TestCases/Darwin/x86-64/jit-re-dlopen-trivial.S @@ -7,8 +7,8 @@ // RUN: %clang -c -o %t.main.o %p/Inputs/dlopen-dlclose-x2.S // RUN: %clang -c -o %t.inits.o %s // RUN: %llvm_jitlink \ -// RUN: -alias _dlopen=___orc_rt_macho_jit_dlopen \ -// RUN: -alias _dlclose=___orc_rt_macho_jit_dlclose \ +// RUN: -alias Platform:_dlopen=___orc_rt_macho_jit_dlopen \ +// RUN: -alias Platform:_dlclose=___orc_rt_macho_jit_dlclose \ // RUN: %t.main.o -jd inits %t.inits.o -lmain | FileCheck %s // CHECK: entering main diff --git a/compiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-jit-dlopen-nested.c b/compiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-jit-dlopen-nested.c index 49d9fb6f37cd..f4b49b2c852a 100644 --- a/compiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-jit-dlopen-nested.c +++ b/compiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-jit-dlopen-nested.c @@ -5,8 +5,8 @@ // RUN: %clang -c -o %t.inits.o %p/Inputs/standalone-ctor-and-cxa-atexit-dtor.S // RUN: %clang -c -o %t.test.o %s // RUN: %llvm_jitlink \ -// RUN: -alias _dlopen=___orc_rt_macho_jit_dlopen \ -// RUN: -alias _dlclose=___orc_rt_macho_jit_dlclose \ +// RUN: -alias Platform:_dlopen=___orc_rt_macho_jit_dlopen \ +// RUN: -alias Platform:_dlclose=___orc_rt_macho_jit_dlclose \ // RUN: %t.test.o -jd inits %t.inits.o -lmain | FileCheck %s // CHECK: entering main diff --git a/compiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-jit-dlopen.c b/compiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-jit-dlopen.c index ee9b9890934c..a0007be97723 100644 --- a/compiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-jit-dlopen.c +++ b/compiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-jit-dlopen.c @@ -5,8 +5,8 @@ // RUN: %clang -c -o %t.inits.o %p/Inputs/standalone-ctor-and-cxa-atexit-dtor.S // RUN: %clang -c -o %t.test.o %s // RUN: %llvm_jitlink \ -// RUN: -alias _dlopen=___orc_rt_macho_jit_dlopen \ -// RUN: -alias _dlclose=___orc_rt_macho_jit_dlclose \ +// RUN: -alias Platform:_dlopen=___orc_rt_macho_jit_dlopen \ +// RUN: -alias Platform:_dlclose=___orc_rt_macho_jit_dlclose \ // RUN: %t.test.o -jd inits %t.inits.o -lmain | FileCheck %s // CHECK: entering main diff --git a/compiler-rt/test/orc/TestCases/Linux/ppc64/trivial-atexit.S b/compiler-rt/test/orc/TestCases/Linux/ppc64/trivial-atexit.S index eaa8ac1088bf..0b2a26244047 100644 --- a/compiler-rt/test/orc/TestCases/Linux/ppc64/trivial-atexit.S +++ b/compiler-rt/test/orc/TestCases/Linux/ppc64/trivial-atexit.S @@ -1,5 +1,11 @@ // Test that the runtime correctly interposes atexit. // +// REQUIRES: disabled +// This test is disabled until a proper atexit interpose can be implemented: +// the current one assumes that atexit is defined in the dylib that calls it, +// which is not true in general. See +// https://github.com/llvm/llvm-project/issues/74641. +// // RUN: %clang -c -o %t %s // RUN: %llvm_jitlink %t diff --git a/compiler-rt/test/orc/TestCases/Linux/x86-64/trivial-atexit.S b/compiler-rt/test/orc/TestCases/Linux/x86-64/trivial-atexit.S index 16852c6e1ab4..7a606e9279d7 100644 --- a/compiler-rt/test/orc/TestCases/Linux/x86-64/trivial-atexit.S +++ b/compiler-rt/test/orc/TestCases/Linux/x86-64/trivial-atexit.S @@ -1,5 +1,11 @@ // Test that the runtime correctly interposes atexit. // +// REQUIRES: disabled +// This test is disabled until a proper atexit interpose can be implemented: +// the current one assumes that atexit is defined in the dylib that calls it, +// which is not true in general. See +// https://github.com/llvm/llvm-project/issues/74641 +// // RUN: %clang -c -o %t %s // RUN: %llvm_jitlink %t diff --git a/compiler-rt/test/orc/TestCases/Windows/x86-64/trivial-jit-dlopen.c b/compiler-rt/test/orc/TestCases/Windows/x86-64/trivial-jit-dlopen.c index 6a9182b0d7ab..fd17993e4c57 100644 --- a/compiler-rt/test/orc/TestCases/Windows/x86-64/trivial-jit-dlopen.c +++ b/compiler-rt/test/orc/TestCases/Windows/x86-64/trivial-jit-dlopen.c @@ -5,8 +5,8 @@ // RUN: %clang_cl -MD -c -o %t.inits.o %p/Inputs/standalone-dylib.c // RUN: %clang_cl -MD -c -o %t.test.o %s // RUN: %llvm_jitlink \ -// RUN: -alias dlopen=__orc_rt_coff_jit_dlopen \ -// RUN: -alias dlclose=__orc_rt_coff_jit_dlclose \ +// RUN: -alias Platform:dlopen=__orc_rt_coff_jit_dlopen \ +// RUN: -alias Platform:dlclose=__orc_rt_coff_jit_dlclose \ // RUN: %t.test.o -jd inits %t.inits.o -lmain | FileCheck %s // CHECK: entering main diff --git a/flang/include/flang/Frontend/CompilerInstance.h b/flang/include/flang/Frontend/CompilerInstance.h index 8ed416c2bbbf..4fcc59f7cf57 100644 --- a/flang/include/flang/Frontend/CompilerInstance.h +++ b/flang/include/flang/Frontend/CompilerInstance.h @@ -21,6 +21,7 @@ #include "flang/Semantics/runtime-type-info.h" #include "flang/Semantics/semantics.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" namespace Fortran::frontend { @@ -57,6 +58,8 @@ class CompilerInstance { std::unique_ptr semaContext; + std::unique_ptr targetMachine; + /// The stream for diagnostics from Semantics llvm::raw_ostream *semaOutputStream = &llvm::errs(); @@ -231,6 +234,26 @@ public: createDefaultOutputFile(bool binary = true, llvm::StringRef baseInput = "", llvm::StringRef extension = ""); + /// { + /// @name Target Machine + /// { + + /// Get the target machine. + const llvm::TargetMachine &getTargetMachine() const { + assert(targetMachine && "target machine was not set"); + return *targetMachine; + } + llvm::TargetMachine &getTargetMachine() { + assert(targetMachine && "target machine was not set"); + return *targetMachine; + } + + /// Sets up LLVM's TargetMachine. + bool setUpTargetMachine(); + + /// Produces the string which represents target feature + std::string getTargetFeatures(); + private: /// Create a new output file /// diff --git a/flang/include/flang/Frontend/CompilerInvocation.h b/flang/include/flang/Frontend/CompilerInvocation.h index 7ce072cd1ec0..4924d090eaf9 100644 --- a/flang/include/flang/Frontend/CompilerInvocation.h +++ b/flang/include/flang/Frontend/CompilerInvocation.h @@ -26,6 +26,10 @@ #include "llvm/Option/ArgList.h" #include +namespace llvm { +class TargetMachine; +} + namespace Fortran::frontend { /// Fill out Opts based on the options given in Args. @@ -98,6 +102,9 @@ class CompilerInvocation : public CompilerInvocationBase { bool warnAsErr = false; + // Executable name + const char *argv0; + /// This flag controls the unparsing and is used to decide whether to print /// out the semantically analyzed version of an object or expression or the /// plain version that does not include any information from semantic @@ -158,7 +165,8 @@ public: /// Creates and configures semantics context based on the compilation flags. std::unique_ptr - getSemanticsCtx(Fortran::parser::AllCookedSources &allCookedSources); + getSemanticsCtx(Fortran::parser::AllCookedSources &allCookedSources, + const llvm::TargetMachine &); std::string &getModuleDir() { return moduleDir; } const std::string &getModuleDir() const { return moduleDir; } @@ -184,6 +192,8 @@ public: return enableConformanceChecks; } + const char *getArgv0() { return argv0; } + bool &getEnableUsageChecks() { return enableUsageChecks; } const bool &getEnableUsageChecks() const { return enableUsageChecks; } @@ -217,6 +227,8 @@ public: void setEnableUsageChecks() { enableUsageChecks = true; } /// Useful setters + void setArgv0(const char *dir) { argv0 = dir; } + void setModuleDir(std::string &dir) { moduleDir = dir; } void setModuleFileSuffix(const char *suffix) { diff --git a/flang/include/flang/Frontend/FrontendActions.h b/flang/include/flang/Frontend/FrontendActions.h index 8272e0729ce3..e2e859f3a81b 100644 --- a/flang/include/flang/Frontend/FrontendActions.h +++ b/flang/include/flang/Frontend/FrontendActions.h @@ -21,7 +21,6 @@ #include "mlir/IR/BuiltinOps.h" #include "llvm/ADT/StringRef.h" #include "llvm/IR/Module.h" -#include "llvm/Target/TargetMachine.h" #include namespace Fortran::frontend { @@ -204,8 +203,6 @@ class CodeGenAction : public FrontendAction { void executeAction() override; /// Runs prescan, parsing, sema and lowers to MLIR. bool beginSourceFileAction() override; - /// Sets up LLVM's TargetMachine. - bool setUpTargetMachine(); /// Runs the optimization (aka middle-end) pipeline on the LLVM module /// associated with this action. void runOptimizationPipeline(llvm::raw_pwrite_stream &os); @@ -234,7 +231,6 @@ protected: BackendActionTy action; - std::unique_ptr tm; /// } public: ~CodeGenAction() override; diff --git a/flang/include/flang/Lower/Bridge.h b/flang/include/flang/Lower/Bridge.h index d363068acfdb..6c0d14d65eda 100644 --- a/flang/include/flang/Lower/Bridge.h +++ b/flang/include/flang/Lower/Bridge.h @@ -22,6 +22,10 @@ #include "flang/Optimizer/Dialect/Support/KindMapping.h" #include "mlir/IR/BuiltinOps.h" +namespace llvm { +class DataLayout; +} // namespace llvm + namespace Fortran { namespace common { class IntrinsicTypeDefaultKinds; @@ -59,10 +63,12 @@ public: llvm::StringRef triple, fir::KindMapping &kindMap, const Fortran::lower::LoweringOptions &loweringOptions, const std::vector &envDefaults, - const Fortran::common::LanguageFeatureControl &languageFeatures) { + const Fortran::common::LanguageFeatureControl &languageFeatures, + const llvm::DataLayout *dataLayout = nullptr) { return LoweringBridge(ctx, semanticsContext, defaultKinds, intrinsics, targetCharacteristics, allCooked, triple, kindMap, - loweringOptions, envDefaults, languageFeatures); + loweringOptions, envDefaults, languageFeatures, + dataLayout); } //===--------------------------------------------------------------------===// @@ -140,7 +146,8 @@ private: fir::KindMapping &kindMap, const Fortran::lower::LoweringOptions &loweringOptions, const std::vector &envDefaults, - const Fortran::common::LanguageFeatureControl &languageFeatures); + const Fortran::common::LanguageFeatureControl &languageFeatures, + const llvm::DataLayout *dataLayout); LoweringBridge() = delete; LoweringBridge(const LoweringBridge &) = delete; diff --git a/flang/include/flang/Lower/ConvertExprToHLFIR.h b/flang/include/flang/Lower/ConvertExprToHLFIR.h index 42ce7b6edd74..dc0bde191354 100644 --- a/flang/include/flang/Lower/ConvertExprToHLFIR.h +++ b/flang/include/flang/Lower/ConvertExprToHLFIR.h @@ -112,6 +112,12 @@ fir::ExtendedValue convertToValue(mlir::Location loc, hlfir::Entity entity, Fortran::lower::StatementContext &); +fir::ExtendedValue convertDataRefToValue(mlir::Location loc, + Fortran::lower::AbstractConverter &, + const Fortran::evaluate::DataRef &, + Fortran::lower::SymMap &, + Fortran::lower::StatementContext &); + /// Lower an evaluate::Expr to a fir::MutableBoxValue value. /// This can only be called if the Expr is a POINTER or ALLOCATABLE, /// otherwise, this will crash. diff --git a/flang/include/flang/Lower/ConvertVariable.h b/flang/include/flang/Lower/ConvertVariable.h index 7da04fea3516..0ff3ca9bdeac 100644 --- a/flang/include/flang/Lower/ConvertVariable.h +++ b/flang/include/flang/Lower/ConvertVariable.h @@ -19,6 +19,7 @@ #include "flang/Lower/Support/Utils.h" #include "flang/Optimizer/Dialect/FIRAttr.h" +#include "flang/Semantics/symbol.h" #include "mlir/IR/Value.h" #include "llvm/ADT/DenseMap.h" @@ -29,7 +30,12 @@ class GlobalOp; class FortranVariableFlagsAttr; } // namespace fir -namespace Fortran ::lower { +namespace Fortran { +namespace semantics { +class Scope; +} // namespace semantics + +namespace lower { class AbstractConverter; class CallerInterface; class StatementContext; @@ -66,6 +72,14 @@ void defineCommonBlocks( const std::vector> &commonBlocks); +/// The COMMON block is a global structure. \p commonValue is the base address +/// of the COMMON block. As the offset from the symbol \p sym, generate the +/// COMMON block member value (commonValue + offset) for the symbol. +mlir::Value genCommonBlockMember(AbstractConverter &converter, + mlir::Location loc, + const Fortran::semantics::Symbol &sym, + mlir::Value commonValue); + /// Lower a symbol attributes given an optional storage \p and add it to the /// provided symbol map. If \preAlloc is not provided, a temporary storage will /// be allocated. This is a low level function that should only be used if @@ -138,5 +152,6 @@ void genDeclareSymbol(Fortran::lower::AbstractConverter &converter, /// Cray pointer symbol. Assert if the pointer symbol cannot be found. Fortran::semantics::SymbolRef getCrayPointer(Fortran::semantics::SymbolRef sym); -} // namespace Fortran::lower +} // namespace lower +} // namespace Fortran #endif // FORTRAN_LOWER_CONVERT_VARIABLE_H diff --git a/flang/include/flang/Optimizer/Dialect/FIROps.td b/flang/include/flang/Optimizer/Dialect/FIROps.td index 14a387990618..fcecc605dfa5 100644 --- a/flang/include/flang/Optimizer/Dialect/FIROps.td +++ b/flang/include/flang/Optimizer/Dialect/FIROps.td @@ -2553,14 +2553,18 @@ def fir_DivcOp : ComplexArithmeticOp<"divc", // Pow is a builtin call and not a primitive def fir_CmpcOp : fir_Op<"cmpc", - [NoMemoryEffect, SameTypeOperands, SameOperandsAndResultShape]> { + [NoMemoryEffect, SameTypeOperands, SameOperandsAndResultShape, + DeclareOpInterfaceMethods]> { let summary = "complex floating-point comparison operator"; let description = [{ A complex comparison to handle complex types found in FIR. }]; - let arguments = (ins fir_ComplexType:$lhs, fir_ComplexType:$rhs); + let arguments = (ins + fir_ComplexType:$lhs, + fir_ComplexType:$rhs, + DefaultValuedAttr:$fastmath); let results = (outs AnyLogicalLike); diff --git a/flang/include/flang/Optimizer/Support/DataLayout.h b/flang/include/flang/Optimizer/Support/DataLayout.h new file mode 100644 index 000000000000..88ff575a8ff0 --- /dev/null +++ b/flang/include/flang/Optimizer/Support/DataLayout.h @@ -0,0 +1,39 @@ +//===-- Optimizer/Support/DataLayout.h --------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Coding style: https://mlir.llvm.org/getting_started/DeveloperGuide/ +// +//===----------------------------------------------------------------------===// + +#ifndef FORTRAN_OPTIMIZER_SUPPORT_DATALAYOUT_H +#define FORTRAN_OPTIMIZER_SUPPORT_DATALAYOUT_H + +namespace mlir { +class ModuleOp; +} +namespace llvm { +class DataLayout; +} + +namespace fir::support { +/// Create an mlir::DataLayoutSpecInterface attribute from an llvm::DataLayout +/// and set it on the provided mlir::ModuleOp. +/// Also set the llvm.data_layout attribute with the string representation of +/// the llvm::DataLayout on the module. +/// These attributes are replaced if they were already set. +void setMLIRDataLayout(mlir::ModuleOp mlirModule, const llvm::DataLayout &dl); + +/// Create an mlir::DataLayoutSpecInterface from the llvm.data_layout attribute +/// if one is provided. If such attribute is not available, create a default +/// target independent layout when allowDefaultLayout is true. Otherwise do +/// nothing. +void setMLIRDataLayoutFromAttributes(mlir::ModuleOp mlirModule, + bool allowDefaultLayout); +} // namespace fir::support + +#endif // FORTRAN_OPTIMIZER_SUPPORT_DATALAYOUT_H diff --git a/flang/include/flang/Tools/TargetSetup.h b/flang/include/flang/Tools/TargetSetup.h new file mode 100644 index 000000000000..238d66c9241d --- /dev/null +++ b/flang/include/flang/Tools/TargetSetup.h @@ -0,0 +1,40 @@ +//===-- Tools/TargetSetup.h ------------------------------------- *-C++-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef FORTRAN_TOOLS_TARGET_SETUP_H +#define FORTRAN_TOOLS_TARGET_SETUP_H + +#include "flang/Evaluate/target.h" +#include "llvm/Target/TargetMachine.h" + +namespace Fortran::tools { + +[[maybe_unused]] inline static void setUpTargetCharacteristics( + Fortran::evaluate::TargetCharacteristics &targetCharacteristics, + const llvm::TargetMachine &targetMachine, + const std::string &compilerVersion, const std::string &compilerOptions) { + + const llvm::Triple &targetTriple{targetMachine.getTargetTriple()}; + // FIXME: Handle real(3) ? + if (targetTriple.getArch() != llvm::Triple::ArchType::x86_64) + targetCharacteristics.DisableType( + Fortran::common::TypeCategory::Real, /*kind=*/10); + + targetCharacteristics.set_compilerOptionsString(compilerOptions) + .set_compilerVersionString(compilerVersion); + + if (targetTriple.isPPC()) + targetCharacteristics.set_isPPC(true); + + // TODO: use target machine data layout to set-up the target characteristics + // type size and alignment info. +} + +} // namespace Fortran::tools + +#endif // FORTRAN_TOOLS_TARGET_SETUP_H diff --git a/flang/lib/Frontend/CompilerInstance.cpp b/flang/lib/Frontend/CompilerInstance.cpp index 328b3774bc29..a6b8f1a9d29e 100644 --- a/flang/lib/Frontend/CompilerInstance.cpp +++ b/flang/lib/Frontend/CompilerInstance.cpp @@ -17,11 +17,15 @@ #include "flang/Parser/parsing.h" #include "flang/Parser/provenance.h" #include "flang/Semantics/semantics.h" +#include "clang/Basic/DiagnosticFrontend.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Errc.h" #include "llvm/Support/Error.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Path.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/TargetParser/TargetParser.h" #include "llvm/TargetParser/Triple.h" using namespace Fortran::frontend; @@ -156,8 +160,10 @@ bool CompilerInstance::executeAction(FrontendAction &act) { invoc.setFortranOpts(); // Set the encoding to read all input files in based on user input. allSources->set_encoding(invoc.getFortranOpts().encoding); + if (!setUpTargetMachine()) + return false; // Create the semantics context - semaContext = invoc.getSemanticsCtx(*allCookedSources); + semaContext = invoc.getSemanticsCtx(*allCookedSources, getTargetMachine()); // Set options controlling lowering to FIR. invoc.setLoweringOptions(); @@ -197,3 +203,129 @@ CompilerInstance::createDiagnostics(clang::DiagnosticOptions *opts, } return diags; } + +// Get feature string which represents combined explicit target features +// for AMD GPU and the target features specified by the user +static std::string +getExplicitAndImplicitAMDGPUTargetFeatures(clang::DiagnosticsEngine &diags, + const TargetOptions &targetOpts, + const llvm::Triple triple) { + llvm::StringRef cpu = targetOpts.cpu; + llvm::StringMap implicitFeaturesMap; + std::string errorMsg; + // Get the set of implicit target features + llvm::AMDGPU::fillAMDGPUFeatureMap(cpu, triple, implicitFeaturesMap); + + // Add target features specified by the user + for (auto &userFeature : targetOpts.featuresAsWritten) { + std::string userKeyString = userFeature.substr(1); + implicitFeaturesMap[userKeyString] = (userFeature[0] == '+'); + } + + if (!llvm::AMDGPU::insertWaveSizeFeature(cpu, triple, implicitFeaturesMap, + errorMsg)) { + unsigned diagID = diags.getCustomDiagID(clang::DiagnosticsEngine::Error, + "Unsupported feature ID: %0"); + diags.Report(diagID) << errorMsg.data(); + return std::string(); + } + + llvm::SmallVector featuresVec; + for (auto &implicitFeatureItem : implicitFeaturesMap) { + featuresVec.push_back((llvm::Twine(implicitFeatureItem.second ? "+" : "-") + + implicitFeatureItem.first().str()) + .str()); + } + llvm::sort(featuresVec); + return llvm::join(featuresVec, ","); +} + +// Get feature string which represents combined explicit target features +// for NVPTX and the target features specified by the user/ +// TODO: Have a more robust target conf like `clang/lib/Basic/Targets/NVPTX.cpp` +static std::string +getExplicitAndImplicitNVPTXTargetFeatures(clang::DiagnosticsEngine &diags, + const TargetOptions &targetOpts, + const llvm::Triple triple) { + llvm::StringRef cpu = targetOpts.cpu; + llvm::StringMap implicitFeaturesMap; + std::string errorMsg; + bool ptxVer = false; + + // Add target features specified by the user + for (auto &userFeature : targetOpts.featuresAsWritten) { + llvm::StringRef userKeyString(llvm::StringRef(userFeature).drop_front(1)); + implicitFeaturesMap[userKeyString.str()] = (userFeature[0] == '+'); + // Check if the user provided a PTX version + if (userKeyString.startswith("ptx")) + ptxVer = true; + } + + // Set the default PTX version to `ptx61` if none was provided. + // TODO: set the default PTX version based on the chip. + if (!ptxVer) + implicitFeaturesMap["ptx61"] = true; + + // Set the compute capability. + implicitFeaturesMap[cpu.str()] = true; + + llvm::SmallVector featuresVec; + for (auto &implicitFeatureItem : implicitFeaturesMap) { + featuresVec.push_back((llvm::Twine(implicitFeatureItem.second ? "+" : "-") + + implicitFeatureItem.first().str()) + .str()); + } + llvm::sort(featuresVec); + return llvm::join(featuresVec, ","); +} + +std::string CompilerInstance::getTargetFeatures() { + const TargetOptions &targetOpts = getInvocation().getTargetOpts(); + const llvm::Triple triple(targetOpts.triple); + + // Clang does not append all target features to the clang -cc1 invocation. + // Some target features are parsed implicitly by clang::TargetInfo child + // class. Clang::TargetInfo classes are the basic clang classes and + // they cannot be reused by Flang. + // That's why we need to extract implicit target features and add + // them to the target features specified by the user + if (triple.isAMDGPU()) { + return getExplicitAndImplicitAMDGPUTargetFeatures(getDiagnostics(), + targetOpts, triple); + } else if (triple.isNVPTX()) { + return getExplicitAndImplicitNVPTXTargetFeatures(getDiagnostics(), + targetOpts, triple); + } + return llvm::join(targetOpts.featuresAsWritten.begin(), + targetOpts.featuresAsWritten.end(), ","); +} + +bool CompilerInstance::setUpTargetMachine() { + const TargetOptions &targetOpts = getInvocation().getTargetOpts(); + const std::string &theTriple = targetOpts.triple; + + // Create `Target` + std::string error; + const llvm::Target *theTarget = + llvm::TargetRegistry::lookupTarget(theTriple, error); + if (!theTarget) { + getDiagnostics().Report(clang::diag::err_fe_unable_to_create_target) + << error; + return false; + } + + // Create `TargetMachine` + const auto &CGOpts = getInvocation().getCodeGenOpts(); + std::optional OptLevelOrNone = + llvm::CodeGenOpt::getLevel(CGOpts.OptimizationLevel); + assert(OptLevelOrNone && "Invalid optimization level!"); + llvm::CodeGenOptLevel OptLevel = *OptLevelOrNone; + std::string featuresStr = getTargetFeatures(); + targetMachine.reset(theTarget->createTargetMachine( + theTriple, /*CPU=*/targetOpts.cpu, + /*Features=*/featuresStr, llvm::TargetOptions(), + /*Reloc::Model=*/CGOpts.getRelocationModel(), + /*CodeModel::Model=*/std::nullopt, OptLevel)); + assert(targetMachine && "Failed to create TargetMachine"); + return true; +} diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index ec04727fb264..b3f32bb241d0 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -18,6 +18,7 @@ #include "flang/Frontend/PreprocessorOptions.h" #include "flang/Frontend/TargetOptions.h" #include "flang/Semantics/semantics.h" +#include "flang/Tools/TargetSetup.h" #include "flang/Version.inc" #include "clang/Basic/AllDiagnostics.h" #include "clang/Basic/DiagnosticDriver.h" @@ -243,11 +244,6 @@ static void parseCodeGenArgs(Fortran::frontend::CodeGenOptions &opts, opts.LoopVersioning = 1; opts.AliasAnalysis = opts.OptimizationLevel > 0; - if (auto *arg = - args.getLastArg(clang::driver::options::OPT_falias_analysis, - clang::driver::options::OPT_fno_alias_analysis)) - opts.AliasAnalysis = - arg->getOption().matches(clang::driver::options::OPT_falias_analysis); for (auto *a : args.filtered(clang::driver::options::OPT_fpass_plugin_EQ)) opts.LLVMPassPlugins.push_back(a->getValue()); @@ -700,19 +696,19 @@ static bool parseFrontendArgs(FrontendOptions &opts, llvm::opt::ArgList &args, } // Generate the path to look for intrinsic modules -static std::string getIntrinsicDir() { +static std::string getIntrinsicDir(const char *argv) { // TODO: Find a system independent API llvm::SmallString<128> driverPath; - driverPath.assign(llvm::sys::fs::getMainExecutable(nullptr, nullptr)); + driverPath.assign(llvm::sys::fs::getMainExecutable(argv, nullptr)); llvm::sys::path::remove_filename(driverPath); driverPath.append("/../include/flang/"); return std::string(driverPath); } // Generate the path to look for OpenMP headers -static std::string getOpenMPHeadersDir() { +static std::string getOpenMPHeadersDir(const char *argv) { llvm::SmallString<128> includePath; - includePath.assign(llvm::sys::fs::getMainExecutable(nullptr, nullptr)); + includePath.assign(llvm::sys::fs::getMainExecutable(argv, nullptr)); llvm::sys::path::remove_filename(includePath); includePath.append("/../include/flang/OpenMP/"); return std::string(includePath); @@ -1216,6 +1212,8 @@ bool CompilerInvocation::createFromArgs( } } + res.setArgv0(argv0); + return success; } @@ -1258,7 +1256,8 @@ void CompilerInvocation::setDefaultFortranOpts() { // Add the location of omp_lib.h to the search directories. Currently this is // identical to the modules' directory. - fortranOptions.searchDirectories.emplace_back(getOpenMPHeadersDir()); + fortranOptions.searchDirectories.emplace_back( + getOpenMPHeadersDir(getArgv0())); fortranOptions.isFixedForm = false; } @@ -1323,7 +1322,8 @@ void CompilerInvocation::setFortranOpts() { preprocessorOptions.searchDirectoriesFromIntrModPath.end()); // Add the default intrinsic module directory - fortranOptions.intrinsicModuleDirectories.emplace_back(getIntrinsicDir()); + fortranOptions.intrinsicModuleDirectories.emplace_back( + getIntrinsicDir(getArgv0())); // Add the directory supplied through -J/-module-dir to the list of search // directories @@ -1348,7 +1348,8 @@ void CompilerInvocation::setFortranOpts() { std::unique_ptr CompilerInvocation::getSemanticsCtx( - Fortran::parser::AllCookedSources &allCookedSources) { + Fortran::parser::AllCookedSources &allCookedSources, + const llvm::TargetMachine &targetMachine) { auto &fortranOptions = getFortranOpts(); auto semanticsContext = std::make_unique( @@ -1361,21 +1362,10 @@ CompilerInvocation::getSemanticsCtx( .set_moduleFileSuffix(getModuleFileSuffix()) .set_underscoring(getCodeGenOpts().Underscoring); - llvm::Triple targetTriple{llvm::Triple(this->targetOpts.triple)}; - // FIXME: Handle real(3) ? - if (targetTriple.getArch() != llvm::Triple::ArchType::x86_64) { - semanticsContext->targetCharacteristics().DisableType( - Fortran::common::TypeCategory::Real, /*kind=*/10); - } - - std::string version = Fortran::common::getFlangFullVersion(); - semanticsContext->targetCharacteristics() - .set_compilerOptionsString(allCompilerInvocOpts) - .set_compilerVersionString(version); - - if (targetTriple.isPPC()) - semanticsContext->targetCharacteristics().set_isPPC(true); - + std::string compilerVersion = Fortran::common::getFlangFullVersion(); + Fortran::tools::setUpTargetCharacteristics( + semanticsContext->targetCharacteristics(), targetMachine, compilerVersion, + allCompilerInvocOpts); return semanticsContext; } diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp index 1be95cc27f42..b114c552b552 100644 --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -21,6 +21,7 @@ #include "flang/Lower/Support/Verifier.h" #include "flang/Optimizer/Dialect/Support/FIRContext.h" #include "flang/Optimizer/Dialect/Support/KindMapping.h" +#include "flang/Optimizer/Support/DataLayout.h" #include "flang/Optimizer/Support/InitFIR.h" #include "flang/Optimizer/Support/Utils.h" #include "flang/Optimizer/Transforms/Passes.h" @@ -53,7 +54,6 @@ #include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/Verifier.h" #include "llvm/IRReader/IRReader.h" -#include "llvm/MC/TargetRegistry.h" #include "llvm/Object/OffloadBinary.h" #include "llvm/Passes/PassBuilder.h" #include "llvm/Passes/PassPlugin.h" @@ -65,7 +65,6 @@ #include "llvm/Support/SourceMgr.h" #include "llvm/Support/ToolOutputFile.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/TargetParser/TargetParser.h" #include "llvm/Transforms/Utils/ModuleUtils.h" #include #include @@ -139,111 +138,6 @@ bool PrescanAndSemaDebugAction::beginSourceFileAction() { (generateRtTypeTables() || true); } -// Get feature string which represents combined explicit target features -// for AMD GPU and the target features specified by the user -static std::string -getExplicitAndImplicitAMDGPUTargetFeatures(CompilerInstance &ci, - const TargetOptions &targetOpts, - const llvm::Triple triple) { - llvm::StringRef cpu = targetOpts.cpu; - llvm::StringMap implicitFeaturesMap; - std::string errorMsg; - // Get the set of implicit target features - llvm::AMDGPU::fillAMDGPUFeatureMap(cpu, triple, implicitFeaturesMap); - - // Add target features specified by the user - for (auto &userFeature : targetOpts.featuresAsWritten) { - std::string userKeyString = userFeature.substr(1); - implicitFeaturesMap[userKeyString] = (userFeature[0] == '+'); - } - - if (!llvm::AMDGPU::insertWaveSizeFeature(cpu, triple, implicitFeaturesMap, - errorMsg)) { - unsigned diagID = ci.getDiagnostics().getCustomDiagID( - clang::DiagnosticsEngine::Error, "Unsupported feature ID: %0"); - ci.getDiagnostics().Report(diagID) << errorMsg.data(); - return std::string(); - } - - llvm::SmallVector featuresVec; - for (auto &implicitFeatureItem : implicitFeaturesMap) { - featuresVec.push_back((llvm::Twine(implicitFeatureItem.second ? "+" : "-") + - implicitFeatureItem.first().str()) - .str()); - } - llvm::sort(featuresVec); - return llvm::join(featuresVec, ","); -} - -// Get feature string which represents combined explicit target features -// for NVPTX and the target features specified by the user/ -// TODO: Have a more robust target conf like `clang/lib/Basic/Targets/NVPTX.cpp` -static std::string -getExplicitAndImplicitNVPTXTargetFeatures(CompilerInstance &ci, - const TargetOptions &targetOpts, - const llvm::Triple triple) { - llvm::StringRef cpu = targetOpts.cpu; - llvm::StringMap implicitFeaturesMap; - std::string errorMsg; - bool ptxVer = false; - - // Add target features specified by the user - for (auto &userFeature : targetOpts.featuresAsWritten) { - llvm::StringRef userKeyString(llvm::StringRef(userFeature).drop_front(1)); - implicitFeaturesMap[userKeyString.str()] = (userFeature[0] == '+'); - // Check if the user provided a PTX version - if (userKeyString.startswith("ptx")) - ptxVer = true; - } - - // Set the default PTX version to `ptx61` if none was provided. - // TODO: set the default PTX version based on the chip. - if (!ptxVer) - implicitFeaturesMap["ptx61"] = true; - - // Set the compute capability. - implicitFeaturesMap[cpu.str()] = true; - - llvm::SmallVector featuresVec; - for (auto &implicitFeatureItem : implicitFeaturesMap) { - featuresVec.push_back((llvm::Twine(implicitFeatureItem.second ? "+" : "-") + - implicitFeatureItem.first().str()) - .str()); - } - llvm::sort(featuresVec); - return llvm::join(featuresVec, ","); -} - -// Produces the string which represents target feature -static std::string getTargetFeatures(CompilerInstance &ci) { - const TargetOptions &targetOpts = ci.getInvocation().getTargetOpts(); - const llvm::Triple triple(targetOpts.triple); - - // Clang does not append all target features to the clang -cc1 invocation. - // Some target features are parsed implicitly by clang::TargetInfo child - // class. Clang::TargetInfo classes are the basic clang classes and - // they cannot be reused by Flang. - // That's why we need to extract implicit target features and add - // them to the target features specified by the user - if (triple.isAMDGPU()) { - return getExplicitAndImplicitAMDGPUTargetFeatures(ci, targetOpts, triple); - } else if (triple.isNVPTX()) { - return getExplicitAndImplicitNVPTXTargetFeatures(ci, targetOpts, triple); - } - return llvm::join(targetOpts.featuresAsWritten.begin(), - targetOpts.featuresAsWritten.end(), ","); -} - -static void setMLIRDataLayout(mlir::ModuleOp &mlirModule, - const llvm::DataLayout &dl) { - mlir::MLIRContext *context = mlirModule.getContext(); - mlirModule->setAttr( - mlir::LLVM::LLVMDialect::getDataLayoutAttrName(), - mlir::StringAttr::get(context, dl.getStringRepresentation())); - mlir::DataLayoutSpecInterface dlSpec = mlir::translateDataLayout(dl, context); - mlirModule->setAttr(mlir::DLTIDialect::kDataLayoutAttrName, dlSpec); -} - static void addDependentLibs(mlir::ModuleOp &mlirModule, CompilerInstance &ci) { const std::vector &libs = ci.getInvocation().getCodeGenOpts().DependentLibs; @@ -352,6 +246,8 @@ bool CodeGenAction::beginSourceFileAction() { fir::support::loadDialects(*mlirCtx); fir::support::registerLLVMTranslation(*mlirCtx); + const llvm::TargetMachine &targetMachine = ci.getTargetMachine(); + // If the input is an MLIR file, just parse it and return. if (this->getCurrentInput().getKind().getLanguage() == Language::MLIR) { llvm::SourceMgr sourceMgr; @@ -369,10 +265,8 @@ bool CodeGenAction::beginSourceFileAction() { } mlirModule = std::make_unique(module.release()); - if (!setUpTargetMachine()) - return false; - const llvm::DataLayout &dl = tm->createDataLayout(); - setMLIRDataLayout(*mlirModule, dl); + const llvm::DataLayout &dl = targetMachine.createDataLayout(); + fir::support::setMLIRDataLayout(*mlirModule, dl); return true; } @@ -394,6 +288,8 @@ bool CodeGenAction::beginSourceFileAction() { ci.getSemanticsContext().defaultKinds(); fir::KindMapping kindMap(mlirCtx.get(), llvm::ArrayRef{ fir::fromDefaultKinds(defKinds)}); + const llvm::DataLayout &dl = targetMachine.createDataLayout(); + lower::LoweringBridge lb = Fortran::lower::LoweringBridge::create( *mlirCtx, ci.getSemanticsContext(), defKinds, ci.getSemanticsContext().intrinsics(), @@ -401,27 +297,22 @@ bool CodeGenAction::beginSourceFileAction() { ci.getParsing().allCooked(), ci.getInvocation().getTargetOpts().triple, kindMap, ci.getInvocation().getLoweringOpts(), ci.getInvocation().getFrontendOpts().envDefaults, - ci.getInvocation().getFrontendOpts().features); + ci.getInvocation().getFrontendOpts().features, &dl); // Fetch module from lb, so we can set mlirModule = std::make_unique(lb.getModule()); - if (!setUpTargetMachine()) - return false; - if (ci.getInvocation().getFrontendOpts().features.IsEnabled( Fortran::common::LanguageFeature::OpenMP)) { setOffloadModuleInterfaceAttributes(*mlirModule, ci.getInvocation().getLangOpts()); - setOffloadModuleInterfaceTargetAttribute(*mlirModule, tm->getTargetCPU(), - tm->getTargetFeatureString()); + setOffloadModuleInterfaceTargetAttribute( + *mlirModule, targetMachine.getTargetCPU(), + targetMachine.getTargetFeatureString()); setOpenMPVersionAttribute(*mlirModule, ci.getInvocation().getLangOpts().OpenMPVersion); } - const llvm::DataLayout &dl = tm->createDataLayout(); - setMLIRDataLayout(*mlirModule, dl); - // Create a parse tree and lower it to FIR Fortran::parser::Program &parseTree{*ci.getParsing().parseTree()}; lb.lower(parseTree, ci.getSemanticsContext()); @@ -830,7 +721,7 @@ getVScaleRange(CompilerInstance &ci, return std::pair( langOpts.VScaleMin ? langOpts.VScaleMin : 1, langOpts.VScaleMax); - std::string featuresStr = getTargetFeatures(ci); + std::string featuresStr = ci.getTargetFeatures(); if (featuresStr.find("+sve") != std::string::npos) return std::pair(1, 16); @@ -911,38 +802,6 @@ void CodeGenAction::generateLLVMIR() { } } -bool CodeGenAction::setUpTargetMachine() { - CompilerInstance &ci = this->getInstance(); - - const TargetOptions &targetOpts = ci.getInvocation().getTargetOpts(); - const std::string &theTriple = targetOpts.triple; - - // Create `Target` - std::string error; - const llvm::Target *theTarget = - llvm::TargetRegistry::lookupTarget(theTriple, error); - if (!theTarget) { - ci.getDiagnostics().Report(clang::diag::err_fe_unable_to_create_target) - << error; - return false; - } - - // Create `TargetMachine` - const auto &CGOpts = ci.getInvocation().getCodeGenOpts(); - std::optional OptLevelOrNone = - llvm::CodeGenOpt::getLevel(CGOpts.OptimizationLevel); - assert(OptLevelOrNone && "Invalid optimization level!"); - llvm::CodeGenOptLevel OptLevel = *OptLevelOrNone; - std::string featuresStr = getTargetFeatures(ci); - tm.reset(theTarget->createTargetMachine( - theTriple, /*CPU=*/targetOpts.cpu, - /*Features=*/featuresStr, llvm::TargetOptions(), - /*Reloc::Model=*/CGOpts.getRelocationModel(), - /*CodeModel::Model=*/std::nullopt, OptLevel)); - assert(tm && "Failed to create TargetMachine"); - return true; -} - static std::unique_ptr getOutputStream(CompilerInstance &ci, llvm::StringRef inFile, BackendActionTy action) { @@ -1020,6 +879,7 @@ void CodeGenAction::runOptimizationPipeline(llvm::raw_pwrite_stream &os) { auto &diags = getInstance().getDiagnostics(); llvm::OptimizationLevel level = mapToLevel(opts); + llvm::TargetMachine *targetMachine = &getInstance().getTargetMachine(); // Create the analysis managers. llvm::LoopAnalysisManager lam; llvm::FunctionAnalysisManager fam; @@ -1033,7 +893,7 @@ void CodeGenAction::runOptimizationPipeline(llvm::raw_pwrite_stream &os) { llvm::StandardInstrumentations si(llvmModule->getContext(), opts.DebugPassManager); si.registerCallbacks(pic, &mam); - llvm::PassBuilder pb(tm.get(), pto, pgoOpt, &pic); + llvm::PassBuilder pb(targetMachine, pto, pgoOpt, &pic); // Attempt to load pass plugins and register their callbacks with PB. for (auto &pluginFile : opts.LLVMPassPlugins) { @@ -1299,9 +1159,8 @@ void CodeGenAction::executeAction() { // Set the triple based on the targetmachine (this comes compiler invocation // and the command-line target option if specified, or the default if not // given on the command-line). - if (!setUpTargetMachine()) - return; - const std::string &theTriple = tm->getTargetTriple().str(); + llvm::TargetMachine &targetMachine = ci.getTargetMachine(); + const std::string &theTriple = targetMachine.getTargetTriple().str(); if (llvmModule->getTargetTriple() != theTriple) { diags.Report(clang::diag::warn_fe_override_module) << theTriple; @@ -1311,7 +1170,7 @@ void CodeGenAction::executeAction() { // Note that this overwrites any datalayout stored in the LLVM-IR. This avoids // an assert for incompatible data layout when the code-generation happens. llvmModule->setTargetTriple(theTriple); - llvmModule->setDataLayout(tm->createDataLayout()); + llvmModule->setDataLayout(targetMachine.createDataLayout()); // Embed offload objects specified with -fembed-offload-object if (!codeGenOpts.OffloadObjects.empty()) @@ -1361,7 +1220,7 @@ void CodeGenAction::executeAction() { if (action == BackendActionTy::Backend_EmitAssembly || action == BackendActionTy::Backend_EmitObj) { generateMachineCodeOrAssemblyImpl( - diags, *tm, action, *llvmModule, codeGenOpts, + diags, targetMachine, action, *llvmModule, codeGenOpts, ci.isOutputStreamNull() ? *os : ci.getOutputStream()); return; } diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp index 1258e3b3ad42..7e64adc3c144 100644 --- a/flang/lib/Lower/Bridge.cpp +++ b/flang/lib/Lower/Bridge.cpp @@ -44,6 +44,7 @@ #include "flang/Optimizer/Dialect/FIROps.h" #include "flang/Optimizer/Dialect/Support/FIRContext.h" #include "flang/Optimizer/HLFIR/HLFIROps.h" +#include "flang/Optimizer/Support/DataLayout.h" #include "flang/Optimizer/Support/FatalError.h" #include "flang/Optimizer/Support/InternalNames.h" #include "flang/Optimizer/Transforms/Passes.h" @@ -5089,7 +5090,8 @@ Fortran::lower::LoweringBridge::LoweringBridge( fir::KindMapping &kindMap, const Fortran::lower::LoweringOptions &loweringOptions, const std::vector &envDefaults, - const Fortran::common::LanguageFeatureControl &languageFeatures) + const Fortran::common::LanguageFeatureControl &languageFeatures, + const llvm::DataLayout *dataLayout) : semanticsContext{semanticsContext}, defaultKinds{defaultKinds}, intrinsics{intrinsics}, targetCharacteristics{targetCharacteristics}, cooked{&cooked}, context{context}, kindMap{kindMap}, @@ -5145,4 +5147,6 @@ Fortran::lower::LoweringBridge::LoweringBridge( assert(module.get() && "module was not created"); fir::setTargetTriple(*module.get(), triple); fir::setKindMapping(*module.get(), kindMap); + if (dataLayout) + fir::support::setMLIRDataLayout(*module.get(), *dataLayout); } diff --git a/flang/lib/Lower/CallInterface.cpp b/flang/lib/Lower/CallInterface.cpp index b1420dcb25a1..1f41c3bec847 100644 --- a/flang/lib/Lower/CallInterface.cpp +++ b/flang/lib/Lower/CallInterface.cpp @@ -91,7 +91,7 @@ bool Fortran::lower::CallerInterface::requireDispatchCall() const { // polymorphic. if (const Fortran::evaluate::Component *component = procRef.proc().GetComponent()) { - if (Fortran::semantics::IsPolymorphic(component->GetFirstSymbol())) + if (Fortran::semantics::IsPolymorphic(component->base().GetLastSymbol())) return true; } // calls with PASS attribute have the passed-object already set in its diff --git a/flang/lib/Lower/ConvertCall.cpp b/flang/lib/Lower/ConvertCall.cpp index 0bdb4452e5eb..81f4c0a2c6d2 100644 --- a/flang/lib/Lower/ConvertCall.cpp +++ b/flang/lib/Lower/ConvertCall.cpp @@ -409,9 +409,11 @@ fir::ExtendedValue Fortran::lower::genCallOpAndResult( const Fortran::evaluate::Component *component = caller.getCallDescription().proc().GetComponent(); assert(component && "expect component for type-bound procedure call."); - fir::ExtendedValue pass = converter.getSymbolExtendedValue( - component->GetFirstSymbol(), &symMap); - mlir::Value passObject = fir::getBase(pass); + + fir::ExtendedValue dataRefValue = Fortran::lower::convertDataRefToValue( + loc, converter, component->base(), symMap, stmtCtx); + mlir::Value passObject = fir::getBase(dataRefValue); + if (fir::isa_ref_type(passObject.getType())) passObject = builder.create(loc, passObject); dispatch = builder.create( diff --git a/flang/lib/Lower/ConvertExprToHLFIR.cpp b/flang/lib/Lower/ConvertExprToHLFIR.cpp index b114fbe1a13a..7771b4a635f2 100644 --- a/flang/lib/Lower/ConvertExprToHLFIR.cpp +++ b/flang/lib/Lower/ConvertExprToHLFIR.cpp @@ -166,6 +166,13 @@ public: return builder.genShape(loc, lbounds, extents); } + fir::FortranVariableOpInterface + gen(const Fortran::evaluate::DataRef &dataRef) { + return std::visit( + Fortran::common::visitors{[&](const auto &x) { return gen(x); }}, + dataRef.u); + } + private: /// Struct that is filled while visiting a part-ref (in the "visit" member /// function) before the top level "gen" generates an hlfir.declare for the @@ -311,13 +318,6 @@ private: return genDesignate(resultType, partInfo, component); } - fir::FortranVariableOpInterface - gen(const Fortran::evaluate::DataRef &dataRef) { - return std::visit( - Fortran::common::visitors{[&](const auto &x) { return gen(x); }}, - dataRef.u); - } - fir::FortranVariableOpInterface gen(const Fortran::evaluate::ArrayRef &arrayRef) { PartInfo partInfo; @@ -1926,6 +1926,15 @@ fir::ExtendedValue Fortran::lower::convertExprToValue( return convertToValue(loc, converter, loweredExpr, stmtCtx); } +fir::ExtendedValue Fortran::lower::convertDataRefToValue( + mlir::Location loc, Fortran::lower::AbstractConverter &converter, + const Fortran::evaluate::DataRef &dataRef, Fortran::lower::SymMap &symMap, + Fortran::lower::StatementContext &stmtCtx) { + fir::FortranVariableOpInterface loweredExpr = + HlfirDesignatorBuilder(loc, converter, symMap, stmtCtx).gen(dataRef); + return convertToValue(loc, converter, loweredExpr, stmtCtx); +} + fir::MutableBoxValue Fortran::lower::convertExprToMutableBox( mlir::Location loc, Fortran::lower::AbstractConverter &converter, const Fortran::lower::SomeExpr &expr, Fortran::lower::SymMap &symMap) { diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp index 7bdb501e757c..676fecdb52a8 100644 --- a/flang/lib/Lower/ConvertVariable.cpp +++ b/flang/lib/Lower/ConvertVariable.cpp @@ -1331,6 +1331,28 @@ void Fortran::lower::defineCommonBlocks( finalizeCommonBlockDefinition(loc, converter, global, cmnBlkMems); } +mlir::Value Fortran::lower::genCommonBlockMember( + Fortran::lower::AbstractConverter &converter, mlir::Location loc, + const Fortran::semantics::Symbol &sym, mlir::Value commonValue) { + fir::FirOpBuilder &builder = converter.getFirOpBuilder(); + + std::size_t byteOffset = sym.GetUltimate().offset(); + mlir::IntegerType i8Ty = builder.getIntegerType(8); + mlir::Type i8Ptr = builder.getRefType(i8Ty); + mlir::Type seqTy = builder.getRefType(builder.getVarLenSeqTy(i8Ty)); + mlir::Value base = builder.createConvert(loc, seqTy, commonValue); + + mlir::Value offs = + builder.createIntegerConstant(loc, builder.getIndexType(), byteOffset); + mlir::Value varAddr = builder.create( + loc, i8Ptr, base, mlir::ValueRange{offs}); + mlir::Type symType = converter.genType(sym); + + return Fortran::semantics::FindEquivalenceSet(sym) != nullptr + ? castAliasToPointer(builder, loc, symType, varAddr) + : builder.createConvert(loc, builder.getRefType(symType), varAddr); +} + /// The COMMON block is a global structure. `var` will be at some offset /// within the COMMON block. Adds the address of `var` (COMMON + offset) to /// the symbol map. @@ -1353,21 +1375,8 @@ static void instantiateCommon(Fortran::lower::AbstractConverter &converter, symMap.addSymbol(common, commonAddr); } - std::size_t byteOffset = varSym.GetUltimate().offset(); - mlir::IntegerType i8Ty = builder.getIntegerType(8); - mlir::Type i8Ptr = builder.getRefType(i8Ty); - mlir::Type seqTy = builder.getRefType(builder.getVarLenSeqTy(i8Ty)); - mlir::Value base = builder.createConvert(loc, seqTy, commonAddr); - mlir::Value offs = - builder.createIntegerConstant(loc, builder.getIndexType(), byteOffset); - auto varAddr = builder.create(loc, i8Ptr, base, - mlir::ValueRange{offs}); - mlir::Type symType = converter.genType(var.getSymbol()); - mlir::Value local; - if (Fortran::semantics::FindEquivalenceSet(var.getSymbol()) != nullptr) - local = castAliasToPointer(builder, loc, symType, varAddr); - else - local = builder.createConvert(loc, builder.getRefType(symType), varAddr); + + mlir::Value local = genCommonBlockMember(converter, loc, varSym, commonAddr); Fortran::lower::StatementContext stmtCtx; mapSymbolAttributes(converter, var, symMap, stmtCtx, local); } diff --git a/flang/lib/Lower/OpenMP.cpp b/flang/lib/Lower/OpenMP.cpp index adbc277d6b01..0fa1ac76d57e 100644 --- a/flang/lib/Lower/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP.cpp @@ -1959,31 +1959,6 @@ static mlir::Operation *getCompareFromReductionOp(mlir::Operation *reductionOp, return nullptr; } -/// The COMMON block is a global structure. \p commonValue is the base address -/// of the COMMON block. As the offset from the symbol \p sym, generate the -/// COMMON block member value (commonValue + offset) for the symbol. -/// FIXME: Share the code with `instantiateCommon` in ConvertVariable.cpp. -static mlir::Value -genCommonBlockMember(Fortran::lower::AbstractConverter &converter, - const Fortran::semantics::Symbol &sym, - mlir::Value commonValue) { - fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); - mlir::Location currentLocation = converter.getCurrentLocation(); - mlir::IntegerType i8Ty = firOpBuilder.getIntegerType(8); - mlir::Type i8Ptr = firOpBuilder.getRefType(i8Ty); - mlir::Type seqTy = firOpBuilder.getRefType(firOpBuilder.getVarLenSeqTy(i8Ty)); - mlir::Value base = - firOpBuilder.createConvert(currentLocation, seqTy, commonValue); - std::size_t byteOffset = sym.GetUltimate().offset(); - mlir::Value offs = firOpBuilder.createIntegerConstant( - currentLocation, firOpBuilder.getIndexType(), byteOffset); - mlir::Value varAddr = firOpBuilder.create( - currentLocation, i8Ptr, base, mlir::ValueRange{offs}); - mlir::Type symType = converter.genType(sym); - return firOpBuilder.createConvert(currentLocation, - firOpBuilder.getRefType(symType), varAddr); -} - // Get the extended value for \p val by extracting additional variable // information from \p base. static fir::ExtendedValue getExtendedValue(fir::ExtendedValue base, @@ -2049,8 +2024,8 @@ static void threadPrivatizeVars(Fortran::lower::AbstractConverter &converter, converter.bindSymbol(*common, commonThreadprivateValue); commonSyms.insert(common); } - symThreadprivateValue = - genCommonBlockMember(converter, *sym, commonThreadprivateValue); + symThreadprivateValue = Fortran::lower::genCommonBlockMember( + converter, currentLocation, *sym, commonThreadprivateValue); } else { symThreadprivateValue = genThreadprivateOp(*sym); } @@ -3554,8 +3529,8 @@ void Fortran::lower::genThreadprivateOp( currentLocation, commonValue.getType(), commonValue); converter.bindSymbol(*common, commonThreadprivateValue); // Generate the threadprivate value for the common block member. - symThreadprivateValue = - genCommonBlockMember(converter, sym, commonThreadprivateValue); + symThreadprivateValue = genCommonBlockMember(converter, currentLocation, + sym, commonThreadprivateValue); } else if (!var.isGlobal()) { // Non-global variable which can be in threadprivate directive must be one // variable in main program, and it has implicit SAVE attribute. Take it as diff --git a/flang/lib/Optimizer/CodeGen/CodeGen.cpp b/flang/lib/Optimizer/CodeGen/CodeGen.cpp index 408377f1d7a1..bf175c8ebade 100644 --- a/flang/lib/Optimizer/CodeGen/CodeGen.cpp +++ b/flang/lib/Optimizer/CodeGen/CodeGen.cpp @@ -840,16 +840,18 @@ struct CmpcOpConversion : public FIROpConversion { mlir::ValueRange operands = adaptor.getOperands(); mlir::Type resTy = convertType(cmp.getType()); mlir::Location loc = cmp.getLoc(); - llvm::SmallVector rp = { + mlir::LLVM::FastmathFlags fmf = + mlir::arith::convertArithFastMathFlagsToLLVM(cmp.getFastmath()); + mlir::LLVM::FCmpPredicate pred = + static_cast(cmp.getPredicate()); + auto rcp = rewriter.create( + loc, resTy, pred, rewriter.create(loc, operands[0], 0), - rewriter.create(loc, operands[1], 0)}; - auto rcp = - rewriter.create(loc, resTy, rp, cmp->getAttrs()); - llvm::SmallVector ip = { + rewriter.create(loc, operands[1], 0), fmf); + auto icp = rewriter.create( + loc, resTy, pred, rewriter.create(loc, operands[0], 1), - rewriter.create(loc, operands[1], 1)}; - auto icp = - rewriter.create(loc, resTy, ip, cmp->getAttrs()); + rewriter.create(loc, operands[1], 1), fmf); llvm::SmallVector cp = {rcp, icp}; switch (cmp.getPredicate()) { case mlir::arith::CmpFPredicate::OEQ: // .EQ. diff --git a/flang/lib/Optimizer/Support/CMakeLists.txt b/flang/lib/Optimizer/Support/CMakeLists.txt index 2d03bc52c83f..55f5718a90b8 100644 --- a/flang/lib/Optimizer/Support/CMakeLists.txt +++ b/flang/lib/Optimizer/Support/CMakeLists.txt @@ -2,6 +2,7 @@ get_property(dialect_libs GLOBAL PROPERTY MLIR_DIALECT_LIBS) get_property(extension_libs GLOBAL PROPERTY MLIR_EXTENSION_LIBS) add_flang_library(FIRSupport + DataLayout.cpp InitFIR.cpp InternalNames.cpp @@ -20,6 +21,7 @@ add_flang_library(FIRSupport MLIROpenMPToLLVMIRTranslation MLIRLLVMToLLVMIRTranslation MLIRTargetLLVMIRExport + MLIRTargetLLVMIRImport LINK_COMPONENTS TargetParser diff --git a/flang/lib/Optimizer/Support/DataLayout.cpp b/flang/lib/Optimizer/Support/DataLayout.cpp new file mode 100644 index 000000000000..5cd9c01e8ce0 --- /dev/null +++ b/flang/lib/Optimizer/Support/DataLayout.cpp @@ -0,0 +1,47 @@ +//===-- Optimizer/Support/DataLayout.cpp ----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "flang/Optimizer/Support/DataLayout.h" +#include "flang/Optimizer/Dialect/Support/FIRContext.h" +#include "flang/Optimizer/Support/FatalError.h" +#include "mlir/Dialect/DLTI/DLTI.h" +#include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/IR/BuiltinOps.h" +#include "mlir/Interfaces/DataLayoutInterfaces.h" +#include "mlir/Support/LLVM.h" +#include "mlir/Target/LLVMIR/Import.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/MC/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Target/TargetMachine.h" + +void fir::support::setMLIRDataLayout(mlir::ModuleOp mlirModule, + const llvm::DataLayout &dl) { + mlir::MLIRContext *context = mlirModule.getContext(); + mlirModule->setAttr( + mlir::LLVM::LLVMDialect::getDataLayoutAttrName(), + mlir::StringAttr::get(context, dl.getStringRepresentation())); + mlir::DataLayoutSpecInterface dlSpec = mlir::translateDataLayout(dl, context); + mlirModule->setAttr(mlir::DLTIDialect::kDataLayoutAttrName, dlSpec); +} + +void fir::support::setMLIRDataLayoutFromAttributes(mlir::ModuleOp mlirModule, + bool allowDefaultLayout) { + if (mlirModule.getDataLayoutSpec()) + return; // Already set. + if (auto dataLayoutString = mlirModule->getAttrOfType( + mlir::LLVM::LLVMDialect::getDataLayoutAttrName())) { + llvm::DataLayout llvmDataLayout(dataLayoutString); + fir::support::setMLIRDataLayout(mlirModule, llvmDataLayout); + return; + } + if (!allowDefaultLayout) + return; + llvm::DataLayout llvmDataLayout(""); + fir::support::setMLIRDataLayout(mlirModule, llvmDataLayout); +} diff --git a/flang/runtime/ISO_Fortran_binding.cpp b/flang/runtime/ISO_Fortran_binding.cpp index ce146844533a..99ba3aa56fee 100644 --- a/flang/runtime/ISO_Fortran_binding.cpp +++ b/flang/runtime/ISO_Fortran_binding.cpp @@ -75,7 +75,7 @@ RT_API_ATTRS int CFI_allocate(CFI_cdesc_t *descriptor, dim->sm = byteSize; byteSize *= extent; } - void *p{std::malloc(byteSize)}; + void *p{byteSize ? std::malloc(byteSize) : std::malloc(1)}; if (!p && byteSize) { return CFI_ERROR_MEM_ALLOCATION; } diff --git a/flang/runtime/exceptions.cpp b/flang/runtime/exceptions.cpp index 797d0c87e601..1dbee833884f 100644 --- a/flang/runtime/exceptions.cpp +++ b/flang/runtime/exceptions.cpp @@ -77,12 +77,8 @@ std::int32_t RTNAME(MapException)(int32_t except) { // Verify that the size of ieee_modes_type and ieee_status_type objects from // intrinsic module file __fortran_ieee_exceptions.f90 are large enough to -// hold femode_t and fenv_t objects, respectively. -#ifndef _WIN32 -static_assert( - sizeof(femode_t) <= sizeof(int) * _FORTRAN_RUNTIME_IEEE_FEMODE_T_EXTENT, - "increase ieee_modes_type size"); -#endif +// hold fenv_t object. +// TODO: consider femode_t object size comparison once its more mature. static_assert( sizeof(fenv_t) <= sizeof(int) * _FORTRAN_RUNTIME_IEEE_FENV_T_EXTENT, "increase ieee_status_type size"); diff --git a/flang/runtime/unit.cpp b/flang/runtime/unit.cpp index 995656b9480c..5fa8565c2f61 100644 --- a/flang/runtime/unit.cpp +++ b/flang/runtime/unit.cpp @@ -20,6 +20,7 @@ namespace Fortran::runtime::io { // The per-unit data structures are created on demand so that Fortran I/O // should work without a Fortran main program. static Lock unitMapLock; +static Lock createOpenLock; static UnitMap *unitMap{nullptr}; static ExternalFileUnit *defaultInput{nullptr}; // unit 5 static ExternalFileUnit *defaultOutput{nullptr}; // unit 6 @@ -52,6 +53,9 @@ ExternalFileUnit *ExternalFileUnit::LookUpOrCreate( ExternalFileUnit *ExternalFileUnit::LookUpOrCreateAnonymous(int unit, Direction dir, std::optional isUnformatted, const Terminator &terminator) { + // Make sure that the returned anonymous unit has been opened + // not just created in the unitMap. + CriticalSection critical{createOpenLock}; bool exists{false}; ExternalFileUnit *result{ GetUnitMap().LookUpOrCreate(unit, terminator, exists)}; diff --git a/flang/test/Driver/compiler_options.f90 b/flang/test/Driver/compiler-options.f90 similarity index 90% rename from flang/test/Driver/compiler_options.f90 rename to flang/test/Driver/compiler-options.f90 index 3edebb915c09..d0bafbffafdf 100644 --- a/flang/test/Driver/compiler_options.f90 +++ b/flang/test/Driver/compiler-options.f90 @@ -1,6 +1,6 @@ ! RUN: %flang -S -emit-llvm -flang-deprecated-no-hlfir -o - %s | FileCheck %s ! Test communication of COMPILER_OPTIONS from flang-new to flang-new -fc1. -! CHECK: [[OPTSVAR:@_QQclX[0-9a-f]+]] = {{[a-z]+}} constant [[[OPTSLEN:[0-9]+]] x i8] c"{{.*}}flang-new{{(\.exe)?}} -S -emit-llvm -flang-deprecated-no-hlfir -o - {{.*}}compiler_options.f90" +! CHECK: [[OPTSVAR:@_QQclX[0-9a-f]+]] = {{[a-z]+}} constant [[[OPTSLEN:[0-9]+]] x i8] c"{{.*}}flang-new{{(\.exe)?}} -S -emit-llvm -flang-deprecated-no-hlfir -o - {{.*}}compiler-options.f90" program main use ISO_FORTRAN_ENV, only: compiler_options implicit none diff --git a/flang/test/Driver/driver-help-hidden.f90 b/flang/test/Driver/driver-help-hidden.f90 index f420f1ef3290..8cb8b54d5941 100644 --- a/flang/test/Driver/driver-help-hidden.f90 +++ b/flang/test/Driver/driver-help-hidden.f90 @@ -26,7 +26,6 @@ ! CHECK-NEXT: -D = Define to (or 1 if omitted) ! CHECK-NEXT: -emit-llvm Use the LLVM representation for assembler and object files ! CHECK-NEXT: -E Only run the preprocessor -! CHECK-NEXT: -falias-analysis Pass alias information on to LLVM (default when optimizing for speed) ! CHECK-NEXT: -falternative-parameter-statement ! CHECK-NEXT: Enable the old style PARAMETER statement ! CHECK-NEXT: -fapprox-func Allow certain math function calls to be replaced with an approximately equivalent calculation @@ -63,7 +62,6 @@ ! CHECK-NEXT: -flto Enable LTO in 'full' mode ! CHECK-NEXT: -fms-runtime-lib= ! CHECK-NEXT: Select Windows run-time library -! CHECK-NEXT: -fno-alias-analysis Do not pass alias information on to LLVM (default for unoptimized builds) ! CHECK-NEXT: -fno-automatic Implies the SAVE attribute for non-automatic local objects in subprograms unless RECURSIVE ! CHECK-NEXT: -fno-color-diagnostics Disable colors in diagnostics ! CHECK-NEXT: -fno-integrated-as Disable the integrated assembler diff --git a/flang/test/Driver/driver-help.f90 b/flang/test/Driver/driver-help.f90 index 23197e8d4890..0607ffde2378 100644 --- a/flang/test/Driver/driver-help.f90 +++ b/flang/test/Driver/driver-help.f90 @@ -22,7 +22,6 @@ ! HELP-NEXT: -D = Define to (or 1 if omitted) ! HELP-NEXT: -emit-llvm Use the LLVM representation for assembler and object files ! HELP-NEXT: -E Only run the preprocessor -! HELP-NEXT: -falias-analysis Pass alias information on to LLVM (default when optimizing for speed) ! HELP-NEXT: -falternative-parameter-statement ! HELP-NEXT: Enable the old style PARAMETER statement ! HELP-NEXT: -fapprox-func Allow certain math function calls to be replaced with an approximately equivalent calculation @@ -53,7 +52,6 @@ ! HELP-NEXT: -flto Enable LTO in 'full' mode ! HELP-NEXT: -fms-runtime-lib= ! HELP-NEXT: Select Windows run-time library -! HELP-NEXT: -fno-alias-analysis Do not pass alias information on to LLVM (default for unoptimized builds) ! HELP-NEXT: -fno-automatic Implies the SAVE attribute for non-automatic local objects in subprograms unless RECURSIVE ! HELP-NEXT: -fno-color-diagnostics Disable colors in diagnostics ! HELP-NEXT: -fno-integrated-as Disable the integrated assembler @@ -152,7 +150,6 @@ ! HELP-FC1-NEXT: -emit-llvm Use the LLVM representation for assembler and object files ! HELP-FC1-NEXT: -emit-obj Emit native object files ! HELP-FC1-NEXT: -E Only run the preprocessor -! HELP-FC1-NEXT: -falias-analysis Pass alias information on to LLVM (default when optimizing for speed) ! HELP-FC1-NEXT: -falternative-parameter-statement ! HELP-FC1-NEXT: Enable the old style PARAMETER statement ! HELP-FC1-NEXT: -fapprox-func Allow certain math function calls to be replaced with an approximately equivalent calculation @@ -199,7 +196,6 @@ ! HELP-FC1-NEXT: -flogical-abbreviations Enable logical abbreviations ! HELP-FC1-NEXT: -flto= Set LTO mode ! HELP-FC1-NEXT: -flto Enable LTO in 'full' mode -! HELP-FC1-NEXT: -fno-alias-analysis Do not pass alias information on to LLVM (default for unoptimized builds) ! HELP-FC1-NEXT: -fno-analyzed-objects-for-unparse ! HELP-FC1-NEXT: Do not use the analyzed objects when unparsing ! HELP-FC1-NEXT: -fno-automatic Implies the SAVE attribute for non-automatic local objects in subprograms unless RECURSIVE diff --git a/flang/test/Driver/falias-analysis.f90 b/flang/test/Driver/falias-analysis.f90 index 3bd389c33dbc..fd2ac9d4d0da 100644 --- a/flang/test/Driver/falias-analysis.f90 +++ b/flang/test/Driver/falias-analysis.f90 @@ -1,27 +1,20 @@ -! Check that -falias-analysis and -fno-alias-analysis work as expected +! Check that tbaa tags are enabled and disabled with optimization flags as expected ! See flang/test/Fir/tbaa-codegen.fir for a test that the output is correct -! RUN: %flang -c -emit-llvm -falias-analysis %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-AA --check-prefix=CHECK-ALL ! RUN: %flang -c -emit-llvm -Ofast %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-AA --check-prefix=CHECK-ALL ! RUN: %flang -c -emit-llvm -O3 %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-AA --check-prefix=CHECK-ALL ! RUN: %flang -c -emit-llvm -O2 %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-AA --check-prefix=CHECK-ALL ! RUN: %flang -c -emit-llvm -O1 %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-AA --check-prefix=CHECK-ALL ! RUN: %flang -c -emit-llvm -O0 %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-NOAA --check-prefix=CHECK-ALL -! RUN: %flang -c -emit-llvm -Ofast -fno-alias-analysis %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-NOAA --check-prefix=CHECK-ALL -! RUN: %flang -c -emit-llvm -fno-alias-analysis -Ofast %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-NOAA --check-prefix=CHECK-ALL ! RUN: %flang -c -emit-llvm %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-NOAA --check-prefix=CHECK-ALL -! RUN: %flang -c -emit-llvm -falias-analysis -fno-alias-analysis %s -o - | llvm-dis | FileCheck %s --check-prefix=CHECK-NOAA --check-prefix=CHECK-ALL -! RUN: %flang -fc1 -emit-llvm -falias-analysis %s -o - | FileCheck %s --check-prefix=CHECK-AA --check-prefix=CHECK-ALL ! RUN: %flang -fc1 -emit-llvm -O3 %s -o - | FileCheck %s --check-prefix=CHECK-AA --check-prefix=CHECK-ALL ! RUN: %flang -fc1 -emit-llvm -O2 %s -o - | FileCheck %s --check-prefix=CHECK-AA --check-prefix=CHECK-ALL ! RUN: %flang -fc1 -emit-llvm -O1 %s -o - | FileCheck %s --check-prefix=CHECK-AA --check-prefix=CHECK-ALL ! RUN: %flang -fc1 -emit-llvm -O0 %s -o - | FileCheck %s --check-prefix=CHECK-NOAA --check-prefix=CHECK-ALL -! RUN: %flang -fc1 -emit-llvm -falias-analysis -fno-alias-analysis %s -o - | FileCheck %s --check-prefix=CHECK-NOAA --check-prefix=CHECK-ALL ! RUN: %flang -fc1 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-NOAA --check-prefix=CHECK-ALL -! RUN: %flang -fc1 -emit-llvm -O3 -fno-alias-analysis %s -o - | FileCheck %s --check-prefix=CHECK-NOAA --check-prefix=CHECK-ALL subroutine simple(a) integer, intent(inout) :: a(:) diff --git a/flang/test/Driver/fast_math.f90 b/flang/test/Driver/fast-math.f90 similarity index 100% rename from flang/test/Driver/fast_math.f90 rename to flang/test/Driver/fast-math.f90 diff --git a/flang/test/Driver/flang_f_opts.f90 b/flang/test/Driver/flang-f-opts.f90 similarity index 100% rename from flang/test/Driver/flang_f_opts.f90 rename to flang/test/Driver/flang-f-opts.f90 diff --git a/flang/test/Driver/no_duplicate_main.f90 b/flang/test/Driver/no-duplicate-main.f90 similarity index 100% rename from flang/test/Driver/no_duplicate_main.f90 rename to flang/test/Driver/no-duplicate-main.f90 diff --git a/flang/test/Evaluate/fold-nearest.f90 b/flang/test/Evaluate/fold-nearest.f90 index f9daf7d69e9c..99af30312841 100644 --- a/flang/test/Evaluate/fold-nearest.f90 +++ b/flang/test/Evaluate/fold-nearest.f90 @@ -14,7 +14,9 @@ module m1 logical, parameter :: test_6 = nearest(-inf, -1.) == -inf logical, parameter :: test_7 = nearest(1.9999999, 1.) == 2. logical, parameter :: test_8 = nearest(2., -1.) == 1.9999999 +#if __x86_64__ logical, parameter :: test_9 = nearest(1.9999999999999999999_10, 1.) == 2._10 +#endif logical, parameter :: test_10 = nearest(-1., 1.) == -.99999994 logical, parameter :: test_11 = nearest(-1., -2.) == -1.0000001 real, parameter :: negZero = sign(0., -1.) @@ -42,7 +44,9 @@ module m2 logical, parameter :: test_8 = ieee_next_after(-inf, -1.) == -inf logical, parameter :: test_9 = ieee_next_after(1.9999999, 3.) == 2. logical, parameter :: test_10 = ieee_next_after(2., 1.) == 1.9999999 +#if __x86_64__ logical, parameter :: test_11 = ieee_next_after(1.9999999999999999999_10, 3.) == 2._10 +#endif logical, parameter :: test_12 = ieee_next_after(1., 1.) == 1. !WARN: warning: invalid argument on division real, parameter :: nan = 0. / 0. diff --git a/flang/test/Fir/convert-to-llvm.fir b/flang/test/Fir/convert-to-llvm.fir index c9a44914b987..993058ebb0a4 100644 --- a/flang/test/Fir/convert-to-llvm.fir +++ b/flang/test/Fir/convert-to-llvm.fir @@ -656,7 +656,7 @@ func.func @compare_complex_eq(%a : !fir.complex<8>, %b : !fir.complex<8>) -> i1 // CHECK: return [[RES]] : i1 func.func @compare_complex_ne(%a : !fir.complex<8>, %b : !fir.complex<8>) -> i1 { - %r = fir.cmpc "une", %a, %b : !fir.complex<8> + %r = fir.cmpc "une", %a, %b {fastmath = #arith.fastmath} : !fir.complex<8> return %r : i1 } @@ -667,13 +667,13 @@ func.func @compare_complex_ne(%a : !fir.complex<8>, %b : !fir.complex<8>) -> i1 // CHECK-DAG: [[IA:%.*]] = llvm.extractvalue [[A]][1] : !llvm.struct<(f64, f64)> // CHECK-DAG: [[RB:%.*]] = llvm.extractvalue [[B]][0] : !llvm.struct<(f64, f64)> // CHECK-DAG: [[IB:%.*]] = llvm.extractvalue [[B]][1] : !llvm.struct<(f64, f64)> -// CHECK-DAG: [[RESR:%.*]] = llvm.fcmp "une" [[RA]], [[RB]] : f64 -// CHECK-DAG: [[RESI:%.*]] = llvm.fcmp "une" [[IA]], [[IB]] : f64 +// CHECK-DAG: [[RESR:%.*]] = llvm.fcmp "une" [[RA]], [[RB]] {fastmathFlags = #llvm.fastmath} : f64 +// CHECK-DAG: [[RESI:%.*]] = llvm.fcmp "une" [[IA]], [[IB]] {fastmathFlags = #llvm.fastmath} : f64 // CHECK: [[RES:%.*]] = llvm.or [[RESR]], [[RESI]] : i1 // CHECK: return [[RES]] : i1 func.func @compare_complex_other(%a : !fir.complex<8>, %b : !fir.complex<8>) -> i1 { - %r = fir.cmpc "ogt", %a, %b : !fir.complex<8> + %r = fir.cmpc "ogt", %a, %b {fastmath = #arith.fastmath} : !fir.complex<8> return %r : i1 } @@ -682,7 +682,7 @@ func.func @compare_complex_other(%a : !fir.complex<8>, %b : !fir.complex<8>) -> // CHECK-SAME: [[B:%.*]]: !llvm.struct<(f64, f64)> // CHECK-DAG: [[RA:%.*]] = llvm.extractvalue [[A]][0] : !llvm.struct<(f64, f64)> // CHECK-DAG: [[RB:%.*]] = llvm.extractvalue [[B]][0] : !llvm.struct<(f64, f64)> -// CHECK: [[RESR:%.*]] = llvm.fcmp "ogt" [[RA]], [[RB]] : f64 +// CHECK: [[RESR:%.*]] = llvm.fcmp "ogt" [[RA]], [[RB]] {fastmathFlags = #llvm.fastmath} : f64 // CHECK: return [[RESR]] : i1 // ----- diff --git a/flang/test/Fir/dispatch.f90 b/flang/test/Fir/dispatch.f90 index 2c06377c9903..1dc71038813d 100644 --- a/flang/test/Fir/dispatch.f90 +++ b/flang/test/Fir/dispatch.f90 @@ -1,5 +1,5 @@ -! RUN: bbc -polymorphic-type -emit-fir -hlfir=false %s -o - | fir-opt --fir-polymorphic-op | FileCheck %s -! RUN: bbc -polymorphic-type -emit-fir -hlfir=false %s -o - | FileCheck %s --check-prefix=BT +! RUN: bbc -polymorphic-type -emit-hlfir %s -o - | fir-opt --fir-polymorphic-op | FileCheck %s +! RUN: bbc -polymorphic-type -emit-hlfir %s -o - | FileCheck %s --check-prefix=BT ! Tests codegen of fir.dispatch operation. This test is intentionally run from ! Fortran through bbc and tco so we have all the binding tables lowered to FIR @@ -184,61 +184,58 @@ end ! CHECK-LABEL: func.func @_QMdispatch1Pdisplay_class( ! CHECK-SAME: %[[ARG:.*]]: [[CLASS:!fir.class<.*>>]] - -! CHECK-DAG: %[[INT32:.*]] = fir.alloca i32 -! CHECK-DAG: %[[REAL:.*]] = fir.alloca f32 -! CHECK-DAG: %[[I:.*]] = fir.alloca i32 +! CHECK: %[[ARG_DECL:.*]]:2 = hlfir.declare %[[ARG]] {uniq_name = "_QMdispatch1Fdisplay_classEp"} : (!fir.class>) -> (!fir.class>, !fir.class>) ! Check dynamic dispatch equal to `call p%display2()` with binding index = 2. -! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG]] : ([[CLASS]]) -> !fir.tdesc +! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG_DECL]]#0 : ([[CLASS]]) -> !fir.tdesc ! CHECK: %[[TYPEDESCPTR:.*]] = fir.convert %[[BOXDESC]] : (!fir.tdesc) -> !fir.ref<[[TYPEINFO:!fir.type<_QM__fortran_type_infoTderivedtype{.*}>]]> ! CHECK: %[[BINDING_FIELD:.*]] = fir.field_index binding, [[TYPEINFO]] ! CHECK: %[[BINDING_BOX_ADDR:.*]] = fir.coordinate_of %[[TYPEDESCPTR]], %[[BINDING_FIELD]] : (!fir.ref<[[TYPEINFO]]>, !fir.field) -> !fir.ref<[[BINDING_BOX_TYPE:.*]]> ! CHECK: %[[BINDING_BOX:.*]] = fir.load %[[BINDING_BOX_ADDR]] : !fir.ref<[[BINDING_BOX_TYPE]]> ! CHECK: %[[BINDING_BASE_ADDR:.*]] = fir.box_addr %[[BINDING_BOX]] : ([[BINDING_BOX_TYPE]]) -> !fir.ptr<[[BINDINGSINFO:.*]]> -! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c2 : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> +! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c2{{.*}} : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> ! CHECK: %[[PROC_FIELD:.*]] = fir.field_index proc, [[BINDINGINFO]] ! CHECK: %[[BUILTIN_FUNC_PTR:.*]] = fir.coordinate_of %[[BINDING_PTR]], %[[PROC_FIELD]] : ({{.*}}) -> !fir.ref<[[BUILTIN_FUNC_TYPE:.*]]> ! CHECK: %[[ADDRESS_FIELD:.*]] = fir.field_index __address, [[BUILTIN_FUNC_TYPE]] ! CHECK: %[[FUNC_ADDR_PTR:.*]] = fir.coordinate_of %[[BUILTIN_FUNC_PTR]], %[[ADDRESS_FIELD]] ! CHECK: %[[FUNC_ADDR:.*]] = fir.load %[[FUNC_ADDR_PTR]] : !fir.ref ! CHECK: %[[FUNC_PTR:.*]] = fir.convert %[[FUNC_ADDR]] : (i64) -> (([[CLASS]]) -> ()) -! CHECK: fir.call %[[FUNC_PTR]](%[[ARG]]) : ([[CLASS]]) -> () +! CHECK: fir.call %[[FUNC_PTR]](%[[ARG_DECL]]#0) : (!fir.class>) -> () ! Check dynamic dispatch equal to `call p%display1()` with binding index = 1. -! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG]] : ([[CLASS]]) -> !fir.tdesc +! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG_DECL]]#0 : ([[CLASS]]) -> !fir.tdesc ! CHECK: %[[TYPEDESCPTR:.*]] = fir.convert %[[BOXDESC]] : (!fir.tdesc) -> !fir.ref<[[TYPEINFO:!fir.type<_QM__fortran_type_infoTderivedtype{.*}>]]> ! CHECK: %[[BINDING_FIELD:.*]] = fir.field_index binding, [[TYPEINFO]] ! CHECK: %[[BINDING_BOX_ADDR:.*]] = fir.coordinate_of %[[TYPEDESCPTR]], %[[BINDING_FIELD]] : (!fir.ref<[[TYPEINFO]]>, !fir.field) -> !fir.ref<[[BINDING_BOX_TYPE:.*]]> ! CHECK: %[[BINDING_BOX:.*]] = fir.load %[[BINDING_BOX_ADDR]] : !fir.ref<[[BINDING_BOX_TYPE]]> ! CHECK: %[[BINDING_BASE_ADDR:.*]] = fir.box_addr %[[BINDING_BOX]] : ([[BINDING_BOX_TYPE]]) -> !fir.ptr<[[BINDINGSINFO:.*]]> -! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c1 : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> +! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c1{{.*}} : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> ! CHECK: %[[PROC_FIELD:.*]] = fir.field_index proc, [[BINDINGINFO]] ! CHECK: %[[BUILTIN_FUNC_PTR:.*]] = fir.coordinate_of %[[BINDING_PTR]], %[[PROC_FIELD]] : ({{.*}}) -> !fir.ref<[[BUILTIN_FUNC_TYPE:.*]]> ! CHECK: %[[ADDRESS_FIELD:.*]] = fir.field_index __address, [[BUILTIN_FUNC_TYPE]] ! CHECK: %[[FUNC_ADDR_PTR:.*]] = fir.coordinate_of %[[BUILTIN_FUNC_PTR]], %[[ADDRESS_FIELD]] ! CHECK: %[[FUNC_ADDR:.*]] = fir.load %[[FUNC_ADDR_PTR]] : !fir.ref ! CHECK: %[[FUNC_PTR:.*]] = fir.convert %[[FUNC_ADDR]] : (i64) -> (([[CLASS]]) -> ()) -! CHECK: fir.call %[[FUNC_PTR]](%[[ARG]]) : ([[CLASS]]) -> () +! CHECK: fir.call %[[FUNC_PTR]](%[[ARG_DECL]]#0) : (!fir.class>) -> () ! Check dynamic dispatch equal to `call p%aproc()` with binding index = 0. -! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG]] : ([[CLASS]]) -> !fir.tdesc +! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG_DECL]]#0 : ([[CLASS]]) -> !fir.tdesc ! CHECK: %[[TYPEDESCPTR:.*]] = fir.convert %[[BOXDESC]] : (!fir.tdesc) -> !fir.ref<[[TYPEINFO:!fir.type<_QM__fortran_type_infoTderivedtype{.*}>]]> ! CHECK: %[[BINDING_FIELD:.*]] = fir.field_index binding, [[TYPEINFO]] ! CHECK: %[[BINDING_BOX_ADDR:.*]] = fir.coordinate_of %[[TYPEDESCPTR]], %[[BINDING_FIELD]] : (!fir.ref<[[TYPEINFO]]>, !fir.field) -> !fir.ref<[[BINDING_BOX_TYPE:.*]]> ! CHECK: %[[BINDING_BOX:.*]] = fir.load %[[BINDING_BOX_ADDR]] : !fir.ref<[[BINDING_BOX_TYPE]]> ! CHECK: %[[BINDING_BASE_ADDR:.*]] = fir.box_addr %[[BINDING_BOX]] : ([[BINDING_BOX_TYPE]]) -> !fir.ptr<[[BINDINGSINFO:.*]]> -! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c0 : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> +! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c0{{.*}}: (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> ! CHECK: %[[PROC_FIELD:.*]] = fir.field_index proc, [[BINDINGINFO]] ! CHECK: %[[BUILTIN_FUNC_PTR:.*]] = fir.coordinate_of %[[BINDING_PTR]], %[[PROC_FIELD]] : ({{.*}}) -> !fir.ref<[[BUILTIN_FUNC_TYPE:.*]]> ! CHECK: %[[ADDRESS_FIELD:.*]] = fir.field_index __address, [[BUILTIN_FUNC_TYPE]] ! CHECK: %[[FUNC_ADDR_PTR:.*]] = fir.coordinate_of %[[BUILTIN_FUNC_PTR]], %[[ADDRESS_FIELD]] ! CHECK: %[[FUNC_ADDR:.*]] = fir.load %[[FUNC_ADDR_PTR]] : !fir.ref ! CHECK: %[[FUNC_PTR:.*]] = fir.convert %[[FUNC_ADDR]] : (i64) -> (([[CLASS]]) -> ()) -! CHECK: fir.call %[[FUNC_PTR]](%[[ARG]]) : ([[CLASS]]) -> () +! CHECK: fir.call %[[FUNC_PTR]](%[[ARG_DECL]]#0) : (!fir.class>) -> () ! Check dynamic dispatch of a function with result. -! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG]] : ([[CLASS]]) -> !fir.tdesc +! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG_DECL]]#0 : ([[CLASS]]) -> !fir.tdesc ! CHECK: %[[TYPEDESCPTR:.*]] = fir.convert %[[BOXDESC]] : (!fir.tdesc) -> !fir.ref<[[TYPEINFO:!fir.type<_QM__fortran_type_infoTderivedtype{.*}>]]> ! CHECK: %[[BINDING_FIELD:.*]] = fir.field_index binding, [[TYPEINFO]] ! CHECK: %[[BINDING_BOX_ADDR:.*]] = fir.coordinate_of %[[TYPEDESCPTR]], %[[BINDING_FIELD]] : (!fir.ref<[[TYPEINFO]]>, !fir.field) -> !fir.ref<[[BINDING_BOX_TYPE:.*]]> @@ -251,32 +248,32 @@ end ! CHECK: %[[FUNC_ADDR_PTR:.*]] = fir.coordinate_of %[[BUILTIN_FUNC_PTR]], %[[ADDRESS_FIELD]] ! CHECK: %[[FUNC_ADDR:.*]] = fir.load %[[FUNC_ADDR_PTR]] : !fir.ref ! CHECK: %[[FUNC_PTR:.*]] = fir.convert %[[FUNC_ADDR]] : (i64) -> (([[CLASS]]) -> i32) -! CHECK: %[[RES:.*]] = fir.call %[[FUNC_PTR]](%[[ARG]]) : ([[CLASS]]) -> i32 +! CHECK: %[[RES:.*]] = fir.call %[[FUNC_PTR]](%[[ARG_DECL]]#0) : (!fir.class>) -> i32 ! Check dynamic dispatch of call with passed-object and additional argument -! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG]] : ([[CLASS]]) -> !fir.tdesc +! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG_DECL]]#0 : ([[CLASS]]) -> !fir.tdesc ! CHECK: %[[TYPEDESCPTR:.*]] = fir.convert %[[BOXDESC]] : (!fir.tdesc) -> !fir.ref<[[TYPEINFO:!fir.type<_QM__fortran_type_infoTderivedtype{.*}>]]> ! CHECK: %[[BINDING_FIELD:.*]] = fir.field_index binding, [[TYPEINFO]] ! CHECK: %[[BINDING_BOX_ADDR:.*]] = fir.coordinate_of %[[TYPEDESCPTR]], %[[BINDING_FIELD]] : (!fir.ref<[[TYPEINFO]]>, !fir.field) -> !fir.ref<[[BINDING_BOX_TYPE:.*]]> ! CHECK: %[[BINDING_BOX:.*]] = fir.load %[[BINDING_BOX_ADDR]] : !fir.ref<[[BINDING_BOX_TYPE]]> ! CHECK: %[[BINDING_BASE_ADDR:.*]] = fir.box_addr %[[BINDING_BOX]] : ([[BINDING_BOX_TYPE]]) -> !fir.ptr<[[BINDINGSINFO:.*]]> -! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c6 : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> +! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c6{{.*}} : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> ! CHECK: %[[PROC_FIELD:.*]] = fir.field_index proc, [[BINDINGINFO]] ! CHECK: %[[BUILTIN_FUNC_PTR:.*]] = fir.coordinate_of %[[BINDING_PTR]], %[[PROC_FIELD]] : ({{.*}}) -> !fir.ref<[[BUILTIN_FUNC_TYPE:.*]]> ! CHECK: %[[ADDRESS_FIELD:.*]] = fir.field_index __address, [[BUILTIN_FUNC_TYPE]] ! CHECK: %[[FUNC_ADDR_PTR:.*]] = fir.coordinate_of %[[BUILTIN_FUNC_PTR]], %[[ADDRESS_FIELD]] ! CHECK: %[[FUNC_ADDR:.*]] = fir.load %[[FUNC_ADDR_PTR]] : !fir.ref ! CHECK: %[[FUNC_PTR:.*]] = fir.convert %[[FUNC_ADDR]] : (i64) -> (([[CLASS]], !fir.ref) -> ()) -! CHECK: fir.call %[[FUNC_PTR]](%[[ARG]], %[[REAL]]) : ([[CLASS]], !fir.ref) -> () +! CHECK: fir.call %[[FUNC_PTR]](%[[ARG_DECL]]#0, %{{.*}}) : (!fir.class>, !fir.ref) -> () ! Check dynamic dispatch of a call with NOPASS -! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG]] : ([[CLASS]]) -> !fir.tdesc +! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG_DECL]]#1 : ([[CLASS]]) -> !fir.tdesc ! CHECK: %[[TYPEDESCPTR:.*]] = fir.convert %[[BOXDESC]] : (!fir.tdesc) -> !fir.ref<[[TYPEINFO:!fir.type<_QM__fortran_type_infoTderivedtype{.*}>]]> ! CHECK: %[[BINDING_FIELD:.*]] = fir.field_index binding, [[TYPEINFO]] ! CHECK: %[[BINDING_BOX_ADDR:.*]] = fir.coordinate_of %[[TYPEDESCPTR]], %[[BINDING_FIELD]] : (!fir.ref<[[TYPEINFO]]>, !fir.field) -> !fir.ref<[[BINDING_BOX_TYPE:.*]]> -! CHECK: %[[BINDING_BOX:.*]] = fir.load %[[BINDING_BOX_ADDR]] : !fir.ref<[[BINDING_BOX_TYPE]]> -! CHECK: %[[BINDING_BASE_ADDR:.*]] = fir.box_addr %[[BINDING_BOX]] : ([[BINDING_BOX_TYPE]]) -> !fir.ptr<[[BINDINGSINFO:.*]]> -! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c4 : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> +! CHECK: %[[BINDING_BOX:.*]] = fir.load %[[BINDING_BOX_ADDR]] : !fir.ref>>>> +! CHECK: %[[BINDING_BASE_ADDR:.*]] = fir.box_addr %[[BINDING_BOX]] : (!fir.box>> +! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c4{{.*}} : (!fir.ptr>>, index) -> !fir.ref> ! CHECK: %[[PROC_FIELD:.*]] = fir.field_index proc, [[BINDINGINFO]] ! CHECK: %[[BUILTIN_FUNC_PTR:.*]] = fir.coordinate_of %[[BINDING_PTR]], %[[PROC_FIELD]] : ({{.*}}) -> !fir.ref<[[BUILTIN_FUNC_TYPE:.*]]> ! CHECK: %[[ADDRESS_FIELD:.*]] = fir.field_index __address, [[BUILTIN_FUNC_TYPE]] @@ -285,20 +282,20 @@ end ! CHECK: %[[FUNC_PTR:.*]] = fir.convert %[[FUNC_ADDR]] : (i64) -> (() -> ()) ! CHECK: fir.call %[[FUNC_PTR]]() : () -> () -! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG]] : ([[CLASS]]) -> !fir.tdesc +! CHECK: %[[BOXDESC:.*]] = fir.box_tdesc %[[ARG_DECL]]#0 : ([[CLASS]]) -> !fir.tdesc ! CHECK: %[[TYPEDESCPTR:.*]] = fir.convert %[[BOXDESC]] : (!fir.tdesc) -> !fir.ref<[[TYPEINFO:!fir.type<_QM__fortran_type_infoTderivedtype{.*}>]]> ! CHECK: %[[BINDING_FIELD:.*]] = fir.field_index binding, [[TYPEINFO]] ! CHECK: %[[BINDING_BOX_ADDR:.*]] = fir.coordinate_of %[[TYPEDESCPTR]], %[[BINDING_FIELD]] : (!fir.ref<[[TYPEINFO]]>, !fir.field) -> !fir.ref<[[BINDING_BOX_TYPE:.*]]> ! CHECK: %[[BINDING_BOX:.*]] = fir.load %[[BINDING_BOX_ADDR]] : !fir.ref<[[BINDING_BOX_TYPE]]> ! CHECK: %[[BINDING_BASE_ADDR:.*]] = fir.box_addr %[[BINDING_BOX]] : ([[BINDING_BOX_TYPE]]) -> !fir.ptr<[[BINDINGSINFO:.*]]> -! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c5 : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> +! CHECK: %[[BINDING_PTR:.*]] = fir.coordinate_of %[[BINDING_BASE_ADDR]], %c5{{.*}} : (!fir.ptr<[[BINDINGSINFO]]>, index) -> !fir.ref<[[BINDINGINFO:.*]]> ! CHECK: %[[PROC_FIELD:.*]] = fir.field_index proc, [[BINDINGINFO]] ! CHECK: %[[BUILTIN_FUNC_PTR:.*]] = fir.coordinate_of %[[BINDING_PTR]], %[[PROC_FIELD]] : ({{.*}}) -> !fir.ref<[[BUILTIN_FUNC_TYPE:.*]]> ! CHECK: %[[ADDRESS_FIELD:.*]] = fir.field_index __address, [[BUILTIN_FUNC_TYPE]] ! CHECK: %[[FUNC_ADDR_PTR:.*]] = fir.coordinate_of %[[BUILTIN_FUNC_PTR]], %[[ADDRESS_FIELD]] ! CHECK: %[[FUNC_ADDR:.*]] = fir.load %[[FUNC_ADDR_PTR]] : !fir.ref ! CHECK: %[[FUNC_PTR:.*]] = fir.convert %[[FUNC_ADDR]] : (i64) -> ((!fir.ref, [[CLASS]]) -> ()) -! CHECK: fir.call %[[FUNC_PTR]](%[[INT32]], %[[ARG]]) : (!fir.ref, [[CLASS]]) -> () +! CHECK: fir.call %[[FUNC_PTR]](%{{.*}}, %[[ARG_DECL]]#0) : (!fir.ref, [[CLASS]]) -> () ! CHECK-LABEL: _QMdispatch1Pno_pass_array ! CHECK-LABEL: _QMdispatch1Pno_pass_array_allocatable diff --git a/flang/test/Fir/fir-ops.fir b/flang/test/Fir/fir-ops.fir index dd0fbb3be36c..3c4095b9fdb1 100644 --- a/flang/test/Fir/fir-ops.fir +++ b/flang/test/Fir/fir-ops.fir @@ -464,37 +464,37 @@ fir.type_info @test_type_info noinit nodestroy nofinal extends !fir.type, [[VAL_152:%.*]]: !fir.complex<16>) { func.func @compare_complex(%a : !fir.complex<16>, %b : !fir.complex<16>) { -// CHECK: [[VAL_153:%.*]] = fir.cmpc "false", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_154:%.*]] = fir.cmpc "oeq", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_155:%.*]] = fir.cmpc "ogt", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_156:%.*]] = fir.cmpc "oge", [[VAL_151]], [[VAL_152]] : !fir.complex<16> +// CHECK: [[VAL_153:%.*]] = fir.cmpc "false", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_154:%.*]] = fir.cmpc "oeq", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_155:%.*]] = fir.cmpc "ogt", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_156:%.*]] = fir.cmpc "oge", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> %d0 = fir.cmpc "false", %a, %b : !fir.complex<16> %d1 = fir.cmpc "oeq", %a, %b : !fir.complex<16> %d2 = fir.cmpc "ogt", %a, %b : !fir.complex<16> %d3 = fir.cmpc "oge", %a, %b : !fir.complex<16> -// CHECK: [[VAL_157:%.*]] = fir.cmpc "olt", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_158:%.*]] = fir.cmpc "ole", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_159:%.*]] = fir.cmpc "one", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_160:%.*]] = fir.cmpc "ord", [[VAL_151]], [[VAL_152]] : !fir.complex<16> +// CHECK: [[VAL_157:%.*]] = fir.cmpc "olt", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_158:%.*]] = fir.cmpc "ole", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_159:%.*]] = fir.cmpc "one", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_160:%.*]] = fir.cmpc "ord", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> %a0 = fir.cmpc "olt", %a, %b : !fir.complex<16> %a1 = fir.cmpc "ole", %a, %b : !fir.complex<16> %a2 = fir.cmpc "one", %a, %b : !fir.complex<16> %a3 = fir.cmpc "ord", %a, %b : !fir.complex<16> -// CHECK: [[VAL_161:%.*]] = fir.cmpc "ueq", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_162:%.*]] = fir.cmpc "ugt", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_163:%.*]] = fir.cmpc "uge", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_164:%.*]] = fir.cmpc "ult", [[VAL_151]], [[VAL_152]] : !fir.complex<16> +// CHECK: [[VAL_161:%.*]] = fir.cmpc "ueq", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_162:%.*]] = fir.cmpc "ugt", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_163:%.*]] = fir.cmpc "uge", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_164:%.*]] = fir.cmpc "ult", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> %b0 = fir.cmpc "ueq", %a, %b : !fir.complex<16> %b1 = fir.cmpc "ugt", %a, %b : !fir.complex<16> %b2 = fir.cmpc "uge", %a, %b : !fir.complex<16> %b3 = fir.cmpc "ult", %a, %b : !fir.complex<16> -// CHECK: [[VAL_165:%.*]] = fir.cmpc "ule", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_166:%.*]] = fir.cmpc "une", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_167:%.*]] = fir.cmpc "uno", [[VAL_151]], [[VAL_152]] : !fir.complex<16> -// CHECK: [[VAL_168:%.*]] = fir.cmpc "true", [[VAL_151]], [[VAL_152]] : !fir.complex<16> +// CHECK: [[VAL_165:%.*]] = fir.cmpc "ule", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_166:%.*]] = fir.cmpc "une", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_167:%.*]] = fir.cmpc "uno", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> +// CHECK: [[VAL_168:%.*]] = fir.cmpc "true", [[VAL_151]], [[VAL_152]] {fastmath = {{.*}}} : !fir.complex<16> %c0 = fir.cmpc "ule", %a, %b : !fir.complex<16> %c1 = fir.cmpc "une", %a, %b : !fir.complex<16> %c2 = fir.cmpc "uno", %a, %b : !fir.complex<16> diff --git a/flang/test/Fir/tco-default-datalayout.fir b/flang/test/Fir/tco-default-datalayout.fir new file mode 100644 index 000000000000..0741e820a8d1 --- /dev/null +++ b/flang/test/Fir/tco-default-datalayout.fir @@ -0,0 +1,12 @@ +// Test that tco tool sets a target independent data layout when none is +// provided. LLVM default data layout aligns i64 with 32 bits. +// RUN: tco -emit-fir %s | FileCheck %s + +module { +} +// CHECK: module attributes { +// CHECK-SAME: dlti.dl_spec = #dlti.dl_spec< +// ... +// CHECK-SAME: #dlti.dl_entry : vector<2xi64>>, +// ... +// CHECK-SAME: llvm.data_layout = "" diff --git a/flang/test/Fir/tco-explicit-datalayout.fir b/flang/test/Fir/tco-explicit-datalayout.fir new file mode 100644 index 000000000000..50d8d835a602 --- /dev/null +++ b/flang/test/Fir/tco-explicit-datalayout.fir @@ -0,0 +1,13 @@ +// Test that tco tool preserves incoming llvm.data_layout and creates a +// related dlti.dl_spec attribute. This tests a weird datalayout where +// i64 would be 128 bit aligned. +// RUN: tco -emit-fir %s | FileCheck %s + +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:128-i128:128-f80:128-n8:16:32:64-S128"} { +} +// CHECK: module attributes { +// CHECK-SAME: dlti.dl_spec = #dlti.dl_spec< +// ... +// CHECK-SAME: #dlti.dl_entry : vector<2xi64>>, +// ... +// CHECK-SAME: llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:128-i128:128-f80:128-n8:16:32:64-S128" diff --git a/flang/test/HLFIR/call_with_poly_dummy.f90 b/flang/test/HLFIR/call_with_poly_dummy.f90 index c4b98fbe5f55..af6876e26603 100644 --- a/flang/test/HLFIR/call_with_poly_dummy.f90 +++ b/flang/test/HLFIR/call_with_poly_dummy.f90 @@ -25,7 +25,7 @@ end subroutine test1 ! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = "_QFtest2Ex"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref ! CHECK: %[[VAL_3:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: %[[VAL_4:.*]] = arith.cmpf oeq, %[[VAL_2]], %[[VAL_3]] : f32 +! CHECK: %[[VAL_4:.*]] = arith.cmpf oeq, %[[VAL_2]], %[[VAL_3]] {{.*}} : f32 ! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i1) -> !fir.logical<4> ! CHECK: %[[VAL_6:.*]]:3 = hlfir.associate %[[VAL_5]] {adapt.valuebyref} : (!fir.logical<4>) -> (!fir.ref>, !fir.ref>, i1) ! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0 : (!fir.ref>) -> !fir.box> diff --git a/flang/test/Lower/HLFIR/binary-ops.f90 b/flang/test/Lower/HLFIR/binary-ops.f90 index 6b89577cc545..e0af9258cda3 100644 --- a/flang/test/Lower/HLFIR/binary-ops.f90 +++ b/flang/test/Lower/HLFIR/binary-ops.f90 @@ -246,7 +246,7 @@ end subroutine ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}}y" ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref -! CHECK: %[[VAL_8:.*]] = arith.cmpf oeq, %[[VAL_6]], %[[VAL_7]] : f32 +! CHECK: %[[VAL_8:.*]] = arith.cmpf oeq, %[[VAL_6]], %[[VAL_7]] {{.*}} : f32 subroutine cmp_real_2(l, x, y) logical :: l @@ -273,7 +273,7 @@ end subroutine ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare {{.*}}y" ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_4]]#0 : !fir.ref> ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref> -! CHECK: %[[VAL_8:.*]] = fir.cmpc "oeq", %[[VAL_6]], %[[VAL_7]] : !fir.complex<4> +! CHECK: %[[VAL_8:.*]] = fir.cmpc "oeq", %[[VAL_6]], %[[VAL_7]] {{.*}} : !fir.complex<4> subroutine cmp_char(l, x, y) logical :: l diff --git a/flang/test/Lower/HLFIR/user-defined-assignment.f90 b/flang/test/Lower/HLFIR/user-defined-assignment.f90 index a41044a60fd8..6f887cb00de3 100644 --- a/flang/test/Lower/HLFIR/user-defined-assignment.f90 +++ b/flang/test/Lower/HLFIR/user-defined-assignment.f90 @@ -101,7 +101,7 @@ end subroutine ! CHECK: ^bb0(%[[VAL_7:.*]]: index): ! CHECK: %[[VAL_8:.*]] = hlfir.designate %[[VAL_1]]#0 (%[[VAL_7]]) : (!fir.box>, index) -> !fir.ref ! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_8]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = arith.cmpf olt, %[[VAL_9]], %[[VAL_2]] : f32 +! CHECK: %[[VAL_10:.*]] = arith.cmpf olt, %[[VAL_9]], %[[VAL_2]] {{.*}} : f32 ! CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_10]] : (i1) -> !fir.logical<4> ! CHECK: hlfir.yield_element %[[VAL_11]] : !fir.logical<4> ! CHECK: } diff --git a/flang/test/Lower/Intrinsics/bessel_jn.f90 b/flang/test/Lower/Intrinsics/bessel_jn.f90 index 3fdef7446100..428733d547d7 100644 --- a/flang/test/Lower/Intrinsics/bessel_jn.f90 +++ b/flang/test/Lower/Intrinsics/bessel_jn.f90 @@ -42,7 +42,7 @@ subroutine test_transformational_real4(x, n1, n2, r) ! ALL-DAG: %[[x:.*]] = fir.load %[[argx]] : !fir.ref ! ALL-DAG: %[[n1:.*]] = fir.load %[[argn1]] : !fir.ref ! ALL-DAG: %[[n2:.*]] = fir.load %[[argn2]] : !fir.ref - ! ALL-DAG: %[[xeq0:.*]] = arith.cmpf ueq, %[[x]], %[[zero]] : f32 + ! ALL-DAG: %[[xeq0:.*]] = arith.cmpf ueq, %[[x]], %[[zero]] {{.*}} : f32 ! ALL-DAG: %[[n1ltn2:.*]] = arith.cmpi slt, %[[n1]], %[[n2]] : i32 ! ALL-DAG: %[[n1eqn2:.*]] = arith.cmpi eq, %[[n1]], %[[n2]] : i32 ! ALL: fir.if %[[xeq0]] { @@ -85,7 +85,7 @@ subroutine test_transformational_real8(x, n1, n2, r) ! ALL-DAG: %[[x:.*]] = fir.load %[[argx]] : !fir.ref ! ALL-DAG: %[[n1:.*]] = fir.load %[[argn1]] : !fir.ref ! ALL-DAG: %[[n2:.*]] = fir.load %[[argn2]] : !fir.ref - ! ALL-DAG: %[[xeq0:.*]] = arith.cmpf ueq, %[[x]], %[[zero]] : f64 + ! ALL-DAG: %[[xeq0:.*]] = arith.cmpf ueq, %[[x]], %[[zero]] {{.*}} : f64 ! ALL-DAG: %[[n1ltn2:.*]] = arith.cmpi slt, %[[n1]], %[[n2]] : i32 ! ALL-DAG: %[[n1eqn2:.*]] = arith.cmpi eq, %[[n1]], %[[n2]] : i32 ! ALL: fir.if %[[xeq0]] { diff --git a/flang/test/Lower/Intrinsics/bessel_yn.f90 b/flang/test/Lower/Intrinsics/bessel_yn.f90 index 9f4fbfbb89d3..ac77e4db5614 100644 --- a/flang/test/Lower/Intrinsics/bessel_yn.f90 +++ b/flang/test/Lower/Intrinsics/bessel_yn.f90 @@ -42,7 +42,7 @@ subroutine test_transformational_real4(x, n1, n2, r) ! ALL-DAG: %[[x:.*]] = fir.load %[[argx]] : !fir.ref ! ALL-DAG: %[[n1:.*]] = fir.load %[[argn1]] : !fir.ref ! ALL-DAG: %[[n2:.*]] = fir.load %[[argn2]] : !fir.ref - ! ALL-DAG: %[[xeq0:.*]] = arith.cmpf ueq, %[[x]], %[[zero]] : f32 + ! ALL-DAG: %[[xeq0:.*]] = arith.cmpf ueq, %[[x]], %[[zero]] {{.*}} : f32 ! ALL-DAG: %[[n1ltn2:.*]] = arith.cmpi slt, %[[n1]], %[[n2]] : i32 ! ALL-DAG: %[[n1eqn2:.*]] = arith.cmpi eq, %[[n1]], %[[n2]] : i32 ! ALL: fir.if %[[xeq0]] { @@ -85,7 +85,7 @@ subroutine test_transformational_real8(x, n1, n2, r) ! ALL-DAG: %[[x:.*]] = fir.load %[[argx]] : !fir.ref ! ALL-DAG: %[[n1:.*]] = fir.load %[[argn1]] : !fir.ref ! ALL-DAG: %[[n2:.*]] = fir.load %[[argn2]] : !fir.ref - ! ALL-DAG: %[[xeq0:.*]] = arith.cmpf ueq, %[[x]], %[[zero]] : f64 + ! ALL-DAG: %[[xeq0:.*]] = arith.cmpf ueq, %[[x]], %[[zero]] {{.*}} : f64 ! ALL-DAG: %[[n1ltn2:.*]] = arith.cmpi slt, %[[n1]], %[[n2]] : i32 ! ALL-DAG: %[[n1eqn2:.*]] = arith.cmpi eq, %[[n1]], %[[n2]] : i32 ! ALL: fir.if %[[xeq0]] { diff --git a/flang/test/Lower/Intrinsics/dim.f90 b/flang/test/Lower/Intrinsics/dim.f90 index 6b6d2179fad9..fb1a496570ca 100644 --- a/flang/test/Lower/Intrinsics/dim.f90 +++ b/flang/test/Lower/Intrinsics/dim.f90 @@ -8,7 +8,7 @@ subroutine dim_testr(x, y, z) ! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_1]] : !fir.ref ! CHECK: %[[VAL_5:.*]] = arith.constant 0.000000e+00 : f32 ! CHECK: %[[VAL_6:.*]] = arith.subf %[[VAL_3]], %[[VAL_4]] {{.*}}: f32 -! CHECK: %[[VAL_7:.*]] = arith.cmpf ogt, %[[VAL_6]], %[[VAL_5]] : f32 +! CHECK: %[[VAL_7:.*]] = arith.cmpf ogt, %[[VAL_6]], %[[VAL_5]] {{.*}} : f32 ! CHECK: %[[VAL_8:.*]] = arith.select %[[VAL_7]], %[[VAL_6]], %[[VAL_5]] : f32 ! CHECK: fir.store %[[VAL_8]] to %[[VAL_2]] : !fir.ref ! CHECK: return diff --git a/flang/test/Lower/Intrinsics/ieee_compare.f90 b/flang/test/Lower/Intrinsics/ieee_compare.f90 index a9fa97724e89..4249e4d16416 100644 --- a/flang/test/Lower/Intrinsics/ieee_compare.f90 +++ b/flang/test/Lower/Intrinsics/ieee_compare.f90 @@ -39,7 +39,7 @@ program p ! CHECK-DAG: %[[V_182:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_181]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK-DAG: %[[V_183:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_180]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK: %[[V_184:[0-9]+]] = arith.ori %[[V_183]], %[[V_182]] : i1 - ! CHECK: %[[V_185:[0-9]+]] = arith.cmpf oeq, %[[V_180]], %[[V_181]] : f32 + ! CHECK: %[[V_185:[0-9]+]] = arith.cmpf oeq, %[[V_180]], %[[V_181]] {{.*}} : f32 ! CHECK: fir.if %[[V_184]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -60,7 +60,7 @@ program p ! CHECK-DAG: %[[V_214:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_213]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK-DAG: %[[V_215:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_212]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK: %[[V_216:[0-9]+]] = arith.ori %[[V_215]], %[[V_214]] : i1 - ! CHECK: %[[V_217:[0-9]+]] = arith.cmpf oge, %[[V_212]], %[[V_213]] : f32 + ! CHECK: %[[V_217:[0-9]+]] = arith.cmpf oge, %[[V_212]], %[[V_213]] {{.*}} : f32 ! CHECK: fir.if %[[V_216]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -81,7 +81,7 @@ program p ! CHECK-DAG: %[[V_246:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_245]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK-DAG: %[[V_247:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_244]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK: %[[V_248:[0-9]+]] = arith.ori %[[V_247]], %[[V_246]] : i1 - ! CHECK: %[[V_249:[0-9]+]] = arith.cmpf ogt, %[[V_244]], %[[V_245]] : f32 + ! CHECK: %[[V_249:[0-9]+]] = arith.cmpf ogt, %[[V_244]], %[[V_245]] {{.*}} : f32 ! CHECK: fir.if %[[V_248]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -102,7 +102,7 @@ program p ! CHECK-DAG: %[[V_278:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_277]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK-DAG: %[[V_279:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_276]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK: %[[V_280:[0-9]+]] = arith.ori %[[V_279]], %[[V_278]] : i1 - ! CHECK: %[[V_281:[0-9]+]] = arith.cmpf ole, %[[V_276]], %[[V_277]] : f32 + ! CHECK: %[[V_281:[0-9]+]] = arith.cmpf ole, %[[V_276]], %[[V_277]] {{.*}} : f32 ! CHECK: fir.if %[[V_280]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -123,7 +123,7 @@ program p ! CHECK-DAG: %[[V_310:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_309]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK-DAG: %[[V_311:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_308]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK: %[[V_312:[0-9]+]] = arith.ori %[[V_311]], %[[V_310]] : i1 - ! CHECK: %[[V_313:[0-9]+]] = arith.cmpf olt, %[[V_308]], %[[V_309]] : f32 + ! CHECK: %[[V_313:[0-9]+]] = arith.cmpf olt, %[[V_308]], %[[V_309]] {{.*}} : f32 ! CHECK: fir.if %[[V_312]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -144,7 +144,7 @@ program p ! CHECK-DAG: %[[V_342:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_341]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK-DAG: %[[V_343:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_340]]) <{bit = 1 : i32}> : (f32) -> i1 ! CHECK: %[[V_344:[0-9]+]] = arith.ori %[[V_343]], %[[V_342]] : i1 - ! CHECK: %[[V_345:[0-9]+]] = arith.cmpf une, %[[V_340]], %[[V_341]] : f32 + ! CHECK: %[[V_345:[0-9]+]] = arith.cmpf une, %[[V_340]], %[[V_341]] {{.*}} : f32 ! CHECK: fir.if %[[V_344]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -162,8 +162,8 @@ program p ! CHECK: %[[V_371:[0-9]+]] = fir.array_coor %[[V_62]](%[[V_61]]) %[[V_370]] : (!fir.ref>, !fir.shape<1>, i64) -> !fir.ref ! CHECK: %[[V_372:[0-9]+]] = fir.load %[[V_368]] : !fir.ref ! CHECK: %[[V_373:[0-9]+]] = fir.load %[[V_371]] : !fir.ref - ! CHECK: %[[V_374:[0-9]+]] = arith.cmpf uno, %[[V_372]], %[[V_373]] : f32 - ! CHECK: %[[V_375:[0-9]+]] = arith.cmpf oeq, %[[V_372]], %[[V_373]] : f32 + ! CHECK: %[[V_374:[0-9]+]] = arith.cmpf uno, %[[V_372]], %[[V_373]] {{.*}} : f32 + ! CHECK: %[[V_375:[0-9]+]] = arith.cmpf oeq, %[[V_372]], %[[V_373]] {{.*}} : f32 ! CHECK: fir.if %[[V_374]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -181,8 +181,8 @@ program p ! CHECK: %[[V_400:[0-9]+]] = fir.array_coor %[[V_62]](%[[V_61]]) %[[V_399]] : (!fir.ref>, !fir.shape<1>, i64) -> !fir.ref ! CHECK: %[[V_401:[0-9]+]] = fir.load %[[V_397]] : !fir.ref ! CHECK: %[[V_402:[0-9]+]] = fir.load %[[V_400]] : !fir.ref - ! CHECK: %[[V_403:[0-9]+]] = arith.cmpf uno, %[[V_401]], %[[V_402]] : f32 - ! CHECK: %[[V_404:[0-9]+]] = arith.cmpf oge, %[[V_401]], %[[V_402]] : f32 + ! CHECK: %[[V_403:[0-9]+]] = arith.cmpf uno, %[[V_401]], %[[V_402]] {{.*}} : f32 + ! CHECK: %[[V_404:[0-9]+]] = arith.cmpf oge, %[[V_401]], %[[V_402]] {{.*}} : f32 ! CHECK: fir.if %[[V_403]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -200,8 +200,8 @@ program p ! CHECK: %[[V_429:[0-9]+]] = fir.array_coor %[[V_62]](%[[V_61]]) %[[V_428]] : (!fir.ref>, !fir.shape<1>, i64) -> !fir.ref ! CHECK: %[[V_430:[0-9]+]] = fir.load %[[V_426]] : !fir.ref ! CHECK: %[[V_431:[0-9]+]] = fir.load %[[V_429]] : !fir.ref - ! CHECK: %[[V_432:[0-9]+]] = arith.cmpf uno, %[[V_430]], %[[V_431]] : f32 - ! CHECK: %[[V_433:[0-9]+]] = arith.cmpf ogt, %[[V_430]], %[[V_431]] : f32 + ! CHECK: %[[V_432:[0-9]+]] = arith.cmpf uno, %[[V_430]], %[[V_431]] {{.*}} : f32 + ! CHECK: %[[V_433:[0-9]+]] = arith.cmpf ogt, %[[V_430]], %[[V_431]] {{.*}} : f32 ! CHECK: fir.if %[[V_432]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -219,8 +219,8 @@ program p ! CHECK: %[[V_458:[0-9]+]] = fir.array_coor %[[V_62]](%[[V_61]]) %[[V_457]] : (!fir.ref>, !fir.shape<1>, i64) -> !fir.ref ! CHECK: %[[V_459:[0-9]+]] = fir.load %[[V_455]] : !fir.ref ! CHECK: %[[V_460:[0-9]+]] = fir.load %[[V_458]] : !fir.ref - ! CHECK: %[[V_461:[0-9]+]] = arith.cmpf uno, %[[V_459]], %[[V_460]] : f32 - ! CHECK: %[[V_462:[0-9]+]] = arith.cmpf ole, %[[V_459]], %[[V_460]] : f32 + ! CHECK: %[[V_461:[0-9]+]] = arith.cmpf uno, %[[V_459]], %[[V_460]] {{.*}} : f32 + ! CHECK: %[[V_462:[0-9]+]] = arith.cmpf ole, %[[V_459]], %[[V_460]] {{.*}} : f32 ! CHECK: fir.if %[[V_461]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -238,8 +238,8 @@ program p ! CHECK: %[[V_487:[0-9]+]] = fir.array_coor %[[V_62]](%[[V_61]]) %[[V_486]] : (!fir.ref>, !fir.shape<1>, i64) -> !fir.ref ! CHECK: %[[V_488:[0-9]+]] = fir.load %[[V_484]] : !fir.ref ! CHECK: %[[V_489:[0-9]+]] = fir.load %[[V_487]] : !fir.ref - ! CHECK: %[[V_490:[0-9]+]] = arith.cmpf uno, %[[V_488]], %[[V_489]] : f32 - ! CHECK: %[[V_491:[0-9]+]] = arith.cmpf olt, %[[V_488]], %[[V_489]] : f32 + ! CHECK: %[[V_490:[0-9]+]] = arith.cmpf uno, %[[V_488]], %[[V_489]] {{.*}} : f32 + ! CHECK: %[[V_491:[0-9]+]] = arith.cmpf olt, %[[V_488]], %[[V_489]] {{.*}} : f32 ! CHECK: fir.if %[[V_490]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 @@ -257,8 +257,8 @@ program p ! CHECK: %[[V_516:[0-9]+]] = fir.array_coor %[[V_62]](%[[V_61]]) %[[V_515]] : (!fir.ref>, !fir.shape<1>, i64) -> !fir.ref ! CHECK: %[[V_517:[0-9]+]] = fir.load %[[V_513]] : !fir.ref ! CHECK: %[[V_518:[0-9]+]] = fir.load %[[V_516]] : !fir.ref - ! CHECK: %[[V_519:[0-9]+]] = arith.cmpf uno, %[[V_517]], %[[V_518]] : f32 - ! CHECK: %[[V_520:[0-9]+]] = arith.cmpf une, %[[V_517]], %[[V_518]] : f32 + ! CHECK: %[[V_519:[0-9]+]] = arith.cmpf uno, %[[V_517]], %[[V_518]] {{.*}} : f32 + ! CHECK: %[[V_520:[0-9]+]] = arith.cmpf une, %[[V_517]], %[[V_518]] {{.*}} : f32 ! CHECK: fir.if %[[V_519]] { ! CHECK: %[[V_526:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_527:[0-9]+]] = fir.call @feraiseexcept(%[[V_526]]) fastmath : (i32) -> i32 diff --git a/flang/test/Lower/Intrinsics/ieee_logb.f90 b/flang/test/Lower/Intrinsics/ieee_logb.f90 index bbbdfbdc3a8e..df15661d51b2 100644 --- a/flang/test/Lower/Intrinsics/ieee_logb.f90 +++ b/flang/test/Lower/Intrinsics/ieee_logb.f90 @@ -29,7 +29,7 @@ subroutine out(x) ! CHECK: %[[V_72:[0-9]+]] = fir.load %[[V_64]] : !fir.ref ! CHECK: %[[V_73:[0-9]+]] = arith.bitcast %[[V_72]] : f64 to i64 - ! CHECK: %[[V_74:[0-9]+]] = arith.cmpf oeq, %[[V_72]], %cst{{[_0-9]*}} : f64 + ! CHECK: %[[V_74:[0-9]+]] = arith.cmpf oeq, %[[V_72]], %cst{{[_0-9]*}} {{.*}} : f64 ! CHECK: %[[V_75:[0-9]+]] = fir.if %[[V_74]] -> (f64) { ! CHECK: %[[V_101:[0-9]+]] = fir.call @_FortranAMapException(%c4{{.*}}) fastmath : (i32) -> i32 ! CHECK: %[[V_102:[0-9]+]] = fir.call @feraiseexcept(%[[V_101]]) fastmath : (i32) -> i32 diff --git a/flang/test/Lower/Intrinsics/ieee_max_min.f90 b/flang/test/Lower/Intrinsics/ieee_max_min.f90 index c2af50d29a63..aecfaf0a7245 100644 --- a/flang/test/Lower/Intrinsics/ieee_max_min.f90 +++ b/flang/test/Lower/Intrinsics/ieee_max_min.f90 @@ -81,15 +81,15 @@ program p ! CHECK: } ! CHECK: %[[V_208:[0-9]+]] = fir.load %[[V_17]] : !fir.ref ! CHECK: %[[V_209:[0-9]+]] = fir.load %[[V_19]] : !fir.ref - ! CHECK: %[[V_210:[0-9]+]] = arith.cmpf olt, %[[V_208]], %[[V_209]] : f32 + ! CHECK: %[[V_210:[0-9]+]] = arith.cmpf olt, %[[V_208]], %[[V_209]] {{.*}} : f32 ! CHECK: %[[V_211:[0-9]+]] = fir.if %[[V_210]] -> (f32) { ! CHECK: fir.result %[[V_209]] : f32 ! CHECK: } else { - ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_208]], %[[V_209]] : f32 + ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_208]], %[[V_209]] {{.*}} : f32 ! CHECK: %[[V_693:[0-9]+]] = fir.if %[[V_692]] -> (f32) { ! CHECK: fir.result %[[V_208]] : f32 ! CHECK: } else { - ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_208]], %[[V_209]] : f32 + ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_208]], %[[V_209]] {{.*}} : f32 ! CHECK: %[[V_695:[0-9]+]] = fir.if %[[V_694]] -> (f32) { ! CHECK: %[[V_696:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_208]]) <{bit = 960 : i32}> : (f32) -> i1 ! CHECK: %[[V_697:[0-9]+]] = arith.select %[[V_696]], %[[V_208]], %[[V_209]] : f32 @@ -140,15 +140,15 @@ program p ! CHECK: %[[V_274:[0-9]+]] = fir.load %[[V_19]] : !fir.ref ! CHECK: %[[V_275:[0-9]+]] = math.copysign %[[V_273]], %cst{{[_0-9]*}} fastmath : f32 ! CHECK: %[[V_276:[0-9]+]] = math.copysign %[[V_274]], %cst{{[_0-9]*}} fastmath : f32 - ! CHECK: %[[V_277:[0-9]+]] = arith.cmpf olt, %[[V_275]], %[[V_276]] : f32 + ! CHECK: %[[V_277:[0-9]+]] = arith.cmpf olt, %[[V_275]], %[[V_276]] {{.*}} : f32 ! CHECK: %[[V_278:[0-9]+]] = fir.if %[[V_277]] -> (f32) { ! CHECK: fir.result %[[V_274]] : f32 ! CHECK: } else { - ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_275]], %[[V_276]] : f32 + ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_275]], %[[V_276]] {{.*}} : f32 ! CHECK: %[[V_693:[0-9]+]] = fir.if %[[V_692]] -> (f32) { ! CHECK: fir.result %[[V_273]] : f32 ! CHECK: } else { - ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_275]], %[[V_276]] : f32 + ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_275]], %[[V_276]] {{.*}} : f32 ! CHECK: %[[V_695:[0-9]+]] = fir.if %[[V_694]] -> (f32) { ! CHECK: %[[V_696:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_273]]) <{bit = 960 : i32}> : (f32) -> i1 ! CHECK: %[[V_697:[0-9]+]] = arith.select %[[V_696]], %[[V_273]], %[[V_274]] : f32 @@ -197,22 +197,22 @@ program p ! CHECK: } ! CHECK: %[[V_334:[0-9]+]] = fir.load %[[V_17]] : !fir.ref ! CHECK: %[[V_335:[0-9]+]] = fir.load %[[V_19]] : !fir.ref - ! CHECK: %[[V_336:[0-9]+]] = arith.cmpf olt, %[[V_334]], %[[V_335]] : f32 + ! CHECK: %[[V_336:[0-9]+]] = arith.cmpf olt, %[[V_334]], %[[V_335]] {{.*}} : f32 ! CHECK: %[[V_337:[0-9]+]] = fir.if %[[V_336]] -> (f32) { ! CHECK: fir.result %[[V_335]] : f32 ! CHECK: } else { - ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_334]], %[[V_335]] : f32 + ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_334]], %[[V_335]] {{.*}} : f32 ! CHECK: %[[V_693:[0-9]+]] = fir.if %[[V_692]] -> (f32) { ! CHECK: fir.result %[[V_334]] : f32 ! CHECK: } else { - ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_334]], %[[V_335]] : f32 + ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_334]], %[[V_335]] {{.*}} : f32 ! CHECK: %[[V_695:[0-9]+]] = fir.if %[[V_694]] -> (f32) { ! CHECK: %[[V_696:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_334]]) <{bit = 960 : i32}> : (f32) -> i1 ! CHECK: %[[V_697:[0-9]+]] = arith.select %[[V_696]], %[[V_334]], %[[V_335]] : f32 ! CHECK: fir.result %[[V_697]] : f32 ! CHECK: } else { - ! CHECK: %[[V_696:[0-9]+]] = arith.cmpf ord, %[[V_334]], %[[V_334]] : f32 - ! CHECK: %[[V_697:[0-9]+]] = arith.cmpf ord, %[[V_335]], %[[V_335]] : f32 + ! CHECK: %[[V_696:[0-9]+]] = arith.cmpf ord, %[[V_334]], %[[V_334]] {{.*}} : f32 + ! CHECK: %[[V_697:[0-9]+]] = arith.cmpf ord, %[[V_335]], %[[V_335]] {{.*}} : f32 ! CHECK: %[[V_698:[0-9]+]] = fir.coordinate_of %[[V_92]], %c2{{.*}} : (!fir.ref>, i8) -> !fir.ref ! CHECK: %[[V_699:[0-9]+]] = fir.load %[[V_698]] : !fir.ref ! CHECK: %[[V_700:[0-9]+]] = arith.bitcast %[[V_699]] : i32 to f32 @@ -260,22 +260,22 @@ program p ! CHECK: %[[V_394:[0-9]+]] = fir.load %[[V_19]] : !fir.ref ! CHECK: %[[V_395:[0-9]+]] = math.copysign %[[V_393]], %cst{{[_0-9]*}} fastmath : f32 ! CHECK: %[[V_396:[0-9]+]] = math.copysign %[[V_394]], %cst{{[_0-9]*}} fastmath : f32 - ! CHECK: %[[V_397:[0-9]+]] = arith.cmpf olt, %[[V_395]], %[[V_396]] : f32 + ! CHECK: %[[V_397:[0-9]+]] = arith.cmpf olt, %[[V_395]], %[[V_396]] {{.*}} : f32 ! CHECK: %[[V_398:[0-9]+]] = fir.if %[[V_397]] -> (f32) { ! CHECK: fir.result %[[V_394]] : f32 ! CHECK: } else { - ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_395]], %[[V_396]] : f32 + ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_395]], %[[V_396]] {{.*}} : f32 ! CHECK: %[[V_693:[0-9]+]] = fir.if %[[V_692]] -> (f32) { ! CHECK: fir.result %[[V_393]] : f32 ! CHECK: } else { - ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_395]], %[[V_396]] : f32 + ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_395]], %[[V_396]] {{.*}} : f32 ! CHECK: %[[V_695:[0-9]+]] = fir.if %[[V_694]] -> (f32) { ! CHECK: %[[V_696:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_393]]) <{bit = 960 : i32}> : (f32) -> i1 ! CHECK: %[[V_697:[0-9]+]] = arith.select %[[V_696]], %[[V_393]], %[[V_394]] : f32 ! CHECK: fir.result %[[V_697]] : f32 ! CHECK: } else { - ! CHECK: %[[V_696:[0-9]+]] = arith.cmpf ord, %[[V_393]], %[[V_393]] : f32 - ! CHECK: %[[V_697:[0-9]+]] = arith.cmpf ord, %[[V_394]], %[[V_394]] : f32 + ! CHECK: %[[V_696:[0-9]+]] = arith.cmpf ord, %[[V_393]], %[[V_393]] {{.*}} : f32 + ! CHECK: %[[V_697:[0-9]+]] = arith.cmpf ord, %[[V_394]], %[[V_394]] {{.*}} : f32 ! CHECK: %[[V_698:[0-9]+]] = fir.coordinate_of %[[V_92]], %c2{{.*}} : (!fir.ref>, i8) -> !fir.ref ! CHECK: %[[V_699:[0-9]+]] = fir.load %[[V_698]] : !fir.ref ! CHECK: %[[V_700:[0-9]+]] = arith.bitcast %[[V_699]] : i32 to f32 @@ -321,15 +321,15 @@ program p ! CHECK: } ! CHECK: %[[V_454:[0-9]+]] = fir.load %[[V_17]] : !fir.ref ! CHECK: %[[V_455:[0-9]+]] = fir.load %[[V_19]] : !fir.ref - ! CHECK: %[[V_456:[0-9]+]] = arith.cmpf olt, %[[V_454]], %[[V_455]] : f32 + ! CHECK: %[[V_456:[0-9]+]] = arith.cmpf olt, %[[V_454]], %[[V_455]] {{.*}} : f32 ! CHECK: %[[V_457:[0-9]+]] = fir.if %[[V_456]] -> (f32) { ! CHECK: fir.result %[[V_454]] : f32 ! CHECK: } else { - ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_454]], %[[V_455]] : f32 + ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_454]], %[[V_455]] {{.*}} : f32 ! CHECK: %[[V_693:[0-9]+]] = fir.if %[[V_692]] -> (f32) { ! CHECK: fir.result %[[V_455]] : f32 ! CHECK: } else { - ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_454]], %[[V_455]] : f32 + ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_454]], %[[V_455]] {{.*}} : f32 ! CHECK: %[[V_695:[0-9]+]] = fir.if %[[V_694]] -> (f32) { ! CHECK: %[[V_696:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_454]]) <{bit = 60 : i32}> : (f32) -> i1 ! CHECK: %[[V_697:[0-9]+]] = arith.select %[[V_696]], %[[V_454]], %[[V_455]] : f32 @@ -380,15 +380,15 @@ program p ! CHECK: %[[V_514:[0-9]+]] = fir.load %[[V_19]] : !fir.ref ! CHECK: %[[V_515:[0-9]+]] = math.copysign %[[V_513]], %cst{{[_0-9]*}} fastmath : f32 ! CHECK: %[[V_516:[0-9]+]] = math.copysign %[[V_514]], %cst{{[_0-9]*}} fastmath : f32 - ! CHECK: %[[V_517:[0-9]+]] = arith.cmpf olt, %[[V_515]], %[[V_516]] : f32 + ! CHECK: %[[V_517:[0-9]+]] = arith.cmpf olt, %[[V_515]], %[[V_516]] {{.*}} : f32 ! CHECK: %[[V_518:[0-9]+]] = fir.if %[[V_517]] -> (f32) { ! CHECK: fir.result %[[V_513]] : f32 ! CHECK: } else { - ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_515]], %[[V_516]] : f32 + ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_515]], %[[V_516]] {{.*}} : f32 ! CHECK: %[[V_693:[0-9]+]] = fir.if %[[V_692]] -> (f32) { ! CHECK: fir.result %[[V_514]] : f32 ! CHECK: } else { - ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_515]], %[[V_516]] : f32 + ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_515]], %[[V_516]] {{.*}} : f32 ! CHECK: %[[V_695:[0-9]+]] = fir.if %[[V_694]] -> (f32) { ! CHECK: %[[V_696:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_513]]) <{bit = 60 : i32}> : (f32) -> i1 ! CHECK: %[[V_697:[0-9]+]] = arith.select %[[V_696]], %[[V_513]], %[[V_514]] : f32 @@ -437,22 +437,22 @@ program p ! CHECK: } ! CHECK: %[[V_574:[0-9]+]] = fir.load %[[V_17]] : !fir.ref ! CHECK: %[[V_575:[0-9]+]] = fir.load %[[V_19]] : !fir.ref - ! CHECK: %[[V_576:[0-9]+]] = arith.cmpf olt, %[[V_574]], %[[V_575]] : f32 + ! CHECK: %[[V_576:[0-9]+]] = arith.cmpf olt, %[[V_574]], %[[V_575]] {{.*}} : f32 ! CHECK: %[[V_577:[0-9]+]] = fir.if %[[V_576]] -> (f32) { ! CHECK: fir.result %[[V_574]] : f32 ! CHECK: } else { - ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_574]], %[[V_575]] : f32 + ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_574]], %[[V_575]] {{.*}} : f32 ! CHECK: %[[V_693:[0-9]+]] = fir.if %[[V_692]] -> (f32) { ! CHECK: fir.result %[[V_575]] : f32 ! CHECK: } else { - ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_574]], %[[V_575]] : f32 + ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_574]], %[[V_575]] {{.*}} : f32 ! CHECK: %[[V_695:[0-9]+]] = fir.if %[[V_694]] -> (f32) { ! CHECK: %[[V_696:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_574]]) <{bit = 60 : i32}> : (f32) -> i1 ! CHECK: %[[V_697:[0-9]+]] = arith.select %[[V_696]], %[[V_574]], %[[V_575]] : f32 ! CHECK: fir.result %[[V_697]] : f32 ! CHECK: } else { - ! CHECK: %[[V_696:[0-9]+]] = arith.cmpf ord, %[[V_574]], %[[V_574]] : f32 - ! CHECK: %[[V_697:[0-9]+]] = arith.cmpf ord, %[[V_575]], %[[V_575]] : f32 + ! CHECK: %[[V_696:[0-9]+]] = arith.cmpf ord, %[[V_574]], %[[V_574]] {{.*}} : f32 + ! CHECK: %[[V_697:[0-9]+]] = arith.cmpf ord, %[[V_575]], %[[V_575]] {{.*}} : f32 ! CHECK: %[[V_698:[0-9]+]] = fir.coordinate_of %[[V_92]], %c2{{.*}} : (!fir.ref>, i8) -> !fir.ref ! CHECK: %[[V_699:[0-9]+]] = fir.load %[[V_698]] : !fir.ref ! CHECK: %[[V_700:[0-9]+]] = arith.bitcast %[[V_699]] : i32 to f32 @@ -500,22 +500,22 @@ program p ! CHECK: %[[V_634:[0-9]+]] = fir.load %[[V_19]] : !fir.ref ! CHECK: %[[V_635:[0-9]+]] = math.copysign %[[V_633]], %cst{{[_0-9]*}} fastmath : f32 ! CHECK: %[[V_636:[0-9]+]] = math.copysign %[[V_634]], %cst{{[_0-9]*}} fastmath : f32 - ! CHECK: %[[V_637:[0-9]+]] = arith.cmpf olt, %[[V_635]], %[[V_636]] : f32 + ! CHECK: %[[V_637:[0-9]+]] = arith.cmpf olt, %[[V_635]], %[[V_636]] {{.*}} : f32 ! CHECK: %[[V_638:[0-9]+]] = fir.if %[[V_637]] -> (f32) { ! CHECK: fir.result %[[V_633]] : f32 ! CHECK: } else { - ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_635]], %[[V_636]] : f32 + ! CHECK: %[[V_692:[0-9]+]] = arith.cmpf ogt, %[[V_635]], %[[V_636]] {{.*}} : f32 ! CHECK: %[[V_693:[0-9]+]] = fir.if %[[V_692]] -> (f32) { ! CHECK: fir.result %[[V_634]] : f32 ! CHECK: } else { - ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_635]], %[[V_636]] : f32 + ! CHECK: %[[V_694:[0-9]+]] = arith.cmpf oeq, %[[V_635]], %[[V_636]] {{.*}} : f32 ! CHECK: %[[V_695:[0-9]+]] = fir.if %[[V_694]] -> (f32) { ! CHECK: %[[V_696:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_633]]) <{bit = 60 : i32}> : (f32) -> i1 ! CHECK: %[[V_697:[0-9]+]] = arith.select %[[V_696]], %[[V_633]], %[[V_634]] : f32 ! CHECK: fir.result %[[V_697]] : f32 ! CHECK: } else { - ! CHECK: %[[V_696:[0-9]+]] = arith.cmpf ord, %[[V_633]], %[[V_633]] : f32 - ! CHECK: %[[V_697:[0-9]+]] = arith.cmpf ord, %[[V_634]], %[[V_634]] : f32 + ! CHECK: %[[V_696:[0-9]+]] = arith.cmpf ord, %[[V_633]], %[[V_633]] {{.*}} : f32 + ! CHECK: %[[V_697:[0-9]+]] = arith.cmpf ord, %[[V_634]], %[[V_634]] {{.*}} : f32 ! CHECK: %[[V_698:[0-9]+]] = fir.coordinate_of %[[V_92]], %c2{{.*}} : (!fir.ref>, i8) -> !fir.ref ! CHECK: %[[V_699:[0-9]+]] = fir.load %[[V_698]] : !fir.ref ! CHECK: %[[V_700:[0-9]+]] = arith.bitcast %[[V_699]] : i32 to f32 diff --git a/flang/test/Lower/Intrinsics/ieee_unordered.f90 b/flang/test/Lower/Intrinsics/ieee_unordered.f90 index e6cbab7ef8c6..a6146eff7f06 100644 --- a/flang/test/Lower/Intrinsics/ieee_unordered.f90 +++ b/flang/test/Lower/Intrinsics/ieee_unordered.f90 @@ -44,21 +44,21 @@ z = ieee_value(z, ieee_quiet_nan) ! CHECK: %[[V_40:[0-9]+]] = fir.load %[[V_2]] : !fir.ref ! CHECK: %[[V_41:[0-9]+]] = fir.load %[[V_3]] : !fir.ref -! CHECK: %[[V_44:[0-9]+]] = arith.cmpf uno, %[[V_40]], %[[V_41]] : f128 +! CHECK: %[[V_44:[0-9]+]] = arith.cmpf uno, %[[V_40]], %[[V_41]] {{.*}} : f128 ! CHECK: %[[V_45:[0-9]+]] = fir.convert %[[V_44]] : (i1) -> !fir.logical<4> ! CHECK: %[[V_46:[0-9]+]] = fir.convert %[[V_45]] : (!fir.logical<4>) -> i1 ! CHECK: %[[V_47:[0-9]+]] = fir.call @_FortranAioOutputLogical(%{{.*}}, %[[V_46]]) {{.*}} : (!fir.ref, i1) -> i1 ! CHECK: %[[V_48:[0-9]+]] = fir.load %[[V_2]] : !fir.ref ! CHECK: %[[V_49:[0-9]+]] = fir.load %[[V_4]] : !fir.ref -! CHECK: %[[V_52:[0-9]+]] = arith.cmpf uno, %[[V_48]], %[[V_49]] : f128 +! CHECK: %[[V_52:[0-9]+]] = arith.cmpf uno, %[[V_48]], %[[V_49]] {{.*}} : f128 ! CHECK: %[[V_53:[0-9]+]] = fir.convert %[[V_52]] : (i1) -> !fir.logical<4> ! CHECK: %[[V_54:[0-9]+]] = fir.convert %[[V_53]] : (!fir.logical<4>) -> i1 ! CHECK: %[[V_55:[0-9]+]] = fir.call @_FortranAioOutputLogical(%{{.*}}, %[[V_54]]) {{.*}} : (!fir.ref, i1) -> i1 ! CHECK: %[[V_56:[0-9]+]] = fir.load %[[V_3]] : !fir.ref ! CHECK: %[[V_57:[0-9]+]] = fir.load %[[V_4]] : !fir.ref -! CHECK: %[[V_60:[0-9]+]] = arith.cmpf uno, %[[V_56]], %[[V_57]] : f128 +! CHECK: %[[V_60:[0-9]+]] = arith.cmpf uno, %[[V_56]], %[[V_57]] {{.*}} : f128 ! CHECK: %[[V_61:[0-9]+]] = fir.convert %[[V_60]] : (i1) -> !fir.logical<4> ! CHECK: %[[V_62:[0-9]+]] = fir.convert %[[V_61]] : (!fir.logical<4>) -> i1 ! CHECK: %[[V_63:[0-9]+]] = fir.call @_FortranAioOutputLogical(%{{.*}}, %[[V_62]]) {{.*}} : (!fir.ref, i1) -> i1 diff --git a/flang/test/Lower/Intrinsics/min.f90 b/flang/test/Lower/Intrinsics/min.f90 index 40e6d96db6e5..c9744cf33d82 100644 --- a/flang/test/Lower/Intrinsics/min.f90 +++ b/flang/test/Lower/Intrinsics/min.f90 @@ -18,11 +18,11 @@ end function ! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref ! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref ! CHECK: %[[VAL_10:.*]] = fir.is_present %[[VAL_5]]#0 : (!fir.ref) -> i1 -! CHECK: %[[VAL_11:.*]] = arith.cmpf olt, %[[VAL_8]], %[[VAL_9]] : f32 +! CHECK: %[[VAL_11:.*]] = arith.cmpf olt, %[[VAL_8]], %[[VAL_9]] {{.*}} : f32 ! CHECK: %[[VAL_12:.*]] = arith.select %[[VAL_11]], %[[VAL_8]], %[[VAL_9]] : f32 ! CHECK: %[[VAL_13:.*]] = fir.if %[[VAL_10]] -> (f32) { ! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.cmpf olt, %[[VAL_12]], %[[VAL_14]] : f32 +! CHECK: %[[VAL_15:.*]] = arith.cmpf olt, %[[VAL_12]], %[[VAL_14]] {{.*}} : f32 ! CHECK: %[[VAL_16:.*]] = arith.select %[[VAL_15]], %[[VAL_12]], %[[VAL_14]] : f32 ! CHECK: fir.result %[[VAL_16]] : f32 ! CHECK: } else { diff --git a/flang/test/Lower/Intrinsics/modulo.f90 b/flang/test/Lower/Intrinsics/modulo.f90 index 4c8c1ff4da3b..64a6607a09cc 100644 --- a/flang/test/Lower/Intrinsics/modulo.f90 +++ b/flang/test/Lower/Intrinsics/modulo.f90 @@ -8,9 +8,9 @@ subroutine modulo_testr(r, a, p) ! CHECK-DAG: %[[p:.*]] = fir.load %[[arg2]] : !fir.ref ! CHECK-DAG: %[[rem:.*]] = arith.remf %[[a]], %[[p]] {{.*}}: f64 ! CHECK-DAG: %[[zero:.*]] = arith.constant 0.000000e+00 : f64 - ! CHECK-DAG: %[[remNotZero:.*]] = arith.cmpf une, %[[rem]], %[[zero]] : f64 - ! CHECK-DAG: %[[aNeg:.*]] = arith.cmpf olt, %[[a]], %[[zero]] : f64 - ! CHECK-DAG: %[[pNeg:.*]] = arith.cmpf olt, %[[p]], %[[zero]] : f64 + ! CHECK-DAG: %[[remNotZero:.*]] = arith.cmpf une, %[[rem]], %[[zero]] {{.*}} : f64 + ! CHECK-DAG: %[[aNeg:.*]] = arith.cmpf olt, %[[a]], %[[zero]] {{.*}} : f64 + ! CHECK-DAG: %[[pNeg:.*]] = arith.cmpf olt, %[[p]], %[[zero]] {{.*}} : f64 ! CHECK-DAG: %[[signDifferent:.*]] = arith.xori %[[aNeg]], %[[pNeg]] : i1 ! CHECK-DAG: %[[mustAddP:.*]] = arith.andi %[[remNotZero]], %[[signDifferent]] : i1 ! CHECK-DAG: %[[remPlusP:.*]] = arith.addf %[[rem]], %[[p]] {{.*}}: f64 diff --git a/flang/test/Lower/Intrinsics/nearest.f90 b/flang/test/Lower/Intrinsics/nearest.f90 index 02ded4919dd7..a023fa8cd804 100644 --- a/flang/test/Lower/Intrinsics/nearest.f90 +++ b/flang/test/Lower/Intrinsics/nearest.f90 @@ -7,7 +7,7 @@ subroutine nearest_test1(x, s) ! CHECK: %[[x:.*]] = fir.load %arg0 : !fir.ref ! CHECK: %[[s:.*]] = fir.load %arg1 : !fir.ref ! CHECK: %[[zero:.*]] = arith.constant 0.000000e+00 : f32 - ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] : f32 + ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] {{.*}} : f32 ! CHECK: %[[pos:.*]] = arith.select %[[cmp]], %true, %false : i1 res = nearest(x, s) ! CHECK: %[[tmp:.*]] = fir.call @_FortranANearest4(%[[x]], %[[pos]]) {{.*}}: (f32, i1) -> f32 @@ -21,7 +21,7 @@ subroutine nearest_test1(x, s) ! CHECK: %[[x:.*]] = fir.load %arg0 : !fir.ref ! CHECK: %[[s:.*]] = fir.load %arg1 : !fir.ref ! CHECK: %[[zero:.*]] = arith.constant 0.000000e+00 : f64 - ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] : f64 + ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] {{.*}} : f64 ! CHECK: %[[pos:.*]] = arith.select %[[cmp]], %true, %false : i1 res = nearest(x, s) ! CHECK: %[[tmp:.*]] = fir.call @_FortranANearest8(%[[x]], %[[pos]]) {{.*}}: (f64, i1) -> f64 @@ -35,7 +35,7 @@ subroutine nearest_test1(x, s) ! CHECK: %[[x:.*]] = fir.load %arg0 : !fir.ref ! CHECK: %[[s:.*]] = fir.load %arg1 : !fir.ref ! CHECK: %[[zero:.*]] = arith.constant 0.000000e+00 : f80 - ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] : f80 + ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] {{.*}} : f80 ! CHECK: %[[pos:.*]] = arith.select %[[cmp]], %true, %false : i1 res = nearest(x, s) ! CHECK: %[[tmp:.*]] = fir.call @_FortranANearest10(%[[x]], %[[pos]]) {{.*}}: (f80, i1) -> f80 @@ -49,7 +49,7 @@ subroutine nearest_test1(x, s) ! CHECK: %[[x:.*]] = fir.load %arg0 : !fir.ref ! CHECK: %[[s:.*]] = fir.load %arg1 : !fir.ref ! CHECK: %[[zero:.*]] = arith.constant 0.000000e+00 : f128 - ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] : f128 + ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] {{.*}} : f128 ! CHECK: %[[pos:.*]] = arith.select %[[cmp]], %true, %false : i1 res = nearest(x, s) ! CHECK: %[[tmp:.*]] = fir.call @_FortranANearest16(%[[x]], %[[pos]]) {{.*}}: (f128, i1) -> f128 @@ -64,7 +64,7 @@ subroutine nearest_test1(x, s) real :: s ! CHECK: %[[s:.*]] = fir.load %arg1 : !fir.ref ! CHECK: %[[zero:.*]] = arith.constant 0.000000e+00 : f32 - ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] : f32 + ! CHECK: %[[cmp:.*]] = arith.cmpf ogt, %[[s]], %[[zero]] {{.*}} : f32 ! CHECK: %[[pos:.*]] = arith.select %[[cmp]], %true, %false : i1 res = nearest(x, s) ! CHECK: %[[tmp:.*]] = fir.call @_FortranANearest16(%[[x]], %[[pos]]) {{.*}}: (f128, i1) -> f128 diff --git a/flang/test/Lower/OpenACC/acc-reduction.f90 b/flang/test/Lower/OpenACC/acc-reduction.f90 index 73f7176cd450..a8f7e1fa81ef 100644 --- a/flang/test/Lower/OpenACC/acc-reduction.f90 +++ b/flang/test/Lower/OpenACC/acc-reduction.f90 @@ -24,7 +24,7 @@ ! HLFIR: %[[D2:.*]] = hlfir.designate %14 (%[[ARG0]], %[[ARG1]]) : (!fir.box>, index, index) -> !fir.ref ! HLFIR: %[[LOAD1:.*]] = fir.load %[[D1]] : !fir.ref ! HLFIR: %[[LOAD2:.*]] = fir.load %[[D2]] : !fir.ref -! HLFIR: %[[CMP:.*]] = arith.cmpf ogt, %[[LOAD1]], %[[LOAD2]] : f32 +! HLFIR: %[[CMP:.*]] = arith.cmpf ogt, %[[LOAD1]], %[[LOAD2]] {{.*}} : f32 ! HLFIR: %[[SELECT:.*]] = arith.select %[[CMP]], %[[LOAD1]], %[[LOAD2]] : f32 ! HLFIR: hlfir.yield_element %[[SELECT]] : f32 ! HLFIR: } @@ -59,7 +59,7 @@ ! HLFIR: %[[V2:.*]] = hlfir.designate %[[DES_V2]] (%[[IV]]) : (!fir.box>>, index) -> !fir.ref ! HLFIR: %[[LOAD_V1:.*]] = fir.load %[[V1]] : !fir.ref ! HLFIR: %[[LOAD_V2:.*]] = fir.load %[[V2]] : !fir.ref -! HLFIR: %[[CMP:.*]] = arith.cmpf ogt, %[[LOAD_V1]], %[[LOAD_V2]] : f32 +! HLFIR: %[[CMP:.*]] = arith.cmpf ogt, %[[LOAD_V1]], %[[LOAD_V2]] {{.*}} : f32 ! HLFIR: %[[SELECT:.*]] = arith.select %[[CMP]], %[[LOAD_V1]], %[[LOAD_V2]] : f32 ! HLFIR: hlfir.yield_element %[[SELECT]] : f32 ! HLFIR: } @@ -113,7 +113,7 @@ ! HLFIR: %[[DES_V2:.*]] = hlfir.designate %[[RIGHT]] (%{{.*}}) : (!fir.box>, index) -> !fir.ref ! HLFIR: %[[LOAD_V1:.*]] = fir.load %[[DES_V1]] : !fir.ref ! HLFIR: %[[LOAD_V2:.*]] = fir.load %[[DES_V2]] : !fir.ref -! HLFIR: %[[CMPF:.*]] = arith.cmpf ogt, %[[LOAD_V1]], %[[LOAD_V2]] : f32 +! HLFIR: %[[CMPF:.*]] = arith.cmpf ogt, %[[LOAD_V1]], %[[LOAD_V2]] {{.*}} : f32 ! HLFIR: %[[SELECT:.*]] = arith.select %[[CMPF]], %[[LOAD_V1]], %[[LOAD_V2]] : f32 ! HLFIR: hlfir.yield_element %[[SELECT]] : f32 ! HLFIR: } @@ -340,7 +340,7 @@ ! CHECK: %[[COORD2:.*]] = fir.coordinate_of %[[ARG1]], %[[IV0]] : (!fir.ref>, index) -> !fir.ref ! CHECK: %[[LOAD1:.*]] = fir.load %[[COORD1]] : !fir.ref ! CHECK: %[[LOAD2:.*]] = fir.load %[[COORD2]] : !fir.ref -! CHECK: %[[CMP:.*]] = arith.cmpf ogt, %[[LOAD1]], %[[LOAD2]] : f32 +! CHECK: %[[CMP:.*]] = arith.cmpf ogt, %[[LOAD1]], %[[LOAD2]] {{.*}} : f32 ! CHECK: %[[SELECT:.*]] = arith.select %[[CMP]], %[[LOAD1]], %[[LOAD2]] : f32 ! CHECK: fir.store %[[SELECT]] to %[[COORD1]] : !fir.ref ! CHECK: } @@ -358,7 +358,7 @@ ! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): ! CHECK: %[[LOAD0:.*]] = fir.load %[[ARG0]] : !fir.ref ! CHECK: %[[LOAD1:.*]] = fir.load %[[ARG1]] : !fir.ref -! CHECK: %[[CMP:.*]] = arith.cmpf ogt, %[[LOAD0]], %[[LOAD1]] : f32 +! CHECK: %[[CMP:.*]] = arith.cmpf ogt, %[[LOAD0]], %[[LOAD1]] {{.*}} : f32 ! CHECK: %[[SELECT:.*]] = arith.select %[[CMP]], %[[LOAD0]], %[[LOAD1]] : f32 ! CHECK: fir.store %[[SELECT]] to %[[ARG0]] : !fir.ref ! CHECK: acc.yield %[[ARG0]] : !fir.ref @@ -431,7 +431,7 @@ ! CHECK: %[[COORD2:.*]] = fir.coordinate_of %[[ARG1]], %[[IV0]], %[[IV1]] : (!fir.ref>, index, index) -> !fir.ref ! CHECK: %[[LOAD1:.*]] = fir.load %[[COORD1]] : !fir.ref ! CHECK: %[[LOAD2:.*]] = fir.load %[[COORD2]] : !fir.ref -! CHECK: %[[CMP:.*]] = arith.cmpf olt, %[[LOAD1]], %[[LOAD2]] : f32 +! CHECK: %[[CMP:.*]] = arith.cmpf olt, %[[LOAD1]], %[[LOAD2]] {{.*}} : f32 ! CHECK: %[[SELECT:.*]] = arith.select %[[CMP]], %[[LOAD1]], %[[LOAD2]] : f32 ! CHECK: fir.store %[[SELECT]] to %[[COORD1]] : !fir.ref ! CHECK: } @@ -450,7 +450,7 @@ ! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): ! CHECK: %[[LOAD0:.*]] = fir.load %[[ARG0]] : !fir.ref ! CHECK: %[[LOAD1:.*]] = fir.load %[[ARG1]] : !fir.ref -! CHECK: %[[CMP:.*]] = arith.cmpf olt, %[[LOAD0]], %[[LOAD1]] : f32 +! CHECK: %[[CMP:.*]] = arith.cmpf olt, %[[LOAD0]], %[[LOAD1]] {{.*}} : f32 ! CHECK: %[[SELECT:.*]] = arith.select %[[CMP]], %[[LOAD0]], %[[LOAD1]] : f32 ! CHECK: fir.store %[[SELECT]] to %[[ARG0]] : !fir.ref ! CHECK: acc.yield %[[ARG0]] : !fir.ref diff --git a/flang/test/Lower/allocatable-polymorphic.f90 b/flang/test/Lower/allocatable-polymorphic.f90 index 75db99dee094..a6a8c039880d 100644 --- a/flang/test/Lower/allocatable-polymorphic.f90 +++ b/flang/test/Lower/allocatable-polymorphic.f90 @@ -1,5 +1,5 @@ -! RUN: bbc --use-desc-for-alloc=false -polymorphic-type -emit-fir -hlfir=false %s -o - | FileCheck %s -! RUN: bbc --use-desc-for-alloc=false -polymorphic-type -emit-fir -hlfir=false %s -o - | tco | FileCheck %s --check-prefix=LLVM +! RUN: bbc --use-desc-for-alloc=false -polymorphic-type -emit-hlfir %s -o - | FileCheck %s +! RUN: bbc --use-desc-for-alloc=false -polymorphic-type -emit-hlfir %s -o - | tco | FileCheck %s --check-prefix=LLVM module poly type p1 @@ -40,7 +40,6 @@ contains print*, 'call proc2_p2' end subroutine - ! ------------------------------------------------------------------------------ ! Test lowering of ALLOCATE statement for polymoprhic pointer ! ------------------------------------------------------------------------------ @@ -88,18 +87,23 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_pointer() ! CHECK: %[[C1_DESC:.*]] = fir.alloca !fir.class>> {bindc_name = "c1", uniq_name = "_QMpolyFtest_pointerEc1"} +! CHECK: %[[C1_DECL:.*]]:2 = hlfir.declare %[[C1_DESC]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_pointerEc1"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[C2_DESC:.*]] = fir.alloca !fir.class>> {bindc_name = "c2", uniq_name = "_QMpolyFtest_pointerEc2"} +! CHECK: %[[C2_DECL:.*]]:2 = hlfir.declare %[[C2_DESC]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_pointerEc2"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[C3_DESC:.*]] = fir.alloca !fir.class>>> {bindc_name = "c3", uniq_name = "_QMpolyFtest_pointerEc3"} +! CHECK: %[[C3_DECL:.*]]:2 = hlfir.declare %[[C3_DESC]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_pointerEc3"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %[[C4_DESC:.*]] = fir.alloca !fir.class>>> {bindc_name = "c4", uniq_name = "_QMpolyFtest_pointerEc4"} +! CHECK: %[[C4_DECL:.*]]:2 = hlfir.declare %[[C4_DESC]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_pointerEc4"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %[[P_DESC:.*]] = fir.alloca !fir.class>> {bindc_name = "p", uniq_name = "_QMpolyFtest_pointerEp"} +! CHECK: %[[P_DECL:.*]]:2 = hlfir.declare %[[P_DESC]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_pointerEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[TYPE_DESC_P1:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[P_DESC_CAST:.*]] = fir.convert %[[P_DESC]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[P_DESC_CAST:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_DESC_P1_CAST:.*]] = fir.convert %[[TYPE_DESC_P1]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 ! CHECK: %{{.*}} = fir.call @_FortranAPointerNullifyDerived(%[[P_DESC_CAST]], %[[TYPE_DESC_P1_CAST]], %[[RANK]], %[[CORANK]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none -! CHECK: %[[P_DESC_CAST:.*]] = fir.convert %[[P_DESC]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[P_DESC_CAST:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[P_DESC_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 ! call p%proc1() @@ -107,98 +111,96 @@ contains ! CHECK: fir.dispatch "proc1"(%[[P_LOAD]] : !fir.class>>) ! CHECK: %[[TYPE_DESC_P1:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C1_DESC_CAST:.*]] = fir.convert %[[C1_DESC:.*]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C1_DESC_CAST:.*]] = fir.convert %[[C1_DECL:.*]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_DESC_P1_CAST:.*]] = fir.convert %[[TYPE_DESC_P1]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 ! CHECK: %{{.*}} = fir.call @_FortranAPointerNullifyDerived(%[[C1_DESC_CAST]], %[[TYPE_DESC_P1_CAST]], %[[RANK]], %[[CORANK]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none -! CHECK: %[[C1_DESC_CAST:.*]] = fir.convert %[[C1_DESC]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C1_DESC_CAST:.*]] = fir.convert %[[C1_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[C1_DESC_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 -! CHECK: %[[TYPE_DESC_P2:.*]] = fir.type_desc !fir.type<_QMpolyTp2{a:i32,b:i32,c:i32}> -! CHECK: %[[C2_DESC_CAST:.*]] = fir.convert %[[C2_DESC]] : (!fir.ref>>>) -> !fir.ref> -! CHECK: %[[TYPE_DESC_P2_CAST:.*]] = fir.convert %[[TYPE_DESC_P2]] : (!fir.tdesc>) -> !fir.ref +! CHECK: %[[TYPE_DESC_P2:.*]] = fir.type_desc !fir.type<_QMpolyTp2{p1:!fir.type<_QMpolyTp1{a:i32,b:i32}>,c:i32}> +! CHECK: %[[C2_DESC_CAST:.*]] = fir.convert %[[C2_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[TYPE_DESC_P2_CAST:.*]] = fir.convert %[[TYPE_DESC_P2]] : (!fir.tdesc,c:i32}>>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 ! CHECK: %{{.*}} = fir.call @_FortranAPointerNullifyDerived(%[[C2_DESC_CAST]], %[[TYPE_DESC_P2_CAST]], %[[RANK]], %[[CORANK]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none -! CHECK: %[[C2_DESC_CAST:.*]] = fir.convert %[[C2_DESC]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C2_DESC_CAST:.*]] = fir.convert %[[C2_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[C2_DESC_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 ! call c1%proc1() -! CHECK: %[[C1_DESC_LOAD:.*]] = fir.load %[[C1_DESC]] : !fir.ref>>> +! CHECK: %[[C1_DESC_LOAD:.*]] = fir.load %[[C1_DECL]]#0 : !fir.ref>>> ! CHECK: fir.dispatch "proc1"(%[[C1_DESC_LOAD]] : !fir.class>>) ! call c2%proc1() -! CHECK: %[[C2_DESC_LOAD:.*]] = fir.load %[[C2_DESC]] : !fir.ref>>> +! CHECK: %[[C2_DESC_LOAD:.*]] = fir.load %[[C2_DECL]]#0 : !fir.ref>>> ! CHECK: fir.dispatch "proc1"(%[[C2_DESC_LOAD]] : !fir.class>>) ! call c1%proc2() -! CHECK: %[[C1_LOAD:.*]] = fir.load %[[C1_DESC]] : !fir.ref>>> +! CHECK: %[[C1_LOAD:.*]] = fir.load %[[C1_DECL]]#0 : !fir.ref>>> ! CHECK: %[[C1_REBOX:.*]] = fir.rebox %[[C1_LOAD]] : (!fir.class>>) -> !fir.class> -! CHECK: fir.dispatch "proc2"(%[[C1_LOAD]] : !fir.class>>) (%[[C1_REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "proc2"(%[[C1_REBOX]] : !fir.class>) (%[[C1_REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} ! call c2%proc2() -! CHECK: %[[C2_LOAD:.*]] = fir.load %[[C2_DESC]] : !fir.ref>>> +! CHECK: %[[C2_LOAD:.*]] = fir.load %[[C2_DECL]]#0 : !fir.ref>>> ! CHECK: %[[C2_REBOX:.*]] = fir.rebox %[[C2_LOAD]] : (!fir.class>>) -> !fir.class> -! CHECK: fir.dispatch "proc2"(%[[C2_LOAD]] : !fir.class>>) (%[[C2_REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "proc2"(%[[C2_REBOX]] : !fir.class>) (%[[C2_REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK: %[[TYPE_DESC_P1:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DESC]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %[[TYPE_DESC_P1_CAST:.*]] = fir.convert %[[TYPE_DESC_P1]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 1 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 ! CHECK: %{{.*}} = fir.call @_FortranAPointerNullifyDerived(%[[C3_CAST]], %[[TYPE_DESC_P1_CAST]], %[[RANK]], %[[CORANK]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none -! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DESC]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerSetBounds(%[[C3_CAST]], %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i32, i64, i64) -> none -! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DESC]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[C3_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 -! CHECK: %[[TYPE_DESC_P2:.*]] = fir.type_desc !fir.type<_QMpolyTp2{a:i32,b:i32,c:i32}> -! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DESC]] : (!fir.ref>>>>) -> !fir.ref> -! CHECK: %[[TYPE_DESC_P2_CAST:.*]] = fir.convert %[[TYPE_DESC_P2]] : (!fir.tdesc>) -> !fir.ref +! CHECK: %[[TYPE_DESC_P2:.*]] = fir.type_desc !fir.type<_QMpolyTp2{p1:!fir.type<_QMpolyTp1{a:i32,b:i32}>,c:i32}> +! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[TYPE_DESC_P2_CAST:.*]] = fir.convert %[[TYPE_DESC_P2]] : (!fir.tdesc,c:i32}>>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 1 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 ! CHECK: %{{.*}} = fir.call @_FortranAPointerNullifyDerived(%[[C4_CAST]], %[[TYPE_DESC_P2_CAST]], %[[RANK]], %[[CORANK]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none -! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DESC]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerSetBounds(%[[C4_CAST]], %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i32, i64, i64) -> none -! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DESC]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[C4_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK-LABEL: fir.do_loop -! CHECK: %[[C3_LOAD:.*]] = fir.load %[[C3_DESC]] : !fir.ref>>>> -! CHECK: %[[C3_COORD:.*]] = fir.coordinate_of %[[C3_LOAD]], %{{.*}} : (!fir.class>>>, i64) -> !fir.ref> -! CHECK: %[[C3_BOXED:.*]] = fir.embox %[[C3_COORD]] source_box %[[C3_LOAD]] : (!fir.ref>, !fir.class>>>) -> !fir.class> -! CHECK: fir.dispatch "proc2"(%[[C3_BOXED]] : !fir.class>) (%[[C3_BOXED]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: %[[C3_LOAD:.*]] = fir.load %[[C3_DECL]]#0 : !fir.ref>>>> +! CHECK: %[[DESIGNATE_C3:.*]] = hlfir.designate %[[C3_LOAD]] (%{{.*}}) : (!fir.class>>>, i64) -> !fir.class> +! CHECK: fir.dispatch "proc2"(%[[DESIGNATE_C3]] : !fir.class>) (%[[DESIGNATE_C3]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK-LABEL: fir.do_loop -! CHECK: %[[C4_LOAD:.*]] = fir.load %[[C4_DESC]] : !fir.ref>>>> -! CHECK: %[[C4_COORD:.*]] = fir.coordinate_of %[[C4_LOAD]], %{{.*}} : (!fir.class>>>, i64) -> !fir.ref> -! CHECK: %[[C4_BOXED:.*]] = fir.embox %[[C4_COORD]] source_box %[[C4_LOAD]] : (!fir.ref>, !fir.class>>>) -> !fir.class> -! CHECK: fir.dispatch "proc2"(%[[C4_BOXED]] : !fir.class>) (%[[C4_BOXED]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: %[[C4_LOAD:.*]] = fir.load %[[C4_DECL]]#0 : !fir.ref>>>> +! CHECK: %[[DESIGNATE_C4:.*]] = hlfir.designate %[[C4_LOAD]] (%{{.*}}) : (!fir.class>>>, i64) -> !fir.class> +! CHECK: fir.dispatch "proc2"(%[[DESIGNATE_C4]] : !fir.class>) (%[[DESIGNATE_C4]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[P_CAST:.*]] = fir.convert %[[P_DESC]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[P_CAST:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAPointerDeallocatePolymorphic(%[[P_CAST]], %[[TYPE_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C1_DESC_CAST:.*]] = fir.convert %[[C1_DESC]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C1_DESC_CAST:.*]] = fir.convert %[[C1_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAPointerDeallocatePolymorphic(%[[C1_DESC_CAST]], %[[TYPE_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C2_DESC_CAST:.*]] = fir.convert %[[C2_DESC]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C2_DESC_CAST:.*]] = fir.convert %[[C2_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAPointerDeallocatePolymorphic(%[[C2_DESC_CAST]], %[[TYPE_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C3_DESC_CAST:.*]] = fir.convert %[[C3_DESC]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C3_DESC_CAST:.*]] = fir.convert %[[C3_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAPointerDeallocatePolymorphic(%[[C3_DESC_CAST]], %[[TYPE_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C4_DESC_CAST:.*]] = fir.convert %[[C4_DESC]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C4_DESC_CAST:.*]] = fir.convert %[[C4_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAPointerDeallocatePolymorphic(%[[C4_DESC_CAST]], %[[TYPE_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 @@ -248,117 +250,120 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_allocatable() ! CHECK-DAG: %[[C1:.*]] = fir.alloca !fir.class>> {bindc_name = "c1", uniq_name = "_QMpolyFtest_allocatableEc1"} +! CHECK-DAG: %[[C1_DECL:.*]]:2 = hlfir.declare %[[C1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatableEc1"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK-DAG: %[[C2:.*]] = fir.alloca !fir.class>> {bindc_name = "c2", uniq_name = "_QMpolyFtest_allocatableEc2"} +! CHECK-DAG: %[[C2_DECL:.*]]:2 = hlfir.declare %[[C2]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatableEc2"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK-DAG: %[[C3:.*]] = fir.alloca !fir.class>>> {bindc_name = "c3", uniq_name = "_QMpolyFtest_allocatableEc3"} +! CHECK-DAG: %[[C3_DECL:.*]]:2 = hlfir.declare %[[C3]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatableEc3"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK-DAG: %[[C4:.*]] = fir.alloca !fir.class>>> {bindc_name = "c4", uniq_name = "_QMpolyFtest_allocatableEc4"} +! CHECK-DAG: %[[C4_DECL:.*]]:2 = hlfir.declare %[[C4]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatableEc4"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK-DAG: %[[P:.*]] = fir.alloca !fir.class>> {bindc_name = "p", uniq_name = "_QMpolyFtest_allocatableEp"} +! CHECK-DAG: %[[P_DECL:.*]]:2 = hlfir.declare %[[P]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatableEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[TYPE_DESC_P1:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[P_CAST:.*]] = fir.convert %[[P]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[P_CAST:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_DESC_P1_CAST:.*]] = fir.convert %[[TYPE_DESC_P1]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[C0:.*]] = arith.constant 0 : i32 ! CHECK: fir.call @_FortranAAllocatableInitDerivedForAllocate(%[[P_CAST]], %[[TYPE_DESC_P1_CAST]], %[[RANK]], %[[C0]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none -! CHECK: %[[P_CAST:.*]] = fir.convert %[[P]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[P_CAST:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableAllocate(%[[P_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_P1:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C1_CAST:.*]] = fir.convert %0 : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C1_CAST:.*]] = fir.convert %[[C1_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_DESC_P1_CAST:.*]] = fir.convert %[[TYPE_DESC_P1]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[C0:.*]] = arith.constant 0 : i32 ! CHECK: fir.call @_FortranAAllocatableInitDerivedForAllocate(%[[C1_CAST]], %[[TYPE_DESC_P1_CAST]], %[[RANK]], %[[C0]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none -! CHECK: %[[C1_CAST:.*]] = fir.convert %[[C1]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C1_CAST:.*]] = fir.convert %[[C1_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableAllocate(%[[C1_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 -! CHECK: %[[TYPE_DESC_P2:.*]] = fir.type_desc !fir.type<_QMpolyTp2{a:i32,b:i32,c:i32}> -! CHECK: %[[C2_CAST:.*]] = fir.convert %[[C2]] : (!fir.ref>>>) -> !fir.ref> -! CHECK: %[[TYPE_DESC_P2_CAST:.*]] = fir.convert %[[TYPE_DESC_P2]] : (!fir.tdesc>) -> !fir.ref +! CHECK: %[[TYPE_DESC_P2:.*]] = fir.type_desc !fir.type<_QMpolyTp2{p1:!fir.type<_QMpolyTp1{a:i32,b:i32}>,c:i32}> +! CHECK: %[[C2_CAST:.*]] = fir.convert %[[C2_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[TYPE_DESC_P2_CAST:.*]] = fir.convert %[[TYPE_DESC_P2]] : (!fir.tdesc,c:i32}>>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[C0:.*]] = arith.constant 0 : i32 ! CHECK: fir.call @_FortranAAllocatableInitDerivedForAllocate(%[[C2_CAST]], %[[TYPE_DESC_P2_CAST]], %[[RANK]], %[[C0]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none -! CHECK: %[[C2_CAST:.*]] = fir.convert %[[C2]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C2_CAST:.*]] = fir.convert %[[C2_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableAllocate(%[[C2_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_P1:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %[[TYPE_DESC_P1_CAST:.*]] = fir.convert %[[TYPE_DESC_P1]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 1 : i32 ! CHECK: %[[C0:.*]] = arith.constant 0 : i32 ! CHECK: fir.call @_FortranAAllocatableInitDerivedForAllocate(%[[C3_CAST]], %[[TYPE_DESC_P1_CAST]], %[[RANK]], %[[C0]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none ! CHECK: %[[C10:.*]] = arith.constant 10 : i32 ! CHECK: %[[C0:.*]] = arith.constant 0 : i32 -! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3]] : (!fir.ref>>>>) -> !fir.ref> -! CHECK: %[[C1_I64:.*]] = fir.convert %c1 : (index) -> i64 +! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C1_I64:.*]] = fir.convert %c1{{.*}} : (index) -> i64 ! CHECK: %[[C10_I64:.*]] = fir.convert %[[C10]] : (i32) -> i64 ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableSetBounds(%[[C3_CAST]], %[[C0]], %[[C1_I64]], %[[C10_I64]]) {{.*}}: (!fir.ref>, i32, i64, i64) -> none -! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableAllocate(%[[C3_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 -! CHECK: %[[TYPE_DESC_P2:.*]] = fir.type_desc !fir.type<_QMpolyTp2{a:i32,b:i32,c:i32}> -! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4]] : (!fir.ref>>>>) -> !fir.ref> -! CHECK: %[[TYPE_DESC_P2_CAST:.*]] = fir.convert %[[TYPE_DESC_P2]] : (!fir.tdesc>) -> !fir.ref +! CHECK: %[[TYPE_DESC_P2:.*]] = fir.type_desc !fir.type<_QMpolyTp2{p1:!fir.type<_QMpolyTp1{a:i32,b:i32}>,c:i32}> +! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[TYPE_DESC_P2_CAST:.*]] = fir.convert %[[TYPE_DESC_P2]] : (!fir.tdesc,c:i32}>>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 1 : i32 ! CHECK: %[[C0:.*]] = arith.constant 0 : i32 ! CHECK: fir.call @_FortranAAllocatableInitDerivedForAllocate(%[[C4_CAST]], %[[TYPE_DESC_P2_CAST]], %[[RANK]], %[[C0]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none ! CHECK: %[[CST1:.*]] = arith.constant 1 : index ! CHECK: %[[C20:.*]] = arith.constant 20 : i32 ! CHECK: %[[C0:.*]] = arith.constant 0 : i32 -! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %[[C1_I64:.*]] = fir.convert %[[CST1]] : (index) -> i64 ! CHECK: %[[C20_I64:.*]] = fir.convert %[[C20]] : (i32) -> i64 ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableSetBounds(%[[C4_CAST]], %[[C0]], %[[C1_I64]], %[[C20_I64]]) {{.*}}: (!fir.ref>, i32, i64, i64) -> none -! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableAllocate(%[[C4_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 -! CHECK: %[[C1_LOAD1:.*]] = fir.load %[[C1_DESC]] : !fir.ref>>> +! CHECK: %[[C1_LOAD1:.*]] = fir.load %[[C1_DECL]]#0 : !fir.ref>>> ! CHECK: fir.dispatch "proc1"(%[[C1_LOAD1]] : !fir.class>>) -! CHECK: %[[C2_LOAD1:.*]] = fir.load %[[C2_DESC]] : !fir.ref>>> +! CHECK: %[[C2_LOAD1:.*]] = fir.load %[[C2_DECL]]#0 : !fir.ref>>> ! CHECK: fir.dispatch "proc1"(%[[C2_LOAD1]] : !fir.class>>) -! CHECK: %[[C1_LOAD2:.*]] = fir.load %[[C1_DESC]] : !fir.ref>>> +! CHECK: %[[C1_LOAD2:.*]] = fir.load %[[C1_DECL]]#0 : !fir.ref>>> ! CHECK: %[[C1_REBOX:.*]] = fir.rebox %[[C1_LOAD2]] : (!fir.class>>) -> !fir.class> -! CHECK: fir.dispatch "proc2"(%[[C1_LOAD2]] : !fir.class>>) (%[[C1_REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "proc2"(%[[C1_REBOX]] : !fir.class>) (%[[C1_REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} -! CHECK: %[[C2_LOAD2:.*]] = fir.load %[[C2_DESC]] : !fir.ref>>> +! CHECK: %[[C2_LOAD2:.*]] = fir.load %[[C2_DECL]]#0 : !fir.ref>>> ! CHECK: %[[C2_REBOX:.*]] = fir.rebox %[[C2_LOAD2]] : (!fir.class>>) -> !fir.class> -! CHECK: fir.dispatch "proc2"(%[[C2_LOAD2]] : !fir.class>>) (%[[C2_REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "proc2"(%[[C2_REBOX]] : !fir.class>) (%[[C2_REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK-LABEL: %{{.*}} = fir.do_loop -! CHECK: %[[C3_LOAD:.*]] = fir.load %[[C3_DESC]] : !fir.ref>>>> -! CHECK: %[[C3_COORD:.*]] = fir.coordinate_of %[[C3_LOAD]], %{{.*}} : (!fir.class>>>, i64) -> !fir.ref> -! CHECK: %[[C3_EMBOX:.*]] = fir.embox %[[C3_COORD]] source_box %[[C3_LOAD]] : (!fir.ref>, !fir.class>>>) -> !fir.class> -! CHECK: fir.dispatch "proc2"(%[[C3_EMBOX]] : !fir.class>) (%[[C3_EMBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: %[[C3_LOAD:.*]] = fir.load %[[C3_DECL]]#0 : !fir.ref>>>> +! CHECK: %[[DESIGNATE_C3:.*]] = hlfir.designate %[[C3_LOAD]] (%{{.*}}) : (!fir.class>>>, i64) -> !fir.class> +! CHECK: fir.dispatch "proc2"(%[[DESIGNATE_C3]] : !fir.class>) (%[[DESIGNATE_C3]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK-LABEL: %{{.*}} = fir.do_loop -! CHECK: %[[C4_LOAD:.*]] = fir.load %[[C4]] : !fir.ref>>>> -! CHECK: %[[C4_COORD:.*]] = fir.coordinate_of %[[C4_LOAD]], %{{.*}} : (!fir.class>>>, i64) -> !fir.ref> -! CHECK: %[[C4_EMBOX:.*]] = fir.embox %[[C4_COORD]] source_box %[[C4_LOAD]] : (!fir.ref>, !fir.class>>>) -> !fir.class> -! CHECK: fir.dispatch "proc2"(%[[C4_EMBOX]] : !fir.class>) (%[[C4_EMBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: %[[C4_LOAD:.*]] = fir.load %[[C4_DECL]]#0 : !fir.ref>>>> +! CHECK: %[[DESIGNATE_C4:.*]] = hlfir.designate %[[C4_LOAD]] (%{{.*}}) : (!fir.class>>>, i64) -> !fir.class> +! CHECK: fir.dispatch "proc2"(%[[DESIGNATE_C4]] : !fir.class>) (%[[DESIGNATE_C4]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[P_CAST:.*]] = fir.convert %[[P]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[P_CAST:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableDeallocatePolymorphic(%[[P_CAST]], %[[TYPE_NONE]], %{{.*}}, %1{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C1_CAST:.*]] = fir.convert %[[C1]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C1_CAST:.*]] = fir.convert %[[C1_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableDeallocatePolymorphic(%[[C1_CAST]], %[[TYPE_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C2_CAST:.*]] = fir.convert %[[C2]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C2_CAST:.*]] = fir.convert %[[C2_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableDeallocatePolymorphic(%[[C2_CAST]], %[[TYPE_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C3_CAST:.*]] = fir.convert %[[C3_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableDeallocatePolymorphic(%[[C3_CAST]], %[[TYPE_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[TYPE_DESC_ADDR:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[C4_CAST:.*]] = fir.convert %[[C4_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %[[TYPE_NONE:.*]] = fir.convert %[[TYPE_DESC_ADDR]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableDeallocatePolymorphic(%[[C4_CAST]], %[[TYPE_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 @@ -375,27 +380,29 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_unlimited_polymorphic_with_intrinsic_type_spec() { ! CHECK: %[[P:.*]] = fir.alloca !fir.class> {bindc_name = "p", uniq_name = "_QMpolyFtest_unlimited_polymorphic_with_intrinsic_type_specEp"} +! CHECK: %[[P_DECL:.*]]:2 = hlfir.declare %[[P]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_unlimited_polymorphic_with_intrinsic_type_specEp"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[PTR:.*]] = fir.alloca !fir.class> {bindc_name = "ptr", uniq_name = "_QMpolyFtest_unlimited_polymorphic_with_intrinsic_type_specEptr"} -! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[P]] : (!fir.ref>>) -> !fir.ref> +! CHECK: %[[PTR_DECL:.*]]:2 = hlfir.declare %[[PTR]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_unlimited_polymorphic_with_intrinsic_type_specEptr"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>) -> !fir.ref> ! CHECK: %[[CAT:.*]] = arith.constant 0 : i32 ! CHECK: %[[KIND:.*]] = arith.constant 4 : i32 ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableInitIntrinsicForAllocate(%[[BOX_NONE]], %[[CAT]], %[[KIND]], %[[RANK]], %[[CORANK]]) {{.*}} : (!fir.ref>, i32, i32, i32, i32) -> none -! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[P]] : (!fir.ref>>) -> !fir.ref> +! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableAllocate(%[[BOX_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 -! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[PTR]] : (!fir.ref>>) -> !fir.ref> +! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[PTR_DECL]]#1 : (!fir.ref>>) -> !fir.ref> ! CHECK: %[[CAT:.*]] = arith.constant 1 : i32 ! CHECK: %[[KIND:.*]] = arith.constant 4 : i32 ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 ! CHECK: %{{.*}} = fir.call @_FortranAPointerNullifyIntrinsic(%[[BOX_NONE]], %[[CAT]], %[[KIND]], %[[RANK]], %[[CORANK]]) {{.*}} : (!fir.ref>, i32, i32, i32, i32) -> none -! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[PTR]] : (!fir.ref>>) -> !fir.ref> +! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[PTR_DECL]]#1 : (!fir.ref>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[BOX_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[NULL_TYPE_DESC:.*]] = fir.zero_bits !fir.ref -! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[PTR]] : (!fir.ref>>) -> !fir.ref> +! CHECK: %[[BOX_NONE:.*]] = fir.convert %[[PTR_DECL]]#1 : (!fir.ref>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerDeallocatePolymorphic(%[[BOX_NONE]], %[[NULL_TYPE_DESC]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, !fir.ref, i1, !fir.box, !fir.ref, i32) -> i32 ! Test code generation of deallocate @@ -413,21 +420,24 @@ contains end subroutine ! CHECK-LABEL: func.func @_QMpolyPtest_type_with_polymorphic_pointer_component() -! CHECK: %[[TYPE_PTR:.*]] = fir.alloca !fir.ptr>>}>> {uniq_name = "_QMpolyFtest_type_with_polymorphic_pointer_componentEa.addr"} -! CHECK: %[[TYPE_PTR_LOAD:.*]] = fir.load %[[TYPE_PTR]] : !fir.ref>>}>>> -! CHECK: %[[ELEMENT:.*]] = fir.field_index element, !fir.type<_QMpolyTwith_alloc{element:!fir.class>>}> -! CHECK: %[[ELEMENT_DESC:.*]] = fir.coordinate_of %[[TYPE_PTR_LOAD]], %[[ELEMENT]] : (!fir.ptr>>}>>, !fir.field) -> !fir.ref>>> +! CHECK: %[[TYPE_PTR:.*]] = fir.alloca !fir.box>>}>>> {bindc_name = "a", uniq_name = "_QMpolyFtest_type_with_polymorphic_pointer_componentEa"} +! CHECK: %[[TYPE_PTR_DECL:.*]]:2 = hlfir.declare %39 {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_type_with_polymorphic_pointer_componentEa"} : (!fir.ref>>}>>>>) -> (!fir.ref>>}>>>>, !fir.ref>>}>>>>) +! CHECK: %[[TYPE_PTR_CONV:.*]] = fir.convert %[[TYPE_PTR_DECL]]#1 : (!fir.ref>>}>>>>) -> !fir.ref> +! CHECK: fir.call @_FortranAPointerAllocate(%[[TYPE_PTR_CONV]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 +! CHECK: %[[TYPE_PTR_LOAD:.*]] = fir.load %[[TYPE_PTR_DECL]]#0 : !fir.ref>>}>>>> +! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[TYPE_PTR_LOAD]] : (!fir.box>>}>>>) -> !fir.ptr>>}>> +! CHECK: %[[ELEMENT:.*]] = hlfir.designate %[[BOX_ADDR]]{"element"} {fortran_attrs = #fir.var_attrs} : (!fir.ptr>>}>>) -> !fir.ref>>> ! CHECK: %[[ZERO:.*]] = fir.zero_bits !fir.ptr> ! CHECK: %[[ZERO_DESC:.*]] = fir.embox %[[ZERO]] : (!fir.ptr>) -> !fir.class>> -! CHECK: fir.store %[[ZERO_DESC]] to %[[ELEMENT_DESC]] : !fir.ref>>> +! CHECK: fir.store %[[ZERO_DESC]] to %[[ELEMENT]] : !fir.ref>>> ! CHECK: %[[TYPE_DESC_P1:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[ELEMENT_DESC_CAST:.*]] = fir.convert %[[ELEMENT_DESC]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[ELEMENT_DESC_CAST:.*]] = fir.convert %[[ELEMENT]] : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_DESC_P1_CAST:.*]] = fir.convert %[[TYPE_DESC_P1]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 -! CHECK: %{{.*}} = fir.call @_FortranAPointerNullifyDerived(%[[ELEMENT_DESC_CAST]], %[[TYPE_DESC_P1_CAST]], %[[RANK]], %[[CORANK]]) {{.*}}: (!fir.ref>, !fir.ref, i32, i32) -> none -! CHECK: %[[ELEMENT_DESC_CAST:.*]] = fir.convert %[[ELEMENT_DESC]] : (!fir.ref>>>) -> !fir.ref> -! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[ELEMENT_DESC_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 +! CHECK: %{{.*}} = fir.call @_FortranAPointerNullifyDerived(%[[ELEMENT_DESC_CAST]], %[[TYPE_DESC_P1_CAST]], %[[RANK]], %[[CORANK]]) {{.*}} : (!fir.ref>, !fir.ref, i32, i32) -> none +! CHECK: %[[ELEMENT_DESC_CAST:.*]] = fir.convert %[[ELEMENT]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[ELEMENT_DESC_CAST]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 subroutine test_allocate_with_mold() type(p2) :: x(10) @@ -441,22 +451,27 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_allocate_with_mold() { ! CHECK: %[[I:.*]] = fir.alloca !fir.array<20xi32> {bindc_name = "i", uniq_name = "_QMpolyFtest_allocate_with_moldEi"} +! CHECK: %[[I_DECL:.*]]:2 = hlfir.declare %[[I]](%{{.*}}) {uniq_name = "_QMpolyFtest_allocate_with_moldEi"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[P:.*]] = fir.alloca !fir.class>>> {bindc_name = "p", uniq_name = "_QMpolyFtest_allocate_with_moldEp"} +! CHECK: %[[P_DECL:.*]]:2 = hlfir.declare %[[P]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocate_with_moldEp"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %[[UP:.*]] = fir.alloca !fir.class>> {bindc_name = "up", uniq_name = "_QMpolyFtest_allocate_with_moldEup"} -! CHECK: %[[X:.*]] = fir.alloca !fir.array<10x!fir.type<_QMpolyTp2{a:i32,b:i32,c:i32}>> {bindc_name = "x", uniq_name = "_QMpolyFtest_allocate_with_moldEx"} -! CHECK: %[[EMBOX_X:.*]] = fir.embox %[[X]](%{{.*}}) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> +! CHECK: %[[UP_DECL:.*]]:2 = hlfir.declare %[[UP:.*]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocate_with_moldEup"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[X:.*]] = fir.alloca !fir.array<10x!fir.type<_QMpolyTp2{p1:!fir.type<_QMpolyTp1{a:i32,b:i32}>,c:i32}>> {bindc_name = "x", uniq_name = "_QMpolyFtest_allocate_with_moldEx"} +! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]](%{{.*}}) {uniq_name = "_QMpolyFtest_allocate_with_moldEx"} : (!fir.ref,c:i32}>>>, !fir.shape<1>) -> (!fir.ref,c:i32}>>>, !fir.ref,c:i32}>>>) + +! CHECK: %[[EMBOX_X:.*]] = fir.embox %[[X_DECL]]#1(%{{.*}}) : (!fir.ref,c:i32}>>>, !fir.shape<1>) -> !fir.box,c:i32}>>> ! CHECK: %[[RANK:.*]] = arith.constant 1 : i32 -! CHECK: %[[P_BOX_NONE:.*]] = fir.convert %[[P]] : (!fir.ref>>>>) -> !fir.ref> -! CHECK: %[[X_BOX_NONE:.*]] = fir.convert %[[EMBOX_X]] : (!fir.box>>) -> !fir.box +! CHECK: %[[P_BOX_NONE:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[X_BOX_NONE:.*]] = fir.convert %[[EMBOX_X]] : (!fir.box,c:i32}>>>) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAPointerApplyMold(%[[P_BOX_NONE]], %[[X_BOX_NONE]], %[[RANK]]) {{.*}} : (!fir.ref>, !fir.box, i32) -> none -! CHECK: %[[P_BOX_NONE:.*]] = fir.convert %[[P]] : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[P_BOX_NONE:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[P_BOX_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 -! CHECK: %[[EMBOX_I:.*]] = fir.embox %[[I]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[EMBOX_I:.*]] = fir.embox %[[I_DECL]]#1(%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> ! CHECK: %[[RANK:.*]] = arith.constant 1 : i32 -! CHECK: %[[UP_BOX_NONE:.*]] = fir.convert %[[UP]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[UP_BOX_NONE:.*]] = fir.convert %[[UP_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[I_BOX_NONE:.*]] = fir.convert %[[EMBOX_I]] : (!fir.box>) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAPointerApplyMold(%[[UP_BOX_NONE]], %[[I_BOX_NONE]], %[[RANK]]) {{.*}} : (!fir.ref>, !fir.box, i32) -> none -! CHECK: %[[UP_BOX_NONE:.*]] = fir.convert %[[UP]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[UP_BOX_NONE:.*]] = fir.convert %[[UP_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%[[UP_BOX_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 subroutine test_allocate_with_source() @@ -471,25 +486,29 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_allocate_with_source() { ! CHECK: %[[I:.*]] = fir.alloca !fir.array<20xi32> {bindc_name = "i", uniq_name = "_QMpolyFtest_allocate_with_sourceEi"} +! CHECK: %[[I_DECL:.*]]:2 = hlfir.declare %[[I]](%{{.*}}) {uniq_name = "_QMpolyFtest_allocate_with_sourceEi"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[P:.*]] = fir.alloca !fir.class>>> {bindc_name = "p", uniq_name = "_QMpolyFtest_allocate_with_sourceEp"} +! CHECK: %[[P_DECL:.*]]:2 = hlfir.declare %[[P]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocate_with_sourceEp"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %[[UP:.*]] = fir.alloca !fir.class>> {bindc_name = "up", uniq_name = "_QMpolyFtest_allocate_with_sourceEup"} -! CHECK: %[[X:.*]] = fir.alloca !fir.array<10x!fir.type<_QMpolyTp2{a:i32,b:i32,c:i32}>> {bindc_name = "x", uniq_name = "_QMpolyFtest_allocate_with_sourceEx"} -! CHECK: %[[EMBOX_X:.*]] = fir.embox %[[X]](%{{.*}}) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> +! CHECK: %[[UP_DECL:.*]]:2 = hlfir.declare %[[UP]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocate_with_sourceEup"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[X:.*]] = fir.alloca !fir.array<10x!fir.type<_QMpolyTp2{p1:!fir.type<_QMpolyTp1{a:i32,b:i32}>,c:i32}>> {bindc_name = "x", uniq_name = "_QMpolyFtest_allocate_with_sourceEx"} +! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]](%{{.*}}) {uniq_name = "_QMpolyFtest_allocate_with_sourceEx"} : (!fir.ref,c:i32}>>>, !fir.shape<1>) -> (!fir.ref,c:i32}>>>, !fir.ref,c:i32}>>>) +! CHECK: %[[EMBOX_X:.*]] = fir.embox %[[X_DECL]]#1(%{{.*}}) : (!fir.ref,c:i32}>>>, !fir.shape<1>) -> !fir.box,c:i32}>>> ! CHECK: %[[RANK:.*]] = arith.constant 1 : i32 -! CHECK: %[[P_BOX_NONE:.*]] = fir.convert %[[P]] : (!fir.ref>>>>) -> !fir.ref> -! CHECK: %[[X_BOX_NONE:.*]] = fir.convert %[[EMBOX_X]] : (!fir.box>>) -> !fir.box +! CHECK: %[[P_BOX_NONE:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[X_BOX_NONE:.*]] = fir.convert %[[EMBOX_X]] : (!fir.box,c:i32}>>>) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAPointerApplyMold(%[[P_BOX_NONE]], %[[X_BOX_NONE]], %[[RANK]]) {{.*}} : (!fir.ref>, !fir.box, i32) -> none ! CHECK: %{{.*}} = fir.call @_FortranAPointerSetBounds -! CHECK: %[[BOX_NONE_P:.*]] = fir.convert %[[P]] : (!fir.ref>>>>) -> !fir.ref> -! CHECK: %[[BOX_NONE_X:.*]] = fir.convert %[[EMBOX_X]] : (!fir.box>>) -> !fir.box +! CHECK: %[[BOX_NONE_P:.*]] = fir.convert %[[P_DECL]]#1 : (!fir.ref>>>>) -> !fir.ref> +! CHECK: %[[BOX_NONE_X:.*]] = fir.convert %[[EMBOX_X]] : (!fir.box,c:i32}>>>) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocateSource(%[[BOX_NONE_P]], %[[BOX_NONE_X]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, !fir.box, i1, !fir.box, !fir.ref, i32) -> i32 -! CHECK: %[[EMBOX_I:.*]] = fir.embox %[[I]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[EMBOX_I:.*]] = fir.embox %[[I_DECL]]#1(%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> ! CHECK: %[[RANK:.*]] = arith.constant 1 : i32 -! CHECK: %[[UP_BOX_NONE:.*]] = fir.convert %[[UP]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[UP_BOX_NONE:.*]] = fir.convert %[[UP_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[I_BOX_NONE:.*]] = fir.convert %[[EMBOX_I]] : (!fir.box>) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAPointerApplyMold(%[[UP_BOX_NONE]], %[[I_BOX_NONE]], %[[RANK]]) {{.*}} : (!fir.ref>, !fir.box, i32) -> none ! CHECK: %{{.*}} = fir.call @_FortranAPointerSetBounds -! CHECK: %[[UP_BOX_NONE:.*]] = fir.convert %[[UP]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[UP_BOX_NONE:.*]] = fir.convert %[[UP_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[I_BOX_NONE:.*]] = fir.convert %[[EMBOX_I]] : (!fir.box>) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocateSource(%[[UP_BOX_NONE]], %[[I_BOX_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, !fir.box, i1, !fir.box, !fir.ref, i32) -> i32 @@ -501,12 +520,14 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_allocatable_up_from_up_mold( ! CHECK-SAME: %[[A:.*]]: !fir.ref>> {fir.bindc_name = "a"}, %[[B:.*]]: !fir.ref>> {fir.bindc_name = "b"}) { -! CHECK: %[[LOAD_B:.*]] = fir.load %[[B]] : !fir.ref>> +! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_from_up_moldEa"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_from_up_moldEb"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[LOAD_B:.*]] = fir.load %[[B_DECL]]#1 : !fir.ref>> ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 -! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A]] : (!fir.ref>>) -> !fir.ref> +! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A_DECL]]#1 : (!fir.ref>>) -> !fir.ref> ! CHECK: %[[B_BOX_NONE:.*]] = fir.convert %[[LOAD_B]] : (!fir.class>) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableApplyMold(%[[A_BOX_NONE]], %[[B_BOX_NONE]], %[[RANK]]) {{.*}} : (!fir.ref>, !fir.box, i32) -> none -! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A]] : (!fir.ref>>) -> !fir.ref> +! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A_DECL]]#1 : (!fir.ref>>) -> !fir.ref> ! CHECK: %[[B_BOX_NONE:.*]] = fir.convert %[[LOAD_B]] : (!fir.class>) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableAllocateSource(%[[A_BOX_NONE]], %[[B_BOX_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, !fir.box, i1, !fir.box, !fir.ref, i32) -> i32 @@ -517,22 +538,23 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_allocatable_up_from_mold_rank( ! CHECK-SAME: %[[A:.*]]: !fir.ref>>> {fir.bindc_name = "a"}) { -! CHECK: %[[VALUE_10:.*]] = fir.alloca i32 {adapt.valuebyref} +! CHECK: %[[VALUE_10:.*]] = fir.alloca i32 +! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_from_mold_rankEa"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[C10:.*]] = arith.constant 10 : i32 ! CHECK: fir.store %[[C10]] to %[[VALUE_10]] : !fir.ref ! CHECK: %[[EMBOX_10:.*]] = fir.embox %[[VALUE_10]] : (!fir.ref) -> !fir.box ! CHECK: %[[RANK:.*]] = arith.constant 1 : i32 -! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[BOX_NONE_10:.*]] = fir.convert %[[EMBOX_10]] : (!fir.box) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableApplyMold(%[[A_BOX_NONE]], %[[BOX_NONE_10]], %[[RANK]]) {{.*}} : (!fir.ref>, !fir.box, i32) -> none ! CHECK: %[[C1:.*]] = arith.constant 1 : index ! CHECK: %[[C2:.*]] = arith.constant 20 : i32 ! CHECK: %[[C0:.*]] = arith.constant 0 : i32 -! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[C1_I64:.*]] = fir.convert %[[C1]] : (index) -> i64 ! CHECK: %[[C20_I64:.*]] = fir.convert %[[C20]] : (i32) -> i64 ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableSetBounds(%[[A_BOX_NONE]], %[[C0]], %[[C1_I64]], %[[C20_I64]]) {{.*}} : (!fir.ref>, i32, i64, i64) -> none -! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[A_BOX_NONE:.*]] = fir.convert %[[A_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[BOX_NONE_10:.*]] = fir.convert %[[EMBOX_10]] : (!fir.box) -> !fir.box ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableAllocateSource(%[[A_BOX_NONE]], %[[BOX_NONE_10]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, !fir.box, i1, !fir.box, !fir.ref, i32) -> i32 @@ -543,13 +565,14 @@ contains ! CHECK-LABEL: func.func @_QMpolyPtest_allocatable_up_character() { ! CHECK: %[[A:.*]] = fir.alloca !fir.class> {bindc_name = "a", uniq_name = "_QMpolyFtest_allocatable_up_characterEa"} +! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_allocatable_up_characterEa"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %[[LEN:.*]] = arith.constant 10 : i64 -! CHECK: %[[A_NONE:.*]] = fir.convert %[[A]] : (!fir.ref>>) -> !fir.ref> +! CHECK: %[[A_NONE:.*]] = fir.convert %[[A_DECL]]#1 : (!fir.ref>>) -> !fir.ref> ! CHECK: %[[KIND:.*]] = arith.constant 1 : i32 ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableInitCharacterForAllocate(%[[A_NONE]], %[[LEN]], %[[KIND]], %[[RANK]], %[[CORANK]]) {{.*}} : (!fir.ref>, i64, i32, i32, i32) -> none -! CHECK: %[[A_NONE:.*]] = fir.convert %[[A:.*]] : (!fir.ref>>) -> !fir.ref> +! CHECK: %[[A_NONE:.*]] = fir.convert %[[A_DECL]]#1 : (!fir.ref>>) -> !fir.ref> ! CHECK: %{{.*}} = fir.call @_FortranAAllocatableAllocate(%[[A_NONE]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}} : (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 end module diff --git a/flang/test/Lower/arithmetic-goto.f90 b/flang/test/Lower/arithmetic-goto.f90 index 73f82c309d2d..7b5288f72748 100644 --- a/flang/test/Lower/arithmetic-goto.f90 +++ b/flang/test/Lower/arithmetic-goto.f90 @@ -36,10 +36,10 @@ function kagf(findex) ! CHECK: %[[V_3:[0-9]+]] = arith.addf %[[V_1]], %[[V_2]] {{.*}} : f32 ! CHECK: %[[V_4:[0-9]+]] = arith.addf %[[V_3]], %[[V_3]] {{.*}} : f32 ! CHECK: %cst = arith.constant 0.000000e+00 : f32 - ! CHECK: %[[V_5:[0-9]+]] = arith.cmpf olt, %[[V_4]], %cst : f32 + ! CHECK: %[[V_5:[0-9]+]] = arith.cmpf olt, %[[V_4]], %cst {{.*}} : f32 ! CHECK: cf.cond_br %[[V_5]], ^bb2, ^bb1 ! CHECK: ^bb1: // pred: ^bb0 - ! CHECK: %[[V_6:[0-9]+]] = arith.cmpf ogt, %[[V_4]], %cst : f32 + ! CHECK: %[[V_6:[0-9]+]] = arith.cmpf ogt, %[[V_4]], %cst {{.*}} : f32 ! CHECK: cf.cond_br %[[V_6]], ^bb4, ^bb3 ! CHECK: ^bb2: // pred: ^bb0 ! CHECK: fir.store %c1{{.*}} to %[[V_0]] : !fir.ref diff --git a/flang/test/Lower/array-elemental-calls-2.f90 b/flang/test/Lower/array-elemental-calls-2.f90 index 1d2c18f8bc7b..c3e40f3f6d4f 100644 --- a/flang/test/Lower/array-elemental-calls-2.f90 +++ b/flang/test/Lower/array-elemental-calls-2.f90 @@ -122,7 +122,7 @@ subroutine check_compare() ! CHECK: fir.do_loop ! CHECK: %[[VAL_25:.*]] = fir.array_fetch %{{.*}}, %{{.*}} : (!fir.array<10xf64>, index) -> f64 ! CHECK: %[[VAL_26:.*]] = fir.array_fetch %{{.*}}, %{{.*}} : (!fir.array<10xf64>, index) -> f64 -! CHECK: %[[VAL_27:.*]] = arith.cmpf olt, %[[VAL_25]], %[[VAL_26]] : f64 +! CHECK: %[[VAL_27:.*]] = arith.cmpf olt, %[[VAL_25]], %[[VAL_26]] {{.*}} : f64 ! CHECK: %[[VAL_28:.*]] = fir.convert %[[VAL_27]] : (i1) -> !fir.logical<4> ! CHECK: fir.store %[[VAL_28]] to %[[VAL_0]] : !fir.ref> ! CHECK: fir.call @_QPelem_func_logical4(%[[VAL_0]]) {{.*}}: (!fir.ref>) -> i32 diff --git a/flang/test/Lower/array-expression-slice-1.f90 b/flang/test/Lower/array-expression-slice-1.f90 index d7865a395db1..d81b8488205e 100644 --- a/flang/test/Lower/array-expression-slice-1.f90 +++ b/flang/test/Lower/array-expression-slice-1.f90 @@ -93,7 +93,7 @@ ! CHECK: %[[VAL_78:.*]] = fir.load %[[VAL_77]] : !fir.ref ! CHECK: %[[VAL_79:.*]] = fir.coordinate_of %[[VAL_26]], %[[VAL_19]] : (!fir.ref>, i64) -> !fir.ref ! CHECK: %[[VAL_80:.*]] = fir.load %[[VAL_79]] : !fir.ref -! CHECK: %[[VAL_81:.*]] = arith.cmpf une, %[[VAL_78]], %[[VAL_80]] : f32 +! CHECK: %[[VAL_81:.*]] = arith.cmpf une, %[[VAL_78]], %[[VAL_80]] {{.*}} : f32 ! CHECK: cond_br %[[VAL_81]], ^bb10, ^bb11 ! CHECK: ^bb10: ! CHECK: %[[VAL_82:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref ! CHECK: %[[VAL_96:.*]] = fir.coordinate_of %[[VAL_26]], %[[VAL_20]] : (!fir.ref>, i64) -> !fir.ref ! CHECK: %[[VAL_97:.*]] = fir.load %[[VAL_96]] : !fir.ref -! CHECK: %[[VAL_98:.*]] = arith.cmpf une, %[[VAL_95]], %[[VAL_97]] : f32 +! CHECK: %[[VAL_98:.*]] = arith.cmpf une, %[[VAL_95]], %[[VAL_97]] {{.*}} : f32 ! CHECK: cond_br %[[VAL_98]], ^bb12, ^bb13 ! CHECK: ^bb12: ! CHECK: %[[VAL_99:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref ! CHECK: %[[VAL_113:.*]] = fir.coordinate_of %[[VAL_26]], %[[VAL_13]] : (!fir.ref>, i64) -> !fir.ref ! CHECK: %[[VAL_114:.*]] = fir.load %[[VAL_113]] : !fir.ref -! CHECK: %[[VAL_115:.*]] = arith.cmpf une, %[[VAL_112]], %[[VAL_114]] : f32 +! CHECK: %[[VAL_115:.*]] = arith.cmpf une, %[[VAL_112]], %[[VAL_114]] {{.*}} : f32 ! CHECK: cond_br %[[VAL_115]], ^bb14, ^bb15 ! CHECK: ^bb14: ! CHECK: %[[VAL_116:.*]] = fir.address_of(@_QQclX{{.*}} : !fir.ref ! CHECK: %[[VAL_139:.*]] = fir.coordinate_of %[[VAL_27]], %[[VAL_19]] : (!fir.ref>, i64) -> !fir.ref ! CHECK: %[[VAL_140:.*]] = fir.load %[[VAL_139]] : !fir.ref -! CHECK: %[[VAL_141:.*]] = arith.cmpf une, %[[VAL_138]], %[[VAL_140]] : f32 +! CHECK: %[[VAL_141:.*]] = arith.cmpf une, %[[VAL_138]], %[[VAL_140]] {{.*}} : f32 ! CHECK: cond_br %[[VAL_141]], ^bb19, ^bb20 ! CHECK: ^bb19: ! CHECK: %[[VAL_142:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref ! CHECK: %[[VAL_155:.*]] = fir.coordinate_of %[[VAL_27]], %[[VAL_16]] : (!fir.ref>, i64) -> !fir.ref ! CHECK: %[[VAL_156:.*]] = fir.load %[[VAL_155]] : !fir.ref -! CHECK: %[[VAL_157:.*]] = arith.cmpf une, %[[VAL_154]], %[[VAL_156]] : f32 +! CHECK: %[[VAL_157:.*]] = arith.cmpf une, %[[VAL_154]], %[[VAL_156]] {{.*}} : f32 ! CHECK: cond_br %[[VAL_157]], ^bb21, ^bb22 ! CHECK: ^bb21: ! CHECK: %[[VAL_158:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref ! CHECK: %[[VAL_171:.*]] = fir.coordinate_of %[[VAL_27]], %[[VAL_8]] : (!fir.ref>, i64) -> !fir.ref ! CHECK: %[[VAL_172:.*]] = fir.load %[[VAL_171]] : !fir.ref -! CHECK: %[[VAL_173:.*]] = arith.cmpf une, %[[VAL_170]], %[[VAL_172]] : f32 +! CHECK: %[[VAL_173:.*]] = arith.cmpf une, %[[VAL_170]], %[[VAL_172]] {{.*}} : f32 ! CHECK: cond_br %[[VAL_173]], ^bb23, ^bb24 ! CHECK: ^bb23: ! CHECK: %[[VAL_174:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref> ! CHECK: %[[VAL_224:.*]] = fir.load %[[VAL_77]] : !fir.ref ! CHECK: %[[VAL_225:.*]] = fir.load %[[VAL_96]] : !fir.ref -! CHECK: %[[VAL_226:.*]] = arith.cmpf une, %[[VAL_224]], %[[VAL_225]] : f32 +! CHECK: %[[VAL_226:.*]] = arith.cmpf une, %[[VAL_224]], %[[VAL_225]] {{.*}} : f32 ! CHECK: cond_br %[[VAL_226]], ^bb35, ^bb36 ! CHECK: ^bb35: ! CHECK: %[[VAL_227:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref ! CHECK: %[[VAL_240:.*]] = fir.load %[[VAL_113]] : !fir.ref -! CHECK: %[[VAL_241:.*]] = arith.cmpf une, %[[VAL_239]], %[[VAL_240]] : f32 +! CHECK: %[[VAL_241:.*]] = arith.cmpf une, %[[VAL_239]], %[[VAL_240]] {{.*}} : f32 ! CHECK: cond_br %[[VAL_241]], ^bb37, ^bb38 ! CHECK: ^bb37: ! CHECK: %[[VAL_242:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref ! CHECK: %[[VAL_255:.*]] = fir.load %[[VAL_79]] : !fir.ref -! CHECK: %[[VAL_256:.*]] = arith.cmpf une, %[[VAL_254]], %[[VAL_255]] : f32 +! CHECK: %[[VAL_256:.*]] = arith.cmpf une, %[[VAL_254]], %[[VAL_255]] {{.*}} : f32 ! CHECK: cond_br %[[VAL_256]], ^bb39, ^bb40 ! CHECK: ^bb39: ! CHECK: %[[VAL_257:.*]] = fir.address_of(@_QQclX{{.*}}) : !fir.ref (!fir.array<100xf32>) { ! CHECK: %[[V_11:[0-9]+]] = fir.array_fetch %[[V_8]], %arg1 : (!fir.array<100xf32>, index) -> f32 -! CHECK: %[[V_12:[0-9]+]] = arith.cmpf olt, %[[V_11]], %[[C_st]] : f32 +! CHECK: %[[V_12:[0-9]+]] = arith.cmpf olt, %[[V_11]], %[[C_st]] {{.*}} : f32 ! CHECK: %[[V_13:[0-9]+]]:2 = fir.array_modify %arg2, %arg1 : (!fir.array<100xf32>, index) -> (!fir.ref, !fir.array<100xf32>) ! CHECK: %[[V_14:[0-9]+]] = fir.convert %[[V_12:[0-9]+]] : (i1) -> !fir.logical<4> ! CHECK: fir.store %[[V_14]] to %[[V_0:[0-9]+]] : !fir.ref> @@ -267,7 +267,7 @@ end subroutine ! CHECK: %[[V_11:[0-9]+]] = arith.subi %[[V_10]], %[[C_1_0]] : index ! CHECK: %[[V_12:[0-9]+]] = fir.array_fetch %[[V_5]], %[[V_11:[0-9]+]] : (!fir.array<10xf32>, index) -> f32 ! CHECK: %[[C_st:[-0-9a-z_]+]] = arith.constant 0.000000e+00 : f32 -! CHECK: %[[V_13:[0-9]+]] = arith.cmpf olt, %[[V_12]], %[[C_st]] : f32 +! CHECK: %[[V_13:[0-9]+]] = arith.cmpf olt, %[[V_12]], %[[C_st]] {{.*}} : f32 ! CHECK: %[[C_1_1:[-0-9a-z_]+]] = arith.constant 1 : index ! CHECK: %[[V_14:[0-9]+]] = fir.load %[[V_1:[0-9]+]] : !fir.ref ! CHECK: %[[V_15:[0-9]+]] = fir.convert %[[V_14:[0-9]+]] : (i32) -> i64 @@ -372,7 +372,7 @@ end subroutine ! CHECK: %[[V_18:[0-9]+]] = fir.convert %[[V_17:[0-9]+]] : (!fir.logical<4>) -> i1 ! CHECK: %[[V_19:[0-9]+]] = fir.if %[[V_18]] -> (!fir.array<10xf32>) { ! CHECK: %[[V_20:[0-9]+]] = fir.array_fetch %[[V_12]], %arg3 : (!fir.array<10xf32>, index) -> f32 -! CHECK: %[[V_21:[0-9]+]] = arith.cmpf olt, %[[V_20]], %[[C_st]] : f32 +! CHECK: %[[V_21:[0-9]+]] = arith.cmpf olt, %[[V_20]], %[[C_st]] {{.*}} : f32 ! CHECK: %[[V_22:[0-9]+]]:2 = fir.array_modify %arg4, %arg3 : (!fir.array<10xf32>, index) -> (!fir.ref, !fir.array<10xf32>) ! CHECK: %[[V_23:[0-9]+]] = fir.convert %[[V_21:[0-9]+]] : (i1) -> !fir.logical<4> ! CHECK: fir.store %[[V_23]] to %[[V_0:[0-9]+]] : !fir.ref> diff --git a/flang/test/Lower/assignment.f90 b/flang/test/Lower/assignment.f90 index 5eb55f864add..6be53463a1c7 100644 --- a/flang/test/Lower/assignment.f90 +++ b/flang/test/Lower/assignment.f90 @@ -1,4 +1,4 @@ -! RUN: bbc %s -o "-" -emit-fir -hlfir=false | FileCheck %s +! RUN: %flang_fc1 %s -o "-" -emit-fir -cpp -flang-deprecated-no-hlfir | FileCheck %s --check-prefixes=CHECK%if target=x86_64{{.*}} %{,CHECK-X86-64%} subroutine sub1(a) integer :: a @@ -264,19 +264,23 @@ subroutine real_constant() real(2) :: a real(4) :: b real(8) :: c +#if __x86_64__ real(10) :: d +#endif real(16) :: e a = 2.0_2 b = 4.0_4 c = 8.0_8 +#if __x86_64__ d = 10.0_10 +#endif e = 16.0_16 end ! CHECK: %[[A:.*]] = fir.alloca f16 ! CHECK: %[[B:.*]] = fir.alloca f32 ! CHECK: %[[C:.*]] = fir.alloca f64 -! CHECK: %[[D:.*]] = fir.alloca f80 +! CHECK-X86-64: %[[D:.*]] = fir.alloca f80 ! CHECK: %[[E:.*]] = fir.alloca f128 ! CHECK: %[[C2:.*]] = arith.constant 2.000000e+00 : f16 ! CHECK: fir.store %[[C2]] to %[[A]] : !fir.ref @@ -284,8 +288,8 @@ end ! CHECK: fir.store %[[C4]] to %[[B]] : !fir.ref ! CHECK: %[[C8:.*]] = arith.constant 8.000000e+00 : f64 ! CHECK: fir.store %[[C8]] to %[[C]] : !fir.ref -! CHECK: %[[C10:.*]] = arith.constant 1.000000e+01 : f80 -! CHECK: fir.store %[[C10]] to %[[D]] : !fir.ref +! CHECK-X86-64: %[[C10:.*]] = arith.constant 1.000000e+01 : f80 +! CHECK-X86-64: fir.store %[[C10]] to %[[D]] : !fir.ref ! CHECK: %[[C16:.*]] = arith.constant 1.600000e+01 : f128 ! CHECK: fir.store %[[C16]] to %[[E]] : !fir.ref diff --git a/flang/test/Lower/bbc-host-datalayout.f90 b/flang/test/Lower/bbc-host-datalayout.f90 new file mode 100644 index 000000000000..1795022e3bf7 --- /dev/null +++ b/flang/test/Lower/bbc-host-datalayout.f90 @@ -0,0 +1,9 @@ +! Test bbc set-up of the target data layout from the host. +! RUN: bbc %s -o - | FileCheck %s +subroutine test +end subroutine + +! CHECK: module attributes { +! CHECK-SAME: dlti.dl_spec = #dlti.dl_spec< +! CHECK-SAME: llvm.data_layout = "{{[^"]}} +! CHECK-SAME: llvm.target_triple = "{{[^"]}} diff --git a/flang/test/Lower/bbc-target-datalayout.f90 b/flang/test/Lower/bbc-target-datalayout.f90 new file mode 100644 index 000000000000..adc1ee77bdfb --- /dev/null +++ b/flang/test/Lower/bbc-target-datalayout.f90 @@ -0,0 +1,10 @@ +! Test bbc target override. +! REQUIRES: x86-registered-target +! RUN: bbc %s -target x86_64-unknown-linux-gnu -o - | FileCheck %s +subroutine test +end subroutine + +! CHECK: module attributes { +! CHECK-SAME: dlti.dl_spec = #dlti.dl_spec< +! CHECK-SAME: llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +! CHECK-SAME: llvm.target_triple = "x86_64-unknown-linux-gnu" diff --git a/flang/test/Lower/default-initialization-globals.f90 b/flang/test/Lower/default-initialization-globals.f90 index aa923f49170c..384d1cb763ad 100644 --- a/flang/test/Lower/default-initialization-globals.f90 +++ b/flang/test/Lower/default-initialization-globals.f90 @@ -1,5 +1,6 @@ ! Test default initialization of global variables (static init) -! RUN: bbc -hlfir=false %s -o - | FileCheck %s +! RUN: bbc -hlfir=false %s -o - | FileCheck %s --check-prefixes=%if system-aix %{"CHECK","CHECK-BE"%} \ +! RUN: %else %{"CHECK","CHECK-LE"%} module tinit real, target :: ziel(100) @@ -191,7 +192,8 @@ subroutine eqv_same_default_init() type(tseq), save :: somet1(2), somet2 equivalence (somet1(1), somet2) ! CHECK-LABEL: fir.global internal @_QFeqv_same_default_initEsomet1 : !fir.array<2xi64> { - ! CHECK: %[[VAL_62:.*]] = arith.constant 12884901890 : i64 + ! CHECK-LE: %[[VAL_62:.*]] = arith.constant 12884901890 : i64 + ! CHECK-BE: %[[VAL_62:.*]] = arith.constant 8589934595 : i64 ! CHECK: %[[VAL_63:.*]] = fir.undefined !fir.array<2xi64> ! CHECK: %[[VAL_64:.*]] = fir.insert_on_range %[[VAL_63]], %[[VAL_62]] from (0) to (1) : (!fir.array<2xi64>, i64) -> !fir.array<2xi64> ! CHECK: fir.has_value %[[VAL_64]] : !fir.array<2xi64> diff --git a/flang/test/Lower/dispatch.f90 b/flang/test/Lower/dispatch.f90 index 1658cc0d75ad..1aad4a4b8e46 100644 --- a/flang/test/Lower/dispatch.f90 +++ b/flang/test/Lower/dispatch.f90 @@ -1,4 +1,4 @@ -! RUN: bbc -polymorphic-type -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: bbc -polymorphic-type -emit-hlfir %s -o - | FileCheck %s ! Tests the different possible type involving polymorphic entities. @@ -49,6 +49,10 @@ module call_dispatch type(node_ptr), pointer :: n end type + type :: q1 + class(p1), allocatable :: p + end type + contains ! ------------------------------------------------------------------------------ @@ -147,20 +151,21 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch( ! CHECK-SAME: %[[P:.*]]: !fir.class> {fir.bindc_name = "p"}) { -! CHECK: fir.dispatch "tbp_nopass"(%[[P]] : !fir.class>){{$}} -! CHECK: fir.dispatch "tbp_pass"(%[[P]] : !fir.class>) (%[[P]] : !fir.class>) {pass_arg_pos = 0 : i32} -! CHECK: fir.dispatch "tbp_pass_arg0"(%[[P]] : !fir.class>) (%[[P]] : !fir.class>) {pass_arg_pos = 0 : i32} -! CHECK: fir.dispatch "tbp_pass_arg1"(%[[P]] : !fir.class>) (%{{.*}}, %[[P]] : !fir.ref, !fir.class>) {pass_arg_pos = 1 : i32} - -! CHECK: fir.dispatch "proc1"(%[[P]] : !fir.class>){{$}} -! CHECK: fir.dispatch "proc2"(%[[P]] : !fir.class>) (%[[P]] : !fir.class>) {pass_arg_pos = 0 : i32} -! CHECK: fir.dispatch "proc3"(%[[P]] : !fir.class>) (%[[P]] : !fir.class>) {pass_arg_pos = 0 : i32} -! CHECK: fir.dispatch "proc4"(%[[P]] : !fir.class>) (%{{.*}}, %[[P]] : !fir.ref, !fir.class>) {pass_arg_pos = 1 : i32} - -! CHECK: %{{.*}} = fir.dispatch "p1_fct1_nopass"(%[[P]] : !fir.class>) -> f32{{$}} -! CHECK: %{{.*}} = fir.dispatch "p1_fct2"(%[[P]] : !fir.class>) (%[[P]] : !fir.class>) -> f32 {pass_arg_pos = 0 : i32} -! CHECK: %{{.*}} = fir.dispatch "p1_fct3_arg0"(%[[P]] : !fir.class>) (%[[P]] : !fir.class>) -> f32 {pass_arg_pos = 0 : i32} -! CHECK: %{{.*}} = fir.dispatch "p1_fct4_arg1"(%[[P]] : !fir.class>) (%{{.*}}, %[[P]] : !fir.ref, !fir.class>) -> f32 {pass_arg_pos = 1 : i32} +! CHECK: %[[P_DECL:.*]]:2 = hlfir.declare %[[P]] {uniq_name = "_QMcall_dispatchFcheck_dispatchEp"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: fir.dispatch "tbp_nopass"(%[[P_DECL]]#1 : !fir.class>){{$}} +! CHECK: fir.dispatch "tbp_pass"(%[[P_DECL]]#0 : !fir.class>) (%[[P_DECL]]#0 : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "tbp_pass_arg0"(%[[P_DECL]]#0 : !fir.class>) (%[[P_DECL]]#0 : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "tbp_pass_arg1"(%[[P_DECL]]#0 : !fir.class>) (%{{.*}}, %[[P_DECL]]#0 : !fir.ref, !fir.class>) {pass_arg_pos = 1 : i32} + +! CHECK: fir.dispatch "proc1"(%[[P_DECL]]#1 : !fir.class>){{$}} +! CHECK: fir.dispatch "proc2"(%[[P_DECL]]#0 : !fir.class>) (%[[P_DECL]]#0 : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "proc3"(%[[P_DECL]]#0 : !fir.class>) (%[[P_DECL]]#0 : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "proc4"(%[[P_DECL]]#0 : !fir.class>) (%{{.*}}, %[[P_DECL]]#0 : !fir.ref, !fir.class>) {pass_arg_pos = 1 : i32} + +! CHECK: %{{.*}} = fir.dispatch "p1_fct1_nopass"(%[[P_DECL]]#1 : !fir.class>) -> f32{{$}} +! CHECK: %{{.*}} = fir.dispatch "p1_fct2"(%[[P_DECL]]#0 : !fir.class>) (%[[P_DECL]]#0 : !fir.class>) -> f32 {pass_arg_pos = 0 : i32} +! CHECK: %{{.*}} = fir.dispatch "p1_fct3_arg0"(%[[P_DECL]]#0 : !fir.class>) (%[[P_DECL]]#0 : !fir.class>) -> f32 {pass_arg_pos = 0 : i32} +! CHECK: %{{.*}} = fir.dispatch "p1_fct4_arg1"(%[[P_DECL]]#0 : !fir.class>) (%{{.*}}, %[[P_DECL]]#0 : !fir.ref, !fir.class>) -> f32 {pass_arg_pos = 1 : i32} subroutine check_dispatch_deferred(a, x) class(a1) :: a @@ -171,7 +176,9 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_deferred( ! CHECK-SAME: %[[ARG0:.*]]: !fir.class> {fir.bindc_name = "a"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: fir.dispatch "nopassd"(%[[ARG0]] : !fir.class>) (%[[ARG1]] : !fir.box>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_deferredEa"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_deferredEx"} : (!fir.box>) -> (!fir.box>, !fir.box>) +! CHECK: fir.dispatch "nopassd"(%[[ARG0_DECL]]#1 : !fir.class>) (%[[ARG1_DECL]]#0 : !fir.box>) subroutine check_dispatch_scalar_allocatable(p) class(p1), allocatable :: p @@ -180,9 +187,10 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_scalar_allocatable( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "p"}) { -! CHECK: %[[LOAD:.*]] = fir.load %[[ARG0]] : !fir.ref>>> +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %arg0 {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_scalar_allocatableEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[LOAD:.*]] = fir.load %[[ARG0_DECL]]#0 : !fir.ref>>> ! CHECK: %[[REBOX:.*]] = fir.rebox %[[LOAD]] : (!fir.class>>) -> !fir.class> -! CHECK: fir.dispatch "tbp_pass"(%[[LOAD]] : !fir.class>>) (%1 : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "tbp_pass"(%[[REBOX]] : !fir.class>) (%[[REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} subroutine check_dispatch_scalar_pointer(p) class(p1), pointer :: p @@ -191,9 +199,10 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_scalar_pointer( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "p"}) { -! CHECK: %[[LOAD:.*]] = fir.load %[[ARG0]] : !fir.ref>>> +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_scalar_pointerEp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[LOAD:.*]] = fir.load %[[ARG0_DECL]]#0 : !fir.ref>>> ! CHECK: %[[REBOX:.*]] = fir.rebox %[[LOAD]] : (!fir.class>>) -> !fir.class> -! CHECK: fir.dispatch "tbp_pass"(%[[LOAD]] : !fir.class>>) (%1 : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: fir.dispatch "tbp_pass"(%[[REBOX]] : !fir.class>) (%[[REBOX]] : !fir.class>) {pass_arg_pos = 0 : i32} subroutine check_dispatch_static_array(p, t) class(p1) :: p(10) @@ -211,15 +220,17 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_static_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.class>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.ref>> {fir.bindc_name = "t"}) { +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_static_arrayEp"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]](%{{.*}}) {uniq_name = "_QMcall_dispatchFcheck_dispatch_static_arrayEt"} : (!fir.ref>>, !fir.shape<1>) -> (!fir.ref>>, !fir.ref>>) ! CHECK: fir.do_loop {{.*}} { -! CHECK: %[[COORD:.*]] = fir.coordinate_of %[[ARG0]], %{{.*}} : (!fir.class>>, i64) -> !fir.ref> -! CHECK: %[[CLASS_BOX:.*]] = fir.embox %[[COORD]] source_box %[[ARG0]] : (!fir.ref>, !fir.class>>) -> !fir.class> -! CHECK: fir.dispatch "tbp_pass"(%[[CLASS_BOX]] : !fir.class>) (%[[CLASS_BOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[ARG0_DECL]]#0 (%{{.*}}) : (!fir.class>>, i64) -> !fir.class> +! CHECK: fir.dispatch "tbp_pass"(%[[DESIGNATE]] : !fir.class>) (%[[DESIGNATE]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK: fir.do_loop {{.*}} { -! CHECK: %[[COORD1:.*]] = fir.coordinate_of %[[ARG1]], %{{.*}} : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[EMBOX:.*]] = fir.embox %[[COORD]] : (!fir.ref>) -> !fir.class> -! CHECK: fir.call @_QMcall_dispatchPtbp_pass(%[[EMBOX]]) {{.*}}: (!fir.class>) -> () +! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[ARG1_DECL]]#0 (%{{.*}}) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[EMBOX:.*]] = fir.embox %[[DESIGNATE]] : (!fir.ref>) -> !fir.box> +! CHECK: %[[CONV:.*]] = fir.convert %[[EMBOX]] : (!fir.box>) -> !fir.class> +! CHECK: fir.call @_QMcall_dispatchPtbp_pass(%[[CONV]]) {{.*}}: (!fir.class>) -> () subroutine check_dispatch_dynamic_array(p, t) class(p1) :: p(:) @@ -237,15 +248,17 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_dynamic_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.class>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.box>> {fir.bindc_name = "t"}) { +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_arrayEp"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_arrayEt"} : (!fir.box>>) -> (!fir.box>>, !fir.box>>) ! CHECK: %{{.*}} = fir.do_loop {{.*}} { -! CHECK: %[[COORD:.*]] = fir.coordinate_of %[[ARG0]], %{{.*}} : (!fir.class>>, i64) -> !fir.ref> -! CHECK: %[[CLASS_BOX:.*]] = fir.embox %[[COORD]] source_box %[[ARG0]] : (!fir.ref>, !fir.class>>) -> !fir.class> -! CHECK: fir.dispatch "tbp_pass"(%[[CLASS_BOX]] : !fir.class>) (%[[CLASS_BOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[ARG0_DECL]]#0 (%{{.*}}) : (!fir.class>>, i64) -> !fir.class> +! CHECK: fir.dispatch "tbp_pass"(%[[DESIGNATE]] : !fir.class>) (%[[DESIGNATE]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK: %{{.*}} = fir.do_loop {{.*}} { -! CHECK: %[[COORD:.*]] = fir.coordinate_of %[[ARG1]], %{{.*}} : (!fir.box>>, i64) -> !fir.ref> -! CHECK: %[[EMBOX:.*]] = fir.embox %[[COORD]] : (!fir.ref>) -> !fir.class> -! CHECK: fir.call @_QMcall_dispatchPtbp_pass(%[[EMBOX]]) {{.*}}: (!fir.class>) -> () +! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[ARG1_DECL]]#0 (%{{.*}}) : (!fir.box>>, i64) -> !fir.ref> +! CHECK: %[[EMBOX:.*]] = fir.embox %[[DESIGNATE]] : (!fir.ref>) -> !fir.box> +! CHECK: %[[CONV:.*]] = fir.convert %[[EMBOX]] : (!fir.box>) -> !fir.class> +! CHECK: fir.call @_QMcall_dispatchPtbp_pass(%[[CONV]]) {{.*}} : (!fir.class>) -> () subroutine check_dispatch_allocatable_array(p, t) class(p1), allocatable :: p(:) @@ -263,22 +276,19 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_allocatable_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.ref>>>> {fir.bindc_name = "t"}) { +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_allocatable_arrayEp"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_allocatable_arrayEt"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %{{.*}} = fir.do_loop {{.*}} { -! CHECK: fir.store %arg3 to %0 : !fir.ref -! CHECK: %[[LOAD_ARG0:.*]] = fir.load %[[ARG0]] : !fir.ref>>>> -! CHECK: %[[C0:.*]] = arith.constant 0 : index -! CHECK: %[[BOX_DIMS_ARG0:.*]]:3 = fir.box_dims %[[LOAD_ARG0]], %[[C0]] : (!fir.class>>>, index) -> (index, index, index) -! CHECK: %[[COORD:.*]] = fir.coordinate_of %[[LOAD_ARG0]], %{{.*}} : (!fir.class>>>, i64) -> !fir.ref> -! CHECK: %[[CLASS_BOX:.*]] = fir.embox %[[COORD]] source_box %[[LOAD_ARG0]] : (!fir.ref>, !fir.class>>>) -> !fir.class> -! CHECK: fir.dispatch "tbp_pass"(%[[CLASS_BOX]] : !fir.class>) (%[[CLASS_BOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: %[[LOAD_ARG0:.*]] = fir.load %[[ARG0_DECL]]#0 : !fir.ref>>>> +! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[LOAD_ARG0]] (%{{.*}}) : (!fir.class>>>, i64) -> !fir.class> +! CHECK: fir.dispatch "tbp_pass"(%[[DESIGNATE]] : !fir.class>) (%[[DESIGNATE]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK: %{{.*}} = fir.do_loop {{.*}} { -! CHECK: %[[LOAD_ARG1:.*]] = fir.load %[[ARG1]] : !fir.ref>>>> -! CHECK: %[[C0:.*]] = arith.constant 0 : index -! CHECK: %[[BOX_DIMS_ARG1:.*]]:3 = fir.box_dims %[[LOAD_ARG1]], %[[C0]] : (!fir.box>>>, index) -> (index, index, index) -! CHECK: %[[COORD:.*]] = fir.coordinate_of %[[LOAD_ARG1]], %{{.*}} : (!fir.box>>>, i64) -> !fir.ref> -! CHECK: %[[EMBOX:.*]] = fir.embox %[[COORD]] : (!fir.ref>) -> !fir.class> -! CHECK: fir.call @_QMcall_dispatchPtbp_pass(%[[EMBOX]]) {{.*}}: (!fir.class>) -> () +! CHECK: %[[LOAD_ARG1:.*]] = fir.load %[[ARG1_DECL]]#0 : !fir.ref>>>> +! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[LOAD_ARG1]] (%{{.*}}) : (!fir.box>>>, i64) -> !fir.ref> +! CHECK: %[[EMBOX:.*]] = fir.embox %[[DESIGNATE]] : (!fir.ref>) -> !fir.box> +! CHECK: %[[CONV:.*]] = fir.convert %[[EMBOX]] : (!fir.box>) -> !fir.class> +! CHECK: fir.call @_QMcall_dispatchPtbp_pass(%[[CONV]]) {{.*}}: (!fir.class>) -> () subroutine check_dispatch_pointer_array(p, t) class(p1), pointer :: p(:) @@ -296,22 +306,20 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_pointer_array( ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.ref>>>> {fir.bindc_name = "t"}) { +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_pointer_arrayEp"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QMcall_dispatchFcheck_dispatch_pointer_arrayEt"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) ! CHECK: %{{.*}} = fir.do_loop {{.*}} { -! CHECK: %[[LOAD_ARG0:.*]] = fir.load %[[ARG0]] : !fir.ref>>>> -! CHECK: %[[C0:.*]] = arith.constant 0 : index -! CHECK: %[[BOX_DIMS_ARG0]]:3 = fir.box_dims %[[LOAD_ARG0]], %[[C0]] : (!fir.class>>>, index) -> (index, index, index) -! CHECK: %[[COORD:.*]] = fir.coordinate_of %[[LOAD_ARG0]], %{{.*}} : (!fir.class>>>, i64) -> !fir.ref> -! CHECK: %[[CLASS_BOX]] = fir.embox %[[COORD]] source_box %[[LOAD_ARG0]] : (!fir.ref>, !fir.class>>>) -> !fir.class> -! CHECK: fir.dispatch "tbp_pass"(%[[CLASS_BOX]] : !fir.class>) (%[[CLASS_BOX]] : !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: %[[LOAD_ARG0:.*]] = fir.load %[[ARG0_DECL]]#0 : !fir.ref>>>> +! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[LOAD_ARG0]] (%{{.*}}) : (!fir.class>>>, i64) -> !fir.class> +! CHECK: fir.dispatch "tbp_pass"(%[[DESIGNATE]] : !fir.class>) (%[[DESIGNATE]] : !fir.class>) {pass_arg_pos = 0 : i32} ! CHECK: %{{.*}} = fir.do_loop {{.*}} { -! CHECK: %[[LOAD_ARG1:.*]] = fir.load %[[ARG1]] : !fir.ref>>>> -! CHECK: %[[C0:.*]] = arith.constant 0 : index -! CHECK: %[[BOX_DIMS_ARG1:.*]]:3 = fir.box_dims %[[LOAD_ARG1]], %[[C0]] : (!fir.box>>>, index) -> (index, index, index) -! CHECK: %[[COORD:.*]] = fir.coordinate_of %[[LOAD_ARG1]], %{{.*}} : (!fir.box>>>, i64) -> !fir.ref> -! CHECK: %[[EMBOX:.*]] = fir.embox %[[COORD]] : (!fir.ref>) -> !fir.class> -! CHECK: fir.call @_QMcall_dispatchPtbp_pass(%[[EMBOX]]) {{.*}}: (!fir.class>) -> () +! CHECK: %[[LOAD_ARG1:.*]] = fir.load %[[ARG1_DECL]]#0 : !fir.ref>>>> +! CHECK: %[[DESIGNATE:.*]] = hlfir.designate %[[LOAD_ARG1]] (%{{.*}}) : (!fir.box>>>, i64) -> !fir.ref> +! CHECK: %[[EMBOX:.*]] = fir.embox %[[DESIGNATE]] : (!fir.ref>) -> !fir.box> +! CHECK: %[[CONV:.*]] = fir.convert %[[EMBOX]] : (!fir.box>) -> !fir.class> +! CHECK: fir.call @_QMcall_dispatchPtbp_pass(%[[CONV]]) fastmath : (!fir.class>) -> () subroutine check_dispatch_dynamic_array_copy(p, o) class(p1) :: p(:) @@ -326,12 +334,13 @@ module call_dispatch ! CHECK-LABEL: func.func @_QMcall_dispatchPcheck_dispatch_dynamic_array_copy( ! CHECK-SAME: %[[ARG0:.*]]: !fir.class>> {fir.bindc_name = "p"}, ! CHECK-SAME: %[[ARG1:.*]]: !fir.class>> {fir.bindc_name = "o"}) { +! CHECK: %[[ARG1_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_array_copyEo"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) +! CHECK: %[[ARG0_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {uniq_name = "_QMcall_dispatchFcheck_dispatch_dynamic_array_copyEp"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) + ! CHECK: %{{.*}} = fir.do_loop {{.*}} { -! CHECK: %[[COORD1:.*]] = fir.coordinate_of %[[ARG0]], %{{.*}} : (!fir.class>>, i64) -> !fir.ref> -! CHECK: %[[CLASS1:.*]] = fir.embox %[[COORD1]] source_box %[[ARG0]] : (!fir.ref>, !fir.class>>) -> !fir.class> -! CHECK: %[[COORD2:.*]] = fir.coordinate_of %[[ARG1]], %{{.*}} : (!fir.class>>, i64) -> !fir.ref> -! CHECK: %[[CLASS2:.*]] = fir.embox %[[COORD2]] source_box %[[ARG1]] : (!fir.ref>, !fir.class>>) -> !fir.class> -! CHECK: fir.dispatch "pass_with_class_arg"(%[[CLASS1]] : !fir.class>) (%[[CLASS1]], %[[CLASS2]] : !fir.class>, !fir.class>) {pass_arg_pos = 0 : i32} +! CHECK: %[[DESIGNATE0:.*]] = hlfir.designate %[[ARG0_DECL]]#0 (%{{.*}}) : (!fir.class>>, i64) -> !fir.class> +! CHECK: %[[DESIGNATE1:.*]] = hlfir.designate %[[ARG1_DECL]]#0 (%{{.*}}) : (!fir.class>>, i64) -> !fir.class> +! CHECK: fir.dispatch "pass_with_class_arg"(%[[DESIGNATE0]] : !fir.class>) (%[[DESIGNATE0]], %[[DESIGNATE1]] : !fir.class>, !fir.class>) {pass_arg_pos = 0 : i32} ! ------------------------------------------------------------------------------ ! Test that direct call is emitted when the type is known @@ -355,4 +364,15 @@ module call_dispatch type(use_node) :: n end subroutine + + subroutine base_component() + type(q1) :: q + allocate(p1::q%p) + + call q%p%tbp_nopass() + end subroutine + +! CHECK-LABEL: func.func @_QMcall_dispatchPbase_component() +! CHECK: fir.dispatch "tbp_nopass"(%{{.*}} : !fir.class>>) + end module diff --git a/flang/test/Lower/forall/forall-construct.f90 b/flang/test/Lower/forall/forall-construct.f90 index 4d2d2d8764e7..6d4dad580ec9 100644 --- a/flang/test/Lower/forall/forall-construct.f90 +++ b/flang/test/Lower/forall/forall-construct.f90 @@ -60,7 +60,7 @@ end subroutine test_forall_construct ! CHECK: %[[VAL_48:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_43]], %[[VAL_47]] : (!fir.box>, i64, i64) -> !fir.ref ! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_48]] : !fir.ref ! CHECK: %[[VAL_50:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: %[[VAL_51:.*]] = arith.cmpf ogt, %[[VAL_49]], %[[VAL_50]] : f32 +! CHECK: %[[VAL_51:.*]] = arith.cmpf ogt, %[[VAL_49]], %[[VAL_50]] {{.*}} : f32 ! CHECK: %[[VAL_52:.*]] = fir.if %[[VAL_51]] -> (!fir.array) { ! CHECK: %[[VAL_53:.*]] = arith.constant 1 : index ! CHECK: %[[VAL_54:.*]] = fir.load %[[VAL_2]] : !fir.ref diff --git a/flang/test/Lower/forall/forall-where.f90 b/flang/test/Lower/forall/forall-where.f90 index 56bce6fc4fc2..af309e63535f 100644 --- a/flang/test/Lower/forall/forall-where.f90 +++ b/flang/test/Lower/forall/forall-where.f90 @@ -172,7 +172,7 @@ end subroutine test_nested_forall_where ! CHECK: %[[VAL_141:.*]] = arith.subi %[[VAL_114]], %[[VAL_139]] : index ! CHECK: %[[VAL_142:.*]] = fir.do_loop %[[VAL_143:.*]] = %[[VAL_140]] to %[[VAL_141]] step %[[VAL_139]] unordered iter_args(%[[VAL_144:.*]] = %[[VAL_122]]) -> (!fir.array) { ! CHECK: %[[VAL_145:.*]] = fir.array_fetch %[[VAL_116]], %[[VAL_143]] : (!fir.array<100xf32>, index) -> f32 -! CHECK: %[[VAL_146:.*]] = arith.cmpf ogt, %[[VAL_145]], %[[VAL_117]] : f32 +! CHECK: %[[VAL_146:.*]] = arith.cmpf ogt, %[[VAL_145]], %[[VAL_117]] {{.*}} : f32 ! CHECK: %[[VAL_147:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_148:.*]] = fir.coordinate_of %[[VAL_102]], %[[VAL_147]] : (!fir.ref>, !fir.heap>>>, i32) -> !fir.ref>> ! CHECK: %[[VAL_149:.*]] = fir.load %[[VAL_148]] : !fir.ref>> diff --git a/flang/test/Lower/host-associated.f90 b/flang/test/Lower/host-associated.f90 index e2db6deb8803..073493d7fe28 100644 --- a/flang/test/Lower/host-associated.f90 +++ b/flang/test/Lower/host-associated.f90 @@ -70,7 +70,7 @@ contains ! CHECK: %[[bb:.*]] = fir.load %[[b]] : !fir.llvm_ptr> ! CHECK-DAG: %[[bd:.*]] = fir.load %[[bb]] : !fir.ref ! CHECK-DAG: %[[ad:.*]] = fir.load %[[aa]] : !fir.ref - ! CHECK: %{{.*}} = arith.cmpf ogt, %[[ad]], %[[bd]] : f32 + ! CHECK: %{{.*}} = arith.cmpf ogt, %[[ad]], %[[bd]] {{.*}} : f32 if (a > b) then b = b + 2.0 end if diff --git a/flang/test/Lower/nullify-polymorphic.f90 b/flang/test/Lower/nullify-polymorphic.f90 index 764aa2948578..005fe93b3543 100644 --- a/flang/test/Lower/nullify-polymorphic.f90 +++ b/flang/test/Lower/nullify-polymorphic.f90 @@ -1,4 +1,4 @@ -! RUN: bbc -polymorphic-type -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: bbc -polymorphic-type -emit-hlfir %s -o - | FileCheck %s module poly type p1 @@ -43,9 +43,10 @@ end ! CHECK-LABEL: func.func @_QMpolyPtest_nullify() ! CHECK: %[[C_DESC:.*]] = fir.alloca !fir.class>> {bindc_name = "c", uniq_name = "_QMpolyFtest_nullifyEc"} +! CHECK: %[[C_DESC_DECL:.*]]:2 = hlfir.declare %28 {fortran_attrs = #fir.var_attrs, uniq_name = "_QMpolyFtest_nullifyEc"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %{{.*}} = fir.call @_FortranAPointerAllocate(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK: %[[DECLARED_TYPE_DESC:.*]] = fir.type_desc !fir.type<_QMpolyTp1{a:i32,b:i32}> -! CHECK: %[[C_DESC_CAST:.*]] = fir.convert %[[C_DESC]] : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[C_DESC_CAST:.*]] = fir.convert %[[C_DESC_DECL]]#1 : (!fir.ref>>>) -> !fir.ref> ! CHECK: %[[TYPE_DESC_CAST:.*]] = fir.convert %[[DECLARED_TYPE_DESC]] : (!fir.tdesc>) -> !fir.ref ! CHECK: %[[RANK:.*]] = arith.constant 0 : i32 ! CHECK: %[[CORANK:.*]] = arith.constant 0 : i32 diff --git a/flang/test/Lower/real-operations-2.f90 b/flang/test/Lower/real-operations-2.f90 index 0323f201f9dd..b8859e952407 100644 --- a/flang/test/Lower/real-operations-2.f90 +++ b/flang/test/Lower/real-operations-2.f90 @@ -8,7 +8,7 @@ REAL(4) :: x0 REAL(4) :: x1 ! CHECK-DAG:[[reg1:%[0-9]+]] = fir.load %arg0 ! CHECK-DAG:[[reg2:%[0-9]+]] = fir.load %arg1 -! CHECK:[[reg3:%[0-9]+]] = arith.cmpf oeq, [[reg1]], [[reg2]] : f32 +! CHECK:[[reg3:%[0-9]+]] = arith.cmpf oeq, [[reg1]], [[reg2]] {{.*}} : f32 ! CHECK:fir.convert [[reg3]] {{.*}} -> !fir.logical<4> eq0_test = x0 .EQ. x1 END FUNCTION @@ -19,7 +19,7 @@ REAL(4) :: x0 REAL(4) :: x1 ! CHECK-DAG:[[reg1:%[0-9]+]] = fir.load %arg0 ! CHECK-DAG:[[reg2:%[0-9]+]] = fir.load %arg1 -! CHECK:[[reg3:%[0-9]+]] = arith.cmpf une, [[reg1]], [[reg2]] : f32 +! CHECK:[[reg3:%[0-9]+]] = arith.cmpf une, [[reg1]], [[reg2]] {{.*}} : f32 ! CHECK:fir.convert [[reg3]] {{.*}} -> !fir.logical<4> ne1_test = x0 .NE. x1 END FUNCTION @@ -30,7 +30,7 @@ REAL(4) :: x0 REAL(4) :: x1 ! CHECK-DAG:[[reg1:%[0-9]+]] = fir.load %arg0 ! CHECK-DAG:[[reg2:%[0-9]+]] = fir.load %arg1 -! CHECK:[[reg3:%[0-9]+]] = arith.cmpf olt, [[reg1]], [[reg2]] : f32 +! CHECK:[[reg3:%[0-9]+]] = arith.cmpf olt, [[reg1]], [[reg2]] {{.*}} : f32 ! CHECK:fir.convert [[reg3]] {{.*}} -> !fir.logical<4> lt2_test = x0 .LT. x1 END FUNCTION @@ -41,7 +41,7 @@ REAL(4) :: x0 REAL(4) :: x1 ! CHECK-DAG:[[reg1:%[0-9]+]] = fir.load %arg0 ! CHECK-DAG:[[reg2:%[0-9]+]] = fir.load %arg1 -! CHECK:[[reg3:%[0-9]+]] = arith.cmpf ole, [[reg1]], [[reg2]] : f32 +! CHECK:[[reg3:%[0-9]+]] = arith.cmpf ole, [[reg1]], [[reg2]] {{.*}} : f32 ! CHECK:fir.convert [[reg3]] {{.*}} -> !fir.logical<4> le3_test = x0 .LE. x1 END FUNCTION @@ -52,7 +52,7 @@ REAL(4) :: x0 REAL(4) :: x1 ! CHECK-DAG:[[reg1:%[0-9]+]] = fir.load %arg0 ! CHECK-DAG:[[reg2:%[0-9]+]] = fir.load %arg1 -! CHECK:[[reg3:%[0-9]+]] = arith.cmpf ogt, [[reg1]], [[reg2]] : f32 +! CHECK:[[reg3:%[0-9]+]] = arith.cmpf ogt, [[reg1]], [[reg2]] {{.*}} : f32 ! CHECK:fir.convert [[reg3]] {{.*}} -> !fir.logical<4> gt4_test = x0 .GT. x1 END FUNCTION @@ -63,7 +63,7 @@ REAL(4) :: x0 REAL(4) :: x1 ! CHECK-DAG:[[reg1:%[0-9]+]] = fir.load %arg0 ! CHECK-DAG:[[reg2:%[0-9]+]] = fir.load %arg1 -! CHECK:[[reg3:%[0-9]+]] = arith.cmpf oge, [[reg1]], [[reg2]] : f32 +! CHECK:[[reg3:%[0-9]+]] = arith.cmpf oge, [[reg1]], [[reg2]] {{.*}} : f32 ! CHECK:fir.convert [[reg3]] {{.*}} -> !fir.logical<4> ge5_test = x0 .GE. x1 END FUNCTION diff --git a/flang/test/Lower/where.f90 b/flang/test/Lower/where.f90 index 117371b19dda..277cead48f48 100644 --- a/flang/test/Lower/where.f90 +++ b/flang/test/Lower/where.f90 @@ -17,7 +17,7 @@ ! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_5]], %[[VAL_12]] : index ! CHECK: %[[VAL_15:.*]] = fir.do_loop %[[VAL_16:.*]] = %[[VAL_13]] to %[[VAL_14]] step %[[VAL_12]] unordered iter_args(%[[VAL_17:.*]] = %[[VAL_11]]) -> (!fir.array<10x!fir.logical<4>>) { ! CHECK: %[[VAL_18:.*]] = fir.array_fetch %[[VAL_7]], %[[VAL_16]] : (!fir.array<10xf32>, index) -> f32 - ! CHECK: %[[VAL_19:.*]] = arith.cmpf ogt, %[[VAL_18]], %[[VAL_8]] : f32 + ! CHECK: %[[VAL_19:.*]] = arith.cmpf ogt, %[[VAL_18]], %[[VAL_8]] {{.*}} : f32 ! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i1) -> !fir.logical<4> ! CHECK: %[[VAL_21:.*]] = fir.array_update %[[VAL_17]], %[[VAL_20]], %[[VAL_16]] : (!fir.array<10x!fir.logical<4>>, !fir.logical<4>, index) -> !fir.array<10x!fir.logical<4>> ! CHECK: fir.result %[[VAL_21]] : !fir.array<10x!fir.logical<4>> @@ -61,7 +61,7 @@ ! CHECK: %[[VAL_55:.*]] = arith.subi %[[VAL_46]], %[[VAL_53]] : index ! CHECK: %[[VAL_56:.*]] = fir.do_loop %[[VAL_57:.*]] = %[[VAL_54]] to %[[VAL_55]] step %[[VAL_53]] unordered iter_args(%[[VAL_58:.*]] = %[[VAL_52]]) -> (!fir.array<10x!fir.logical<4>>) { ! CHECK: %[[VAL_59:.*]] = fir.array_fetch %[[VAL_48]], %[[VAL_57]] : (!fir.array<10xf32>, index) -> f32 - ! CHECK: %[[VAL_60:.*]] = arith.cmpf ogt, %[[VAL_59]], %[[VAL_49]] : f32 + ! CHECK: %[[VAL_60:.*]] = arith.cmpf ogt, %[[VAL_59]], %[[VAL_49]] {{.*}} : f32 ! CHECK: %[[VAL_61:.*]] = fir.convert %[[VAL_60]] : (i1) -> !fir.logical<4> ! CHECK: %[[VAL_62:.*]] = fir.array_update %[[VAL_58]], %[[VAL_61]], %[[VAL_57]] : (!fir.array<10x!fir.logical<4>>, !fir.logical<4>, index) -> !fir.array<10x!fir.logical<4>> ! CHECK: fir.result %[[VAL_62]] : !fir.array<10x!fir.logical<4>> @@ -105,7 +105,7 @@ ! CHECK: %[[VAL_97:.*]] = arith.subi %[[VAL_88]], %[[VAL_95]] : index ! CHECK: %[[VAL_98:.*]] = fir.do_loop %[[VAL_99:.*]] = %[[VAL_96]] to %[[VAL_97]] step %[[VAL_95]] unordered iter_args(%[[VAL_100:.*]] = %[[VAL_94]]) -> (!fir.array<10x!fir.logical<4>>) { ! CHECK: %[[VAL_101:.*]] = fir.array_fetch %[[VAL_90]], %[[VAL_99]] : (!fir.array<10xf32>, index) -> f32 - ! CHECK: %[[VAL_102:.*]] = arith.cmpf ogt, %[[VAL_101]], %[[VAL_91]] : f32 + ! CHECK: %[[VAL_102:.*]] = arith.cmpf ogt, %[[VAL_101]], %[[VAL_91]] {{.*}} : f32 ! CHECK: %[[VAL_103:.*]] = fir.convert %[[VAL_102]] : (i1) -> !fir.logical<4> ! CHECK: %[[VAL_104:.*]] = fir.array_update %[[VAL_100]], %[[VAL_103]], %[[VAL_99]] : (!fir.array<10x!fir.logical<4>>, !fir.logical<4>, index) -> !fir.array<10x!fir.logical<4>> ! CHECK: fir.result %[[VAL_104]] : !fir.array<10x!fir.logical<4>> diff --git a/flang/test/Semantics/kinds04_q10.f90 b/flang/test/Semantics/kinds04_q10.f90 index 07da32e92c0f..fbde6ed4c8cc 100644 --- a/flang/test/Semantics/kinds04_q10.f90 +++ b/flang/test/Semantics/kinds04_q10.f90 @@ -8,6 +8,7 @@ ! This test is for x86_64, where exponent-letter 'q' is for ! 10-byte extended precision ! UNSUPPORTED: system-windows +! REQUIRES: x86-registered-target subroutine s(var) real :: realvar1 = 4.0E6_4 diff --git a/flang/test/Semantics/real10-x86-01.f90 b/flang/test/Semantics/real10-x86-01.f90 index 8e59fa842e21..ccaf34d8332a 100644 --- a/flang/test/Semantics/real10-x86-01.f90 +++ b/flang/test/Semantics/real10-x86-01.f90 @@ -1,4 +1,5 @@ ! RUN: %python %S/test_symbols.py %s %flang_fc1 -triple x86_64-unknown-linux-gnu +! REQUIRES: x86-registered-target !DEF: /MainProgram1/rpdt DerivedType !DEF: /MainProgram1/rpdt/k TypeParam INTEGER(4) diff --git a/flang/test/Semantics/real10-x86-02.f90 b/flang/test/Semantics/real10-x86-02.f90 index 1e7c0de39305..9cbc85d91c4d 100644 --- a/flang/test/Semantics/real10-x86-02.f90 +++ b/flang/test/Semantics/real10-x86-02.f90 @@ -1,6 +1,7 @@ ! RUN: %python %S/test_modfile.py %s %flang_fc1 -triple x86_64-unknown-linux-gnu ! Intrinsics SELECTED_INT_KIND, SELECTED_REAL_KIND, PRECISION, RANGE, ! RADIX, DIGITS +! REQUIRES: x86-registered-target module m1 ! REAL(KIND=10) handles 16 <= P < 19 (if available; ifort is KIND=16) diff --git a/flang/test/Semantics/realkinds-aarch64-01.f90 b/flang/test/Semantics/realkinds-aarch64-01.f90 index c316e2510324..e22920ff991e 100644 --- a/flang/test/Semantics/realkinds-aarch64-01.f90 +++ b/flang/test/Semantics/realkinds-aarch64-01.f90 @@ -1,3 +1,4 @@ +! REQUIRES: aarch64-registered-target ! RUN: %python %S/test_modfile.py %s %flang_fc1 -triple aarch64-unknown-linux-gnu module m1 diff --git a/flang/test/Transforms/simplifyintrinsics.fir b/flang/test/Transforms/simplifyintrinsics.fir index 8cb2dcfe31d7..39483a9cc18f 100644 --- a/flang/test/Transforms/simplifyintrinsics.fir +++ b/flang/test/Transforms/simplifyintrinsics.fir @@ -2028,7 +2028,7 @@ func.func @_QPtestminloc_works1d_scalarmask_f64(%arg0: !fir.ref (f64) { // CHECK: %[[INARR_ITEM:.*]] = fir.coordinate_of %[[BOX_INARR]], %[[ITER]] : (!fir.box>, index) -> !fir.ref // CHECK: %[[INARR_ITEMVAL:.*]] = fir.load %[[INARR_ITEM]] : !fir.ref -// CHECK: %[[NEW_MIN:.*]] = arith.cmpf olt, %[[INARR_ITEMVAL]], %[[MIN]] : f64 +// CHECK: %[[NEW_MIN:.*]] = arith.cmpf olt, %[[INARR_ITEMVAL]], %[[MIN]] fastmath<{{.*}}> : f64 // CHECK: %[[IF_NEW_MIN:.*]] = fir.if %[[NEW_MIN]] -> (f64) { // CHECK: %[[ONE:.*]] = arith.constant 1 : i32 // CHECK: %[[OUTARR_IDX:.*]] = arith.constant 0 : index @@ -2048,7 +2048,7 @@ func.func @_QPtestminloc_works1d_scalarmask_f64(%arg0: !fir.ref : f64 // CHECK: fir.if %[[INIT_NOT_CHANGED]] { // CHECK: %[[FLAG_OUTARR_IDX:.*]] = arith.constant 0 : index // CHECK: %[[FLAG_OUTARR_ITEM:.*]] = fir.coordinate_of %[[BOX_OUTARR]], %[[FLAG_OUTARR_IDX]] : (!fir.box>>, index) -> !fir.ref diff --git a/flang/tools/bbc/CMakeLists.txt b/flang/tools/bbc/CMakeLists.txt index cbae4ecd56c9..f21fa3b7bae3 100644 --- a/flang/tools/bbc/CMakeLists.txt +++ b/flang/tools/bbc/CMakeLists.txt @@ -1,5 +1,8 @@ set(LLVM_LINK_COMPONENTS Passes +AllTargetsCodeGens +AllTargetsDescs +AllTargetsInfos TargetParser ) diff --git a/flang/tools/bbc/bbc.cpp b/flang/tools/bbc/bbc.cpp index 0c35d5c8438c..0122cf33b0b6 100644 --- a/flang/tools/bbc/bbc.cpp +++ b/flang/tools/bbc/bbc.cpp @@ -16,6 +16,7 @@ #include "flang/Common/Fortran-features.h" #include "flang/Common/OpenMP-features.h" +#include "flang/Common/Version.h" #include "flang/Common/default-kinds.h" #include "flang/Lower/Bridge.h" #include "flang/Lower/PFTBuilder.h" @@ -39,6 +40,7 @@ #include "flang/Semantics/semantics.h" #include "flang/Semantics/unparse-with-symbols.h" #include "flang/Tools/CrossToolHelpers.h" +#include "flang/Tools/TargetSetup.h" #include "flang/Version.inc" #include "mlir/Dialect/OpenMP/OpenMPDialect.h" #include "mlir/IR/AsmState.h" @@ -50,6 +52,7 @@ #include "mlir/Pass/PassRegistry.h" #include "mlir/Transforms/GreedyPatternRewriteDriver.h" #include "mlir/Transforms/Passes.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Passes/OptimizationLevel.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorOr.h" @@ -63,6 +66,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/Host.h" #include "llvm/TargetParser/Triple.h" +#include //===----------------------------------------------------------------------===// // Some basic command-line options @@ -202,6 +206,10 @@ static llvm::cl::opt enableCUDA("fcuda", static llvm::cl::opt fixedForm("ffixed-form", llvm::cl::desc("enable fixed form"), llvm::cl::init(false)); +static llvm::cl::opt + targetTripleOverride("target", + llvm::cl::desc("Override host target triple"), + llvm::cl::init("")); #define FLANG_EXCLUDE_CODEGEN #include "flang/Tools/CLOptions.inc" @@ -221,6 +229,27 @@ static void registerAllPasses() { fir::registerOptTransformPasses(); } +/// Create a target machine that is at least sufficient to get data-layout +/// information required by flang semantics and lowering. Note that it may not +/// contain all the CPU feature information to get optimized assembly generation +/// from LLVM IR. Drivers that needs to generate assembly from LLVM IR should +/// create a target machine according to their specific options. +static std::unique_ptr +createTargetMachine(llvm::StringRef targetTriple, std::string &error) { + std::string triple{targetTriple}; + if (triple.empty()) + triple = llvm::sys::getDefaultTargetTriple(); + + const llvm::Target *theTarget = + llvm::TargetRegistry::lookupTarget(triple, error); + if (!theTarget) + return nullptr; + return std::unique_ptr{ + theTarget->createTargetMachine(triple, /*CPU=*/"", + /*Features=*/"", llvm::TargetOptions(), + /*Reloc::Model=*/std::nullopt)}; +} + //===----------------------------------------------------------------------===// // Translate Fortran input to FIR, a dialect of MLIR. //===----------------------------------------------------------------------===// @@ -229,7 +258,8 @@ static mlir::LogicalResult convertFortranSourceToMLIR( std::string path, Fortran::parser::Options options, const ProgramName &programPrefix, Fortran::semantics::SemanticsContext &semanticsContext, - const mlir::PassPipelineCLParser &passPipeline) { + const mlir::PassPipelineCLParser &passPipeline, + const llvm::TargetMachine &targetMachine) { // prep for prescan and parse Fortran::parser::Parsing parsing{semanticsContext.allCookedSources()}; @@ -295,6 +325,8 @@ static mlir::LogicalResult convertFortranSourceToMLIR( auto &defKinds = semanticsContext.defaultKinds(); fir::KindMapping kindMap( &ctx, llvm::ArrayRef{fir::fromDefaultKinds(defKinds)}); + const llvm::DataLayout &dataLayout = targetMachine.createDataLayout(); + std::string targetTriple = targetMachine.getTargetTriple().normalize(); // Use default lowering options for bbc. Fortran::lower::LoweringOptions loweringOptions{}; loweringOptions.setPolymorphicTypeImpl(enablePolymorphic); @@ -302,8 +334,9 @@ static mlir::LogicalResult convertFortranSourceToMLIR( loweringOptions.setLowerToHighLevelFIR(useHLFIR || emitHLFIR); auto burnside = Fortran::lower::LoweringBridge::create( ctx, semanticsContext, defKinds, semanticsContext.intrinsics(), - semanticsContext.targetCharacteristics(), parsing.allCooked(), "", - kindMap, loweringOptions, {}, semanticsContext.languageFeatures()); + semanticsContext.targetCharacteristics(), parsing.allCooked(), + targetTriple, kindMap, loweringOptions, {}, + semanticsContext.languageFeatures(), &dataLayout); burnside.lower(parseTree, semanticsContext); mlir::ModuleOp mlirModule = burnside.getModule(); if (enableOpenMP) { @@ -388,6 +421,8 @@ static mlir::LogicalResult convertFortranSourceToMLIR( int main(int argc, char **argv) { [[maybe_unused]] llvm::InitLLVM y(argc, argv); + llvm::InitializeAllTargets(); + llvm::InitializeAllTargetMCs(); registerAllPasses(); mlir::registerMLIRContextCLOptions(); @@ -453,17 +488,21 @@ int main(int argc, char **argv) { .set_warnOnNonstandardUsage(warnStdViolation) .set_warningsAreErrors(warnIsError); - llvm::Triple targetTriple{llvm::Triple( - llvm::Triple::normalize(llvm::sys::getDefaultTargetTriple()))}; - // FIXME: Handle real(3) ? - if (targetTriple.getArch() != llvm::Triple::ArchType::x86 && - targetTriple.getArch() != llvm::Triple::ArchType::x86_64) { - semanticsContext.targetCharacteristics().DisableType( - Fortran::common::TypeCategory::Real, /*kind=*/10); + std::string error; + // Create host target machine. + std::unique_ptr targetMachine = + createTargetMachine(targetTripleOverride, error); + if (!targetMachine) { + llvm::errs() << "failed to create target machine: " << error << "\n"; + return mlir::failed(mlir::failure()); } - if (targetTriple.isPPC()) - semanticsContext.targetCharacteristics().set_isPPC(true); - - return mlir::failed(convertFortranSourceToMLIR( - inputFilename, options, programPrefix, semanticsContext, passPipe)); + std::string compilerVersion = Fortran::common::getFlangToolFullVersion("bbc"); + std::string compilerOptions = ""; + Fortran::tools::setUpTargetCharacteristics( + semanticsContext.targetCharacteristics(), *targetMachine, compilerVersion, + compilerOptions); + + return mlir::failed( + convertFortranSourceToMLIR(inputFilename, options, programPrefix, + semanticsContext, passPipe, *targetMachine)); } diff --git a/flang/tools/f18/CMakeLists.txt b/flang/tools/f18/CMakeLists.txt index 270124bce324..ba6c6642c0b6 100644 --- a/flang/tools/f18/CMakeLists.txt +++ b/flang/tools/f18/CMakeLists.txt @@ -49,9 +49,14 @@ if (NOT CMAKE_CROSSCOMPILING) # The module contains PPC vector types that needs the PPC target. set(opts "") - if(${filename} STREQUAL "__ppc_intrinsics" OR - ${filename} STREQUAL "mma") - set(opts "--target=ppc64le") + if(${filename} STREQUAL "__ppc_intrinsics" OR + ${filename} STREQUAL "mma") + if (PowerPC IN_LIST LLVM_TARGETS_TO_BUILD) + set(opts "--target=ppc64le") + else() + # Do not compile PPC module if the target is not available. + continue() + endif() endif() add_custom_command(OUTPUT ${base}.mod diff --git a/flang/tools/tco/tco.cpp b/flang/tools/tco/tco.cpp index a649535a39b7..d5f5cd0002ed 100644 --- a/flang/tools/tco/tco.cpp +++ b/flang/tools/tco/tco.cpp @@ -14,6 +14,7 @@ #include "flang/Optimizer/CodeGen/CodeGen.h" #include "flang/Optimizer/Dialect/Support/FIRContext.h" #include "flang/Optimizer/Dialect/Support/KindMapping.h" +#include "flang/Optimizer/Support/DataLayout.h" #include "flang/Optimizer/Support/InitFIR.h" #include "flang/Optimizer/Support/InternalNames.h" #include "flang/Optimizer/Transforms/Passes.h" @@ -61,9 +62,8 @@ static cl::opt codeGenLLVM( #include "flang/Tools/CLOptions.inc" -static void printModuleBody(mlir::ModuleOp mod, raw_ostream &output) { - for (auto &op : *mod.getBody()) - output << op << '\n'; +static void printModule(mlir::ModuleOp mod, raw_ostream &output) { + output << mod << '\n'; } // compile a .fir file @@ -104,6 +104,10 @@ compileFIR(const mlir::PassPipelineCLParser &passPipeline) { fir::KindMapping kindMap{&context}; fir::setTargetTriple(*owningRef, targetTriple); fir::setKindMapping(*owningRef, kindMap); + // tco is a testing tool, so it will happily use the target independent + // data layout if none is on the module. + fir::support::setMLIRDataLayoutFromAttributes(*owningRef, + /*allowDefaultLayout=*/true); mlir::PassManager pm((*owningRef)->getName(), mlir::OpPassManager::Nesting::Implicit); pm.enableVerifier(/*verifyPasses=*/true); @@ -135,13 +139,13 @@ compileFIR(const mlir::PassPipelineCLParser &passPipeline) { if (mlir::succeeded(pm.run(*owningRef))) { // passes ran successfully, so keep the output if ((emitFir || passPipeline.hasAnyOccurrences()) && !codeGenLLVM) - printModuleBody(*owningRef, out.os()); + printModule(*owningRef, out.os()); out.keep(); return mlir::success(); } // pass manager failed - printModuleBody(*owningRef, errs()); + printModule(*owningRef, errs()); errs() << "\n\nFAILED: " << inputFilename << '\n'; return mlir::failure(); } diff --git a/flang/unittests/Evaluate/real.cpp b/flang/unittests/Evaluate/real.cpp index 970108289838..ccbaf81f054c 100644 --- a/flang/unittests/Evaluate/real.cpp +++ b/flang/unittests/Evaluate/real.cpp @@ -14,7 +14,9 @@ using Real2 = Scalar>; using Real3 = Scalar>; using Real4 = Scalar>; using Real8 = Scalar>; +#ifdef __x86_64__ using Real10 = Scalar>; +#endif using Real16 = Scalar>; using Integer4 = Scalar>; using Integer8 = Scalar>; @@ -538,7 +540,9 @@ void roundTest(int rm, Rounding rounding, std::uint32_t opds) { basicTests(rm, rounding); basicTests(rm, rounding); basicTests(rm, rounding); +#ifdef __x86_64__ basicTests(rm, rounding); +#endif basicTests(rm, rounding); ScopedHostFloatingPointEnvironment::SetRounding(rounding); subsetTests(rm, rounding, opds); diff --git a/flang/unittests/Frontend/FrontendActionTest.cpp b/flang/unittests/Frontend/FrontendActionTest.cpp index 2ef63e864b92..d57154cb1001 100644 --- a/flang/unittests/Frontend/FrontendActionTest.cpp +++ b/flang/unittests/Frontend/FrontendActionTest.cpp @@ -64,6 +64,13 @@ protected: compInst.createDiagnostics(); invoc = std::make_shared(); + // Set-up default target triple and initialize LLVM Targets so that the + // target data layout can be passed to the frontend. + invoc->getTargetOpts().triple = + llvm::Triple::normalize(llvm::sys::getDefaultTargetTriple()); + llvm::InitializeAllTargets(); + llvm::InitializeAllTargetMCs(); + compInst.setInvocation(std::move(invoc)); compInst.getFrontendOpts().inputs.push_back( FrontendInputFile(inputFilePath, Language::Fortran)); @@ -174,13 +181,7 @@ TEST_F(FrontendActionTest, EmitLLVM) { // Set-up the action kind. compInst.getInvocation().getFrontendOpts().programAction = EmitLLVM; - // Set-up default target triple. - compInst.getInvocation().getTargetOpts().triple = - llvm::Triple::normalize(llvm::sys::getDefaultTargetTriple()); - // Initialise LLVM backend - llvm::InitializeAllTargets(); - llvm::InitializeAllTargetMCs(); llvm::InitializeAllAsmPrinters(); // Set-up the output stream. We are using output buffer wrapped as an output @@ -209,13 +210,7 @@ TEST_F(FrontendActionTest, EmitAsm) { // Set-up the action kind. compInst.getInvocation().getFrontendOpts().programAction = EmitAssembly; - // Set-up default target triple. - compInst.getInvocation().getTargetOpts().triple = - llvm::Triple::normalize(llvm::sys::getDefaultTargetTriple()); - // Initialise LLVM backend - llvm::InitializeAllTargets(); - llvm::InitializeAllTargetMCs(); llvm::InitializeAllAsmPrinters(); // Set-up the output stream. We are using output buffer wrapped as an output diff --git a/flang/unittests/Runtime/CommandTest.cpp b/flang/unittests/Runtime/CommandTest.cpp index 9f66c7924c86..2b648b31666a 100644 --- a/flang/unittests/Runtime/CommandTest.cpp +++ b/flang/unittests/Runtime/CommandTest.cpp @@ -171,7 +171,7 @@ protected: std::string spaces(value->ElementBytes(), ' '); CheckDescriptorEqStr(value.get(), spaces); - CheckDescriptorEqInt(length.get(), 0); + CheckDescriptorEqInt(length.get(), 0); if (errStr) { std::string paddedErrStr(GetPaddedStr(errStr, err->ElementBytes())); @@ -193,7 +193,7 @@ protected: std::string spaces(value->ElementBytes(), ' '); CheckDescriptorEqStr(value.get(), spaces); - CheckDescriptorEqInt(length.get(), 0); + CheckDescriptorEqInt(length.get(), 0); if (errStr) { std::string paddedErrStr(GetPaddedStr(errStr, err->ElementBytes())); @@ -294,7 +294,7 @@ TEST_F(SeveralArguments, ArgValueTooShort) { RTNAME(GetCommandArgument)(1, tooShort.get(), length.get(), errMsg.get()), -1); - CheckDescriptorEqInt(length.get(), 16); + CheckDescriptorEqInt(length.get(), 16); std::string expectedErrMsg{ GetPaddedStr("Value too short", errMsg->ElementBytes())}; CheckDescriptorEqStr(errMsg.get(), expectedErrMsg); @@ -320,7 +320,7 @@ TEST_F(SeveralArguments, CommandErrMsgTooShort) { std::string spaces(value->ElementBytes(), ' '); CheckDescriptorEqStr(value.get(), spaces); - CheckDescriptorEqInt(length.get(), 0); + CheckDescriptorEqInt(length.get(), 0); CheckDescriptorEqStr(errMsg.get(), "Mis"); } @@ -351,7 +351,7 @@ TEST_F(OnlyValidArguments, CommandValueTooShort) { CheckDescriptorEqStr( tooShort.get(), "aProgram -f has/a/few/slashes has\\a\\few\\backslashe"); - CheckDescriptorEqInt(length.get(), 51); + CheckDescriptorEqInt(length.get(), 51); OwningPtr errMsg{CreateEmptyCharDescriptor()}; ASSERT_NE(errMsg, nullptr); @@ -377,7 +377,7 @@ TEST_F(OnlyValidArguments, GetCommandCanTakeNull) { value->ElementBytes())); EXPECT_EQ(0, RTNAME(GetCommand)(nullptr, length.get(), nullptr)); - CheckDescriptorEqInt(length.get(), 51); + CheckDescriptorEqInt(length.get(), 51); } TEST_F(OnlyValidArguments, GetCommandShortLength) { diff --git a/flang/unittests/Runtime/MatmulTranspose.cpp b/flang/unittests/Runtime/MatmulTranspose.cpp index 2362887c414e..fe946f6d5a20 100644 --- a/flang/unittests/Runtime/MatmulTranspose.cpp +++ b/flang/unittests/Runtime/MatmulTranspose.cpp @@ -206,7 +206,7 @@ TEST(MatmulTranspose, Basic) { auto yLog{MakeArray(std::vector{3, 2}, std::vector{false, false, false, true, true, false})}; auto vLog{MakeArray( - std::vector{3}, std::vector{true, false, true})}; + std::vector{3}, std::vector{true, false, true})}; RTNAME(MatmulTranspose)(result, *xLog, *yLog, __FILE__, __LINE__); ASSERT_EQ(result.rank(), 2); EXPECT_EQ(result.GetDimension(0).LowerBound(), 1); diff --git a/libc/cmake/modules/prepare_libc_gpu_build.cmake b/libc/cmake/modules/prepare_libc_gpu_build.cmake index 377bc4eeae8f..f3ccbdc9eb15 100644 --- a/libc/cmake/modules/prepare_libc_gpu_build.cmake +++ b/libc/cmake/modules/prepare_libc_gpu_build.cmake @@ -78,6 +78,9 @@ set(LIBC_GPU_TEST_JOBS "" CACHE STRING "Number of jobs to use for GPU tests") if(LIBC_GPU_TEST_JOBS) set_property(GLOBAL PROPERTY JOB_POOLS LIBC_GPU_TEST_POOL=${LIBC_GPU_TEST_JOBS}) set(LIBC_HERMETIC_TEST_JOB_POOL JOB_POOL LIBC_GPU_TEST_POOL) +else() + set_property(GLOBAL PROPERTY JOB_POOLS LIBC_GPU_TEST_POOL=1) + set(LIBC_HERMETIC_TEST_JOB_POOL JOB_POOL LIBC_GPU_TEST_POOL) endif() set(LIBC_GPU_TEST_ARCHITECTURE "" CACHE STRING "Architecture for the GPU tests") diff --git a/libc/config/linux/aarch64/entrypoints.txt b/libc/config/linux/aarch64/entrypoints.txt index ba3a7c557964..60e0e2b29aed 100644 --- a/libc/config/linux/aarch64/entrypoints.txt +++ b/libc/config/linux/aarch64/entrypoints.txt @@ -136,7 +136,6 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.sys.mman.mprotect libc.src.sys.mman.munmap libc.src.sys.mman.posix_madvise - libc.src.sys.mman.mincore # sys/random.h entrypoints libc.src.sys.random.getrandom @@ -166,6 +165,9 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.sys.wait.wait4 libc.src.sys.wait.waitpid + # sys/prctl.h entrypoints + libc.src.sys.prctl.prctl + # termios.h entrypoints libc.src.termios.cfgetispeed libc.src.termios.cfgetospeed diff --git a/libc/config/linux/app.h b/libc/config/linux/app.h index b17026a7832a..0d2f9475c10d 100644 --- a/libc/config/linux/app.h +++ b/libc/config/linux/app.h @@ -69,7 +69,7 @@ struct Args { // Data structure which captures properties of a linux application. struct AppProperties { // Page size used for the application. - uintptr_t pageSize; + uintptr_t page_size; Args *args; @@ -77,7 +77,7 @@ struct AppProperties { TLSImage tls; // Environment data. - EnvironType *envPtr; + EnvironType *env_ptr; }; extern AppProperties app; diff --git a/libc/config/linux/arm/entrypoints.txt b/libc/config/linux/arm/entrypoints.txt index b7783ace90a8..123c7e33377a 100644 --- a/libc/config/linux/arm/entrypoints.txt +++ b/libc/config/linux/arm/entrypoints.txt @@ -92,6 +92,9 @@ set(TARGET_LIBC_ENTRYPOINTS # sys/mman.h entrypoints libc.src.sys.mman.mmap libc.src.sys.mman.munmap + + # sys/prctl.h entrypoints + libc.src.sys.prctl.prctl ) set(TARGET_LIBM_ENTRYPOINTS diff --git a/libc/config/linux/riscv/entrypoints.txt b/libc/config/linux/riscv/entrypoints.txt index 63c1f9227f91..948708e35f45 100644 --- a/libc/config/linux/riscv/entrypoints.txt +++ b/libc/config/linux/riscv/entrypoints.txt @@ -142,7 +142,6 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.sys.mman.mprotect libc.src.sys.mman.munmap libc.src.sys.mman.posix_madvise - libc.src.sys.mman.mincore # sys/random.h entrypoints libc.src.sys.random.getrandom @@ -172,6 +171,9 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.sys.wait.wait4 libc.src.sys.wait.waitpid + # sys/prctl.h entrypoints + libc.src.sys.prctl.prctl + # termios.h entrypoints libc.src.termios.cfgetispeed libc.src.termios.cfgetospeed diff --git a/libc/config/linux/x86_64/entrypoints.txt b/libc/config/linux/x86_64/entrypoints.txt index eb5457678e99..13b81d3b7ca7 100644 --- a/libc/config/linux/x86_64/entrypoints.txt +++ b/libc/config/linux/x86_64/entrypoints.txt @@ -142,7 +142,6 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.sys.mman.mprotect libc.src.sys.mman.munmap libc.src.sys.mman.posix_madvise - libc.src.sys.mman.mincore # sys/random.h entrypoints libc.src.sys.random.getrandom @@ -175,6 +174,9 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.sys.wait.wait4 libc.src.sys.wait.waitpid + # sys/prctl.h entrypoints + libc.src.sys.prctl.prctl + # termios.h entrypoints libc.src.termios.cfgetispeed libc.src.termios.cfgetospeed diff --git a/libc/docs/dev/undefined_behavior.rst b/libc/docs/dev/undefined_behavior.rst index 7a6b5d71b35d..0cb25c7f2a23 100644 --- a/libc/docs/dev/undefined_behavior.rst +++ b/libc/docs/dev/undefined_behavior.rst @@ -62,3 +62,10 @@ Often the standard will imply an intended behavior through what it states is und Ignoring Bug-For-Bug Compatibility ---------------------------------- Any long running implementations will have bugs and deviations from the standard. Hyrum's Law states that “all observable behaviors of your system will be depended on by somebody” which includes these bugs. An example of a long-standing bug is glibc's scanf float parsing behavior. The behavior is specifically defined in the standard, but it isn't adhered to by all libc implementations. There is a longstanding bug in glibc where it incorrectly parses the string 100er and this caused the C standard to add that specific example to the definition for scanf. The intended behavior is for scanf, when parsing a float, to parse the longest possibly valid prefix and then accept it if and only if that complete parsed value is a float. In the case of 100er the longest possibly valid prefix is 100e but the float parsed from that string is only 100. Since there is no number after the e it shouldn't be included in the float, so scanf should return a parsing error. For LLVM's libc it was decided to follow the standard, even though glibc's version is slightly simpler to implement and this edge case is rare. Following the standard must be the first priority, since that's the goal of the library. + +Design Decisions +================ + +Resizable Tables for hsearch +---------------------------- +The POSIX.1 standard does not delineate the behavior consequent to invoking hsearch or hdestroy without prior initialization of the hash table via hcreate. Furthermore, the standard does not specify the outcomes of successive invocations of hsearch absent intervening hdestroy calls. Libraries such as MUSL and Glibc do not apply checks to these scenarios, potentially leading to memory corruption or leakage. Conversely, FreeBSD's libc and Bionic automatically initialize the hash table to a minimal size if it is found uninitialized, and proceeding to destroy the table only if initialization has occurred. This approach also avoids redundant table allocation if an initialized hash table is already present. Given that the hash table starts with a minimal size, resizing becomes necessary to accommodate additional user insertions. LLVM's libc mirrors the approach of FreeBSD's libc and Bionic, owing to its enhanced robustness and user-friendliness. Notably, such resizing behavior itself aligns with POSIX.1 standards, which explicitly permit implementations to modify the capacity of the hash table. diff --git a/libc/include/sys/prctl.h.def b/libc/include/sys/prctl.h.def index 3c29719837ca..0a11543d0729 100644 --- a/libc/include/sys/prctl.h.def +++ b/libc/include/sys/prctl.h.def @@ -15,8 +15,6 @@ // the macros itself. #include -// TODO: Define the prctl macros. - %%public_api() #endif // LLVM_LIBC_SYS_PRCTL_H diff --git a/libc/spec/linux.td b/libc/spec/linux.td index eab0a987b920..ba5f99c12ecd 100644 --- a/libc/spec/linux.td +++ b/libc/spec/linux.td @@ -76,20 +76,7 @@ def Linux : StandardSpec<"Linux"> { HeaderSpec SysMMan = HeaderSpec< "sys/mman.h", - [Macro<"MAP_ANONYMOUS">], - [], // Types - [], // Enumerations - [ - FunctionSpec< - "mincore", - RetValSpec, - [ - ArgSpec, - ArgSpec, - ArgSpec, - ] - >, - ] // Functions + [Macro<"MAP_ANONYMOUS">] >; diff --git a/libc/spec/spec.td b/libc/spec/spec.td index 818cfaee6b61..9b689b5eb502 100644 --- a/libc/spec/spec.td +++ b/libc/spec/spec.td @@ -49,7 +49,6 @@ def FloatType : NamedType<"float">; def DoubleType : NamedType<"double">; def LongDoubleType : NamedType<"long double">; def CharType : NamedType<"char">; -def UnsignedCharType : NamedType<"unsigned char">; // TODO: Add compatibility layer to use C23 type _Float128 if possible. def Float128Type : NamedType<"__float128">; @@ -110,7 +109,6 @@ def IntPtr : PtrType; def RestrictedIntPtr : RestrictedPtrType; def FloatPtr : PtrType; def DoublePtr : PtrType; -def UnsignedCharPtr : PtrType; def SigHandlerT : NamedType<"__sighandler_t">; diff --git a/libc/src/__support/CMakeLists.txt b/libc/src/__support/CMakeLists.txt index ba80965b5aaa..502bf72ae990 100644 --- a/libc/src/__support/CMakeLists.txt +++ b/libc/src/__support/CMakeLists.txt @@ -135,13 +135,13 @@ add_header_library( .str_to_num_result .uint128 libc.src.__support.common + libc.src.__support.CPP.bit libc.src.__support.CPP.limits libc.src.__support.CPP.optional libc.src.__support.FPUtil.dyadic_float libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.rounding_mode - libc.src.__support.bit libc.src.errno.errno ) @@ -188,9 +188,10 @@ add_header_library( HDRS integer_utils.h DEPENDS - .bit + .math_extras .number_pair libc.src.__support.common + libc.src.__support.CPP.bit libc.src.__support.CPP.type_traits ) @@ -199,11 +200,11 @@ add_header_library( HDRS UInt.h DEPENDS - .bit .integer_utils .math_extras .number_pair libc.src.__support.CPP.array + libc.src.__support.CPP.bit libc.src.__support.CPP.type_traits libc.src.__support.macros.optimization ) @@ -230,8 +231,9 @@ add_header_library( HDRS hash.h DEPENDS - .bit .uint128 + libc.src.__support.CPP.bit + libc.src.__support.CPP.limits libc.src.__support.macros.attributes ) diff --git a/libc/src/__support/FPUtil/CMakeLists.txt b/libc/src/__support/FPUtil/CMakeLists.txt index 58a182eaa797..3d6d712fc205 100644 --- a/libc/src/__support/FPUtil/CMakeLists.txt +++ b/libc/src/__support/FPUtil/CMakeLists.txt @@ -41,7 +41,6 @@ add_header_library( libc.src.__support.common libc.src.__support.CPP.bit libc.src.__support.CPP.type_traits - libc.src.__support.bit ) add_header_library( @@ -146,7 +145,6 @@ add_header_library( libc.src.__support.common libc.src.__support.CPP.bit libc.src.__support.CPP.type_traits - libc.src.__support.bit libc.src.__support.uint128 ) diff --git a/libc/src/__support/FPUtil/FPBits.h b/libc/src/__support/FPUtil/FPBits.h index f5b73440de21..ca98aa712624 100644 --- a/libc/src/__support/FPUtil/FPBits.h +++ b/libc/src/__support/FPUtil/FPBits.h @@ -11,7 +11,6 @@ #include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/bit.h" #include "src/__support/common.h" #include "src/__support/macros/attributes.h" // LIBC_INLINE @@ -222,7 +221,7 @@ template struct FPBits { LIBC_INLINE static constexpr FPBits make_value(UIntType number, int ep) { FPBits result; // offset: +1 for sign, but -1 for implicit first bit - int lz = unsafe_clz(number) - FloatProp::EXPONENT_WIDTH; + int lz = cpp::countl_zero(number) - FloatProp::EXPONENT_WIDTH; number <<= lz; ep -= lz; diff --git a/libc/src/__support/FPUtil/Hypot.h b/libc/src/__support/FPUtil/Hypot.h index db2a62fbdf2a..8a6eb4b920ac 100644 --- a/libc/src/__support/FPUtil/Hypot.h +++ b/libc/src/__support/FPUtil/Hypot.h @@ -16,7 +16,6 @@ #include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" #include "src/__support/UInt128.h" -#include "src/__support/bit.h" #include "src/__support/common.h" namespace LIBC_NAMESPACE { @@ -28,7 +27,7 @@ template LIBC_INLINE T find_leading_one(T mant, int &shift_length) { shift_length = 0; if (mant > 0) { - shift_length = (sizeof(mant) * 8) - 1 - unsafe_clz(mant); + shift_length = (sizeof(mant) * 8) - 1 - cpp::countl_zero(mant); } return T(1) << shift_length; } @@ -37,9 +36,13 @@ LIBC_INLINE T find_leading_one(T mant, int &shift_length) { template struct DoubleLength; -template <> struct DoubleLength { using Type = uint32_t; }; +template <> struct DoubleLength { + using Type = uint32_t; +}; -template <> struct DoubleLength { using Type = uint64_t; }; +template <> struct DoubleLength { + using Type = uint64_t; +}; template <> struct DoubleLength { using Type = UInt128; diff --git a/libc/src/__support/FPUtil/generic/CMakeLists.txt b/libc/src/__support/FPUtil/generic/CMakeLists.txt index c799d502b47d..b17f32521047 100644 --- a/libc/src/__support/FPUtil/generic/CMakeLists.txt +++ b/libc/src/__support/FPUtil/generic/CMakeLists.txt @@ -11,7 +11,6 @@ add_header_library( libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.rounding_mode - libc.src.__support.bit libc.src.__support.uint128 ) @@ -21,13 +20,13 @@ add_header_library( FMA.h DEPENDS libc.src.__support.common + libc.src.__support.CPP.bit libc.src.__support.CPP.type_traits libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.float_properties libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.rounding_mode libc.src.__support.macros.optimization - libc.src.__support.bit libc.src.__support.uint128 ) @@ -37,12 +36,12 @@ add_header_library( FMod.h DEPENDS libc.src.__support.common + libc.src.__support.CPP.bit libc.src.__support.CPP.type_traits libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.float_properties libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.rounding_mode libc.src.__support.macros.optimization - libc.src.__support.bit libc.src.math.generic.math_utils ) diff --git a/libc/src/__support/FPUtil/generic/FMA.h b/libc/src/__support/FPUtil/generic/FMA.h index 5a856d144733..4a825f2f4942 100644 --- a/libc/src/__support/FPUtil/generic/FMA.h +++ b/libc/src/__support/FPUtil/generic/FMA.h @@ -9,13 +9,13 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_GENERIC_FMA_H #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_GENERIC_FMA_H +#include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/FloatProperties.h" #include "src/__support/FPUtil/rounding_mode.h" #include "src/__support/UInt128.h" -#include "src/__support/bit.h" #include "src/__support/macros/attributes.h" // LIBC_INLINE #include "src/__support/macros/optimization.h" // LIBC_UNLIKELY @@ -209,9 +209,9 @@ template <> LIBC_INLINE double fma(double x, double y, double z) { // Normalize the result. if (prod_mant != 0) { uint64_t prod_hi = static_cast(prod_mant >> 64); - int lead_zeros = prod_hi - ? unsafe_clz(prod_hi) - : 64 + unsafe_clz(static_cast(prod_mant)); + int lead_zeros = + prod_hi ? cpp::countl_zero(prod_hi) + : 64 + cpp::countl_zero(static_cast(prod_mant)); // Move the leading 1 to the most significant bit. prod_mant <<= lead_zeros; // The lower 64 bits are always sticky bits after moving the leading 1 to diff --git a/libc/src/__support/FPUtil/generic/FMod.h b/libc/src/__support/FPUtil/generic/FMod.h index 6f934cd4a87b..0e71b039d5c0 100644 --- a/libc/src/__support/FPUtil/generic/FMod.h +++ b/libc/src/__support/FPUtil/generic/FMod.h @@ -9,11 +9,11 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_GENERIC_FMOD_H #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_GENERIC_FMOD_H +#include "src/__support/CPP/bit.h" #include "src/__support/CPP/limits.h" #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" -#include "src/__support/bit.h" #include "src/__support/macros/optimization.h" // LIBC_UNLIKELY #include "src/math/generic/math_utils.h" @@ -229,7 +229,7 @@ private: if (LIBC_LIKELY(sx.uintval() <= sy.uintval())) { if (sx.uintval() < sy.uintval()) - return sx; // |x|<|y| return x + return sx; // |x|<|y| return x return FPB(FPB::zero()); // |x|=|y| return 0.0 } @@ -264,11 +264,11 @@ private: e_y--; } else { m_y = sy.get_mantissa(); - lead_zeros_m_y = unsafe_clz(m_y); + lead_zeros_m_y = cpp::countl_zero(m_y); } // Assume hy != 0 - int tail_zeros_m_y = unsafe_ctz(m_y); + int tail_zeros_m_y = cpp::countr_zero(m_y); int sides_zeroes_count = lead_zeros_m_y + tail_zeros_m_y; // n > 0 by conditions above int exp_diff = e_x - e_y; diff --git a/libc/src/__support/FPUtil/generic/sqrt.h b/libc/src/__support/FPUtil/generic/sqrt.h index b93fa7a35f82..6ae2171bacf7 100644 --- a/libc/src/__support/FPUtil/generic/sqrt.h +++ b/libc/src/__support/FPUtil/generic/sqrt.h @@ -10,13 +10,12 @@ #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_GENERIC_SQRT_H #include "sqrt_80_bit_long_double.h" -#include "src/__support/CPP/bit.h" +#include "src/__support/CPP/bit.h" // countl_zero #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/rounding_mode.h" #include "src/__support/UInt128.h" -#include "src/__support/bit.h" #include "src/__support/common.h" namespace LIBC_NAMESPACE { @@ -37,7 +36,7 @@ template <> struct SpecialLongDouble { template LIBC_INLINE void normalize(int &exponent, typename FPBits::UIntType &mantissa) { - const int shift = unsafe_clz(mantissa) - + const int shift = cpp::countl_zero(mantissa) - (8 * sizeof(mantissa) - 1 - MantissaWidth::VALUE); exponent -= shift; mantissa <<= shift; @@ -52,9 +51,9 @@ LIBC_INLINE void normalize(int &exponent, uint64_t &mantissa) { template <> LIBC_INLINE void normalize(int &exponent, UInt128 &mantissa) { const uint64_t hi_bits = static_cast(mantissa >> 64); - const int shift = hi_bits - ? (unsafe_clz(hi_bits) - 15) - : (unsafe_clz(static_cast(mantissa)) + 49); + const int shift = + hi_bits ? (cpp::countl_zero(hi_bits) - 15) + : (cpp::countl_zero(static_cast(mantissa)) + 49); exponent -= shift; mantissa <<= shift; } @@ -137,7 +136,7 @@ LIBC_INLINE cpp::enable_if_t, T> sqrt(T x) { // We compute one more iteration in order to round correctly. bool lsb = static_cast(y & 1); // Least significant bit - bool rb = false; // Round bit + bool rb = false; // Round bit r <<= 2; UIntType tmp = (y << 2) + 1; if (r >= tmp) { diff --git a/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h b/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h index a3bf7e3cabad..0e7907e82943 100644 --- a/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h +++ b/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h @@ -9,11 +9,11 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_GENERIC_SQRT_80_BIT_LONG_DOUBLE_H #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_GENERIC_SQRT_80_BIT_LONG_DOUBLE_H +#include "src/__support/CPP/bit.h" #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/rounding_mode.h" #include "src/__support/UInt128.h" -#include "src/__support/bit.h" #include "src/__support/common.h" namespace LIBC_NAMESPACE { @@ -22,7 +22,7 @@ namespace x86 { LIBC_INLINE void normalize(int &exponent, UInt128 &mantissa) { const unsigned int shift = static_cast( - unsafe_clz(static_cast(mantissa)) - + cpp::countl_zero(static_cast(mantissa)) - (8 * sizeof(uint64_t) - 1 - MantissaWidth::VALUE)); exponent -= shift; mantissa <<= shift; @@ -101,7 +101,7 @@ LIBC_INLINE long double sqrt(long double x) { // We compute one more iteration in order to round correctly. bool lsb = static_cast(y & 1); // Least significant bit - bool rb = false; // Round bit + bool rb = false; // Round bit r <<= 2; UIntType tmp = (y << 2) + 1; if (r >= tmp) { diff --git a/libc/src/__support/HashTable/CMakeLists.txt b/libc/src/__support/HashTable/CMakeLists.txt index e9b4aa31290a..dce37fdb5143 100644 --- a/libc/src/__support/HashTable/CMakeLists.txt +++ b/libc/src/__support/HashTable/CMakeLists.txt @@ -6,7 +6,7 @@ add_header_library( PREFER_GENERIC DEPENDS libc.src.__support.common - libc.src.__support.bit + libc.src.__support.CPP.bit libc.src.__support.macros.properties.cpu_features ) @@ -25,17 +25,16 @@ add_header_library( table.h DEPENDS .bitmask - libc.src.__support.memory_size - libc.src.__support.bit - libc.src.__support.CPP.type_traits + libc.include.llvm-libc-types.ENTRY + libc.src.__support.CPP.bit libc.src.__support.CPP.new + libc.src.__support.hash libc.src.__support.macros.attributes libc.src.__support.macros.optimization - libc.src.__support.hash + libc.src.__support.memory_size libc.src.string.memset libc.src.string.strcmp libc.src.string.strlen - libc.include.llvm-libc-types.ENTRY ) add_header_library( diff --git a/libc/src/__support/HashTable/bitmask.h b/libc/src/__support/HashTable/bitmask.h index 8247161c449b..f97a7bccde32 100644 --- a/libc/src/__support/HashTable/bitmask.h +++ b/libc/src/__support/HashTable/bitmask.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_HASHTABLE_BITMASK_H #define LLVM_LIBC_SRC___SUPPORT_HASHTABLE_BITMASK_H -#include "src/__support/bit.h" +#include "src/__support/CPP/bit.h" #include "src/__support/macros/properties/cpu_features.h" #include // size_t #include // uint8_t, uint64_t @@ -31,9 +31,7 @@ namespace internal { // | Available | 0b1xxx'xxxx | // | Occupied | 0b0xxx'xxxx | // ============================= -template struct BitMaskAdaptor { - // A masked constant whose bits are all set. - LIBC_INLINE_VAR constexpr static T MASK = WORD_MASK; +template struct BitMaskAdaptor { // A stride in the bitmask may use multiple bits. LIBC_INLINE_VAR constexpr static size_t STRIDE = WORD_STRIDE; @@ -45,7 +43,7 @@ template struct BitMaskAdaptor { // Count trailing zeros with respect to stride. (Assume the bitmask is none // zero.) LIBC_INLINE constexpr size_t lowest_set_bit_nonzero() const { - return unsafe_ctz(word) / WORD_STRIDE; + return cpp::countr_zero(word) / WORD_STRIDE; } }; @@ -73,7 +71,7 @@ template struct IteratableBitMaskAdaptor : public BitMask { return *this; } LIBC_INLINE IteratableBitMaskAdaptor begin() { return *this; } - LIBC_INLINE IteratableBitMaskAdaptor end() { return {0}; } + LIBC_INLINE IteratableBitMaskAdaptor end() { return {BitMask{0}}; } LIBC_INLINE bool operator==(const IteratableBitMaskAdaptor &other) { return this->word == other.word; } diff --git a/libc/src/__support/HashTable/generic/bitmask_impl.inc b/libc/src/__support/HashTable/generic/bitmask_impl.inc index b8d2bfc7a6ff..b825cb5fbc44 100644 --- a/libc/src/__support/HashTable/generic/bitmask_impl.inc +++ b/libc/src/__support/HashTable/generic/bitmask_impl.inc @@ -34,14 +34,14 @@ LIBC_INLINE constexpr bitmask_t repeat_byte(bitmask_t byte) { return byte; } -using BitMask = BitMaskAdaptor; +using BitMask = BitMaskAdaptor; using IteratableBitMask = IteratableBitMaskAdaptor; struct Group { bitmask_t data; // Load a group of control words from an arbitary address. - LIBC_INLINE static Group load(const void *__restrict addr) { + LIBC_INLINE static Group load(const void *addr) { union { bitmask_t value; char bytes[sizeof(bitmask_t)]; @@ -51,6 +51,11 @@ struct Group { return {data.value}; } + // Load a group of control words from an aligned address. + LIBC_INLINE static Group load_aligned(const void *addr) { + return *static_cast(addr); + } + // Find out the lanes equal to the given byte and return the bitmask // with corresponding bits set. LIBC_INLINE IteratableBitMask match_byte(uint8_t byte) const { @@ -98,7 +103,7 @@ struct Group { auto cmp = data ^ repeat_byte(byte); auto result = LIBC_NAMESPACE::Endian::to_little_endian( (cmp - repeat_byte(0x01)) & ~cmp & repeat_byte(0x80)); - return {result}; + return {BitMask{result}}; } // Find out the lanes equal to EMPTY or DELETE (highest bit set) and @@ -106,6 +111,10 @@ struct Group { LIBC_INLINE BitMask mask_available() const { return {LIBC_NAMESPACE::Endian::to_little_endian(data) & repeat_byte(0x80)}; } + + LIBC_INLINE IteratableBitMask occupied() const { + return {static_cast(mask_available().word ^ repeat_byte(0x80))}; + } }; } // namespace internal } // namespace LIBC_NAMESPACE diff --git a/libc/src/__support/HashTable/sse2/bitmask_impl.inc b/libc/src/__support/HashTable/sse2/bitmask_impl.inc index 6308f2fed666..d65240901ed4 100644 --- a/libc/src/__support/HashTable/sse2/bitmask_impl.inc +++ b/libc/src/__support/HashTable/sse2/bitmask_impl.inc @@ -12,17 +12,22 @@ namespace internal { // With SSE2, every bitmask is iteratable as // we use single bit to encode the data. -using BitMask = BitMaskAdaptor; +using BitMask = BitMaskAdaptor; using IteratableBitMask = IteratableBitMaskAdaptor; struct Group { __m128i data; // Load a group of control words from an arbitary address. - LIBC_INLINE static Group load(const void *__restrict addr) { + LIBC_INLINE static Group load(const void *addr) { return {_mm_loadu_si128(static_cast(addr))}; } + // Load a group of control words from an aligned address. + LIBC_INLINE static Group load_aligned(const void *addr) { + return {_mm_load_si128(static_cast(addr))}; + } + // Find out the lanes equal to the given byte and return the bitmask // with corresponding bits set. LIBC_INLINE IteratableBitMask match_byte(uint8_t byte) const { @@ -35,6 +40,10 @@ struct Group { auto bitmask = static_cast(_mm_movemask_epi8(data)); return {bitmask}; } + + LIBC_INLINE IteratableBitMask occupied() const { + return {static_cast(~mask_available().word)}; + } }; } // namespace internal } // namespace LIBC_NAMESPACE diff --git a/libc/src/__support/HashTable/table.h b/libc/src/__support/HashTable/table.h index ec0ec78869ad..d70ca4d23380 100644 --- a/libc/src/__support/HashTable/table.h +++ b/libc/src/__support/HashTable/table.h @@ -10,10 +10,9 @@ #define LLVM_LIBC_SRC___SUPPORT_HASHTABLE_table_H #include "include/llvm-libc-types/ENTRY.h" +#include "src/__support/CPP/bit.h" // bit_ceil #include "src/__support/CPP/new.h" -#include "src/__support/CPP/type_traits.h" #include "src/__support/HashTable/bitmask.h" -#include "src/__support/bit.h" #include "src/__support/hash.h" #include "src/__support/macros/attributes.h" #include "src/__support/macros/optimization.h" @@ -70,7 +69,7 @@ LIBC_INLINE size_t capacity_to_entries(size_t cap) { if (cap < sizeof(Group)) cap = sizeof(Group); // overflow is always checked in allocate() - return next_power_of_two(cap * 8 / 7); + return cpp::bit_ceil(cap * 8 / 7); } // The heap memory layout for N buckets HashTable is as follows: @@ -79,7 +78,7 @@ LIBC_INLINE size_t capacity_to_entries(size_t cap) { // | N * Entry | // ======================= <- align boundary // | Header | -// ======================= +// ======================= <- align boundary (for fast resize) // | (N + 1) * Byte | // ======================= // @@ -94,31 +93,52 @@ private: // How many entries are there in the table. LIBC_INLINE size_t num_of_entries() const { return entries_mask + 1; } + // How many entries can we store in the table before resizing. + LIBC_INLINE size_t full_capacity() const { return num_of_entries() / 8 * 7; } + + // The alignment of the whole memory area is the maximum of the alignment + // among the following types: + // - HashTable + // - ENTRY + // - Group + LIBC_INLINE constexpr static size_t table_alignment() { + size_t left_align = alignof(HashTable) > alignof(ENTRY) ? alignof(HashTable) + : alignof(ENTRY); + return left_align > alignof(Group) ? left_align : alignof(Group); + } + LIBC_INLINE bool is_full() const { return available_slots == 0; } LIBC_INLINE size_t offset_from_entries() const { size_t entries_size = num_of_entries() * sizeof(ENTRY); - return entries_size + offset_to(entries_size, table_alignment()); - } - - LIBC_INLINE constexpr static size_t table_alignment() { - return alignof(HashTable) > alignof(ENTRY) ? alignof(HashTable) - : alignof(ENTRY); + return entries_size + + SafeMemSize::offset_to(entries_size, table_alignment()); } LIBC_INLINE constexpr static size_t offset_to_groups() { - return sizeof(HashTable); + size_t header_size = sizeof(HashTable); + return header_size + SafeMemSize::offset_to(header_size, table_alignment()); } LIBC_INLINE ENTRY &entry(size_t i) { return reinterpret_cast(this)[-i - 1]; } + LIBC_INLINE const ENTRY &entry(size_t i) const { + return reinterpret_cast(this)[-i - 1]; + } + LIBC_INLINE uint8_t &control(size_t i) { uint8_t *ptr = reinterpret_cast(this) + offset_to_groups(); return ptr[i]; } + LIBC_INLINE const uint8_t &control(size_t i) const { + const uint8_t *ptr = + reinterpret_cast(this) + offset_to_groups(); + return ptr[i]; + } + // We duplicate a group of control bytes to the end. Thus, it is possible that // we need to set two control bytes at the same time. LIBC_INLINE void set_ctrl(size_t index, uint8_t value) { @@ -127,6 +147,107 @@ private: control(index2) = value; } + LIBC_INLINE size_t find(const char *key, uint64_t primary) { + uint8_t secondary = secondary_hash(primary); + ProbeSequence sequence{static_cast(primary), 0, entries_mask}; + while (true) { + size_t pos = sequence.next(); + Group ctrls = Group::load(&control(pos)); + IteratableBitMask masks = ctrls.match_byte(secondary); + for (size_t i : masks) { + size_t index = (pos + i) & entries_mask; + ENTRY &entry = this->entry(index); + if (LIBC_LIKELY(entry.key != nullptr && strcmp(entry.key, key) == 0)) + return index; + } + BitMask available = ctrls.mask_available(); + // Since there is no deletion, the first time we find an available slot + // it is also ready to be used as an insertion point. Therefore, we also + // return the first available slot we find. If such entry is empty, the + // key will be nullptr. + if (LIBC_LIKELY(available.any_bit_set())) { + size_t index = + (pos + available.lowest_set_bit_nonzero()) & entries_mask; + return index; + } + } + } + + LIBC_INLINE uint64_t oneshot_hash(const char *key) const { + LIBC_NAMESPACE::internal::HashState hasher = state; + hasher.update(key, strlen(key)); + return hasher.finish(); + } + + // A fast insertion routine without checking if a key already exists. + // Nor does the routine check if the table is full. + // This is only to be used in grow() where we insert all existing entries + // into a new table. Hence, the requirements are naturally satisfied. + LIBC_INLINE ENTRY *unsafe_insert(ENTRY item) { + uint64_t primary = oneshot_hash(item.key); + uint8_t secondary = secondary_hash(primary); + ProbeSequence sequence{static_cast(primary), 0, entries_mask}; + while (true) { + size_t pos = sequence.next(); + Group ctrls = Group::load(&control(pos)); + BitMask available = ctrls.mask_available(); + if (available.any_bit_set()) { + size_t index = + (pos + available.lowest_set_bit_nonzero()) & entries_mask; + set_ctrl(index, secondary); + entry(index).key = item.key; + entry(index).data = item.data; + available_slots--; + return &entry(index); + } + } + } + + LIBC_INLINE HashTable *grow() const { + size_t hint = full_capacity() + 1; + HashState state = this->state; + // migrate to a new random state + state.update(&hint, sizeof(hint)); + HashTable *new_table = allocate(hint, state.finish()); + // It is safe to call unsafe_insert() because we know that: + // - the new table has enough capacity to hold all the entries + // - there is no duplicate key in the old table + if (new_table != nullptr) + for (ENTRY e : *this) + new_table->unsafe_insert(e); + return new_table; + } + + LIBC_INLINE static ENTRY *insert(HashTable *&table, ENTRY item, + uint64_t primary) { + auto index = table->find(item.key, primary); + auto slot = &table->entry(index); + // SVr4 and POSIX.1-2001 specify that action is significant only for + // unsuccessful searches, so that an ENTER should not do anything + // for a successful search. + if (slot->key != nullptr) + return slot; + + // if table of full, we try to grow the table + if (table->is_full()) { + HashTable *new_table = table->grow(); + // allocation failed, return nullptr to indicate failure + if (new_table == nullptr) + return nullptr; + // resized sccuessfully: clean up the old table and use the new one + deallocate(table); + table = new_table; + // it is still valid to use the fastpath insertion. + return table->unsafe_insert(item); + } + + table->set_ctrl(index, secondary_hash(primary)); + slot->key = item.key; + slot->data = item.data; + table->available_slots--; + return slot; + } + public: LIBC_INLINE static void deallocate(HashTable *table) { if (table) { @@ -135,6 +256,7 @@ public: operator delete(ptr, std::align_val_t{table_alignment()}); } } + LIBC_INLINE static HashTable *allocate(size_t capacity, uint64_t randomness) { // check if capacity_to_entries overflows MAX_MEM_SIZE if (capacity > size_t{1} << (8 * sizeof(size_t) - 1 - 3)) @@ -165,68 +287,65 @@ public: return table; } -private: - LIBC_INLINE size_t find(const char *key, uint64_t primary) { - uint8_t secondary = secondary_hash(primary); - ProbeSequence sequence{static_cast(primary), 0, entries_mask}; - while (true) { - size_t pos = sequence.next(); - Group ctrls = Group::load(&control(pos)); - IteratableBitMask masks = ctrls.match_byte(secondary); - for (size_t i : masks) { - size_t index = (pos + i) & entries_mask; - ENTRY &entry = this->entry(index); - if (LIBC_LIKELY(entry.key != nullptr && strcmp(entry.key, key) == 0)) - return index; - } - BitMask available = ctrls.mask_available(); - // Since there is no deletion, the first time we find an available slot - // it is also ready to be used as an insertion point. Therefore, we also - // return the first available slot we find. If such entry is empty, the - // key will be nullptr. - if (LIBC_LIKELY(available.any_bit_set())) { - size_t index = - (pos + available.lowest_set_bit_nonzero()) & entries_mask; - return index; - } + struct FullTableIterator { + size_t current_offset; + size_t remaining; + IteratableBitMask current_mask; + const HashTable &table; + + // It is fine to use remaining to represent the iterator: + // - this comparison only happens with the same table + // - hashtable will not be mutated during the iteration + LIBC_INLINE bool operator==(const FullTableIterator &other) const { + return remaining == other.remaining; + } + LIBC_INLINE bool operator!=(const FullTableIterator &other) const { + return remaining != other.remaining; } - } -private: - LIBC_INLINE ENTRY *insert(ENTRY item, uint64_t primary) { - auto index = find(item.key, primary); - auto slot = &this->entry(index); - // SVr4 and POSIX.1-2001 specify that action is significant only for - // unsuccessful searches, so that an ENTER should not do anything - // for a successful search. - if (slot->key != nullptr) - return slot; + LIBC_INLINE FullTableIterator &operator++() { + this->ensure_valid_group(); + current_mask.remove_lowest_bit(); + remaining--; + return *this; + } + LIBC_INLINE const ENTRY &operator*() { + this->ensure_valid_group(); + return table.entry( + (current_offset + current_mask.lowest_set_bit_nonzero()) & + table.entries_mask); + } - if (!is_full()) { - set_ctrl(index, secondary_hash(primary)); - slot->key = item.key; - slot->data = item.data; - available_slots--; - return slot; + private: + LIBC_INLINE void ensure_valid_group() { + while (!current_mask.any_bit_set()) { + current_offset += sizeof(Group); + // It is ensured that the load will only happen at aligned boundaries. + current_mask = + Group::load_aligned(&table.control(current_offset)).occupied(); + } } - return nullptr; + }; + + using value_type = ENTRY; + using iterator = FullTableIterator; + iterator begin() const { + return {0, full_capacity() - available_slots, + Group::load_aligned(&control(0)).occupied(), *this}; } + iterator end() const { return {0, 0, {0}, *this}; } -public: LIBC_INLINE ENTRY *find(const char *key) { - LIBC_NAMESPACE::internal::HashState hasher = state; - hasher.update(key, strlen(key)); - uint64_t primary = hasher.finish(); + uint64_t primary = oneshot_hash(key); ENTRY &entry = this->entry(find(key, primary)); if (entry.key == nullptr) return nullptr; return &entry; } - LIBC_INLINE ENTRY *insert(ENTRY item) { - LIBC_NAMESPACE::internal::HashState hasher = state; - hasher.update(item.key, strlen(item.key)); - uint64_t primary = hasher.finish(); - return insert(item, primary); + + LIBC_INLINE static ENTRY *insert(HashTable *&table, ENTRY item) { + uint64_t primary = table->oneshot_hash(item.key); + return insert(table, item, primary); } }; } // namespace internal diff --git a/libc/src/__support/UInt.h b/libc/src/__support/UInt.h index dbedfbc4c197..3bec2e3a4713 100644 --- a/libc/src/__support/UInt.h +++ b/libc/src/__support/UInt.h @@ -10,10 +10,10 @@ #define LLVM_LIBC_SRC___SUPPORT_UINT_H #include "src/__support/CPP/array.h" +#include "src/__support/CPP/bit.h" // countl_zero #include "src/__support/CPP/limits.h" #include "src/__support/CPP/optional.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/bit.h" // unsafe_clz #include "src/__support/integer_utils.h" #include "src/__support/macros/attributes.h" // LIBC_INLINE #include "src/__support/macros/optimization.h" // LIBC_UNLIKELY @@ -121,6 +121,7 @@ template struct BigInt { return lo; } } else { + // TODO: silence shift warning return static_cast((static_cast(val[1]) << 64) + lo); } } @@ -556,7 +557,7 @@ template struct BigInt { if (val[i - 1] == 0) { leading_zeroes += sizeof(uint64_t) * 8; } else { - leading_zeroes += unsafe_clz(val[i - 1]); + leading_zeroes += countl_zero(val[i - 1]); break; } } diff --git a/libc/src/__support/bit.h b/libc/src/__support/bit.h deleted file mode 100644 index ba7fc31de122..000000000000 --- a/libc/src/__support/bit.h +++ /dev/null @@ -1,117 +0,0 @@ -//===-- Mimics llvm/ADT/Bit.h -----------------------------------*- C++ -*-===// -// Provides useful bit functions. -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC___SUPPORT_BIT_H -#define LLVM_LIBC_SRC___SUPPORT_BIT_H - -#include "src/__support/CPP/type_traits.h" // make_unsigned -#include "src/__support/macros/attributes.h" // LIBC_INLINE - -namespace LIBC_NAMESPACE { - -// The following overloads are matched based on what is accepted by -// __builtin_clz/ctz* rather than using the exactly-sized aliases from stdint.h. -// This way, we can avoid making any assumptions about integer sizes and let the -// compiler match for us. -namespace __internal { - -template LIBC_INLINE int constexpr correct_zero(T val, int bits) { - if (val == T(0)) - return sizeof(T(0)) * 8; - else - return bits; -} - -template LIBC_INLINE constexpr int clz(T val); -template <> LIBC_INLINE int clz(unsigned char val) { - return __builtin_clz(static_cast(val)) - - 8 * static_cast(sizeof(unsigned int) - sizeof(unsigned char)); -} -template <> LIBC_INLINE int clz(unsigned short val) { - return __builtin_clz(static_cast(val)) - - 8 * static_cast(sizeof(unsigned int) - sizeof(unsigned short)); -} -template <> LIBC_INLINE int clz(unsigned int val) { - return __builtin_clz(val); -} -template <> -LIBC_INLINE constexpr int clz(unsigned long int val) { - return __builtin_clzl(val); -} -template <> -LIBC_INLINE constexpr int -clz(unsigned long long int val) { - return __builtin_clzll(val); -} - -template LIBC_INLINE constexpr int ctz(T val); -template <> LIBC_INLINE int ctz(unsigned char val) { - return __builtin_ctz(static_cast(val)); -} -template <> LIBC_INLINE int ctz(unsigned short val) { - return __builtin_ctz(static_cast(val)); -} -template <> LIBC_INLINE int ctz(unsigned int val) { - return __builtin_ctz(val); -} -template <> -LIBC_INLINE constexpr int ctz(unsigned long int val) { - return __builtin_ctzl(val); -} -template <> -LIBC_INLINE constexpr int -ctz(unsigned long long int val) { - return __builtin_ctzll(val); -} -} // namespace __internal - -template LIBC_INLINE constexpr int safe_ctz(T val) { - return __internal::correct_zero(val, __internal::ctz(val)); -} - -template LIBC_INLINE constexpr int unsafe_ctz(T val) { - return __internal::ctz(val); -} - -template LIBC_INLINE constexpr int safe_clz(T val) { - return __internal::correct_zero(val, __internal::clz(val)); -} - -template LIBC_INLINE constexpr int unsafe_clz(T val) { - return __internal::clz(val); -} - -template LIBC_INLINE constexpr T next_power_of_two(T val) { - if (val == 0) - return 1; - T idx = safe_clz(val - 1); - return static_cast(1) << ((8ull * sizeof(T)) - idx); -} - -template LIBC_INLINE constexpr bool is_power_of_two(T val) { - return val != 0 && (val & (val - 1)) == 0; -} - -template LIBC_INLINE constexpr T offset_to(T val, T align) { - return (-val) & (align - 1); -} - -template LIBC_INLINE constexpr T rotate_left(T val, T amount) { - // Implementation taken from "Safe, Efficient, and Portable Rotate in C/C++" - // https://blog.regehr.org/archives/1063 - // Using the safe version as the rotation pattern is now recognized by both - // GCC and Clang. - using U = cpp::make_unsigned_t; - U v = static_cast(val); - U a = static_cast(amount); - return (v << a) | (v >> ((-a) & (sizeof(U) * 8 - 1))); -} -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_SRC___SUPPORT_BIT_H diff --git a/libc/src/__support/float_to_string.h b/libc/src/__support/float_to_string.h index 1bb4e5c5b924..34c0c0ceef28 100644 --- a/libc/src/__support/float_to_string.h +++ b/libc/src/__support/float_to_string.h @@ -103,7 +103,7 @@ constexpr size_t MID_INT_SIZE = 192; namespace LIBC_NAMESPACE { using BlockInt = uint32_t; -constexpr size_t BLOCK_SIZE = 9; +constexpr uint32_t BLOCK_SIZE = 9; using MantissaInt = fputil::FPBits::UIntType; @@ -136,12 +136,12 @@ LIBC_INLINE constexpr uint32_t log10_pow2(const uint64_t e) { // us the floor, whereas counting the digits of the power of 2 gives us the // ceiling. With a similar loop I checked the maximum valid value and found // 42039. - return (e * 0x13441350fbdll) >> 42; + return static_cast((e * 0x13441350fbdll) >> 42); } // Same as above, but with different constants. LIBC_INLINE constexpr uint32_t log2_pow5(const uint64_t e) { - return (e * 0x12934f0979bll) >> 39; + return static_cast((e * 0x12934f0979bll) >> 39); } // Returns 1 + floor(log_10(2^e). This could technically be off by 1 if any @@ -290,7 +290,7 @@ LIBC_INLINE cpp::UInt get_table_negative(int exponent, size_t i) { } else { ten_blocks = 0; five_blocks = i; - shift_amount = static_cast(shift_amount + (i * BLOCK_SIZE)); + shift_amount = shift_amount + (static_cast(i) * BLOCK_SIZE); } } @@ -488,7 +488,8 @@ public: val = POW10_SPLIT[POW10_OFFSET[idx] + block_index]; #endif - const uint32_t shift_amount = SHIFT_CONST + (IDX_SIZE * idx) - exponent; + const uint32_t shift_amount = + SHIFT_CONST + (static_cast(IDX_SIZE) * idx) - exponent; const uint32_t digits = internal::mul_shift_mod_1e9(mantissa, val, (int32_t)(shift_amount)); return digits; @@ -548,7 +549,8 @@ public: val = POW10_SPLIT_2[p]; #endif - const int32_t shift_amount = SHIFT_CONST + (-exponent - IDX_SIZE * idx); + const int32_t shift_amount = + SHIFT_CONST + (-exponent - (static_cast(IDX_SIZE) * idx)); uint32_t digits = internal::mul_shift_mod_1e9(mantissa, val, shift_amount); return digits; @@ -746,7 +748,8 @@ FloatToString::get_negative_block(int block_index) { block_index + 1); } #endif - const int32_t shift_amount = SHIFT_CONST + (-exponent - IDX_SIZE * idx); + const int32_t shift_amount = + SHIFT_CONST + (-exponent - static_cast(IDX_SIZE * idx)); BlockInt digits = internal::mul_shift_mod_1e9(mantissa, val, shift_amount); return digits; } else { diff --git a/libc/src/__support/hash.h b/libc/src/__support/hash.h index ad12cf79e8d2..6b362ba83189 100644 --- a/libc/src/__support/hash.h +++ b/libc/src/__support/hash.h @@ -9,8 +9,9 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_HASH_H #define LLVM_LIBC_SRC___SUPPORT_HASH_H +#include "src/__support/CPP/bit.h" // rotl +#include "src/__support/CPP/limits.h" // numeric_limits #include "src/__support/UInt128.h" // UInt128 -#include "src/__support/bit.h" // rotate_left #include "src/__support/macros/attributes.h" // LIBC_INLINE #include // For uint64_t @@ -103,7 +104,7 @@ class HashState { uint64_t combined = folded_multiply(low ^ extra_keys[0], high ^ extra_keys[1]); buffer = (buffer + pad) ^ combined; - buffer = rotate_left(buffer, ROTATE); + buffer = cpp::rotl(buffer, ROTATE); } LIBC_INLINE static uint64_t mix(uint64_t seed) { HashState mixer{RANDOMNESS[0][0], RANDOMNESS[0][1], RANDOMNESS[0][2], @@ -152,9 +153,9 @@ public: } } LIBC_INLINE uint64_t finish() { - uint64_t rot = buffer & 63; + int rot = buffer & 63; uint64_t folded = folded_multiply(buffer, pad); - return rotate_left(folded, rot); + return cpp::rotl(folded, rot); } }; diff --git a/libc/src/__support/integer_utils.h b/libc/src/__support/integer_utils.h index 433e99227bcf..1d9a134934cc 100644 --- a/libc/src/__support/integer_utils.h +++ b/libc/src/__support/integer_utils.h @@ -12,7 +12,7 @@ #include "src/__support/CPP/type_traits.h" #include "src/__support/common.h" -#include "bit.h" +#include "math_extras.h" #include "number_pair.h" #include diff --git a/libc/src/__support/memory_size.h b/libc/src/__support/memory_size.h index df179a660471..4c7d2079553e 100644 --- a/libc/src/__support/memory_size.h +++ b/libc/src/__support/memory_size.h @@ -6,11 +6,12 @@ // //===----------------------------------------------------------------------===// +#include "src/__support/CPP/bit.h" // has_single_bit #include "src/__support/CPP/limits.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/bit.h" #include "src/__support/macros/attributes.h" #include "src/__support/macros/optimization.h" +#include "src/string/memory_utils/utils.h" namespace LIBC_NAMESPACE { namespace internal { @@ -37,10 +38,18 @@ private: public: LIBC_INLINE_VAR static constexpr size_t MAX_MEM_SIZE = static_cast(cpp::numeric_limits::max()); + LIBC_INLINE explicit SafeMemSize(size_t value) : value(value <= MAX_MEM_SIZE ? static_cast(value) : -1) {} + + LIBC_INLINE static constexpr size_t offset_to(size_t val, size_t align) { + return (-val) & (align - 1); + } + LIBC_INLINE operator size_t() { return static_cast(value); } + LIBC_INLINE bool valid() { return value >= 0; } + LIBC_INLINE SafeMemSize operator+(const SafeMemSize &other) { type result; if (LIBC_UNLIKELY((value | other.value) < 0)) @@ -48,6 +57,7 @@ public: result = value + other.value; return SafeMemSize{result}; } + LIBC_INLINE SafeMemSize operator*(const SafeMemSize &other) { type result; if (LIBC_UNLIKELY((value | other.value) < 0)) @@ -56,11 +66,12 @@ public: result = -1; return SafeMemSize{result}; } + LIBC_INLINE SafeMemSize align_up(size_t alignment) { - if (!is_power_of_two(alignment) || alignment > MAX_MEM_SIZE || !valid()) + if (!cpp::has_single_bit(alignment) || alignment > MAX_MEM_SIZE || !valid()) return SafeMemSize{type{-1}}; - type offset = LIBC_NAMESPACE::offset_to(value, alignment); + type offset = offset_to(value, alignment); if (LIBC_UNLIKELY(offset > static_cast(MAX_MEM_SIZE) - value)) return SafeMemSize{type{-1}}; diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h index a872c25e2f09..ad73e93f6faa 100644 --- a/libc/src/__support/str_to_float.h +++ b/libc/src/__support/str_to_float.h @@ -16,7 +16,6 @@ #include "src/__support/FPUtil/dyadic_float.h" #include "src/__support/FPUtil/rounding_mode.h" #include "src/__support/UInt128.h" -#include "src/__support/bit.h" #include "src/__support/common.h" #include "src/__support/ctype_utils.h" #include "src/__support/detailed_powers_of_ten.h" @@ -69,12 +68,12 @@ template LIBC_INLINE uint32_t leading_zeroes(T inputNumber) { template <> LIBC_INLINE uint32_t leading_zeroes(uint32_t inputNumber) { - return safe_clz(inputNumber); + return cpp::countl_zero(inputNumber); } template <> LIBC_INLINE uint32_t leading_zeroes(uint64_t inputNumber) { - return safe_clz(inputNumber); + return cpp::countl_zero(inputNumber); } LIBC_INLINE uint64_t low64(const UInt128 &num) { diff --git a/libc/src/__support/threads/linux/thread.cpp b/libc/src/__support/threads/linux/thread.cpp index 5c84266ee5d0..fcf87cc587a5 100644 --- a/libc/src/__support/threads/linux/thread.cpp +++ b/libc/src/__support/threads/linux/thread.cpp @@ -176,7 +176,7 @@ cleanup_thread_resources(ThreadAttributes *attrib) { #endif } -[[gnu::noinline]] LIBC_INLINE void start_thread() { +[[gnu::noinline]] void start_thread() { auto *start_args = reinterpret_cast(get_start_args_addr()); auto *attrib = start_args->thread_attrib; self.attrib = attrib; diff --git a/libc/src/__support/wctype_utils.h b/libc/src/__support/wctype_utils.h index 6d825499a1b0..aa1161c77745 100644 --- a/libc/src/__support/wctype_utils.h +++ b/libc/src/__support/wctype_utils.h @@ -29,8 +29,10 @@ LIBC_INLINE cpp::optional wctob(wint_t c) { // This needs to be translated to EOF at the callsite. This is to avoid // including stdio.h in this file. // The standard states that wint_t may either be an alias of wchar_t or - // an alias of an integer type, so we need to keep the c < 0 check. - if (c > 127 || c < 0) + // an alias of an integer type, different platforms define this type with + // different signedness. This is equivalent to `(c > 127) || (c < 0)` but also + // works without -Wtype-limits warnings when `wint_t` is unsigned. + if ((c & ~127) != 0) return cpp::nullopt; return static_cast(c); } diff --git a/libc/src/math/generic/CMakeLists.txt b/libc/src/math/generic/CMakeLists.txt index 538050221082..214d57842d93 100644 --- a/libc/src/math/generic/CMakeLists.txt +++ b/libc/src/math/generic/CMakeLists.txt @@ -780,7 +780,6 @@ add_entrypoint_object( .explogxf libc.include.errno libc.include.math - libc.src.__support.bit libc.src.__support.CPP.bit libc.src.__support.CPP.optional libc.src.__support.FPUtil.fenv_impl diff --git a/libc/src/math/generic/math_utils.h b/libc/src/math/generic/math_utils.h index 38a14a47e88f..e884fe2deae2 100644 --- a/libc/src/math/generic/math_utils.h +++ b/libc/src/math/generic/math_utils.h @@ -18,24 +18,13 @@ #include -namespace LIBC_NAMESPACE { - -LIBC_INLINE uint32_t as_uint32_bits(float x) { - return cpp::bit_cast(x); -} - -LIBC_INLINE uint64_t as_uint64_bits(double x) { - return cpp::bit_cast(x); -} +// TODO: evaluate which functions from this file are actually used. -LIBC_INLINE float as_float(uint32_t x) { return cpp::bit_cast(x); } +namespace LIBC_NAMESPACE { +// TODO: Remove this, or move it to exp_utils.cpp which is its only user. LIBC_INLINE double as_double(uint64_t x) { return cpp::bit_cast(x); } -LIBC_INLINE uint32_t top12_bits(float x) { return as_uint32_bits(x) >> 20; } - -LIBC_INLINE uint32_t top12_bits(double x) { return as_uint64_bits(x) >> 52; } - // Values to trigger underflow and overflow. template struct XFlowValues; diff --git a/libc/src/math/generic/powf.cpp b/libc/src/math/generic/powf.cpp index 2de8e76b04b5..5f2e95b44e52 100644 --- a/libc/src/math/generic/powf.cpp +++ b/libc/src/math/generic/powf.cpp @@ -18,7 +18,6 @@ #include "src/__support/FPUtil/nearest_integer.h" #include "src/__support/FPUtil/rounding_mode.h" #include "src/__support/FPUtil/sqrt.h" // Speedup for powf(x, 1/2) = sqrtf(x) -#include "src/__support/bit.h" #include "src/__support/common.h" #include "src/__support/macros/optimization.h" // LIBC_UNLIKELY @@ -392,7 +391,7 @@ LIBC_INLINE bool is_odd_integer(float x) { uint32_t x_u = cpp::bit_cast(x); int x_e = static_cast((x_u & FloatProp::EXPONENT_MASK) >> FloatProp::MANTISSA_WIDTH); - int lsb = unsafe_ctz(x_u | FloatProp::EXPONENT_MASK); + int lsb = cpp::countr_zero(x_u | FloatProp::EXPONENT_MASK); constexpr int UNIT_EXPONENT = static_cast(FloatProp::EXPONENT_BIAS + FloatProp::MANTISSA_WIDTH); return (x_e + lsb == UNIT_EXPONENT); @@ -403,7 +402,7 @@ LIBC_INLINE bool is_integer(float x) { uint32_t x_u = cpp::bit_cast(x); int x_e = static_cast((x_u & FloatProp::EXPONENT_MASK) >> FloatProp::MANTISSA_WIDTH); - int lsb = unsafe_ctz(x_u | FloatProp::EXPONENT_MASK); + int lsb = cpp::countr_zero(x_u | FloatProp::EXPONENT_MASK); constexpr int UNIT_EXPONENT = static_cast(FloatProp::EXPONENT_BIAS + FloatProp::MANTISSA_WIDTH); return (x_e + lsb >= UNIT_EXPONENT); diff --git a/libc/src/search/CMakeLists.txt b/libc/src/search/CMakeLists.txt index 4ae5274a3ba9..24a4ba67decf 100644 --- a/libc/src/search/CMakeLists.txt +++ b/libc/src/search/CMakeLists.txt @@ -36,7 +36,7 @@ add_entrypoint_object( DEPENDS libc.src.search.hsearch.global libc.src.__support.HashTable.table - libc.src.__support.libc_assert + libc.src.__support.HashTable.randomness libc.src.errno.errno libc.include.search ) @@ -62,7 +62,6 @@ add_entrypoint_object( DEPENDS libc.src.search.hsearch.global libc.src.__support.HashTable.table - libc.src.__support.libc_assert libc.include.search ) diff --git a/libc/src/search/hcreate.cpp b/libc/src/search/hcreate.cpp index 9c05e317a2d0..4bf638b5920e 100644 --- a/libc/src/search/hcreate.cpp +++ b/libc/src/search/hcreate.cpp @@ -14,6 +14,12 @@ namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(int, hcreate, (size_t capacity)) { + // We follow FreeBSD's implementation here. If the global_hash_table is + // already initialized, this function will do nothing and return 1. + // https://cgit.freebsd.org/src/tree/lib/libc/stdlib/hcreate.c + if (internal::global_hash_table != nullptr) + return 1; + uint64_t randomness = internal::randomness::next_random_seed(); internal::HashTable *table = internal::HashTable::allocate(capacity, randomness); diff --git a/libc/src/search/hdestroy.cpp b/libc/src/search/hdestroy.cpp index 1af64f195e32..3c5ea7b7af03 100644 --- a/libc/src/search/hdestroy.cpp +++ b/libc/src/search/hdestroy.cpp @@ -8,12 +8,12 @@ #include "src/search/hdestroy.h" #include "src/__support/HashTable/table.h" -#include "src/__support/libc_assert.h" #include "src/search/hsearch/global.h" namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(void, hdestroy, (void)) { - LIBC_ASSERT(internal::global_hash_table != nullptr); + // HashTable::deallocate will check for nullptr. It will be a no-op if + // global_hash_table is null. internal::HashTable::deallocate(internal::global_hash_table); internal::global_hash_table = nullptr; } diff --git a/libc/src/search/hsearch.cpp b/libc/src/search/hsearch.cpp index 3a0d09aae835..5aeb5c29449e 100644 --- a/libc/src/search/hsearch.cpp +++ b/libc/src/search/hsearch.cpp @@ -7,24 +7,37 @@ //===----------------------------------------------------------------------===// #include "src/search/hsearch.h" +#include "src/__support/HashTable/randomness.h" #include "src/__support/HashTable/table.h" -#include "src/__support/libc_assert.h" #include "src/errno/libc_errno.h" #include "src/search/hsearch/global.h" namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(ENTRY *, hsearch, (ENTRY item, ACTION action)) { ENTRY *result; - LIBC_ASSERT(internal::global_hash_table != nullptr); + if (internal::global_hash_table == nullptr) { + // If global_hash_table is null, we create a new hash table with a minimal + // capacity. Such hashtable will be expanded as needed. + uint64_t randomness = internal::randomness::next_random_seed(); + internal::global_hash_table = internal::HashTable::allocate(0, randomness); + } + + // In rare cases, the global hashtable may still fail to allocate. We treat it + // as ESRCH or ENOMEM depending on the action. switch (action) { case FIND: - result = internal::global_hash_table->find(item.key); + result = internal::global_hash_table + ? internal::global_hash_table->find(item.key) + : nullptr; if (result == nullptr) { libc_errno = ESRCH; } break; case ENTER: - result = internal::global_hash_table->insert(item); + result = + internal::global_hash_table + ? internal::HashTable::insert(internal::global_hash_table, item) + : nullptr; if (result == nullptr) { libc_errno = ENOMEM; } diff --git a/libc/src/search/hsearch_r.cpp b/libc/src/search/hsearch_r.cpp index 958fba7c00d0..a2c3a86eded6 100644 --- a/libc/src/search/hsearch_r.cpp +++ b/libc/src/search/hsearch_r.cpp @@ -29,7 +29,8 @@ LLVM_LIBC_FUNCTION(int, hsearch_r, } break; case ENTER: - *retval = table->insert(item); + *retval = internal::HashTable::insert(table, item); + htab->__opaque = table; if (*retval == nullptr) { libc_errno = ENOMEM; return 0; diff --git a/libc/src/stdio/printf_core/float_dec_converter.h b/libc/src/stdio/printf_core/float_dec_converter.h index 0e152a260256..ca5227100406 100644 --- a/libc/src/stdio/printf_core/float_dec_converter.h +++ b/libc/src/stdio/printf_core/float_dec_converter.h @@ -537,7 +537,7 @@ LIBC_INLINE int convert_float_decimal_typed(Writer *writer, } if (exponent < MANT_WIDTH) { - const uint32_t blocks = (precision / BLOCK_SIZE) + 1; + const uint32_t blocks = (precision / static_cast(BLOCK_SIZE)) + 1; uint32_t i = 0; // if all the blocks we should write are zero if (blocks <= float_converter.zero_blocks_after_point()) { @@ -561,7 +561,8 @@ LIBC_INLINE int convert_float_decimal_typed(Writer *writer, RET_IF_RESULT_NEGATIVE(float_writer.write_middle_block(digits)); } else { - const uint32_t maximum = precision - BLOCK_SIZE * i; + const uint32_t maximum = + static_cast(precision - BLOCK_SIZE * i); uint32_t last_digit = 0; for (uint32_t k = 0; k < BLOCK_SIZE - maximum; ++k) { last_digit = digits % 10; @@ -646,7 +647,8 @@ LIBC_INLINE int convert_float_dec_exp_typed(Writer *writer, const size_t block_width = IntegerToString(digits).size(); - final_exponent = (cur_block * BLOCK_SIZE) + static_cast(block_width - 1); + final_exponent = static_cast(cur_block * BLOCK_SIZE) + + static_cast(block_width - 1); int positive_exponent = final_exponent < 0 ? -final_exponent : final_exponent; size_t exponent_width = IntegerToString(positive_exponent).size(); @@ -819,7 +821,8 @@ LIBC_INLINE int convert_float_dec_auto_typed(Writer *writer, size_t trailing_zeroes = 0; size_t trailing_nines = 0; - base_10_exp = (cur_block * BLOCK_SIZE) + static_cast(block_width - 1); + base_10_exp = static_cast(cur_block * BLOCK_SIZE) + + static_cast(block_width - 1); // If the first block is not also the last block if (block_width <= exp_precision + 1) { @@ -858,13 +861,13 @@ LIBC_INLINE int convert_float_dec_auto_typed(Writer *writer, trailing_nines = 0; trailing_zeroes = 0; BlockInt copy_of_digits = digits; - int cur_last_digit = copy_of_digits % 10; + BlockInt cur_last_digit = copy_of_digits % 10; // We only care if it ends in nines or zeroes. while (copy_of_digits > 0 && (cur_last_digit == 9 || cur_last_digit == 0)) { // If the next digit is not the same as the previous one, then there are // no more contiguous trailing digits. - if ((copy_of_digits % 10) != cur_last_digit) { + if (copy_of_digits % 10 != cur_last_digit) { break; } if (cur_last_digit == 9) { diff --git a/libc/src/stdio/printf_core/float_hex_converter.h b/libc/src/stdio/printf_core/float_hex_converter.h index 6a980a74d4a6..1f105492e8e5 100644 --- a/libc/src/stdio/printf_core/float_hex_converter.h +++ b/libc/src/stdio/printf_core/float_hex_converter.h @@ -139,8 +139,8 @@ LIBC_INLINE int convert_float_hex_exp(Writer *writer, size_t first_non_zero = 1; for (; mant_cur > 0; --mant_cur, mantissa >>= 4) { char mant_mod_16 = static_cast(mantissa) & 15; - char new_digit = - (mant_mod_16 > 9) ? (mant_mod_16 - 10 + a) : (mant_mod_16 + '0'); + char new_digit = static_cast( + (mant_mod_16 > 9) ? (mant_mod_16 - 10 + a) : (mant_mod_16 + '0')); mant_buffer[mant_cur - 1] = new_digit; if (new_digit != '0' && first_non_zero < mant_cur) first_non_zero = mant_cur; @@ -169,7 +169,7 @@ LIBC_INLINE int convert_float_hex_exp(Writer *writer, size_t exp_cur = EXP_LEN; for (; exponent > 0; --exp_cur, exponent /= 10) { - exp_buffer[exp_cur - 1] = (exponent % 10) + '0'; + exp_buffer[exp_cur - 1] = static_cast((exponent % 10) + '0'); } if (exp_cur == EXP_LEN) { // if nothing else was written, write a 0. exp_buffer[EXP_LEN - 1] = '0'; diff --git a/libc/src/stdlib/getenv.cpp b/libc/src/stdlib/getenv.cpp index 08397e0d8057..7a8eb1943c0a 100644 --- a/libc/src/stdlib/getenv.cpp +++ b/libc/src/stdlib/getenv.cpp @@ -16,7 +16,7 @@ namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(char *, getenv, (const char *name)) { - char **env_ptr = reinterpret_cast(LIBC_NAMESPACE::app.envPtr); + char **env_ptr = reinterpret_cast(LIBC_NAMESPACE::app.env_ptr); if (name == nullptr || env_ptr == nullptr) return nullptr; diff --git a/libc/src/string/memory_utils/op_aarch64.h b/libc/src/string/memory_utils/op_aarch64.h index 10de5bcfce85..3aae328945dd 100644 --- a/libc/src/string/memory_utils/op_aarch64.h +++ b/libc/src/string/memory_utils/op_aarch64.h @@ -17,6 +17,7 @@ #if defined(LIBC_TARGET_ARCH_IS_AARCH64) +#include "src/__support/CPP/type_traits.h" // cpp::always_false #include "src/__support/common.h" #include "src/string/memory_utils/op_generic.h" @@ -105,7 +106,7 @@ template struct Bcmp { if (auto value = Bcmp::block(p1 + offset, p2 + offset)) return value; } else { - deferred_static_assert("SIZE not implemented"); + static_assert(cpp::always_false, "SIZE not implemented"); } return BcmpReturnType::ZERO(); } @@ -151,7 +152,7 @@ template struct Bcmp { uint32x2_t abnocpdq_reduced = vqmovn_u64(abnocpdq); return vmaxv_u32(abnocpdq_reduced); } else { - deferred_static_assert("SIZE not implemented"); + static_assert(cpp::always_false, "SIZE not implemented"); } return BcmpReturnType::ZERO(); } diff --git a/libc/src/string/memory_utils/op_builtin.h b/libc/src/string/memory_utils/op_builtin.h index cfa58e43d745..16c9f519c37e 100644 --- a/libc/src/string/memory_utils/op_builtin.h +++ b/libc/src/string/memory_utils/op_builtin.h @@ -15,6 +15,7 @@ #ifndef LLVM_LIBC_SRC_STRING_MEMORY_UTILS_OP_BUILTIN_H #define LLVM_LIBC_SRC_STRING_MEMORY_UTILS_OP_BUILTIN_H +#include "src/__support/CPP/type_traits.h" #include "src/string/memory_utils/utils.h" namespace LIBC_NAMESPACE::builtin { @@ -75,7 +76,8 @@ template struct Memset { #ifdef LLVM_LIBC_HAS_BUILTIN_MEMSET_INLINE __builtin_memset_inline(dst, value, Size); #else - deferred_static_assert("Missing __builtin_memset_inline"); + static_assert(cpp::always_false, + "Missing __builtin_memset_inline"); (void)dst; (void)value; #endif @@ -107,22 +109,23 @@ template struct Bcmp { using ME = Bcmp; static constexpr size_t SIZE = Size; LIBC_INLINE static BcmpReturnType block(CPtr, CPtr) { - deferred_static_assert("Missing __builtin_memcmp_inline"); + static_assert(cpp::always_false, + "Missing __builtin_memcmp_inline"); return BcmpReturnType::ZERO(); } LIBC_INLINE static BcmpReturnType tail(CPtr, CPtr, size_t) { - deferred_static_assert("Not implemented"); + static_assert(cpp::always_false, "Not implemented"); return BcmpReturnType::ZERO(); } LIBC_INLINE static BcmpReturnType head_tail(CPtr, CPtr, size_t) { - deferred_static_assert("Not implemented"); + static_assert(cpp::always_false, "Not implemented"); return BcmpReturnType::ZERO(); } LIBC_INLINE static BcmpReturnType loop_and_tail(CPtr, CPtr, size_t) { - deferred_static_assert("Not implemented"); + static_assert(cpp::always_false, "Not implemented"); return BcmpReturnType::ZERO(); } }; @@ -133,22 +136,23 @@ template struct Memcmp { using ME = Memcmp; static constexpr size_t SIZE = Size; LIBC_INLINE static MemcmpReturnType block(CPtr, CPtr) { - deferred_static_assert("Missing __builtin_memcmp_inline"); + static_assert(cpp::always_false, + "Missing __builtin_memcmp_inline"); return MemcmpReturnType::ZERO(); } LIBC_INLINE static MemcmpReturnType tail(CPtr, CPtr, size_t) { - deferred_static_assert("Not implemented"); + static_assert(cpp::always_false, "Not implemented"); return MemcmpReturnType::ZERO(); } LIBC_INLINE static MemcmpReturnType head_tail(CPtr, CPtr, size_t) { - deferred_static_assert("Not implemented"); + static_assert(cpp::always_false, "Not implemented"); return MemcmpReturnType::ZERO(); } LIBC_INLINE static MemcmpReturnType loop_and_tail(CPtr, CPtr, size_t) { - deferred_static_assert("Not implemented"); + static_assert(cpp::always_false, "Not implemented"); return MemcmpReturnType::ZERO(); } }; diff --git a/libc/src/string/memory_utils/utils.h b/libc/src/string/memory_utils/utils.h index 9c293185a2e9..5cd716e033d6 100644 --- a/libc/src/string/memory_utils/utils.h +++ b/libc/src/string/memory_utils/utils.h @@ -22,45 +22,12 @@ namespace LIBC_NAMESPACE { -// Allows compile time error reporting in `if constexpr` branches. -template -LIBC_INLINE void deferred_static_assert(const char *msg) { - static_assert(flag, "compilation error"); - (void)msg; -} - -// Return whether `value` is zero or a power of two. -LIBC_INLINE constexpr bool is_power2_or_zero(size_t value) { - return (value & (value - 1U)) == 0; -} - -// Return whether `value` is a power of two. -LIBC_INLINE constexpr bool is_power2(size_t value) { - return value && is_power2_or_zero(value); -} - -// Compile time version of log2 that handles 0. -LIBC_INLINE constexpr size_t log2s(size_t value) { - return (value == 0 || value == 1) ? 0 : 1 + log2s(value / 2); -} - -// Returns the first power of two preceding value or value if it is already a -// power of two (or 0 when value is 0). -LIBC_INLINE constexpr size_t le_power2(size_t value) { - return value == 0 ? value : 1ULL << log2s(value); -} - -// Returns the first power of two following value or value if it is already a -// power of two (or 0 when value is 0). -LIBC_INLINE constexpr size_t ge_power2(size_t value) { - return is_power2_or_zero(value) ? value : 1ULL << (log2s(value) + 1); -} - // Returns the number of bytes to substract from ptr to get to the previous // multiple of alignment. If ptr is already aligned returns 0. template LIBC_INLINE uintptr_t distance_to_align_down(const void *ptr) { - static_assert(is_power2(alignment), "alignment must be a power of 2"); + static_assert(cpp::has_single_bit(alignment), + "alignment must be a power of 2"); return reinterpret_cast(ptr) & (alignment - 1U); } @@ -68,7 +35,8 @@ LIBC_INLINE uintptr_t distance_to_align_down(const void *ptr) { // alignment. If ptr is already aligned returns 0. template LIBC_INLINE uintptr_t distance_to_align_up(const void *ptr) { - static_assert(is_power2(alignment), "alignment must be a power of 2"); + static_assert(cpp::has_single_bit(alignment), + "alignment must be a power of 2"); // The logic is not straightforward and involves unsigned modulo arithmetic // but the generated code is as fast as it can be. return -reinterpret_cast(ptr) & (alignment - 1U); @@ -265,7 +233,7 @@ LIBC_INLINE ValueType load_aligned(CPtr src) { else if constexpr (Endian::IS_BIG) return (value << shift) | next; else - deferred_static_assert("Invalid endianness"); + static_assert(cpp::always_false, "Invalid endianness"); } else { return value; } @@ -302,7 +270,7 @@ LIBC_INLINE void store_aligned(ValueType value, Ptr dst) { if constexpr (sizeof...(TS) > 0) store_aligned(value >> shift, dst); } else { - deferred_static_assert("Invalid endianness"); + static_assert(cpp::always_false, "Invalid endianness"); } } @@ -360,7 +328,8 @@ LIBC_INLINE void align_to_next_boundary(T1 *__restrict &p1, T2 *__restrict &p2, else if constexpr (AlignOn == Arg::P2) align_p1_to_next_boundary(p2, p1, count); // swapping p1 and p2. else - deferred_static_assert("AlignOn must be either Arg::P1 or Arg::P2"); + static_assert(cpp::always_false, + "AlignOn must be either Arg::P1 or Arg::P2"); } template struct AlignHelper { diff --git a/libc/src/sys/CMakeLists.txt b/libc/src/sys/CMakeLists.txt index bf869ddc6a23..12e2020f013a 100644 --- a/libc/src/sys/CMakeLists.txt +++ b/libc/src/sys/CMakeLists.txt @@ -7,3 +7,4 @@ add_subdirectory(sendfile) add_subdirectory(stat) add_subdirectory(utsname) add_subdirectory(wait) +add_subdirectory(prctl) diff --git a/libc/src/sys/mman/CMakeLists.txt b/libc/src/sys/mman/CMakeLists.txt index 2d17429a26b4..e336bfd5d6db 100644 --- a/libc/src/sys/mman/CMakeLists.txt +++ b/libc/src/sys/mman/CMakeLists.txt @@ -36,10 +36,3 @@ add_entrypoint_object( DEPENDS .${LIBC_TARGET_OS}.posix_madvise ) - -add_entrypoint_object( - mincore - ALIAS - DEPENDS - .${LIBC_TARGET_OS}.mincore -) diff --git a/libc/src/sys/mman/linux/CMakeLists.txt b/libc/src/sys/mman/linux/CMakeLists.txt index ce0cda7f2227..163e7dead888 100644 --- a/libc/src/sys/mman/linux/CMakeLists.txt +++ b/libc/src/sys/mman/linux/CMakeLists.txt @@ -61,16 +61,3 @@ add_entrypoint_object( libc.include.sys_syscall libc.src.__support.OSUtil.osutil ) - -add_entrypoint_object( - mincore - SRCS - mincore.cpp - HDRS - ../mincore.h - DEPENDS - libc.include.sys_mman - libc.include.sys_syscall - libc.src.__support.OSUtil.osutil - libc.src.errno.errno -) diff --git a/libc/src/sys/mman/linux/mincore.cpp b/libc/src/sys/mman/linux/mincore.cpp deleted file mode 100644 index 8220c69ef2cb..000000000000 --- a/libc/src/sys/mman/linux/mincore.cpp +++ /dev/null @@ -1,28 +0,0 @@ -//===---------- Linux implementation of the mincore function --------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "src/sys/mman/mincore.h" - -#include "src/__support/OSUtil/syscall.h" // For internal syscall function. - -#include "src/errno/libc_errno.h" -#include // For syscall numbers. - -namespace LIBC_NAMESPACE { - -LLVM_LIBC_FUNCTION(int, mincore, (void *addr, size_t len, unsigned char *vec)) { - long ret = syscall_impl(SYS_mincore, reinterpret_cast(addr), len, - reinterpret_cast(vec)); - if (ret < 0) { - libc_errno = static_cast(-ret); - return -1; - } - return 0; -} - -} // namespace LIBC_NAMESPACE diff --git a/libc/src/sys/prctl/CMakeLists.txt b/libc/src/sys/prctl/CMakeLists.txt new file mode 100644 index 000000000000..a78c3c5a40bc --- /dev/null +++ b/libc/src/sys/prctl/CMakeLists.txt @@ -0,0 +1,10 @@ +if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) + add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) +endif() + +add_entrypoint_object( + prctl + ALIAS + DEPENDS + .${LIBC_TARGET_OS}.prctl +) diff --git a/libc/src/sys/prctl/linux/CMakeLists.txt b/libc/src/sys/prctl/linux/CMakeLists.txt new file mode 100644 index 000000000000..05d336441f4d --- /dev/null +++ b/libc/src/sys/prctl/linux/CMakeLists.txt @@ -0,0 +1,12 @@ +add_entrypoint_object( + prctl + SRCS + prctl.cpp + HDRS + ../prctl.h + DEPENDS + libc.include.sys_prctl + libc.include.sys_syscall + libc.src.__support.OSUtil.osutil + libc.src.errno.errno +) diff --git a/libc/src/sys/prctl/linux/prctl.cpp b/libc/src/sys/prctl/linux/prctl.cpp new file mode 100644 index 000000000000..b68b7621555d --- /dev/null +++ b/libc/src/sys/prctl/linux/prctl.cpp @@ -0,0 +1,37 @@ +//===---------- Linux implementation of the prctl function ----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/sys/prctl/prctl.h" + +#include "src/__support/OSUtil/syscall.h" // For internal syscall function. + +#include "src/errno/libc_errno.h" +#include // For syscall numbers. + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(int, prctl, + (int option, unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5)) { + long ret = + LIBC_NAMESPACE::syscall_impl(SYS_prctl, option, arg2, arg3, arg4, arg5); + // The manpage states that "... return the nonnegative values described + // above. All other option values return 0 on success. On error, + // -1 is returned, and errno is set to indicate the error." + // According to the kernel implementation + // (https://github.com/torvalds/linux/blob/bee0e7762ad2c6025b9f5245c040fcc36ef2bde8/kernel/sys.c#L2442), + // return value from the syscall is set to 0 on default so we do not need to + // set the value on success manually. + if (ret < 0) { + libc_errno = static_cast(-ret); + return -1; + } + return static_cast(ret); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/sys/mman/mincore.h b/libc/src/sys/prctl/prctl.h similarity index 50% rename from libc/src/sys/mman/mincore.h rename to libc/src/sys/prctl/prctl.h index 403afaeb6af9..baa0676d4254 100644 --- a/libc/src/sys/mman/mincore.h +++ b/libc/src/sys/prctl/prctl.h @@ -1,4 +1,4 @@ -//===-- Implementation header for mincore function --------------*- C++ -*-===// +//===-- Implementation header for prctl ---------------------------*-C++-*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,15 +6,16 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIBC_SRC_SYS_MMAN_MINCORE_H -#define LLVM_LIBC_SRC_SYS_MMAN_MINCORE_H +#ifndef LLVM_LIBC_SRC_SYS_PRCTL_PRCTL_H +#define LLVM_LIBC_SRC_SYS_PRCTL_PRCTL_H -#include // For size_t +#include namespace LIBC_NAMESPACE { -int mincore(void *addr, size_t len, unsigned char *vec); +int prctl(int option, unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5); } // namespace LIBC_NAMESPACE -#endif // LLVM_LIBC_SRC_SYS_MMAN_MINCORE_H +#endif // LLVM_LIBC_SRC_SYS_PRCTL_PRCTL_H diff --git a/libc/startup/linux/aarch64/start.cpp b/libc/startup/linux/aarch64/start.cpp index 002af5313cc8..b5c426866b56 100644 --- a/libc/startup/linux/aarch64/start.cpp +++ b/libc/startup/linux/aarch64/start.cpp @@ -74,7 +74,7 @@ void init_tls(TLSDescriptor &tls_descriptor) { MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); // We cannot check the return value with MAP_FAILED as that is the return // of the mmap function and not the mmap syscall. - if (mmap_ret_val < 0 && static_cast(mmap_ret_val) > -app.pageSize) + if (mmap_ret_val < 0 && static_cast(mmap_ret_val) > -app.page_size) LIBC_NAMESPACE::syscall_impl(SYS_exit, 1); uintptr_t thread_ptr = uintptr_t(reinterpret_cast(mmap_ret_val)); uintptr_t tls_addr = thread_ptr + size_of_pointers + padding; @@ -144,7 +144,7 @@ __attribute__((noinline)) static void do_start() { // value. We step over it (the "+ 1" below) to get to the env values. uint64_t *env_ptr = app.args->argv + app.args->argc + 1; uint64_t *env_end_marker = env_ptr; - app.envPtr = env_ptr; + app.env_ptr = env_ptr; while (*env_end_marker) ++env_end_marker; @@ -153,19 +153,19 @@ __attribute__((noinline)) static void do_start() { // After the env array, is the aux-vector. The end of the aux-vector is // denoted by an AT_NULL entry. - Elf64_Phdr *programHdrTable = nullptr; - uintptr_t programHdrCount; + Elf64_Phdr *program_hdr_table = nullptr; + uintptr_t program_hdr_count; for (AuxEntry *aux_entry = reinterpret_cast(env_end_marker + 1); aux_entry->type != AT_NULL; ++aux_entry) { switch (aux_entry->type) { case AT_PHDR: - programHdrTable = reinterpret_cast(aux_entry->value); + program_hdr_table = reinterpret_cast(aux_entry->value); break; case AT_PHNUM: - programHdrCount = aux_entry->value; + program_hdr_count = aux_entry->value; break; case AT_PAGESZ: - app.pageSize = aux_entry->value; + app.page_size = aux_entry->value; break; default: break; // TODO: Read other useful entries from the aux vector. @@ -173,8 +173,8 @@ __attribute__((noinline)) static void do_start() { } app.tls.size = 0; - for (uintptr_t i = 0; i < programHdrCount; ++i) { - Elf64_Phdr *phdr = programHdrTable + i; + for (uintptr_t i = 0; i < program_hdr_count; ++i) { + Elf64_Phdr *phdr = program_hdr_table + i; if (phdr->p_type != PT_TLS) continue; // TODO: p_vaddr value has to be adjusted for static-pie executables. diff --git a/libc/startup/linux/riscv/start.cpp b/libc/startup/linux/riscv/start.cpp index ed976d294d94..bf04be5ad14a 100644 --- a/libc/startup/linux/riscv/start.cpp +++ b/libc/startup/linux/riscv/start.cpp @@ -61,7 +61,7 @@ void init_tls(TLSDescriptor &tls_descriptor) { MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); // We cannot check the return value with MAP_FAILED as that is the return // of the mmap function and not the mmap syscall. - if (mmap_ret_val < 0 && static_cast(mmap_ret_val) > -app.pageSize) + if (mmap_ret_val < 0 && static_cast(mmap_ret_val) > -app.page_size) LIBC_NAMESPACE::syscall_impl(SYS_exit, 1); uintptr_t thread_ptr = uintptr_t(reinterpret_cast(mmap_ret_val)); uintptr_t tls_addr = thread_ptr + size_of_pointers + padding; @@ -147,7 +147,7 @@ __attribute__((noinline)) static void do_start() { // value. We step over it (the "+ 1" below) to get to the env values. LIBC_NAMESPACE::ArgVEntryType *env_ptr = app.args->argv + app.args->argc + 1; LIBC_NAMESPACE::ArgVEntryType *env_end_marker = env_ptr; - app.envPtr = env_ptr; + app.env_ptr = env_ptr; while (*env_end_marker) ++env_end_marker; @@ -156,19 +156,19 @@ __attribute__((noinline)) static void do_start() { // After the env array, is the aux-vector. The end of the aux-vector is // denoted by an AT_NULL entry. - PgrHdrTableType *programHdrTable = nullptr; - uintptr_t programHdrCount; + PgrHdrTableType *program_hdr_table = nullptr; + uintptr_t program_hdr_count; for (AuxEntry *aux_entry = reinterpret_cast(env_end_marker + 1); aux_entry->type != AT_NULL; ++aux_entry) { switch (aux_entry->type) { case AT_PHDR: - programHdrTable = reinterpret_cast(aux_entry->value); + program_hdr_table = reinterpret_cast(aux_entry->value); break; case AT_PHNUM: - programHdrCount = aux_entry->value; + program_hdr_count = aux_entry->value; break; case AT_PAGESZ: - app.pageSize = aux_entry->value; + app.page_size = aux_entry->value; break; default: break; // TODO: Read other useful entries from the aux vector. @@ -176,8 +176,8 @@ __attribute__((noinline)) static void do_start() { } app.tls.size = 0; - for (uintptr_t i = 0; i < programHdrCount; ++i) { - PgrHdrTableType *phdr = programHdrTable + i; + for (uintptr_t i = 0; i < program_hdr_count; ++i) { + PgrHdrTableType *phdr = program_hdr_table + i; if (phdr->p_type != PT_TLS) continue; // TODO: p_vaddr value has to be adjusted for static-pie executables. diff --git a/libc/startup/linux/x86_64/start.cpp b/libc/startup/linux/x86_64/start.cpp index af95d2702ded..bc1b4f0487f3 100644 --- a/libc/startup/linux/x86_64/start.cpp +++ b/libc/startup/linux/x86_64/start.cpp @@ -33,9 +33,9 @@ extern "C" void __stack_chk_fail() { namespace LIBC_NAMESPACE { #ifdef SYS_mmap2 -static constexpr long mmapSyscallNumber = SYS_mmap2; +static constexpr long MMAP_SYSCALL_NUMBER = SYS_mmap2; #elif SYS_mmap -static constexpr long mmapSyscallNumber = SYS_mmap; +static constexpr long MMAP_SYSCALL_NUMBER = SYS_mmap; #else #error "mmap and mmap2 syscalls not available." #endif @@ -54,49 +54,50 @@ void init_tls(TLSDescriptor &tls_descriptor) { } // We will assume the alignment is always a power of two. - uintptr_t tlsSize = app.tls.size & -app.tls.align; - if (tlsSize != app.tls.size) - tlsSize += app.tls.align; + uintptr_t tls_size = app.tls.size & -app.tls.align; + if (tls_size != app.tls.size) + tls_size += app.tls.align; // Per the x86_64 TLS ABI, the entry pointed to by the thread pointer is the // address of the TLS block. So, we add more size to accomodate this address // entry. // We also need to include space for the stack canary. The canary is at // offset 0x28 (40) and is of size uintptr_t. - uintptr_t tlsSizeWithAddr = tlsSize + sizeof(uintptr_t) + 40; + uintptr_t tls_size_with_addr = tls_size + sizeof(uintptr_t) + 40; // We cannot call the mmap function here as the functions set errno on // failure. Since errno is implemented via a thread local variable, we cannot // use errno before TLS is setup. - long mmapRetVal = LIBC_NAMESPACE::syscall_impl( - mmapSyscallNumber, nullptr, tlsSizeWithAddr, PROT_READ | PROT_WRITE, + long mmap_retval = LIBC_NAMESPACE::syscall_impl( + MMAP_SYSCALL_NUMBER, nullptr, tls_size_with_addr, PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); // We cannot check the return value with MAP_FAILED as that is the return // of the mmap function and not the mmap syscall. - if (mmapRetVal < 0 && static_cast(mmapRetVal) > -app.pageSize) + if (mmap_retval < 0 && static_cast(mmap_retval) > -app.page_size) LIBC_NAMESPACE::syscall_impl(SYS_exit, 1); - uintptr_t *tlsAddr = reinterpret_cast(mmapRetVal); + uintptr_t *tls_addr = reinterpret_cast(mmap_retval); // x86_64 TLS faces down from the thread pointer with the first entry // pointing to the address of the first real TLS byte. - uintptr_t endPtr = reinterpret_cast(tlsAddr) + tlsSize; - *reinterpret_cast(endPtr) = endPtr; + uintptr_t end_ptr = reinterpret_cast(tls_addr) + tls_size; + *reinterpret_cast(end_ptr) = end_ptr; - LIBC_NAMESPACE::inline_memcpy(reinterpret_cast(tlsAddr), + LIBC_NAMESPACE::inline_memcpy(reinterpret_cast(tls_addr), reinterpret_cast(app.tls.address), app.tls.init_size); - uintptr_t *stackGuardAddr = reinterpret_cast(endPtr + 40); + uintptr_t *stack_guard_addr = reinterpret_cast(end_ptr + 40); // Setting the stack guard to a random value. // We cannot call the get_random function here as the function sets errno on // failure. Since errno is implemented via a thread local variable, we cannot // use errno before TLS is setup. - ssize_t stackGuardRetVal = LIBC_NAMESPACE::syscall_impl( - SYS_getrandom, reinterpret_cast(stackGuardAddr), sizeof(uint64_t), + ssize_t stack_guard_retval = LIBC_NAMESPACE::syscall_impl( + SYS_getrandom, reinterpret_cast(stack_guard_addr), sizeof(uint64_t), 0); - if (stackGuardRetVal < 0) + if (stack_guard_retval < 0) LIBC_NAMESPACE::syscall_impl(SYS_exit, 1); - tls_descriptor = {tlsSizeWithAddr, uintptr_t(tlsAddr), endPtr}; + tls_descriptor = {tls_size_with_addr, reinterpret_cast(tls_addr), + end_ptr}; return; } @@ -181,7 +182,7 @@ extern "C" void _start() { // value. We step over it (the "+ 1" below) to get to the env values. uint64_t *env_ptr = app.args->argv + app.args->argc + 1; uint64_t *env_end_marker = env_ptr; - app.envPtr = env_ptr; + app.env_ptr = env_ptr; while (*env_end_marker) ++env_end_marker; @@ -190,19 +191,19 @@ extern "C" void _start() { // After the env array, is the aux-vector. The end of the aux-vector is // denoted by an AT_NULL entry. - Elf64_Phdr *programHdrTable = nullptr; - uintptr_t programHdrCount; + Elf64_Phdr *program_hdr_table = nullptr; + uintptr_t program_hdr_count = 0; for (AuxEntry *aux_entry = reinterpret_cast(env_end_marker + 1); aux_entry->type != AT_NULL; ++aux_entry) { switch (aux_entry->type) { case AT_PHDR: - programHdrTable = reinterpret_cast(aux_entry->value); + program_hdr_table = reinterpret_cast(aux_entry->value); break; case AT_PHNUM: - programHdrCount = aux_entry->value; + program_hdr_count = aux_entry->value; break; case AT_PAGESZ: - app.pageSize = aux_entry->value; + app.page_size = aux_entry->value; break; default: break; // TODO: Read other useful entries from the aux vector. @@ -210,8 +211,8 @@ extern "C" void _start() { } app.tls.size = 0; - for (uintptr_t i = 0; i < programHdrCount; ++i) { - Elf64_Phdr *phdr = programHdrTable + i; + for (uintptr_t i = 0; i < program_hdr_count; ++i) { + Elf64_Phdr *phdr = program_hdr_table + i; if (phdr->p_type != PT_TLS) continue; // TODO: p_vaddr value has to be adjusted for static-pie executables. diff --git a/libc/test/src/__support/CMakeLists.txt b/libc/test/src/__support/CMakeLists.txt index 2b9fa93bb548..740209bc83d7 100644 --- a/libc/test/src/__support/CMakeLists.txt +++ b/libc/test/src/__support/CMakeLists.txt @@ -23,18 +23,6 @@ add_libc_test( libc.src.__support.common ) - -add_libc_test( - bit_test - SUITE - libc-support-tests - SRCS - bit_test.cpp - DEPENDS - libc.src.__support.bit -) - - add_libc_test( math_extras_test SUITE @@ -45,7 +33,6 @@ add_libc_test( libc.src.__support.math_extras ) - add_libc_test( high_precision_decimal_test SUITE diff --git a/libc/test/src/__support/HashTable/CMakeLists.txt b/libc/test/src/__support/HashTable/CMakeLists.txt index ee8dde107c3f..f84835fe95c7 100644 --- a/libc/test/src/__support/HashTable/CMakeLists.txt +++ b/libc/test/src/__support/HashTable/CMakeLists.txt @@ -6,6 +6,7 @@ add_libc_test( bitmask_test.cpp DEPENDS libc.src.__support.HashTable.bitmask + libc.src.search.hsearch ) add_libc_test( @@ -18,6 +19,7 @@ add_libc_test( libc.src.__support.HashTable.randomness libc.src.__support.HashTable.table libc.src.__support.common + libc.src.search.hsearch UNIT_TEST_ONLY ) @@ -30,4 +32,5 @@ add_libc_test( DEPENDS libc.src.__support.HashTable.bitmask libc.src.stdlib.rand + libc.src.search.hsearch ) diff --git a/libc/test/src/__support/HashTable/bitmask_test.cpp b/libc/test/src/__support/HashTable/bitmask_test.cpp index c816c5d10638..5203220e9b5c 100644 --- a/libc/test/src/__support/HashTable/bitmask_test.cpp +++ b/libc/test/src/__support/HashTable/bitmask_test.cpp @@ -11,8 +11,8 @@ namespace LIBC_NAMESPACE { namespace internal { -using ShortBitMask = BitMaskAdaptor; -using LargeBitMask = BitMaskAdaptor; +using ShortBitMask = BitMaskAdaptor; +using LargeBitMask = BitMaskAdaptor; TEST(LlvmLibcHashTableBitMaskTest, SingleBitStrideLowestSetBit) { uint16_t data = 0xffff; @@ -53,7 +53,7 @@ TEST(LlvmLibcHashTableBitMaskTest, SingleBitStrideIteration) { TEST(LlvmLibcHashTableBitMaskTest, MultiBitStrideIteration) { using Iter = IteratableBitMaskAdaptor; - uint64_t data = Iter::MASK; + uint64_t data = 0x8080808080808080ul; for (size_t i = 0; i < 8; ++i) { Iter iter = {data}; size_t j = i; diff --git a/libc/test/src/__support/HashTable/table_test.cpp b/libc/test/src/__support/HashTable/table_test.cpp index f0aa82f2d5c7..dcae6f4e8fca 100644 --- a/libc/test/src/__support/HashTable/table_test.cpp +++ b/libc/test/src/__support/HashTable/table_test.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "src/__support/CPP/bit.h" // bit_ceil #include "src/__support/HashTable/randomness.h" #include "src/__support/HashTable/table.h" #include "test/UnitTest/Test.h" @@ -29,15 +30,65 @@ TEST(LlvmLibcTableTest, AllocationAndDeallocation) { HashTable::deallocate(nullptr); } +TEST(LlvmLibcTableTest, Iteration) { + constexpr size_t TEST_SIZE = 512; + size_t counter[TEST_SIZE]; + struct key { + uint8_t bytes[3]; + } keys[TEST_SIZE]; + HashTable *table = HashTable::allocate(0, 0x7f7f7f7f7f7f7f7f); + ASSERT_NE(table, static_cast(nullptr)); + for (size_t i = 0; i < TEST_SIZE; ++i) { + counter[i] = 0; + if (i >= 256) { + keys[i].bytes[0] = 2; + keys[i].bytes[1] = i % 256; + keys[i].bytes[2] = 0; + } else { + keys[i].bytes[0] = 1; + keys[i].bytes[1] = i; + keys[i].bytes[2] = 0; + } + HashTable::insert(table, {reinterpret_cast(keys[i].bytes), + reinterpret_cast((size_t)i)}); + } + + size_t count = 0; + for (const ENTRY &e : *table) { + size_t data = reinterpret_cast(e.data); + ++counter[data]; + ++count; + } + ASSERT_EQ(count, TEST_SIZE); + for (size_t i = 0; i < TEST_SIZE; ++i) { + ASSERT_EQ(counter[i], static_cast(1)); + } + HashTable::deallocate(table); +} + +// Check if resize works correctly. This test actually covers two things: +// - The sizes are indeed growing. +// - The sizes are growing rapidly enough to reach the upper bound. +TEST(LlvmLibcTableTest, GrowthSequence) { + size_t cap = capacity_to_entries(0); + // right shift 4 to avoid overflow ssize_t. + while (cap < static_cast(-1) >> 4u) { + size_t hint = cap / 8 * 7 + 1; + size_t new_cap = capacity_to_entries(hint); + ASSERT_GT(new_cap, cap); + cap = new_cap; + } +} + TEST(LlvmLibcTableTest, Insertion) { union key { - uint64_t value; - char bytes[8]; + char bytes[2]; } keys[256]; for (size_t k = 0; k < 256; ++k) { - keys[k].value = LIBC_NAMESPACE::Endian::to_little_endian(k); + keys[k].bytes[0] = static_cast(k); + keys[k].bytes[1] = 0; } - constexpr size_t CAP = next_power_of_two((sizeof(Group) + 1) * 8 / 7) / 8 * 7; + constexpr size_t CAP = cpp::bit_ceil((sizeof(Group) + 1) * 8 / 7) / 8 * 7; static_assert(CAP + 1 < 256, "CAP is too large for this test."); HashTable *table = HashTable::allocate(sizeof(Group) + 1, randomness::next_random_seed()); @@ -45,27 +96,30 @@ TEST(LlvmLibcTableTest, Insertion) { // insert to full capacity. for (size_t i = 0; i < CAP; ++i) { - ASSERT_NE(table->insert({keys[i].bytes, keys[i].bytes}), + ASSERT_NE(HashTable::insert(table, {keys[i].bytes, keys[i].bytes}), static_cast(nullptr)); } - // one more insert should fail. - ASSERT_EQ(table->insert({keys[CAP + 1].bytes, keys[CAP + 1].bytes}), - static_cast(nullptr)); + // One more insert should grow the table successfully. We test the value + // here because the grow finishes with a fastpath insertion that is different + // from the normal insertion. + ASSERT_EQ(HashTable::insert(table, {keys[CAP].bytes, keys[CAP].bytes})->data, + static_cast(keys[CAP].bytes)); - for (size_t i = 0; i < CAP; ++i) { + for (size_t i = 0; i <= CAP; ++i) { ASSERT_EQ(strcmp(table->find(keys[i].bytes)->key, keys[i].bytes), 0); } - for (size_t i = CAP; i < 256; ++i) { + for (size_t i = CAP + 1; i < 256; ++i) { ASSERT_EQ(table->find(keys[i].bytes), static_cast(nullptr)); } // do not replace old value - for (size_t i = 0; i < CAP; ++i) { - ASSERT_NE(table->insert({keys[i].bytes, reinterpret_cast(i)}), - static_cast(nullptr)); + for (size_t i = 0; i <= CAP; ++i) { + ASSERT_NE( + HashTable::insert(table, {keys[i].bytes, reinterpret_cast(i)}), + static_cast(nullptr)); } - for (size_t i = 0; i < CAP; ++i) { + for (size_t i = 0; i <= CAP; ++i) { ASSERT_EQ(table->find(keys[i].bytes)->data, reinterpret_cast(keys[i].bytes)); } diff --git a/libc/test/src/__support/bit_test.cpp b/libc/test/src/__support/bit_test.cpp deleted file mode 100644 index e585735394e2..000000000000 --- a/libc/test/src/__support/bit_test.cpp +++ /dev/null @@ -1,67 +0,0 @@ -//===-- Unittests for BlockStore ------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "src/__support/bit.h" -#include "test/UnitTest/Test.h" - -namespace LIBC_NAMESPACE { - -TEST(LlvmLibcBlockBitTest, TODO) { - // TODO Implement me. -} - -TEST(LlvmLibcBlockBitTest, OffsetTo) { - ASSERT_EQ(offset_to(0, 512), 0); - ASSERT_EQ(offset_to(1, 512), 511); - ASSERT_EQ(offset_to(2, 512), 510); - ASSERT_EQ(offset_to(13, 1), 0); - ASSERT_EQ(offset_to(13, 4), 3); - for (unsigned int i = 0; i < 31; ++i) { - ASSERT_EQ((offset_to(i, 1u << i) + i) % (1u << i), 0u); - } -} - -TEST(LlvmLibcBlockBitTest, RotateLeft) { - { - unsigned current = 1; - for (unsigned i = 0; i < 8 * sizeof(unsigned); ++i) { - ASSERT_EQ(1u << i, current); - ASSERT_EQ(current, rotate_left(1u, i)); - current = rotate_left(current, 1u); - } - ASSERT_EQ(current, 1u); - } - { - int current = 1; - for (int i = 0; i < 8 * static_cast(sizeof(int)); ++i) { - ASSERT_EQ(1 << i, current); - ASSERT_EQ(current, rotate_left(1, i)); - current = rotate_left(current, 1); - } - ASSERT_EQ(current, 1); - } -} - -TEST(LlvmLibcBlockBitTest, NextPowerOfTwo) { - ASSERT_EQ(1u, next_power_of_two(0u)); - for (unsigned int i = 0; i < 31; ++i) { - ASSERT_EQ(1u << (i + 1), next_power_of_two((1u << i) + 1)); - ASSERT_EQ(1u << i, next_power_of_two(1u << i)); - } -} - -TEST(LlvmLibcBlockBitTest, IsPowerOfTwo) { - ASSERT_FALSE(is_power_of_two(0u)); - ASSERT_TRUE(is_power_of_two(1u)); - for (unsigned int i = 1; i < 31; ++i) { - ASSERT_TRUE(is_power_of_two(1u << i)); - ASSERT_FALSE(is_power_of_two((1u << i) + 1)); - } -} - -} // namespace LIBC_NAMESPACE diff --git a/libc/test/src/__support/memory_size_test.cpp b/libc/test/src/__support/memory_size_test.cpp index 98b6a613e62f..93ef3711d40e 100644 --- a/libc/test/src/__support/memory_size_test.cpp +++ b/libc/test/src/__support/memory_size_test.cpp @@ -75,11 +75,22 @@ TEST(LlvmLibcMemSizeTest, AlignUp) { auto safe_size = SafeMemSize{size}; auto safe_aligned_size = safe_size.align_up(alignment); ASSERT_TRUE(safe_aligned_size.valid()); - ASSERT_EQ(static_cast(safe_aligned_size) % alignment, size_t{0}); + ASSERT_EQ(static_cast(safe_aligned_size) % alignment, size_t(0)); } } auto max = SafeMemSize{SAFE_MEM_SIZE_TEST_LIMIT}; ASSERT_FALSE(max.align_up(8).valid()); } + +TEST(LlvmLibcBlockBitTest, OffsetTo) { + ASSERT_EQ(SafeMemSize::offset_to(0, 512), size_t(0)); + ASSERT_EQ(SafeMemSize::offset_to(1, 512), size_t(511)); + ASSERT_EQ(SafeMemSize::offset_to(2, 512), size_t(510)); + ASSERT_EQ(SafeMemSize::offset_to(13, 1), size_t(0)); + ASSERT_EQ(SafeMemSize::offset_to(13, 4), size_t(3)); + for (unsigned int i = 0; i < 31; ++i) { + ASSERT_EQ((SafeMemSize::offset_to(i, 1u << i) + i) % (1u << i), size_t(0)); + } +} } // namespace internal } // namespace LIBC_NAMESPACE diff --git a/libc/test/src/search/hsearch_test.cpp b/libc/test/src/search/hsearch_test.cpp index bc9dea748758..f7d94791f2bc 100644 --- a/libc/test/src/search/hsearch_test.cpp +++ b/libc/test/src/search/hsearch_test.cpp @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// +#include "src/__support/CPP/bit.h" // bit_ceil #include "src/__support/HashTable/table.h" -#include "src/__support/bit.h" #include "src/search/hcreate.h" #include "src/search/hcreate_r.h" #include "src/search/hdestroy.h" @@ -48,20 +48,24 @@ char search_data2[] = constexpr size_t GROUP_SIZE = sizeof(LIBC_NAMESPACE::internal::Group); constexpr size_t CAP = - LIBC_NAMESPACE::next_power_of_two((GROUP_SIZE + 1) * 8 / 7) / 8 * 7; + LIBC_NAMESPACE::cpp::bit_ceil((GROUP_SIZE + 1) * 8 / 7) / 8 * 7; static_assert(CAP < sizeof(search_data), "CAP too large"); -TEST(LlvmLibcHSearchTest, InsertTooMany) { +TEST(LlvmLibcHSearchTest, GrowFromZero) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; - ASSERT_GT(LIBC_NAMESPACE::hcreate(GROUP_SIZE + 1), 0); - - for (size_t i = 0; i < CAP; ++i) { - ASSERT_EQ(LIBC_NAMESPACE::hsearch({&search_data[i], nullptr}, ENTER)->key, - &search_data[i]); + ASSERT_GT(LIBC_NAMESPACE::hcreate(0), 0); + for (size_t i = 0; i < sizeof(search_data) - 1; ++i) { + ENTRY *inserted = LIBC_NAMESPACE::hsearch( + {&search_data[i], reinterpret_cast(i)}, ENTER); + ASSERT_NE(inserted, static_cast(nullptr)); + ASSERT_EQ(inserted->key, &search_data[i]); } - ASSERT_THAT(static_cast( - LIBC_NAMESPACE::hsearch({search_data2, nullptr}, ENTER)), - Fails(ENOMEM, static_cast(nullptr))); + for (size_t i = sizeof(search_data) - 1; i != 0; --i) { + ASSERT_EQ( + LIBC_NAMESPACE::hsearch({&search_data[i - 1], nullptr}, FIND)->data, + reinterpret_cast(i - 1)); + } + LIBC_NAMESPACE::hdestroy(); } @@ -85,10 +89,10 @@ TEST(LlvmLibcHSearchTest, Found) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; ASSERT_GT(LIBC_NAMESPACE::hcreate(GROUP_SIZE + 1), 0); for (size_t i = 0; i < CAP; ++i) { - ASSERT_EQ(LIBC_NAMESPACE::hsearch( - {&search_data[i], reinterpret_cast(i)}, ENTER) - ->key, - &search_data[i]); + ENTRY *inserted = LIBC_NAMESPACE::hsearch( + {&search_data[i], reinterpret_cast(i)}, ENTER); + ASSERT_NE(inserted, static_cast(nullptr)); + ASSERT_EQ(inserted->key, &search_data[i]); } for (size_t i = 0; i < CAP; ++i) { ASSERT_EQ(LIBC_NAMESPACE::hsearch({&search_data[i], nullptr}, FIND)->data, diff --git a/libc/test/src/string/memory_utils/utils_test.cpp b/libc/test/src/string/memory_utils/utils_test.cpp index 8e9052de56f1..5ed35b08cdff 100644 --- a/libc/test/src/string/memory_utils/utils_test.cpp +++ b/libc/test/src/string/memory_utils/utils_test.cpp @@ -12,66 +12,6 @@ namespace LIBC_NAMESPACE { -TEST(LlvmLibcUtilsTest, IsPowerOfTwoOrZero) { - static const cpp::array kExpectedValues{ - 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, // 0-15 - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 16-31 - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 32-47 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 48-63 - 1 // 64 - }; - for (size_t i = 0; i < kExpectedValues.size(); ++i) - EXPECT_EQ(is_power2_or_zero(i), kExpectedValues[i]); -} - -TEST(LlvmLibcUtilsTest, IsPowerOfTwo) { - static const cpp::array kExpectedValues{ - 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, // 0-15 - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 16-31 - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 32-47 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 48-63 - 1 // 64 - }; - for (size_t i = 0; i < kExpectedValues.size(); ++i) - EXPECT_EQ(is_power2(i), kExpectedValues[i]); -} - -TEST(LlvmLibcUtilsTest, Log2) { - static const cpp::array kExpectedValues{ - 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, // 0-15 - 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, // 16-31 - 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, // 32-47 - 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, // 48-63 - 6 // 64 - }; - for (size_t i = 0; i < kExpectedValues.size(); ++i) - EXPECT_EQ(log2s(i), kExpectedValues[i]); -} - -TEST(LlvmLibcUtilsTest, LEPowerOf2) { - static const cpp::array kExpectedValues{ - 0, 1, 2, 2, 4, 4, 4, 4, 8, 8, 8, 8, 8, 8, 8, 8, // 0-15 - 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, // 16-31 - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, // 32-47 - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, // 48-63 - 64 // 64 - }; - for (size_t i = 0; i < kExpectedValues.size(); ++i) - EXPECT_EQ(le_power2(i), kExpectedValues[i]); -} - -TEST(LlvmLibcUtilsTest, GEPowerOf2) { - static const cpp::array kExpectedValues{ - 0, 1, 2, 4, 4, 8, 8, 8, 8, 16, 16, 16, 16, 16, 16, 16, // 0-15 - 16, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, // 16-31 - 32, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, // 32-47 - 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, // 48-63 - 64, 128 // 64-65 - }; - for (size_t i = 0; i < kExpectedValues.size(); ++i) - EXPECT_EQ(ge_power2(i), kExpectedValues[i]); -} - using UINT = uintptr_t; // Converts an offset into a pointer. diff --git a/libc/test/src/sys/CMakeLists.txt b/libc/test/src/sys/CMakeLists.txt index 5ef97fe81770..a87e77da7d2c 100644 --- a/libc/test/src/sys/CMakeLists.txt +++ b/libc/test/src/sys/CMakeLists.txt @@ -7,3 +7,4 @@ add_subdirectory(socket) add_subdirectory(stat) add_subdirectory(utsname) add_subdirectory(wait) +add_subdirectory(prctl) diff --git a/libc/test/src/sys/mman/linux/CMakeLists.txt b/libc/test/src/sys/mman/linux/CMakeLists.txt index c60377eb2cc1..66743be175fe 100644 --- a/libc/test/src/sys/mman/linux/CMakeLists.txt +++ b/libc/test/src/sys/mman/linux/CMakeLists.txt @@ -62,20 +62,3 @@ add_libc_unittest( libc.src.sys.mman.posix_madvise libc.test.UnitTest.ErrnoSetterMatcher ) - -add_libc_unittest( - mincore_test - SUITE - libc_sys_mman_unittests - SRCS - mincore_test.cpp - DEPENDS - libc.include.sys_mman - libc.src.errno.errno - libc.src.sys.mman.mmap - libc.src.sys.mman.munmap - libc.src.sys.mman.madvise - libc.src.sys.mman.mincore - libc.src.unistd.sysconf - libc.test.UnitTest.ErrnoSetterMatcher -) diff --git a/libc/test/src/sys/mman/linux/mincore_test.cpp b/libc/test/src/sys/mman/linux/mincore_test.cpp deleted file mode 100644 index 1b0ed157483e..000000000000 --- a/libc/test/src/sys/mman/linux/mincore_test.cpp +++ /dev/null @@ -1,123 +0,0 @@ -//===-- Unittests for mincore ---------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "src/errno/libc_errno.h" -#include "src/sys/mman/madvise.h" -#include "src/sys/mman/mincore.h" -#include "src/sys/mman/mmap.h" -#include "src/sys/mman/munmap.h" -#include "src/unistd/sysconf.h" -#include "test/UnitTest/ErrnoSetterMatcher.h" -#include "test/UnitTest/LibcTest.h" -#include "test/UnitTest/Test.h" - -#include -#include // For sysconf. - -using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; -using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; - -TEST(LlvmLibcMincoreTest, UnMappedMemory) { - libc_errno = 0; - unsigned char vec; - int res = LIBC_NAMESPACE::mincore(nullptr, 1, &vec); - EXPECT_THAT(res, Fails(ENOMEM, -1)); -} - -// It is always possible to find an aligned boundary if we allocate page sized -// memory. -static char *aligned_addr(void *addr, size_t alignment) { - char *byte_addr = static_cast(addr); - uintptr_t addr_val = reinterpret_cast(addr); - uintptr_t offset = - addr_val % alignment == 0 ? 0 : alignment - (addr_val % alignment); - return byte_addr + offset; -} - -TEST(LlvmLibcMincoreTest, InvalidVec) { - size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); - void *addr = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ, - MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); - EXPECT_NE(addr, MAP_FAILED); - char *aligned = aligned_addr(addr, page_size); - int res = LIBC_NAMESPACE::mincore(aligned, 1, nullptr); - EXPECT_THAT(res, Fails(EFAULT, -1)); - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); -} - -TEST(LlvmLibcMincoreTest, UnalignedAddr) { - size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); - void *addr = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ, - MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); - EXPECT_NE(addr, MAP_FAILED); - char *aligned = aligned_addr(addr, page_size); - libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(aligned + 1, 1, nullptr); - EXPECT_THAT(res, Fails(EINVAL, -1)); - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); -} - -TEST(LlvmLibcMincoreTest, NoError) { - size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); - void *addr = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ, - MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); - EXPECT_NE(addr, MAP_FAILED); - char *aligned = aligned_addr(addr, page_size); - unsigned char vec; - libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(aligned, 1, &vec); - EXPECT_THAT(res, Succeeds()); - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); -} - -TEST(LlvmLibcMincoreTest, NegativeLength) { - size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); - void *addr = LIBC_NAMESPACE::mmap(nullptr, page_size, PROT_READ, - MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); - EXPECT_NE(addr, MAP_FAILED); - char *aligned = aligned_addr(addr, page_size); - unsigned char vec; - libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(aligned, -1, &vec); - EXPECT_THAT(res, Fails(ENOMEM, -1)); - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); -} - -TEST(LlvmLibcMincoreTest, PageOut) { - unsigned char vec; - size_t page_size = static_cast(LIBC_NAMESPACE::sysconf(_SC_PAGESIZE)); - // allocate 2 pages since we need to page out page_size bytes - void *addr = - LIBC_NAMESPACE::mmap(nullptr, 2 * page_size, PROT_READ | PROT_WRITE, - MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); - EXPECT_NE(addr, MAP_FAILED); - char *aligned = aligned_addr(addr, page_size); - - // touch the page - { - aligned[0] = 0; - libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(aligned, 1, &vec); - EXPECT_EQ(vec & 1u, 1u); - EXPECT_THAT(res, Succeeds()); - } - - // page out the memory - { - libc_errno = 0; - EXPECT_THAT(LIBC_NAMESPACE::madvise(aligned, page_size, MADV_DONTNEED), - Succeeds()); - - libc_errno = 0; - int res = LIBC_NAMESPACE::mincore(aligned, 1, &vec); - EXPECT_EQ(vec & 1u, 0u); - EXPECT_THAT(res, Succeeds()); - } - - EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, 2 * page_size), Succeeds()); -} diff --git a/libc/test/src/sys/prctl/CMakeLists.txt b/libc/test/src/sys/prctl/CMakeLists.txt new file mode 100644 index 000000000000..b4bbe81c92ff --- /dev/null +++ b/libc/test/src/sys/prctl/CMakeLists.txt @@ -0,0 +1,3 @@ +if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) + add_subdirectory(${LIBC_TARGET_OS}) +endif() diff --git a/libc/test/src/sys/prctl/linux/CMakeLists.txt b/libc/test/src/sys/prctl/linux/CMakeLists.txt new file mode 100644 index 000000000000..25e9b8fd8a00 --- /dev/null +++ b/libc/test/src/sys/prctl/linux/CMakeLists.txt @@ -0,0 +1,14 @@ +add_custom_target(libc_sys_prctl_unittests) + +add_libc_unittest( + prctl_test + SUITE + libc_sys_prctl_unittests + SRCS + prctl_test.cpp + DEPENDS + libc.include.sys_prctl + libc.include.errno + libc.src.sys.prctl.prctl + libc.src.errno.errno +) diff --git a/libc/test/src/sys/prctl/linux/prctl_test.cpp b/libc/test/src/sys/prctl/linux/prctl_test.cpp new file mode 100644 index 000000000000..643c9513b36e --- /dev/null +++ b/libc/test/src/sys/prctl/linux/prctl_test.cpp @@ -0,0 +1,44 @@ +//===-- Unittests for prctl -----------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/errno/libc_errno.h" +#include "src/sys/prctl/prctl.h" +#include "test/UnitTest/ErrnoSetterMatcher.h" +#include +#include + +using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; +using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; + +TEST(LlvmLibcSysPrctlTest, GetSetName) { + char name[17]; + unsigned long name_addr = 0; + ASSERT_THAT(LIBC_NAMESPACE::prctl(PR_GET_NAME, name_addr, 0, 0, 0), + Fails(EFAULT, -1)); + + name_addr = reinterpret_cast("libc-test"); + ASSERT_THAT(LIBC_NAMESPACE::prctl(PR_SET_NAME, name_addr, 0, 0, 0), + Succeeds()); + + name_addr = reinterpret_cast(name); + ASSERT_THAT(LIBC_NAMESPACE::prctl(PR_GET_NAME, name_addr, 0, 0, 0), + Succeeds()); + ASSERT_STREQ(name, "libc-test"); +} + +TEST(LlvmLibcSysPrctlTest, GetTHPDisable) { + // Manually check errno since the return value logic here is not + // covered in ErrnoSetterMatcher. + libc_errno = 0; + int ret = LIBC_NAMESPACE::prctl(PR_GET_THP_DISABLE, 0, 0, 0, 0); + ASSERT_EQ(libc_errno, 0); + // PR_GET_THP_DISABLE return (as the function result) the current + // setting of the "THP disable" flag for the calling thread, which + // is either 1, if the flag is set; or 0, if it is not. + ASSERT_TRUE(ret == 0 || ret == 1); +} diff --git a/libcxx/docs/Contributing.rst b/libcxx/docs/Contributing.rst index 4cd0568989f8..3ff8c15a969b 100644 --- a/libcxx/docs/Contributing.rst +++ b/libcxx/docs/Contributing.rst @@ -67,7 +67,6 @@ avoid invoking a user-defined ``operator,``, make sure to cast the result to In general, try to follow the style of existing code. There are a few exceptions: -- ``_VSTD::foo`` is no longer used in new code. Use ``std::foo`` instead. - Prefer ``using foo = int`` over ``typedef int foo``. The compilers supported by libc++ accept alias declarations in all standard modes. diff --git a/libcxx/docs/Hardening.rst b/libcxx/docs/Hardening.rst index 7692f2a2c788..33a168d6e168 100644 --- a/libcxx/docs/Hardening.rst +++ b/libcxx/docs/Hardening.rst @@ -15,61 +15,72 @@ assertions that prevent undefined behavior caused by violating preconditions of the standard library. Different hardening modes make different trade-offs between the amount of checking and runtime performance. The available hardening modes are: -- fast mode; -- extensive mode; -- debug mode. - -The fast mode contains a set of security-critical checks that can be done with -relatively little overhead in constant time and are intended to be used in -production. We recommend most projects to adopt the fast mode. - -The extensive mode contains all the checks from the fast mode and additionally -some checks for undefined behavior that incur relatively little overhead but -aren't security-critical. While the performance penalty is somewhat more -significant compared to the fast mode, the extensive mode is still intended to -be usable in production. - -The debug mode enables all the available checks in the library, including -internal assertions, some of which might be very expensive. This mode is -intended to be used for testing, not in production. - -Vendors can set the default hardening mode by using the -``LIBCXX_HARDENING_MODE`` variable at CMake configuration time with the possible -values of ``none``, ``fast``, ``extensive`` and ``debug``. The default value is -``none`` which doesn't enable any hardening checks (this mode is sometimes -called the ``unchecked`` mode). - -When hardening is enabled, the compiled library is built with the corresponding -mode enabled, **and** user code will be built with the same mode enabled by -default. If the mode is set to "none" at the CMake configuration time, the -compiled library will not contain any assertions and the default when building -user code will be to have assertions disabled. As a user, you can consult your -vendor to know which level of hardening is enabled by default. - -Furthermore, independently of any vendor-selected default, users can always -control which level of hardening is enabled in their code by defining the macro -``_LIBCPP_HARDENING_MODE`` before including any libc++ headers (preferably by -passing ``-D_LIBCPP_HARDENING_MODE=X`` to the compiler). The macro can be -set to one of the following possible values: - -- ``_LIBCPP_HARDENING_MODE_NONE``; -- ``_LIBCPP_HARDENING_MODE_FAST``; -- ``_LIBCPP_HARDENING_MODE_EXTENSIVE``; -- ``_LIBCPP_HARDENING_MODE_DEBUG``. - -The exact numeric values of these macros are unspecified and users should not -rely on them (e.g. expect the values to be sorted in any way). - -Note that if the compiled library was built by the vendor with the hardening -mode set to "none", functions compiled inside the static or shared library won't -have any hardening enabled even if the user compiles with hardening enabled (the -same is true for the inverse case where the static or shared library was -compiled **with** hardening enabled but the user tries to disable it). However, -most of the code in libc++ is in the headers, so the user-selected value for -``_LIBCPP_HARDENING_MODE``, if any, will usually be respected. - -Enabling hardening has no impact on the ABI. + +- **Unchecked mode/none**, which disables all hardening checks. +- **Fast mode**, which contains a set of security-critical checks that can be + done with relatively little overhead in constant time and are intended to be + used in production. We recommend most projects adopt this. +- **Extensive mode**, which contains all the checks from fast mode and some + additional checks for undefined behavior that incur relatively little overhead + but aren't security-critical. Production builds requiring a broader set of + checks than fast mode should consider enabling extensive mode. The additional + rigour impacts performance more than fast mode: we recommend benchmarking to + determine if that is acceptable for your program. +- **Debug mode**, which enables all the available checks in the library, + including internal assertions, some of which might be very expensive. This + mode is intended to be used for testing, not in production. + +.. note:: + + Enabling hardening has no impact on the ABI. + +Notes for users +--------------- + +As a libc++ user, consult with your vendor to determine the level of hardening +enabled by default. + +Users wishing for a different hardening level to their vendor default are able +to control the level by passing **one** of the following options to the compiler: + +- ``-D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_NONE`` +- ``-D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_FAST`` +- ``-D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE`` +- ``-D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_DEBUG`` + +.. warning:: + + The exact numeric values of these macros are unspecified and users should not + rely on them (e.g. expect the values to be sorted in any way). + +.. warning:: + + If you would prefer to override the hardening level on a per-translation-unit + basis, you must do so **before** including any headers to avoid `ODR issues`_. + +.. _`ODR issues`: https://en.cppreference.com/w/cpp/language/definition#:~:text=is%20ill%2Dformed.-,One%20Definition%20Rule,-Only%20one%20definition + +.. note:: + + Since the static and shared library components of libc++ are built by the + vendor, setting this macro will have no impact on the hardening mode for the + pre-built components. Most libc++ code is header-based, so a user-provided + value for ``_LIBCPP_HARDENING_MODE`` will be mostly respected. + +Notes for vendors +----------------- + +Vendors can set the default hardening mode by providing ``LIBCXX_HARDENING_MODE`` +as a configuration option, with the possible values of ``none``, ``fast``, +``extensive`` and ``debug``. The default value is ``none`` which doesn't enable +any hardening checks (this mode is sometimes called the ``unchecked`` mode). + +This option controls both the hardening mode that the precompiled library is +built with and the default hardening mode that users will build with. If set to +``none``, the precompiled library will not contain any assertions, and user code +will default to building without assertions. Iterator bounds checking ------------------------ + TODO(hardening) diff --git a/libcxx/docs/Status/Cxx23Papers.csv b/libcxx/docs/Status/Cxx23Papers.csv index 5cc9e488297b..e03cbff2a08b 100644 --- a/libcxx/docs/Status/Cxx23Papers.csv +++ b/libcxx/docs/Status/Cxx23Papers.csv @@ -5,7 +5,7 @@ "`P1679R3 `__","LWG","string contains function","Autumn 2020","|Complete|","12.0" "","","","","","","" "`P1682R3 `__","LWG","std::to_underlying for enumerations","February 2021","|Complete|","13.0" -"`P2017R1 `__","LWG","Conditionally borrowed ranges","February 2021","","","|ranges|" +"`P2017R1 `__","LWG","Conditionally borrowed ranges","February 2021","|Complete|","16.0","|ranges|" "`P2160R1 `__","LWG","Locks lock lockables","February 2021","","" "`P2162R2 `__","LWG","Inheriting from std::variant","February 2021","|Complete|","13.0" "`P2212R2 `__","LWG","Relax Requirements for time_point::clock","February 2021","","" diff --git a/libcxx/include/__algorithm/clamp.h b/libcxx/include/__algorithm/clamp.h index fc0882791940..1631b2673c3f 100644 --- a/libcxx/include/__algorithm/clamp.h +++ b/libcxx/include/__algorithm/clamp.h @@ -35,7 +35,7 @@ _LIBCPP_NODISCARD_EXT inline _LIBCPP_HIDE_FROM_ABI constexpr const _Tp& clamp(_LIBCPP_LIFETIMEBOUND const _Tp& __v, _LIBCPP_LIFETIMEBOUND const _Tp& __lo, _LIBCPP_LIFETIMEBOUND const _Tp& __hi) { - return _VSTD::clamp(__v, __lo, __hi, __less<>()); + return std::clamp(__v, __lo, __hi, __less<>()); } #endif diff --git a/libcxx/include/__algorithm/copy_n.h b/libcxx/include/__algorithm/copy_n.h index 19f3f729c3d0..1707e26688c6 100644 --- a/libcxx/include/__algorithm/copy_n.h +++ b/libcxx/include/__algorithm/copy_n.h @@ -28,7 +28,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _OutputIterator copy_n(_InputIterator __first, _Size __orig_n, _OutputIterator __result) { - typedef decltype(_VSTD::__convert_to_integral(__orig_n)) _IntegralSize; + typedef decltype(std::__convert_to_integral(__orig_n)) _IntegralSize; _IntegralSize __n = __orig_n; if (__n > 0) { @@ -51,9 +51,9 @@ _OutputIterator copy_n(_InputIterator __first, _Size __orig_n, _OutputIterator __result) { typedef typename iterator_traits<_InputIterator>::difference_type difference_type; - typedef decltype(_VSTD::__convert_to_integral(__orig_n)) _IntegralSize; + typedef decltype(std::__convert_to_integral(__orig_n)) _IntegralSize; _IntegralSize __n = __orig_n; - return _VSTD::copy(__first, __first + difference_type(__n), __result); + return std::copy(__first, __first + difference_type(__n), __result); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/equal.h b/libcxx/include/__algorithm/equal.h index ca2e49ca5679..fb358613e210 100644 --- a/libcxx/include/__algorithm/equal.h +++ b/libcxx/include/__algorithm/equal.h @@ -107,7 +107,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 bool __equal(_RandomAccessIterator1 __first1, _RandomAccessIterator1 __last1, _RandomAccessIterator2 __first2, _RandomAccessIterator2 __last2, _BinaryPredicate __pred, random_access_iterator_tag, random_access_iterator_tag) { - if (_VSTD::distance(__first1, __last1) != _VSTD::distance(__first2, __last2)) + if (std::distance(__first1, __last1) != std::distance(__first2, __last2)) return false; __identity __proj; return std::__equal_impl( @@ -124,7 +124,7 @@ template _LIBCPP_NODISCARD_EXT inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 bool equal(_InputIterator1 __first1, _InputIterator1 __last1, _InputIterator2 __first2, _InputIterator2 __last2, _BinaryPredicate __pred) { - return _VSTD::__equal<_BinaryPredicate&>( + return std::__equal<_BinaryPredicate&>( __first1, __last1, __first2, __last2, __pred, typename iterator_traits<_InputIterator1>::iterator_category(), typename iterator_traits<_InputIterator2>::iterator_category()); } diff --git a/libcxx/include/__algorithm/fill.h b/libcxx/include/__algorithm/fill.h index e59c4963851d..360e2c3c3c85 100644 --- a/libcxx/include/__algorithm/fill.h +++ b/libcxx/include/__algorithm/fill.h @@ -35,7 +35,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __fill(_RandomAccessIterator __first, _RandomAccessIterator __last, const _Tp& __value, random_access_iterator_tag) { - _VSTD::fill_n(__first, __last - __first, __value); + std::fill_n(__first, __last - __first, __value); } template @@ -43,7 +43,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void fill(_ForwardIterator __first, _ForwardIterator __last, const _Tp& __value) { - _VSTD::__fill(__first, __last, __value, typename iterator_traits<_ForwardIterator>::iterator_category()); + std::__fill(__first, __last, __value, typename iterator_traits<_ForwardIterator>::iterator_category()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/fill_n.h b/libcxx/include/__algorithm/fill_n.h index c2dfbf119758..89681a342ea7 100644 --- a/libcxx/include/__algorithm/fill_n.h +++ b/libcxx/include/__algorithm/fill_n.h @@ -36,7 +36,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _OutputIterator fill_n(_OutputIterator __first, _Size __n, const _Tp& __value) { - return _VSTD::__fill_n(__first, _VSTD::__convert_to_integral(__n), __value); + return std::__fill_n(__first, std::__convert_to_integral(__n), __value); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/find_first_of.h b/libcxx/include/__algorithm/find_first_of.h index c386687d46ff..15a147242b0e 100644 --- a/libcxx/include/__algorithm/find_first_of.h +++ b/libcxx/include/__algorithm/find_first_of.h @@ -38,7 +38,7 @@ template diff --git a/libcxx/include/__algorithm/for_each_n.h b/libcxx/include/__algorithm/for_each_n.h index 7006bafe7304..a72a0912cfa5 100644 --- a/libcxx/include/__algorithm/for_each_n.h +++ b/libcxx/include/__algorithm/for_each_n.h @@ -25,7 +25,7 @@ template inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _InputIterator for_each_n(_InputIterator __first, _Size __orig_n, _Function __f) { - typedef decltype(_VSTD::__convert_to_integral(__orig_n)) _IntegralSize; + typedef decltype(std::__convert_to_integral(__orig_n)) _IntegralSize; _IntegralSize __n = __orig_n; while (__n > 0) { __f(*__first); diff --git a/libcxx/include/__algorithm/generate_n.h b/libcxx/include/__algorithm/generate_n.h index 1c8194c3c071..5719826e93ed 100644 --- a/libcxx/include/__algorithm/generate_n.h +++ b/libcxx/include/__algorithm/generate_n.h @@ -23,7 +23,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _OutputIterator generate_n(_OutputIterator __first, _Size __orig_n, _Generator __gen) { - typedef decltype(_VSTD::__convert_to_integral(__orig_n)) _IntegralSize; + typedef decltype(std::__convert_to_integral(__orig_n)) _IntegralSize; _IntegralSize __n = __orig_n; for (; __n > 0; ++__first, (void) --__n) *__first = __gen(); diff --git a/libcxx/include/__algorithm/inplace_merge.h b/libcxx/include/__algorithm/inplace_merge.h index a3dad4668cbd..d49c2e5cedda 100644 --- a/libcxx/include/__algorithm/inplace_merge.h +++ b/libcxx/include/__algorithm/inplace_merge.h @@ -224,10 +224,10 @@ __inplace_merge(_BidirectionalIterator __first, _BidirectionalIterator __middle, typedef typename iterator_traits<_BidirectionalIterator>::difference_type difference_type; difference_type __len1 = _IterOps<_AlgPolicy>::distance(__first, __middle); difference_type __len2 = _IterOps<_AlgPolicy>::distance(__middle, __last); - difference_type __buf_size = _VSTD::min(__len1, __len2); + difference_type __buf_size = std::min(__len1, __len2); // TODO: Remove the use of std::get_temporary_buffer _LIBCPP_SUPPRESS_DEPRECATED_PUSH - pair __buf = _VSTD::get_temporary_buffer(__buf_size); + pair __buf = std::get_temporary_buffer(__buf_size); _LIBCPP_SUPPRESS_DEPRECATED_POP unique_ptr __h(__buf.first); return std::__inplace_merge<_AlgPolicy>( diff --git a/libcxx/include/__algorithm/is_heap.h b/libcxx/include/__algorithm/is_heap.h index 77cbe019ec0b..dd78031579ec 100644 --- a/libcxx/include/__algorithm/is_heap.h +++ b/libcxx/include/__algorithm/is_heap.h @@ -36,7 +36,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 bool is_heap(_RandomAccessIterator __first, _RandomAccessIterator __last) { - return _VSTD::is_heap(__first, __last, __less<>()); + return std::is_heap(__first, __last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/is_heap_until.h b/libcxx/include/__algorithm/is_heap_until.h index d7131114bd60..85f70e649f56 100644 --- a/libcxx/include/__algorithm/is_heap_until.h +++ b/libcxx/include/__algorithm/is_heap_until.h @@ -58,7 +58,7 @@ template _LIBCPP_NODISCARD_EXT inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _RandomAccessIterator is_heap_until(_RandomAccessIterator __first, _RandomAccessIterator __last) { - return _VSTD::__is_heap_until(__first, __last, __less<>()); + return std::__is_heap_until(__first, __last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/is_sorted.h b/libcxx/include/__algorithm/is_sorted.h index 69374962c105..0003097b362c 100644 --- a/libcxx/include/__algorithm/is_sorted.h +++ b/libcxx/include/__algorithm/is_sorted.h @@ -27,7 +27,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 bool is_sorted(_ForwardIterator __first, _ForwardIterator __last, _Compare __comp) { - return _VSTD::__is_sorted_until<__comp_ref_type<_Compare> >(__first, __last, __comp) == __last; + return std::__is_sorted_until<__comp_ref_type<_Compare> >(__first, __last, __comp) == __last; } template @@ -36,7 +36,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 bool is_sorted(_ForwardIterator __first, _ForwardIterator __last) { - return _VSTD::is_sorted(__first, __last, __less<>()); + return std::is_sorted(__first, __last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/is_sorted_until.h b/libcxx/include/__algorithm/is_sorted_until.h index 890b93631c46..aeb3f1c8be98 100644 --- a/libcxx/include/__algorithm/is_sorted_until.h +++ b/libcxx/include/__algorithm/is_sorted_until.h @@ -41,14 +41,14 @@ template _LIBCPP_NODISCARD_EXT inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _ForwardIterator is_sorted_until(_ForwardIterator __first, _ForwardIterator __last, _Compare __comp) { - return _VSTD::__is_sorted_until<__comp_ref_type<_Compare> >(__first, __last, __comp); + return std::__is_sorted_until<__comp_ref_type<_Compare> >(__first, __last, __comp); } template _LIBCPP_NODISCARD_EXT inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _ForwardIterator is_sorted_until(_ForwardIterator __first, _ForwardIterator __last) { - return _VSTD::is_sorted_until(__first, __last, __less<>()); + return std::is_sorted_until(__first, __last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/lexicographical_compare.h b/libcxx/include/__algorithm/lexicographical_compare.h index 9a5b657b7f91..1ee189a25902 100644 --- a/libcxx/include/__algorithm/lexicographical_compare.h +++ b/libcxx/include/__algorithm/lexicographical_compare.h @@ -42,7 +42,7 @@ bool lexicographical_compare(_InputIterator1 __first1, _InputIterator1 __last1, _InputIterator2 __first2, _InputIterator2 __last2, _Compare __comp) { - return _VSTD::__lexicographical_compare<__comp_ref_type<_Compare> >(__first1, __last1, __first2, __last2, __comp); + return std::__lexicographical_compare<__comp_ref_type<_Compare> >(__first1, __last1, __first2, __last2, __comp); } template @@ -52,7 +52,7 @@ bool lexicographical_compare(_InputIterator1 __first1, _InputIterator1 __last1, _InputIterator2 __first2, _InputIterator2 __last2) { - return _VSTD::lexicographical_compare(__first1, __last1, __first2, __last2, __less<>()); + return std::lexicographical_compare(__first1, __last1, __first2, __last2, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/max.h b/libcxx/include/__algorithm/max.h index 38ef792f0cf2..183a4e9cac06 100644 --- a/libcxx/include/__algorithm/max.h +++ b/libcxx/include/__algorithm/max.h @@ -39,7 +39,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 const _Tp& max(_LIBCPP_LIFETIMEBOUND const _Tp& __a, _LIBCPP_LIFETIMEBOUND const _Tp& __b) { - return _VSTD::max(__a, __b, __less<>()); + return std::max(__a, __b, __less<>()); } #ifndef _LIBCPP_CXX03_LANG @@ -50,7 +50,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp max(initializer_list<_Tp> __t, _Compare __comp) { - return *_VSTD::__max_element<__comp_ref_type<_Compare> >(__t.begin(), __t.end(), __comp); + return *std::__max_element<__comp_ref_type<_Compare> >(__t.begin(), __t.end(), __comp); } template @@ -59,7 +59,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp max(initializer_list<_Tp> __t) { - return *_VSTD::max_element(__t.begin(), __t.end(), __less<>()); + return *std::max_element(__t.begin(), __t.end(), __less<>()); } #endif // _LIBCPP_CXX03_LANG diff --git a/libcxx/include/__algorithm/max_element.h b/libcxx/include/__algorithm/max_element.h index 8fd52c77723c..a2dc9707c00b 100644 --- a/libcxx/include/__algorithm/max_element.h +++ b/libcxx/include/__algorithm/max_element.h @@ -40,7 +40,7 @@ template _LIBCPP_NODISCARD_EXT inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _ForwardIterator max_element(_ForwardIterator __first, _ForwardIterator __last, _Compare __comp) { - return _VSTD::__max_element<__comp_ref_type<_Compare> >(__first, __last, __comp); + return std::__max_element<__comp_ref_type<_Compare> >(__first, __last, __comp); } @@ -48,7 +48,7 @@ template _LIBCPP_NODISCARD_EXT inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _ForwardIterator max_element(_ForwardIterator __first, _ForwardIterator __last) { - return _VSTD::max_element(__first, __last, __less<>()); + return std::max_element(__first, __last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/merge.h b/libcxx/include/__algorithm/merge.h index ff02e562c3dd..8a6021f1880b 100644 --- a/libcxx/include/__algorithm/merge.h +++ b/libcxx/include/__algorithm/merge.h @@ -30,7 +30,7 @@ __merge(_InputIterator1 __first1, _InputIterator1 __last1, for (; __first1 != __last1; ++__result) { if (__first2 == __last2) - return _VSTD::copy(__first1, __last1, __result); + return std::copy(__first1, __last1, __result); if (__comp(*__first2, *__first1)) { *__result = *__first2; @@ -42,7 +42,7 @@ __merge(_InputIterator1 __first1, _InputIterator1 __last1, ++__first1; } } - return _VSTD::copy(__first2, __last2, __result); + return std::copy(__first2, __last2, __result); } template @@ -51,7 +51,7 @@ _OutputIterator merge(_InputIterator1 __first1, _InputIterator1 __last1, _InputIterator2 __first2, _InputIterator2 __last2, _OutputIterator __result, _Compare __comp) { - return _VSTD::__merge<__comp_ref_type<_Compare> >(__first1, __last1, __first2, __last2, __result, __comp); + return std::__merge<__comp_ref_type<_Compare> >(__first1, __last1, __first2, __last2, __result, __comp); } template @@ -60,7 +60,7 @@ _OutputIterator merge(_InputIterator1 __first1, _InputIterator1 __last1, _InputIterator2 __first2, _InputIterator2 __last2, _OutputIterator __result) { - return _VSTD::merge(__first1, __last1, __first2, __last2, __result, __less<>()); + return std::merge(__first1, __last1, __first2, __last2, __result, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/min.h b/libcxx/include/__algorithm/min.h index 542c90a6decc..58574517132f 100644 --- a/libcxx/include/__algorithm/min.h +++ b/libcxx/include/__algorithm/min.h @@ -39,7 +39,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 const _Tp& min(_LIBCPP_LIFETIMEBOUND const _Tp& __a, _LIBCPP_LIFETIMEBOUND const _Tp& __b) { - return _VSTD::min(__a, __b, __less<>()); + return std::min(__a, __b, __less<>()); } #ifndef _LIBCPP_CXX03_LANG @@ -50,7 +50,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp min(initializer_list<_Tp> __t, _Compare __comp) { - return *_VSTD::__min_element<__comp_ref_type<_Compare> >(__t.begin(), __t.end(), __comp); + return *std::__min_element<__comp_ref_type<_Compare> >(__t.begin(), __t.end(), __comp); } template @@ -59,7 +59,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp min(initializer_list<_Tp> __t) { - return *_VSTD::min_element(__t.begin(), __t.end(), __less<>()); + return *std::min_element(__t.begin(), __t.end(), __less<>()); } #endif // _LIBCPP_CXX03_LANG diff --git a/libcxx/include/__algorithm/min_element.h b/libcxx/include/__algorithm/min_element.h index 45f3e85ef92d..0ce7af69333f 100644 --- a/libcxx/include/__algorithm/min_element.h +++ b/libcxx/include/__algorithm/min_element.h @@ -64,7 +64,7 @@ template _LIBCPP_NODISCARD_EXT inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _ForwardIterator min_element(_ForwardIterator __first, _ForwardIterator __last) { - return _VSTD::min_element(__first, __last, __less<>()); + return std::min_element(__first, __last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/next_permutation.h b/libcxx/include/__algorithm/next_permutation.h index bfa63ef16970..ebaed15ae2ad 100644 --- a/libcxx/include/__algorithm/next_permutation.h +++ b/libcxx/include/__algorithm/next_permutation.h @@ -69,7 +69,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 bool next_permutation(_BidirectionalIterator __first, _BidirectionalIterator __last) { - return _VSTD::next_permutation(__first, __last, __less<>()); + return std::next_permutation(__first, __last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/nth_element.h b/libcxx/include/__algorithm/nth_element.h index ebd1cbf76143..6b3b2bb434d5 100644 --- a/libcxx/include/__algorithm/nth_element.h +++ b/libcxx/include/__algorithm/nth_element.h @@ -92,7 +92,7 @@ __nth_element(_RandomAccessIterator __first, _RandomAccessIterator __nth, _Rando if (!__comp(*__i, *__m)) // if *__first == *__m { // *__first == *__m, *__first doesn't go in first part - if (_VSTD::__nth_element_find_guard<_Compare>(__i, __j, __m, __comp)) { + if (std::__nth_element_find_guard<_Compare>(__i, __j, __m, __comp)) { _Ops::iter_swap(__i, __j); ++__n_swaps; } else { @@ -142,7 +142,7 @@ __nth_element(_RandomAccessIterator __first, _RandomAccessIterator __nth, _Rando return; } // __nth_element the second part - // _VSTD::__nth_element<_Compare>(__i, __nth, __last, __comp); + // std::__nth_element<_Compare>(__i, __nth, __last, __comp); __first = __i; continue; } @@ -228,12 +228,12 @@ __nth_element(_RandomAccessIterator __first, _RandomAccessIterator __nth, _Rando // __nth_element on range containing __nth if (__nth < __i) { - // _VSTD::__nth_element<_Compare>(__first, __nth, __i, __comp); + // std::__nth_element<_Compare>(__first, __nth, __i, __comp); __last = __i; } else { - // _VSTD::__nth_element<_Compare>(__i+1, __nth, __last, __comp); + // std::__nth_element<_Compare>(__i+1, __nth, __last, __comp); __first = ++__i; } } diff --git a/libcxx/include/__algorithm/partial_sort.h b/libcxx/include/__algorithm/partial_sort.h index 0d813e3a2503..de4ebfcbd858 100644 --- a/libcxx/include/__algorithm/partial_sort.h +++ b/libcxx/include/__algorithm/partial_sort.h @@ -87,7 +87,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void partial_sort(_RandomAccessIterator __first, _RandomAccessIterator __middle, _RandomAccessIterator __last) { - _VSTD::partial_sort(__first, __middle, __last, __less<>()); + std::partial_sort(__first, __middle, __last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/partial_sort_copy.h b/libcxx/include/__algorithm/partial_sort_copy.h index 05dd7c3b499f..2c1e786d030e 100644 --- a/libcxx/include/__algorithm/partial_sort_copy.h +++ b/libcxx/include/__algorithm/partial_sort_copy.h @@ -79,7 +79,7 @@ _RandomAccessIterator partial_sort_copy(_InputIterator __first, _InputIterator __last, _RandomAccessIterator __result_first, _RandomAccessIterator __result_last) { - return _VSTD::partial_sort_copy(__first, __last, __result_first, __result_last, __less<>()); + return std::partial_sort_copy(__first, __last, __result_first, __result_last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/partition_point.h b/libcxx/include/__algorithm/partition_point.h index 6ede71a264cd..a61ed5ec5b41 100644 --- a/libcxx/include/__algorithm/partition_point.h +++ b/libcxx/include/__algorithm/partition_point.h @@ -26,12 +26,12 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _ForwardIterator partition_point(_ForwardIterator __first, _ForwardIterator __last, _Predicate __pred) { typedef typename iterator_traits<_ForwardIterator>::difference_type difference_type; - difference_type __len = _VSTD::distance(__first, __last); + difference_type __len = std::distance(__first, __last); while (__len != 0) { - difference_type __l2 = _VSTD::__half_positive(__len); + difference_type __l2 = std::__half_positive(__len); _ForwardIterator __m = __first; - _VSTD::advance(__m, __l2); + std::advance(__m, __l2); if (__pred(*__m)) { __first = ++__m; diff --git a/libcxx/include/__algorithm/prev_permutation.h b/libcxx/include/__algorithm/prev_permutation.h index a531edf581f3..4a6bf4a66439 100644 --- a/libcxx/include/__algorithm/prev_permutation.h +++ b/libcxx/include/__algorithm/prev_permutation.h @@ -70,7 +70,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 bool prev_permutation(_BidirectionalIterator __first, _BidirectionalIterator __last) { - return _VSTD::prev_permutation(__first, __last, __less<>()); + return std::prev_permutation(__first, __last, __less<>()); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/ranges_rotate_copy.h b/libcxx/include/__algorithm/ranges_rotate_copy.h index 301672707f72..ab76c0944c47 100644 --- a/libcxx/include/__algorithm/ranges_rotate_copy.h +++ b/libcxx/include/__algorithm/ranges_rotate_copy.h @@ -13,7 +13,6 @@ #include <__algorithm/ranges_copy.h> #include <__config> #include <__iterator/concepts.h> -#include <__iterator/reverse_iterator.h> #include <__ranges/access.h> #include <__ranges/concepts.h> #include <__ranges/dangling.h> @@ -34,7 +33,7 @@ using rotate_copy_result = in_out_result<_InIter, _OutIter>; namespace __rotate_copy { struct __fn { - template _Sent, weakly_incrementable _OutIter> + template _Sent, weakly_incrementable _OutIter> requires indirectly_copyable<_InIter, _OutIter> _LIBCPP_HIDE_FROM_ABI constexpr rotate_copy_result<_InIter, _OutIter> operator()(_InIter __first, _InIter __middle, _Sent __last, _OutIter __result) const { @@ -43,7 +42,7 @@ struct __fn { return {std::move(__res1.in), std::move(__res2.out)}; } - template + template requires indirectly_copyable, _OutIter> _LIBCPP_HIDE_FROM_ABI constexpr rotate_copy_result, _OutIter> operator()(_Range&& __range, iterator_t<_Range> __middle, _OutIter __result) const { diff --git a/libcxx/include/__algorithm/remove.h b/libcxx/include/__algorithm/remove.h index 533e41b54fa4..eff22757186e 100644 --- a/libcxx/include/__algorithm/remove.h +++ b/libcxx/include/__algorithm/remove.h @@ -24,7 +24,7 @@ template _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _ForwardIterator remove(_ForwardIterator __first, _ForwardIterator __last, const _Tp& __value) { - __first = _VSTD::find(__first, __last, __value); + __first = std::find(__first, __last, __value); if (__first != __last) { _ForwardIterator __i = __first; @@ -32,7 +32,7 @@ remove(_ForwardIterator __first, _ForwardIterator __last, const _Tp& __value) { if (!(*__i == __value)) { - *__first = _VSTD::move(*__i); + *__first = std::move(*__i); ++__first; } } diff --git a/libcxx/include/__algorithm/remove_if.h b/libcxx/include/__algorithm/remove_if.h index 27350728d256..8197e4fc2f8e 100644 --- a/libcxx/include/__algorithm/remove_if.h +++ b/libcxx/include/__algorithm/remove_if.h @@ -23,7 +23,7 @@ template _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _ForwardIterator remove_if(_ForwardIterator __first, _ForwardIterator __last, _Predicate __pred) { - __first = _VSTD::find_if<_ForwardIterator, _Predicate&>(__first, __last, __pred); + __first = std::find_if<_ForwardIterator, _Predicate&>(__first, __last, __pred); if (__first != __last) { _ForwardIterator __i = __first; @@ -31,7 +31,7 @@ remove_if(_ForwardIterator __first, _ForwardIterator __last, _Predicate __pred) { if (!__pred(*__i)) { - *__first = _VSTD::move(*__i); + *__first = std::move(*__i); ++__first; } } diff --git a/libcxx/include/__algorithm/rotate.h b/libcxx/include/__algorithm/rotate.h index a1cc2dfeeec9..f9236fcaafb2 100644 --- a/libcxx/include/__algorithm/rotate.h +++ b/libcxx/include/__algorithm/rotate.h @@ -35,7 +35,7 @@ __rotate_left(_ForwardIterator __first, _ForwardIterator __last) value_type __tmp = _Ops::__iter_move(__first); _ForwardIterator __lm1 = std::__move<_AlgPolicy>( _Ops::next(__first), __last, __first).second; - *__lm1 = _VSTD::move(__tmp); + *__lm1 = std::move(__tmp); return __lm1; } @@ -49,7 +49,7 @@ __rotate_right(_BidirectionalIterator __first, _BidirectionalIterator __last) _BidirectionalIterator __lm1 = _Ops::prev(__last); value_type __tmp = _Ops::__iter_move(__lm1); _BidirectionalIterator __fp1 = std::__move_backward<_AlgPolicy>(__first, __lm1, std::move(__last)).second; - *__first = _VSTD::move(__tmp); + *__first = std::move(__tmp); return __fp1; } @@ -117,7 +117,7 @@ __rotate_gcd(_RandomAccessIterator __first, _RandomAccessIterator __middle, _Ran std::__swap_ranges<_AlgPolicy>(__first, __middle, __middle, __last); return __middle; } - const difference_type __g = _VSTD::__algo_gcd(__m1, __m2); + const difference_type __g = std::__algo_gcd(__m1, __m2); for (_RandomAccessIterator __p = __first + __g; __p != __first;) { value_type __t(_Ops::__iter_move(--__p)); @@ -133,7 +133,7 @@ __rotate_gcd(_RandomAccessIterator __first, _RandomAccessIterator __middle, _Ran else __p2 = __first + (__m1 - __d); } while (__p2 != __p); - *__p1 = _VSTD::move(__t); + *__p1 = std::move(__t); } return __first + __m2; } @@ -142,7 +142,7 @@ template inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _ForwardIterator __rotate_impl(_ForwardIterator __first, _ForwardIterator __middle, _ForwardIterator __last, - _VSTD::forward_iterator_tag) + std::forward_iterator_tag) { typedef typename iterator_traits<_ForwardIterator>::value_type value_type; if (is_trivially_move_assignable::value) diff --git a/libcxx/include/__algorithm/rotate_copy.h b/libcxx/include/__algorithm/rotate_copy.h index 0eabb911723c..6e886cb73cfc 100644 --- a/libcxx/include/__algorithm/rotate_copy.h +++ b/libcxx/include/__algorithm/rotate_copy.h @@ -23,7 +23,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _OutputIterator rotate_copy(_ForwardIterator __first, _ForwardIterator __middle, _ForwardIterator __last, _OutputIterator __result) { - return _VSTD::copy(__first, __middle, _VSTD::copy(__middle, __last, __result)); + return std::copy(__first, __middle, std::copy(__middle, __last, __result)); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/sample.h b/libcxx/include/__algorithm/sample.h index e5b63378f359..100b0a466863 100644 --- a/libcxx/include/__algorithm/sample.h +++ b/libcxx/include/__algorithm/sample.h @@ -47,7 +47,7 @@ _SampleIterator __sample(_PopulationIterator __first, if (__r < __sz) __output_iter[__r] = *__first; } - return __output_iter + _VSTD::min(__n, __k); + return __output_iter + std::min(__n, __k); } template ::distance(__first, __last); - for (__n = _VSTD::min(__n, __unsampled_sz); __n != 0; ++__first) { + for (__n = std::min(__n, __unsampled_sz); __n != 0; ++__first) { _Distance __r = uniform_int_distribution<_Distance>(0, --__unsampled_sz)(__g); if (__r < __n) { *__output_iter++ = *__first; diff --git a/libcxx/include/__algorithm/shift_left.h b/libcxx/include/__algorithm/shift_left.h index 88e3525dfa23..c9f2cbb9f7b6 100644 --- a/libcxx/include/__algorithm/shift_left.h +++ b/libcxx/include/__algorithm/shift_left.h @@ -45,7 +45,7 @@ shift_left(_ForwardIterator __first, _ForwardIterator __last, ++__m; } } - return _VSTD::move(__m, __last, __first); + return std::move(__m, __last, __first); } #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__algorithm/shift_right.h b/libcxx/include/__algorithm/shift_right.h index b73d09c99603..70983e327bcb 100644 --- a/libcxx/include/__algorithm/shift_right.h +++ b/libcxx/include/__algorithm/shift_right.h @@ -40,7 +40,7 @@ shift_right(_ForwardIterator __first, _ForwardIterator __last, return __last; } _ForwardIterator __m = __first + (__d - __n); - return _VSTD::move_backward(__first, __m, __last); + return std::move_backward(__first, __m, __last); } else if constexpr (__has_bidirectional_iterator_category<_ForwardIterator>::value) { _ForwardIterator __m = __last; for (; __n > 0; --__n) { @@ -49,7 +49,7 @@ shift_right(_ForwardIterator __first, _ForwardIterator __last, } --__m; } - return _VSTD::move_backward(__first, __m, __last); + return std::move_backward(__first, __m, __last); } else { _ForwardIterator __ret = __first; for (; __n > 0; --__n) { @@ -69,7 +69,7 @@ shift_right(_ForwardIterator __first, _ForwardIterator __last, auto __lead = __ret; while (__trail != __ret) { if (__lead == __last) { - _VSTD::move(__first, __trail, __ret); + std::move(__first, __trail, __ret); return __ret; } ++__trail; @@ -79,8 +79,8 @@ shift_right(_ForwardIterator __first, _ForwardIterator __last, _ForwardIterator __mid = __first; while (true) { if (__lead == __last) { - __trail = _VSTD::move(__mid, __ret, __trail); - _VSTD::move(__first, __mid, __trail); + __trail = std::move(__mid, __ret, __trail); + std::move(__first, __mid, __trail); return __ret; } swap(*__mid, *__trail); diff --git a/libcxx/include/__algorithm/sift_down.h b/libcxx/include/__algorithm/sift_down.h index 20f0b0275dd9..3a222f7c7f1b 100644 --- a/libcxx/include/__algorithm/sift_down.h +++ b/libcxx/include/__algorithm/sift_down.h @@ -77,7 +77,7 @@ __sift_down(_RandomAccessIterator __first, _Compare&& __comp, // check if we are in heap-order } while (!__comp(*__child_i, __top)); - *__start = _VSTD::move(__top); + *__start = std::move(__top); } template diff --git a/libcxx/include/__algorithm/stable_partition.h b/libcxx/include/__algorithm/stable_partition.h index e64ce850f08c..0e92a0a5f73d 100644 --- a/libcxx/include/__algorithm/stable_partition.h +++ b/libcxx/include/__algorithm/stable_partition.h @@ -144,7 +144,7 @@ __stable_partition_impl(_ForwardIterator __first, _ForwardIterator __last, _Pred { // TODO: Remove the use of std::get_temporary_buffer _LIBCPP_SUPPRESS_DEPRECATED_PUSH - __p = _VSTD::get_temporary_buffer(__len); + __p = std::get_temporary_buffer(__len); _LIBCPP_SUPPRESS_DEPRECATED_POP __h.reset(__p.first); } @@ -298,7 +298,7 @@ __stable_partition_impl(_BidirectionalIterator __first, _BidirectionalIterator _ { // TODO: Remove the use of std::get_temporary_buffer _LIBCPP_SUPPRESS_DEPRECATED_PUSH - __p = _VSTD::get_temporary_buffer(__len); + __p = std::get_temporary_buffer(__len); _LIBCPP_SUPPRESS_DEPRECATED_POP __h.reset(__p.first); } diff --git a/libcxx/include/__algorithm/stable_sort.h b/libcxx/include/__algorithm/stable_sort.h index dc24218b74dd..175393fc4777 100644 --- a/libcxx/include/__algorithm/stable_sort.h +++ b/libcxx/include/__algorithm/stable_sort.h @@ -230,7 +230,7 @@ __stable_sort(_RandomAccessIterator __first, _RandomAccessIterator __last, _Comp __d.__set(__len, (value_type*)nullptr); std::__merge_move_assign<_AlgPolicy, _Compare>( __buff, __buff + __l2, __buff + __l2, __buff + __len, __first, __comp); -// _VSTD::__merge<_Compare>(move_iterator(__buff), +// std::__merge<_Compare>(move_iterator(__buff), // move_iterator(__buff + __l2), // move_iterator<_RandomAccessIterator>(__buff + __l2), // move_iterator<_RandomAccessIterator>(__buff + __len), diff --git a/libcxx/include/__availability b/libcxx/include/__availability index a5bae266dc16..b5230b3f56b8 100644 --- a/libcxx/include/__availability +++ b/libcxx/include/__availability @@ -165,10 +165,12 @@ # define _LIBCPP_AVAILABILITY_BAD_ANY_CAST _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS // +// clang-format off # if (defined(__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ < 101500) || \ (defined(__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__ < 130000) || \ (defined(__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__ < 130000) || \ (defined(__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__ < 60000) +// clang-format on # define _LIBCPP_AVAILABILITY_HAS_FILESYSTEM_LIBRARY 0 # else # define _LIBCPP_AVAILABILITY_HAS_FILESYSTEM_LIBRARY 1 @@ -178,6 +180,7 @@ __attribute__((availability(ios,strict,introduced=13.0))) \ __attribute__((availability(tvos,strict,introduced=13.0))) \ __attribute__((availability(watchos,strict,introduced=6.0))) +// clang-format off # define _LIBCPP_AVAILABILITY_FILESYSTEM_LIBRARY_PUSH \ _Pragma("clang attribute push(__attribute__((availability(macos,strict,introduced=10.15))), apply_to=any(function,record))") \ _Pragma("clang attribute push(__attribute__((availability(ios,strict,introduced=13.0))), apply_to=any(function,record))") \ @@ -188,12 +191,15 @@ _Pragma("clang attribute pop") \ _Pragma("clang attribute pop") \ _Pragma("clang attribute pop") +// clang-format on // std::to_chars(floating-point) +// clang-format off # if (defined(__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ < 130300) || \ (defined(__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__ < 160300) || \ (defined(__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__ < 160300) || \ (defined(__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__ < 90300) +// clang-format on # define _LIBCPP_AVAILABILITY_HAS_TO_CHARS_FLOATING_POINT 0 # else # define _LIBCPP_AVAILABILITY_HAS_TO_CHARS_FLOATING_POINT 1 @@ -205,10 +211,12 @@ __attribute__((availability(watchos,strict,introduced=9.3))) // c++20 synchronization library +// clang-format off # if (defined(__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ < 110000) || \ (defined(__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__ < 140000) || \ (defined(__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__ < 140000) || \ (defined(__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__ < 70000) +// clang-format on # define _LIBCPP_AVAILABILITY_HAS_SYNC 0 # else # define _LIBCPP_AVAILABILITY_HAS_SYNC 1 @@ -227,10 +235,12 @@ __attribute__((unavailable)) // std::pmr +// clang-format off # if (defined(__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ < 140000) || \ (defined(__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__ < 170000) || \ (defined(__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__ < 170000) || \ (defined(__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__ < 100000) +// clang-format on # define _LIBCPP_AVAILABILITY_HAS_PMR 0 # else # define _LIBCPP_AVAILABILITY_HAS_PMR 1 @@ -252,10 +262,12 @@ # define _LIBCPP_AVAILABILITY_HAS_TZDB 0 # define _LIBCPP_AVAILABILITY_TZDB __attribute__((unavailable)) +// clang-format off # if (defined(__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ < 120000) || \ (defined(__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__ < 150000) || \ (defined(__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__ < 150000) || \ (defined(__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__ < 80000) +// clang-format on # define _LIBCPP_AVAILABILITY_HAS_ADDITIONAL_IOSTREAM_EXPLICIT_INSTANTIATIONS_1 0 # else # define _LIBCPP_AVAILABILITY_HAS_ADDITIONAL_IOSTREAM_EXPLICIT_INSTANTIATIONS_1 1 diff --git a/libcxx/include/__compare/compare_partial_order_fallback.h b/libcxx/include/__compare/compare_partial_order_fallback.h index fb2921ed52d2..a49408e1cfda 100644 --- a/libcxx/include/__compare/compare_partial_order_fallback.h +++ b/libcxx/include/__compare/compare_partial_order_fallback.h @@ -32,34 +32,34 @@ namespace __compare_partial_order_fallback { requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<1>) - noexcept(noexcept(_VSTD::partial_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - -> decltype( _VSTD::partial_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))) - { return _VSTD::partial_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)); } + noexcept(noexcept(std::partial_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + -> decltype( std::partial_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))) + { return std::partial_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)); } template requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<0>) - noexcept(noexcept(_VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u) ? partial_ordering::equivalent : - _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u) ? partial_ordering::less : - _VSTD::forward<_Up>(__u) < _VSTD::forward<_Tp>(__t) ? partial_ordering::greater : + noexcept(noexcept(std::forward<_Tp>(__t) == std::forward<_Up>(__u) ? partial_ordering::equivalent : + std::forward<_Tp>(__t) < std::forward<_Up>(__u) ? partial_ordering::less : + std::forward<_Up>(__u) < std::forward<_Tp>(__t) ? partial_ordering::greater : partial_ordering::unordered)) - -> decltype( _VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u) ? partial_ordering::equivalent : - _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u) ? partial_ordering::less : - _VSTD::forward<_Up>(__u) < _VSTD::forward<_Tp>(__t) ? partial_ordering::greater : + -> decltype( std::forward<_Tp>(__t) == std::forward<_Up>(__u) ? partial_ordering::equivalent : + std::forward<_Tp>(__t) < std::forward<_Up>(__u) ? partial_ordering::less : + std::forward<_Up>(__u) < std::forward<_Tp>(__t) ? partial_ordering::greater : partial_ordering::unordered) { - return _VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u) ? partial_ordering::equivalent : - _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u) ? partial_ordering::less : - _VSTD::forward<_Up>(__u) < _VSTD::forward<_Tp>(__t) ? partial_ordering::greater : + return std::forward<_Tp>(__t) == std::forward<_Up>(__u) ? partial_ordering::equivalent : + std::forward<_Tp>(__t) < std::forward<_Up>(__u) ? partial_ordering::less : + std::forward<_Up>(__u) < std::forward<_Tp>(__t) ? partial_ordering::greater : partial_ordering::unordered; } template _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp&& __t, _Up&& __u) const - noexcept(noexcept(__go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<1>()))) - -> decltype( __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<1>())) - { return __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<1>()); } + noexcept(noexcept(__go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<1>()))) + -> decltype( __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<1>())) + { return __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<1>()); } }; } // namespace __compare_partial_order_fallback diff --git a/libcxx/include/__compare/compare_strong_order_fallback.h b/libcxx/include/__compare/compare_strong_order_fallback.h index d84d065e4064..9e2dfee6b389 100644 --- a/libcxx/include/__compare/compare_strong_order_fallback.h +++ b/libcxx/include/__compare/compare_strong_order_fallback.h @@ -32,31 +32,31 @@ namespace __compare_strong_order_fallback { requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<1>) - noexcept(noexcept(_VSTD::strong_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - -> decltype( _VSTD::strong_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))) - { return _VSTD::strong_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)); } + noexcept(noexcept(std::strong_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + -> decltype( std::strong_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))) + { return std::strong_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)); } template requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<0>) - noexcept(noexcept(_VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u) ? strong_ordering::equal : - _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u) ? strong_ordering::less : + noexcept(noexcept(std::forward<_Tp>(__t) == std::forward<_Up>(__u) ? strong_ordering::equal : + std::forward<_Tp>(__t) < std::forward<_Up>(__u) ? strong_ordering::less : strong_ordering::greater)) - -> decltype( _VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u) ? strong_ordering::equal : - _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u) ? strong_ordering::less : + -> decltype( std::forward<_Tp>(__t) == std::forward<_Up>(__u) ? strong_ordering::equal : + std::forward<_Tp>(__t) < std::forward<_Up>(__u) ? strong_ordering::less : strong_ordering::greater) { - return _VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u) ? strong_ordering::equal : - _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u) ? strong_ordering::less : + return std::forward<_Tp>(__t) == std::forward<_Up>(__u) ? strong_ordering::equal : + std::forward<_Tp>(__t) < std::forward<_Up>(__u) ? strong_ordering::less : strong_ordering::greater; } template _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp&& __t, _Up&& __u) const - noexcept(noexcept(__go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<1>()))) - -> decltype( __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<1>())) - { return __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<1>()); } + noexcept(noexcept(__go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<1>()))) + -> decltype( __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<1>())) + { return __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<1>()); } }; } // namespace __compare_strong_order_fallback diff --git a/libcxx/include/__compare/compare_three_way.h b/libcxx/include/__compare/compare_three_way.h index 2bc63a00e55d..b1ed2d1e7251 100644 --- a/libcxx/include/__compare/compare_three_way.h +++ b/libcxx/include/__compare/compare_three_way.h @@ -28,8 +28,8 @@ struct _LIBCPP_TEMPLATE_VIS compare_three_way requires three_way_comparable_with<_T1, _T2> constexpr _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) <=> _VSTD::forward<_T2>(__u))) - { return _VSTD::forward<_T1>(__t) <=> _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) <=> std::forward<_T2>(__u))) + { return std::forward<_T1>(__t) <=> std::forward<_T2>(__u); } using is_transparent = void; }; diff --git a/libcxx/include/__compare/compare_weak_order_fallback.h b/libcxx/include/__compare/compare_weak_order_fallback.h index d3ba04a86bcf..b0a04abcaaf0 100644 --- a/libcxx/include/__compare/compare_weak_order_fallback.h +++ b/libcxx/include/__compare/compare_weak_order_fallback.h @@ -32,31 +32,31 @@ namespace __compare_weak_order_fallback { requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<1>) - noexcept(noexcept(_VSTD::weak_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - -> decltype( _VSTD::weak_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))) - { return _VSTD::weak_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)); } + noexcept(noexcept(std::weak_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + -> decltype( std::weak_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))) + { return std::weak_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)); } template requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<0>) - noexcept(noexcept(_VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u) ? weak_ordering::equivalent : - _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u) ? weak_ordering::less : + noexcept(noexcept(std::forward<_Tp>(__t) == std::forward<_Up>(__u) ? weak_ordering::equivalent : + std::forward<_Tp>(__t) < std::forward<_Up>(__u) ? weak_ordering::less : weak_ordering::greater)) - -> decltype( _VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u) ? weak_ordering::equivalent : - _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u) ? weak_ordering::less : + -> decltype( std::forward<_Tp>(__t) == std::forward<_Up>(__u) ? weak_ordering::equivalent : + std::forward<_Tp>(__t) < std::forward<_Up>(__u) ? weak_ordering::less : weak_ordering::greater) { - return _VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u) ? weak_ordering::equivalent : - _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u) ? weak_ordering::less : + return std::forward<_Tp>(__t) == std::forward<_Up>(__u) ? weak_ordering::equivalent : + std::forward<_Tp>(__t) < std::forward<_Up>(__u) ? weak_ordering::less : weak_ordering::greater; } template _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp&& __t, _Up&& __u) const - noexcept(noexcept(__go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<1>()))) - -> decltype( __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<1>())) - { return __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<1>()); } + noexcept(noexcept(__go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<1>()))) + -> decltype( __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<1>())) + { return __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<1>()); } }; } // namespace __compare_weak_order_fallback diff --git a/libcxx/include/__compare/partial_order.h b/libcxx/include/__compare/partial_order.h index 9cb76cc5bdbd..36a11dfaa288 100644 --- a/libcxx/include/__compare/partial_order.h +++ b/libcxx/include/__compare/partial_order.h @@ -34,32 +34,32 @@ namespace __partial_order { requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<2>) - noexcept(noexcept(partial_ordering(partial_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))))) - -> decltype( partial_ordering(partial_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - { return partial_ordering(partial_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))); } + noexcept(noexcept(partial_ordering(partial_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))))) + -> decltype( partial_ordering(partial_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + { return partial_ordering(partial_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))); } // NOLINTEND(libcpp-robust-against-adl) template requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<1>) - noexcept(noexcept(partial_ordering(compare_three_way()(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))))) - -> decltype( partial_ordering(compare_three_way()(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - { return partial_ordering(compare_three_way()(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))); } + noexcept(noexcept(partial_ordering(compare_three_way()(std::forward<_Tp>(__t), std::forward<_Up>(__u))))) + -> decltype( partial_ordering(compare_three_way()(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + { return partial_ordering(compare_three_way()(std::forward<_Tp>(__t), std::forward<_Up>(__u))); } template requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<0>) - noexcept(noexcept(partial_ordering(_VSTD::weak_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))))) - -> decltype( partial_ordering(_VSTD::weak_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - { return partial_ordering(_VSTD::weak_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))); } + noexcept(noexcept(partial_ordering(std::weak_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))))) + -> decltype( partial_ordering(std::weak_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + { return partial_ordering(std::weak_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))); } template _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp&& __t, _Up&& __u) const - noexcept(noexcept(__go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<2>()))) - -> decltype( __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<2>())) - { return __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<2>()); } + noexcept(noexcept(__go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<2>()))) + -> decltype( __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<2>())) + { return __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<2>()); } }; } // namespace __partial_order diff --git a/libcxx/include/__compare/strong_order.h b/libcxx/include/__compare/strong_order.h index b6e0cfaaa57d..cbfcf7316de9 100644 --- a/libcxx/include/__compare/strong_order.h +++ b/libcxx/include/__compare/strong_order.h @@ -40,9 +40,9 @@ namespace __strong_order { requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<2>) - noexcept(noexcept(strong_ordering(strong_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))))) - -> decltype( strong_ordering(strong_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - { return strong_ordering(strong_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))); } + noexcept(noexcept(strong_ordering(strong_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))))) + -> decltype( strong_ordering(strong_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + { return strong_ordering(strong_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))); } // NOLINTEND(libcpp-robust-against-adl) template> @@ -51,14 +51,14 @@ namespace __strong_order { __go(_Tp&& __t, _Up&& __u, __priority_tag<1>) noexcept { if constexpr (numeric_limits<_Dp>::is_iec559 && sizeof(_Dp) == sizeof(int32_t)) { - int32_t __rx = _VSTD::bit_cast(__t); - int32_t __ry = _VSTD::bit_cast(__u); + int32_t __rx = std::bit_cast(__t); + int32_t __ry = std::bit_cast(__u); __rx = (__rx < 0) ? (numeric_limits::min() - __rx - 1) : __rx; __ry = (__ry < 0) ? (numeric_limits::min() - __ry - 1) : __ry; return (__rx <=> __ry); } else if constexpr (numeric_limits<_Dp>::is_iec559 && sizeof(_Dp) == sizeof(int64_t)) { - int64_t __rx = _VSTD::bit_cast(__t); - int64_t __ry = _VSTD::bit_cast(__u); + int64_t __rx = std::bit_cast(__t); + int64_t __ry = std::bit_cast(__u); __rx = (__rx < 0) ? (numeric_limits::min() - __rx - 1) : __rx; __ry = (__ry < 0) ? (numeric_limits::min() - __ry - 1) : __ry; return (__rx <=> __ry); @@ -68,27 +68,27 @@ namespace __strong_order { return strong_ordering::greater; } else if (__t == __u) { if constexpr (numeric_limits<_Dp>::radix == 2) { - return _VSTD::signbit(__u) <=> _VSTD::signbit(__t); + return std::signbit(__u) <=> std::signbit(__t); } else { // This is bullet 3 of the IEEE754 algorithm, relevant // only for decimal floating-point; // see https://stackoverflow.com/questions/69068075/ - if (__t == 0 || _VSTD::isinf(__t)) { - return _VSTD::signbit(__u) <=> _VSTD::signbit(__t); + if (__t == 0 || std::isinf(__t)) { + return std::signbit(__u) <=> std::signbit(__t); } else { int __texp, __uexp; - (void)_VSTD::frexp(__t, &__texp); - (void)_VSTD::frexp(__u, &__uexp); + (void)std::frexp(__t, &__texp); + (void)std::frexp(__u, &__uexp); return (__t < 0) ? (__texp <=> __uexp) : (__uexp <=> __texp); } } } else { // They're unordered, so one of them must be a NAN. // The order is -QNAN, -SNAN, numbers, +SNAN, +QNAN. - bool __t_is_nan = _VSTD::isnan(__t); - bool __u_is_nan = _VSTD::isnan(__u); - bool __t_is_negative = _VSTD::signbit(__t); - bool __u_is_negative = _VSTD::signbit(__u); + bool __t_is_nan = std::isnan(__t); + bool __u_is_nan = std::isnan(__u); + bool __t_is_negative = std::signbit(__t); + bool __u_is_negative = std::signbit(__u); using _IntType = conditional_t< sizeof(__t) == sizeof(int32_t), int32_t, conditional_t< sizeof(__t) == sizeof(int64_t), int64_t, void> @@ -100,7 +100,7 @@ namespace __strong_order { if (__t_is_negative != __u_is_negative) { return (__u_is_negative <=> __t_is_negative); } else { - return _VSTD::bit_cast<_IntType>(__t) <=> _VSTD::bit_cast<_IntType>(__u); + return std::bit_cast<_IntType>(__t) <=> std::bit_cast<_IntType>(__u); } } else if (__t_is_nan) { return __t_is_negative ? strong_ordering::less : strong_ordering::greater; @@ -114,15 +114,15 @@ namespace __strong_order { requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<0>) - noexcept(noexcept(strong_ordering(compare_three_way()(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))))) - -> decltype( strong_ordering(compare_three_way()(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - { return strong_ordering(compare_three_way()(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))); } + noexcept(noexcept(strong_ordering(compare_three_way()(std::forward<_Tp>(__t), std::forward<_Up>(__u))))) + -> decltype( strong_ordering(compare_three_way()(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + { return strong_ordering(compare_three_way()(std::forward<_Tp>(__t), std::forward<_Up>(__u))); } template _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp&& __t, _Up&& __u) const - noexcept(noexcept(__go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<2>()))) - -> decltype( __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<2>())) - { return __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<2>()); } + noexcept(noexcept(__go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<2>()))) + -> decltype( __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<2>())) + { return __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<2>()); } }; } // namespace __strong_order diff --git a/libcxx/include/__compare/weak_order.h b/libcxx/include/__compare/weak_order.h index 9cbc1d24aa04..e6a42ac4c923 100644 --- a/libcxx/include/__compare/weak_order.h +++ b/libcxx/include/__compare/weak_order.h @@ -34,9 +34,9 @@ namespace __weak_order { requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<3>) - noexcept(noexcept(weak_ordering(weak_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))))) - -> decltype( weak_ordering(weak_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - { return weak_ordering(weak_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))); } + noexcept(noexcept(weak_ordering(weak_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))))) + -> decltype( weak_ordering(weak_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + { return weak_ordering(weak_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))); } // NOLINTEND(libcpp-robust-against-adl) template> @@ -53,10 +53,10 @@ namespace __weak_order { return weak_ordering::greater; } else { // Otherwise, at least one of them is a NaN. - bool __t_is_nan = _VSTD::isnan(__t); - bool __u_is_nan = _VSTD::isnan(__u); - bool __t_is_negative = _VSTD::signbit(__t); - bool __u_is_negative = _VSTD::signbit(__u); + bool __t_is_nan = std::isnan(__t); + bool __u_is_nan = std::isnan(__u); + bool __t_is_negative = std::signbit(__t); + bool __u_is_negative = std::signbit(__u); if (__t_is_nan && __u_is_nan) { return (__u_is_negative <=> __t_is_negative); } else if (__t_is_nan) { @@ -71,23 +71,23 @@ namespace __weak_order { requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<1>) - noexcept(noexcept(weak_ordering(compare_three_way()(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))))) - -> decltype( weak_ordering(compare_three_way()(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - { return weak_ordering(compare_three_way()(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))); } + noexcept(noexcept(weak_ordering(compare_three_way()(std::forward<_Tp>(__t), std::forward<_Up>(__u))))) + -> decltype( weak_ordering(compare_three_way()(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + { return weak_ordering(compare_three_way()(std::forward<_Tp>(__t), std::forward<_Up>(__u))); } template requires is_same_v, decay_t<_Up>> _LIBCPP_HIDE_FROM_ABI static constexpr auto __go(_Tp&& __t, _Up&& __u, __priority_tag<0>) - noexcept(noexcept(weak_ordering(_VSTD::strong_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))))) - -> decltype( weak_ordering(_VSTD::strong_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) - { return weak_ordering(_VSTD::strong_order(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u))); } + noexcept(noexcept(weak_ordering(std::strong_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))))) + -> decltype( weak_ordering(std::strong_order(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) + { return weak_ordering(std::strong_order(std::forward<_Tp>(__t), std::forward<_Up>(__u))); } template _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp&& __t, _Up&& __u) const - noexcept(noexcept(__go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<3>()))) - -> decltype( __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<3>())) - { return __go(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u), __priority_tag<3>()); } + noexcept(noexcept(__go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<3>()))) + -> decltype( __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<3>())) + { return __go(std::forward<_Tp>(__t), std::forward<_Up>(__u), __priority_tag<3>()); } }; } // namespace __weak_order diff --git a/libcxx/include/__concepts/assignable.h b/libcxx/include/__concepts/assignable.h index 3f7544c93406..7423daabba78 100644 --- a/libcxx/include/__concepts/assignable.h +++ b/libcxx/include/__concepts/assignable.h @@ -31,7 +31,7 @@ concept assignable_from = is_lvalue_reference_v<_Lhs> && common_reference_with<__make_const_lvalue_ref<_Lhs>, __make_const_lvalue_ref<_Rhs>> && requires(_Lhs __lhs, _Rhs&& __rhs) { - { __lhs = _VSTD::forward<_Rhs>(__rhs) } -> same_as<_Lhs>; + { __lhs = std::forward<_Rhs>(__rhs) } -> same_as<_Lhs>; }; #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__concepts/boolean_testable.h b/libcxx/include/__concepts/boolean_testable.h index d290e1cf3d83..b379fe9c5a88 100644 --- a/libcxx/include/__concepts/boolean_testable.h +++ b/libcxx/include/__concepts/boolean_testable.h @@ -28,7 +28,7 @@ concept __boolean_testable_impl = convertible_to<_Tp, bool>; template concept __boolean_testable = __boolean_testable_impl<_Tp> && requires(_Tp&& __t) { - { !_VSTD::forward<_Tp>(__t) } -> __boolean_testable_impl; + { !std::forward<_Tp>(__t) } -> __boolean_testable_impl; }; #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__concepts/invocable.h b/libcxx/include/__concepts/invocable.h index e5be514b5c38..8a29398b3a29 100644 --- a/libcxx/include/__concepts/invocable.h +++ b/libcxx/include/__concepts/invocable.h @@ -25,7 +25,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD template concept invocable = requires(_Fn&& __fn, _Args&&... __args) { - _VSTD::invoke(_VSTD::forward<_Fn>(__fn), _VSTD::forward<_Args>(__args)...); // not required to be equality preserving + std::invoke(std::forward<_Fn>(__fn), std::forward<_Args>(__args)...); // not required to be equality preserving }; // [concept.regular.invocable] diff --git a/libcxx/include/__concepts/swappable.h b/libcxx/include/__concepts/swappable.h index cdffe3420555..1337dc49d75b 100644 --- a/libcxx/include/__concepts/swappable.h +++ b/libcxx/include/__concepts/swappable.h @@ -48,7 +48,7 @@ template concept __unqualified_swappable_with = (__class_or_enum> || __class_or_enum>) && requires(_Tp&& __t, _Up&& __u) { - swap(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)); + swap(std::forward<_Tp>(__t), std::forward<_Up>(__u)); }; // clang-format on @@ -74,8 +74,8 @@ struct __fn { template requires __unqualified_swappable_with<_Tp, _Up> _LIBCPP_HIDE_FROM_ABI constexpr void operator()(_Tp&& __t, _Up&& __u) const - noexcept(noexcept(swap(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)))) { - swap(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)); + noexcept(noexcept(swap(std::forward<_Tp>(__t), std::forward<_Up>(__u)))) { + swap(std::forward<_Tp>(__t), std::forward<_Up>(__u)); } // 2.2 Otherwise, if `E1` and `E2` are lvalues of array types with equal extent and... @@ -93,7 +93,7 @@ struct __fn { template <__exchangeable _Tp> _LIBCPP_HIDE_FROM_ABI constexpr void operator()(_Tp& __x, _Tp& __y) const noexcept(is_nothrow_move_constructible_v<_Tp> && is_nothrow_move_assignable_v<_Tp>) { - __y = _VSTD::exchange(__x, _VSTD::move(__y)); + __y = std::exchange(__x, std::move(__y)); } }; } // namespace __swap @@ -108,10 +108,10 @@ concept swappable = requires(_Tp& __a, _Tp& __b) { ranges::swap(__a, __b); }; template concept swappable_with = common_reference_with<_Tp, _Up> && requires(_Tp&& __t, _Up&& __u) { - ranges::swap(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Tp>(__t)); - ranges::swap(_VSTD::forward<_Up>(__u), _VSTD::forward<_Up>(__u)); - ranges::swap(_VSTD::forward<_Tp>(__t), _VSTD::forward<_Up>(__u)); - ranges::swap(_VSTD::forward<_Up>(__u), _VSTD::forward<_Tp>(__t)); + ranges::swap(std::forward<_Tp>(__t), std::forward<_Tp>(__t)); + ranges::swap(std::forward<_Up>(__u), std::forward<_Up>(__u)); + ranges::swap(std::forward<_Tp>(__t), std::forward<_Up>(__u)); + ranges::swap(std::forward<_Up>(__u), std::forward<_Tp>(__t)); }; #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__config b/libcxx/include/__config index 3de4d610e8cd..7f66042f9025 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -815,16 +815,16 @@ typedef __char32_t char32_t; # define _LIBCPP_HIDE_FROM_ABI_AFTER_V1 _LIBCPP_HIDE_FROM_ABI # endif -// TODO(LLVM-19): Remove _LIBCPP_INLINE_VISIBILITY, which we're keeping around only to -// ease the renaming for downstreams. +// TODO(LLVM-19): Remove _LIBCPP_INLINE_VISIBILITY and _VSTD, which we're keeping around +// only to ease the renaming for downstreams. # define _LIBCPP_INLINE_VISIBILITY _LIBCPP_HIDE_FROM_ABI +# define _VSTD std // Inline namespaces are available in Clang/GCC/MSVC regardless of C++ dialect. // clang-format off # define _LIBCPP_BEGIN_NAMESPACE_STD namespace _LIBCPP_TYPE_VISIBILITY_DEFAULT std { \ inline namespace _LIBCPP_ABI_NAMESPACE { # define _LIBCPP_END_NAMESPACE_STD }} -# define _VSTD std # define _LIBCPP_BEGIN_NAMESPACE_FILESYSTEM _LIBCPP_BEGIN_NAMESPACE_STD \ inline namespace __fs { namespace filesystem { diff --git a/libcxx/include/__coroutine/coroutine_handle.h b/libcxx/include/__coroutine/coroutine_handle.h index 7a4eff745eb7..4e4e3eb5ba30 100644 --- a/libcxx/include/__coroutine/coroutine_handle.h +++ b/libcxx/include/__coroutine/coroutine_handle.h @@ -117,7 +117,7 @@ public: using _RawPromise = __remove_cv_t<_Promise>; coroutine_handle __tmp; __tmp.__handle_ = - __builtin_coro_promise(_VSTD::addressof(const_cast<_RawPromise&>(__promise)), alignof(_Promise), true); + __builtin_coro_promise(std::addressof(const_cast<_RawPromise&>(__promise)), alignof(_Promise), true); return __tmp; } diff --git a/libcxx/include/__filesystem/directory_entry.h b/libcxx/include/__filesystem/directory_entry.h index cbd0c7dd10dd..fe3cace853d6 100644 --- a/libcxx/include/__filesystem/directory_entry.h +++ b/libcxx/include/__filesystem/directory_entry.h @@ -316,7 +316,7 @@ private: _LIBCPP_HIDE_FROM_ABI void __assign_iter_entry(_Path&& __p, __cached_data __dt) { - __p_ = _VSTD::move(__p); + __p_ = std::move(__p); __data_ = __dt; } @@ -502,7 +502,7 @@ private: class __dir_element_proxy { public: inline _LIBCPP_HIDE_FROM_ABI directory_entry operator*() { - return _VSTD::move(__elem_); + return std::move(__elem_); } private: @@ -510,7 +510,7 @@ private: friend class recursive_directory_iterator; _LIBCPP_HIDE_FROM_ABI explicit __dir_element_proxy(directory_entry const& __e) : __elem_(__e) {} _LIBCPP_HIDE_FROM_ABI __dir_element_proxy(__dir_element_proxy&& __o) - : __elem_(_VSTD::move(__o.__elem_)) {} + : __elem_(std::move(__o.__elem_)) {} directory_entry __elem_; }; diff --git a/libcxx/include/__filesystem/directory_iterator.h b/libcxx/include/__filesystem/directory_iterator.h index 9c611a38cfec..a2a48e593307 100644 --- a/libcxx/include/__filesystem/directory_iterator.h +++ b/libcxx/include/__filesystem/directory_iterator.h @@ -74,7 +74,7 @@ public: directory_iterator& operator=(directory_iterator&& __o) noexcept { // non-default implementation provided to support self-move assign. if (this != &__o) { - __imp_ = _VSTD::move(__o.__imp_); + __imp_ = std::move(__o.__imp_); } return *this; } @@ -156,11 +156,11 @@ _LIBCPP_END_NAMESPACE_FILESYSTEM template <> _LIBCPP_AVAILABILITY_FILESYSTEM_LIBRARY -inline constexpr bool _VSTD::ranges::enable_borrowed_range = true; +inline constexpr bool std::ranges::enable_borrowed_range = true; template <> _LIBCPP_AVAILABILITY_FILESYSTEM_LIBRARY -inline constexpr bool _VSTD::ranges::enable_view = true; +inline constexpr bool std::ranges::enable_view = true; #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__filesystem/filesystem_error.h b/libcxx/include/__filesystem/filesystem_error.h index d6fb2607e759..bfdcc5eaee52 100644 --- a/libcxx/include/__filesystem/filesystem_error.h +++ b/libcxx/include/__filesystem/filesystem_error.h @@ -72,7 +72,7 @@ private: template _LIBCPP_NORETURN inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_FILESYSTEM_LIBRARY void __throw_filesystem_error(_Args&&... __args) { - throw filesystem_error(_VSTD::forward<_Args>(__args)...); + throw filesystem_error(std::forward<_Args>(__args)...); } # else template diff --git a/libcxx/include/__filesystem/path.h b/libcxx/include/__filesystem/path.h index dbe08426da8a..466fa25a38ed 100644 --- a/libcxx/include/__filesystem/path.h +++ b/libcxx/include/__filesystem/path.h @@ -469,11 +469,11 @@ public: _LIBCPP_HIDE_FROM_ABI path() noexcept {} _LIBCPP_HIDE_FROM_ABI path(const path& __p) : __pn_(__p.__pn_) {} _LIBCPP_HIDE_FROM_ABI path(path&& __p) noexcept - : __pn_(_VSTD::move(__p.__pn_)) {} + : __pn_(std::move(__p.__pn_)) {} _LIBCPP_HIDE_FROM_ABI path(string_type&& __s, format = format::auto_format) noexcept - : __pn_(_VSTD::move(__s)) {} + : __pn_(std::move(__s)) {} template > _LIBCPP_HIDE_FROM_ABI @@ -511,19 +511,19 @@ public: _LIBCPP_HIDE_FROM_ABI path& operator=(path&& __p) noexcept { - __pn_ = _VSTD::move(__p.__pn_); + __pn_ = std::move(__p.__pn_); return *this; } _LIBCPP_HIDE_FROM_ABI path& operator=(string_type&& __s) noexcept { - __pn_ = _VSTD::move(__s); + __pn_ = std::move(__s); return *this; } _LIBCPP_HIDE_FROM_ABI path& assign(string_type&& __s) noexcept { - __pn_ = _VSTD::move(__s); + __pn_ = std::move(__s); return *this; } @@ -709,7 +709,7 @@ public: _LIBCPP_HIDE_FROM_ABI path& make_preferred() { #if defined(_LIBCPP_WIN32API) - _VSTD::replace(__pn_.begin(), __pn_.end(), L'/', L'\\'); + std::replace(__pn_.begin(), __pn_.end(), L'/', L'\\'); #endif return *this; } @@ -778,13 +778,13 @@ public: _LIBCPP_HIDE_FROM_ABI operator string_type() const { return __pn_; } #if defined(_LIBCPP_WIN32API) - _LIBCPP_HIDE_FROM_ABI _VSTD::wstring wstring() const { return __pn_; } + _LIBCPP_HIDE_FROM_ABI std::wstring wstring() const { return __pn_; } _LIBCPP_HIDE_FROM_ABI - _VSTD::wstring generic_wstring() const { - _VSTD::wstring __s; + std::wstring generic_wstring() const { + std::wstring __s; __s.resize(__pn_.size()); - _VSTD::replace_copy(__pn_.begin(), __pn_.end(), __s.begin(), '\\', '/'); + std::replace_copy(__pn_.begin(), __pn_.end(), __s.begin(), '\\', '/'); return __s; } @@ -801,7 +801,7 @@ public: return __s; } - _LIBCPP_HIDE_FROM_ABI _VSTD::string string() const { + _LIBCPP_HIDE_FROM_ABI std::string string() const { return string(); } _LIBCPP_HIDE_FROM_ABI __u8_string u8string() const { @@ -812,10 +812,10 @@ public: return __s; } - _LIBCPP_HIDE_FROM_ABI _VSTD::u16string u16string() const { + _LIBCPP_HIDE_FROM_ABI std::u16string u16string() const { return string(); } - _LIBCPP_HIDE_FROM_ABI _VSTD::u32string u32string() const { + _LIBCPP_HIDE_FROM_ABI std::u32string u32string() const { return string(); } @@ -830,28 +830,28 @@ public: // Note: This (and generic_u8string below) is slightly suboptimal as // it iterates twice over the string; once to convert it to the right // character type, and once to replace path delimiters. - _VSTD::replace(__s.begin(), __s.end(), + std::replace(__s.begin(), __s.end(), static_cast<_ECharT>('\\'), static_cast<_ECharT>('/')); return __s; } - _LIBCPP_HIDE_FROM_ABI _VSTD::string generic_string() const { return generic_string(); } - _LIBCPP_HIDE_FROM_ABI _VSTD::u16string generic_u16string() const { return generic_string(); } - _LIBCPP_HIDE_FROM_ABI _VSTD::u32string generic_u32string() const { return generic_string(); } + _LIBCPP_HIDE_FROM_ABI std::string generic_string() const { return generic_string(); } + _LIBCPP_HIDE_FROM_ABI std::u16string generic_u16string() const { return generic_string(); } + _LIBCPP_HIDE_FROM_ABI std::u32string generic_u32string() const { return generic_string(); } _LIBCPP_HIDE_FROM_ABI __u8_string generic_u8string() const { __u8_string __s = u8string(); - _VSTD::replace(__s.begin(), __s.end(), '\\', '/'); + std::replace(__s.begin(), __s.end(), '\\', '/'); return __s; } #endif /* !_LIBCPP_HAS_NO_LOCALIZATION */ #else /* _LIBCPP_WIN32API */ - _LIBCPP_HIDE_FROM_ABI _VSTD::string string() const { return __pn_; } + _LIBCPP_HIDE_FROM_ABI std::string string() const { return __pn_; } #ifndef _LIBCPP_HAS_NO_CHAR8_T - _LIBCPP_HIDE_FROM_ABI _VSTD::u8string u8string() const { return _VSTD::u8string(__pn_.begin(), __pn_.end()); } + _LIBCPP_HIDE_FROM_ABI std::u8string u8string() const { return std::u8string(__pn_.begin(), __pn_.end()); } #else - _LIBCPP_HIDE_FROM_ABI _VSTD::string u8string() const { return __pn_; } + _LIBCPP_HIDE_FROM_ABI std::string u8string() const { return __pn_; } #endif #if !defined(_LIBCPP_HAS_NO_LOCALIZATION) @@ -869,24 +869,24 @@ public: } #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - _LIBCPP_HIDE_FROM_ABI _VSTD::wstring wstring() const { + _LIBCPP_HIDE_FROM_ABI std::wstring wstring() const { return string(); } #endif - _LIBCPP_HIDE_FROM_ABI _VSTD::u16string u16string() const { + _LIBCPP_HIDE_FROM_ABI std::u16string u16string() const { return string(); } - _LIBCPP_HIDE_FROM_ABI _VSTD::u32string u32string() const { + _LIBCPP_HIDE_FROM_ABI std::u32string u32string() const { return string(); } #endif /* !_LIBCPP_HAS_NO_LOCALIZATION */ // generic format observers - _LIBCPP_HIDE_FROM_ABI _VSTD::string generic_string() const { return __pn_; } + _LIBCPP_HIDE_FROM_ABI std::string generic_string() const { return __pn_; } #ifndef _LIBCPP_HAS_NO_CHAR8_T - _LIBCPP_HIDE_FROM_ABI _VSTD::u8string generic_u8string() const { return _VSTD::u8string(__pn_.begin(), __pn_.end()); } + _LIBCPP_HIDE_FROM_ABI std::u8string generic_u8string() const { return std::u8string(__pn_.begin(), __pn_.end()); } #else - _LIBCPP_HIDE_FROM_ABI _VSTD::string generic_u8string() const { return __pn_; } + _LIBCPP_HIDE_FROM_ABI std::string generic_u8string() const { return __pn_; } #endif #if !defined(_LIBCPP_HAS_NO_LOCALIZATION) @@ -899,10 +899,10 @@ public: } #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - _LIBCPP_HIDE_FROM_ABI _VSTD::wstring generic_wstring() const { return string(); } + _LIBCPP_HIDE_FROM_ABI std::wstring generic_wstring() const { return string(); } #endif - _LIBCPP_HIDE_FROM_ABI _VSTD::u16string generic_u16string() const { return string(); } - _LIBCPP_HIDE_FROM_ABI _VSTD::u32string generic_u32string() const { return string(); } + _LIBCPP_HIDE_FROM_ABI std::u16string generic_u16string() const { return string(); } + _LIBCPP_HIDE_FROM_ABI std::u32string generic_u32string() const { return string(); } #endif /* !_LIBCPP_HAS_NO_LOCALIZATION */ #endif /* !_LIBCPP_WIN32API */ @@ -1039,7 +1039,7 @@ public: _LIBCPP_HIDE_FROM_ABI friend basic_ostream<_CharT, _Traits>& operator<<(basic_ostream<_CharT, _Traits>& __os, const path& __p) { - __os << _VSTD::__quoted(__p.native()); + __os << std::__quoted(__p.native()); return __os; } @@ -1048,7 +1048,7 @@ public: _LIBCPP_HIDE_FROM_ABI friend basic_ostream<_CharT, _Traits>& operator<<(basic_ostream<_CharT, _Traits>& __os, const path& __p) { - __os << _VSTD::__quoted(__p.string<_CharT, _Traits>()); + __os << std::__quoted(__p.string<_CharT, _Traits>()); return __os; } @@ -1056,7 +1056,7 @@ public: _LIBCPP_HIDE_FROM_ABI friend basic_istream<_CharT, _Traits>& operator>>(basic_istream<_CharT, _Traits>& __is, path& __p) { basic_string<_CharT, _Traits> __tmp; - __is >> _VSTD::__quoted(__tmp); + __is >> std::__quoted(__tmp); __p = __tmp; return __is; } diff --git a/libcxx/include/__filesystem/recursive_directory_iterator.h b/libcxx/include/__filesystem/recursive_directory_iterator.h index ee4e61b580ed..e0aac636db8c 100644 --- a/libcxx/include/__filesystem/recursive_directory_iterator.h +++ b/libcxx/include/__filesystem/recursive_directory_iterator.h @@ -72,7 +72,7 @@ public: operator=(recursive_directory_iterator&& __o) noexcept { // non-default implementation provided to support self-move assign. if (this != &__o) { - __imp_ = _VSTD::move(__o.__imp_); + __imp_ = std::move(__o.__imp_); __rec_ = __o.__rec_; } return *this; @@ -170,11 +170,11 @@ _LIBCPP_END_NAMESPACE_FILESYSTEM template <> _LIBCPP_AVAILABILITY_FILESYSTEM_LIBRARY -inline constexpr bool _VSTD::ranges::enable_borrowed_range = true; +inline constexpr bool std::ranges::enable_borrowed_range = true; template <> _LIBCPP_AVAILABILITY_FILESYSTEM_LIBRARY -inline constexpr bool _VSTD::ranges::enable_view = true; +inline constexpr bool std::ranges::enable_view = true; #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__filesystem/u8path.h b/libcxx/include/__filesystem/u8path.h index 048e1b5235ce..a79007e969ca 100644 --- a/libcxx/include/__filesystem/u8path.h +++ b/libcxx/include/__filesystem/u8path.h @@ -46,7 +46,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_DEPRECATED_WITH_CHAR8_T #if defined(_LIBCPP_WIN32API) string __tmp(__f, __l); using _CVT = __widen_from_utf8; - _VSTD::wstring __w; + std::wstring __w; __w.reserve(__tmp.size()); _CVT()(back_inserter(__w), __tmp.data(), __tmp.data() + __tmp.size()); return path(__w); @@ -72,7 +72,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_DEPRECATED_WITH_CHAR8_T for (; *__f != __sentinel; ++__f) __tmp.push_back(*__f); using _CVT = __widen_from_utf8; - _VSTD::wstring __w; + std::wstring __w; __w.reserve(__tmp.size()); _CVT()(back_inserter(__w), __tmp.data(), __tmp.data() + __tmp.size()); return path(__w); @@ -92,7 +92,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_DEPRECATED_WITH_CHAR8_T "'char' or 'char8_t'"); #if defined(_LIBCPP_WIN32API) using _Traits = __is_pathable<_Source>; - return u8path(_VSTD::__unwrap_iter(_Traits::__range_begin(__s)), _VSTD::__unwrap_iter(_Traits::__range_end(__s))); + return u8path(std::__unwrap_iter(_Traits::__range_begin(__s)), std::__unwrap_iter(_Traits::__range_end(__s))); #else return path(__s); #endif diff --git a/libcxx/include/__format/buffer.h b/libcxx/include/__format/buffer.h index c0502971ce12..8aa58d6464bb 100644 --- a/libcxx/include/__format/buffer.h +++ b/libcxx/include/__format/buffer.h @@ -108,7 +108,7 @@ public: __flush_on_overflow(__n); if (__n < __capacity_) { // push_back requires the buffer to have room for at least one character (so use <). - _VSTD::copy_n(__str.data(), __n, _VSTD::addressof(__ptr_[__size_])); + std::copy_n(__str.data(), __n, std::addressof(__ptr_[__size_])); __size_ += __n; return; } @@ -118,8 +118,8 @@ public: _LIBCPP_ASSERT_UNCATEGORIZED(__size_ == 0, "the buffer should be flushed by __flush_on_overflow"); const _InCharT* __first = __str.data(); do { - size_t __chunk = _VSTD::min(__n, __capacity_); - _VSTD::copy_n(__first, __chunk, _VSTD::addressof(__ptr_[__size_])); + size_t __chunk = std::min(__n, __capacity_); + std::copy_n(__first, __chunk, std::addressof(__ptr_[__size_])); __size_ = __chunk; __first += __chunk; __n -= __chunk; @@ -137,7 +137,7 @@ public: size_t __n = static_cast(__last - __first); __flush_on_overflow(__n); if (__n < __capacity_) { // push_back requires the buffer to have room for at least one character (so use <). - _VSTD::transform(__first, __last, _VSTD::addressof(__ptr_[__size_]), _VSTD::move(__operation)); + std::transform(__first, __last, std::addressof(__ptr_[__size_]), std::move(__operation)); __size_ += __n; return; } @@ -146,8 +146,8 @@ public: // Transform the data in "__capacity_" sized chunks. _LIBCPP_ASSERT_UNCATEGORIZED(__size_ == 0, "the buffer should be flushed by __flush_on_overflow"); do { - size_t __chunk = _VSTD::min(__n, __capacity_); - _VSTD::transform(__first, __first + __chunk, _VSTD::addressof(__ptr_[__size_]), __operation); + size_t __chunk = std::min(__n, __capacity_); + std::transform(__first, __first + __chunk, std::addressof(__ptr_[__size_]), __operation); __size_ = __chunk; __first += __chunk; __n -= __chunk; @@ -159,7 +159,7 @@ public: _LIBCPP_HIDE_FROM_ABI void __fill(size_t __n, _CharT __value) { __flush_on_overflow(__n); if (__n < __capacity_) { // push_back requires the buffer to have room for at least one character (so use <). - _VSTD::fill_n(_VSTD::addressof(__ptr_[__size_]), __n, __value); + std::fill_n(std::addressof(__ptr_[__size_]), __n, __value); __size_ += __n; return; } @@ -168,8 +168,8 @@ public: // Fill the buffer in "__capacity_" sized chunks. _LIBCPP_ASSERT_UNCATEGORIZED(__size_ == 0, "the buffer should be flushed by __flush_on_overflow"); do { - size_t __chunk = _VSTD::min(__n, __capacity_); - _VSTD::fill_n(_VSTD::addressof(__ptr_[__size_]), __chunk, __value); + size_t __chunk = std::min(__n, __capacity_); + std::fill_n(std::addressof(__ptr_[__size_]), __chunk, __value); __size_ = __chunk; __n -= __chunk; __flush(); @@ -282,7 +282,7 @@ template class _LIBCPP_TEMPLATE_VIS __writer_iterator { public: _LIBCPP_HIDE_FROM_ABI explicit __writer_iterator(_OutIt __out_it) - : __out_it_{_VSTD::move(__out_it)} {} + : __out_it_{std::move(__out_it)} {} _LIBCPP_HIDE_FROM_ABI _OutIt __out_it() && { return std::move(__out_it_); } @@ -359,12 +359,12 @@ requires(output_iterator<_OutIt, const _CharT&>) class _LIBCPP_TEMPLATE_VIS public: _LIBCPP_HIDE_FROM_ABI explicit __format_buffer(_OutIt __out_it) requires(same_as<_Storage, __internal_storage<_CharT>>) - : __output_(__storage_.__begin(), __storage_.__buffer_size, this), __writer_(_VSTD::move(__out_it)) {} + : __output_(__storage_.__begin(), __storage_.__buffer_size, this), __writer_(std::move(__out_it)) {} _LIBCPP_HIDE_FROM_ABI explicit __format_buffer(_OutIt __out_it) requires( same_as<_Storage, __direct_storage<_CharT>>) - : __output_(_VSTD::__unwrap_iter(__out_it), size_t(-1), this), - __writer_(_VSTD::move(__out_it)) {} + : __output_(std::__unwrap_iter(__out_it), size_t(-1), this), + __writer_(std::move(__out_it)) {} _LIBCPP_HIDE_FROM_ABI auto __make_output_iterator() { return __output_.__make_output_iterator(); } @@ -372,7 +372,7 @@ public: _LIBCPP_HIDE_FROM_ABI _OutIt __out_it() && { __output_.__flush(); - return _VSTD::move(__writer_).__out_it(); + return std::move(__writer_).__out_it(); } private: @@ -411,11 +411,11 @@ struct _LIBCPP_TEMPLATE_VIS __format_to_n_buffer_base { public: _LIBCPP_HIDE_FROM_ABI explicit __format_to_n_buffer_base(_OutIt __out_it, _Size __max_size) - : __writer_(_VSTD::move(__out_it)), __max_size_(_VSTD::max(_Size(0), __max_size)) {} + : __writer_(std::move(__out_it)), __max_size_(std::max(_Size(0), __max_size)) {} _LIBCPP_HIDE_FROM_ABI void __flush(_CharT* __ptr, size_t __n) { if (_Size(__size_) <= __max_size_) - __writer_.__flush(__ptr, _VSTD::min(_Size(__n), __max_size_ - __size_)); + __writer_.__flush(__ptr, std::min(_Size(__n), __max_size_ - __size_)); __size_ += __n; } @@ -441,8 +441,8 @@ class _LIBCPP_TEMPLATE_VIS __format_to_n_buffer_base<_OutIt, _CharT, true> { public: _LIBCPP_HIDE_FROM_ABI explicit __format_to_n_buffer_base(_OutIt __out_it, _Size __max_size) - : __output_(_VSTD::__unwrap_iter(__out_it), __max_size, this), - __writer_(_VSTD::move(__out_it)), + : __output_(std::__unwrap_iter(__out_it), __max_size, this), + __writer_(std::move(__out_it)), __max_size_(__max_size) { if (__max_size <= 0) [[unlikely]] __output_.__reset(__storage_.__begin(), __storage_.__buffer_size); @@ -466,7 +466,7 @@ public: } else if (__size_ < __max_size_) { // Copies a part of the internal buffer to the output up to n characters. // See __output_buffer<_CharT>::__flush_on_overflow for more information. - _Size __s = _VSTD::min(_Size(__n), __max_size_ - __size_); + _Size __s = std::min(_Size(__n), __max_size_ - __size_); std::copy_n(__ptr, __s, __writer_.__out_it()); __writer_.__flush(__ptr, __s); } @@ -493,12 +493,12 @@ struct _LIBCPP_TEMPLATE_VIS __format_to_n_buffer final public: _LIBCPP_HIDE_FROM_ABI explicit __format_to_n_buffer(_OutIt __out_it, _Size __max_size) - : _Base(_VSTD::move(__out_it), __max_size) {} + : _Base(std::move(__out_it), __max_size) {} _LIBCPP_HIDE_FROM_ABI auto __make_output_iterator() { return this->__output_.__make_output_iterator(); } _LIBCPP_HIDE_FROM_ABI format_to_n_result<_OutIt> __result() && { this->__output_.__flush(); - return {_VSTD::move(this->__writer_).__out_it(), this->__size_}; + return {std::move(this->__writer_).__out_it(), this->__size_}; } }; diff --git a/libcxx/include/__format/escaped_output_table.h b/libcxx/include/__format/escaped_output_table.h index 222847e6af67..495a2fbc7b03 100644 --- a/libcxx/include/__format/escaped_output_table.h +++ b/libcxx/include/__format/escaped_output_table.h @@ -75,6 +75,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD #if _LIBCPP_STD_VER >= 23 namespace __escaped_output_table { +// clang-format off /// The entries of the characters to escape in format's debug string. /// @@ -1029,6 +1030,7 @@ inline constexpr uint32_t __unallocated_region_lower_bound = 0x000323b0; return __code_point <= __upper_bound; } +// clang-format on } // namespace __escaped_output_table #endif //_LIBCPP_STD_VER >= 23 diff --git a/libcxx/include/__format/extended_grapheme_cluster_table.h b/libcxx/include/__format/extended_grapheme_cluster_table.h index bd6d39fdc7c2..9616dfecd604 100644 --- a/libcxx/include/__format/extended_grapheme_cluster_table.h +++ b/libcxx/include/__format/extended_grapheme_cluster_table.h @@ -124,6 +124,7 @@ enum class __property : uint8_t { /// this approach uses less space for the data and is about 4% faster in the /// following benchmark. /// libcxx/benchmarks/std_format_spec_string_unicode.bench.cpp +// clang-format off inline constexpr uint32_t __entries[1496] = { 0x00000091, 0x00005005, @@ -1621,6 +1622,7 @@ inline constexpr uint32_t __entries[1496] = { 0x707787f1, 0x707b87f1, 0x707f80f1}; +// clang-format on /// Returns the extended grapheme cluster bondary property of a code point. [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr __property __get_property(const char32_t __code_point) noexcept { diff --git a/libcxx/include/__format/format_arg.h b/libcxx/include/__format/format_arg.h index ca06107f551d..cc6be7a25660 100644 --- a/libcxx/include/__format/format_arg.h +++ b/libcxx/include/__format/format_arg.h @@ -100,45 +100,45 @@ _LIBCPP_HIDE_FROM_ABI decltype(auto) __visit_format_arg(_Visitor&& __vis, basic_format_arg<_Context> __arg) { switch (__arg.__type_) { case __format::__arg_t::__none: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__monostate_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__monostate_); case __format::__arg_t::__boolean: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__boolean_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__boolean_); case __format::__arg_t::__char_type: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__char_type_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__char_type_); case __format::__arg_t::__int: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__int_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__int_); case __format::__arg_t::__long_long: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__long_long_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__long_long_); case __format::__arg_t::__i128: # ifndef _LIBCPP_HAS_NO_INT128 - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__i128_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__i128_); # else __libcpp_unreachable(); # endif case __format::__arg_t::__unsigned: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__unsigned_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__unsigned_); case __format::__arg_t::__unsigned_long_long: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__unsigned_long_long_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__unsigned_long_long_); case __format::__arg_t::__u128: # ifndef _LIBCPP_HAS_NO_INT128 - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__u128_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__u128_); # else __libcpp_unreachable(); # endif case __format::__arg_t::__float: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__float_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__float_); case __format::__arg_t::__double: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__double_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__double_); case __format::__arg_t::__long_double: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__long_double_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__long_double_); case __format::__arg_t::__const_char_type_ptr: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__const_char_type_ptr_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__const_char_type_ptr_); case __format::__arg_t::__string_view: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__string_view_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__string_view_); case __format::__arg_t::__ptr: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), __arg.__value_.__ptr_); + return std::invoke(std::forward<_Visitor>(__vis), __arg.__value_.__ptr_); case __format::__arg_t::__handle: - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), + return std::invoke(std::forward<_Visitor>(__vis), typename basic_format_arg<_Context>::handle{__arg.__value_.__handle_}); } @@ -158,7 +158,7 @@ public: struct __handle { template _LIBCPP_HIDE_FROM_ABI explicit __handle(_Tp& __v) noexcept - : __ptr_(_VSTD::addressof(__v)), + : __ptr_(std::addressof(__v)), __format_([](basic_format_parse_context<_CharT>& __parse_ctx, _Context& __ctx, const void* __ptr) { using _Dp = remove_const_t<_Tp>; using _Qp = conditional_t<__formattable_with, const _Dp, _Dp>; @@ -278,16 +278,16 @@ visit_format_arg(_Visitor&& __vis, basic_format_arg<_Context> __arg) { # ifndef _LIBCPP_HAS_NO_INT128 case __format::__arg_t::__i128: { typename __basic_format_arg_value<_Context>::__handle __h{__arg.__value_.__i128_}; - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), typename basic_format_arg<_Context>::handle{__h}); + return std::invoke(std::forward<_Visitor>(__vis), typename basic_format_arg<_Context>::handle{__h}); } case __format::__arg_t::__u128: { typename __basic_format_arg_value<_Context>::__handle __h{__arg.__value_.__u128_}; - return _VSTD::invoke(_VSTD::forward<_Visitor>(__vis), typename basic_format_arg<_Context>::handle{__h}); + return std::invoke(std::forward<_Visitor>(__vis), typename basic_format_arg<_Context>::handle{__h}); } # endif default: - return _VSTD::__visit_format_arg(_VSTD::forward<_Visitor>(__vis), __arg); + return std::__visit_format_arg(std::forward<_Visitor>(__vis), __arg); } } diff --git a/libcxx/include/__format/format_context.h b/libcxx/include/__format/format_context.h index 9d50cee2483f..4e3d15ec862e 100644 --- a/libcxx/include/__format/format_context.h +++ b/libcxx/include/__format/format_context.h @@ -54,8 +54,8 @@ _LIBCPP_HIDE_FROM_ABI basic_format_context<_OutIt, _CharT> __format_context_create( _OutIt __out_it, basic_format_args> __args, - optional<_VSTD::locale>&& __loc = nullopt) { - return _VSTD::basic_format_context(_VSTD::move(__out_it), __args, _VSTD::move(__loc)); + optional&& __loc = nullopt) { + return std::basic_format_context(std::move(__out_it), __args, std::move(__loc)); } #else template @@ -63,7 +63,7 @@ _LIBCPP_HIDE_FROM_ABI basic_format_context<_OutIt, _CharT> __format_context_create( _OutIt __out_it, basic_format_args> __args) { - return _VSTD::basic_format_context(_VSTD::move(__out_it), __args); + return std::basic_format_context(std::move(__out_it), __args); } #endif @@ -95,9 +95,9 @@ public: return __args_.get(__id); } #ifndef _LIBCPP_HAS_NO_LOCALIZATION - _LIBCPP_HIDE_FROM_ABI _VSTD::locale locale() { + _LIBCPP_HIDE_FROM_ABI std::locale locale() { if (!__loc_) - __loc_ = _VSTD::locale{}; + __loc_ = std::locale{}; return *__loc_; } #endif @@ -118,20 +118,20 @@ private: // locale() is called and the optional has no value the value will be created. // This allows the implementation to lazily create the locale. // TODO FMT Validate whether lazy creation is the best solution. - optional<_VSTD::locale> __loc_; + optional __loc_; template friend _LIBCPP_HIDE_FROM_ABI basic_format_context<_OtherOutIt, _OtherCharT> __format_context_create(_OtherOutIt, basic_format_args>, - optional<_VSTD::locale>&&); + optional&&); // Note: the Standard doesn't specify the required constructors. _LIBCPP_HIDE_FROM_ABI explicit basic_format_context(_OutIt __out_it, basic_format_args __args, - optional<_VSTD::locale>&& __loc) - : __out_it_(_VSTD::move(__out_it)), __args_(__args), - __loc_(_VSTD::move(__loc)) {} + optional&& __loc) + : __out_it_(std::move(__out_it)), __args_(__args), + __loc_(std::move(__loc)) {} #else template friend _LIBCPP_HIDE_FROM_ABI basic_format_context<_OtherOutIt, _OtherCharT> @@ -140,7 +140,7 @@ private: _LIBCPP_HIDE_FROM_ABI explicit basic_format_context(_OutIt __out_it, basic_format_args __args) - : __out_it_(_VSTD::move(__out_it)), __args_(__args) {} + : __out_it_(std::move(__out_it)), __args_(__args) {} #endif }; @@ -198,7 +198,7 @@ public: return __arg_(__ctx_, __id); } # ifndef _LIBCPP_HAS_NO_LOCALIZATION - _LIBCPP_HIDE_FROM_ABI _VSTD::locale locale() { return __loc_(__ctx_); } + _LIBCPP_HIDE_FROM_ABI std::locale locale() { return __loc_(__ctx_); } # endif _LIBCPP_HIDE_FROM_ABI iterator out() { return std::move(__out_it_); } _LIBCPP_HIDE_FROM_ABI void advance_to(iterator __it) { __out_it_ = std::move(__it); } diff --git a/libcxx/include/__format/format_functions.h b/libcxx/include/__format/format_functions.h index d4d36d68a98c..164592d2ec15 100644 --- a/libcxx/include/__format/format_functions.h +++ b/libcxx/include/__format/format_functions.h @@ -64,14 +64,14 @@ using wformat_args = basic_format_args; template _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI __format_arg_store<_Context, _Args...> make_format_args(_Args&&... __args) { - return _VSTD::__format_arg_store<_Context, _Args...>(__args...); + return std::__format_arg_store<_Context, _Args...>(__args...); } # ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS template _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI __format_arg_store make_wformat_args(_Args&&... __args) { - return _VSTD::__format_arg_store(__args...); + return std::__format_arg_store(__args...); } # endif @@ -271,7 +271,7 @@ __handle_replacement_field(_Iterator __begin, _Iterator __end, else if (__parse) __format::__compile_time_visit_format_arg(__parse_ctx, __ctx, __type); } else - _VSTD::__visit_format_arg( + std::__visit_format_arg( [&](auto __arg) { if constexpr (same_as) std::__throw_format_error("The argument index value is too large for the number of arguments supplied"); @@ -310,7 +310,7 @@ __vformat_to(_ParseCtx&& __parse_ctx, _Ctx&& __ctx) { std::__throw_format_error("The format string terminates at a '{'"); if (*__begin != _CharT('{')) [[likely]] { - __ctx.advance_to(_VSTD::move(__out_it)); + __ctx.advance_to(std::move(__out_it)); __begin = __format::__handle_replacement_field(__begin, __end, __parse_ctx, __ctx); __out_it = __ctx.out(); @@ -410,13 +410,13 @@ requires(output_iterator<_OutIt, const _CharT&>) _LIBCPP_HIDE_FROM_ABI _OutIt _OutIt __out_it, basic_string_view<_CharT> __fmt, basic_format_args> __args) { if constexpr (same_as<_OutIt, _FormatOutIt>) - return _VSTD::__format::__vformat_to(basic_format_parse_context{__fmt, __args.__size()}, - _VSTD::__format_context_create(_VSTD::move(__out_it), __args)); + return std::__format::__vformat_to(basic_format_parse_context{__fmt, __args.__size()}, + std::__format_context_create(std::move(__out_it), __args)); else { - __format::__format_buffer<_OutIt, _CharT> __buffer{_VSTD::move(__out_it)}; - _VSTD::__format::__vformat_to(basic_format_parse_context{__fmt, __args.__size()}, - _VSTD::__format_context_create(__buffer.__make_output_iterator(), __args)); - return _VSTD::move(__buffer).__out_it(); + __format::__format_buffer<_OutIt, _CharT> __buffer{std::move(__out_it)}; + std::__format::__vformat_to(basic_format_parse_context{__fmt, __args.__size()}, + std::__format_context_create(__buffer.__make_output_iterator(), __args)); + return std::move(__buffer).__out_it(); } } @@ -426,30 +426,30 @@ requires(output_iterator<_OutIt, const _CharT&>) _LIBCPP_HIDE_FROM_ABI _OutIt template _OutIt> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt vformat_to(_OutIt __out_it, string_view __fmt, format_args __args) { - return _VSTD::__vformat_to(_VSTD::move(__out_it), __fmt, __args); + return std::__vformat_to(std::move(__out_it), __fmt, __args); } #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS template _OutIt> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt vformat_to(_OutIt __out_it, wstring_view __fmt, wformat_args __args) { - return _VSTD::__vformat_to(_VSTD::move(__out_it), __fmt, __args); + return std::__vformat_to(std::move(__out_it), __fmt, __args); } #endif template _OutIt, class... _Args> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt format_to(_OutIt __out_it, format_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::vformat_to(_VSTD::move(__out_it), __fmt.get(), - _VSTD::make_format_args(__args...)); + return std::vformat_to(std::move(__out_it), __fmt.get(), + std::make_format_args(__args...)); } #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS template _OutIt, class... _Args> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt format_to(_OutIt __out_it, wformat_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::vformat_to(_VSTD::move(__out_it), __fmt.get(), - _VSTD::make_wformat_args(__args...)); + return std::vformat_to(std::move(__out_it), __fmt.get(), + std::make_wformat_args(__args...)); } #endif @@ -459,7 +459,7 @@ template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE inline _LIBCPP_HIDE_FROM_ABI string vformat(string_view __fmt, format_args __args) { string __res; - _VSTD::vformat_to(_VSTD::back_inserter(__res), __fmt, __args); + std::vformat_to(std::back_inserter(__res), __fmt, __args); return __res; } @@ -470,7 +470,7 @@ template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE inline _LIBCPP_HIDE_FROM_ABI wstring vformat(wstring_view __fmt, wformat_args __args) { wstring __res; - _VSTD::vformat_to(_VSTD::back_inserter(__res), __fmt, __args); + std::vformat_to(std::back_inserter(__res), __fmt, __args); return __res; } # endif @@ -478,14 +478,14 @@ vformat(wstring_view __fmt, wformat_args __args) { template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI string format(format_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::vformat(__fmt.get(), _VSTD::make_format_args(__args...)); + return std::vformat(__fmt.get(), std::make_format_args(__args...)); } # ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI wstring format(wformat_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::vformat(__fmt.get(), _VSTD::make_wformat_args(__args...)); + return std::vformat(__fmt.get(), std::make_wformat_args(__args...)); } # endif @@ -493,16 +493,16 @@ template _LIBCPP_HIDE_FROM_ABI format_to_n_result<_OutIt> __vformat_to_n(_OutIt __out_it, iter_difference_t<_OutIt> __n, basic_string_view<_CharT> __fmt, basic_format_args<_Context> __args) { - __format::__format_to_n_buffer<_OutIt, _CharT> __buffer{_VSTD::move(__out_it), __n}; - _VSTD::__format::__vformat_to(basic_format_parse_context{__fmt, __args.__size()}, - _VSTD::__format_context_create(__buffer.__make_output_iterator(), __args)); - return _VSTD::move(__buffer).__result(); + __format::__format_to_n_buffer<_OutIt, _CharT> __buffer{std::move(__out_it), __n}; + std::__format::__vformat_to(basic_format_parse_context{__fmt, __args.__size()}, + std::__format_context_create(__buffer.__make_output_iterator(), __args)); + return std::move(__buffer).__result(); } template _OutIt, class... _Args> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI format_to_n_result<_OutIt> format_to_n(_OutIt __out_it, iter_difference_t<_OutIt> __n, format_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::__vformat_to_n(_VSTD::move(__out_it), __n, __fmt.get(), _VSTD::make_format_args(__args...)); + return std::__vformat_to_n(std::move(__out_it), __n, __fmt.get(), std::make_format_args(__args...)); } #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS @@ -510,29 +510,29 @@ template _OutIt, class... _Args> _LIBCPP_HIDE_FROM_ABI format_to_n_result<_OutIt> format_to_n(_OutIt __out_it, iter_difference_t<_OutIt> __n, wformat_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::__vformat_to_n(_VSTD::move(__out_it), __n, __fmt.get(), _VSTD::make_wformat_args(__args...)); + return std::__vformat_to_n(std::move(__out_it), __n, __fmt.get(), std::make_wformat_args(__args...)); } #endif template _LIBCPP_HIDE_FROM_ABI size_t __vformatted_size(basic_string_view<_CharT> __fmt, auto __args) { __format::__formatted_size_buffer<_CharT> __buffer; - _VSTD::__format::__vformat_to(basic_format_parse_context{__fmt, __args.__size()}, - _VSTD::__format_context_create(__buffer.__make_output_iterator(), __args)); - return _VSTD::move(__buffer).__result(); + std::__format::__vformat_to(basic_format_parse_context{__fmt, __args.__size()}, + std::__format_context_create(__buffer.__make_output_iterator(), __args)); + return std::move(__buffer).__result(); } template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI size_t formatted_size(format_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::__vformatted_size(__fmt.get(), basic_format_args{_VSTD::make_format_args(__args...)}); + return std::__vformatted_size(__fmt.get(), basic_format_args{std::make_format_args(__args...)}); } # ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI size_t formatted_size(wformat_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::__vformatted_size(__fmt.get(), basic_format_args{_VSTD::make_wformat_args(__args...)}); + return std::__vformatted_size(__fmt.get(), basic_format_args{std::make_wformat_args(__args...)}); } # endif @@ -544,22 +544,22 @@ requires(output_iterator<_OutIt, const _CharT&>) _LIBCPP_HIDE_FROM_ABI _OutIt _OutIt __out_it, locale __loc, basic_string_view<_CharT> __fmt, basic_format_args> __args) { if constexpr (same_as<_OutIt, _FormatOutIt>) - return _VSTD::__format::__vformat_to( + return std::__format::__vformat_to( basic_format_parse_context{__fmt, __args.__size()}, - _VSTD::__format_context_create(_VSTD::move(__out_it), __args, _VSTD::move(__loc))); + std::__format_context_create(std::move(__out_it), __args, std::move(__loc))); else { - __format::__format_buffer<_OutIt, _CharT> __buffer{_VSTD::move(__out_it)}; - _VSTD::__format::__vformat_to( + __format::__format_buffer<_OutIt, _CharT> __buffer{std::move(__out_it)}; + std::__format::__vformat_to( basic_format_parse_context{__fmt, __args.__size()}, - _VSTD::__format_context_create(__buffer.__make_output_iterator(), __args, _VSTD::move(__loc))); - return _VSTD::move(__buffer).__out_it(); + std::__format_context_create(__buffer.__make_output_iterator(), __args, std::move(__loc))); + return std::move(__buffer).__out_it(); } } template _OutIt> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt vformat_to( _OutIt __out_it, locale __loc, string_view __fmt, format_args __args) { - return _VSTD::__vformat_to(_VSTD::move(__out_it), _VSTD::move(__loc), __fmt, + return std::__vformat_to(std::move(__out_it), std::move(__loc), __fmt, __args); } @@ -567,7 +567,7 @@ _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt vformat_to( template _OutIt> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt vformat_to( _OutIt __out_it, locale __loc, wstring_view __fmt, wformat_args __args) { - return _VSTD::__vformat_to(_VSTD::move(__out_it), _VSTD::move(__loc), __fmt, + return std::__vformat_to(std::move(__out_it), std::move(__loc), __fmt, __args); } #endif @@ -575,16 +575,16 @@ _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt vformat_to( template _OutIt, class... _Args> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt format_to(_OutIt __out_it, locale __loc, format_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::vformat_to(_VSTD::move(__out_it), _VSTD::move(__loc), __fmt.get(), - _VSTD::make_format_args(__args...)); + return std::vformat_to(std::move(__out_it), std::move(__loc), __fmt.get(), + std::make_format_args(__args...)); } #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS template _OutIt, class... _Args> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _OutIt format_to(_OutIt __out_it, locale __loc, wformat_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::vformat_to(_VSTD::move(__out_it), _VSTD::move(__loc), __fmt.get(), - _VSTD::make_wformat_args(__args...)); + return std::vformat_to(std::move(__out_it), std::move(__loc), __fmt.get(), + std::make_wformat_args(__args...)); } #endif @@ -594,7 +594,7 @@ template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE inline _LIBCPP_HIDE_FROM_ABI string vformat(locale __loc, string_view __fmt, format_args __args) { string __res; - _VSTD::vformat_to(_VSTD::back_inserter(__res), _VSTD::move(__loc), __fmt, + std::vformat_to(std::back_inserter(__res), std::move(__loc), __fmt, __args); return __res; } @@ -606,7 +606,7 @@ template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE inline _LIBCPP_HIDE_FROM_ABI wstring vformat(locale __loc, wstring_view __fmt, wformat_args __args) { wstring __res; - _VSTD::vformat_to(_VSTD::back_inserter(__res), _VSTD::move(__loc), __fmt, + std::vformat_to(std::back_inserter(__res), std::move(__loc), __fmt, __args); return __res; } @@ -615,16 +615,16 @@ vformat(locale __loc, wstring_view __fmt, wformat_args __args) { template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI string format(locale __loc, format_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::vformat(_VSTD::move(__loc), __fmt.get(), - _VSTD::make_format_args(__args...)); + return std::vformat(std::move(__loc), __fmt.get(), + std::make_format_args(__args...)); } # ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI wstring format(locale __loc, wformat_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::vformat(_VSTD::move(__loc), __fmt.get(), - _VSTD::make_wformat_args(__args...)); + return std::vformat(std::move(__loc), __fmt.get(), + std::make_wformat_args(__args...)); } # endif @@ -632,19 +632,19 @@ template _LIBCPP_HIDE_FROM_ABI format_to_n_result<_OutIt> __vformat_to_n(_OutIt __out_it, iter_difference_t<_OutIt> __n, locale __loc, basic_string_view<_CharT> __fmt, basic_format_args<_Context> __args) { - __format::__format_to_n_buffer<_OutIt, _CharT> __buffer{_VSTD::move(__out_it), __n}; - _VSTD::__format::__vformat_to( + __format::__format_to_n_buffer<_OutIt, _CharT> __buffer{std::move(__out_it), __n}; + std::__format::__vformat_to( basic_format_parse_context{__fmt, __args.__size()}, - _VSTD::__format_context_create(__buffer.__make_output_iterator(), __args, _VSTD::move(__loc))); - return _VSTD::move(__buffer).__result(); + std::__format_context_create(__buffer.__make_output_iterator(), __args, std::move(__loc))); + return std::move(__buffer).__result(); } template _OutIt, class... _Args> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI format_to_n_result<_OutIt> format_to_n(_OutIt __out_it, iter_difference_t<_OutIt> __n, locale __loc, format_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::__vformat_to_n(_VSTD::move(__out_it), __n, _VSTD::move(__loc), __fmt.get(), - _VSTD::make_format_args(__args...)); + return std::__vformat_to_n(std::move(__out_it), __n, std::move(__loc), __fmt.get(), + std::make_format_args(__args...)); } #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS @@ -652,31 +652,31 @@ template _OutIt, class... _Args> _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI format_to_n_result<_OutIt> format_to_n(_OutIt __out_it, iter_difference_t<_OutIt> __n, locale __loc, wformat_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::__vformat_to_n(_VSTD::move(__out_it), __n, _VSTD::move(__loc), __fmt.get(), - _VSTD::make_wformat_args(__args...)); + return std::__vformat_to_n(std::move(__out_it), __n, std::move(__loc), __fmt.get(), + std::make_wformat_args(__args...)); } #endif template _LIBCPP_HIDE_FROM_ABI size_t __vformatted_size(locale __loc, basic_string_view<_CharT> __fmt, auto __args) { __format::__formatted_size_buffer<_CharT> __buffer; - _VSTD::__format::__vformat_to( + std::__format::__vformat_to( basic_format_parse_context{__fmt, __args.__size()}, - _VSTD::__format_context_create(__buffer.__make_output_iterator(), __args, _VSTD::move(__loc))); - return _VSTD::move(__buffer).__result(); + std::__format_context_create(__buffer.__make_output_iterator(), __args, std::move(__loc))); + return std::move(__buffer).__result(); } template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI size_t formatted_size(locale __loc, format_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::__vformatted_size(_VSTD::move(__loc), __fmt.get(), basic_format_args{_VSTD::make_format_args(__args...)}); + return std::__vformatted_size(std::move(__loc), __fmt.get(), basic_format_args{std::make_format_args(__args...)}); } # ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS template _LIBCPP_NODISCARD_EXT _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI size_t formatted_size(locale __loc, wformat_string<_Args...> __fmt, _Args&&... __args) { - return _VSTD::__vformatted_size(_VSTD::move(__loc), __fmt.get(), basic_format_args{_VSTD::make_wformat_args(__args...)}); + return std::__vformatted_size(std::move(__loc), __fmt.get(), basic_format_args{std::make_wformat_args(__args...)}); } # endif diff --git a/libcxx/include/__format/formatter_floating_point.h b/libcxx/include/__format/formatter_floating_point.h index 9bf48df21961..b45c2a6ebd39 100644 --- a/libcxx/include/__format/formatter_floating_point.h +++ b/libcxx/include/__format/formatter_floating_point.h @@ -56,21 +56,21 @@ namespace __formatter { template _LIBCPP_HIDE_FROM_ABI char* __to_buffer(char* __first, char* __last, _Tp __value) { - to_chars_result __r = _VSTD::to_chars(__first, __last, __value); + to_chars_result __r = std::to_chars(__first, __last, __value); _LIBCPP_ASSERT_UNCATEGORIZED(__r.ec == errc(0), "Internal buffer too small"); return __r.ptr; } template _LIBCPP_HIDE_FROM_ABI char* __to_buffer(char* __first, char* __last, _Tp __value, chars_format __fmt) { - to_chars_result __r = _VSTD::to_chars(__first, __last, __value, __fmt); + to_chars_result __r = std::to_chars(__first, __last, __value, __fmt); _LIBCPP_ASSERT_UNCATEGORIZED(__r.ec == errc(0), "Internal buffer too small"); return __r.ptr; } template _LIBCPP_HIDE_FROM_ABI char* __to_buffer(char* __first, char* __last, _Tp __value, chars_format __fmt, int __precision) { - to_chars_result __r = _VSTD::to_chars(__first, __last, __value, __fmt, __precision); + to_chars_result __r = std::to_chars(__first, __last, __value, __fmt, __precision); _LIBCPP_ASSERT_UNCATEGORIZED(__r.ec == errc(0), "Internal buffer too small"); return __r.ptr; } @@ -224,7 +224,7 @@ struct __float_result { constexpr inline _LIBCPP_HIDE_FROM_ABI char* __find_exponent(char* __first, char* __last) { ptrdiff_t __size = __last - __first; if (__size >= 4) { - __first = __last - _VSTD::min(__size, ptrdiff_t(6)); + __first = __last - std::min(__size, ptrdiff_t(6)); for (; __first != __last - 3; ++__first) { if (*__first == 'e') return __first; @@ -245,7 +245,7 @@ _LIBCPP_HIDE_FROM_ABI __float_result __format_buffer_default(const __float_buffe // Constrains: // - There's at least one decimal digit before the radix point. // - The radix point, when present, is placed before the exponent. - __result.__radix_point = _VSTD::find(__result.__integral + 1, __result.__exponent, '.'); + __result.__radix_point = std::find(__result.__integral + 1, __result.__exponent, '.'); // When the radix point isn't found its position is the exponent instead of // __result.__last. @@ -299,7 +299,7 @@ _LIBCPP_HIDE_FROM_ABI __float_result __format_buffer_hexadecimal_lower_case(cons char* __last = __result.__last - 2; __first = __last - __traits<_Fp>::__hex_precision_digits; - __result.__exponent = _VSTD::find(__first, __last, 'p'); + __result.__exponent = std::find(__first, __last, 'p'); } else { __result.__radix_point = __result.__last; __result.__exponent = __first; @@ -321,7 +321,7 @@ _LIBCPP_HIDE_FROM_ABI __float_result __format_buffer_hexadecimal_upper_case(cons char* __integral) { __float_result __result = __formatter::__format_buffer_hexadecimal_lower_case(__buffer, __value, __precision, __integral); - _VSTD::transform(__result.__integral, __result.__exponent, __result.__integral, __hex_to_upper); + std::transform(__result.__integral, __result.__exponent, __result.__integral, __hex_to_upper); *__result.__exponent = 'P'; return __result; } @@ -411,7 +411,7 @@ _LIBCPP_HIDE_FROM_ABI __float_result __format_buffer_general_lower_case(__float_ // In fixed mode the algorithm truncates trailing spaces and possibly the // radix point. There's no good guess for the position of the radix point // therefore scan the output after the first digit. - __result.__radix_point = _VSTD::find(__first, __result.__last, '.'); + __result.__radix_point = std::find(__first, __result.__last, '.'); } } @@ -502,13 +502,13 @@ _LIBCPP_HIDE_FROM_ABI _OutIt __format_locale_specific_form( _OutIt __out_it, const __float_buffer<_Fp>& __buffer, const __float_result& __result, - _VSTD::locale __loc, + std::locale __loc, __format_spec::__parsed_specifications<_CharT> __specs) { const auto& __np = std::use_facet>(__loc); string __grouping = __np.grouping(); char* __first = __result.__integral; // When no radix point or exponent are present __last will be __result.__last. - char* __last = _VSTD::min(__result.__radix_point, __result.__exponent); + char* __last = std::min(__result.__radix_point, __result.__exponent); ptrdiff_t __digits = __last - __first; if (!__grouping.empty()) { @@ -538,13 +538,13 @@ _LIBCPP_HIDE_FROM_ABI _OutIt __format_locale_specific_form( // sign and (zero padding or alignment) if (__zero_padding && __first != __buffer.begin()) *__out_it++ = *__buffer.begin(); - __out_it = __formatter::__fill(_VSTD::move(__out_it), __padding.__before_, __specs.__fill_); + __out_it = __formatter::__fill(std::move(__out_it), __padding.__before_, __specs.__fill_); if (!__zero_padding && __first != __buffer.begin()) *__out_it++ = *__buffer.begin(); // integral part if (__grouping.empty()) { - __out_it = __formatter::__copy(__first, __digits, _VSTD::move(__out_it)); + __out_it = __formatter::__copy(__first, __digits, std::move(__out_it)); } else { auto __r = __grouping.rbegin(); auto __e = __grouping.rend() - 1; @@ -556,7 +556,7 @@ _LIBCPP_HIDE_FROM_ABI _OutIt __format_locale_specific_form( // This loop achieves that process by testing the termination condition // midway in the loop. while (true) { - __out_it = __formatter::__copy(__first, *__r, _VSTD::move(__out_it)); + __out_it = __formatter::__copy(__first, *__r, std::move(__out_it)); __first += *__r; if (__r == __e) @@ -570,16 +570,16 @@ _LIBCPP_HIDE_FROM_ABI _OutIt __format_locale_specific_form( // fractional part if (__result.__radix_point != __result.__last) { *__out_it++ = __np.decimal_point(); - __out_it = __formatter::__copy(__result.__radix_point + 1, __result.__exponent, _VSTD::move(__out_it)); - __out_it = __formatter::__fill(_VSTD::move(__out_it), __buffer.__num_trailing_zeros(), _CharT('0')); + __out_it = __formatter::__copy(__result.__radix_point + 1, __result.__exponent, std::move(__out_it)); + __out_it = __formatter::__fill(std::move(__out_it), __buffer.__num_trailing_zeros(), _CharT('0')); } // exponent if (__result.__exponent != __result.__last) - __out_it = __formatter::__copy(__result.__exponent, __result.__last, _VSTD::move(__out_it)); + __out_it = __formatter::__copy(__result.__exponent, __result.__last, std::move(__out_it)); // alignment - return __formatter::__fill(_VSTD::move(__out_it), __padding.__after_, __specs.__fill_); + return __formatter::__fill(std::move(__out_it), __padding.__after_, __specs.__fill_); } # endif // _LIBCPP_HAS_NO_LOCALIZATION @@ -597,7 +597,7 @@ _LIBCPP_HIDE_FROM_ABI _OutIt __format_floating_point_non_finite( __specs.__std_.__type_ == __format_spec::__type::__scientific_upper_case || __specs.__std_.__type_ == __format_spec::__type::__fixed_upper_case || __specs.__std_.__type_ == __format_spec::__type::__general_upper_case; - __last = _VSTD::copy_n(&("infnanINFNAN"[6 * __upper_case + 3 * __isnan]), 3, __last); + __last = std::copy_n(&("infnanINFNAN"[6 * __upper_case + 3 * __isnan]), 3, __last); // [format.string.std]/13 // A zero (0) character preceding the width field pads the field with @@ -606,7 +606,7 @@ _LIBCPP_HIDE_FROM_ABI _OutIt __format_floating_point_non_finite( if (__specs.__alignment_ == __format_spec::__alignment::__zero_padding) __specs.__alignment_ = __format_spec::__alignment::__right; - return __formatter::__write(__buffer, __last, _VSTD::move(__out_it), __specs); + return __formatter::__write(__buffer, __last, std::move(__out_it), __specs); } /// Writes additional zero's for the precision before the exponent. @@ -632,21 +632,21 @@ _LIBCPP_HIDE_FROM_ABI auto __write_using_trailing_zeros( __padding_size_result __padding = __formatter::__padding_size(__size + __num_trailing_zeros, __specs.__width_, __specs.__alignment_); - __out_it = __formatter::__fill(_VSTD::move(__out_it), __padding.__before_, __specs.__fill_); - __out_it = __formatter::__copy(__first, __exponent, _VSTD::move(__out_it)); - __out_it = __formatter::__fill(_VSTD::move(__out_it), __num_trailing_zeros, _CharT('0')); - __out_it = __formatter::__copy(__exponent, __last, _VSTD::move(__out_it)); - return __formatter::__fill(_VSTD::move(__out_it), __padding.__after_, __specs.__fill_); + __out_it = __formatter::__fill(std::move(__out_it), __padding.__before_, __specs.__fill_); + __out_it = __formatter::__copy(__first, __exponent, std::move(__out_it)); + __out_it = __formatter::__fill(std::move(__out_it), __num_trailing_zeros, _CharT('0')); + __out_it = __formatter::__copy(__exponent, __last, std::move(__out_it)); + return __formatter::__fill(std::move(__out_it), __padding.__after_, __specs.__fill_); } template _LIBCPP_HIDE_FROM_ABI typename _FormatContext::iterator __format_floating_point(_Tp __value, _FormatContext& __ctx, __format_spec::__parsed_specifications<_CharT> __specs) { - bool __negative = _VSTD::signbit(__value); + bool __negative = std::signbit(__value); - if (!_VSTD::isfinite(__value)) [[unlikely]] - return __formatter::__format_floating_point_non_finite(__ctx.out(), __specs, __negative, _VSTD::isnan(__value)); + if (!std::isfinite(__value)) [[unlikely]] + return __formatter::__format_floating_point_non_finite(__ctx.out(), __specs, __negative, std::isnan(__value)); // Depending on the std-format-spec string the sign and the value // might not be outputted together: @@ -672,7 +672,7 @@ __format_floating_point(_Tp __value, _FormatContext& __ctx, __format_spec::__par // When there is an exponent the point needs to be moved before the // exponent. When there's no exponent the rotate does nothing. Since // rotate tests whether the operation is a nop, call it unconditionally. - _VSTD::rotate(__result.__exponent, __result.__last - 1, __result.__last); + std::rotate(__result.__exponent, __result.__last - 1, __result.__last); __result.__radix_point = __result.__exponent; // The radix point is always placed before the exponent. @@ -697,7 +697,7 @@ __format_floating_point(_Tp __value, _FormatContext& __ctx, __format_spec::__par // Let P equal the precision if nonzero, 6 if the precision is not // specified, or 1 if the precision is 0. Then, if a conversion with // style E would have an exponent of X: - int __p = _VSTD::max(1, (__specs.__has_precision() ? __specs.__precision_ : 6)); + int __p = std::max(1, (__specs.__has_precision() ? __specs.__precision_ : 6)); if (__result.__exponent == __result.__last) // if P > X >= -4, the conversion is with style f or F and precision P - 1 - X. // By including the radix point it calculates P - (1 + X) @@ -749,9 +749,9 @@ __format_floating_point(_Tp __value, _FormatContext& __ctx, __format_spec::__par if (__num_trailing_zeros) return __formatter::__write_using_trailing_zeros( - __first, __result.__last, _VSTD::move(__out_it), __specs, __size, __result.__exponent, __num_trailing_zeros); + __first, __result.__last, std::move(__out_it), __specs, __size, __result.__exponent, __num_trailing_zeros); - return __formatter::__write(__first, __result.__last, _VSTD::move(__out_it), __specs, __size); + return __formatter::__write(__first, __result.__last, std::move(__out_it), __specs, __size); } } // namespace __formatter diff --git a/libcxx/include/__format/formatter_integral.h b/libcxx/include/__format/formatter_integral.h index 54246aa02718..598decb0a95e 100644 --- a/libcxx/include/__format/formatter_integral.h +++ b/libcxx/include/__format/formatter_integral.h @@ -141,7 +141,7 @@ _LIBCPP_HIDE_FROM_ABI auto __format_char( } const auto __c = static_cast<_CharT>(__value); - return __formatter::__write(_VSTD::addressof(__c), _VSTD::addressof(__c) + 1, _VSTD::move(__out_it), __specs); + return __formatter::__write(std::addressof(__c), std::addressof(__c) + 1, std::move(__out_it), __specs); } // @@ -153,7 +153,7 @@ template _LIBCPP_HIDE_FROM_ABI char* __to_buffer(char* __first, char* __last, _Tp __value, int __base) { // TODO FMT Evaluate code overhead due to not calling the internal function // directly. (Should be zero overhead.) - to_chars_result __r = _VSTD::to_chars(__first, __last, __value, __base); + to_chars_result __r = std::to_chars(__first, __last, __value, __base); _LIBCPP_ASSERT_UNCATEGORIZED(__r.ec == errc(0), "Internal buffer too small"); return __r.ptr; } @@ -214,22 +214,22 @@ _LIBCPP_HIDE_FROM_ABI _OutIt __write_using_decimal_separators(_OutIt __out_it, c __padding_size_result __padding = {0, 0}; if (__specs.__alignment_ == __format_spec::__alignment::__zero_padding) { // Write [sign][prefix]. - __out_it = __formatter::__copy(__begin, __first, _VSTD::move(__out_it)); + __out_it = __formatter::__copy(__begin, __first, std::move(__out_it)); if (__specs.__width_ > __size) { // Write zero padding. __padding.__before_ = __specs.__width_ - __size; - __out_it = __formatter::__fill(_VSTD::move(__out_it), __specs.__width_ - __size, _CharT('0')); + __out_it = __formatter::__fill(std::move(__out_it), __specs.__width_ - __size, _CharT('0')); } } else { if (__specs.__width_ > __size) { // Determine padding and write padding. __padding = __formatter::__padding_size(__size, __specs.__width_, __specs.__alignment_); - __out_it = __formatter::__fill(_VSTD::move(__out_it), __padding.__before_, __specs.__fill_); + __out_it = __formatter::__fill(std::move(__out_it), __padding.__before_, __specs.__fill_); } // Write [sign][prefix]. - __out_it = __formatter::__copy(__begin, __first, _VSTD::move(__out_it)); + __out_it = __formatter::__copy(__begin, __first, std::move(__out_it)); } auto __r = __grouping.rbegin(); @@ -250,10 +250,10 @@ _LIBCPP_HIDE_FROM_ABI _OutIt __write_using_decimal_separators(_OutIt __out_it, c while (true) { if (__specs.__std_.__type_ == __format_spec::__type::__hexadecimal_upper_case) { __last = __first + *__r; - __out_it = __formatter::__transform(__first, __last, _VSTD::move(__out_it), __hex_to_upper); + __out_it = __formatter::__transform(__first, __last, std::move(__out_it), __hex_to_upper); __first = __last; } else { - __out_it = __formatter::__copy(__first, *__r, _VSTD::move(__out_it)); + __out_it = __formatter::__copy(__first, *__r, std::move(__out_it)); __first += *__r; } @@ -264,7 +264,7 @@ _LIBCPP_HIDE_FROM_ABI _OutIt __write_using_decimal_separators(_OutIt __out_it, c *__out_it++ = __sep; } - return __formatter::__fill(_VSTD::move(__out_it), __padding.__after_, __specs.__fill_); + return __formatter::__fill(std::move(__out_it), __padding.__after_, __specs.__fill_); } @@ -315,12 +315,12 @@ _LIBCPP_HIDE_FROM_ABI typename _FormatContext::iterator __format_integer( // The zero padding is done like: // - Write [sign][prefix] // - Write data right aligned with '0' as fill character. - __out_it = __formatter::__copy(__begin, __first, _VSTD::move(__out_it)); + __out_it = __formatter::__copy(__begin, __first, std::move(__out_it)); __specs.__alignment_ = __format_spec::__alignment::__right; __specs.__fill_.__data[0] = _CharT('0'); int32_t __size = __first - __begin; - __specs.__width_ -= _VSTD::min(__size, __specs.__width_); + __specs.__width_ -= std::min(__size, __specs.__width_); } if (__specs.__std_.__type_ != __format_spec::__type::__hexadecimal_upper_case) [[likely]] diff --git a/libcxx/include/__format/formatter_output.h b/libcxx/include/__format/formatter_output.h index 072305b6dbca..2909fcd9baf1 100644 --- a/libcxx/include/__format/formatter_output.h +++ b/libcxx/include/__format/formatter_output.h @@ -98,15 +98,15 @@ __padding_size(size_t __size, size_t __width, __format_spec::__alignment __align template <__fmt_char_type _CharT, __fmt_char_type _OutCharT = _CharT> _LIBCPP_HIDE_FROM_ABI auto __copy(basic_string_view<_CharT> __str, output_iterator auto __out_it) -> decltype(__out_it) { - if constexpr (_VSTD::same_as>>) { + if constexpr (std::same_as>>) { __out_it.__get_container()->__copy(__str); return __out_it; - } else if constexpr (_VSTD::same_as::__iterator>) { __out_it.__buffer_->__copy(__str); return __out_it; } else { - return std::ranges::copy(__str, _VSTD::move(__out_it)).out; + return std::ranges::copy(__str, std::move(__out_it)).out; } } @@ -114,13 +114,13 @@ template <__fmt_char_type _CharT, __fmt_char_type _OutCharT = _CharT> _LIBCPP_HIDE_FROM_ABI auto __copy(const _CharT* __first, const _CharT* __last, output_iterator auto __out_it) -> decltype(__out_it) { - return __formatter::__copy(basic_string_view{__first, __last}, _VSTD::move(__out_it)); + return __formatter::__copy(basic_string_view{__first, __last}, std::move(__out_it)); } template <__fmt_char_type _CharT, __fmt_char_type _OutCharT = _CharT> _LIBCPP_HIDE_FROM_ABI auto __copy(const _CharT* __first, size_t __n, output_iterator auto __out_it) -> decltype(__out_it) { - return __formatter::__copy(basic_string_view{__first, __n}, _VSTD::move(__out_it)); + return __formatter::__copy(basic_string_view{__first, __n}, std::move(__out_it)); } /// Transform wrapper. @@ -132,15 +132,15 @@ __transform(const _CharT* __first, const _CharT* __last, output_iterator auto __out_it, _UnaryOperation __operation) -> decltype(__out_it) { - if constexpr (_VSTD::same_as>>) { - __out_it.__get_container()->__transform(__first, __last, _VSTD::move(__operation)); + if constexpr (std::same_as>>) { + __out_it.__get_container()->__transform(__first, __last, std::move(__operation)); return __out_it; - } else if constexpr (_VSTD::same_as::__iterator>) { - __out_it.__buffer_->__transform(__first, __last, _VSTD::move(__operation)); + __out_it.__buffer_->__transform(__first, __last, std::move(__operation)); return __out_it; } else { - return std::ranges::transform(__first, __last, _VSTD::move(__out_it), __operation).out; + return std::ranges::transform(__first, __last, std::move(__out_it), __operation).out; } } @@ -149,14 +149,14 @@ __transform(const _CharT* __first, /// This uses a "mass output function" of __format::__output_buffer when possible. template <__fmt_char_type _CharT, output_iterator _OutIt> _LIBCPP_HIDE_FROM_ABI _OutIt __fill(_OutIt __out_it, size_t __n, _CharT __value) { - if constexpr (_VSTD::same_as>>) { + if constexpr (std::same_as>>) { __out_it.__get_container()->__fill(__n, __value); return __out_it; - } else if constexpr (_VSTD::same_as::__iterator>) { + } else if constexpr (std::same_as::__iterator>) { __out_it.__buffer_->__fill(__n, __value); return __out_it; } else { - return std::ranges::fill_n(_VSTD::move(__out_it), __n, __value); + return std::ranges::fill_n(std::move(__out_it), __n, __value); } } @@ -228,12 +228,12 @@ __write(basic_string_view<_CharT> __str, __format_spec::__parsed_specifications<_ParserCharT> __specs, ptrdiff_t __size) -> decltype(__out_it) { if (__size >= __specs.__width_) - return __formatter::__copy(__str, _VSTD::move(__out_it)); + return __formatter::__copy(__str, std::move(__out_it)); __padding_size_result __padding = __formatter::__padding_size(__size, __specs.__width_, __specs.__std_.__alignment_); - __out_it = __formatter::__fill(_VSTD::move(__out_it), __padding.__before_, __specs.__fill_); - __out_it = __formatter::__copy(__str, _VSTD::move(__out_it)); - return __formatter::__fill(_VSTD::move(__out_it), __padding.__after_, __specs.__fill_); + __out_it = __formatter::__fill(std::move(__out_it), __padding.__before_, __specs.__fill_); + __out_it = __formatter::__copy(__str, std::move(__out_it)); + return __formatter::__fill(std::move(__out_it), __padding.__after_, __specs.__fill_); } template @@ -244,7 +244,7 @@ __write(_Iterator __first, __format_spec::__parsed_specifications<_ParserCharT> __specs, ptrdiff_t __size) -> decltype(__out_it) { _LIBCPP_ASSERT_UNCATEGORIZED(__first <= __last, "Not a valid range"); - return __formatter::__write(basic_string_view{__first, __last}, _VSTD::move(__out_it), __specs, __size); + return __formatter::__write(basic_string_view{__first, __last}, std::move(__out_it), __specs, __size); } /// \overload @@ -257,7 +257,7 @@ __write(_Iterator __first, output_iterator&> auto __out_it, __format_spec::__parsed_specifications<_ParserCharT> __specs) -> decltype(__out_it) { _LIBCPP_ASSERT_UNCATEGORIZED(__first <= __last, "Not a valid range"); - return __formatter::__write(__first, __last, _VSTD::move(__out_it), __specs, __last - __first); + return __formatter::__write(__first, __last, std::move(__out_it), __specs, __last - __first); } template @@ -269,12 +269,12 @@ _LIBCPP_HIDE_FROM_ABI auto __write_transformed(const _CharT* __first, const _Cha ptrdiff_t __size = __last - __first; if (__size >= __specs.__width_) - return __formatter::__transform(__first, __last, _VSTD::move(__out_it), __op); + return __formatter::__transform(__first, __last, std::move(__out_it), __op); __padding_size_result __padding = __formatter::__padding_size(__size, __specs.__width_, __specs.__alignment_); - __out_it = __formatter::__fill(_VSTD::move(__out_it), __padding.__before_, __specs.__fill_); - __out_it = __formatter::__transform(__first, __last, _VSTD::move(__out_it), __op); - return __formatter::__fill(_VSTD::move(__out_it), __padding.__after_, __specs.__fill_); + __out_it = __formatter::__fill(std::move(__out_it), __padding.__before_, __specs.__fill_); + __out_it = __formatter::__transform(__first, __last, std::move(__out_it), __op); + return __formatter::__fill(std::move(__out_it), __padding.__after_, __specs.__fill_); } /// Writes a string using format's width estimation algorithm. @@ -292,7 +292,7 @@ _LIBCPP_HIDE_FROM_ABI auto __write_string_no_precision( // No padding -> copy the string if (!__specs.__has_width()) - return __formatter::__copy(__str, _VSTD::move(__out_it)); + return __formatter::__copy(__str, std::move(__out_it)); // Note when the estimated width is larger than size there's no padding. So // there's no reason to get the real size when the estimate is larger than or @@ -300,7 +300,7 @@ _LIBCPP_HIDE_FROM_ABI auto __write_string_no_precision( size_t __size = __format_spec::__estimate_column_width(__str, __specs.__width_, __format_spec::__column_width_rounding::__up) .__width_; - return __formatter::__write(__str, _VSTD::move(__out_it), __specs, __size); + return __formatter::__write(__str, std::move(__out_it), __specs, __size); } template diff --git a/libcxx/include/__format/parser_std_format_spec.h b/libcxx/include/__format/parser_std_format_spec.h index e79fc8fc481b..ea5dfdf30511 100644 --- a/libcxx/include/__format/parser_std_format_spec.h +++ b/libcxx/include/__format/parser_std_format_spec.h @@ -92,7 +92,7 @@ __substitute_arg_id(basic_format_arg<_Context> __format_arg) { // This means the 128-bit will not be valid anymore. // TODO FMT Verify this resolution is accepted and add a test to verify // 128-bit integrals fail and switch to visit_format_arg. - return _VSTD::__visit_format_arg( + return std::__visit_format_arg( [](auto __arg) -> uint32_t { using _Type = decltype(__arg); if constexpr (same_as<_Type, monostate>) @@ -1158,7 +1158,7 @@ __estimate_column_width(basic_string_view<_CharT> __str, size_t __maximum, __col // When Unicode isn't supported assume ASCII and every code unit is one code // point. In ASCII the estimated column width is always one. Thus there's no // need for rounding. - size_t __width_ = _VSTD::min(__str.size(), __maximum); + size_t __width_ = std::min(__str.size(), __maximum); return {__width_, __str.begin() + __width_}; } diff --git a/libcxx/include/__format/write_escaped.h b/libcxx/include/__format/write_escaped.h index e415fc5f0505..51bae3cb238f 100644 --- a/libcxx/include/__format/write_escaped.h +++ b/libcxx/include/__format/write_escaped.h @@ -47,11 +47,11 @@ _LIBCPP_HIDE_FROM_ABI auto __write_string( output_iterator auto __out_it, __format_spec::__parsed_specifications<_CharT> __specs) -> decltype(__out_it) { if (!__specs.__has_precision()) - return __formatter::__write_string_no_precision(__str, _VSTD::move(__out_it), __specs); + return __formatter::__write_string_no_precision(__str, std::move(__out_it), __specs); int __size = __formatter::__truncate(__str, __specs.__precision_); - return __formatter::__write(__str.begin(), __str.end(), _VSTD::move(__out_it), __specs, __size); + return __formatter::__write(__str.begin(), __str.end(), std::move(__out_it), __specs, __size); } # endif // _LIBCPP_STD_VER >= 20 @@ -198,7 +198,7 @@ __format_escaped_char(_CharT __value, __str += _CharT('\''); __formatter::__escape(__str, basic_string_view{std::addressof(__value), 1}, __escape_quotation_mark::__apostrophe); __str += _CharT('\''); - return __formatter::__write(__str.data(), __str.data() + __str.size(), _VSTD::move(__out_it), __specs, __str.size()); + return __formatter::__write(__str.data(), __str.data() + __str.size(), std::move(__out_it), __specs, __str.size()); } template @@ -210,7 +210,7 @@ __format_escaped_string(basic_string_view<_CharT> __values, __str += _CharT('"'); __formatter::__escape(__str, __values, __escape_quotation_mark::__double_quote); __str += _CharT('"'); - return __formatter::__write_string(basic_string_view{__str}, _VSTD::move(__out_it), __specs); + return __formatter::__write_string(basic_string_view{__str}, std::move(__out_it), __specs); } # endif // _LIBCPP_STD_VER >= 23 diff --git a/libcxx/include/__functional/bind.h b/libcxx/include/__functional/bind.h index 03e214a1dfa8..61d99e1fd564 100644 --- a/libcxx/include/__functional/bind.h +++ b/libcxx/include/__functional/bind.h @@ -95,7 +95,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 typename __invoke_of<_Ti&, _Uj...>::type __mu_expand(_Ti& __ti, tuple<_Uj...>& __uj, __tuple_indices<_Indx...>) { - return __ti(_VSTD::forward<_Uj>(_VSTD::get<_Indx>(__uj))...); + return __ti(std::forward<_Uj>(std::get<_Indx>(__uj))...); } template ::value, int> = 0> @@ -104,7 +104,7 @@ typename __invoke_of<_Ti&, _Uj...>::type __mu(_Ti& __ti, tuple<_Uj...>& __uj) { typedef typename __make_tuple_indices::type __indices; - return _VSTD::__mu_expand(__ti, __uj, __indices()); + return std::__mu_expand(__ti, __uj, __indices()); } template @@ -122,7 +122,7 @@ typename __mu_return2<0 < is_placeholder<_Ti>::value, _Ti, _Uj>::type __mu(_Ti&, _Uj& __uj) { const size_t __indx = is_placeholder<_Ti>::value - 1; - return _VSTD::forward::type>(_VSTD::get<__indx>(__uj)); + return std::forward::type>(std::get<__indx>(__uj)); } template ::value && @@ -245,7 +245,7 @@ typename __bind_return<_Fp, _BoundArgs, _Args>::type __apply_functor(_Fp& __f, _BoundArgs& __bound_args, __tuple_indices<_Indx...>, _Args&& __args) { - return _VSTD::__invoke(__f, _VSTD::__mu(_VSTD::get<_Indx>(__bound_args), __args)...); + return std::__invoke(__f, std::__mu(std::get<_Indx>(__bound_args), __args)...); } template @@ -264,16 +264,16 @@ public: __enable_if_t::value && !is_same<__libcpp_remove_reference_t<_Gp>, __bind>::value, int> = 0> _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 explicit __bind(_Gp&& __f, _BA&& ...__bound_args) - : __f_(_VSTD::forward<_Gp>(__f)), - __bound_args_(_VSTD::forward<_BA>(__bound_args)...) {} + : __f_(std::forward<_Gp>(__f)), + __bound_args_(std::forward<_BA>(__bound_args)...) {} template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 typename __bind_return<_Fd, _Td, tuple<_Args&&...> >::type operator()(_Args&& ...__args) { - return _VSTD::__apply_functor(__f_, __bound_args_, __indices(), - tuple<_Args&&...>(_VSTD::forward<_Args>(__args)...)); + return std::__apply_functor(__f_, __bound_args_, __indices(), + tuple<_Args&&...>(std::forward<_Args>(__args)...)); } template @@ -281,8 +281,8 @@ public: typename __bind_return >::type operator()(_Args&& ...__args) const { - return _VSTD::__apply_functor(__f_, __bound_args_, __indices(), - tuple<_Args&&...>(_VSTD::forward<_Args>(__args)...)); + return std::__apply_functor(__f_, __bound_args_, __indices(), + tuple<_Args&&...>(std::forward<_Args>(__args)...)); } }; @@ -304,8 +304,8 @@ public: __enable_if_t::value && !is_same<__libcpp_remove_reference_t<_Gp>, __bind_r>::value, int> = 0> _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 explicit __bind_r(_Gp&& __f, _BA&& ...__bound_args) - : base(_VSTD::forward<_Gp>(__f), - _VSTD::forward<_BA>(__bound_args)...) {} + : base(std::forward<_Gp>(__f), + std::forward<_BA>(__bound_args)...) {} template >::type, result_type>::value || is_void<_Rp>::value, int> = 0> @@ -314,7 +314,7 @@ public: operator()(_Args&& ...__args) { typedef __invoke_void_return_wrapper<_Rp> _Invoker; - return _Invoker::__call(static_cast(*this), _VSTD::forward<_Args>(__args)...); + return _Invoker::__call(static_cast(*this), std::forward<_Args>(__args)...); } template >::type, @@ -324,7 +324,7 @@ public: operator()(_Args&& ...__args) const { typedef __invoke_void_return_wrapper<_Rp> _Invoker; - return _Invoker::__call(static_cast(*this), _VSTD::forward<_Args>(__args)...); + return _Invoker::__call(static_cast(*this), std::forward<_Args>(__args)...); } }; @@ -337,7 +337,7 @@ __bind<_Fp, _BoundArgs...> bind(_Fp&& __f, _BoundArgs&&... __bound_args) { typedef __bind<_Fp, _BoundArgs...> type; - return type(_VSTD::forward<_Fp>(__f), _VSTD::forward<_BoundArgs>(__bound_args)...); + return type(std::forward<_Fp>(__f), std::forward<_BoundArgs>(__bound_args)...); } template @@ -346,7 +346,7 @@ __bind_r<_Rp, _Fp, _BoundArgs...> bind(_Fp&& __f, _BoundArgs&&... __bound_args) { typedef __bind_r<_Rp, _Fp, _BoundArgs...> type; - return type(_VSTD::forward<_Fp>(__f), _VSTD::forward<_BoundArgs>(__bound_args)...); + return type(std::forward<_Fp>(__f), std::forward<_BoundArgs>(__bound_args)...); } #endif // _LIBCPP_CXX03_LANG diff --git a/libcxx/include/__functional/bind_back.h b/libcxx/include/__functional/bind_back.h index 0dd2befb5240..5b5b40520933 100644 --- a/libcxx/include/__functional/bind_back.h +++ b/libcxx/include/__functional/bind_back.h @@ -33,9 +33,9 @@ template struct __bind_back_op<_NBound, index_sequence<_Ip...>> { template _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Fn&& __f, _BoundArgs&& __bound_args, _Args&&... __args) const - noexcept(noexcept(_VSTD::invoke(_VSTD::forward<_Fn>(__f), _VSTD::forward<_Args>(__args)..., _VSTD::get<_Ip>(_VSTD::forward<_BoundArgs>(__bound_args))...))) - -> decltype( _VSTD::invoke(_VSTD::forward<_Fn>(__f), _VSTD::forward<_Args>(__args)..., _VSTD::get<_Ip>(_VSTD::forward<_BoundArgs>(__bound_args))...)) - { return _VSTD::invoke(_VSTD::forward<_Fn>(__f), _VSTD::forward<_Args>(__args)..., _VSTD::get<_Ip>(_VSTD::forward<_BoundArgs>(__bound_args))...); } + noexcept(noexcept(std::invoke(std::forward<_Fn>(__f), std::forward<_Args>(__args)..., std::get<_Ip>(std::forward<_BoundArgs>(__bound_args))...))) + -> decltype( std::invoke(std::forward<_Fn>(__f), std::forward<_Args>(__args)..., std::get<_Ip>(std::forward<_BoundArgs>(__bound_args))...)) + { return std::invoke(std::forward<_Fn>(__f), std::forward<_Args>(__args)..., std::get<_Ip>(std::forward<_BoundArgs>(__bound_args))...); } }; template @@ -48,9 +48,9 @@ template (is_constructible_v, _Args> && ...) && (is_move_constructible_v> && ...) _LIBCPP_HIDE_FROM_ABI constexpr auto __bind_back(_Fn&& __f, _Args&&... __args) - noexcept(noexcept(__bind_back_t, tuple...>>(_VSTD::forward<_Fn>(__f), _VSTD::forward_as_tuple(_VSTD::forward<_Args>(__args)...)))) - -> decltype( __bind_back_t, tuple...>>(_VSTD::forward<_Fn>(__f), _VSTD::forward_as_tuple(_VSTD::forward<_Args>(__args)...))) - { return __bind_back_t, tuple...>>(_VSTD::forward<_Fn>(__f), _VSTD::forward_as_tuple(_VSTD::forward<_Args>(__args)...)); } + noexcept(noexcept(__bind_back_t, tuple...>>(std::forward<_Fn>(__f), std::forward_as_tuple(std::forward<_Args>(__args)...)))) + -> decltype( __bind_back_t, tuple...>>(std::forward<_Fn>(__f), std::forward_as_tuple(std::forward<_Args>(__args)...))) + { return __bind_back_t, tuple...>>(std::forward<_Fn>(__f), std::forward_as_tuple(std::forward<_Args>(__args)...)); } #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__functional/bind_front.h b/libcxx/include/__functional/bind_front.h index 7ccd6e563b6e..d47624343876 100644 --- a/libcxx/include/__functional/bind_front.h +++ b/libcxx/include/__functional/bind_front.h @@ -32,9 +32,9 @@ struct __bind_front_op { template _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Args&& ...__args) const - noexcept(noexcept(_VSTD::invoke(_VSTD::forward<_Args>(__args)...))) - -> decltype( _VSTD::invoke(_VSTD::forward<_Args>(__args)...)) - { return _VSTD::invoke(_VSTD::forward<_Args>(__args)...); } + noexcept(noexcept(std::invoke(std::forward<_Args>(__args)...))) + -> decltype( std::invoke(std::forward<_Args>(__args)...)) + { return std::invoke(std::forward<_Args>(__args)...); } }; template @@ -47,7 +47,7 @@ template (is_constructible_v, _Args> && ...) && (is_move_constructible_v> && ...) _LIBCPP_HIDE_FROM_ABI constexpr auto bind_front(_Fn&& __f, _Args&&... __args) { - return __bind_front_t, decay_t<_Args>...>(_VSTD::forward<_Fn>(__f), _VSTD::forward<_Args>(__args)...); + return __bind_front_t, decay_t<_Args>...>(std::forward<_Fn>(__f), std::forward<_Args>(__args)...); } #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__functional/compose.h b/libcxx/include/__functional/compose.h index 80fcd7076c83..af207e7cbafb 100644 --- a/libcxx/include/__functional/compose.h +++ b/libcxx/include/__functional/compose.h @@ -28,9 +28,9 @@ struct __compose_op { template _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Fn1&& __f1, _Fn2&& __f2, _Args&&... __args) const - noexcept(noexcept(_VSTD::invoke(_VSTD::forward<_Fn1>(__f1), _VSTD::invoke(_VSTD::forward<_Fn2>(__f2), _VSTD::forward<_Args>(__args)...)))) - -> decltype( _VSTD::invoke(_VSTD::forward<_Fn1>(__f1), _VSTD::invoke(_VSTD::forward<_Fn2>(__f2), _VSTD::forward<_Args>(__args)...))) - { return _VSTD::invoke(_VSTD::forward<_Fn1>(__f1), _VSTD::invoke(_VSTD::forward<_Fn2>(__f2), _VSTD::forward<_Args>(__args)...)); } + noexcept(noexcept(std::invoke(std::forward<_Fn1>(__f1), std::invoke(std::forward<_Fn2>(__f2), std::forward<_Args>(__args)...)))) + -> decltype( std::invoke(std::forward<_Fn1>(__f1), std::invoke(std::forward<_Fn2>(__f2), std::forward<_Args>(__args)...))) + { return std::invoke(std::forward<_Fn1>(__f1), std::invoke(std::forward<_Fn2>(__f2), std::forward<_Args>(__args)...)); } }; template @@ -41,9 +41,9 @@ struct __compose_t : __perfect_forward<__compose_op, _Fn1, _Fn2> { template _LIBCPP_HIDE_FROM_ABI constexpr auto __compose(_Fn1&& __f1, _Fn2&& __f2) - noexcept(noexcept(__compose_t, decay_t<_Fn2>>(_VSTD::forward<_Fn1>(__f1), _VSTD::forward<_Fn2>(__f2)))) - -> decltype( __compose_t, decay_t<_Fn2>>(_VSTD::forward<_Fn1>(__f1), _VSTD::forward<_Fn2>(__f2))) - { return __compose_t, decay_t<_Fn2>>(_VSTD::forward<_Fn1>(__f1), _VSTD::forward<_Fn2>(__f2)); } + noexcept(noexcept(__compose_t, decay_t<_Fn2>>(std::forward<_Fn1>(__f1), std::forward<_Fn2>(__f2)))) + -> decltype( __compose_t, decay_t<_Fn2>>(std::forward<_Fn1>(__f1), std::forward<_Fn2>(__f2))) + { return __compose_t, decay_t<_Fn2>>(std::forward<_Fn1>(__f1), std::forward<_Fn2>(__f2)); } #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__functional/function.h b/libcxx/include/__functional/function.h index adae29924298..7cc4cccc26cd 100644 --- a/libcxx/include/__functional/function.h +++ b/libcxx/include/__functional/function.h @@ -162,29 +162,29 @@ class __alloc_func<_Fp, _Ap, _Rp(_ArgTypes...)> _LIBCPP_HIDE_FROM_ABI explicit __alloc_func(_Target&& __f) - : __f_(piecewise_construct, _VSTD::forward_as_tuple(_VSTD::move(__f)), - _VSTD::forward_as_tuple()) + : __f_(piecewise_construct, std::forward_as_tuple(std::move(__f)), + std::forward_as_tuple()) { } _LIBCPP_HIDE_FROM_ABI explicit __alloc_func(const _Target& __f, const _Alloc& __a) - : __f_(piecewise_construct, _VSTD::forward_as_tuple(__f), - _VSTD::forward_as_tuple(__a)) + : __f_(piecewise_construct, std::forward_as_tuple(__f), + std::forward_as_tuple(__a)) { } _LIBCPP_HIDE_FROM_ABI explicit __alloc_func(const _Target& __f, _Alloc&& __a) - : __f_(piecewise_construct, _VSTD::forward_as_tuple(__f), - _VSTD::forward_as_tuple(_VSTD::move(__a))) + : __f_(piecewise_construct, std::forward_as_tuple(__f), + std::forward_as_tuple(std::move(__a))) { } _LIBCPP_HIDE_FROM_ABI explicit __alloc_func(_Target&& __f, _Alloc&& __a) - : __f_(piecewise_construct, _VSTD::forward_as_tuple(_VSTD::move(__f)), - _VSTD::forward_as_tuple(_VSTD::move(__a))) + : __f_(piecewise_construct, std::forward_as_tuple(std::move(__f)), + std::forward_as_tuple(std::move(__a))) { } @@ -193,7 +193,7 @@ class __alloc_func<_Fp, _Ap, _Rp(_ArgTypes...)> { typedef __invoke_void_return_wrapper<_Rp> _Invoker; return _Invoker::__call(__f_.first(), - _VSTD::forward<_ArgTypes>(__arg)...); + std::forward<_ArgTypes>(__arg)...); } _LIBCPP_HIDE_FROM_ABI @@ -231,7 +231,7 @@ public: const _Target& __target() const { return __f_; } _LIBCPP_HIDE_FROM_ABI - explicit __default_alloc_func(_Target&& __f) : __f_(_VSTD::move(__f)) {} + explicit __default_alloc_func(_Target&& __f) : __f_(std::move(__f)) {} _LIBCPP_HIDE_FROM_ABI explicit __default_alloc_func(const _Target& __f) : __f_(__f) {} @@ -239,7 +239,7 @@ public: _LIBCPP_HIDE_FROM_ABI _Rp operator()(_ArgTypes&&... __arg) { typedef __invoke_void_return_wrapper<_Rp> _Invoker; - return _Invoker::__call(__f_, _VSTD::forward<_ArgTypes>(__arg)...); + return _Invoker::__call(__f_, std::forward<_ArgTypes>(__arg)...); } _LIBCPP_HIDE_FROM_ABI @@ -296,7 +296,7 @@ class __func<_Fp, _Alloc, _Rp(_ArgTypes...)> public: _LIBCPP_HIDE_FROM_ABI explicit __func(_Fp&& __f) - : __f_(_VSTD::move(__f)) {} + : __f_(std::move(__f)) {} _LIBCPP_HIDE_FROM_ABI explicit __func(const _Fp& __f, const _Alloc& __a) @@ -304,11 +304,11 @@ public: _LIBCPP_HIDE_FROM_ABI explicit __func(const _Fp& __f, _Alloc&& __a) - : __f_(__f, _VSTD::move(__a)) {} + : __f_(__f, std::move(__a)) {} _LIBCPP_HIDE_FROM_ABI explicit __func(_Fp&& __f, _Alloc&& __a) - : __f_(_VSTD::move(__f), _VSTD::move(__a)) {} + : __f_(std::move(__f), std::move(__a)) {} _LIBCPP_HIDE_FROM_ABI_VIRTUAL virtual __base<_Rp(_ArgTypes...)>* __clone() const; _LIBCPP_HIDE_FROM_ABI_VIRTUAL virtual void __clone(__base<_Rp(_ArgTypes...)>*) const; @@ -363,7 +363,7 @@ template _Rp __func<_Fp, _Alloc, _Rp(_ArgTypes...)>::operator()(_ArgTypes&& ... __arg) { - return __f_(_VSTD::forward<_ArgTypes>(__arg)...); + return __f_(std::forward<_ArgTypes>(__arg)...); } #ifndef _LIBCPP_HAS_NO_RTTI @@ -373,7 +373,7 @@ const void* __func<_Fp, _Alloc, _Rp(_ArgTypes...)>::target(const type_info& __ti) const _NOEXCEPT { if (__ti == typeid(_Fp)) - return _VSTD::addressof(__f_.__target()); + return std::addressof(__f_.__target()); return nullptr; } @@ -424,13 +424,13 @@ template class __value_func<_Rp(_ArgTypes...)> is_nothrow_copy_constructible<_FunAlloc>::value) { __f_ = - ::new ((void*)&__buf_) _Fun(_VSTD::move(__f), _Alloc(__af)); + ::new ((void*)&__buf_) _Fun(std::move(__f), _Alloc(__af)); } else { typedef __allocator_destructor<_FunAlloc> _Dp; unique_ptr<__func, _Dp> __hold(__af.allocate(1), _Dp(__af, 1)); - ::new ((void*)__hold.get()) _Fun(_VSTD::move(__f), _Alloc(__a)); + ::new ((void*)__hold.get()) _Fun(std::move(__f), _Alloc(__a)); __f_ = __hold.release(); } } @@ -438,7 +438,7 @@ template class __value_func<_Rp(_ArgTypes...)> template , __value_func>::value, int> = 0> _LIBCPP_HIDE_FROM_ABI explicit __value_func(_Fp&& __f) - : __value_func(_VSTD::forward<_Fp>(__f), allocator<_Fp>()) {} + : __value_func(std::forward<_Fp>(__f), allocator<_Fp>()) {} _LIBCPP_HIDE_FROM_ABI __value_func(const __value_func& __f) @@ -516,7 +516,7 @@ template class __value_func<_Rp(_ArgTypes...)> { if (__f_ == nullptr) __throw_bad_function_call(); - return (*__f_)(_VSTD::forward<_ArgTypes>(__args)...); + return (*__f_)(std::forward<_ArgTypes>(__args)...); } _LIBCPP_HIDE_FROM_ABI @@ -556,7 +556,7 @@ template class __value_func<_Rp(_ArgTypes...)> __f_ = __as_base(&__buf_); } else - _VSTD::swap(__f_, __f.__f_); + std::swap(__f_, __f.__f_); } _LIBCPP_HIDE_FROM_ABI @@ -722,7 +722,7 @@ struct __policy_invoker<_Rp(_ArgTypes...)> _Fun* __f = reinterpret_cast<_Fun*>(__use_small_storage<_Fun>::value ? &__buf->__small : __buf->__large); - return (*__f)(_VSTD::forward<_ArgTypes>(__args)...); + return (*__f)(std::forward<_ArgTypes>(__args)...); } }; @@ -767,14 +767,14 @@ template class __policy_func<_Rp(_ArgTypes...)> if (__use_small_storage<_Fun>()) { ::new ((void*)&__buf_.__small) - _Fun(_VSTD::move(__f), _Alloc(__af)); + _Fun(std::move(__f), _Alloc(__af)); } else { typedef __allocator_destructor<_FunAlloc> _Dp; unique_ptr<_Fun, _Dp> __hold(__af.allocate(1), _Dp(__af, 1)); ::new ((void*)__hold.get()) - _Fun(_VSTD::move(__f), _Alloc(__af)); + _Fun(std::move(__f), _Alloc(__af)); __buf_.__large = __hold.release(); } } @@ -789,11 +789,11 @@ template class __policy_func<_Rp(_ArgTypes...)> __invoker_ = __invoker::template __create<_Fun>(); __policy_ = __policy::__create<_Fun>(); if (__use_small_storage<_Fun>()) { - ::new ((void*)&__buf_.__small) _Fun(_VSTD::move(__f)); + ::new ((void*)&__buf_.__small) _Fun(std::move(__f)); } else { __builtin_new_allocator::__holder_t __hold = __builtin_new_allocator::__allocate_type<_Fun>(1); - __buf_.__large = ::new ((void*)__hold.get()) _Fun(_VSTD::move(__f)); + __buf_.__large = ::new ((void*)__hold.get()) _Fun(std::move(__f)); (void)__hold.release(); } } @@ -853,16 +853,16 @@ template class __policy_func<_Rp(_ArgTypes...)> _LIBCPP_HIDE_FROM_ABI _Rp operator()(_ArgTypes&&... __args) const { - return __invoker_.__call_(_VSTD::addressof(__buf_), - _VSTD::forward<_ArgTypes>(__args)...); + return __invoker_.__call_(std::addressof(__buf_), + std::forward<_ArgTypes>(__args)...); } _LIBCPP_HIDE_FROM_ABI void swap(__policy_func& __f) { - _VSTD::swap(__invoker_, __f.__invoker_); - _VSTD::swap(__policy_, __f.__policy_); - _VSTD::swap(__buf_, __f.__buf_); + std::swap(__invoker_, __f.__invoker_); + std::swap(__policy_, __f.__policy_); + std::swap(__buf_, __f.__buf_); } _LIBCPP_HIDE_FROM_ABI @@ -952,7 +952,7 @@ public: } virtual _Rp operator()(_ArgTypes&& ... __arg) { - return _VSTD::__invoke(__f_, _VSTD::forward<_ArgTypes>(__arg)...); + return std::__invoke(__f_, std::forward<_ArgTypes>(__arg)...); } #ifndef _LIBCPP_HAS_NO_RTTI @@ -1048,7 +1048,7 @@ public: template _LIBCPP_HIDE_FROM_ABI void assign(_Fp&& __f, const _Alloc& __a) - {function(allocator_arg, __a, _VSTD::forward<_Fp>(__f)).swap(*this);} + {function(allocator_arg, __a, std::forward<_Fp>(__f)).swap(*this);} #endif // function capacity: @@ -1098,26 +1098,26 @@ function<_Rp(_ArgTypes...)>::function(allocator_arg_t, const _Alloc&, template function<_Rp(_ArgTypes...)>::function(function&& __f) _NOEXCEPT - : __f_(_VSTD::move(__f.__f_)) {} + : __f_(std::move(__f.__f_)) {} #if _LIBCPP_STD_VER <= 14 template template function<_Rp(_ArgTypes...)>::function(allocator_arg_t, const _Alloc&, function&& __f) - : __f_(_VSTD::move(__f.__f_)) {} + : __f_(std::move(__f.__f_)) {} #endif template template -function<_Rp(_ArgTypes...)>::function(_Fp __f) : __f_(_VSTD::move(__f)) {} +function<_Rp(_ArgTypes...)>::function(_Fp __f) : __f_(std::move(__f)) {} #if _LIBCPP_STD_VER <= 14 template template function<_Rp(_ArgTypes...)>::function(allocator_arg_t, const _Alloc& __a, _Fp __f) - : __f_(_VSTD::move(__f), __a) {} + : __f_(std::move(__f), __a) {} #endif template @@ -1132,7 +1132,7 @@ template function<_Rp(_ArgTypes...)>& function<_Rp(_ArgTypes...)>::operator=(function&& __f) _NOEXCEPT { - __f_ = _VSTD::move(__f.__f_); + __f_ = std::move(__f.__f_); return *this; } @@ -1149,7 +1149,7 @@ template function<_Rp(_ArgTypes...)>& function<_Rp(_ArgTypes...)>::operator=(_Fp&& __f) { - function(_VSTD::forward<_Fp>(__f)).swap(*this); + function(std::forward<_Fp>(__f)).swap(*this); return *this; } @@ -1167,7 +1167,7 @@ template _Rp function<_Rp(_ArgTypes...)>::operator()(_ArgTypes... __arg) const { - return __f_(_VSTD::forward<_ArgTypes>(__arg)...); + return __f_(std::forward<_ArgTypes>(__arg)...); } #ifndef _LIBCPP_HAS_NO_RTTI diff --git a/libcxx/include/__functional/hash.h b/libcxx/include/__functional/hash.h index 87307f7f9934..c369e39ce003 100644 --- a/libcxx/include/__functional/hash.h +++ b/libcxx/include/__functional/hash.h @@ -40,7 +40,7 @@ _Size __loadword(const void* __p) { _Size __r; - _VSTD::memcpy(&__r, __p, sizeof(__r)); + std::memcpy(&__r, __p, sizeof(__r)); return __r; } @@ -127,7 +127,7 @@ struct __murmur2_or_cityhash<_Size, 64> __v = __weak_hash_len_32_with_seeds(__s, __v.second * __k1, __x + __w.first); __w = __weak_hash_len_32_with_seeds(__s + 32, __z + __w.second, __y + std::__loadword<_Size>(__s + 16)); - _VSTD::swap(__z, __x); + std::swap(__z, __x); __s += 64; __len -= 64; } while (__len != 0); diff --git a/libcxx/include/__functional/identity.h b/libcxx/include/__functional/identity.h index 5dffedf677f9..ee92c4130e71 100644 --- a/libcxx/include/__functional/identity.h +++ b/libcxx/include/__functional/identity.h @@ -41,7 +41,7 @@ struct identity { template _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI constexpr _Tp&& operator()(_Tp&& __t) const noexcept { - return _VSTD::forward<_Tp>(__t); + return std::forward<_Tp>(__t); } using is_transparent = void; diff --git a/libcxx/include/__functional/invoke.h b/libcxx/include/__functional/invoke.h index a7dd311074d8..df2f99fe27d6 100644 --- a/libcxx/include/__functional/invoke.h +++ b/libcxx/include/__functional/invoke.h @@ -27,7 +27,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 invoke_result_t<_Fn, _Args.. invoke(_Fn&& __f, _Args&&... __args) noexcept(is_nothrow_invocable_v<_Fn, _Args...>) { - return _VSTD::__invoke(_VSTD::forward<_Fn>(__f), _VSTD::forward<_Args>(__args)...); + return std::__invoke(std::forward<_Fn>(__f), std::forward<_Args>(__args)...); } #endif // _LIBCPP_STD_VER >= 17 diff --git a/libcxx/include/__functional/not_fn.h b/libcxx/include/__functional/not_fn.h index 0cdb1b7e238b..bbd1a8bc35af 100644 --- a/libcxx/include/__functional/not_fn.h +++ b/libcxx/include/__functional/not_fn.h @@ -31,9 +31,9 @@ struct __not_fn_op { template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 auto operator()(_Args&&... __args) const - noexcept(noexcept(!_VSTD::invoke(_VSTD::forward<_Args>(__args)...))) - -> decltype( !_VSTD::invoke(_VSTD::forward<_Args>(__args)...)) - { return !_VSTD::invoke(_VSTD::forward<_Args>(__args)...); } + noexcept(noexcept(!std::invoke(std::forward<_Args>(__args)...))) + -> decltype( !std::invoke(std::forward<_Args>(__args)...)) + { return !std::invoke(std::forward<_Args>(__args)...); } }; template @@ -47,7 +47,7 @@ template > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 auto not_fn(_Fn&& __f) { - return __not_fn_t>(_VSTD::forward<_Fn>(__f)); + return __not_fn_t>(std::forward<_Fn>(__f)); } #endif // _LIBCPP_STD_VER >= 17 diff --git a/libcxx/include/__functional/operations.h b/libcxx/include/__functional/operations.h index a28fdd954780..23928e9fc22d 100644 --- a/libcxx/include/__functional/operations.h +++ b/libcxx/include/__functional/operations.h @@ -55,9 +55,9 @@ struct _LIBCPP_TEMPLATE_VIS plus template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) + _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) + _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) + _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) + std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) + std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) + std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -84,9 +84,9 @@ struct _LIBCPP_TEMPLATE_VIS minus template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) - _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) - _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) - _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) - std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) - std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) - std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -113,9 +113,9 @@ struct _LIBCPP_TEMPLATE_VIS multiplies template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) * _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) * _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) * _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) * std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) * std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) * std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -142,9 +142,9 @@ struct _LIBCPP_TEMPLATE_VIS divides template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) / _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) / _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) / _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) / std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) / std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) / std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -171,9 +171,9 @@ struct _LIBCPP_TEMPLATE_VIS modulus template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) % _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) % _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) % _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) % std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) % std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) % std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -200,9 +200,9 @@ struct _LIBCPP_TEMPLATE_VIS negate template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_Tp&& __x) const - noexcept(noexcept(- _VSTD::forward<_Tp>(__x))) - -> decltype( - _VSTD::forward<_Tp>(__x)) - { return - _VSTD::forward<_Tp>(__x); } + noexcept(noexcept(- std::forward<_Tp>(__x))) + -> decltype( - std::forward<_Tp>(__x)) + { return - std::forward<_Tp>(__x); } typedef void is_transparent; }; #endif @@ -231,9 +231,9 @@ struct _LIBCPP_TEMPLATE_VIS bit_and template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) & _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) & _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) & _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) & std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) & std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) & std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -255,9 +255,9 @@ struct _LIBCPP_TEMPLATE_VIS bit_not template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_Tp&& __x) const - noexcept(noexcept(~_VSTD::forward<_Tp>(__x))) - -> decltype( ~_VSTD::forward<_Tp>(__x)) - { return ~_VSTD::forward<_Tp>(__x); } + noexcept(noexcept(~std::forward<_Tp>(__x))) + -> decltype( ~std::forward<_Tp>(__x)) + { return ~std::forward<_Tp>(__x); } typedef void is_transparent; }; #endif @@ -284,9 +284,9 @@ struct _LIBCPP_TEMPLATE_VIS bit_or template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) | _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) | _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) | _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) | std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) | std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) | std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -313,9 +313,9 @@ struct _LIBCPP_TEMPLATE_VIS bit_xor template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) ^ _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) ^ _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) ^ _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) ^ std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) ^ std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) ^ std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -344,9 +344,9 @@ struct _LIBCPP_TEMPLATE_VIS equal_to template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) == _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) == _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) == _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) == std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) == std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) == std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -382,9 +382,9 @@ struct _LIBCPP_TEMPLATE_VIS not_equal_to template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) != _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) != _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) != _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) != std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) != std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) != std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -411,9 +411,9 @@ struct _LIBCPP_TEMPLATE_VIS less template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) < _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) < _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) < _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) < std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) < std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) < std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -440,9 +440,9 @@ struct _LIBCPP_TEMPLATE_VIS less_equal template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) <= _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) <= _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) <= _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) <= std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) <= std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) <= std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -469,9 +469,9 @@ struct _LIBCPP_TEMPLATE_VIS greater_equal template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) >= _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) >= _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) >= _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) >= std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) >= std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) >= std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -498,9 +498,9 @@ struct _LIBCPP_TEMPLATE_VIS greater template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) > _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) > _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) > _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) > std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) > std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) > std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -529,9 +529,9 @@ struct _LIBCPP_TEMPLATE_VIS logical_and template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) && _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) && _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) && _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) && std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) && std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) && std::forward<_T2>(__u); } typedef void is_transparent; }; #endif @@ -558,9 +558,9 @@ struct _LIBCPP_TEMPLATE_VIS logical_not template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_Tp&& __x) const - noexcept(noexcept(!_VSTD::forward<_Tp>(__x))) - -> decltype( !_VSTD::forward<_Tp>(__x)) - { return !_VSTD::forward<_Tp>(__x); } + noexcept(noexcept(!std::forward<_Tp>(__x))) + -> decltype( !std::forward<_Tp>(__x)) + { return !std::forward<_Tp>(__x); } typedef void is_transparent; }; #endif @@ -587,9 +587,9 @@ struct _LIBCPP_TEMPLATE_VIS logical_or template _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI auto operator()(_T1&& __t, _T2&& __u) const - noexcept(noexcept(_VSTD::forward<_T1>(__t) || _VSTD::forward<_T2>(__u))) - -> decltype( _VSTD::forward<_T1>(__t) || _VSTD::forward<_T2>(__u)) - { return _VSTD::forward<_T1>(__t) || _VSTD::forward<_T2>(__u); } + noexcept(noexcept(std::forward<_T1>(__t) || std::forward<_T2>(__u))) + -> decltype( std::forward<_T1>(__t) || std::forward<_T2>(__u)) + { return std::forward<_T1>(__t) || std::forward<_T2>(__u); } typedef void is_transparent; }; #endif diff --git a/libcxx/include/__functional/perfect_forward.h b/libcxx/include/__functional/perfect_forward.h index b848fbf69631..2fbb623a7d89 100644 --- a/libcxx/include/__functional/perfect_forward.h +++ b/libcxx/include/__functional/perfect_forward.h @@ -44,7 +44,7 @@ public: is_constructible_v, _Args&&...> >> _LIBCPP_HIDE_FROM_ABI explicit constexpr __perfect_forward_impl(_Args&&... __bound_args) - : __bound_args_(_VSTD::forward<_Args>(__bound_args)...) {} + : __bound_args_(std::forward<_Args>(__bound_args)...) {} _LIBCPP_HIDE_FROM_ABI __perfect_forward_impl(__perfect_forward_impl const&) = default; _LIBCPP_HIDE_FROM_ABI __perfect_forward_impl(__perfect_forward_impl&&) = default; @@ -54,36 +54,36 @@ public: template >> _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Args&&... __args) & - noexcept(noexcept(_Op()(_VSTD::get<_Idx>(__bound_args_)..., _VSTD::forward<_Args>(__args)...))) - -> decltype( _Op()(_VSTD::get<_Idx>(__bound_args_)..., _VSTD::forward<_Args>(__args)...)) - { return _Op()(_VSTD::get<_Idx>(__bound_args_)..., _VSTD::forward<_Args>(__args)...); } + noexcept(noexcept(_Op()(std::get<_Idx>(__bound_args_)..., std::forward<_Args>(__args)...))) + -> decltype( _Op()(std::get<_Idx>(__bound_args_)..., std::forward<_Args>(__args)...)) + { return _Op()(std::get<_Idx>(__bound_args_)..., std::forward<_Args>(__args)...); } template >> auto operator()(_Args&&...) & = delete; template >> _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Args&&... __args) const& - noexcept(noexcept(_Op()(_VSTD::get<_Idx>(__bound_args_)..., _VSTD::forward<_Args>(__args)...))) - -> decltype( _Op()(_VSTD::get<_Idx>(__bound_args_)..., _VSTD::forward<_Args>(__args)...)) - { return _Op()(_VSTD::get<_Idx>(__bound_args_)..., _VSTD::forward<_Args>(__args)...); } + noexcept(noexcept(_Op()(std::get<_Idx>(__bound_args_)..., std::forward<_Args>(__args)...))) + -> decltype( _Op()(std::get<_Idx>(__bound_args_)..., std::forward<_Args>(__args)...)) + { return _Op()(std::get<_Idx>(__bound_args_)..., std::forward<_Args>(__args)...); } template >> auto operator()(_Args&&...) const& = delete; template >> _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Args&&... __args) && - noexcept(noexcept(_Op()(_VSTD::get<_Idx>(_VSTD::move(__bound_args_))..., _VSTD::forward<_Args>(__args)...))) - -> decltype( _Op()(_VSTD::get<_Idx>(_VSTD::move(__bound_args_))..., _VSTD::forward<_Args>(__args)...)) - { return _Op()(_VSTD::get<_Idx>(_VSTD::move(__bound_args_))..., _VSTD::forward<_Args>(__args)...); } + noexcept(noexcept(_Op()(std::get<_Idx>(std::move(__bound_args_))..., std::forward<_Args>(__args)...))) + -> decltype( _Op()(std::get<_Idx>(std::move(__bound_args_))..., std::forward<_Args>(__args)...)) + { return _Op()(std::get<_Idx>(std::move(__bound_args_))..., std::forward<_Args>(__args)...); } template >> auto operator()(_Args&&...) && = delete; template >> _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Args&&... __args) const&& - noexcept(noexcept(_Op()(_VSTD::get<_Idx>(_VSTD::move(__bound_args_))..., _VSTD::forward<_Args>(__args)...))) - -> decltype( _Op()(_VSTD::get<_Idx>(_VSTD::move(__bound_args_))..., _VSTD::forward<_Args>(__args)...)) - { return _Op()(_VSTD::get<_Idx>(_VSTD::move(__bound_args_))..., _VSTD::forward<_Args>(__args)...); } + noexcept(noexcept(_Op()(std::get<_Idx>(std::move(__bound_args_))..., std::forward<_Args>(__args)...))) + -> decltype( _Op()(std::get<_Idx>(std::move(__bound_args_))..., std::forward<_Args>(__args)...)) + { return _Op()(std::get<_Idx>(std::move(__bound_args_))..., std::forward<_Args>(__args)...); } template >> auto operator()(_Args&&...) const&& = delete; diff --git a/libcxx/include/__functional/ranges_operations.h b/libcxx/include/__functional/ranges_operations.h index b54589f8c0d8..0ed631d8a74b 100644 --- a/libcxx/include/__functional/ranges_operations.h +++ b/libcxx/include/__functional/ranges_operations.h @@ -31,8 +31,8 @@ struct equal_to { template requires equality_comparable_with<_Tp, _Up> [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool operator()(_Tp &&__t, _Up &&__u) const - noexcept(noexcept(bool(_VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u)))) { - return _VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u); + noexcept(noexcept(bool(std::forward<_Tp>(__t) == std::forward<_Up>(__u)))) { + return std::forward<_Tp>(__t) == std::forward<_Up>(__u); } using is_transparent = void; @@ -42,8 +42,8 @@ struct not_equal_to { template requires equality_comparable_with<_Tp, _Up> [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool operator()(_Tp &&__t, _Up &&__u) const - noexcept(noexcept(bool(!(_VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u))))) { - return !(_VSTD::forward<_Tp>(__t) == _VSTD::forward<_Up>(__u)); + noexcept(noexcept(bool(!(std::forward<_Tp>(__t) == std::forward<_Up>(__u))))) { + return !(std::forward<_Tp>(__t) == std::forward<_Up>(__u)); } using is_transparent = void; @@ -53,8 +53,8 @@ struct less { template requires totally_ordered_with<_Tp, _Up> [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool operator()(_Tp &&__t, _Up &&__u) const - noexcept(noexcept(bool(_VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u)))) { - return _VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u); + noexcept(noexcept(bool(std::forward<_Tp>(__t) < std::forward<_Up>(__u)))) { + return std::forward<_Tp>(__t) < std::forward<_Up>(__u); } using is_transparent = void; @@ -64,8 +64,8 @@ struct less_equal { template requires totally_ordered_with<_Tp, _Up> [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool operator()(_Tp &&__t, _Up &&__u) const - noexcept(noexcept(bool(!(_VSTD::forward<_Up>(__u) < _VSTD::forward<_Tp>(__t))))) { - return !(_VSTD::forward<_Up>(__u) < _VSTD::forward<_Tp>(__t)); + noexcept(noexcept(bool(!(std::forward<_Up>(__u) < std::forward<_Tp>(__t))))) { + return !(std::forward<_Up>(__u) < std::forward<_Tp>(__t)); } using is_transparent = void; @@ -75,8 +75,8 @@ struct greater { template requires totally_ordered_with<_Tp, _Up> [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool operator()(_Tp &&__t, _Up &&__u) const - noexcept(noexcept(bool(_VSTD::forward<_Up>(__u) < _VSTD::forward<_Tp>(__t)))) { - return _VSTD::forward<_Up>(__u) < _VSTD::forward<_Tp>(__t); + noexcept(noexcept(bool(std::forward<_Up>(__u) < std::forward<_Tp>(__t)))) { + return std::forward<_Up>(__u) < std::forward<_Tp>(__t); } using is_transparent = void; @@ -86,8 +86,8 @@ struct greater_equal { template requires totally_ordered_with<_Tp, _Up> [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool operator()(_Tp &&__t, _Up &&__u) const - noexcept(noexcept(bool(!(_VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u))))) { - return !(_VSTD::forward<_Tp>(__t) < _VSTD::forward<_Up>(__u)); + noexcept(noexcept(bool(!(std::forward<_Tp>(__t) < std::forward<_Up>(__u))))) { + return !(std::forward<_Tp>(__t) < std::forward<_Up>(__u)); } using is_transparent = void; diff --git a/libcxx/include/__functional/reference_wrapper.h b/libcxx/include/__functional/reference_wrapper.h index b89916066b80..3688590d10d1 100644 --- a/libcxx/include/__functional/reference_wrapper.h +++ b/libcxx/include/__functional/reference_wrapper.h @@ -42,7 +42,7 @@ public: _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 reference_wrapper(_Up&& __u) _NOEXCEPT_(noexcept(__fun(std::declval<_Up>()))) { type& __f = static_cast<_Up&&>(__u); - __f_ = _VSTD::addressof(__f); + __f_ = std::addressof(__f); } // access diff --git a/libcxx/include/__functional/weak_result_type.h b/libcxx/include/__functional/weak_result_type.h index 18d1bf718c4e..da6fe54bfae7 100644 --- a/libcxx/include/__functional/weak_result_type.h +++ b/libcxx/include/__functional/weak_result_type.h @@ -286,7 +286,7 @@ struct __weak_result_type<_Rp (_Cp::*)(_A1, _A2, _A3...) const volatile> template struct __invoke_return { - typedef decltype(_VSTD::__invoke(std::declval<_Tp>(), std::declval<_Args>()...)) type; + typedef decltype(std::__invoke(std::declval<_Tp>(), std::declval<_Args>()...)) type; }; _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__hash_table b/libcxx/include/__hash_table index 08a5c613849e..fa950ac7e9b7 100644 --- a/libcxx/include/__hash_table +++ b/libcxx/include/__hash_table @@ -199,11 +199,11 @@ struct __hash_key_value_types { } _LIBCPP_HIDE_FROM_ABI static __container_value_type* __get_ptr(__node_value_type& __n) { - return _VSTD::addressof(__n); + return std::addressof(__n); } _LIBCPP_HIDE_FROM_ABI static __container_value_type&& __move(__node_value_type& __v) { - return _VSTD::move(__v); + return std::move(__v); } }; @@ -237,7 +237,7 @@ struct __hash_key_value_types<__hash_value_type<_Key, _Tp> > { _LIBCPP_HIDE_FROM_ABI static __container_value_type* __get_ptr(__node_value_type& __n) { - return _VSTD::addressof(__n.__get_value()); + return std::addressof(__n.__get_value()); } _LIBCPP_HIDE_FROM_ABI static pair __move(__node_value_type& __v) { @@ -643,7 +643,7 @@ public: _LIBCPP_HIDE_FROM_ABI __bucket_list_deallocator(__bucket_list_deallocator&& __x) _NOEXCEPT_(is_nothrow_move_constructible::value) - : __data_(_VSTD::move(__x.__data_)) + : __data_(std::move(__x.__data_)) { __x.size() = 0; } @@ -889,7 +889,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type max_size() const _NOEXCEPT { - return _VSTD::min( + return std::min( __node_traits::max_size(__node_alloc()), numeric_limits::max() ); @@ -929,7 +929,7 @@ public: template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique(_Pp&& __x) { - return __emplace_unique_extract_key(_VSTD::forward<_Pp>(__x), + return __emplace_unique_extract_key(std::forward<_Pp>(__x), __can_extract_key<_Pp, key_type>()); } @@ -938,33 +938,33 @@ public: _LIBCPP_HIDE_FROM_ABI pair __emplace_unique(_First&& __f, _Second&& __s) { - return __emplace_unique_key_args(__f, _VSTD::forward<_First>(__f), - _VSTD::forward<_Second>(__s)); + return __emplace_unique_key_args(__f, std::forward<_First>(__f), + std::forward<_Second>(__s)); } template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique(_Args&&... __args) { - return __emplace_unique_impl(_VSTD::forward<_Args>(__args)...); + return __emplace_unique_impl(std::forward<_Args>(__args)...); } template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique_extract_key(_Pp&& __x, __extract_key_fail_tag) { - return __emplace_unique_impl(_VSTD::forward<_Pp>(__x)); + return __emplace_unique_impl(std::forward<_Pp>(__x)); } template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique_extract_key(_Pp&& __x, __extract_key_self_tag) { - return __emplace_unique_key_args(__x, _VSTD::forward<_Pp>(__x)); + return __emplace_unique_key_args(__x, std::forward<_Pp>(__x)); } template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique_extract_key(_Pp&& __x, __extract_key_first_tag) { - return __emplace_unique_key_args(__x.first, _VSTD::forward<_Pp>(__x)); + return __emplace_unique_key_args(__x.first, std::forward<_Pp>(__x)); } template @@ -978,25 +978,25 @@ public: _LIBCPP_HIDE_FROM_ABI pair __insert_unique(__container_value_type&& __x) { - return __emplace_unique_key_args(_NodeTypes::__get_key(__x), _VSTD::move(__x)); + return __emplace_unique_key_args(_NodeTypes::__get_key(__x), std::move(__x)); } template ::value> > _LIBCPP_HIDE_FROM_ABI pair __insert_unique(_Pp&& __x) { - return __emplace_unique(_VSTD::forward<_Pp>(__x)); + return __emplace_unique(std::forward<_Pp>(__x)); } template _LIBCPP_HIDE_FROM_ABI iterator __insert_multi(_Pp&& __x) { - return __emplace_multi(_VSTD::forward<_Pp>(__x)); + return __emplace_multi(std::forward<_Pp>(__x)); } template _LIBCPP_HIDE_FROM_ABI iterator __insert_multi(const_iterator __p, _Pp&& __x) { - return __emplace_hint_multi(__p, _VSTD::forward<_Pp>(__x)); + return __emplace_hint_multi(__p, std::forward<_Pp>(__x)); } _LIBCPP_HIDE_FROM_ABI @@ -1132,7 +1132,7 @@ public: { _LIBCPP_ASSERT_UNCATEGORIZED(__mlf > 0, "unordered container::max_load_factor(lf) called with lf <= 0"); - max_load_factor() = _VSTD::max(__mlf, load_factor()); + max_load_factor() = std::max(__mlf, load_factor()); } _LIBCPP_HIDE_FROM_ABI @@ -1213,8 +1213,8 @@ private: is_nothrow_move_assignable<__node_allocator>::value) { __bucket_list_.get_deleter().__alloc() = - _VSTD::move(__u.__bucket_list_.get_deleter().__alloc()); - __node_alloc() = _VSTD::move(__u.__node_alloc()); + std::move(__u.__bucket_list_.get_deleter().__alloc()); + __node_alloc() = std::move(__u.__node_alloc()); } _LIBCPP_HIDE_FROM_ABI void __move_assign_alloc(__hash_table&, false_type) _NOEXCEPT {} @@ -1302,10 +1302,10 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__hash_table(__hash_table&& __u) is_nothrow_move_constructible<__node_allocator>::value && is_nothrow_move_constructible::value && is_nothrow_move_constructible::value) - : __bucket_list_(_VSTD::move(__u.__bucket_list_)), - __p1_(_VSTD::move(__u.__p1_)), - __p2_(_VSTD::move(__u.__p2_)), - __p3_(_VSTD::move(__u.__p3_)) + : __bucket_list_(std::move(__u.__bucket_list_)), + __p1_(std::move(__u.__p1_)), + __p2_(std::move(__u.__p2_)), + __p3_(std::move(__u.__p3_)) { if (size() > 0) { @@ -1321,8 +1321,8 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__hash_table(__hash_table&& __u, const allocator_type& __a) : __bucket_list_(nullptr, __bucket_list_deleter(__pointer_allocator(__a), 0)), __p1_(__default_init_tag(), __node_allocator(__a)), - __p2_(0, _VSTD::move(__u.hash_function())), - __p3_(_VSTD::move(__u.__p3_)) + __p2_(0, std::move(__u.hash_function())), + __p3_(std::move(__u.__p3_)) { if (__a == allocator_type(__u.__node_alloc())) { @@ -1373,7 +1373,7 @@ template __hash_table<_Tp, _Hash, _Equal, _Alloc>& __hash_table<_Tp, _Hash, _Equal, _Alloc>::operator=(const __hash_table& __u) { - if (this != _VSTD::addressof(__u)) + if (this != std::addressof(__u)) { __copy_assign_alloc(__u); hash_function() = __u.hash_function(); @@ -1429,9 +1429,9 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__move_assign( __u.__bucket_list_.get_deleter().size() = 0; __move_assign_alloc(__u); size() = __u.size(); - hash_function() = _VSTD::move(__u.hash_function()); + hash_function() = std::move(__u.hash_function()); max_load_factor() = __u.max_load_factor(); - key_eq() = _VSTD::move(__u.key_eq()); + key_eq() = std::move(__u.key_eq()); __p1_.first().__next_ = __u.__p1_.first().__next_; if (size() > 0) { @@ -1451,8 +1451,8 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__move_assign( __move_assign(__u, true_type()); else { - hash_function() = _VSTD::move(__u.hash_function()); - key_eq() = _VSTD::move(__u.key_eq()); + hash_function() = std::move(__u.hash_function()); + key_eq() = std::move(__u.key_eq()); max_load_factor() = __u.max_load_factor(); if (bucket_count() != 0) { @@ -1465,7 +1465,7 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__move_assign( while (__cache != nullptr && __u.size() != 0) { __cache->__upcast()->__get_value() = - _VSTD::move(__u.remove(__i++)->__get_value()); + std::move(__u.remove(__i++)->__get_value()); __next_pointer __next = __cache->__next_; __node_insert_multi(__cache->__upcast()); __cache = __next; @@ -1666,7 +1666,7 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__node_insert_unique_prepare( } if (size()+1 > __bc * max_load_factor() || __bc == 0) { - __rehash_unique(_VSTD::max(2 * __bc + !std::__is_hash_power2(__bc), + __rehash_unique(std::max(2 * __bc + !std::__is_hash_power2(__bc), size_type(std::ceil(float(size() + 1) / max_load_factor())))); } return nullptr; @@ -1738,7 +1738,7 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__node_insert_multi_prepare( size_type __bc = bucket_count(); if (size()+1 > __bc * max_load_factor() || __bc == 0) { - __rehash_multi(_VSTD::max(2 * __bc + !std::__is_hash_power2(__bc), + __rehash_multi(std::max(2 * __bc + !std::__is_hash_power2(__bc), size_type(std::ceil(float(size() + 1) / max_load_factor())))); __bc = bucket_count(); } @@ -1829,7 +1829,7 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__node_insert_multi( size_type __bc = bucket_count(); if (size()+1 > __bc * max_load_factor() || __bc == 0) { - __rehash_multi(_VSTD::max(2 * __bc + !std::__is_hash_power2(__bc), + __rehash_multi(std::max(2 * __bc + !std::__is_hash_power2(__bc), size_type(std::ceil(float(size() + 1) / max_load_factor())))); __bc = bucket_count(); } @@ -1875,10 +1875,10 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__emplace_unique_key_args(_Key const& } } { - __node_holder __h = __construct_node_hash(__hash, _VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node_hash(__hash, std::forward<_Args>(__args)...); if (size()+1 > __bc * max_load_factor() || __bc == 0) { - __rehash_unique(_VSTD::max(2 * __bc + !std::__is_hash_power2(__bc), + __rehash_unique(std::max(2 * __bc + !std::__is_hash_power2(__bc), size_type(std::ceil(float(size() + 1) / max_load_factor())))); __bc = bucket_count(); __chash = std::__constrain_hash(__hash, __bc); @@ -1915,7 +1915,7 @@ template pair::iterator, bool> __hash_table<_Tp, _Hash, _Equal, _Alloc>::__emplace_unique_impl(_Args&&... __args) { - __node_holder __h = __construct_node(_VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node(std::forward<_Args>(__args)...); pair __r = __node_insert_unique(__h.get()); if (__r.second) __h.release(); @@ -1927,7 +1927,7 @@ template typename __hash_table<_Tp, _Hash, _Equal, _Alloc>::iterator __hash_table<_Tp, _Hash, _Equal, _Alloc>::__emplace_multi(_Args&&... __args) { - __node_holder __h = __construct_node(_VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node(std::forward<_Args>(__args)...); iterator __r = __node_insert_multi(__h.get()); __h.release(); return __r; @@ -1939,7 +1939,7 @@ typename __hash_table<_Tp, _Hash, _Equal, _Alloc>::iterator __hash_table<_Tp, _Hash, _Equal, _Alloc>::__emplace_hint_multi( const_iterator __p, _Args&&... __args) { - __node_holder __h = __construct_node(_VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node(std::forward<_Args>(__args)...); iterator __r = __node_insert_multi(__p, __h.get()); __h.release(); return __r; @@ -1958,7 +1958,7 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__node_handle_insert_unique( pair __result = __node_insert_unique(__nh.__ptr_); if (__result.second) __nh.__release_ptr(); - return _InsertReturnType{__result.first, __result.second, _VSTD::move(__nh)}; + return _InsertReturnType{__result.first, __result.second, std::move(__nh)}; } template @@ -2092,7 +2092,7 @@ _LIBCPP_DISABLE_UBSAN_UNSIGNED_INTEGER_CHECK __do_rehash<_UniqueKeys>(__n); else if (__n < __bc) { - __n = _VSTD::max + __n = std::max ( __n, std::__is_hash_power2(__bc) ? std::__next_hash_pow2(size_t(std::ceil(float(size()) / max_load_factor()))) : @@ -2233,7 +2233,7 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__construct_node(_Args&& ...__args) std::__construct_at(std::addressof(*__h), /* next = */nullptr, /* hash = */0); // Now construct the value_type using the allocator's construct() method. - __node_traits::construct(__na, _NodeTypes::__get_ptr(__h->__get_value()), _VSTD::forward<_Args>(__args)...); + __node_traits::construct(__na, _NodeTypes::__get_ptr(__h->__get_value()), std::forward<_Args>(__args)...); __h.get_deleter().__value_constructed = true; __h->__hash_ = hash_function()(__h->__get_value()); @@ -2252,8 +2252,8 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::__construct_node_hash( __node_holder __h(__node_traits::allocate(__na, 1), _Dp(__na)); std::__construct_at(std::addressof(*__h), /* next = */nullptr, /* hash = */__hash); __node_traits::construct(__na, _NodeTypes::__get_ptr(__h->__get_value()), - _VSTD::forward<_First>(__f), - _VSTD::forward<_Rest>(__rest)...); + std::forward<_First>(__f), + std::forward<_Rest>(__rest)...); __h.get_deleter().__value_constructed = true; return __h; } @@ -2472,11 +2472,11 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::swap(__hash_table& __u) __bucket_list_.reset(__u.__bucket_list_.release()); __u.__bucket_list_.reset(__npp); } - _VSTD::swap(__bucket_list_.get_deleter().size(), __u.__bucket_list_.get_deleter().size()); - _VSTD::__swap_allocator(__bucket_list_.get_deleter().__alloc(), + std::swap(__bucket_list_.get_deleter().size(), __u.__bucket_list_.get_deleter().size()); + std::__swap_allocator(__bucket_list_.get_deleter().__alloc(), __u.__bucket_list_.get_deleter().__alloc()); - _VSTD::__swap_allocator(__node_alloc(), __u.__node_alloc()); - _VSTD::swap(__p1_.first().__next_, __u.__p1_.first().__next_); + std::__swap_allocator(__node_alloc(), __u.__node_alloc()); + std::swap(__p1_.first().__next_, __u.__p1_.first().__next_); __p2_.swap(__u.__p2_); __p3_.swap(__u.__p3_); if (size() > 0) diff --git a/libcxx/include/__iterator/advance.h b/libcxx/include/__iterator/advance.h index 04cbe0767ae4..76938970b0c3 100644 --- a/libcxx/include/__iterator/advance.h +++ b/libcxx/include/__iterator/advance.h @@ -60,15 +60,15 @@ void __advance(_RandIter& __i, typename iterator_traits<_RandIter>::difference_t template < class _InputIter, class _Distance, - class _IntegralDistance = decltype(_VSTD::__convert_to_integral(std::declval<_Distance>())), + class _IntegralDistance = decltype(std::__convert_to_integral(std::declval<_Distance>())), class = __enable_if_t::value> > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX17 void advance(_InputIter& __i, _Distance __orig_n) { typedef typename iterator_traits<_InputIter>::difference_type _Difference; - _Difference __n = static_cast<_Difference>(_VSTD::__convert_to_integral(__orig_n)); + _Difference __n = static_cast<_Difference>(std::__convert_to_integral(__orig_n)); _LIBCPP_ASSERT_UNCATEGORIZED(__n >= 0 || __has_bidirectional_iterator_category<_InputIter>::value, "Attempt to advance(it, n) with negative n on a non-bidirectional iterator"); - _VSTD::__advance(__i, __n, typename iterator_traits<_InputIter>::iterator_category()); + std::__advance(__i, __n, typename iterator_traits<_InputIter>::iterator_category()); } #if _LIBCPP_STD_VER >= 20 @@ -128,7 +128,7 @@ public: _LIBCPP_HIDE_FROM_ABI constexpr void operator()(_Ip& __i, _Sp __bound_sentinel) const { // If `I` and `S` model `assignable_from`, equivalent to `i = std::move(bound_sentinel)`. if constexpr (assignable_from<_Ip&, _Sp>) { - __i = _VSTD::move(__bound_sentinel); + __i = std::move(__bound_sentinel); } // Otherwise, if `S` and `I` model `sized_sentinel_for`, equivalent to `ranges::advance(i, bound_sentinel - i)`. else if constexpr (sized_sentinel_for<_Sp, _Ip>) { diff --git a/libcxx/include/__iterator/back_insert_iterator.h b/libcxx/include/__iterator/back_insert_iterator.h index a0083da1519f..f022d3bdf8dd 100644 --- a/libcxx/include/__iterator/back_insert_iterator.h +++ b/libcxx/include/__iterator/back_insert_iterator.h @@ -48,12 +48,12 @@ public: typedef void reference; typedef _Container container_type; - _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 explicit back_insert_iterator(_Container& __x) : container(_VSTD::addressof(__x)) {} + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 explicit back_insert_iterator(_Container& __x) : container(std::addressof(__x)) {} _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 back_insert_iterator& operator=(const typename _Container::value_type& __value) {container->push_back(__value); return *this;} #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 back_insert_iterator& operator=(typename _Container::value_type&& __value) - {container->push_back(_VSTD::move(__value)); return *this;} + {container->push_back(std::move(__value)); return *this;} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 back_insert_iterator& operator*() {return *this;} _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 back_insert_iterator& operator++() {return *this;} diff --git a/libcxx/include/__iterator/common_iterator.h b/libcxx/include/__iterator/common_iterator.h index 6e82b683600e..d7c308d8da00 100644 --- a/libcxx/include/__iterator/common_iterator.h +++ b/libcxx/include/__iterator/common_iterator.h @@ -51,7 +51,7 @@ template _Sent> class common_iterator { struct __proxy { _LIBCPP_HIDE_FROM_ABI constexpr const iter_value_t<_Iter>* operator->() const noexcept { - return _VSTD::addressof(__value_); + return std::addressof(__value_); } iter_value_t<_Iter> __value_; }; @@ -71,8 +71,8 @@ class common_iterator { public: _LIBCPP_HIDE_FROM_ABI common_iterator() requires default_initializable<_Iter> = default; - _LIBCPP_HIDE_FROM_ABI constexpr common_iterator(_Iter __i) : __hold_(in_place_type<_Iter>, _VSTD::move(__i)) {} - _LIBCPP_HIDE_FROM_ABI constexpr common_iterator(_Sent __s) : __hold_(in_place_type<_Sent>, _VSTD::move(__s)) {} + _LIBCPP_HIDE_FROM_ABI constexpr common_iterator(_Iter __i) : __hold_(in_place_type<_Iter>, std::move(__i)) {} + _LIBCPP_HIDE_FROM_ABI constexpr common_iterator(_Sent __s) : __hold_(in_place_type<_Sent>, std::move(__s)) {} template requires convertible_to && convertible_to @@ -81,8 +81,8 @@ public: _LIBCPP_ASSERT_UNCATEGORIZED(!__other.__hold_.valueless_by_exception(), "Attempted to construct from a valueless common_iterator"); if (__other.__hold_.index() == 0) - return variant<_Iter, _Sent>{in_place_index<0>, _VSTD::__unchecked_get<0>(__other.__hold_)}; - return variant<_Iter, _Sent>{in_place_index<1>, _VSTD::__unchecked_get<1>(__other.__hold_)}; + return variant<_Iter, _Sent>{in_place_index<0>, std::__unchecked_get<0>(__other.__hold_)}; + return variant<_Iter, _Sent>{in_place_index<1>, std::__unchecked_get<1>(__other.__hold_)}; }()) {} template @@ -97,15 +97,15 @@ public: // If they're the same index, just assign. if (__idx == 0 && __other_idx == 0) - _VSTD::__unchecked_get<0>(__hold_) = _VSTD::__unchecked_get<0>(__other.__hold_); + std::__unchecked_get<0>(__hold_) = std::__unchecked_get<0>(__other.__hold_); else if (__idx == 1 && __other_idx == 1) - _VSTD::__unchecked_get<1>(__hold_) = _VSTD::__unchecked_get<1>(__other.__hold_); + std::__unchecked_get<1>(__hold_) = std::__unchecked_get<1>(__other.__hold_); // Otherwise replace with the oposite element. else if (__other_idx == 1) - __hold_.template emplace<1>(_VSTD::__unchecked_get<1>(__other.__hold_)); + __hold_.template emplace<1>(std::__unchecked_get<1>(__other.__hold_)); else if (__other_idx == 0) - __hold_.template emplace<0>(_VSTD::__unchecked_get<0>(__other.__hold_)); + __hold_.template emplace<0>(std::__unchecked_get<0>(__other.__hold_)); return *this; } @@ -114,7 +114,7 @@ public: { _LIBCPP_ASSERT_UNCATEGORIZED(std::holds_alternative<_Iter>(__hold_), "Attempted to dereference a non-dereferenceable common_iterator"); - return *_VSTD::__unchecked_get<_Iter>(__hold_); + return *std::__unchecked_get<_Iter>(__hold_); } _LIBCPP_HIDE_FROM_ABI constexpr decltype(auto) operator*() const @@ -122,7 +122,7 @@ public: { _LIBCPP_ASSERT_UNCATEGORIZED(std::holds_alternative<_Iter>(__hold_), "Attempted to dereference a non-dereferenceable common_iterator"); - return *_VSTD::__unchecked_get<_Iter>(__hold_); + return *std::__unchecked_get<_Iter>(__hold_); } template @@ -135,19 +135,19 @@ public: _LIBCPP_ASSERT_UNCATEGORIZED(std::holds_alternative<_Iter>(__hold_), "Attempted to dereference a non-dereferenceable common_iterator"); if constexpr (is_pointer_v<_Iter> || requires(const _Iter& __i) { __i.operator->(); }) { - return _VSTD::__unchecked_get<_Iter>(__hold_); + return std::__unchecked_get<_Iter>(__hold_); } else if constexpr (is_reference_v>) { - auto&& __tmp = *_VSTD::__unchecked_get<_Iter>(__hold_); - return _VSTD::addressof(__tmp); + auto&& __tmp = *std::__unchecked_get<_Iter>(__hold_); + return std::addressof(__tmp); } else { - return __proxy{*_VSTD::__unchecked_get<_Iter>(__hold_)}; + return __proxy{*std::__unchecked_get<_Iter>(__hold_)}; } } _LIBCPP_HIDE_FROM_ABI common_iterator& operator++() { _LIBCPP_ASSERT_UNCATEGORIZED(std::holds_alternative<_Iter>(__hold_), "Attempted to increment a non-dereferenceable common_iterator"); - ++_VSTD::__unchecked_get<_Iter>(__hold_); return *this; + ++std::__unchecked_get<_Iter>(__hold_); return *this; } _LIBCPP_HIDE_FROM_ABI decltype(auto) operator++(int) { @@ -159,7 +159,7 @@ public: return __tmp; } else if constexpr (requires (_Iter& __i) { { *__i++ } -> __can_reference; } || !__can_use_postfix_proxy<_Iter>) { - return _VSTD::__unchecked_get<_Iter>(__hold_)++; + return std::__unchecked_get<_Iter>(__hold_)++; } else { auto __p = __postfix_proxy{**this}; ++*this; @@ -183,9 +183,9 @@ public: return true; if (__x_index == 0) - return _VSTD::__unchecked_get<_Iter>(__x.__hold_) == _VSTD::__unchecked_get<_S2>(__y.__hold_); + return std::__unchecked_get<_Iter>(__x.__hold_) == std::__unchecked_get<_S2>(__y.__hold_); - return _VSTD::__unchecked_get<_Sent>(__x.__hold_) == _VSTD::__unchecked_get<_I2>(__y.__hold_); + return std::__unchecked_get<_Sent>(__x.__hold_) == std::__unchecked_get<_I2>(__y.__hold_); } template _S2> @@ -204,12 +204,12 @@ public: return true; if (__x_index == 0 && __y_index == 0) - return _VSTD::__unchecked_get<_Iter>(__x.__hold_) == _VSTD::__unchecked_get<_I2>(__y.__hold_); + return std::__unchecked_get<_Iter>(__x.__hold_) == std::__unchecked_get<_I2>(__y.__hold_); if (__x_index == 0) - return _VSTD::__unchecked_get<_Iter>(__x.__hold_) == _VSTD::__unchecked_get<_S2>(__y.__hold_); + return std::__unchecked_get<_Iter>(__x.__hold_) == std::__unchecked_get<_S2>(__y.__hold_); - return _VSTD::__unchecked_get<_Sent>(__x.__hold_) == _VSTD::__unchecked_get<_I2>(__y.__hold_); + return std::__unchecked_get<_Sent>(__x.__hold_) == std::__unchecked_get<_I2>(__y.__hold_); } template _I2, sized_sentinel_for<_Iter> _S2> @@ -228,12 +228,12 @@ public: return 0; if (__x_index == 0 && __y_index == 0) - return _VSTD::__unchecked_get<_Iter>(__x.__hold_) - _VSTD::__unchecked_get<_I2>(__y.__hold_); + return std::__unchecked_get<_Iter>(__x.__hold_) - std::__unchecked_get<_I2>(__y.__hold_); if (__x_index == 0) - return _VSTD::__unchecked_get<_Iter>(__x.__hold_) - _VSTD::__unchecked_get<_S2>(__y.__hold_); + return std::__unchecked_get<_Iter>(__x.__hold_) - std::__unchecked_get<_S2>(__y.__hold_); - return _VSTD::__unchecked_get<_Sent>(__x.__hold_) - _VSTD::__unchecked_get<_I2>(__y.__hold_); + return std::__unchecked_get<_Sent>(__x.__hold_) - std::__unchecked_get<_I2>(__y.__hold_); } _LIBCPP_HIDE_FROM_ABI friend constexpr iter_rvalue_reference_t<_Iter> iter_move(const common_iterator& __i) @@ -242,7 +242,7 @@ public: { _LIBCPP_ASSERT_UNCATEGORIZED(std::holds_alternative<_Iter>(__i.__hold_), "Attempted to iter_move a non-dereferenceable common_iterator"); - return ranges::iter_move( _VSTD::__unchecked_get<_Iter>(__i.__hold_)); + return ranges::iter_move( std::__unchecked_get<_Iter>(__i.__hold_)); } template _I2, class _S2> @@ -253,7 +253,7 @@ public: "Attempted to iter_swap a non-dereferenceable common_iterator"); _LIBCPP_ASSERT_UNCATEGORIZED(std::holds_alternative<_I2>(__y.__hold_), "Attempted to iter_swap a non-dereferenceable common_iterator"); - return ranges::iter_swap(_VSTD::__unchecked_get<_Iter>(__x.__hold_), _VSTD::__unchecked_get<_I2>(__y.__hold_)); + return ranges::iter_swap(std::__unchecked_get<_Iter>(__x.__hold_), std::__unchecked_get<_I2>(__y.__hold_)); } }; diff --git a/libcxx/include/__iterator/concepts.h b/libcxx/include/__iterator/concepts.h index d317273a7bb2..614de85847a0 100644 --- a/libcxx/include/__iterator/concepts.h +++ b/libcxx/include/__iterator/concepts.h @@ -72,10 +72,10 @@ using iter_common_reference_t = common_reference_t, iter_v template concept indirectly_writable = requires(_Out&& __o, _Tp&& __t) { - *__o = _VSTD::forward<_Tp>(__t); // not required to be equality-preserving - *_VSTD::forward<_Out>(__o) = _VSTD::forward<_Tp>(__t); // not required to be equality-preserving - const_cast&&>(*__o) = _VSTD::forward<_Tp>(__t); // not required to be equality-preserving - const_cast&&>(*_VSTD::forward<_Out>(__o)) = _VSTD::forward<_Tp>(__t); // not required to be equality-preserving + *__o = std::forward<_Tp>(__t); // not required to be equality-preserving + *std::forward<_Out>(__o) = std::forward<_Tp>(__t); // not required to be equality-preserving + const_cast&&>(*__o) = std::forward<_Tp>(__t); // not required to be equality-preserving + const_cast&&>(*std::forward<_Out>(__o)) = std::forward<_Tp>(__t); // not required to be equality-preserving }; // [iterator.concept.winc] @@ -147,7 +147,7 @@ concept output_iterator = input_or_output_iterator<_Ip> && indirectly_writable<_Ip, _Tp> && requires (_Ip __it, _Tp&& __t) { - *__it++ = _VSTD::forward<_Tp>(__t); // not required to be equality-preserving + *__it++ = std::forward<_Tp>(__t); // not required to be equality-preserving }; // [iterator.concept.forward] @@ -190,7 +190,7 @@ concept contiguous_iterator = is_lvalue_reference_v> && same_as, remove_cvref_t>> && requires(const _Ip& __i) { - { _VSTD::to_address(__i) } -> same_as>>; + { std::to_address(__i) } -> same_as>>; }; template diff --git a/libcxx/include/__iterator/counted_iterator.h b/libcxx/include/__iterator/counted_iterator.h index 306b5f36c6e0..171c0d7f0e77 100644 --- a/libcxx/include/__iterator/counted_iterator.h +++ b/libcxx/include/__iterator/counted_iterator.h @@ -82,7 +82,7 @@ public: _LIBCPP_HIDE_FROM_ABI constexpr counted_iterator(_Iter __iter, iter_difference_t<_Iter> __n) - : __current_(_VSTD::move(__iter)), __count_(__n) { + : __current_(std::move(__iter)), __count_(__n) { _LIBCPP_ASSERT_UNCATEGORIZED(__n >= 0, "__n must not be negative."); } @@ -105,7 +105,7 @@ public: constexpr const _Iter& base() const& noexcept { return __current_; } _LIBCPP_HIDE_FROM_ABI - constexpr _Iter base() && { return _VSTD::move(__current_); } + constexpr _Iter base() && { return std::move(__current_); } _LIBCPP_HIDE_FROM_ABI constexpr iter_difference_t<_Iter> count() const noexcept { return __count_; } @@ -128,7 +128,7 @@ public: constexpr auto operator->() const noexcept requires contiguous_iterator<_Iter> { - return _VSTD::to_address(__current_); + return std::to_address(__current_); } _LIBCPP_HIDE_FROM_ABI diff --git a/libcxx/include/__iterator/distance.h b/libcxx/include/__iterator/distance.h index 49294752c4f4..83a926539095 100644 --- a/libcxx/include/__iterator/distance.h +++ b/libcxx/include/__iterator/distance.h @@ -50,7 +50,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX17 typename iterator_traits<_InputIter>::difference_type distance(_InputIter __first, _InputIter __last) { - return _VSTD::__distance(__first, __last, typename iterator_traits<_InputIter>::iterator_category()); + return std::__distance(__first, __last, typename iterator_traits<_InputIter>::iterator_category()); } #if _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__iterator/front_insert_iterator.h b/libcxx/include/__iterator/front_insert_iterator.h index d1bfbc3fcb3f..f9aa442177b2 100644 --- a/libcxx/include/__iterator/front_insert_iterator.h +++ b/libcxx/include/__iterator/front_insert_iterator.h @@ -48,12 +48,12 @@ public: typedef void reference; typedef _Container container_type; - _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 explicit front_insert_iterator(_Container& __x) : container(_VSTD::addressof(__x)) {} + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 explicit front_insert_iterator(_Container& __x) : container(std::addressof(__x)) {} _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 front_insert_iterator& operator=(const typename _Container::value_type& __value) {container->push_front(__value); return *this;} #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 front_insert_iterator& operator=(typename _Container::value_type&& __value) - {container->push_front(_VSTD::move(__value)); return *this;} + {container->push_front(std::move(__value)); return *this;} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 front_insert_iterator& operator*() {return *this;} _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 front_insert_iterator& operator++() {return *this;} diff --git a/libcxx/include/__iterator/insert_iterator.h b/libcxx/include/__iterator/insert_iterator.h index 8ed90dd4b15a..1a9c74a16f4f 100644 --- a/libcxx/include/__iterator/insert_iterator.h +++ b/libcxx/include/__iterator/insert_iterator.h @@ -59,12 +59,12 @@ public: typedef _Container container_type; _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 insert_iterator(_Container& __x, __insert_iterator_iter_t<_Container> __i) - : container(_VSTD::addressof(__x)), iter(__i) {} + : container(std::addressof(__x)), iter(__i) {} _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 insert_iterator& operator=(const typename _Container::value_type& __value) {iter = container->insert(iter, __value); ++iter; return *this;} #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 insert_iterator& operator=(typename _Container::value_type&& __value) - {iter = container->insert(iter, _VSTD::move(__value)); ++iter; return *this;} + {iter = container->insert(iter, std::move(__value)); ++iter; return *this;} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 insert_iterator& operator*() {return *this;} _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 insert_iterator& operator++() {return *this;} diff --git a/libcxx/include/__iterator/istream_iterator.h b/libcxx/include/__iterator/istream_iterator.h index 6a36b1977f01..2efe5772ba61 100644 --- a/libcxx/include/__iterator/istream_iterator.h +++ b/libcxx/include/__iterator/istream_iterator.h @@ -51,14 +51,14 @@ public: #if _LIBCPP_STD_VER >= 20 _LIBCPP_HIDE_FROM_ABI constexpr istream_iterator(default_sentinel_t) : istream_iterator() {} #endif // _LIBCPP_STD_VER >= 20 - _LIBCPP_HIDE_FROM_ABI istream_iterator(istream_type& __s) : __in_stream_(_VSTD::addressof(__s)) + _LIBCPP_HIDE_FROM_ABI istream_iterator(istream_type& __s) : __in_stream_(std::addressof(__s)) { if (!(*__in_stream_ >> __value_)) __in_stream_ = nullptr; } _LIBCPP_HIDE_FROM_ABI const _Tp& operator*() const {return __value_;} - _LIBCPP_HIDE_FROM_ABI const _Tp* operator->() const {return _VSTD::addressof((operator*()));} + _LIBCPP_HIDE_FROM_ABI const _Tp* operator->() const {return std::addressof((operator*()));} _LIBCPP_HIDE_FROM_ABI istream_iterator& operator++() { if (!(*__in_stream_ >> __value_)) diff --git a/libcxx/include/__iterator/iter_swap.h b/libcxx/include/__iterator/iter_swap.h index 2fa92f6ef232..23d3e4009f53 100644 --- a/libcxx/include/__iterator/iter_swap.h +++ b/libcxx/include/__iterator/iter_swap.h @@ -45,7 +45,7 @@ namespace __iter_swap { (__class_or_enum> || __class_or_enum>) && requires (_T1&& __x, _T2&& __y) { // NOLINTNEXTLINE(libcpp-robust-against-adl) iter_swap ADL calls should only be made through ranges::iter_swap - iter_swap(_VSTD::forward<_T1>(__x), _VSTD::forward<_T2>(__y)); + iter_swap(std::forward<_T1>(__x), std::forward<_T2>(__y)); }; template @@ -60,9 +60,9 @@ namespace __iter_swap { requires __unqualified_iter_swap<_T1, _T2> _LIBCPP_HIDE_FROM_ABI constexpr void operator()(_T1&& __x, _T2&& __y) const - noexcept(noexcept(iter_swap(_VSTD::forward<_T1>(__x), _VSTD::forward<_T2>(__y)))) + noexcept(noexcept(iter_swap(std::forward<_T1>(__x), std::forward<_T2>(__y)))) { - (void)iter_swap(_VSTD::forward<_T1>(__x), _VSTD::forward<_T2>(__y)); + (void)iter_swap(std::forward<_T1>(__x), std::forward<_T2>(__y)); } // NOLINTEND(libcpp-robust-against-adl) @@ -71,25 +71,25 @@ namespace __iter_swap { __readable_swappable<_T1, _T2> _LIBCPP_HIDE_FROM_ABI constexpr void operator()(_T1&& __x, _T2&& __y) const - noexcept(noexcept(ranges::swap(*_VSTD::forward<_T1>(__x), *_VSTD::forward<_T2>(__y)))) + noexcept(noexcept(ranges::swap(*std::forward<_T1>(__x), *std::forward<_T2>(__y)))) { - ranges::swap(*_VSTD::forward<_T1>(__x), *_VSTD::forward<_T2>(__y)); + ranges::swap(*std::forward<_T1>(__x), *std::forward<_T2>(__y)); } template - requires (!__unqualified_iter_swap<_T1, _T2> && - !__readable_swappable<_T1, _T2>) && - indirectly_movable_storable<_T1, _T2> && + requires (!__unqualified_iter_swap<_T1, _T2> && // + !__readable_swappable<_T1, _T2>) && // + indirectly_movable_storable<_T1, _T2> && // indirectly_movable_storable<_T2, _T1> _LIBCPP_HIDE_FROM_ABI constexpr void operator()(_T1&& __x, _T2&& __y) const - noexcept(noexcept(iter_value_t<_T2>(ranges::iter_move(__y))) && - noexcept(*__y = ranges::iter_move(__x)) && - noexcept(*_VSTD::forward<_T1>(__x) = std::declval>())) + noexcept(noexcept(iter_value_t<_T2>(ranges::iter_move(__y))) && // + noexcept(*__y = ranges::iter_move(__x)) && // + noexcept(*std::forward<_T1>(__x) = std::declval>())) { iter_value_t<_T2> __old(ranges::iter_move(__y)); *__y = ranges::iter_move(__x); - *_VSTD::forward<_T1>(__x) = _VSTD::move(__old); + *std::forward<_T1>(__x) = std::move(__old); } }; } // namespace __iter_swap diff --git a/libcxx/include/__iterator/next.h b/libcxx/include/__iterator/next.h index ab9b7e223956..ae98229bdabf 100644 --- a/libcxx/include/__iterator/next.h +++ b/libcxx/include/__iterator/next.h @@ -31,7 +31,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX17 _LIBCPP_ASSERT_UNCATEGORIZED(__n >= 0 || __has_bidirectional_iterator_category<_InputIter>::value, "Attempt to next(it, n) with negative n on a non-bidirectional iterator"); - _VSTD::advance(__x, __n); + std::advance(__x, __n); return __x; } diff --git a/libcxx/include/__iterator/ostream_iterator.h b/libcxx/include/__iterator/ostream_iterator.h index 6fc22b2b8162..381f75832fc6 100644 --- a/libcxx/include/__iterator/ostream_iterator.h +++ b/libcxx/include/__iterator/ostream_iterator.h @@ -51,9 +51,9 @@ private: const char_type* __delim_; public: _LIBCPP_HIDE_FROM_ABI ostream_iterator(ostream_type& __s) _NOEXCEPT - : __out_stream_(_VSTD::addressof(__s)), __delim_(nullptr) {} + : __out_stream_(std::addressof(__s)), __delim_(nullptr) {} _LIBCPP_HIDE_FROM_ABI ostream_iterator(ostream_type& __s, const _CharT* __delimiter) _NOEXCEPT - : __out_stream_(_VSTD::addressof(__s)), __delim_(__delimiter) {} + : __out_stream_(std::addressof(__s)), __delim_(__delimiter) {} _LIBCPP_HIDE_FROM_ABI ostream_iterator& operator=(const _Tp& __value) { *__out_stream_ << __value; diff --git a/libcxx/include/__iterator/prev.h b/libcxx/include/__iterator/prev.h index ab6101f30db6..3bc29a27e743 100644 --- a/libcxx/include/__iterator/prev.h +++ b/libcxx/include/__iterator/prev.h @@ -30,7 +30,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX17 prev(_InputIter __x, typename iterator_traits<_InputIter>::difference_type __n = 1) { _LIBCPP_ASSERT_UNCATEGORIZED(__n <= 0 || __has_bidirectional_iterator_category<_InputIter>::value, "Attempt to prev(it, n) with a positive n on a non-bidirectional iterator"); - _VSTD::advance(__x, -__n); + std::advance(__x, -__n); return __x; } diff --git a/libcxx/include/__iterator/reverse_access.h b/libcxx/include/__iterator/reverse_access.h index 0857d4aecc5d..5e01f667e115 100644 --- a/libcxx/include/__iterator/reverse_access.h +++ b/libcxx/include/__iterator/reverse_access.h @@ -81,16 +81,16 @@ auto rend(const _Cp& __c) -> decltype(__c.rend()) template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX17 -auto crbegin(const _Cp& __c) -> decltype(_VSTD::rbegin(__c)) +auto crbegin(const _Cp& __c) -> decltype(std::rbegin(__c)) { - return _VSTD::rbegin(__c); + return std::rbegin(__c); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX17 -auto crend(const _Cp& __c) -> decltype(_VSTD::rend(__c)) +auto crend(const _Cp& __c) -> decltype(std::rend(__c)) { - return _VSTD::rend(__c); + return std::rend(__c); } #endif // _LIBCPP_STD_VER >= 14 diff --git a/libcxx/include/__iterator/wrap_iter.h b/libcxx/include/__iterator/wrap_iter.h index 8cab2179cfef..d028d7b3c33c 100644 --- a/libcxx/include/__iterator/wrap_iter.h +++ b/libcxx/include/__iterator/wrap_iter.h @@ -56,7 +56,7 @@ public: } _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 pointer operator->() const _NOEXCEPT { - return _VSTD::__to_address(__i_); + return std::__to_address(__i_); } _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 __wrap_iter& operator++() _NOEXCEPT { @@ -222,7 +222,7 @@ struct _LIBCPP_TEMPLATE_VIS pointer_traits<__wrap_iter<_It> > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR static element_type *to_address(pointer __w) _NOEXCEPT { - return _VSTD::__to_address(__w.base()); + return std::__to_address(__w.base()); } }; diff --git a/libcxx/include/__locale b/libcxx/include/__locale index 78c2fc1d9d10..ab36939f9c14 100644 --- a/libcxx/include/__locale +++ b/libcxx/include/__locale @@ -186,10 +186,10 @@ template locale locale::combine(const locale& __other) const { - if (!_VSTD::has_facet<_Facet>(__other)) + if (!std::has_facet<_Facet>(__other)) __throw_runtime_error("locale::combine: locale missing facet"); - return locale(*this, &const_cast<_Facet&>(_VSTD::use_facet<_Facet>(__other))); + return locale(*this, &const_cast<_Facet&>(std::use_facet<_Facet>(__other))); } template @@ -348,7 +348,7 @@ bool locale::operator()(const basic_string<_CharT, _Traits, _Allocator>& __x, const basic_string<_CharT, _Traits, _Allocator>& __y) const { - return _VSTD::use_facet<_VSTD::collate<_CharT> >(*this).compare( + return std::use_facet >(*this).compare( __x.data(), __x.data() + __x.size(), __y.data(), __y.data() + __y.size()) < 0; } diff --git a/libcxx/include/__locale_dir/locale_base_api/locale_guard.h b/libcxx/include/__locale_dir/locale_base_api/locale_guard.h index 836742b6e758..efe674b5e7b3 100644 --- a/libcxx/include/__locale_dir/locale_base_api/locale_guard.h +++ b/libcxx/include/__locale_dir/locale_base_api/locale_guard.h @@ -46,7 +46,7 @@ struct __libcpp_locale_guard { // locale name, otherwise it will be a semicolon-separated string listing // each category. In the second case, we know at least one category won't // be what we want, so we only have to check the first case. - if (_VSTD::strcmp(__l.__get_locale(), __lc) != 0) { + if (std::strcmp(__l.__get_locale(), __lc) != 0) { __locale_all = _strdup(__lc); if (__locale_all == nullptr) __throw_bad_alloc(); diff --git a/libcxx/include/__memory/allocation_guard.h b/libcxx/include/__memory/allocation_guard.h index f63b17430ed1..c36ce15397c0 100644 --- a/libcxx/include/__memory/allocation_guard.h +++ b/libcxx/include/__memory/allocation_guard.h @@ -52,7 +52,7 @@ struct __allocation_guard { template // we perform the allocator conversion inside the constructor _LIBCPP_HIDE_FROM_ABI explicit __allocation_guard(_AllocT __alloc, _Size __n) - : __alloc_(_VSTD::move(__alloc)) + : __alloc_(std::move(__alloc)) , __n_(__n) , __ptr_(allocator_traits<_Alloc>::allocate(__alloc_, __n_)) // initialization order is important { } diff --git a/libcxx/include/__memory/allocator.h b/libcxx/include/__memory/allocator.h index 1c6429fbe833..7568da799782 100644 --- a/libcxx/include/__memory/allocator.h +++ b/libcxx/include/__memory/allocator.h @@ -111,7 +111,7 @@ public: if (__libcpp_is_constant_evaluated()) { return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp))); } else { - return static_cast<_Tp*>(_VSTD::__libcpp_allocate(__n * sizeof(_Tp), _LIBCPP_ALIGNOF(_Tp))); + return static_cast<_Tp*>(std::__libcpp_allocate(__n * sizeof(_Tp), _LIBCPP_ALIGNOF(_Tp))); } } @@ -127,7 +127,7 @@ public: if (__libcpp_is_constant_evaluated()) { ::operator delete(__p); } else { - _VSTD::__libcpp_deallocate((void*)__p, __n * sizeof(_Tp), _LIBCPP_ALIGNOF(_Tp)); + std::__libcpp_deallocate((void*)__p, __n * sizeof(_Tp), _LIBCPP_ALIGNOF(_Tp)); } } @@ -145,11 +145,11 @@ public: _LIBCPP_DEPRECATED_IN_CXX17 _LIBCPP_HIDE_FROM_ABI pointer address(reference __x) const _NOEXCEPT { - return _VSTD::addressof(__x); + return std::addressof(__x); } _LIBCPP_DEPRECATED_IN_CXX17 _LIBCPP_HIDE_FROM_ABI const_pointer address(const_reference __x) const _NOEXCEPT { - return _VSTD::addressof(__x); + return std::addressof(__x); } _LIBCPP_NODISCARD_AFTER_CXX17 _LIBCPP_HIDE_FROM_ABI _LIBCPP_DEPRECATED_IN_CXX17 @@ -164,7 +164,7 @@ public: template _LIBCPP_DEPRECATED_IN_CXX17 _LIBCPP_HIDE_FROM_ABI void construct(_Up* __p, _Args&&... __args) { - ::new ((void*)__p) _Up(_VSTD::forward<_Args>(__args)...); + ::new ((void*)__p) _Up(std::forward<_Args>(__args)...); } _LIBCPP_DEPRECATED_IN_CXX17 _LIBCPP_HIDE_FROM_ABI @@ -199,7 +199,7 @@ public: if (__libcpp_is_constant_evaluated()) { return static_cast(::operator new(__n * sizeof(_Tp))); } else { - return static_cast(_VSTD::__libcpp_allocate(__n * sizeof(_Tp), _LIBCPP_ALIGNOF(_Tp))); + return static_cast(std::__libcpp_allocate(__n * sizeof(_Tp), _LIBCPP_ALIGNOF(_Tp))); } } @@ -215,7 +215,7 @@ public: if (__libcpp_is_constant_evaluated()) { ::operator delete(const_cast<_Tp*>(__p)); } else { - _VSTD::__libcpp_deallocate((void*) const_cast<_Tp *>(__p), __n * sizeof(_Tp), _LIBCPP_ALIGNOF(_Tp)); + std::__libcpp_deallocate((void*) const_cast<_Tp *>(__p), __n * sizeof(_Tp), _LIBCPP_ALIGNOF(_Tp)); } } @@ -233,7 +233,7 @@ public: _LIBCPP_DEPRECATED_IN_CXX17 _LIBCPP_HIDE_FROM_ABI const_pointer address(const_reference __x) const _NOEXCEPT { - return _VSTD::addressof(__x); + return std::addressof(__x); } _LIBCPP_NODISCARD_AFTER_CXX17 _LIBCPP_HIDE_FROM_ABI _LIBCPP_DEPRECATED_IN_CXX17 @@ -248,7 +248,7 @@ public: template _LIBCPP_DEPRECATED_IN_CXX17 _LIBCPP_HIDE_FROM_ABI void construct(_Up* __p, _Args&&... __args) { - ::new ((void*)__p) _Up(_VSTD::forward<_Args>(__args)...); + ::new ((void*)__p) _Up(std::forward<_Args>(__args)...); } _LIBCPP_DEPRECATED_IN_CXX17 _LIBCPP_HIDE_FROM_ABI diff --git a/libcxx/include/__memory/allocator_arg_t.h b/libcxx/include/__memory/allocator_arg_t.h index d103c03af0c8..09a015acdf11 100644 --- a/libcxx/include/__memory/allocator_arg_t.h +++ b/libcxx/include/__memory/allocator_arg_t.h @@ -54,7 +54,7 @@ template inline _LIBCPP_HIDE_FROM_ABI void __user_alloc_construct_impl (integral_constant, _Tp *__storage, const _Allocator &, _Args &&... __args ) { - new (__storage) _Tp (_VSTD::forward<_Args>(__args)...); + new (__storage) _Tp (std::forward<_Args>(__args)...); } // FIXME: This should have a version which takes a non-const alloc. @@ -62,7 +62,7 @@ template inline _LIBCPP_HIDE_FROM_ABI void __user_alloc_construct_impl (integral_constant, _Tp *__storage, const _Allocator &__a, _Args &&... __args ) { - new (__storage) _Tp (allocator_arg, __a, _VSTD::forward<_Args>(__args)...); + new (__storage) _Tp (allocator_arg, __a, std::forward<_Args>(__args)...); } // FIXME: This should have a version which takes a non-const alloc. @@ -70,7 +70,7 @@ template inline _LIBCPP_HIDE_FROM_ABI void __user_alloc_construct_impl (integral_constant, _Tp *__storage, const _Allocator &__a, _Args &&... __args ) { - new (__storage) _Tp (_VSTD::forward<_Args>(__args)..., __a); + new (__storage) _Tp (std::forward<_Args>(__args)..., __a); } #endif // _LIBCPP_CXX03_LANG diff --git a/libcxx/include/__memory/allocator_traits.h b/libcxx/include/__memory/allocator_traits.h index d55c7c159d3a..c5db3e896fad 100644 --- a/libcxx/include/__memory/allocator_traits.h +++ b/libcxx/include/__memory/allocator_traits.h @@ -293,7 +293,7 @@ struct _LIBCPP_TEMPLATE_VIS allocator_traits _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 static void construct(allocator_type& __a, _Tp* __p, _Args&&... __args) { _LIBCPP_SUPPRESS_DEPRECATED_PUSH - __a.construct(__p, _VSTD::forward<_Args>(__args)...); + __a.construct(__p, std::forward<_Args>(__args)...); _LIBCPP_SUPPRESS_DEPRECATED_POP } template __holder_t; _LIBCPP_HIDE_FROM_ABI static __holder_t __allocate_bytes(size_t __s, size_t __align) { - return __holder_t(_VSTD::__libcpp_allocate(__s, __align), + return __holder_t(std::__libcpp_allocate(__s, __align), __builtin_new_deleter(__s, __align)); } _LIBCPP_HIDE_FROM_ABI static void __deallocate_bytes(void* __p, size_t __s, size_t __align) _NOEXCEPT { - _VSTD::__libcpp_deallocate(__p, __s, __align); + std::__libcpp_deallocate(__p, __s, __align); } template diff --git a/libcxx/include/__memory/pointer_traits.h b/libcxx/include/__memory/pointer_traits.h index 0569149f21b9..7fcf3bf06110 100644 --- a/libcxx/include/__memory/pointer_traits.h +++ b/libcxx/include/__memory/pointer_traits.h @@ -156,7 +156,7 @@ private: public: _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 static pointer pointer_to(__conditional_t::value, __nat, element_type>& __r) _NOEXCEPT - {return _VSTD::addressof(__r);} + {return std::addressof(__r);} }; #ifndef _LIBCPP_CXX03_LANG @@ -213,9 +213,9 @@ __to_address(const _Pointer& __p) _NOEXCEPT { template struct __to_address_helper { _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR - static decltype(_VSTD::__to_address(std::declval().operator->())) + static decltype(std::__to_address(std::declval().operator->())) __call(const _Pointer& __p) _NOEXCEPT { - return _VSTD::__to_address(__p.operator->()); + return std::__to_address(__p.operator->()); } }; @@ -232,13 +232,13 @@ struct __to_address_helper<_Pointer, decltype((void)pointer_traits<_Pointer>::to template inline _LIBCPP_HIDE_FROM_ABI constexpr auto to_address(_Tp *__p) noexcept { - return _VSTD::__to_address(__p); + return std::__to_address(__p); } template inline _LIBCPP_HIDE_FROM_ABI constexpr auto to_address(const _Pointer& __p) noexcept -> decltype(std::__to_address(__p)) { - return _VSTD::__to_address(__p); + return std::__to_address(__p); } #endif diff --git a/libcxx/include/__memory/ranges_construct_at.h b/libcxx/include/__memory/ranges_construct_at.h index ed800f4a75b4..b6008a7b7f03 100644 --- a/libcxx/include/__memory/ranges_construct_at.h +++ b/libcxx/include/__memory/ranges_construct_at.h @@ -46,7 +46,7 @@ struct __fn { )> _LIBCPP_HIDE_FROM_ABI constexpr _Tp* operator()(_Tp* __location, _Args&& ...__args) const { - return _VSTD::construct_at(__location, _VSTD::forward<_Args>(__args)...); + return std::construct_at(__location, std::forward<_Args>(__args)...); } }; @@ -64,7 +64,7 @@ struct __fn { template _LIBCPP_HIDE_FROM_ABI constexpr void operator()(_Tp* __location) const noexcept { - _VSTD::destroy_at(__location); + std::destroy_at(__location); } }; @@ -83,7 +83,7 @@ struct __fn { requires destructible> _LIBCPP_HIDE_FROM_ABI constexpr _InputIterator operator()(_InputIterator __first, _Sentinel __last) const noexcept { - return _VSTD::__destroy(_VSTD::move(__first), _VSTD::move(__last)); + return std::__destroy(std::move(__first), std::move(__last)); } template <__nothrow_input_range _InputRange> @@ -109,7 +109,7 @@ struct __fn { requires destructible> _LIBCPP_HIDE_FROM_ABI constexpr _InputIterator operator()(_InputIterator __first, iter_difference_t<_InputIterator> __n) const noexcept { - return _VSTD::destroy_n(_VSTD::move(__first), __n); + return std::destroy_n(std::move(__first), __n); } }; diff --git a/libcxx/include/__memory/ranges_uninitialized_algorithms.h b/libcxx/include/__memory/ranges_uninitialized_algorithms.h index 96b6a9a99765..513fcf70f154 100644 --- a/libcxx/include/__memory/ranges_uninitialized_algorithms.h +++ b/libcxx/include/__memory/ranges_uninitialized_algorithms.h @@ -47,8 +47,8 @@ struct __fn { requires default_initializable> _LIBCPP_HIDE_FROM_ABI _ForwardIterator operator()(_ForwardIterator __first, _Sentinel __last) const { using _ValueType = remove_reference_t>; - return _VSTD::__uninitialized_default_construct<_ValueType>( - _VSTD::move(__first), _VSTD::move(__last)); + return std::__uninitialized_default_construct<_ValueType>( + std::move(__first), std::move(__last)); } template <__nothrow_forward_range _ForwardRange> @@ -74,7 +74,7 @@ struct __fn { _LIBCPP_HIDE_FROM_ABI _ForwardIterator operator()(_ForwardIterator __first, iter_difference_t<_ForwardIterator> __n) const { using _ValueType = remove_reference_t>; - return _VSTD::__uninitialized_default_construct_n<_ValueType>(_VSTD::move(__first), __n); + return std::__uninitialized_default_construct_n<_ValueType>(std::move(__first), __n); } }; @@ -94,8 +94,8 @@ struct __fn { requires default_initializable> _LIBCPP_HIDE_FROM_ABI _ForwardIterator operator()(_ForwardIterator __first, _Sentinel __last) const { using _ValueType = remove_reference_t>; - return _VSTD::__uninitialized_value_construct<_ValueType>( - _VSTD::move(__first), _VSTD::move(__last)); + return std::__uninitialized_value_construct<_ValueType>( + std::move(__first), std::move(__last)); } template <__nothrow_forward_range _ForwardRange> @@ -121,7 +121,7 @@ struct __fn { _LIBCPP_HIDE_FROM_ABI _ForwardIterator operator()(_ForwardIterator __first, iter_difference_t<_ForwardIterator> __n) const { using _ValueType = remove_reference_t>; - return _VSTD::__uninitialized_value_construct_n<_ValueType>(_VSTD::move(__first), __n); + return std::__uninitialized_value_construct_n<_ValueType>(std::move(__first), __n); } }; @@ -142,7 +142,7 @@ struct __fn { requires constructible_from, const _Tp&> _LIBCPP_HIDE_FROM_ABI _ForwardIterator operator()(_ForwardIterator __first, _Sentinel __last, const _Tp& __x) const { using _ValueType = remove_reference_t>; - return _VSTD::__uninitialized_fill<_ValueType>(_VSTD::move(__first), _VSTD::move(__last), __x); + return std::__uninitialized_fill<_ValueType>(std::move(__first), std::move(__last), __x); } template <__nothrow_forward_range _ForwardRange, class _Tp> @@ -169,7 +169,7 @@ struct __fn { iter_difference_t<_ForwardIterator> __n, const _Tp& __x) const { using _ValueType = remove_reference_t>; - return _VSTD::__uninitialized_fill_n<_ValueType>(_VSTD::move(__first), __n, __x); + return std::__uninitialized_fill_n<_ValueType>(std::move(__first), __n, __x); } }; @@ -199,7 +199,7 @@ struct __fn { auto __stop_copying = [&__olast](auto&& __out_iter) -> bool { return __out_iter == __olast; }; auto __result = std::__uninitialized_copy<_ValueType>( std::move(__ifirst), std::move(__ilast), std::move(__ofirst), __stop_copying); - return {_VSTD::move(__result.first), _VSTD::move(__result.second)}; + return {std::move(__result.first), std::move(__result.second)}; } template @@ -236,7 +236,7 @@ struct __fn { auto __stop_copying = [&__olast](auto&& __out_iter) -> bool { return __out_iter == __olast; }; auto __result = std::__uninitialized_copy_n<_ValueType>(std::move(__ifirst), __n, std::move(__ofirst), __stop_copying); - return {_VSTD::move(__result.first), _VSTD::move(__result.second)}; + return {std::move(__result.first), std::move(__result.second)}; } }; @@ -266,7 +266,7 @@ struct __fn { auto __stop_moving = [&__olast](auto&& __out_iter) -> bool { return __out_iter == __olast; }; auto __result = std::__uninitialized_move<_ValueType>( std::move(__ifirst), std::move(__ilast), std::move(__ofirst), __stop_moving, __iter_move); - return {_VSTD::move(__result.first), _VSTD::move(__result.second)}; + return {std::move(__result.first), std::move(__result.second)}; } template @@ -304,7 +304,7 @@ struct __fn { auto __stop_moving = [&__olast](auto&& __out_iter) -> bool { return __out_iter == __olast; }; auto __result = std::__uninitialized_move_n<_ValueType>( std::move(__ifirst), __n, std::move(__ofirst), __stop_moving, __iter_move); - return {_VSTD::move(__result.first), _VSTD::move(__result.second)}; + return {std::move(__result.first), std::move(__result.second)}; } }; diff --git a/libcxx/include/__memory/raw_storage_iterator.h b/libcxx/include/__memory/raw_storage_iterator.h index 4466d5b0ad24..7aa75dca350a 100644 --- a/libcxx/include/__memory/raw_storage_iterator.h +++ b/libcxx/include/__memory/raw_storage_iterator.h @@ -50,10 +50,10 @@ public: _LIBCPP_HIDE_FROM_ABI explicit raw_storage_iterator(_OutputIterator __x) : __x_(__x) {} _LIBCPP_HIDE_FROM_ABI raw_storage_iterator& operator*() {return *this;} _LIBCPP_HIDE_FROM_ABI raw_storage_iterator& operator=(const _Tp& __element) - {::new ((void*)_VSTD::addressof(*__x_)) _Tp(__element); return *this;} + {::new ((void*)std::addressof(*__x_)) _Tp(__element); return *this;} #if _LIBCPP_STD_VER >= 14 _LIBCPP_HIDE_FROM_ABI raw_storage_iterator& operator=(_Tp&& __element) - {::new ((void*)_VSTD::addressof(*__x_)) _Tp(_VSTD::move(__element)); return *this;} + {::new ((void*)std::addressof(*__x_)) _Tp(std::move(__element)); return *this;} #endif _LIBCPP_HIDE_FROM_ABI raw_storage_iterator& operator++() {++__x_; return *this;} _LIBCPP_HIDE_FROM_ABI raw_storage_iterator operator++(int) diff --git a/libcxx/include/__memory/shared_ptr.h b/libcxx/include/__memory/shared_ptr.h index a8957b6adcbb..84db7998a147 100644 --- a/libcxx/include/__memory/shared_ptr.h +++ b/libcxx/include/__memory/shared_ptr.h @@ -233,7 +233,7 @@ class __shared_ptr_pointer public: _LIBCPP_HIDE_FROM_ABI __shared_ptr_pointer(_Tp __p, _Dp __d, _Alloc __a) - : __data_(__compressed_pair<_Tp, _Dp>(__p, _VSTD::move(__d)), _VSTD::move(__a)) {} + : __data_(__compressed_pair<_Tp, _Dp>(__p, std::move(__d)), std::move(__a)) {} #ifndef _LIBCPP_HAS_NO_RTTI _LIBCPP_HIDE_FROM_ABI_VIRTUAL const void* __get_deleter(const type_info&) const _NOEXCEPT override; @@ -250,7 +250,7 @@ template const void* __shared_ptr_pointer<_Tp, _Dp, _Alloc>::__get_deleter(const type_info& __t) const _NOEXCEPT { - return __t == typeid(_Dp) ? _VSTD::addressof(__data_.first().second()) : nullptr; + return __t == typeid(_Dp) ? std::addressof(__data_.first().second()) : nullptr; } #endif // _LIBCPP_HAS_NO_RTTI @@ -288,7 +288,7 @@ struct __shared_ptr_emplace template ::value, int> = 0> _LIBCPP_HIDE_FROM_ABI explicit __shared_ptr_emplace(_Alloc __a, _Args&& ...) - : __storage_(_VSTD::move(__a)) + : __storage_(std::move(__a)) { static_assert(sizeof...(_Args) == 0, "No argument should be provided to the control block when using _for_overwrite"); ::new ((void*)__get_elem()) _Tp; @@ -297,11 +297,11 @@ struct __shared_ptr_emplace template ::value, int> = 0> _LIBCPP_HIDE_FROM_ABI explicit __shared_ptr_emplace(_Alloc __a, _Args&& ...__args) - : __storage_(_VSTD::move(__a)) + : __storage_(std::move(__a)) { using _TpAlloc = typename __allocator_traits_rebind<_Alloc, _Tp>::type; _TpAlloc __tmp(*__get_alloc()); - allocator_traits<_TpAlloc>::construct(__tmp, __get_elem(), _VSTD::forward<_Args>(__args)...); + allocator_traits<_TpAlloc>::construct(__tmp, __get_elem(), std::forward<_Args>(__args)...); } _LIBCPP_HIDE_FROM_ABI @@ -349,7 +349,7 @@ private: char __blob_[sizeof(_CompressedPair)]; _LIBCPP_HIDE_FROM_ABI explicit _Storage(_Alloc&& __a) { - ::new ((void*)__get_alloc()) _Alloc(_VSTD::move(__a)); + ::new ((void*)__get_alloc()) _Alloc(std::move(__a)); } _LIBCPP_HIDE_FROM_ABI ~_Storage() { __get_alloc()->~_Alloc(); @@ -533,7 +533,7 @@ public: typedef typename __shared_ptr_default_allocator<_Yp>::type _AllocT; typedef __shared_ptr_pointer<_Yp*, _Dp, _AllocT> _CntrlBlk; #ifndef _LIBCPP_CXX03_LANG - __cntrl_ = new _CntrlBlk(__p, _VSTD::move(__d), _AllocT()); + __cntrl_ = new _CntrlBlk(__p, std::move(__d), _AllocT()); #else __cntrl_ = new _CntrlBlk(__p, __d, _AllocT()); #endif // not _LIBCPP_CXX03_LANG @@ -562,13 +562,13 @@ public: typedef __allocator_destructor<_A2> _D2; _A2 __a2(__a); unique_ptr<_CntrlBlk, _D2> __hold2(__a2.allocate(1), _D2(__a2, 1)); - ::new ((void*)_VSTD::addressof(*__hold2.get())) + ::new ((void*)std::addressof(*__hold2.get())) #ifndef _LIBCPP_CXX03_LANG - _CntrlBlk(__p, _VSTD::move(__d), __a); + _CntrlBlk(__p, std::move(__d), __a); #else _CntrlBlk(__p, __d, __a); #endif // not _LIBCPP_CXX03_LANG - __cntrl_ = _VSTD::addressof(*__hold2.release()); + __cntrl_ = std::addressof(*__hold2.release()); __enable_weak_this(__p, __p); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } @@ -592,7 +592,7 @@ public: typedef typename __shared_ptr_default_allocator<_Tp>::type _AllocT; typedef __shared_ptr_pointer _CntrlBlk; #ifndef _LIBCPP_CXX03_LANG - __cntrl_ = new _CntrlBlk(__p, _VSTD::move(__d), _AllocT()); + __cntrl_ = new _CntrlBlk(__p, std::move(__d), _AllocT()); #else __cntrl_ = new _CntrlBlk(__p, __d, _AllocT()); #endif // not _LIBCPP_CXX03_LANG @@ -620,13 +620,13 @@ public: typedef __allocator_destructor<_A2> _D2; _A2 __a2(__a); unique_ptr<_CntrlBlk, _D2> __hold2(__a2.allocate(1), _D2(__a2, 1)); - ::new ((void*)_VSTD::addressof(*__hold2.get())) + ::new ((void*)std::addressof(*__hold2.get())) #ifndef _LIBCPP_CXX03_LANG - _CntrlBlk(__p, _VSTD::move(__d), __a); + _CntrlBlk(__p, std::move(__d), __a); #else _CntrlBlk(__p, __d, __a); #endif // not _LIBCPP_CXX03_LANG - __cntrl_ = _VSTD::addressof(*__hold2.release()); + __cntrl_ = std::addressof(*__hold2.release()); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) @@ -762,7 +762,7 @@ public: typedef __shared_ptr_pointer::pointer, reference_wrapper<__libcpp_remove_reference_t<_Dp> >, _AllocT> _CntrlBlk; - __cntrl_ = new _CntrlBlk(__r.get(), _VSTD::ref(__r.get_deleter()), _AllocT()); + __cntrl_ = new _CntrlBlk(__r.get(), std::ref(__r.get_deleter()), _AllocT()); __enable_weak_this(__r.get(), __r.get()); } __r.release(); @@ -793,7 +793,7 @@ public: _LIBCPP_HIDE_FROM_ABI shared_ptr<_Tp>& operator=(shared_ptr&& __r) _NOEXCEPT { - shared_ptr(_VSTD::move(__r)).swap(*this); + shared_ptr(std::move(__r)).swap(*this); return *this; } @@ -801,7 +801,7 @@ public: _LIBCPP_HIDE_FROM_ABI shared_ptr<_Tp>& operator=(shared_ptr<_Yp>&& __r) { - shared_ptr(_VSTD::move(__r)).swap(*this); + shared_ptr(std::move(__r)).swap(*this); return *this; } @@ -813,7 +813,7 @@ public: _LIBCPP_HIDE_FROM_ABI shared_ptr<_Tp>& operator=(auto_ptr<_Yp>&& __r) { - shared_ptr(_VSTD::move(__r)).swap(*this); + shared_ptr(std::move(__r)).swap(*this); return *this; } #endif @@ -825,15 +825,15 @@ public: _LIBCPP_HIDE_FROM_ABI shared_ptr<_Tp>& operator=(unique_ptr<_Yp, _Dp>&& __r) { - shared_ptr(_VSTD::move(__r)).swap(*this); + shared_ptr(std::move(__r)).swap(*this); return *this; } _LIBCPP_HIDE_FROM_ABI void swap(shared_ptr& __r) _NOEXCEPT { - _VSTD::swap(__ptr_, __r.__ptr_); - _VSTD::swap(__cntrl_, __r.__cntrl_); + std::swap(__ptr_, __r.__ptr_); + std::swap(__cntrl_, __r.__cntrl_); } _LIBCPP_HIDE_FROM_ABI @@ -1022,16 +1022,16 @@ shared_ptr<_Tp> allocate_shared(const _Alloc& __a, _Args&& ...__args) using _ControlBlock = __shared_ptr_emplace<_Tp, _Alloc>; using _ControlBlockAllocator = typename __allocator_traits_rebind<_Alloc, _ControlBlock>::type; __allocation_guard<_ControlBlockAllocator> __guard(__a, 1); - ::new ((void*)_VSTD::addressof(*__guard.__get())) _ControlBlock(__a, _VSTD::forward<_Args>(__args)...); + ::new ((void*)std::addressof(*__guard.__get())) _ControlBlock(__a, std::forward<_Args>(__args)...); auto __control_block = __guard.__release_ptr(); - return shared_ptr<_Tp>::__create_with_control_block((*__control_block).__get_elem(), _VSTD::addressof(*__control_block)); + return shared_ptr<_Tp>::__create_with_control_block((*__control_block).__get_elem(), std::addressof(*__control_block)); } template::value> > _LIBCPP_HIDE_FROM_ABI shared_ptr<_Tp> make_shared(_Args&& ...__args) { - return _VSTD::allocate_shared<_Tp>(allocator<_Tp>(), _VSTD::forward<_Args>(__args)...); + return std::allocate_shared<_Tp>(allocator<_Tp>(), std::forward<_Args>(__args)...); } #if _LIBCPP_STD_VER >= 20 @@ -1789,7 +1789,7 @@ inline weak_ptr<_Tp>& weak_ptr<_Tp>::operator=(weak_ptr&& __r) _NOEXCEPT { - weak_ptr(_VSTD::move(__r)).swap(*this); + weak_ptr(std::move(__r)).swap(*this); return *this; } @@ -1799,7 +1799,7 @@ inline weak_ptr<_Tp>& weak_ptr<_Tp>::operator=(weak_ptr<_Yp>&& __r) _NOEXCEPT { - weak_ptr(_VSTD::move(__r)).swap(*this); + weak_ptr(std::move(__r)).swap(*this); return *this; } @@ -1818,8 +1818,8 @@ inline void weak_ptr<_Tp>::swap(weak_ptr& __r) _NOEXCEPT { - _VSTD::swap(__ptr_, __r.__ptr_); - _VSTD::swap(__cntrl_, __r.__cntrl_); + std::swap(__ptr_, __r.__ptr_); + std::swap(__cntrl_, __r.__cntrl_); } template @@ -2060,12 +2060,12 @@ atomic_compare_exchange_strong(shared_ptr<_Tp>* __p, shared_ptr<_Tp>* __v, share __m.lock(); if (__p->__owner_equivalent(*__v)) { - _VSTD::swap(__temp, *__p); + std::swap(__temp, *__p); *__p = __w; __m.unlock(); return true; } - _VSTD::swap(__temp, *__v); + std::swap(__temp, *__v); *__v = *__p; __m.unlock(); return false; diff --git a/libcxx/include/__memory/swap_allocator.h b/libcxx/include/__memory/swap_allocator.h index 90851cb79cfc..f2c509056391 100644 --- a/libcxx/include/__memory/swap_allocator.h +++ b/libcxx/include/__memory/swap_allocator.h @@ -29,7 +29,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 void __swap_allocator(_Alloc _NOEXCEPT_(__is_nothrow_swappable<_Alloc>::value) #endif { - using _VSTD::swap; + using std::swap; swap(__a1, __a2); } @@ -45,7 +45,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 void __swap_allocator _NOEXCEPT_(__is_nothrow_swappable<_Alloc>::value) #endif { - _VSTD::__swap_allocator( + std::__swap_allocator( __a1, __a2, integral_constant::propagate_on_container_swap::value>()); } diff --git a/libcxx/include/__memory/temporary_buffer.h b/libcxx/include/__memory/temporary_buffer.h index 9749944bd28e..28ef5d028bec 100644 --- a/libcxx/include/__memory/temporary_buffer.h +++ b/libcxx/include/__memory/temporary_buffer.h @@ -70,14 +70,14 @@ template inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_DEPRECATED_IN_CXX17 void return_temporary_buffer(_Tp* __p) _NOEXCEPT { - _VSTD::__libcpp_deallocate_unsized((void*)__p, _LIBCPP_ALIGNOF(_Tp)); + std::__libcpp_deallocate_unsized((void*)__p, _LIBCPP_ALIGNOF(_Tp)); } struct __return_temporary_buffer { _LIBCPP_SUPPRESS_DEPRECATED_PUSH template - _LIBCPP_HIDE_FROM_ABI void operator()(_Tp* __p) const {_VSTD::return_temporary_buffer(__p);} + _LIBCPP_HIDE_FROM_ABI void operator()(_Tp* __p) const {std::return_temporary_buffer(__p);} _LIBCPP_SUPPRESS_DEPRECATED_POP }; diff --git a/libcxx/include/__memory/uninitialized_algorithms.h b/libcxx/include/__memory/uninitialized_algorithms.h index af0d83c97cf5..b0eb7001598b 100644 --- a/libcxx/include/__memory/uninitialized_algorithms.h +++ b/libcxx/include/__memory/uninitialized_algorithms.h @@ -61,15 +61,15 @@ inline _LIBCPP_HIDE_FROM_ABI pair<_InputIterator, _ForwardIterator> __uninitiali try { #endif for (; __ifirst != __ilast && !__stop_copying(__idx); ++__ifirst, (void)++__idx) - ::new (_VSTD::__voidify(*__idx)) _ValueType(*__ifirst); + ::new (std::__voidify(*__idx)) _ValueType(*__ifirst); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__ofirst, __idx); + std::__destroy(__ofirst, __idx); throw; } #endif - return pair<_InputIterator, _ForwardIterator>(_VSTD::move(__ifirst), _VSTD::move(__idx)); + return pair<_InputIterator, _ForwardIterator>(std::move(__ifirst), std::move(__idx)); } template @@ -79,7 +79,7 @@ _ForwardIterator uninitialized_copy(_InputIterator __ifirst, _InputIterator __il typedef typename iterator_traits<_ForwardIterator>::value_type _ValueType; auto __result = std::__uninitialized_copy<_ValueType>( std::move(__ifirst), std::move(__ilast), std::move(__ofirst), __always_false()); - return _VSTD::move(__result.second); + return std::move(__result.second); } // uninitialized_copy_n @@ -92,15 +92,15 @@ inline _LIBCPP_HIDE_FROM_ABI pair<_InputIterator, _ForwardIterator> __uninitiali try { #endif for (; __n > 0 && !__stop_copying(__idx); ++__ifirst, (void)++__idx, (void)--__n) - ::new (_VSTD::__voidify(*__idx)) _ValueType(*__ifirst); + ::new (std::__voidify(*__idx)) _ValueType(*__ifirst); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__ofirst, __idx); + std::__destroy(__ofirst, __idx); throw; } #endif - return pair<_InputIterator, _ForwardIterator>(_VSTD::move(__ifirst), _VSTD::move(__idx)); + return pair<_InputIterator, _ForwardIterator>(std::move(__ifirst), std::move(__idx)); } template @@ -109,7 +109,7 @@ inline _LIBCPP_HIDE_FROM_ABI _ForwardIterator uninitialized_copy_n(_InputIterato typedef typename iterator_traits<_ForwardIterator>::value_type _ValueType; auto __result = std::__uninitialized_copy_n<_ValueType>(std::move(__ifirst), __n, std::move(__ofirst), __always_false()); - return _VSTD::move(__result.second); + return std::move(__result.second); } // uninitialized_fill @@ -124,12 +124,12 @@ _ForwardIterator __uninitialized_fill(_ForwardIterator __first, _Sentinel __last { #endif for (; __idx != __last; ++__idx) - ::new (_VSTD::__voidify(*__idx)) _ValueType(__x); + ::new (std::__voidify(*__idx)) _ValueType(__x); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__first, __idx); + std::__destroy(__first, __idx); throw; } #endif @@ -142,7 +142,7 @@ inline _LIBCPP_HIDE_FROM_ABI void uninitialized_fill(_ForwardIterator __first, _ForwardIterator __last, const _Tp& __x) { typedef typename iterator_traits<_ForwardIterator>::value_type _ValueType; - (void)_VSTD::__uninitialized_fill<_ValueType>(__first, __last, __x); + (void)std::__uninitialized_fill<_ValueType>(__first, __last, __x); } // uninitialized_fill_n @@ -157,12 +157,12 @@ _ForwardIterator __uninitialized_fill_n(_ForwardIterator __first, _Size __n, con { #endif for (; __n > 0; ++__idx, (void) --__n) - ::new (_VSTD::__voidify(*__idx)) _ValueType(__x); + ::new (std::__voidify(*__idx)) _ValueType(__x); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__first, __idx); + std::__destroy(__first, __idx); throw; } #endif @@ -175,7 +175,7 @@ inline _LIBCPP_HIDE_FROM_ABI _ForwardIterator uninitialized_fill_n(_ForwardIterator __first, _Size __n, const _Tp& __x) { typedef typename iterator_traits<_ForwardIterator>::value_type _ValueType; - return _VSTD::__uninitialized_fill_n<_ValueType>(__first, __n, __x); + return std::__uninitialized_fill_n<_ValueType>(__first, __n, __x); } #if _LIBCPP_STD_VER >= 17 @@ -190,10 +190,10 @@ _ForwardIterator __uninitialized_default_construct(_ForwardIterator __first, _Se try { #endif for (; __idx != __last; ++__idx) - ::new (_VSTD::__voidify(*__idx)) _ValueType; + ::new (std::__voidify(*__idx)) _ValueType; #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__first, __idx); + std::__destroy(__first, __idx); throw; } #endif @@ -205,8 +205,8 @@ template inline _LIBCPP_HIDE_FROM_ABI void uninitialized_default_construct(_ForwardIterator __first, _ForwardIterator __last) { using _ValueType = typename iterator_traits<_ForwardIterator>::value_type; - (void)_VSTD::__uninitialized_default_construct<_ValueType>( - _VSTD::move(__first), _VSTD::move(__last)); + (void)std::__uninitialized_default_construct<_ValueType>( + std::move(__first), std::move(__last)); } // uninitialized_default_construct_n @@ -219,10 +219,10 @@ _ForwardIterator __uninitialized_default_construct_n(_ForwardIterator __first, _ try { #endif for (; __n > 0; ++__idx, (void) --__n) - ::new (_VSTD::__voidify(*__idx)) _ValueType; + ::new (std::__voidify(*__idx)) _ValueType; #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__first, __idx); + std::__destroy(__first, __idx); throw; } #endif @@ -234,7 +234,7 @@ template inline _LIBCPP_HIDE_FROM_ABI _ForwardIterator uninitialized_default_construct_n(_ForwardIterator __first, _Size __n) { using _ValueType = typename iterator_traits<_ForwardIterator>::value_type; - return _VSTD::__uninitialized_default_construct_n<_ValueType>(_VSTD::move(__first), __n); + return std::__uninitialized_default_construct_n<_ValueType>(std::move(__first), __n); } // uninitialized_value_construct @@ -247,10 +247,10 @@ _ForwardIterator __uninitialized_value_construct(_ForwardIterator __first, _Sent try { #endif for (; __idx != __last; ++__idx) - ::new (_VSTD::__voidify(*__idx)) _ValueType(); + ::new (std::__voidify(*__idx)) _ValueType(); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__first, __idx); + std::__destroy(__first, __idx); throw; } #endif @@ -262,8 +262,8 @@ template inline _LIBCPP_HIDE_FROM_ABI void uninitialized_value_construct(_ForwardIterator __first, _ForwardIterator __last) { using _ValueType = typename iterator_traits<_ForwardIterator>::value_type; - (void)_VSTD::__uninitialized_value_construct<_ValueType>( - _VSTD::move(__first), _VSTD::move(__last)); + (void)std::__uninitialized_value_construct<_ValueType>( + std::move(__first), std::move(__last)); } // uninitialized_value_construct_n @@ -276,10 +276,10 @@ _ForwardIterator __uninitialized_value_construct_n(_ForwardIterator __first, _Si try { #endif for (; __n > 0; ++__idx, (void) --__n) - ::new (_VSTD::__voidify(*__idx)) _ValueType(); + ::new (std::__voidify(*__idx)) _ValueType(); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__first, __idx); + std::__destroy(__first, __idx); throw; } #endif @@ -291,7 +291,7 @@ template inline _LIBCPP_HIDE_FROM_ABI _ForwardIterator uninitialized_value_construct_n(_ForwardIterator __first, _Size __n) { using _ValueType = typename iterator_traits<_ForwardIterator>::value_type; - return std::__uninitialized_value_construct_n<_ValueType>(_VSTD::move(__first), __n); + return std::__uninitialized_value_construct_n<_ValueType>(std::move(__first), __n); } // uninitialized_move @@ -313,27 +313,27 @@ inline _LIBCPP_HIDE_FROM_ABI pair<_InputIterator, _ForwardIterator> __uninitiali try { #endif for (; __ifirst != __ilast && !__stop_moving(__idx); ++__idx, (void)++__ifirst) { - ::new (_VSTD::__voidify(*__idx)) _ValueType(__iter_move(__ifirst)); + ::new (std::__voidify(*__idx)) _ValueType(__iter_move(__ifirst)); } #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__ofirst, __idx); + std::__destroy(__ofirst, __idx); throw; } #endif - return {_VSTD::move(__ifirst), _VSTD::move(__idx)}; + return {std::move(__ifirst), std::move(__idx)}; } template inline _LIBCPP_HIDE_FROM_ABI _ForwardIterator uninitialized_move(_InputIterator __ifirst, _InputIterator __ilast, _ForwardIterator __ofirst) { using _ValueType = typename iterator_traits<_ForwardIterator>::value_type; - auto __iter_move = [](auto&& __iter) -> decltype(auto) { return _VSTD::move(*__iter); }; + auto __iter_move = [](auto&& __iter) -> decltype(auto) { return std::move(*__iter); }; auto __result = std::__uninitialized_move<_ValueType>( std::move(__ifirst), std::move(__ilast), std::move(__ofirst), __always_false(), __iter_move); - return _VSTD::move(__result.second); + return std::move(__result.second); } // uninitialized_move_n @@ -351,22 +351,22 @@ inline _LIBCPP_HIDE_FROM_ABI pair<_InputIterator, _ForwardIterator> __uninitiali try { #endif for (; __n > 0 && !__stop_moving(__idx); ++__idx, (void)++__ifirst, --__n) - ::new (_VSTD::__voidify(*__idx)) _ValueType(__iter_move(__ifirst)); + ::new (std::__voidify(*__idx)) _ValueType(__iter_move(__ifirst)); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { - _VSTD::__destroy(__ofirst, __idx); + std::__destroy(__ofirst, __idx); throw; } #endif - return {_VSTD::move(__ifirst), _VSTD::move(__idx)}; + return {std::move(__ifirst), std::move(__idx)}; } template inline _LIBCPP_HIDE_FROM_ABI pair<_InputIterator, _ForwardIterator> uninitialized_move_n(_InputIterator __ifirst, _Size __n, _ForwardIterator __ofirst) { using _ValueType = typename iterator_traits<_ForwardIterator>::value_type; - auto __iter_move = [](auto&& __iter) -> decltype(auto) { return _VSTD::move(*__iter); }; + auto __iter_move = [](auto&& __iter) -> decltype(auto) { return std::move(*__iter); }; return std::__uninitialized_move_n<_ValueType>( std::move(__ifirst), __n, std::move(__ofirst), __always_false(), __iter_move); diff --git a/libcxx/include/__memory/unique_ptr.h b/libcxx/include/__memory/unique_ptr.h index 33fda1da5d43..32e4942a834c 100644 --- a/libcxx/include/__memory/unique_ptr.h +++ b/libcxx/include/__memory/unique_ptr.h @@ -200,7 +200,7 @@ public: template > > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 - unique_ptr(pointer __p, _GoodRValRefType<_Dummy> __d) _NOEXCEPT : __ptr_(__p, _VSTD::move(__d)) { + unique_ptr(pointer __p, _GoodRValRefType<_Dummy> __d) _NOEXCEPT : __ptr_(__p, std::move(__d)) { static_assert(!is_reference::value, "rvalue deleter bound to reference"); } @@ -211,14 +211,14 @@ public: unique_ptr(pointer __p, _BadRValRefType<_Dummy> __d) = delete; _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr(unique_ptr&& __u) _NOEXCEPT - : __ptr_(__u.release(), _VSTD::forward(__u.get_deleter())) {} + : __ptr_(__u.release(), std::forward(__u.get_deleter())) {} template , _Up>, class = _EnableIfDeleterConvertible<_Ep> > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr(unique_ptr<_Up, _Ep>&& __u) _NOEXCEPT - : __ptr_(__u.release(), _VSTD::forward<_Ep>(__u.get_deleter())) {} + : __ptr_(__u.release(), std::forward<_Ep>(__u.get_deleter())) {} #if _LIBCPP_STD_VER <= 14 || defined(_LIBCPP_ENABLE_CXX17_REMOVED_AUTO_PTR) template ::value && @@ -230,7 +230,7 @@ public: _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr& operator=(unique_ptr&& __u) _NOEXCEPT { reset(__u.release()); - __ptr_.second() = _VSTD::forward(__u.get_deleter()); + __ptr_.second() = std::forward(__u.get_deleter()); return *this; } @@ -240,7 +240,7 @@ public: class = _EnableIfDeleterAssignable<_Ep> > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr& operator=(unique_ptr<_Up, _Ep>&& __u) _NOEXCEPT { reset(__u.release()); - __ptr_.second() = _VSTD::forward<_Ep>(__u.get_deleter()); + __ptr_.second() = std::forward<_Ep>(__u.get_deleter()); return *this; } @@ -408,14 +408,14 @@ public: class = _EnableIfDeleterConstructible<_GoodRValRefType<_Dummy> >, class = _EnableIfPointerConvertible<_Pp> > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr(_Pp __p, _GoodRValRefType<_Dummy> __d) _NOEXCEPT - : __ptr_(__p, _VSTD::move(__d)) { + : __ptr_(__p, std::move(__d)) { static_assert(!is_reference::value, "rvalue deleter bound to reference"); } template > > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr(nullptr_t, _GoodRValRefType<_Dummy> __d) _NOEXCEPT - : __ptr_(nullptr, _VSTD::move(__d)) { + : __ptr_(nullptr, std::move(__d)) { static_assert(!is_reference::value, "rvalue deleter bound to reference"); } @@ -427,11 +427,11 @@ public: unique_ptr(_Pp __p, _BadRValRefType<_Dummy> __d) = delete; _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr(unique_ptr&& __u) _NOEXCEPT - : __ptr_(__u.release(), _VSTD::forward(__u.get_deleter())) {} + : __ptr_(__u.release(), std::forward(__u.get_deleter())) {} _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr& operator=(unique_ptr&& __u) _NOEXCEPT { reset(__u.release()); - __ptr_.second() = _VSTD::forward(__u.get_deleter()); + __ptr_.second() = std::forward(__u.get_deleter()); return *this; } @@ -440,7 +440,7 @@ public: class = _EnableIfMoveConvertible, _Up>, class = _EnableIfDeleterConvertible<_Ep> > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr(unique_ptr<_Up, _Ep>&& __u) _NOEXCEPT - : __ptr_(__u.release(), _VSTD::forward<_Ep>(__u.get_deleter())) {} + : __ptr_(__u.release(), std::forward<_Ep>(__u.get_deleter())) {} template > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unique_ptr& operator=(unique_ptr<_Up, _Ep>&& __u) _NOEXCEPT { reset(__u.release()); - __ptr_.second() = _VSTD::forward<_Ep>(__u.get_deleter()); + __ptr_.second() = std::forward<_Ep>(__u.get_deleter()); return *this; } @@ -682,7 +682,7 @@ struct __unique_if<_Tp[_Np]> template inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 typename __unique_if<_Tp>::__unique_single make_unique(_Args&&... __args) { - return unique_ptr<_Tp>(new _Tp(_VSTD::forward<_Args>(__args)...)); + return unique_ptr<_Tp>(new _Tp(std::forward<_Args>(__args)...)); } template diff --git a/libcxx/include/__memory/voidify.h b/libcxx/include/__memory/voidify.h index 39e10343f4ca..dbd083bd8c1e 100644 --- a/libcxx/include/__memory/voidify.h +++ b/libcxx/include/__memory/voidify.h @@ -22,7 +22,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD template _LIBCPP_ALWAYS_INLINE _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void* __voidify(_Tp& __from) { // Cast away cv-qualifiers to allow modifying elements of a range through const iterators. - return const_cast(static_cast(_VSTD::addressof(__from))); + return const_cast(static_cast(std::addressof(__from))); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__mutex/once_flag.h b/libcxx/include/__mutex/once_flag.h index 086f75ca4f81..5a6f8e09055f 100644 --- a/libcxx/include/__mutex/once_flag.h +++ b/libcxx/include/__mutex/once_flag.h @@ -91,7 +91,7 @@ public: private: template _LIBCPP_HIDE_FROM_ABI void __execute(__tuple_indices<_Indices...>) { - _VSTD::__invoke(_VSTD::get<0>(_VSTD::move(__f_)), _VSTD::get<_Indices>(_VSTD::move(__f_))...); + std::__invoke(std::get<0>(std::move(__f_)), std::get<_Indices>(std::move(__f_))...); } }; @@ -123,7 +123,7 @@ template inline _LIBCPP_HIDE_FROM_ABI void call_once(once_flag& __flag, _Callable&& __func, _Args&&... __args) { if (__libcpp_acquire_load(&__flag.__state_) != once_flag::_Complete) { typedef tuple<_Callable&&, _Args&&...> _Gp; - _Gp __f(_VSTD::forward<_Callable>(__func), _VSTD::forward<_Args>(__args)...); + _Gp __f(std::forward<_Callable>(__func), std::forward<_Args>(__args)...); __call_once_param<_Gp> __p(__f); std::__call_once(__flag.__state_, &__p, &__call_once_proxy<_Gp>); } diff --git a/libcxx/include/__node_handle b/libcxx/include/__node_handle index 552bd4174458..e680fe542c6d 100644 --- a/libcxx/include/__node_handle +++ b/libcxx/include/__node_handle @@ -109,7 +109,7 @@ private: void __release_ptr() { __ptr_ = nullptr; - __alloc_ = _VSTD::nullopt; + __alloc_ = std::nullopt; } _LIBCPP_HIDE_FROM_ABI @@ -140,17 +140,17 @@ public: _LIBCPP_HIDE_FROM_ABI __basic_node_handle(__basic_node_handle&& __other) noexcept : __ptr_(__other.__ptr_), - __alloc_(_VSTD::move(__other.__alloc_)) + __alloc_(std::move(__other.__alloc_)) { __other.__ptr_ = nullptr; - __other.__alloc_ = _VSTD::nullopt; + __other.__alloc_ = std::nullopt; } _LIBCPP_HIDE_FROM_ABI __basic_node_handle& operator=(__basic_node_handle&& __other) { _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR( - __alloc_ == _VSTD::nullopt || + __alloc_ == std::nullopt || __alloc_traits::propagate_on_container_move_assignment::value || __alloc_ == __other.__alloc_, "node_type with incompatible allocator passed to " @@ -160,11 +160,11 @@ public: __ptr_ = __other.__ptr_; if (__alloc_traits::propagate_on_container_move_assignment::value || - __alloc_ == _VSTD::nullopt) - __alloc_ = _VSTD::move(__other.__alloc_); + __alloc_ == std::nullopt) + __alloc_ = std::move(__other.__alloc_); __other.__ptr_ = nullptr; - __other.__alloc_ = _VSTD::nullopt; + __other.__alloc_ = std::nullopt; return *this; } @@ -183,10 +183,10 @@ public: __alloc_traits::propagate_on_container_swap::value || __alloc_traits::is_always_equal::value) { - using _VSTD::swap; + using std::swap; swap(__ptr_, __other.__ptr_); if (__alloc_traits::propagate_on_container_swap::value || - __alloc_ == _VSTD::nullopt || __other.__alloc_ == _VSTD::nullopt) + __alloc_ == std::nullopt || __other.__alloc_ == std::nullopt) swap(__alloc_, __other.__alloc_); } diff --git a/libcxx/include/__numeric/accumulate.h b/libcxx/include/__numeric/accumulate.h index 3a1bfbe70008..1ab6c4b616db 100644 --- a/libcxx/include/__numeric/accumulate.h +++ b/libcxx/include/__numeric/accumulate.h @@ -29,7 +29,7 @@ accumulate(_InputIterator __first, _InputIterator __last, _Tp __init) { for (; __first != __last; ++__first) #if _LIBCPP_STD_VER >= 20 - __init = _VSTD::move(__init) + *__first; + __init = std::move(__init) + *__first; #else __init = __init + *__first; #endif @@ -43,7 +43,7 @@ accumulate(_InputIterator __first, _InputIterator __last, _Tp __init, _BinaryOpe { for (; __first != __last; ++__first) #if _LIBCPP_STD_VER >= 20 - __init = __binary_op(_VSTD::move(__init), *__first); + __init = __binary_op(std::move(__init), *__first); #else __init = __binary_op(__init, *__first); #endif diff --git a/libcxx/include/__numeric/adjacent_difference.h b/libcxx/include/__numeric/adjacent_difference.h index 9142a85082e4..31ffe9c04a1d 100644 --- a/libcxx/include/__numeric/adjacent_difference.h +++ b/libcxx/include/__numeric/adjacent_difference.h @@ -36,11 +36,11 @@ adjacent_difference(_InputIterator __first, _InputIterator __last, _OutputIterat { typename iterator_traits<_InputIterator>::value_type __val(*__first); #if _LIBCPP_STD_VER >= 20 - *__result = __val - _VSTD::move(__acc); + *__result = __val - std::move(__acc); #else *__result = __val - __acc; #endif - __acc = _VSTD::move(__val); + __acc = std::move(__val); } } return __result; @@ -60,11 +60,11 @@ adjacent_difference(_InputIterator __first, _InputIterator __last, _OutputIterat { typename iterator_traits<_InputIterator>::value_type __val(*__first); #if _LIBCPP_STD_VER >= 20 - *__result = __binary_op(__val, _VSTD::move(__acc)); + *__result = __binary_op(__val, std::move(__acc)); #else *__result = __binary_op(__val, __acc); #endif - __acc = _VSTD::move(__val); + __acc = std::move(__val); } } return __result; diff --git a/libcxx/include/__numeric/exclusive_scan.h b/libcxx/include/__numeric/exclusive_scan.h index 722917151158..8b4a5c820dd9 100644 --- a/libcxx/include/__numeric/exclusive_scan.h +++ b/libcxx/include/__numeric/exclusive_scan.h @@ -31,12 +31,12 @@ exclusive_scan(_InputIterator __first, _InputIterator __last, _OutputIterator __ if (__first != __last) { _Tp __tmp(__b(__init, *__first)); while (true) { - *__result = _VSTD::move(__init); + *__result = std::move(__init); ++__result; ++__first; if (__first == __last) break; - __init = _VSTD::move(__tmp); + __init = std::move(__tmp); __tmp = __b(__init, *__first); } } @@ -46,7 +46,7 @@ exclusive_scan(_InputIterator __first, _InputIterator __last, _OutputIterator __ template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _OutputIterator exclusive_scan(_InputIterator __first, _InputIterator __last, _OutputIterator __result, _Tp __init) { - return _VSTD::exclusive_scan(__first, __last, __result, __init, _VSTD::plus<>()); + return std::exclusive_scan(__first, __last, __result, __init, std::plus<>()); } #endif // _LIBCPP_STD_VER >= 17 diff --git a/libcxx/include/__numeric/gcd_lcm.h b/libcxx/include/__numeric/gcd_lcm.h index 2287920b18a8..693be704af29 100644 --- a/libcxx/include/__numeric/gcd_lcm.h +++ b/libcxx/include/__numeric/gcd_lcm.h @@ -55,7 +55,7 @@ _LIBCPP_CONSTEXPR _LIBCPP_HIDDEN _Tp __gcd(_Tp __m, _Tp __n) { static_assert((!is_signed<_Tp>::value), ""); - return __n == 0 ? __m : _VSTD::__gcd<_Tp>(__n, __m % __n); + return __n == 0 ? __m : std::__gcd<_Tp>(__n, __m % __n); } template @@ -68,7 +68,7 @@ gcd(_Tp __m, _Up __n) static_assert((!is_same<__remove_cv_t<_Up>, bool>::value), "Second argument to gcd cannot be bool" ); using _Rp = common_type_t<_Tp,_Up>; using _Wp = make_unsigned_t<_Rp>; - return static_cast<_Rp>(_VSTD::__gcd( + return static_cast<_Rp>(std::__gcd( static_cast<_Wp>(__ct_abs<_Rp, _Tp>()(__m)), static_cast<_Wp>(__ct_abs<_Rp, _Up>()(__n)))); } @@ -85,7 +85,7 @@ lcm(_Tp __m, _Up __n) return 0; using _Rp = common_type_t<_Tp,_Up>; - _Rp __val1 = __ct_abs<_Rp, _Tp>()(__m) / _VSTD::gcd(__m, __n); + _Rp __val1 = __ct_abs<_Rp, _Tp>()(__m) / std::gcd(__m, __n); _Rp __val2 = __ct_abs<_Rp, _Up>()(__n); _LIBCPP_ASSERT_UNCATEGORIZED((numeric_limits<_Rp>::max() / __val1 > __val2), "Overflow in lcm"); return __val1 * __val2; diff --git a/libcxx/include/__numeric/inclusive_scan.h b/libcxx/include/__numeric/inclusive_scan.h index b6d72afb4ab0..162b9e688433 100644 --- a/libcxx/include/__numeric/inclusive_scan.h +++ b/libcxx/include/__numeric/inclusive_scan.h @@ -40,7 +40,7 @@ inclusive_scan(_InputIterator __first, _InputIterator __last, _OutputIterator __ typename iterator_traits<_InputIterator>::value_type __init = *__first; *__result++ = __init; if (++__first != __last) - return _VSTD::inclusive_scan(__first, __last, __result, __b, __init); + return std::inclusive_scan(__first, __last, __result, __b, __init); } return __result; @@ -50,7 +50,7 @@ template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _OutputIterator inclusive_scan(_InputIterator __first, _InputIterator __last, _OutputIterator __result) { - return _VSTD::inclusive_scan(__first, __last, __result, _VSTD::plus<>()); + return std::inclusive_scan(__first, __last, __result, std::plus<>()); } #endif // _LIBCPP_STD_VER >= 17 diff --git a/libcxx/include/__numeric/inner_product.h b/libcxx/include/__numeric/inner_product.h index c9476c5d0187..48f2ea348987 100644 --- a/libcxx/include/__numeric/inner_product.h +++ b/libcxx/include/__numeric/inner_product.h @@ -29,7 +29,7 @@ inner_product(_InputIterator1 __first1, _InputIterator1 __last1, _InputIterator2 { for (; __first1 != __last1; ++__first1, (void) ++__first2) #if _LIBCPP_STD_VER >= 20 - __init = _VSTD::move(__init) + *__first1 * *__first2; + __init = std::move(__init) + *__first1 * *__first2; #else __init = __init + *__first1 * *__first2; #endif @@ -44,7 +44,7 @@ inner_product(_InputIterator1 __first1, _InputIterator1 __last1, _InputIterator2 { for (; __first1 != __last1; ++__first1, (void) ++__first2) #if _LIBCPP_STD_VER >= 20 - __init = __binary_op1(_VSTD::move(__init), __binary_op2(*__first1, *__first2)); + __init = __binary_op1(std::move(__init), __binary_op2(*__first1, *__first2)); #else __init = __binary_op1(__init, __binary_op2(*__first1, *__first2)); #endif diff --git a/libcxx/include/__numeric/midpoint.h b/libcxx/include/__numeric/midpoint.h index 780dfd6d0bbd..c92e450767c9 100644 --- a/libcxx/include/__numeric/midpoint.h +++ b/libcxx/include/__numeric/midpoint.h @@ -60,7 +60,7 @@ enable_if_t && (sizeof(remove_pointer_t<_TPtr>) > 0), _TPtr> midpoint(_TPtr __a, _TPtr __b) noexcept { - return __a + _VSTD::midpoint(ptrdiff_t(0), __b - __a); + return __a + std::midpoint(ptrdiff_t(0), __b - __a); } diff --git a/libcxx/include/__numeric/partial_sum.h b/libcxx/include/__numeric/partial_sum.h index 6b0cea1e2215..49afcbb746f5 100644 --- a/libcxx/include/__numeric/partial_sum.h +++ b/libcxx/include/__numeric/partial_sum.h @@ -35,7 +35,7 @@ partial_sum(_InputIterator __first, _InputIterator __last, _OutputIterator __res for (++__first, (void) ++__result; __first != __last; ++__first, (void) ++__result) { #if _LIBCPP_STD_VER >= 20 - __t = _VSTD::move(__t) + *__first; + __t = std::move(__t) + *__first; #else __t = __t + *__first; #endif @@ -58,7 +58,7 @@ partial_sum(_InputIterator __first, _InputIterator __last, _OutputIterator __res for (++__first, (void) ++__result; __first != __last; ++__first, (void) ++__result) { #if _LIBCPP_STD_VER >= 20 - __t = __binary_op(_VSTD::move(__t), *__first); + __t = __binary_op(std::move(__t), *__first); #else __t = __binary_op(__t, *__first); #endif diff --git a/libcxx/include/__numeric/reduce.h b/libcxx/include/__numeric/reduce.h index df1b93d17955..eb53053c26a6 100644 --- a/libcxx/include/__numeric/reduce.h +++ b/libcxx/include/__numeric/reduce.h @@ -33,13 +33,13 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp reduce(_InputIterator __ template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp reduce(_InputIterator __first, _InputIterator __last, _Tp __init) { - return _VSTD::reduce(__first, __last, __init, _VSTD::plus<>()); + return std::reduce(__first, __last, __init, std::plus<>()); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 typename iterator_traits<_InputIterator>::value_type reduce(_InputIterator __first, _InputIterator __last) { - return _VSTD::reduce(__first, __last, typename iterator_traits<_InputIterator>::value_type{}); + return std::reduce(__first, __last, typename iterator_traits<_InputIterator>::value_type{}); } #endif diff --git a/libcxx/include/__numeric/transform_inclusive_scan.h b/libcxx/include/__numeric/transform_inclusive_scan.h index be153bccc857..e1b818ca58e0 100644 --- a/libcxx/include/__numeric/transform_inclusive_scan.h +++ b/libcxx/include/__numeric/transform_inclusive_scan.h @@ -45,7 +45,7 @@ transform_inclusive_scan(_InputIterator __first, _InputIterator __last, typename iterator_traits<_InputIterator>::value_type __init = __u(*__first); *__result++ = __init; if (++__first != __last) - return _VSTD::transform_inclusive_scan(__first, __last, __result, __b, __u, __init); + return std::transform_inclusive_scan(__first, __last, __result, __b, __u, __init); } return __result; diff --git a/libcxx/include/__numeric/transform_reduce.h b/libcxx/include/__numeric/transform_reduce.h index 05f48841ebc1..04d02b6c6a6b 100644 --- a/libcxx/include/__numeric/transform_reduce.h +++ b/libcxx/include/__numeric/transform_reduce.h @@ -44,8 +44,8 @@ template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp transform_reduce(_InputIterator1 __first1, _InputIterator1 __last1, _InputIterator2 __first2, _Tp __init) { - return _VSTD::transform_reduce(__first1, __last1, __first2, _VSTD::move(__init), _VSTD::plus<>(), - _VSTD::multiplies<>()); + return std::transform_reduce(__first1, __last1, __first2, std::move(__init), std::plus<>(), + std::multiplies<>()); } #endif diff --git a/libcxx/include/__random/binomial_distribution.h b/libcxx/include/__random/binomial_distribution.h index 492cafd388e0..03661b19bebf 100644 --- a/libcxx/include/__random/binomial_distribution.h +++ b/libcxx/include/__random/binomial_distribution.h @@ -134,10 +134,10 @@ binomial_distribution<_IntType>::param_type::param_type(result_type __t, double if (0 < __p_ && __p_ < 1) { __r0_ = static_cast((__t_ + 1) * __p_); - __pr_ = _VSTD::exp(std::__libcpp_lgamma(__t_ + 1.) - + __pr_ = std::exp(std::__libcpp_lgamma(__t_ + 1.) - std::__libcpp_lgamma(__r0_ + 1.) - - std::__libcpp_lgamma(__t_ - __r0_ + 1.) + __r0_ * _VSTD::log(__p_) + - (__t_ - __r0_) * _VSTD::log(1 - __p_)); + std::__libcpp_lgamma(__t_ - __r0_ + 1.) + __r0_ * std::log(__p_) + + (__t_ - __r0_) * std::log(1 - __p_)); __odds_ratio_ = __p_ / (1 - __p_); } } diff --git a/libcxx/include/__random/cauchy_distribution.h b/libcxx/include/__random/cauchy_distribution.h index 667de9fcffb4..b057074ab8d8 100644 --- a/libcxx/include/__random/cauchy_distribution.h +++ b/libcxx/include/__random/cauchy_distribution.h @@ -120,7 +120,7 @@ cauchy_distribution<_RealType>::operator()(_URNG& __g, const param_type& __p) static_assert(__libcpp_random_is_valid_urng<_URNG>::value, ""); uniform_real_distribution __gen; // purposefully let tan arg get as close to pi/2 as it wants, tan will return a finite - return __p.a() + __p.b() * _VSTD::tan(3.1415926535897932384626433832795 * __gen(__g)); + return __p.a() + __p.b() * std::tan(3.1415926535897932384626433832795 * __gen(__g)); } template diff --git a/libcxx/include/__random/discard_block_engine.h b/libcxx/include/__random/discard_block_engine.h index f6c670e95d55..8ce5a1cf2cb2 100644 --- a/libcxx/include/__random/discard_block_engine.h +++ b/libcxx/include/__random/discard_block_engine.h @@ -68,7 +68,7 @@ public: #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI explicit discard_block_engine(_Engine&& __e) - : __e_(_VSTD::move(__e)), __n_(0) {} + : __e_(std::move(__e)), __n_(0) {} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI explicit discard_block_engine(result_type __sd) : __e_(__sd), __n_(0) {} diff --git a/libcxx/include/__random/discrete_distribution.h b/libcxx/include/__random/discrete_distribution.h index a89172c1b571..9f0bc3591439 100644 --- a/libcxx/include/__random/discrete_distribution.h +++ b/libcxx/include/__random/discrete_distribution.h @@ -180,11 +180,11 @@ discrete_distribution<_IntType>::param_type::__init() { if (__p_.size() > 1) { - double __s = _VSTD::accumulate(__p_.begin(), __p_.end(), 0.0); + double __s = std::accumulate(__p_.begin(), __p_.end(), 0.0); for (vector::iterator __i = __p_.begin(), __e = __p_.end(); __i < __e; ++__i) *__i /= __s; vector __t(__p_.size() - 1); - _VSTD::partial_sum(__p_.begin(), __p_.end() - 1, __t.begin()); + std::partial_sum(__p_.begin(), __p_.end() - 1, __t.begin()); swap(__p_, __t); } else @@ -201,7 +201,7 @@ discrete_distribution<_IntType>::param_type::probabilities() const { size_t __n = __p_.size(); vector __p(__n+1); - _VSTD::adjacent_difference(__p_.begin(), __p_.end(), __p.begin()); + std::adjacent_difference(__p_.begin(), __p_.end(), __p.begin()); if (__n > 0) __p[__n] = 1 - __p_[__n-1]; else @@ -217,7 +217,7 @@ discrete_distribution<_IntType>::operator()(_URNG& __g, const param_type& __p) static_assert(__libcpp_random_is_valid_urng<_URNG>::value, ""); uniform_real_distribution __gen; return static_cast<_IntType>( - _VSTD::upper_bound(__p.__p_.begin(), __p.__p_.end(), __gen(__g)) - + std::upper_bound(__p.__p_.begin(), __p.__p_.end(), __gen(__g)) - __p.__p_.begin()); } diff --git a/libcxx/include/__random/exponential_distribution.h b/libcxx/include/__random/exponential_distribution.h index fcf4814b36e9..e5f0dad8cb88 100644 --- a/libcxx/include/__random/exponential_distribution.h +++ b/libcxx/include/__random/exponential_distribution.h @@ -112,10 +112,10 @@ _RealType exponential_distribution<_RealType>::operator()(_URNG& __g, const param_type& __p) { static_assert(__libcpp_random_is_valid_urng<_URNG>::value, ""); - return -_VSTD::log + return -std::log ( result_type(1) - - _VSTD::generate_canonical::digits>(__g) ) / __p.lambda(); diff --git a/libcxx/include/__random/extreme_value_distribution.h b/libcxx/include/__random/extreme_value_distribution.h index e13db96a5384..4afc27598157 100644 --- a/libcxx/include/__random/extreme_value_distribution.h +++ b/libcxx/include/__random/extreme_value_distribution.h @@ -120,7 +120,7 @@ extreme_value_distribution<_RealType>::operator()(_URNG& __g, const param_type& { static_assert(__libcpp_random_is_valid_urng<_URNG>::value, ""); return __p.a() - __p.b() * - _VSTD::log(-_VSTD::log(1-uniform_real_distribution()(__g))); + std::log(-std::log(1-uniform_real_distribution()(__g))); } template diff --git a/libcxx/include/__random/gamma_distribution.h b/libcxx/include/__random/gamma_distribution.h index d3591a3c8766..e2f04ad51727 100644 --- a/libcxx/include/__random/gamma_distribution.h +++ b/libcxx/include/__random/gamma_distribution.h @@ -137,7 +137,7 @@ gamma_distribution<_RealType>::operator()(_URNG& __g, const param_type& __p) const result_type __w = __u * (1 - __u); if (__w != 0) { - const result_type __y = _VSTD::sqrt(__c / __w) * + const result_type __y = std::sqrt(__c / __w) * (__u - result_type(0.5)); __x = __b + __y; if (__x >= 0) @@ -145,7 +145,7 @@ gamma_distribution<_RealType>::operator()(_URNG& __g, const param_type& __p) const result_type __z = 64 * __w * __w * __w * __v * __v; if (__z <= 1 - 2 * __y * __y / __x) break; - if (_VSTD::log(__z) <= 2 * (__b * _VSTD::log(__x / __b) - __y)) + if (std::log(__z) <= 2 * (__b * std::log(__x / __b) - __y)) break; } } @@ -159,14 +159,14 @@ gamma_distribution<_RealType>::operator()(_URNG& __g, const param_type& __p) const result_type __es = __egen(__g); if (__u <= 1 - __a) { - __x = _VSTD::pow(__u, 1 / __a); + __x = std::pow(__u, 1 / __a); if (__x <= __es) break; } else { - const result_type __e = -_VSTD::log((1-__u)/__a); - __x = _VSTD::pow(1 - __a + __a * __e, 1 / __a); + const result_type __e = -std::log((1-__u)/__a); + __x = std::pow(1 - __a + __a * __e, 1 / __a); if (__x <= __e + __es) break; } diff --git a/libcxx/include/__random/independent_bits_engine.h b/libcxx/include/__random/independent_bits_engine.h index 197c8439cc33..b81fa49d3bde 100644 --- a/libcxx/include/__random/independent_bits_engine.h +++ b/libcxx/include/__random/independent_bits_engine.h @@ -101,7 +101,7 @@ public: #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI explicit independent_bits_engine(_Engine&& __e) - : __e_(_VSTD::move(__e)) {} + : __e_(std::move(__e)) {} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI explicit independent_bits_engine(result_type __sd) : __e_(__sd) {} diff --git a/libcxx/include/__random/lognormal_distribution.h b/libcxx/include/__random/lognormal_distribution.h index a96212cdfb2a..c30f9adf103a 100644 --- a/libcxx/include/__random/lognormal_distribution.h +++ b/libcxx/include/__random/lognormal_distribution.h @@ -83,7 +83,7 @@ public: _LIBCPP_HIDE_FROM_ABI result_type operator()(_URNG& __g) { - return _VSTD::exp(__nd_(__g)); + return std::exp(__nd_(__g)); } template @@ -91,7 +91,7 @@ public: result_type operator()(_URNG& __g, const param_type& __p) { typename normal_distribution::param_type __pn(__p.m(), __p.s()); - return _VSTD::exp(__nd_(__g, __pn)); + return std::exp(__nd_(__g, __pn)); } // property functions diff --git a/libcxx/include/__random/mersenne_twister_engine.h b/libcxx/include/__random/mersenne_twister_engine.h index 6deec211b928..abc5ec255bc6 100644 --- a/libcxx/include/__random/mersenne_twister_engine.h +++ b/libcxx/include/__random/mersenne_twister_engine.h @@ -401,37 +401,37 @@ operator==(const mersenne_twister_engine<_UInt, _Wp, _Np, _Mp, _Rp, _Ap, _Up, _D _Bp, _Tp, _Cp, _Lp, _Fp>& __y) { if (__x.__i_ == __y.__i_) - return _VSTD::equal(__x.__x_, __x.__x_ + _Np, __y.__x_); + return std::equal(__x.__x_, __x.__x_ + _Np, __y.__x_); if (__x.__i_ == 0 || __y.__i_ == 0) { - size_t __j = _VSTD::min(_Np - __x.__i_, _Np - __y.__i_); - if (!_VSTD::equal(__x.__x_ + __x.__i_, __x.__x_ + __x.__i_ + __j, + size_t __j = std::min(_Np - __x.__i_, _Np - __y.__i_); + if (!std::equal(__x.__x_ + __x.__i_, __x.__x_ + __x.__i_ + __j, __y.__x_ + __y.__i_)) return false; if (__x.__i_ == 0) - return _VSTD::equal(__x.__x_ + __j, __x.__x_ + _Np, __y.__x_); - return _VSTD::equal(__x.__x_, __x.__x_ + (_Np - __j), __y.__x_ + __j); + return std::equal(__x.__x_ + __j, __x.__x_ + _Np, __y.__x_); + return std::equal(__x.__x_, __x.__x_ + (_Np - __j), __y.__x_ + __j); } if (__x.__i_ < __y.__i_) { size_t __j = _Np - __y.__i_; - if (!_VSTD::equal(__x.__x_ + __x.__i_, __x.__x_ + (__x.__i_ + __j), + if (!std::equal(__x.__x_ + __x.__i_, __x.__x_ + (__x.__i_ + __j), __y.__x_ + __y.__i_)) return false; - if (!_VSTD::equal(__x.__x_ + (__x.__i_ + __j), __x.__x_ + _Np, + if (!std::equal(__x.__x_ + (__x.__i_ + __j), __x.__x_ + _Np, __y.__x_)) return false; - return _VSTD::equal(__x.__x_, __x.__x_ + __x.__i_, + return std::equal(__x.__x_, __x.__x_ + __x.__i_, __y.__x_ + (_Np - (__x.__i_ + __j))); } size_t __j = _Np - __x.__i_; - if (!_VSTD::equal(__y.__x_ + __y.__i_, __y.__x_ + (__y.__i_ + __j), + if (!std::equal(__y.__x_ + __y.__i_, __y.__x_ + (__y.__i_ + __j), __x.__x_ + __x.__i_)) return false; - if (!_VSTD::equal(__y.__x_ + (__y.__i_ + __j), __y.__x_ + _Np, + if (!std::equal(__y.__x_ + (__y.__i_ + __j), __y.__x_ + _Np, __x.__x_)) return false; - return _VSTD::equal(__y.__x_, __y.__x_ + __y.__i_, + return std::equal(__y.__x_, __y.__x_ + __y.__i_, __x.__x_ + (_Np - (__y.__i_ + __j))); } diff --git a/libcxx/include/__random/normal_distribution.h b/libcxx/include/__random/normal_distribution.h index b4687dfa4494..14649f1757ff 100644 --- a/libcxx/include/__random/normal_distribution.h +++ b/libcxx/include/__random/normal_distribution.h @@ -152,7 +152,7 @@ normal_distribution<_RealType>::operator()(_URNG& __g, const param_type& __p) __v = __uni(__g); __s = __u * __u + __v * __v; } while (__s > 1 || __s == 0); - result_type __fp = _VSTD::sqrt(-2 * _VSTD::log(__s) / __s); + result_type __fp = std::sqrt(-2 * std::log(__s) / __s); __v_ = __v * __fp; __v_hot_ = true; __up = __u * __fp; diff --git a/libcxx/include/__random/piecewise_constant_distribution.h b/libcxx/include/__random/piecewise_constant_distribution.h index 78a79f699873..f5b90290209b 100644 --- a/libcxx/include/__random/piecewise_constant_distribution.h +++ b/libcxx/include/__random/piecewise_constant_distribution.h @@ -188,14 +188,14 @@ void piecewise_constant_distribution<_RealType>::param_type::__init() { // __densities_ contains non-normalized areas - result_type __total_area = _VSTD::accumulate(__densities_.begin(), + result_type __total_area = std::accumulate(__densities_.begin(), __densities_.end(), result_type()); for (size_t __i = 0; __i < __densities_.size(); ++__i) __densities_[__i] /= __total_area; // __densities_ contains normalized areas __areas_.assign(__densities_.size(), result_type()); - _VSTD::partial_sum(__densities_.begin(), __densities_.end() - 1, + std::partial_sum(__densities_.begin(), __densities_.end() - 1, __areas_.begin() + 1); // __areas_ contains partial sums of normalized areas: [0, __densities_ - 1] __densities_.back() = 1 - __areas_.back(); // correct round off error @@ -289,7 +289,7 @@ piecewise_constant_distribution<_RealType>::operator()(_URNG& __g, const param_t static_assert(__libcpp_random_is_valid_urng<_URNG>::value, ""); typedef uniform_real_distribution _Gen; result_type __u = _Gen()(__g); - ptrdiff_t __k = _VSTD::upper_bound(__p.__areas_.begin(), __p.__areas_.end(), + ptrdiff_t __k = std::upper_bound(__p.__areas_.begin(), __p.__areas_.end(), __u) - __p.__areas_.begin() - 1; return (__u - __p.__areas_[__k]) / __p.__densities_[__k] + __p.__b_[__k]; } diff --git a/libcxx/include/__random/piecewise_linear_distribution.h b/libcxx/include/__random/piecewise_linear_distribution.h index 1bdf26a09f14..824e089b0c34 100644 --- a/libcxx/include/__random/piecewise_linear_distribution.h +++ b/libcxx/include/__random/piecewise_linear_distribution.h @@ -294,7 +294,7 @@ piecewise_linear_distribution<_RealType>::operator()(_URNG& __g, const param_typ static_assert(__libcpp_random_is_valid_urng<_URNG>::value, ""); typedef uniform_real_distribution _Gen; result_type __u = _Gen()(__g); - ptrdiff_t __k = _VSTD::upper_bound(__p.__areas_.begin(), __p.__areas_.end(), + ptrdiff_t __k = std::upper_bound(__p.__areas_.begin(), __p.__areas_.end(), __u) - __p.__areas_.begin() - 1; __u -= __p.__areas_[__k]; const result_type __dk = __p.__densities_[__k]; @@ -306,7 +306,7 @@ piecewise_linear_distribution<_RealType>::operator()(_URNG& __g, const param_typ const result_type __bk1 = __p.__b_[__k+1]; const result_type __deltab = __bk1 - __bk; return (__bk * __dk1 - __bk1 * __dk + - _VSTD::sqrt(__deltab * (__deltab * __dk * __dk + 2 * __deltad * __u))) / + std::sqrt(__deltab * (__deltab * __dk * __dk + 2 * __deltad * __u))) / __deltad; } diff --git a/libcxx/include/__random/poisson_distribution.h b/libcxx/include/__random/poisson_distribution.h index f7e89f4b637f..12641addf494 100644 --- a/libcxx/include/__random/poisson_distribution.h +++ b/libcxx/include/__random/poisson_distribution.h @@ -131,7 +131,7 @@ poisson_distribution<_IntType>::param_type::param_type(double __mean) { __s_ = 0; __d_ = 0; - __l_ = _VSTD::exp(-__mean_); + __l_ = std::exp(-__mean_); __omega_ = 0; __c3_ = 0; __c2_ = 0; @@ -141,9 +141,9 @@ poisson_distribution<_IntType>::param_type::param_type(double __mean) } else { - __s_ = _VSTD::sqrt(__mean_); + __s_ = std::sqrt(__mean_); __d_ = 6 * __mean_ * __mean_; - __l_ = _VSTD::trunc(__mean_ - 1.1484); + __l_ = std::trunc(__mean_ - 1.1484); __omega_ = .3989423 / __s_; double __b1 = .4166667E-1 / __mean_; double __b2 = .3 * __b1 * __b1; @@ -176,13 +176,13 @@ poisson_distribution<_IntType>::operator()(_URNG& __urng, const param_type& __pr double __u; if (__g > 0) { - __tx = _VSTD::trunc(__g); + __tx = std::trunc(__g); if (__tx >= __pr.__l_) - return _VSTD::__clamp_to_integral(__tx); + return std::__clamp_to_integral(__tx); __difmuk = __pr.__mean_ - __tx; __u = __urd(__urng); if (__pr.__d_ * __u >= __difmuk * __difmuk * __difmuk) - return _VSTD::__clamp_to_integral(__tx); + return std::__clamp_to_integral(__tx); } exponential_distribution __edist; for (bool __using_exp_dist = false; true; __using_exp_dist = true) @@ -198,7 +198,7 @@ poisson_distribution<_IntType>::operator()(_URNG& __urng, const param_type& __pr __u += __u - 1; __t = 1.8 + (__u < 0 ? -__e : __e); } while (__t <= -.6744); - __tx = _VSTD::trunc(__pr.__mean_ + __pr.__s_ * __t); + __tx = std::trunc(__pr.__mean_ + __pr.__s_ * __t); __difmuk = __pr.__mean_ - __tx; __using_exp_dist = true; } @@ -209,20 +209,20 @@ poisson_distribution<_IntType>::operator()(_URNG& __urng, const param_type& __pr const double __fac[] = {1, 1, 2, 6, 24, 120, 720, 5040, 40320, 362880}; __px = -__pr.__mean_; - __py = _VSTD::pow(__pr.__mean_, (double)__tx) / __fac[static_cast(__tx)]; + __py = std::pow(__pr.__mean_, (double)__tx) / __fac[static_cast(__tx)]; } else { double __del = .8333333E-1 / __tx; __del -= 4.8 * __del * __del * __del; double __v = __difmuk / __tx; - if (_VSTD::abs(__v) > 0.25) - __px = __tx * _VSTD::log(1 + __v) - __difmuk - __del; + if (std::abs(__v) > 0.25) + __px = __tx * std::log(1 + __v) - __difmuk - __del; else __px = __tx * __v * __v * (((((((.1250060 * __v + -.1384794) * __v + .1421878) * __v + -.1661269) * __v + .2000118) * __v + -.2500068) * __v + .3333333) * __v + -.5) - __del; - __py = .3989423 / _VSTD::sqrt(__tx); + __py = .3989423 / std::sqrt(__tx); } double __r = (0.5 - __difmuk) / __pr.__s_; double __r2 = __r * __r; @@ -231,18 +231,18 @@ poisson_distribution<_IntType>::operator()(_URNG& __urng, const param_type& __pr __r2 + __pr.__c1_) * __r2 + __pr.__c0_); if (__using_exp_dist) { - if (__pr.__c_ * _VSTD::abs(__u) <= __py * _VSTD::exp(__px + __e) - - __fy * _VSTD::exp(__fx + __e)) + if (__pr.__c_ * std::abs(__u) <= __py * std::exp(__px + __e) - + __fy * std::exp(__fx + __e)) break; } else { - if (__fy - __u * __fy <= __py * _VSTD::exp(__px - __fx)) + if (__fy - __u * __fy <= __py * std::exp(__px - __fx)) break; } } } - return _VSTD::__clamp_to_integral(__tx); + return std::__clamp_to_integral(__tx); } template diff --git a/libcxx/include/__random/seed_seq.h b/libcxx/include/__random/seed_seq.h index f55b0819da3d..7ae9f492c8af 100644 --- a/libcxx/include/__random/seed_seq.h +++ b/libcxx/include/__random/seed_seq.h @@ -62,7 +62,7 @@ public: template _LIBCPP_HIDE_FROM_ABI void param(_OutputIterator __dest) const - {_VSTD::copy(__v_.begin(), __v_.end(), __dest);} + {std::copy(__v_.begin(), __v_.end(), __dest);} seed_seq(const seed_seq&) = delete; void operator=(const seed_seq&) = delete; @@ -91,7 +91,7 @@ seed_seq::generate(_RandomAccessIterator __first, _RandomAccessIterator __last) { if (__first != __last) { - _VSTD::fill(__first, __last, 0x8b8b8b8b); + std::fill(__first, __last, 0x8b8b8b8b); const size_t __n = static_cast(__last - __first); const size_t __s = __v_.size(); const size_t __t = (__n >= 623) ? 11 @@ -101,7 +101,7 @@ seed_seq::generate(_RandomAccessIterator __first, _RandomAccessIterator __last) : (__n - 1) / 2; const size_t __p = (__n - __t) / 2; const size_t __q = __p + __t; - const size_t __m = _VSTD::max(__s + 1, __n); + const size_t __m = std::max(__s + 1, __n); // __k = 0; { result_type __r = 1664525 * _Tp(__first[0] ^ __first[__p] diff --git a/libcxx/include/__random/shuffle_order_engine.h b/libcxx/include/__random/shuffle_order_engine.h index 859fee01a0d0..4836dee48926 100644 --- a/libcxx/include/__random/shuffle_order_engine.h +++ b/libcxx/include/__random/shuffle_order_engine.h @@ -94,7 +94,7 @@ public: #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI explicit shuffle_order_engine(_Engine&& __e) - : __e_(_VSTD::move(__e)) {__init();} + : __e_(std::move(__e)) {__init();} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI explicit shuffle_order_engine(result_type __sd) : __e_(__sd) {__init();} @@ -210,7 +210,7 @@ operator==( const shuffle_order_engine<_Eng, _Kp>& __x, const shuffle_order_engine<_Eng, _Kp>& __y) { - return __x.__y_ == __y.__y_ && _VSTD::equal(__x.__v_, __x.__v_ + _Kp, __y.__v_) && + return __x.__y_ == __y.__y_ && std::equal(__x.__v_, __x.__v_ + _Kp, __y.__v_) && __x.__e_ == __y.__e_; } diff --git a/libcxx/include/__random/student_t_distribution.h b/libcxx/include/__random/student_t_distribution.h index 5a4de5cfb37e..d52510dca4ed 100644 --- a/libcxx/include/__random/student_t_distribution.h +++ b/libcxx/include/__random/student_t_distribution.h @@ -115,7 +115,7 @@ student_t_distribution<_RealType>::operator()(_URNG& __g, const param_type& __p) { static_assert(__libcpp_random_is_valid_urng<_URNG>::value, ""); gamma_distribution __gd(__p.n() * .5, 2); - return __nd_(__g) * _VSTD::sqrt(__p.n()/__gd(__g)); + return __nd_(__g) * std::sqrt(__p.n()/__gd(__g)); } template diff --git a/libcxx/include/__random/subtract_with_carry_engine.h b/libcxx/include/__random/subtract_with_carry_engine.h index e90e236251f1..fe2a66800adc 100644 --- a/libcxx/include/__random/subtract_with_carry_engine.h +++ b/libcxx/include/__random/subtract_with_carry_engine.h @@ -253,37 +253,37 @@ operator==( if (__x.__c_ != __y.__c_) return false; if (__x.__i_ == __y.__i_) - return _VSTD::equal(__x.__x_, __x.__x_ + _Rp, __y.__x_); + return std::equal(__x.__x_, __x.__x_ + _Rp, __y.__x_); if (__x.__i_ == 0 || __y.__i_ == 0) { - size_t __j = _VSTD::min(_Rp - __x.__i_, _Rp - __y.__i_); - if (!_VSTD::equal(__x.__x_ + __x.__i_, __x.__x_ + __x.__i_ + __j, + size_t __j = std::min(_Rp - __x.__i_, _Rp - __y.__i_); + if (!std::equal(__x.__x_ + __x.__i_, __x.__x_ + __x.__i_ + __j, __y.__x_ + __y.__i_)) return false; if (__x.__i_ == 0) - return _VSTD::equal(__x.__x_ + __j, __x.__x_ + _Rp, __y.__x_); - return _VSTD::equal(__x.__x_, __x.__x_ + (_Rp - __j), __y.__x_ + __j); + return std::equal(__x.__x_ + __j, __x.__x_ + _Rp, __y.__x_); + return std::equal(__x.__x_, __x.__x_ + (_Rp - __j), __y.__x_ + __j); } if (__x.__i_ < __y.__i_) { size_t __j = _Rp - __y.__i_; - if (!_VSTD::equal(__x.__x_ + __x.__i_, __x.__x_ + (__x.__i_ + __j), + if (!std::equal(__x.__x_ + __x.__i_, __x.__x_ + (__x.__i_ + __j), __y.__x_ + __y.__i_)) return false; - if (!_VSTD::equal(__x.__x_ + (__x.__i_ + __j), __x.__x_ + _Rp, + if (!std::equal(__x.__x_ + (__x.__i_ + __j), __x.__x_ + _Rp, __y.__x_)) return false; - return _VSTD::equal(__x.__x_, __x.__x_ + __x.__i_, + return std::equal(__x.__x_, __x.__x_ + __x.__i_, __y.__x_ + (_Rp - (__x.__i_ + __j))); } size_t __j = _Rp - __x.__i_; - if (!_VSTD::equal(__y.__x_ + __y.__i_, __y.__x_ + (__y.__i_ + __j), + if (!std::equal(__y.__x_ + __y.__i_, __y.__x_ + (__y.__i_ + __j), __x.__x_ + __x.__i_)) return false; - if (!_VSTD::equal(__y.__x_ + (__y.__i_ + __j), __y.__x_ + _Rp, + if (!std::equal(__y.__x_ + (__y.__i_ + __j), __y.__x_ + _Rp, __x.__x_)) return false; - return _VSTD::equal(__y.__x_, __y.__x_ + __y.__i_, + return std::equal(__y.__x_, __y.__x_ + __y.__i_, __x.__x_ + (_Rp - (__y.__i_ + __j))); } diff --git a/libcxx/include/__random/uniform_real_distribution.h b/libcxx/include/__random/uniform_real_distribution.h index 81fc3cd9ea8a..c5ee527353ab 100644 --- a/libcxx/include/__random/uniform_real_distribution.h +++ b/libcxx/include/__random/uniform_real_distribution.h @@ -117,7 +117,7 @@ uniform_real_distribution<_RealType>::operator()(_URNG& __g, const param_type& _ { static_assert(__libcpp_random_is_valid_urng<_URNG>::value, ""); return (__p.b() - __p.a()) - * _VSTD::generate_canonical<_RealType, numeric_limits<_RealType>::digits>(__g) + * std::generate_canonical<_RealType, numeric_limits<_RealType>::digits>(__g) + __p.a(); } diff --git a/libcxx/include/__random/weibull_distribution.h b/libcxx/include/__random/weibull_distribution.h index 62741148a670..099cfdd6171b 100644 --- a/libcxx/include/__random/weibull_distribution.h +++ b/libcxx/include/__random/weibull_distribution.h @@ -86,7 +86,7 @@ public: _LIBCPP_HIDE_FROM_ABI result_type operator()(_URNG& __g, const param_type& __p) {return __p.b() * - _VSTD::pow(exponential_distribution()(__g), 1/__p.a());} + std::pow(exponential_distribution()(__g), 1/__p.a());} // property functions _LIBCPP_HIDE_FROM_ABI diff --git a/libcxx/include/__split_buffer b/libcxx/include/__split_buffer index da73f4c83225..07dedba5e801 100644 --- a/libcxx/include/__split_buffer +++ b/libcxx/include/__split_buffer @@ -198,7 +198,7 @@ public: private: _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __move_assign_alloc(__split_buffer& __c, true_type) _NOEXCEPT_(is_nothrow_move_assignable::value) { - __alloc() = _VSTD::move(__c.__alloc()); + __alloc() = std::move(__c.__alloc()); } _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __move_assign_alloc(__split_buffer&, false_type) _NOEXCEPT {} @@ -258,7 +258,7 @@ __split_buffer<_Tp, _Allocator>::__construct_at_end(size_type __n) { _ConstructTransaction __tx(&this->__end_, __n); for (; __tx.__pos_ != __tx.__end_; ++__tx.__pos_) { - __alloc_traits::construct(this->__alloc(), _VSTD::__to_address(__tx.__pos_)); + __alloc_traits::construct(this->__alloc(), std::__to_address(__tx.__pos_)); } } @@ -276,7 +276,7 @@ __split_buffer<_Tp, _Allocator>::__construct_at_end(size_type __n, const_referen _ConstructTransaction __tx(&this->__end_, __n); for (; __tx.__pos_ != __tx.__end_; ++__tx.__pos_) { __alloc_traits::construct(this->__alloc(), - _VSTD::__to_address(__tx.__pos_), __x); + std::__to_address(__tx.__pos_), __x); } } @@ -298,14 +298,14 @@ void __split_buffer<_Tp, _Allocator>::__construct_at_end_with_sentinel(_Iterator if (__end_ == __end_cap()) { size_type __old_cap = __end_cap() - __first_; - size_type __new_cap = _VSTD::max(2 * __old_cap, 8); + size_type __new_cap = std::max(2 * __old_cap, 8); __split_buffer __buf(__new_cap, 0, __a); for (pointer __p = __begin_; __p != __end_; ++__p, (void) ++__buf.__end_) __alloc_traits::construct(__buf.__alloc(), - _VSTD::__to_address(__buf.__end_), _VSTD::move(*__p)); + std::__to_address(__buf.__end_), std::move(*__p)); swap(__buf); } - __alloc_traits::construct(__a, _VSTD::__to_address(this->__end_), *__first); + __alloc_traits::construct(__a, std::__to_address(this->__end_), *__first); ++this->__end_; } } @@ -324,7 +324,7 @@ void __split_buffer<_Tp, _Allocator>::__construct_at_end_with_size(_ForwardItera _ConstructTransaction __tx(&this->__end_, __n); for (; __tx.__pos_ != __tx.__end_; ++__tx.__pos_, (void) ++__first) { __alloc_traits::construct(this->__alloc(), - _VSTD::__to_address(__tx.__pos_), *__first); + std::__to_address(__tx.__pos_), *__first); } } @@ -335,7 +335,7 @@ void __split_buffer<_Tp, _Allocator>::__destruct_at_begin(pointer __new_begin, false_type) { while (__begin_ != __new_begin) - __alloc_traits::destroy(__alloc(), _VSTD::__to_address(__begin_++)); + __alloc_traits::destroy(__alloc(), std::__to_address(__begin_++)); } template @@ -354,7 +354,7 @@ void __split_buffer<_Tp, _Allocator>::__destruct_at_end(pointer __new_last, false_type) _NOEXCEPT { while (__new_last != __end_) - __alloc_traits::destroy(__alloc(), _VSTD::__to_address(--__end_)); + __alloc_traits::destroy(__alloc(), std::__to_address(--__end_)); } template @@ -395,10 +395,10 @@ template _LIBCPP_CONSTEXPR_SINCE_CXX20 __split_buffer<_Tp, _Allocator>::__split_buffer(__split_buffer&& __c) _NOEXCEPT_(is_nothrow_move_constructible::value) - : __first_(_VSTD::move(__c.__first_)), - __begin_(_VSTD::move(__c.__begin_)), - __end_(_VSTD::move(__c.__end_)), - __end_cap_(_VSTD::move(__c.__end_cap_)) + : __first_(std::move(__c.__first_)), + __begin_(std::move(__c.__begin_)), + __end_(std::move(__c.__end_)), + __end_cap_(std::move(__c.__end_cap_)) { __c.__first_ = nullptr; __c.__begin_ = nullptr; @@ -461,11 +461,11 @@ __split_buffer<_Tp, _Allocator>::swap(__split_buffer& __x) _NOEXCEPT_(!__alloc_traits::propagate_on_container_swap::value|| __is_nothrow_swappable<__alloc_rr>::value) { - _VSTD::swap(__first_, __x.__first_); - _VSTD::swap(__begin_, __x.__begin_); - _VSTD::swap(__end_, __x.__end_); - _VSTD::swap(__end_cap(), __x.__end_cap()); - _VSTD::__swap_allocator(__alloc(), __x.__alloc()); + std::swap(__first_, __x.__first_); + std::swap(__begin_, __x.__begin_); + std::swap(__end_, __x.__end_); + std::swap(__end_cap(), __x.__end_cap()); + std::__swap_allocator(__alloc(), __x.__alloc()); } template @@ -478,10 +478,10 @@ __split_buffer<_Tp, _Allocator>::reserve(size_type __n) __split_buffer __t(__n, 0, __alloc()); __t.__construct_at_end(move_iterator(__begin_), move_iterator(__end_)); - _VSTD::swap(__first_, __t.__first_); - _VSTD::swap(__begin_, __t.__begin_); - _VSTD::swap(__end_, __t.__end_); - _VSTD::swap(__end_cap(), __t.__end_cap()); + std::swap(__first_, __t.__first_); + std::swap(__begin_, __t.__begin_); + std::swap(__end_, __t.__end_); + std::swap(__end_cap(), __t.__end_cap()); } } @@ -500,10 +500,10 @@ __split_buffer<_Tp, _Allocator>::shrink_to_fit() _NOEXCEPT __t.__construct_at_end(move_iterator(__begin_), move_iterator(__end_)); __t.__end_ = __t.__begin_ + (__end_ - __begin_); - _VSTD::swap(__first_, __t.__first_); - _VSTD::swap(__begin_, __t.__begin_); - _VSTD::swap(__end_, __t.__end_); - _VSTD::swap(__end_cap(), __t.__end_cap()); + std::swap(__first_, __t.__first_); + std::swap(__begin_, __t.__begin_); + std::swap(__end_, __t.__end_); + std::swap(__end_cap(), __t.__end_cap()); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) @@ -524,7 +524,7 @@ __split_buffer<_Tp, _Allocator>::push_front(const_reference __x) { difference_type __d = __end_cap() - __end_; __d = (__d + 1) / 2; - __begin_ = _VSTD::move_backward(__begin_, __end_, __end_ + __d); + __begin_ = std::move_backward(__begin_, __end_, __end_ + __d); __end_ += __d; } else @@ -533,13 +533,13 @@ __split_buffer<_Tp, _Allocator>::push_front(const_reference __x) __split_buffer __t(__c, (__c + 3) / 4, __alloc()); __t.__construct_at_end(move_iterator(__begin_), move_iterator(__end_)); - _VSTD::swap(__first_, __t.__first_); - _VSTD::swap(__begin_, __t.__begin_); - _VSTD::swap(__end_, __t.__end_); - _VSTD::swap(__end_cap(), __t.__end_cap()); + std::swap(__first_, __t.__first_); + std::swap(__begin_, __t.__begin_); + std::swap(__end_, __t.__end_); + std::swap(__end_cap(), __t.__end_cap()); } } - __alloc_traits::construct(__alloc(), _VSTD::__to_address(__begin_-1), __x); + __alloc_traits::construct(__alloc(), std::__to_address(__begin_-1), __x); --__begin_; } @@ -554,7 +554,7 @@ __split_buffer<_Tp, _Allocator>::push_front(value_type&& __x) { difference_type __d = __end_cap() - __end_; __d = (__d + 1) / 2; - __begin_ = _VSTD::move_backward(__begin_, __end_, __end_ + __d); + __begin_ = std::move_backward(__begin_, __end_, __end_ + __d); __end_ += __d; } else @@ -563,14 +563,14 @@ __split_buffer<_Tp, _Allocator>::push_front(value_type&& __x) __split_buffer __t(__c, (__c + 3) / 4, __alloc()); __t.__construct_at_end(move_iterator(__begin_), move_iterator(__end_)); - _VSTD::swap(__first_, __t.__first_); - _VSTD::swap(__begin_, __t.__begin_); - _VSTD::swap(__end_, __t.__end_); - _VSTD::swap(__end_cap(), __t.__end_cap()); + std::swap(__first_, __t.__first_); + std::swap(__begin_, __t.__begin_); + std::swap(__end_, __t.__end_); + std::swap(__end_cap(), __t.__end_cap()); } } - __alloc_traits::construct(__alloc(), _VSTD::__to_address(__begin_-1), - _VSTD::move(__x)); + __alloc_traits::construct(__alloc(), std::__to_address(__begin_-1), + std::move(__x)); --__begin_; } @@ -586,7 +586,7 @@ __split_buffer<_Tp, _Allocator>::push_back(const_reference __x) { difference_type __d = __begin_ - __first_; __d = (__d + 1) / 2; - __end_ = _VSTD::move(__begin_, __end_, __begin_ - __d); + __end_ = std::move(__begin_, __end_, __begin_ - __d); __begin_ -= __d; } else @@ -595,13 +595,13 @@ __split_buffer<_Tp, _Allocator>::push_back(const_reference __x) __split_buffer __t(__c, __c / 4, __alloc()); __t.__construct_at_end(move_iterator(__begin_), move_iterator(__end_)); - _VSTD::swap(__first_, __t.__first_); - _VSTD::swap(__begin_, __t.__begin_); - _VSTD::swap(__end_, __t.__end_); - _VSTD::swap(__end_cap(), __t.__end_cap()); + std::swap(__first_, __t.__first_); + std::swap(__begin_, __t.__begin_); + std::swap(__end_, __t.__end_); + std::swap(__end_cap(), __t.__end_cap()); } } - __alloc_traits::construct(__alloc(), _VSTD::__to_address(__end_), __x); + __alloc_traits::construct(__alloc(), std::__to_address(__end_), __x); ++__end_; } @@ -616,7 +616,7 @@ __split_buffer<_Tp, _Allocator>::push_back(value_type&& __x) { difference_type __d = __begin_ - __first_; __d = (__d + 1) / 2; - __end_ = _VSTD::move(__begin_, __end_, __begin_ - __d); + __end_ = std::move(__begin_, __end_, __begin_ - __d); __begin_ -= __d; } else @@ -625,14 +625,14 @@ __split_buffer<_Tp, _Allocator>::push_back(value_type&& __x) __split_buffer __t(__c, __c / 4, __alloc()); __t.__construct_at_end(move_iterator(__begin_), move_iterator(__end_)); - _VSTD::swap(__first_, __t.__first_); - _VSTD::swap(__begin_, __t.__begin_); - _VSTD::swap(__end_, __t.__end_); - _VSTD::swap(__end_cap(), __t.__end_cap()); + std::swap(__first_, __t.__first_); + std::swap(__begin_, __t.__begin_); + std::swap(__end_, __t.__end_); + std::swap(__end_cap(), __t.__end_cap()); } } - __alloc_traits::construct(__alloc(), _VSTD::__to_address(__end_), - _VSTD::move(__x)); + __alloc_traits::construct(__alloc(), std::__to_address(__end_), + std::move(__x)); ++__end_; } @@ -648,7 +648,7 @@ __split_buffer<_Tp, _Allocator>::emplace_back(_Args&&... __args) { difference_type __d = __begin_ - __first_; __d = (__d + 1) / 2; - __end_ = _VSTD::move(__begin_, __end_, __begin_ - __d); + __end_ = std::move(__begin_, __end_, __begin_ - __d); __begin_ -= __d; } else @@ -657,14 +657,14 @@ __split_buffer<_Tp, _Allocator>::emplace_back(_Args&&... __args) __split_buffer __t(__c, __c / 4, __alloc()); __t.__construct_at_end(move_iterator(__begin_), move_iterator(__end_)); - _VSTD::swap(__first_, __t.__first_); - _VSTD::swap(__begin_, __t.__begin_); - _VSTD::swap(__end_, __t.__end_); - _VSTD::swap(__end_cap(), __t.__end_cap()); + std::swap(__first_, __t.__first_); + std::swap(__begin_, __t.__begin_); + std::swap(__end_, __t.__end_); + std::swap(__end_cap(), __t.__end_cap()); } } - __alloc_traits::construct(__alloc(), _VSTD::__to_address(__end_), - _VSTD::forward<_Args>(__args)...); + __alloc_traits::construct(__alloc(), std::__to_address(__end_), + std::forward<_Args>(__args)...); ++__end_; } diff --git a/libcxx/include/__string/char_traits.h b/libcxx/include/__string/char_traits.h index c1c5dc7c7070..9ec78dc3936d 100644 --- a/libcxx/include/__string/char_traits.h +++ b/libcxx/include/__string/char_traits.h @@ -710,7 +710,7 @@ inline _SizeT _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI __str_rfind(const _CharT *__p, _SizeT __sz, const _CharT* __s, _SizeT __pos, _SizeT __n) _NOEXCEPT { - __pos = _VSTD::min(__pos, __sz); + __pos = std::min(__pos, __sz); if (__n < __sz - __pos) __pos += __n; else @@ -729,7 +729,7 @@ __str_find_first_of(const _CharT *__p, _SizeT __sz, { if (__pos >= __sz || __n == 0) return __npos; - const _CharT* __r = _VSTD::__find_first_of_ce + const _CharT* __r = std::__find_first_of_ce (__p + __pos, __p + __sz, __s, __s + __n, _Traits::eq ); if (__r == __p + __sz) return __npos; diff --git a/libcxx/include/__string/extern_template_lists.h b/libcxx/include/__string/extern_template_lists.h index a833c000a289..cc536e514d4f 100644 --- a/libcxx/include/__string/extern_template_lists.h +++ b/libcxx/include/__string/extern_template_lists.h @@ -15,6 +15,8 @@ # pragma GCC system_header #endif +// clang-format off + // We maintain 2 ABI lists: // - _LIBCPP_STRING_V1_EXTERN_TEMPLATE_LIST // - _LIBCPP_STRING_UNSTABLE_EXTERN_TEMPLATE_LIST @@ -126,5 +128,6 @@ _Func(_LIBCPP_EXPORTED_FROM_ABI void basic_string<_CharType>::resize(size_type, value_type)) \ _Func(_LIBCPP_EXPORTED_FROM_ABI basic_string<_CharType>& basic_string<_CharType>::insert(size_type, basic_string const&, size_type, size_type)) +// clang-format on #endif // _LIBCPP___STRING_EXTERN_TEMPLATE_LISTS_H diff --git a/libcxx/include/__thread/thread.h b/libcxx/include/__thread/thread.h index b66d46575903..ee37a0320d69 100644 --- a/libcxx/include/__thread/thread.h +++ b/libcxx/include/__thread/thread.h @@ -196,7 +196,7 @@ public: } _LIBCPP_HIDE_FROM_ABI - void swap(thread& __t) _NOEXCEPT {_VSTD::swap(__t_, __t.__t_);} + void swap(thread& __t) _NOEXCEPT {std::swap(__t_, __t.__t_);} _LIBCPP_HIDE_FROM_ABI bool joinable() const _NOEXCEPT {return !__libcpp_thread_isnull(&__t_);} @@ -217,7 +217,7 @@ inline _LIBCPP_HIDE_FROM_ABI void __thread_execute(tuple<_TSp, _Fp, _Args...>& __t, __tuple_indices<_Indices...>) { - _VSTD::__invoke(_VSTD::move(_VSTD::get<1>(__t)), _VSTD::move(_VSTD::get<_Indices>(__t))...); + std::__invoke(std::move(std::get<1>(__t)), std::move(std::get<_Indices>(__t))...); } template @@ -226,9 +226,9 @@ void* __thread_proxy(void* __vp) { // _Fp = tuple< unique_ptr<__thread_struct>, Functor, Args...> unique_ptr<_Fp> __p(static_cast<_Fp*>(__vp)); - __thread_local_data().set_pointer(_VSTD::get<0>(*__p.get()).release()); + __thread_local_data().set_pointer(std::get<0>(*__p.get()).release()); typedef typename __make_tuple_indices::value, 2>::type _Index; - _VSTD::__thread_execute(*__p.get(), _Index()); + std::__thread_execute(*__p.get(), _Index()); return nullptr; } @@ -241,10 +241,10 @@ thread::thread(_Fp&& __f, _Args&&... __args) _TSPtr __tsp(new __thread_struct); typedef tuple<_TSPtr, __decay_t<_Fp>, __decay_t<_Args>...> _Gp; unique_ptr<_Gp> __p( - new _Gp(_VSTD::move(__tsp), - _VSTD::forward<_Fp>(__f), - _VSTD::forward<_Args>(__args)...)); - int __ec = _VSTD::__libcpp_thread_create(&__t_, &__thread_proxy<_Gp>, __p.get()); + new _Gp(std::move(__tsp), + std::forward<_Fp>(__f), + std::forward<_Args>(__args)...)); + int __ec = std::__libcpp_thread_create(&__t_, &__thread_proxy<_Gp>, __p.get()); if (__ec == 0) __p.release(); else @@ -279,7 +279,7 @@ thread::thread(_Fp __f) typedef __thread_invoke_pair<_Fp> _InvokePair; typedef unique_ptr<_InvokePair> _PairPtr; _PairPtr __pp(new _InvokePair(__f)); - int __ec = _VSTD::__libcpp_thread_create(&__t_, &__thread_proxy_cxx03<_InvokePair>, __pp.get()); + int __ec = std::__libcpp_thread_create(&__t_, &__thread_proxy_cxx03<_InvokePair>, __pp.get()); if (__ec == 0) __pp.release(); else diff --git a/libcxx/include/__threading_support b/libcxx/include/__threading_support index b5881a0e8986..3af1a778ecf7 100644 --- a/libcxx/include/__threading_support +++ b/libcxx/include/__threading_support @@ -404,7 +404,7 @@ void __libcpp_thread_yield() void __libcpp_thread_sleep_for(const chrono::nanoseconds& __ns) { - __libcpp_timespec_t __ts = _VSTD::__convert_to_timespec<__libcpp_timespec_t>(__ns); + __libcpp_timespec_t __ts = std::__convert_to_timespec<__libcpp_timespec_t>(__ns); while (nanosleep(&__ts, &__ts) == -1 && errno == EINTR); } @@ -561,7 +561,7 @@ void __libcpp_thread_yield() void __libcpp_thread_sleep_for(const chrono::nanoseconds& __ns) { - __libcpp_timespec_t __ts = _VSTD::__convert_to_timespec<__libcpp_timespec_t>(__ns); + __libcpp_timespec_t __ts = std::__convert_to_timespec<__libcpp_timespec_t>(__ns); thrd_sleep(&__ts, nullptr); } diff --git a/libcxx/include/__tree b/libcxx/include/__tree index 5d1ccf3996e4..d76cccb21c18 100644 --- a/libcxx/include/__tree +++ b/libcxx/include/__tree @@ -132,10 +132,10 @@ __tree_sub_invariant(_NodePtr __x) if (__x->__right_ && !__x->__right_->__is_black_) return 0; } - unsigned __h = _VSTD::__tree_sub_invariant(__x->__left_); + unsigned __h = std::__tree_sub_invariant(__x->__left_); if (__h == 0) return 0; // invalid left subtree - if (__h != _VSTD::__tree_sub_invariant(__x->__right_)) + if (__h != std::__tree_sub_invariant(__x->__right_)) return 0; // invalid or different height right subtree return __h + __x->__is_black_; // return black height of this node } @@ -152,13 +152,13 @@ __tree_invariant(_NodePtr __root) // check __x->__parent_ consistency if (__root->__parent_ == nullptr) return false; - if (!_VSTD::__tree_is_left_child(__root)) + if (!std::__tree_is_left_child(__root)) return false; // root must be black if (!__root->__is_black_) return false; // do normal node checks - return _VSTD::__tree_sub_invariant(__root) != 0; + return std::__tree_sub_invariant(__root) != 0; } // Returns: pointer to the left-most node under __x. @@ -192,8 +192,8 @@ __tree_next(_NodePtr __x) _NOEXCEPT { _LIBCPP_ASSERT_INTERNAL(__x != nullptr, "node shouldn't be null"); if (__x->__right_ != nullptr) - return _VSTD::__tree_min(__x->__right_); - while (!_VSTD::__tree_is_left_child(__x)) + return std::__tree_min(__x->__right_); + while (!std::__tree_is_left_child(__x)) __x = __x->__parent_unsafe(); return __x->__parent_unsafe(); } @@ -205,8 +205,8 @@ __tree_next_iter(_NodePtr __x) _NOEXCEPT { _LIBCPP_ASSERT_INTERNAL(__x != nullptr, "node shouldn't be null"); if (__x->__right_ != nullptr) - return static_cast<_EndNodePtr>(_VSTD::__tree_min(__x->__right_)); - while (!_VSTD::__tree_is_left_child(__x)) + return static_cast<_EndNodePtr>(std::__tree_min(__x->__right_)); + while (!std::__tree_is_left_child(__x)) __x = __x->__parent_unsafe(); return static_cast<_EndNodePtr>(__x->__parent_); } @@ -220,9 +220,9 @@ __tree_prev_iter(_EndNodePtr __x) _NOEXCEPT { _LIBCPP_ASSERT_INTERNAL(__x != nullptr, "node shouldn't be null"); if (__x->__left_ != nullptr) - return _VSTD::__tree_max(__x->__left_); + return std::__tree_max(__x->__left_); _NodePtr __xx = static_cast<_NodePtr>(__x); - while (_VSTD::__tree_is_left_child(__xx)) + while (std::__tree_is_left_child(__xx)) __xx = __xx->__parent_unsafe(); return __xx->__parent_unsafe(); } @@ -263,7 +263,7 @@ __tree_left_rotate(_NodePtr __x) _NOEXCEPT if (__x->__right_ != nullptr) __x->__right_->__set_parent(__x); __y->__parent_ = __x->__parent_; - if (_VSTD::__tree_is_left_child(__x)) + if (std::__tree_is_left_child(__x)) __x->__parent_->__left_ = __y; else __x->__parent_unsafe()->__right_ = __y; @@ -284,7 +284,7 @@ __tree_right_rotate(_NodePtr __x) _NOEXCEPT if (__x->__left_ != nullptr) __x->__left_->__set_parent(__x); __y->__parent_ = __x->__parent_; - if (_VSTD::__tree_is_left_child(__x)) + if (std::__tree_is_left_child(__x)) __x->__parent_->__left_ = __y; else __x->__parent_unsafe()->__right_ = __y; @@ -309,7 +309,7 @@ __tree_balance_after_insert(_NodePtr __root, _NodePtr __x) _NOEXCEPT while (__x != __root && !__x->__parent_unsafe()->__is_black_) { // __x->__parent_ != __root because __x->__parent_->__is_black == false - if (_VSTD::__tree_is_left_child(__x->__parent_unsafe())) + if (std::__tree_is_left_child(__x->__parent_unsafe())) { _NodePtr __y = __x->__parent_unsafe()->__parent_unsafe()->__right_; if (__y != nullptr && !__y->__is_black_) @@ -322,16 +322,16 @@ __tree_balance_after_insert(_NodePtr __root, _NodePtr __x) _NOEXCEPT } else { - if (!_VSTD::__tree_is_left_child(__x)) + if (!std::__tree_is_left_child(__x)) { __x = __x->__parent_unsafe(); - _VSTD::__tree_left_rotate(__x); + std::__tree_left_rotate(__x); } __x = __x->__parent_unsafe(); __x->__is_black_ = true; __x = __x->__parent_unsafe(); __x->__is_black_ = false; - _VSTD::__tree_right_rotate(__x); + std::__tree_right_rotate(__x); break; } } @@ -348,16 +348,16 @@ __tree_balance_after_insert(_NodePtr __root, _NodePtr __x) _NOEXCEPT } else { - if (_VSTD::__tree_is_left_child(__x)) + if (std::__tree_is_left_child(__x)) { __x = __x->__parent_unsafe(); - _VSTD::__tree_right_rotate(__x); + std::__tree_right_rotate(__x); } __x = __x->__parent_unsafe(); __x->__is_black_ = true; __x = __x->__parent_unsafe(); __x->__is_black_ = false; - _VSTD::__tree_left_rotate(__x); + std::__tree_left_rotate(__x); break; } } @@ -381,7 +381,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT // __y will have at most one child. // __y will be the initial hole in the tree (make the hole at a leaf) _NodePtr __y = (__z->__left_ == nullptr || __z->__right_ == nullptr) ? - __z : _VSTD::__tree_next(__z); + __z : std::__tree_next(__z); // __x is __y's possibly null single child _NodePtr __x = __y->__left_ != nullptr ? __y->__left_ : __y->__right_; // __w is __x's possibly null uncle (will become __x's sibling) @@ -389,7 +389,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT // link __x to __y's parent, and find __w if (__x != nullptr) __x->__parent_ = __y->__parent_; - if (_VSTD::__tree_is_left_child(__y)) + if (std::__tree_is_left_child(__y)) { __y->__parent_->__left_ = __x; if (__y != __root) @@ -410,7 +410,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT { // __z->__left_ != nulptr but __z->__right_ might == __x == nullptr __y->__parent_ = __z->__parent_; - if (_VSTD::__tree_is_left_child(__z)) + if (std::__tree_is_left_child(__z)) __y->__parent_->__left_ = __y; else __y->__parent_unsafe()->__right_ = __y; @@ -450,13 +450,13 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT // with a non-null black child). while (true) { - if (!_VSTD::__tree_is_left_child(__w)) // if x is left child + if (!std::__tree_is_left_child(__w)) // if x is left child { if (!__w->__is_black_) { __w->__is_black_ = true; __w->__parent_unsafe()->__is_black_ = false; - _VSTD::__tree_left_rotate(__w->__parent_unsafe()); + std::__tree_left_rotate(__w->__parent_unsafe()); // __x is still valid // reset __root only if necessary if (__root == __w->__left_) @@ -477,7 +477,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT break; } // reset sibling, and it still can't be null - __w = _VSTD::__tree_is_left_child(__x) ? + __w = std::__tree_is_left_child(__x) ? __x->__parent_unsafe()->__right_ : __x->__parent_->__left_; // continue; @@ -489,7 +489,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT // __w left child is non-null and red __w->__left_->__is_black_ = true; __w->__is_black_ = false; - _VSTD::__tree_right_rotate(__w); + std::__tree_right_rotate(__w); // __w is known not to be root, so root hasn't changed // reset sibling, and it still can't be null __w = __w->__parent_unsafe(); @@ -498,7 +498,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT __w->__is_black_ = __w->__parent_unsafe()->__is_black_; __w->__parent_unsafe()->__is_black_ = true; __w->__right_->__is_black_ = true; - _VSTD::__tree_left_rotate(__w->__parent_unsafe()); + std::__tree_left_rotate(__w->__parent_unsafe()); break; } } @@ -508,7 +508,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT { __w->__is_black_ = true; __w->__parent_unsafe()->__is_black_ = false; - _VSTD::__tree_right_rotate(__w->__parent_unsafe()); + std::__tree_right_rotate(__w->__parent_unsafe()); // __x is still valid // reset __root only if necessary if (__root == __w->__right_) @@ -529,7 +529,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT break; } // reset sibling, and it still can't be null - __w = _VSTD::__tree_is_left_child(__x) ? + __w = std::__tree_is_left_child(__x) ? __x->__parent_unsafe()->__right_ : __x->__parent_->__left_; // continue; @@ -541,7 +541,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT // __w right child is non-null and red __w->__right_->__is_black_ = true; __w->__is_black_ = false; - _VSTD::__tree_left_rotate(__w); + std::__tree_left_rotate(__w); // __w is known not to be root, so root hasn't changed // reset sibling, and it still can't be null __w = __w->__parent_unsafe(); @@ -550,7 +550,7 @@ __tree_remove(_NodePtr __root, _NodePtr __z) _NOEXCEPT __w->__is_black_ = __w->__parent_unsafe()->__is_black_; __w->__parent_unsafe()->__is_black_ = true; __w->__left_->__is_black_ = true; - _VSTD::__tree_right_rotate(__w->__parent_unsafe()); + std::__tree_right_rotate(__w->__parent_unsafe()); break; } } @@ -591,11 +591,11 @@ struct __tree_key_value_types { } _LIBCPP_HIDE_FROM_ABI static __container_value_type* __get_ptr(__node_value_type& __n) { - return _VSTD::addressof(__n); + return std::addressof(__n); } _LIBCPP_HIDE_FROM_ABI static __container_value_type&& __move(__node_value_type& __v) { - return _VSTD::move(__v); + return std::move(__v); } }; @@ -636,7 +636,7 @@ struct __tree_key_value_types<__value_type<_Key, _Tp> > { _LIBCPP_HIDE_FROM_ABI static __container_value_type* __get_ptr(__node_value_type& __n) { - return _VSTD::addressof(__n.__get_value()); + return std::addressof(__n.__get_value()); } _LIBCPP_HIDE_FROM_ABI @@ -864,7 +864,7 @@ public: _LIBCPP_HIDE_FROM_ABI __tree_iterator& operator++() { __ptr_ = static_cast<__iter_pointer>( - _VSTD::__tree_next_iter<__end_node_pointer>(static_cast<__node_base_pointer>(__ptr_))); + std::__tree_next_iter<__end_node_pointer>(static_cast<__node_base_pointer>(__ptr_))); return *this; } _LIBCPP_HIDE_FROM_ABI @@ -873,7 +873,7 @@ public: _LIBCPP_HIDE_FROM_ABI __tree_iterator& operator--() { - __ptr_ = static_cast<__iter_pointer>(_VSTD::__tree_prev_iter<__node_base_pointer>( + __ptr_ = static_cast<__iter_pointer>(std::__tree_prev_iter<__node_base_pointer>( static_cast<__end_node_pointer>(__ptr_))); return *this; } @@ -945,7 +945,7 @@ public: _LIBCPP_HIDE_FROM_ABI __tree_const_iterator& operator++() { __ptr_ = static_cast<__iter_pointer>( - _VSTD::__tree_next_iter<__end_node_pointer>(static_cast<__node_base_pointer>(__ptr_))); + std::__tree_next_iter<__end_node_pointer>(static_cast<__node_base_pointer>(__ptr_))); return *this; } @@ -955,7 +955,7 @@ public: _LIBCPP_HIDE_FROM_ABI __tree_const_iterator& operator--() { - __ptr_ = static_cast<__iter_pointer>(_VSTD::__tree_prev_iter<__node_base_pointer>( + __ptr_ = static_cast<__iter_pointer>(std::__tree_prev_iter<__node_base_pointer>( static_cast<__end_node_pointer>(__ptr_))); return *this; } @@ -1103,7 +1103,7 @@ public: {return static_cast<__node_pointer>(__end_node()->__left_);} _LIBCPP_HIDE_FROM_ABI __node_base_pointer* __root_ptr() const _NOEXCEPT { - return _VSTD::addressof(__end_node()->__left_); + return std::addressof(__end_node()->__left_); } typedef __tree_iterator iterator; @@ -1144,7 +1144,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type max_size() const _NOEXCEPT - {return _VSTD::min( + {return std::min( __node_traits::max_size(__node_alloc()), numeric_limits::max());} @@ -1183,7 +1183,7 @@ public: template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique(_Pp&& __x) { - return __emplace_unique_extract_key(_VSTD::forward<_Pp>(__x), + return __emplace_unique_extract_key(std::forward<_Pp>(__x), __can_extract_key<_Pp, key_type>()); } @@ -1192,41 +1192,41 @@ public: _LIBCPP_HIDE_FROM_ABI pair __emplace_unique(_First&& __f, _Second&& __s) { - return __emplace_unique_key_args(__f, _VSTD::forward<_First>(__f), - _VSTD::forward<_Second>(__s)); + return __emplace_unique_key_args(__f, std::forward<_First>(__f), + std::forward<_Second>(__s)); } template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique(_Args&&... __args) { - return __emplace_unique_impl(_VSTD::forward<_Args>(__args)...); + return __emplace_unique_impl(std::forward<_Args>(__args)...); } template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique_extract_key(_Pp&& __x, __extract_key_fail_tag) { - return __emplace_unique_impl(_VSTD::forward<_Pp>(__x)); + return __emplace_unique_impl(std::forward<_Pp>(__x)); } template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique_extract_key(_Pp&& __x, __extract_key_self_tag) { - return __emplace_unique_key_args(__x, _VSTD::forward<_Pp>(__x)); + return __emplace_unique_key_args(__x, std::forward<_Pp>(__x)); } template _LIBCPP_HIDE_FROM_ABI pair __emplace_unique_extract_key(_Pp&& __x, __extract_key_first_tag) { - return __emplace_unique_key_args(__x.first, _VSTD::forward<_Pp>(__x)); + return __emplace_unique_key_args(__x.first, std::forward<_Pp>(__x)); } template _LIBCPP_HIDE_FROM_ABI iterator __emplace_hint_unique(const_iterator __p, _Pp&& __x) { - return __emplace_hint_unique_extract_key(__p, _VSTD::forward<_Pp>(__x), + return __emplace_hint_unique_extract_key(__p, std::forward<_Pp>(__x), __can_extract_key<_Pp, key_type>()); } @@ -1236,35 +1236,35 @@ public: iterator __emplace_hint_unique(const_iterator __p, _First&& __f, _Second&& __s) { return __emplace_hint_unique_key_args(__p, __f, - _VSTD::forward<_First>(__f), - _VSTD::forward<_Second>(__s)).first; + std::forward<_First>(__f), + std::forward<_Second>(__s)).first; } template _LIBCPP_HIDE_FROM_ABI iterator __emplace_hint_unique(const_iterator __p, _Args&&... __args) { - return __emplace_hint_unique_impl(__p, _VSTD::forward<_Args>(__args)...); + return __emplace_hint_unique_impl(__p, std::forward<_Args>(__args)...); } template _LIBCPP_HIDE_FROM_ABI iterator __emplace_hint_unique_extract_key(const_iterator __p, _Pp&& __x, __extract_key_fail_tag) { - return __emplace_hint_unique_impl(__p, _VSTD::forward<_Pp>(__x)); + return __emplace_hint_unique_impl(__p, std::forward<_Pp>(__x)); } template _LIBCPP_HIDE_FROM_ABI iterator __emplace_hint_unique_extract_key(const_iterator __p, _Pp&& __x, __extract_key_self_tag) { - return __emplace_hint_unique_key_args(__p, __x, _VSTD::forward<_Pp>(__x)).first; + return __emplace_hint_unique_key_args(__p, __x, std::forward<_Pp>(__x)).first; } template _LIBCPP_HIDE_FROM_ABI iterator __emplace_hint_unique_extract_key(const_iterator __p, _Pp&& __x, __extract_key_first_tag) { - return __emplace_hint_unique_key_args(__p, __x.first, _VSTD::forward<_Pp>(__x)).first; + return __emplace_hint_unique_key_args(__p, __x.first, std::forward<_Pp>(__x)).first; } _LIBCPP_HIDE_FROM_ABI @@ -1279,48 +1279,48 @@ public: _LIBCPP_HIDE_FROM_ABI pair __insert_unique(__container_value_type&& __v) { - return __emplace_unique_key_args(_NodeTypes::__get_key(__v), _VSTD::move(__v)); + return __emplace_unique_key_args(_NodeTypes::__get_key(__v), std::move(__v)); } _LIBCPP_HIDE_FROM_ABI iterator __insert_unique(const_iterator __p, __container_value_type&& __v) { - return __emplace_hint_unique_key_args(__p, _NodeTypes::__get_key(__v), _VSTD::move(__v)).first; + return __emplace_hint_unique_key_args(__p, _NodeTypes::__get_key(__v), std::move(__v)).first; } template , __container_value_type>::value> > _LIBCPP_HIDE_FROM_ABI pair __insert_unique(_Vp&& __v) { - return __emplace_unique(_VSTD::forward<_Vp>(__v)); + return __emplace_unique(std::forward<_Vp>(__v)); } template , __container_value_type>::value> > _LIBCPP_HIDE_FROM_ABI iterator __insert_unique(const_iterator __p, _Vp&& __v) { - return __emplace_hint_unique(__p, _VSTD::forward<_Vp>(__v)); + return __emplace_hint_unique(__p, std::forward<_Vp>(__v)); } _LIBCPP_HIDE_FROM_ABI iterator __insert_multi(__container_value_type&& __v) { - return __emplace_multi(_VSTD::move(__v)); + return __emplace_multi(std::move(__v)); } _LIBCPP_HIDE_FROM_ABI iterator __insert_multi(const_iterator __p, __container_value_type&& __v) { - return __emplace_hint_multi(__p, _VSTD::move(__v)); + return __emplace_hint_multi(__p, std::move(__v)); } template _LIBCPP_HIDE_FROM_ABI iterator __insert_multi(_Vp&& __v) { - return __emplace_multi(_VSTD::forward<_Vp>(__v)); + return __emplace_multi(std::forward<_Vp>(__v)); } template _LIBCPP_HIDE_FROM_ABI iterator __insert_multi(const_iterator __p, _Vp&& __v) { - return __emplace_hint_multi(__p, _VSTD::forward<_Vp>(__v)); + return __emplace_hint_multi(__p, std::forward<_Vp>(__v)); } _LIBCPP_HIDE_FROM_ABI @@ -1493,7 +1493,7 @@ private: _LIBCPP_HIDE_FROM_ABI void __move_assign_alloc(__tree& __t, true_type) _NOEXCEPT_(is_nothrow_move_assignable<__node_allocator>::value) - {__node_alloc() = _VSTD::move(__t.__node_alloc());} + {__node_alloc() = std::move(__t.__node_alloc());} _LIBCPP_HIDE_FROM_ABI void __move_assign_alloc(__tree&, false_type) _NOEXCEPT {} @@ -1603,27 +1603,27 @@ __tree<_Tp, _Compare, _Allocator>::_DetachedTreeCache::__detach_next(__node_poin { if (__cache->__parent_ == nullptr) return nullptr; - if (_VSTD::__tree_is_left_child(static_cast<__node_base_pointer>(__cache))) + if (std::__tree_is_left_child(static_cast<__node_base_pointer>(__cache))) { __cache->__parent_->__left_ = nullptr; __cache = static_cast<__node_pointer>(__cache->__parent_); if (__cache->__right_ == nullptr) return __cache; - return static_cast<__node_pointer>(_VSTD::__tree_leaf(__cache->__right_)); + return static_cast<__node_pointer>(std::__tree_leaf(__cache->__right_)); } // __cache is right child __cache->__parent_unsafe()->__right_ = nullptr; __cache = static_cast<__node_pointer>(__cache->__parent_); if (__cache->__left_ == nullptr) return __cache; - return static_cast<__node_pointer>(_VSTD::__tree_leaf(__cache->__left_)); + return static_cast<__node_pointer>(std::__tree_leaf(__cache->__left_)); } template __tree<_Tp, _Compare, _Allocator>& __tree<_Tp, _Compare, _Allocator>::operator=(const __tree& __t) { - if (this != _VSTD::addressof(__t)) + if (this != std::addressof(__t)) { value_comp() = __t.value_comp(); __copy_assign_alloc(__t); @@ -1693,9 +1693,9 @@ __tree<_Tp, _Compare, _Allocator>::__tree(__tree&& __t) _NOEXCEPT_( is_nothrow_move_constructible<__node_allocator>::value && is_nothrow_move_constructible::value) - : __begin_node_(_VSTD::move(__t.__begin_node_)), - __pair1_(_VSTD::move(__t.__pair1_)), - __pair3_(_VSTD::move(__t.__pair3_)) + : __begin_node_(std::move(__t.__begin_node_)), + __pair1_(std::move(__t.__pair1_)), + __pair3_(std::move(__t.__pair3_)) { if (size() == 0) __begin_node() = __end_node(); @@ -1711,7 +1711,7 @@ __tree<_Tp, _Compare, _Allocator>::__tree(__tree&& __t) template __tree<_Tp, _Compare, _Allocator>::__tree(__tree&& __t, const allocator_type& __a) : __pair1_(__default_init_tag(), __node_allocator(__a)), - __pair3_(0, _VSTD::move(__t.value_comp())) + __pair3_(0, std::move(__t.value_comp())) { if (__a == __t.__alloc()) { @@ -1744,7 +1744,7 @@ __tree<_Tp, _Compare, _Allocator>::__move_assign(__tree& __t, true_type) __begin_node_ = __t.__begin_node_; __pair1_.first() = __t.__pair1_.first(); __move_assign_alloc(__t); - __pair3_ = _VSTD::move(__t.__pair3_); + __pair3_ = std::move(__t.__pair3_); if (size() == 0) __begin_node() = __end_node(); else @@ -1764,13 +1764,13 @@ __tree<_Tp, _Compare, _Allocator>::__move_assign(__tree& __t, false_type) __move_assign(__t, true_type()); else { - value_comp() = _VSTD::move(__t.value_comp()); + value_comp() = std::move(__t.value_comp()); const_iterator __e = end(); if (size() != 0) { _DetachedTreeCache __cache(this); while (__cache.__get() != nullptr && __t.size() != 0) { - __cache.__get()->__value_ = _VSTD::move(__t.remove(__t.begin())->__value_); + __cache.__get()->__value_ = std::move(__t.remove(__t.begin())->__value_); __node_insert_multi(__cache.__get()); __cache.__advance(); } @@ -1829,10 +1829,10 @@ __tree<_Tp, _Compare, _Allocator>::swap(__tree& __t) _NOEXCEPT_(__is_nothrow_swappable::value) #endif { - using _VSTD::swap; + using std::swap; swap(__begin_node_, __t.__begin_node_); swap(__pair1_.first(), __t.__pair1_.first()); - _VSTD::__swap_allocator(__node_alloc(), __t.__node_alloc()); + std::__swap_allocator(__node_alloc(), __t.__node_alloc()); __pair3_.swap(__t.__pair3_); if (size() == 0) __begin_node() = __end_node(); @@ -1988,7 +1988,7 @@ __tree<_Tp, _Compare, _Allocator>::__find_equal(__parent_pointer& __parent, if (value_comp()(__v, __nd->__value_)) { if (__nd->__left_ != nullptr) { - __nd_ptr = _VSTD::addressof(__nd->__left_); + __nd_ptr = std::addressof(__nd->__left_); __nd = static_cast<__node_pointer>(__nd->__left_); } else { __parent = static_cast<__parent_pointer>(__nd); @@ -1998,7 +1998,7 @@ __tree<_Tp, _Compare, _Allocator>::__find_equal(__parent_pointer& __parent, else if (value_comp()(__nd->__value_, __v)) { if (__nd->__right_ != nullptr) { - __nd_ptr = _VSTD::addressof(__nd->__right_); + __nd_ptr = std::addressof(__nd->__right_); __nd = static_cast<__node_pointer>(__nd->__right_); } else { __parent = static_cast<__parent_pointer>(__nd); @@ -2055,10 +2055,10 @@ __tree<_Tp, _Compare, _Allocator>::__find_equal(const_iterator __hint, else if (value_comp()(*__hint, __v)) // check after { // *__hint < __v - const_iterator __next = _VSTD::next(__hint); + const_iterator __next = std::next(__hint); if (__next == end() || value_comp()(__v, *__next)) { - // *__hint < __v < *_VSTD::next(__hint) + // *__hint < __v < *std::next(__hint) if (__hint.__get_np()->__right_ == nullptr) { __parent = static_cast<__parent_pointer>(__hint.__ptr_); @@ -2091,7 +2091,7 @@ void __tree<_Tp, _Compare, _Allocator>::__insert_node_at( __child = __new_node; if (__begin_node()->__left_ != nullptr) __begin_node() = static_cast<__iter_pointer>(__begin_node()->__left_); - _VSTD::__tree_balance_after_insert(__end_node()->__left_, __child); + std::__tree_balance_after_insert(__end_node()->__left_, __child); ++size(); } @@ -2106,7 +2106,7 @@ __tree<_Tp, _Compare, _Allocator>::__emplace_unique_key_args(_Key const& __k, _A bool __inserted = false; if (__child == nullptr) { - __node_holder __h = __construct_node(_VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node(std::forward<_Args>(__args)...); __insert_node_at(__parent, __child, static_cast<__node_base_pointer>(__h.get())); __r = __h.release(); __inserted = true; @@ -2127,7 +2127,7 @@ __tree<_Tp, _Compare, _Allocator>::__emplace_hint_unique_key_args( bool __inserted = false; if (__child == nullptr) { - __node_holder __h = __construct_node(_VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node(std::forward<_Args>(__args)...); __insert_node_at(__parent, __child, static_cast<__node_base_pointer>(__h.get())); __r = __h.release(); __inserted = true; @@ -2144,7 +2144,7 @@ __tree<_Tp, _Compare, _Allocator>::__construct_node(_Args&& ...__args) "Cannot construct from __value_type"); __node_allocator& __na = __node_alloc(); __node_holder __h(__node_traits::allocate(__na, 1), _Dp(__na)); - __node_traits::construct(__na, _NodeTypes::__get_ptr(__h->__value_), _VSTD::forward<_Args>(__args)...); + __node_traits::construct(__na, _NodeTypes::__get_ptr(__h->__value_), std::forward<_Args>(__args)...); __h.get_deleter().__value_constructed = true; return __h; } @@ -2155,7 +2155,7 @@ template pair::iterator, bool> __tree<_Tp, _Compare, _Allocator>::__emplace_unique_impl(_Args&&... __args) { - __node_holder __h = __construct_node(_VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node(std::forward<_Args>(__args)...); __parent_pointer __parent; __node_base_pointer& __child = __find_equal(__parent, __h->__value_); __node_pointer __r = static_cast<__node_pointer>(__child); @@ -2174,7 +2174,7 @@ template typename __tree<_Tp, _Compare, _Allocator>::iterator __tree<_Tp, _Compare, _Allocator>::__emplace_hint_unique_impl(const_iterator __p, _Args&&... __args) { - __node_holder __h = __construct_node(_VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node(std::forward<_Args>(__args)...); __parent_pointer __parent; __node_base_pointer __dummy; __node_base_pointer& __child = __find_equal(__p, __parent, __dummy, __h->__value_); @@ -2192,7 +2192,7 @@ template typename __tree<_Tp, _Compare, _Allocator>::iterator __tree<_Tp, _Compare, _Allocator>::__emplace_multi(_Args&&... __args) { - __node_holder __h = __construct_node(_VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node(std::forward<_Args>(__args)...); __parent_pointer __parent; __node_base_pointer& __child = __find_leaf_high(__parent, _NodeTypes::__get_key(__h->__value_)); __insert_node_at(__parent, __child, static_cast<__node_base_pointer>(__h.get())); @@ -2205,7 +2205,7 @@ typename __tree<_Tp, _Compare, _Allocator>::iterator __tree<_Tp, _Compare, _Allocator>::__emplace_hint_multi(const_iterator __p, _Args&&... __args) { - __node_holder __h = __construct_node(_VSTD::forward<_Args>(__args)...); + __node_holder __h = __construct_node(std::forward<_Args>(__args)...); __parent_pointer __parent; __node_base_pointer& __child = __find_leaf(__p, __parent, _NodeTypes::__get_key(__h->__value_)); __insert_node_at(__parent, __child, static_cast<__node_base_pointer>(__h.get())); @@ -2261,7 +2261,7 @@ __tree<_Tp, _Compare, _Allocator>::__remove_node_pointer(__node_pointer __ptr) _ if (__begin_node() == __ptr) __begin_node() = __r.__ptr_; --size(); - _VSTD::__tree_remove(__end_node()->__left_, + std::__tree_remove(__end_node()->__left_, static_cast<__node_base_pointer>(__ptr)); return __r; } @@ -2284,7 +2284,7 @@ __tree<_Tp, _Compare, _Allocator>::__node_handle_insert_unique( if (__child != nullptr) return _InsertReturnType{ iterator(static_cast<__node_pointer>(__child)), - false, _VSTD::move(__nh)}; + false, std::move(__nh)}; __insert_node_at(__parent, __child, static_cast<__node_base_pointer>(__ptr)); @@ -2530,7 +2530,7 @@ __tree<_Tp, _Compare, _Allocator>::__count_multi(const _Key& __k) const else if (value_comp()(__rt->__value_, __k)) __rt = static_cast<__node_pointer>(__rt->__right_); else - return _VSTD::distance( + return std::distance( __lower_bound(__k, static_cast<__node_pointer>(__rt->__left_), static_cast<__iter_pointer>(__rt)), __upper_bound(__k, static_cast<__node_pointer>(__rt->__right_), __result) ); @@ -2640,7 +2640,7 @@ __tree<_Tp, _Compare, _Allocator>::__equal_range_unique(const _Key& __k) return _Pp(iterator(__rt), iterator( __rt->__right_ != nullptr ? - static_cast<__iter_pointer>(_VSTD::__tree_min(__rt->__right_)) + static_cast<__iter_pointer>(std::__tree_min(__rt->__right_)) : __result)); } return _Pp(iterator(__result), iterator(__result)); @@ -2668,7 +2668,7 @@ __tree<_Tp, _Compare, _Allocator>::__equal_range_unique(const _Key& __k) const return _Pp(const_iterator(__rt), const_iterator( __rt->__right_ != nullptr ? - static_cast<__iter_pointer>(_VSTD::__tree_min(__rt->__right_)) + static_cast<__iter_pointer>(std::__tree_min(__rt->__right_)) : __result)); } return _Pp(const_iterator(__result), const_iterator(__result)); @@ -2737,7 +2737,7 @@ __tree<_Tp, _Compare, _Allocator>::remove(const_iterator __p) _NOEXCEPT __begin_node() = static_cast<__iter_pointer>(__np->__parent_); } --size(); - _VSTD::__tree_remove(__end_node()->__left_, + std::__tree_remove(__end_node()->__left_, static_cast<__node_base_pointer>(__np)); return __node_holder(__np, _Dp(__node_alloc(), true)); } diff --git a/libcxx/include/__type_traits/invoke.h b/libcxx/include/__type_traits/invoke.h index bd2fb5dbf2c1..c0487e25a0d8 100644 --- a/libcxx/include/__type_traits/invoke.h +++ b/libcxx/include/__type_traits/invoke.h @@ -380,7 +380,7 @@ struct __nothrow_invokable_r_imp { static const bool value = false; #else static const bool value = - noexcept(_ThisT::__test_noexcept<_Ret>(_VSTD::__invoke(std::declval<_Fp>(), std::declval<_Args>()...))); + noexcept(_ThisT::__test_noexcept<_Ret>(std::__invoke(std::declval<_Fp>(), std::declval<_Args>()...))); #endif }; @@ -389,7 +389,7 @@ struct __nothrow_invokable_r_imp { #ifdef _LIBCPP_CXX03_LANG static const bool value = false; #else - static const bool value = noexcept(_VSTD::__invoke(std::declval<_Fp>(), std::declval<_Args>()...)); + static const bool value = noexcept(std::__invoke(std::declval<_Fp>(), std::declval<_Args>()...)); #endif }; diff --git a/libcxx/include/__type_traits/is_nothrow_constructible.h b/libcxx/include/__type_traits/is_nothrow_constructible.h index 4949062433b7..f56816b943c4 100644 --- a/libcxx/include/__type_traits/is_nothrow_constructible.h +++ b/libcxx/include/__type_traits/is_nothrow_constructible.h @@ -42,7 +42,7 @@ void __implicit_conversion_to(_Tp) noexcept {} template struct __libcpp_is_nothrow_constructible - : public integral_constant(std::declval<_Arg>()))> {}; + : public integral_constant(std::declval<_Arg>()))> {}; template struct __libcpp_is_nothrow_constructible : public false_type { diff --git a/libcxx/include/__type_traits/is_nothrow_convertible.h b/libcxx/include/__type_traits/is_nothrow_convertible.h index a8f8b4d063a1..eda7a49d7224 100644 --- a/libcxx/include/__type_traits/is_nothrow_convertible.h +++ b/libcxx/include/__type_traits/is_nothrow_convertible.h @@ -30,7 +30,7 @@ template void __test_noexcept(_Tp) noexcept; template -bool_constant(std::declval<_Fm>()))> __is_nothrow_convertible_test(); +bool_constant(std::declval<_Fm>()))> __is_nothrow_convertible_test(); template struct __is_nothrow_convertible_helper : decltype(__is_nothrow_convertible_test<_Fm, _To>()) {}; diff --git a/libcxx/include/__utility/cmp.h b/libcxx/include/__utility/cmp.h index b20c80b35cc4..5c62d2bfa073 100644 --- a/libcxx/include/__utility/cmp.h +++ b/libcxx/include/__utility/cmp.h @@ -59,7 +59,7 @@ template<__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_not_equal(_Tp __t, _Up __u) noexcept { - return !_VSTD::cmp_equal(__t, __u); + return !std::cmp_equal(__t, __u); } template<__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> @@ -78,29 +78,29 @@ template<__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_greater(_Tp __t, _Up __u) noexcept { - return _VSTD::cmp_less(__u, __t); + return std::cmp_less(__u, __t); } template<__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_less_equal(_Tp __t, _Up __u) noexcept { - return !_VSTD::cmp_greater(__t, __u); + return !std::cmp_greater(__t, __u); } template<__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_greater_equal(_Tp __t, _Up __u) noexcept { - return !_VSTD::cmp_less(__t, __u); + return !std::cmp_less(__t, __u); } template<__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool in_range(_Up __u) noexcept { - return _VSTD::cmp_less_equal(__u, numeric_limits<_Tp>::max()) && - _VSTD::cmp_greater_equal(__u, numeric_limits<_Tp>::min()); + return std::cmp_less_equal(__u, numeric_limits<_Tp>::max()) && + std::cmp_greater_equal(__u, numeric_limits<_Tp>::min()); } #endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__utility/exchange.h b/libcxx/include/__utility/exchange.h index dd0989c41113..819549a9dcb4 100644 --- a/libcxx/include/__utility/exchange.h +++ b/libcxx/include/__utility/exchange.h @@ -30,8 +30,8 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _T1 exchange(_T1& __obj, _T2&& __new_value) noexcept(is_nothrow_move_constructible<_T1>::value && is_nothrow_assignable<_T1&, _T2>::value) { - _T1 __old_value = _VSTD::move(__obj); - __obj = _VSTD::forward<_T2>(__new_value); + _T1 __old_value = std::move(__obj); + __obj = std::forward<_T2>(__new_value); return __old_value; } #endif // _LIBCPP_STD_VER >= 14 diff --git a/libcxx/include/__utility/integer_sequence.h b/libcxx/include/__utility/integer_sequence.h index 2b70337a29a1..bae8c241ef5a 100644 --- a/libcxx/include/__utility/integer_sequence.h +++ b/libcxx/include/__utility/integer_sequence.h @@ -51,6 +51,7 @@ template struct __repeat<__integer_s template struct __parity; template struct __make : __parity<_Np % 8>::template __pmake<_Np> {}; +// clang-format off template<> struct __make<0> { typedef __integer_sequence type; }; template<> struct __make<1> { typedef __integer_sequence type; }; template<> struct __make<2> { typedef __integer_sequence type; }; @@ -68,6 +69,7 @@ template<> struct __parity<4> { template struct __pmake : __repeat struct __parity<5> { template struct __pmake : __repeat::type, _Np - 5, _Np - 4, _Np - 3, _Np - 2, _Np - 1> {}; }; template<> struct __parity<6> { template struct __pmake : __repeat::type, _Np - 6, _Np - 5, _Np - 4, _Np - 3, _Np - 2, _Np - 1> {}; }; template<> struct __parity<7> { template struct __pmake : __repeat::type, _Np - 7, _Np - 6, _Np - 5, _Np - 4, _Np - 3, _Np - 2, _Np - 1> {}; }; +// clang-format on } // namespace detail diff --git a/libcxx/include/__utility/swap.h b/libcxx/include/__utility/swap.h index 09a6693a0102..ca8280c729df 100644 --- a/libcxx/include/__utility/swap.h +++ b/libcxx/include/__utility/swap.h @@ -39,9 +39,9 @@ using __swap_result_t = void; template inline _LIBCPP_HIDE_FROM_ABI __swap_result_t<_Tp> _LIBCPP_CONSTEXPR_SINCE_CXX20 swap(_Tp& __x, _Tp& __y) _NOEXCEPT_(is_nothrow_move_constructible<_Tp>::value&& is_nothrow_move_assignable<_Tp>::value) { - _Tp __t(_VSTD::move(__x)); - __x = _VSTD::move(__y); - __y = _VSTD::move(__t); + _Tp __t(std::move(__x)); + __x = std::move(__y); + __y = std::move(__t); } template ::value, int> > diff --git a/libcxx/include/__utility/to_underlying.h b/libcxx/include/__utility/to_underlying.h index f8d9f39cb2f8..114e088c1692 100644 --- a/libcxx/include/__utility/to_underlying.h +++ b/libcxx/include/__utility/to_underlying.h @@ -31,7 +31,7 @@ __to_underlying(_Tp __val) noexcept { template _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI constexpr underlying_type_t<_Tp> to_underlying(_Tp __val) noexcept { - return _VSTD::__to_underlying(__val); + return std::__to_underlying(__val); } #endif diff --git a/libcxx/include/any b/libcxx/include/any index 5e558a0510fe..516fd6ddb23c 100644 --- a/libcxx/include/any +++ b/libcxx/include/any @@ -266,7 +266,7 @@ public: _LIBCPP_HIDE_FROM_ABI any & operator=(any && __rhs) _NOEXCEPT { - any(_VSTD::move(__rhs)).swap(*this); + any(std::move(__rhs)).swap(*this); return *this; } @@ -399,7 +399,7 @@ namespace __any_imp typedef allocator_traits<_Alloc> _ATraits; _Alloc __a; _Tp * __ret = static_cast<_Tp*>(static_cast(&__dest.__s_.__buf)); - _ATraits::construct(__a, __ret, _VSTD::forward<_Args>(__args)...); + _ATraits::construct(__a, __ret, std::forward<_Args>(__args)...); __dest.__h_ = &_SmallHandler::__handle; return *__ret; } @@ -423,7 +423,7 @@ namespace __any_imp _LIBCPP_HIDE_FROM_ABI static void __move(any & __this, any & __dest) { - _SmallHandler::__create(__dest, _VSTD::move( + _SmallHandler::__create(__dest, std::move( *static_cast<_Tp*>(static_cast(&__this.__s_.__buf)))); __destroy(__this); } @@ -485,7 +485,7 @@ namespace __any_imp _Alloc __a; unique_ptr<_Tp, _Dp> __hold(_ATraits::allocate(__a, 1), _Dp(__a, 1)); _Tp * __ret = __hold.get(); - _ATraits::construct(__a, __ret, _VSTD::forward<_Args>(__args)...); + _ATraits::construct(__a, __ret, std::forward<_Args>(__args)...); __dest.__s_.__ptr = __hold.release(); __dest.__h_ = &_LargeHandler::__handle; return *__ret; @@ -543,24 +543,24 @@ namespace __any_imp template any::any(_ValueType && __v) : __h_(nullptr) { - __any_imp::_Handler<_Tp>::__create(*this, _VSTD::forward<_ValueType>(__v)); + __any_imp::_Handler<_Tp>::__create(*this, std::forward<_ValueType>(__v)); } template any::any(in_place_type_t<_ValueType>, _Args&&... __args) { - __any_imp::_Handler<_Tp>::__create(*this, _VSTD::forward<_Args>(__args)...); + __any_imp::_Handler<_Tp>::__create(*this, std::forward<_Args>(__args)...); } template any::any(in_place_type_t<_ValueType>, initializer_list<_Up> __il, _Args&&... __args) { - __any_imp::_Handler<_Tp>::__create(*this, __il, _VSTD::forward<_Args>(__args)...); + __any_imp::_Handler<_Tp>::__create(*this, __il, std::forward<_Args>(__args)...); } template inline _LIBCPP_HIDE_FROM_ABI any & any::operator=(_ValueType && __v) { - any(_VSTD::forward<_ValueType>(__v)).swap(*this); + any(std::forward<_ValueType>(__v)).swap(*this); return *this; } @@ -568,14 +568,14 @@ template inline _LIBCPP_HIDE_FROM_ABI _Tp& any::emplace(_Args&&... __args) { reset(); - return __any_imp::_Handler<_Tp>::__create(*this, _VSTD::forward<_Args>(__args)...); + return __any_imp::_Handler<_Tp>::__create(*this, std::forward<_Args>(__args)...); } template inline _LIBCPP_HIDE_FROM_ABI _Tp& any::emplace(initializer_list<_Up> __il, _Args&&... __args) { reset(); - return __any_imp::_Handler<_Tp>::__create(*this, __il, _VSTD::forward<_Args>(__args)...); + return __any_imp::_Handler<_Tp>::__create(*this, __il, std::forward<_Args>(__args)...); } inline _LIBCPP_HIDE_FROM_ABI @@ -608,13 +608,13 @@ void swap(any & __lhs, any & __rhs) _NOEXCEPT template inline _LIBCPP_HIDE_FROM_ABI any make_any(_Args&&... __args) { - return any(in_place_type<_Tp>, _VSTD::forward<_Args>(__args)...); + return any(in_place_type<_Tp>, std::forward<_Args>(__args)...); } template inline _LIBCPP_HIDE_FROM_ABI any make_any(initializer_list<_Up> __il, _Args&&... __args) { - return any(in_place_type<_Tp>, __il, _VSTD::forward<_Args>(__args)...); + return any(in_place_type<_Tp>, __il, std::forward<_Args>(__args)...); } template @@ -626,7 +626,7 @@ _ValueType any_cast(any const & __v) static_assert(is_constructible<_ValueType, _RawValueType const &>::value, "ValueType is required to be a const lvalue reference " "or a CopyConstructible type"); - auto __tmp = _VSTD::any_cast>(&__v); + auto __tmp = std::any_cast>(&__v); if (__tmp == nullptr) __throw_bad_any_cast(); return static_cast<_ValueType>(*__tmp); @@ -641,7 +641,7 @@ _ValueType any_cast(any & __v) static_assert(is_constructible<_ValueType, _RawValueType &>::value, "ValueType is required to be an lvalue reference " "or a CopyConstructible type"); - auto __tmp = _VSTD::any_cast<_RawValueType>(&__v); + auto __tmp = std::any_cast<_RawValueType>(&__v); if (__tmp == nullptr) __throw_bad_any_cast(); return static_cast<_ValueType>(*__tmp); @@ -656,10 +656,10 @@ _ValueType any_cast(any && __v) static_assert(is_constructible<_ValueType, _RawValueType>::value, "ValueType is required to be an rvalue reference " "or a CopyConstructible type"); - auto __tmp = _VSTD::any_cast<_RawValueType>(&__v); + auto __tmp = std::any_cast<_RawValueType>(&__v); if (__tmp == nullptr) __throw_bad_any_cast(); - return static_cast<_ValueType>(_VSTD::move(*__tmp)); + return static_cast<_ValueType>(std::move(*__tmp)); } template @@ -669,7 +669,7 @@ any_cast(any const * __any) _NOEXCEPT { static_assert(!is_reference<_ValueType>::value, "_ValueType may not be a reference."); - return _VSTD::any_cast<_ValueType>(const_cast(__any)); + return std::any_cast<_ValueType>(const_cast(__any)); } template @@ -701,7 +701,7 @@ any_cast(any * __any) _NOEXCEPT nullptr, #endif __any_imp::__get_fallback_typeid<_ValueType>()); - return _VSTD::__pointer_or_func_cast<_ReturnType>( + return std::__pointer_or_func_cast<_ReturnType>( __p, is_function<_ValueType>{}); } return nullptr; diff --git a/libcxx/include/array b/libcxx/include/array index fc5371ebae21..127092f6bca9 100644 --- a/libcxx/include/array +++ b/libcxx/include/array @@ -164,30 +164,30 @@ template struct _LIBCPP_TEMPLATE_VIS array { // types: - typedef array __self; - typedef _Tp value_type; - typedef value_type& reference; - typedef const value_type& const_reference; - typedef value_type* iterator; - typedef const value_type* const_iterator; - typedef value_type* pointer; - typedef const value_type* const_pointer; - typedef size_t size_type; - typedef ptrdiff_t difference_type; - typedef _VSTD::reverse_iterator reverse_iterator; - typedef _VSTD::reverse_iterator const_reverse_iterator; + using __self = array; + using value_type = _Tp; + using reference = value_type&; + using const_reference = const value_type&; + using iterator = value_type*; + using const_iterator = const value_type*; + using pointer = value_type*; + using const_pointer = const value_type*; + using size_type = size_t; + using difference_type = ptrdiff_t; + using reverse_iterator = std::reverse_iterator; + using const_reverse_iterator = std::reverse_iterator; _Tp __elems_[_Size]; // No explicit construct/copy/destroy for aggregate type _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void fill(const value_type& __u) { - _VSTD::fill_n(data(), _Size, __u); + std::fill_n(data(), _Size, __u); } _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void swap(array& __a) _NOEXCEPT_(__is_nothrow_swappable<_Tp>::value) { - _VSTD::swap_ranges(data(), data() + _Size, __a.data()); + std::swap_ranges(data(), data() + _Size, __a.data()); } // iterators: @@ -277,8 +277,8 @@ struct _LIBCPP_TEMPLATE_VIS array<_Tp, 0> typedef const value_type* const_pointer; typedef size_t size_type; typedef ptrdiff_t difference_type; - typedef _VSTD::reverse_iterator reverse_iterator; - typedef _VSTD::reverse_iterator const_reverse_iterator; + typedef std::reverse_iterator reverse_iterator; + typedef std::reverse_iterator const_reverse_iterator; typedef __conditional_t::value, const char, char> _CharType; @@ -403,7 +403,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 bool operator==(const array<_Tp, _Size>& __x, const array<_Tp, _Size>& __y) { - return _VSTD::equal(__x.begin(), __x.end(), __y.begin()); + return std::equal(__x.begin(), __x.end(), __y.begin()); } #if _LIBCPP_STD_VER <= 17 @@ -415,7 +415,7 @@ inline _LIBCPP_HIDE_FROM_ABI bool operator!=(const array<_Tp, _Size>& __x, const template inline _LIBCPP_HIDE_FROM_ABI bool operator<(const array<_Tp, _Size>& __x, const array<_Tp, _Size>& __y) { - return _VSTD::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); + return std::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); } template @@ -488,7 +488,7 @@ _Tp&& get(array<_Tp, _Size>&& __a) _NOEXCEPT { static_assert(_Ip < _Size, "Index out of bounds in std::get<> (std::array &&)"); - return _VSTD::move(__a.__elems_[_Ip]); + return std::move(__a.__elems_[_Ip]); } template @@ -497,7 +497,7 @@ const _Tp&& get(const array<_Tp, _Size>&& __a) _NOEXCEPT { static_assert(_Ip < _Size, "Index out of bounds in std::get<> (const std::array &&)"); - return _VSTD::move(__a.__elems_[_Ip]); + return std::move(__a.__elems_[_Ip]); } #if _LIBCPP_STD_VER >= 20 @@ -511,7 +511,7 @@ __to_array_lvalue_impl(_Tp (&__arr)[_Size], index_sequence<_Index...>) { template _LIBCPP_HIDE_FROM_ABI constexpr array, _Size> __to_array_rvalue_impl(_Tp(&&__arr)[_Size], index_sequence<_Index...>) { - return {{_VSTD::move(__arr[_Index])...}}; + return {{std::move(__arr[_Index])...}}; } template @@ -523,7 +523,7 @@ to_array(_Tp (&__arr)[_Size]) noexcept(is_nothrow_constructible_v<_Tp, _Tp&>) { static_assert( is_constructible_v<_Tp, _Tp&>, "[array.creation]/1: to_array requires copy constructible elements."); - return _VSTD::__to_array_lvalue_impl(__arr, make_index_sequence<_Size>()); + return std::__to_array_lvalue_impl(__arr, make_index_sequence<_Size>()); } template @@ -535,7 +535,7 @@ to_array(_Tp(&&__arr)[_Size]) noexcept(is_nothrow_move_constructible_v<_Tp>) { static_assert( is_move_constructible_v<_Tp>, "[array.creation]/4: to_array requires move constructible elements."); - return _VSTD::__to_array_rvalue_impl(_VSTD::move(__arr), + return std::__to_array_rvalue_impl(std::move(__arr), make_index_sequence<_Size>()); } diff --git a/libcxx/include/barrier b/libcxx/include/barrier index 9ba3abbe1856..dff650b75d1f 100644 --- a/libcxx/include/barrier +++ b/libcxx/include/barrier @@ -310,7 +310,7 @@ public: _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI explicit barrier(ptrdiff_t __count, _CompletionF __completion = _CompletionF()) - : __b_(__count, _VSTD::move(__completion)) { + : __b_(__count, std::move(__completion)) { _LIBCPP_ASSERT_UNCATEGORIZED( __count >= 0, "barrier::barrier(ptrdiff_t, CompletionFunction): barrier cannot be initialized with a negative value"); @@ -332,7 +332,7 @@ public: _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI void wait(arrival_token&& __phase) const { - __b_.wait(_VSTD::move(__phase)); + __b_.wait(std::move(__phase)); } _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI void arrive_and_wait() diff --git a/libcxx/include/bitset b/libcxx/include/bitset index 224cda770f35..d33015dc6b87 100644 --- a/libcxx/include/bitset +++ b/libcxx/include/bitset @@ -10,6 +10,8 @@ #ifndef _LIBCPP_BITSET #define _LIBCPP_BITSET +// clang-format off + /* bitset synopsis @@ -122,6 +124,8 @@ template struct hash>; */ +// clang-format on + #include <__algorithm/count.h> #include <__algorithm/fill.h> #include <__algorithm/find.h> @@ -248,7 +252,7 @@ __bitset<_N_words, _Size>::__bitset() _NOEXCEPT #endif { #ifdef _LIBCPP_CXX03_LANG - _VSTD::fill_n(__first_, _N_words, __storage_type(0)); + std::fill_n(__first_, _N_words, __storage_type(0)); #endif } @@ -266,8 +270,8 @@ __bitset<_N_words, _Size>::__init(unsigned long long __v, false_type) _NOEXCEPT else __t[__i] = static_cast<__storage_type>(__v); - _VSTD::copy(__t, __t + sizeof(__t)/sizeof(__t[0]), __first_); - _VSTD::fill(__first_ + sizeof(__t)/sizeof(__t[0]), __first_ + sizeof(__first_)/sizeof(__first_[0]), + std::copy(__t, __t + sizeof(__t)/sizeof(__t[0]), __first_); + std::fill(__first_ + sizeof(__t)/sizeof(__t[0]), __first_ + sizeof(__first_)/sizeof(__first_[0]), __storage_type(0)); } @@ -280,7 +284,7 @@ __bitset<_N_words, _Size>::__init(unsigned long long __v, true_type) _NOEXCEPT if (_Size < __bits_per_word) __first_[0] &= ( 1ULL << _Size ) - 1; - _VSTD::fill(__first_ + 1, __first_ + sizeof(__first_)/sizeof(__first_[0]), __storage_type(0)); + std::fill(__first_ + 1, __first_ + sizeof(__first_)/sizeof(__first_[0]), __storage_type(0)); } #endif // _LIBCPP_CXX03_LANG @@ -357,7 +361,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unsigned long __bitset<_N_words, _Size>::to_ulong(false_type) const { const_iterator __e = __make_iter(_Size); - const_iterator __i = _VSTD::find(__make_iter(sizeof(unsigned long) * CHAR_BIT), __e, true); + const_iterator __i = std::find(__make_iter(sizeof(unsigned long) * CHAR_BIT), __e, true); if (__i != __e) __throw_overflow_error("bitset to_ulong overflow error"); @@ -377,7 +381,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 unsigned long long __bitset<_N_words, _Size>::to_ullong(false_type) const { const_iterator __e = __make_iter(_Size); - const_iterator __i = _VSTD::find(__make_iter(sizeof(unsigned long long) * CHAR_BIT), __e, true); + const_iterator __i = std::find(__make_iter(sizeof(unsigned long long) * CHAR_BIT), __e, true); if (__i != __e) __throw_overflow_error("bitset to_ullong overflow error"); @@ -880,9 +884,9 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 bitset<_Size>& bitset<_Size>::operator<<=(size_t __pos) _NOEXCEPT { - __pos = _VSTD::min(__pos, _Size); - _VSTD::copy_backward(base::__make_iter(0), base::__make_iter(_Size - __pos), base::__make_iter(_Size)); - _VSTD::fill_n(base::__make_iter(0), __pos, false); + __pos = std::min(__pos, _Size); + std::copy_backward(base::__make_iter(0), base::__make_iter(_Size - __pos), base::__make_iter(_Size)); + std::fill_n(base::__make_iter(0), __pos, false); return *this; } @@ -891,9 +895,9 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 bitset<_Size>& bitset<_Size>::operator>>=(size_t __pos) _NOEXCEPT { - __pos = _VSTD::min(__pos, _Size); - _VSTD::copy(base::__make_iter(__pos), base::__make_iter(_Size), base::__make_iter(0)); - _VSTD::fill_n(base::__make_iter(_Size - __pos), __pos, false); + __pos = std::min(__pos, _Size); + std::copy(base::__make_iter(__pos), base::__make_iter(_Size), base::__make_iter(0)); + std::fill_n(base::__make_iter(_Size - __pos), __pos, false); return *this; } @@ -903,7 +907,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 bitset<_Size>& bitset<_Size>::set() _NOEXCEPT { - _VSTD::fill_n(base::__make_iter(0), _Size, true); + std::fill_n(base::__make_iter(0), _Size, true); return *this; } @@ -925,7 +929,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 bitset<_Size>& bitset<_Size>::reset() _NOEXCEPT { - _VSTD::fill_n(base::__make_iter(0), _Size, false); + std::fill_n(base::__make_iter(0), _Size, false); return *this; } @@ -1052,7 +1056,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX23 bool bitset<_Size>::operator==(const bitset& __rhs) const _NOEXCEPT { - return _VSTD::equal(base::__make_iter(0), base::__make_iter(_Size), __rhs.__make_iter(0)); + return std::equal(base::__make_iter(0), base::__make_iter(_Size), __rhs.__make_iter(0)); } #if _LIBCPP_STD_VER <= 17 diff --git a/libcxx/include/chrono b/libcxx/include/chrono index becf95c0d03e..b3ed9acc5e5d 100644 --- a/libcxx/include/chrono +++ b/libcxx/include/chrono @@ -10,6 +10,8 @@ #ifndef _LIBCPP_CHRONO #define _LIBCPP_CHRONO +// clang-format off + /* chrono synopsis @@ -796,6 +798,8 @@ constexpr chrono::year operator ""y(unsigned lo } // std */ +// clang-format on + #include <__assert> // all public C++ headers provide the assertion handler #include <__chrono/calendar.h> #include <__chrono/convert_to_timespec.h> diff --git a/libcxx/include/complex b/libcxx/include/complex index 0a2bc27eaa2a..7017f25e6c5e 100644 --- a/libcxx/include/complex +++ b/libcxx/include/complex @@ -1150,7 +1150,7 @@ complex::type> pow(const complex<_Tp>& __x, const complex<_Up>& __y) { typedef complex::type> result_type; - return _VSTD::pow(result_type(__x), result_type(__y)); + return std::pow(result_type(__x), result_type(__y)); } template::value, int> = 0> @@ -1159,7 +1159,7 @@ complex::type> pow(const complex<_Tp>& __x, const _Up& __y) { typedef complex::type> result_type; - return _VSTD::pow(result_type(__x), result_type(__y)); + return std::pow(result_type(__x), result_type(__y)); } template::value, int> = 0> @@ -1168,7 +1168,7 @@ complex::type> pow(const _Tp& __x, const complex<_Up>& __y) { typedef complex::type> result_type; - return _VSTD::pow(result_type(__x), result_type(__y)); + return std::pow(result_type(__x), result_type(__y)); } // __sqr, computes pow(x, 2) diff --git a/libcxx/include/condition_variable b/libcxx/include/condition_variable index 38a5eeb3dba4..4109ee52c125 100644 --- a/libcxx/include/condition_variable +++ b/libcxx/include/condition_variable @@ -295,7 +295,7 @@ condition_variable_any::wait_for(_Lock& __lock, _Predicate __pred) { return wait_until(__lock, chrono::steady_clock::now() + __d, - _VSTD::move(__pred)); + std::move(__pred)); } #if _LIBCPP_STD_VER >= 20 && !defined(_LIBCPP_HAS_NO_EXPERIMENTAL_STOP_TOKEN) diff --git a/libcxx/include/deque b/libcxx/include/deque index 1438f1e992e2..b5d094dc415d 100644 --- a/libcxx/include/deque +++ b/libcxx/include/deque @@ -750,7 +750,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type max_size() const _NOEXCEPT - {return _VSTD::min( + {return std::min( __alloc_traits::max_size(__alloc()), numeric_limits::max());} _LIBCPP_HIDE_FROM_ABI void resize(size_type __n); @@ -894,7 +894,7 @@ public: void __move_assign_alloc(deque& __c, true_type) _NOEXCEPT_(is_nothrow_move_assignable::value) { - __alloc() = _VSTD::move(__c.__alloc()); + __alloc() = std::move(__c.__alloc()); } _LIBCPP_HIDE_FROM_ABI @@ -906,7 +906,7 @@ public: _NOEXCEPT_(__alloc_traits::propagate_on_container_move_assignment::value && is_nothrow_move_assignable::value) { - __map_ = _VSTD::move(__c.__map_); + __map_ = std::move(__c.__map_); __start_ = __c.__start_; __size() = __c.size(); __move_assign_alloc(__c); @@ -966,25 +966,27 @@ public: // __asan_annotate_container_with_allocator to false. // For more details, see the "Using libc++" documentation page or // the documentation for __sanitizer_annotate_contiguous_container. -#if !defined(_LIBCPP_HAS_NO_ASAN) _LIBCPP_HIDE_FROM_ABI void __annotate_double_ended_contiguous_container( - const void* __beg, - const void* __end, - const void* __old_con_beg, - const void* __old_con_end, - const void* __new_con_beg, - const void* __new_con_end) const { + [[__maybe_unused__]] const void* __beg, + [[__maybe_unused__]] const void* __end, + [[__maybe_unused__]] const void* __old_con_beg, + [[__maybe_unused__]] const void* __old_con_end, + [[__maybe_unused__]] const void* __new_con_beg, + [[__maybe_unused__]] const void* __new_con_end) const { +#ifndef _LIBCPP_HAS_NO_ASAN if (__beg != nullptr && __asan_annotate_container_with_allocator<_Allocator>::value) __sanitizer_annotate_double_ended_contiguous_container( __beg, __end, __old_con_beg, __old_con_end, __new_con_beg, __new_con_end); +#endif } -#else - _LIBCPP_HIDE_FROM_ABI void __annotate_double_ended_contiguous_container( - const void*, const void*, const void*, const void*, const void*, const void*) const _NOEXCEPT {} -#endif // !defined(_LIBCPP_HAS_NO_ASAN) _LIBCPP_HIDE_FROM_ABI - void __annotate_from_to(size_type __beg, size_type __end, __asan_annotation_type __annotation_type, __asan_annotation_place __place) const _NOEXCEPT { + void __annotate_from_to( + [[__maybe_unused__]] size_type __beg, + [[__maybe_unused__]] size_type __end, + [[__maybe_unused__]] __asan_annotation_type __annotation_type, + [[__maybe_unused__]] __asan_annotation_place __place) const _NOEXCEPT { +#ifndef _LIBCPP_HAS_NO_ASAN // __beg - index of the first item to annotate // __end - index behind the last item to annotate (so last item + 1) // __annotation_type - __asan_unposion or __asan_poison @@ -1075,6 +1077,7 @@ public: __annotate_double_ended_contiguous_container(__mem_beg, __mem_end, __old_beg, __old_end, __new_beg, __new_end); } +#endif // !_LIBCPP_HAS_NO_ASAN } _LIBCPP_HIDE_FROM_ABI @@ -1405,7 +1408,7 @@ template deque<_Tp, _Allocator>& deque<_Tp, _Allocator>::operator=(const deque& __c) { - if (this != _VSTD::addressof(__c)) + if (this != std::addressof(__c)) { __copy_assign_alloc(__c); assign(__c.begin(), __c.end()); @@ -1570,12 +1573,12 @@ deque<_Tp, _Allocator>::assign(size_type __n, const value_type& __v) { if (__n > size()) { - _VSTD::fill_n(begin(), size(), __v); + std::fill_n(begin(), size(), __v); __n -= size(); __append(__n, __v); } else - __erase_to_end(_VSTD::fill_n(begin(), __n, __v)); + __erase_to_end(std::fill_n(begin(), __n, __v)); } template @@ -1653,7 +1656,7 @@ typename deque<_Tp, _Allocator>::reference deque<_Tp, _Allocator>::at(size_type __i) { if (__i >= size()) - _VSTD::__throw_out_of_range("deque"); + std::__throw_out_of_range("deque"); size_type __p = __start_ + __i; return *(*(__map_.begin() + __p / __block_size) + __p % __block_size); } @@ -1664,7 +1667,7 @@ typename deque<_Tp, _Allocator>::const_reference deque<_Tp, _Allocator>::at(size_type __i) const { if (__i >= size()) - _VSTD::__throw_out_of_range("deque"); + std::__throw_out_of_range("deque"); size_type __p = __start_ + __i; return *(*(__map_.begin() + __p / __block_size) + __p % __block_size); } @@ -1714,7 +1717,7 @@ deque<_Tp, _Allocator>::push_back(const value_type& __v) __add_back_capacity(); // __back_spare() >= 1 __annotate_increase_back(1); - __alloc_traits::construct(__a, _VSTD::addressof(*end()), __v); + __alloc_traits::construct(__a, std::addressof(*end()), __v); ++__size(); } @@ -1727,7 +1730,7 @@ deque<_Tp, _Allocator>::push_front(const value_type& __v) __add_front_capacity(); // __front_spare() >= 1 __annotate_increase_front(1); - __alloc_traits::construct(__a, _VSTD::addressof(*--begin()), __v); + __alloc_traits::construct(__a, std::addressof(*--begin()), __v); --__start_; ++__size(); } @@ -1742,7 +1745,7 @@ deque<_Tp, _Allocator>::push_back(value_type&& __v) __add_back_capacity(); // __back_spare() >= 1 __annotate_increase_back(1); - __alloc_traits::construct(__a, _VSTD::addressof(*end()), _VSTD::move(__v)); + __alloc_traits::construct(__a, std::addressof(*end()), std::move(__v)); ++__size(); } @@ -1760,8 +1763,8 @@ deque<_Tp, _Allocator>::emplace_back(_Args&&... __args) __add_back_capacity(); // __back_spare() >= 1 __annotate_increase_back(1); - __alloc_traits::construct(__a, _VSTD::addressof(*end()), - _VSTD::forward<_Args>(__args)...); + __alloc_traits::construct(__a, std::addressof(*end()), + std::forward<_Args>(__args)...); ++__size(); #if _LIBCPP_STD_VER >= 17 return *--end(); @@ -1777,7 +1780,7 @@ deque<_Tp, _Allocator>::push_front(value_type&& __v) __add_front_capacity(); // __front_spare() >= 1 __annotate_increase_front(1); - __alloc_traits::construct(__a, _VSTD::addressof(*--begin()), _VSTD::move(__v)); + __alloc_traits::construct(__a, std::addressof(*--begin()), std::move(__v)); --__start_; ++__size(); } @@ -1797,7 +1800,7 @@ deque<_Tp, _Allocator>::emplace_front(_Args&&... __args) __add_front_capacity(); // __front_spare() >= 1 __annotate_increase_front(1); - __alloc_traits::construct(__a, _VSTD::addressof(*--begin()), _VSTD::forward<_Args>(__args)...); + __alloc_traits::construct(__a, std::addressof(*--begin()), std::forward<_Args>(__args)...); --__start_; ++__size(); #if _LIBCPP_STD_VER >= 17 @@ -1820,20 +1823,20 @@ deque<_Tp, _Allocator>::insert(const_iterator __p, value_type&& __v) __annotate_increase_front(1); if (__pos == 0) { - __alloc_traits::construct(__a, _VSTD::addressof(*--begin()), _VSTD::move(__v)); + __alloc_traits::construct(__a, std::addressof(*--begin()), std::move(__v)); --__start_; ++__size(); } else { iterator __b = begin(); - iterator __bm1 = _VSTD::prev(__b); - __alloc_traits::construct(__a, _VSTD::addressof(*__bm1), _VSTD::move(*__b)); + iterator __bm1 = std::prev(__b); + __alloc_traits::construct(__a, std::addressof(*__bm1), std::move(*__b)); --__start_; ++__size(); if (__pos > 1) - __b = _VSTD::move(_VSTD::next(__b), __b + __pos, __b); - *__b = _VSTD::move(__v); + __b = std::move(std::next(__b), __b + __pos, __b); + *__b = std::move(__v); } } else @@ -1845,18 +1848,18 @@ deque<_Tp, _Allocator>::insert(const_iterator __p, value_type&& __v) size_type __de = size() - __pos; if (__de == 0) { - __alloc_traits::construct(__a, _VSTD::addressof(*end()), _VSTD::move(__v)); + __alloc_traits::construct(__a, std::addressof(*end()), std::move(__v)); ++__size(); } else { iterator __e = end(); - iterator __em1 = _VSTD::prev(__e); - __alloc_traits::construct(__a, _VSTD::addressof(*__e), _VSTD::move(*__em1)); + iterator __em1 = std::prev(__e); + __alloc_traits::construct(__a, std::addressof(*__e), std::move(*__em1)); ++__size(); if (__de > 1) - __e = _VSTD::move_backward(__e - __de, __em1, __e); - *--__e = _VSTD::move(__v); + __e = std::move_backward(__e - __de, __em1, __e); + *--__e = std::move(__v); } } return begin() + __pos; @@ -1878,21 +1881,21 @@ deque<_Tp, _Allocator>::emplace(const_iterator __p, _Args&&... __args) __annotate_increase_front(1); if (__pos == 0) { - __alloc_traits::construct(__a, _VSTD::addressof(*--begin()), _VSTD::forward<_Args>(__args)...); + __alloc_traits::construct(__a, std::addressof(*--begin()), std::forward<_Args>(__args)...); --__start_; ++__size(); } else { - __temp_value __tmp(__alloc(), _VSTD::forward<_Args>(__args)...); + __temp_value __tmp(__alloc(), std::forward<_Args>(__args)...); iterator __b = begin(); - iterator __bm1 = _VSTD::prev(__b); - __alloc_traits::construct(__a, _VSTD::addressof(*__bm1), _VSTD::move(*__b)); + iterator __bm1 = std::prev(__b); + __alloc_traits::construct(__a, std::addressof(*__bm1), std::move(*__b)); --__start_; ++__size(); if (__pos > 1) - __b = _VSTD::move(_VSTD::next(__b), __b + __pos, __b); - *__b = _VSTD::move(__tmp.get()); + __b = std::move(std::next(__b), __b + __pos, __b); + *__b = std::move(__tmp.get()); } } else @@ -1904,19 +1907,19 @@ deque<_Tp, _Allocator>::emplace(const_iterator __p, _Args&&... __args) size_type __de = size() - __pos; if (__de == 0) { - __alloc_traits::construct(__a, _VSTD::addressof(*end()), _VSTD::forward<_Args>(__args)...); + __alloc_traits::construct(__a, std::addressof(*end()), std::forward<_Args>(__args)...); ++__size(); } else { - __temp_value __tmp(__alloc(), _VSTD::forward<_Args>(__args)...); + __temp_value __tmp(__alloc(), std::forward<_Args>(__args)...); iterator __e = end(); - iterator __em1 = _VSTD::prev(__e); - __alloc_traits::construct(__a, _VSTD::addressof(*__e), _VSTD::move(*__em1)); + iterator __em1 = std::prev(__e); + __alloc_traits::construct(__a, std::addressof(*__e), std::move(*__em1)); ++__size(); if (__de > 1) - __e = _VSTD::move_backward(__e - __de, __em1, __e); - *--__e = _VSTD::move(__tmp.get()); + __e = std::move_backward(__e - __de, __em1, __e); + *--__e = std::move(__tmp.get()); } } return begin() + __pos; @@ -1940,7 +1943,7 @@ deque<_Tp, _Allocator>::insert(const_iterator __p, const value_type& __v) __annotate_increase_front(1); if (__pos == 0) { - __alloc_traits::construct(__a, _VSTD::addressof(*--begin()), __v); + __alloc_traits::construct(__a, std::addressof(*--begin()), __v); --__start_; ++__size(); } @@ -1948,14 +1951,14 @@ deque<_Tp, _Allocator>::insert(const_iterator __p, const value_type& __v) { const_pointer __vt = pointer_traits::pointer_to(__v); iterator __b = begin(); - iterator __bm1 = _VSTD::prev(__b); + iterator __bm1 = std::prev(__b); if (__vt == pointer_traits::pointer_to(*__b)) __vt = pointer_traits::pointer_to(*__bm1); - __alloc_traits::construct(__a, _VSTD::addressof(*__bm1), _VSTD::move(*__b)); + __alloc_traits::construct(__a, std::addressof(*__bm1), std::move(*__b)); --__start_; ++__size(); if (__pos > 1) - __b = __move_and_check(_VSTD::next(__b), __b + __pos, __b, __vt); + __b = __move_and_check(std::next(__b), __b + __pos, __b, __vt); *__b = *__vt; } } @@ -1968,17 +1971,17 @@ deque<_Tp, _Allocator>::insert(const_iterator __p, const value_type& __v) size_type __de = size() - __pos; if (__de == 0) { - __alloc_traits::construct(__a, _VSTD::addressof(*end()), __v); + __alloc_traits::construct(__a, std::addressof(*end()), __v); ++__size(); } else { const_pointer __vt = pointer_traits::pointer_to(__v); iterator __e = end(); - iterator __em1 = _VSTD::prev(__e); + iterator __em1 = std::prev(__e); if (__vt == pointer_traits::pointer_to(*__em1)) __vt = pointer_traits::pointer_to(*__e); - __alloc_traits::construct(__a, _VSTD::addressof(*__e), _VSTD::move(*__em1)); + __alloc_traits::construct(__a, std::addressof(*__e), std::move(*__em1)); ++__size(); if (__de > 1) __e = __move_backward_and_check(__e - __de, __em1, __e, __vt); @@ -2006,7 +2009,7 @@ deque<_Tp, _Allocator>::insert(const_iterator __p, size_type __n, const value_ty if (__n > __pos) { for (size_type __m = __n - __pos; __m; --__m, --__start_, ++__size()) - __alloc_traits::construct(__a, _VSTD::addressof(*--__i), __v); + __alloc_traits::construct(__a, std::addressof(*--__i), __v); __n = __pos; } if (__n > 0) @@ -2016,7 +2019,7 @@ deque<_Tp, _Allocator>::insert(const_iterator __p, size_type __n, const value_ty __move_construct_backward_and_check(__old_begin, __obn, __i, __vt); if (__n < __pos) __old_begin = __move_and_check(__obn, __old_begin + __pos, __old_begin, __vt); - _VSTD::fill_n(__old_begin, __n, *__vt); + std::fill_n(__old_begin, __n, *__vt); } } else @@ -2032,7 +2035,7 @@ deque<_Tp, _Allocator>::insert(const_iterator __p, size_type __n, const value_ty if (__n > __de) { for (size_type __m = __n - __de; __m; --__m, (void) ++__i, ++__size()) - __alloc_traits::construct(__a, _VSTD::addressof(*__i), __v); + __alloc_traits::construct(__a, std::addressof(*__i), __v); __n = __de; } if (__n > 0) @@ -2042,7 +2045,7 @@ deque<_Tp, _Allocator>::insert(const_iterator __p, size_type __n, const value_ty __move_construct_and_check(__oen, __old_end, __i, __vt); if (__n < __de) __old_end = __move_backward_and_check(__old_end - __de, __oen, __old_end, __vt); - _VSTD::fill_n(__old_end - __n, __n, *__vt); + std::fill_n(__old_end - __n, __n, *__vt); } } return begin() + __pos; @@ -2121,9 +2124,9 @@ deque<_Tp, _Allocator>::__insert_bidirectional(const_iterator __p, _BiIter __f, _BiIter __m = __f; if (__n > __pos) { - __m = __pos < __n / 2 ? _VSTD::prev(__l, __pos) : _VSTD::next(__f, __n - __pos); + __m = __pos < __n / 2 ? std::prev(__l, __pos) : std::next(__f, __n - __pos); for (_BiIter __j = __m; __j != __f; --__start_, ++__size()) - __alloc_traits::construct(__a, _VSTD::addressof(*--__i), *--__j); + __alloc_traits::construct(__a, std::addressof(*--__i), *--__j); __n = __pos; } if (__n > 0) @@ -2131,13 +2134,13 @@ deque<_Tp, _Allocator>::__insert_bidirectional(const_iterator __p, _BiIter __f, iterator __obn = __old_begin + __n; for (iterator __j = __obn; __j != __old_begin;) { - __alloc_traits::construct(__a, _VSTD::addressof(*--__i), _VSTD::move(*--__j)); + __alloc_traits::construct(__a, std::addressof(*--__i), std::move(*--__j)); --__start_; ++__size(); } if (__n < __pos) - __old_begin = _VSTD::move(__obn, __old_begin + __pos, __old_begin); - _VSTD::copy(__m, __l, __old_begin); + __old_begin = std::move(__obn, __old_begin + __pos, __old_begin); + std::copy(__m, __l, __old_begin); } } else @@ -2153,19 +2156,19 @@ deque<_Tp, _Allocator>::__insert_bidirectional(const_iterator __p, _BiIter __f, size_type __de = size() - __pos; if (__n > __de) { - __m = __de < __n / 2 ? _VSTD::next(__f, __de) : _VSTD::prev(__l, __n - __de); + __m = __de < __n / 2 ? std::next(__f, __de) : std::prev(__l, __n - __de); for (_BiIter __j = __m; __j != __l; ++__i, (void) ++__j, ++__size()) - __alloc_traits::construct(__a, _VSTD::addressof(*__i), *__j); + __alloc_traits::construct(__a, std::addressof(*__i), *__j); __n = __de; } if (__n > 0) { iterator __oen = __old_end - __n; for (iterator __j = __oen; __j != __old_end; ++__i, (void) ++__j, ++__size()) - __alloc_traits::construct(__a, _VSTD::addressof(*__i), _VSTD::move(*__j)); + __alloc_traits::construct(__a, std::addressof(*__i), std::move(*__j)); if (__n < __de) - __old_end = _VSTD::move_backward(__old_end - __de, __oen, __old_end); - _VSTD::copy_backward(__f, __m, __old_end); + __old_end = std::move_backward(__old_end - __de, __oen, __old_end); + std::copy_backward(__f, __m, __old_end); } } return begin() + __pos; @@ -2213,7 +2216,7 @@ void deque<_Tp, _Allocator>::__append_with_size(_InputIterator __f, size_type __ for (__deque_block_range __br : __deque_range(end(), end() + __n)) { _ConstructTransaction __tx(this, __br); for (; __tx.__pos_ != __tx.__end_; ++__tx.__pos_, (void)++__f) { - __alloc_traits::construct(__a, _VSTD::__to_address(__tx.__pos_), *__f); + __alloc_traits::construct(__a, std::__to_address(__tx.__pos_), *__f); } } } @@ -2231,7 +2234,7 @@ deque<_Tp, _Allocator>::__append(size_type __n) for (__deque_block_range __br : __deque_range(end(), end() + __n)) { _ConstructTransaction __tx(this, __br); for (; __tx.__pos_ != __tx.__end_; ++__tx.__pos_) { - __alloc_traits::construct(__a, _VSTD::__to_address(__tx.__pos_)); + __alloc_traits::construct(__a, std::__to_address(__tx.__pos_)); } } } @@ -2249,7 +2252,7 @@ deque<_Tp, _Allocator>::__append(size_type __n, const value_type& __v) for (__deque_block_range __br : __deque_range(end(), end() + __n)) { _ConstructTransaction __tx(this, __br); for (; __tx.__pos_ != __tx.__end_; ++__tx.__pos_) { - __alloc_traits::construct(__a, _VSTD::__to_address(__tx.__pos_), __v); + __alloc_traits::construct(__a, std::__to_address(__tx.__pos_), __v); } } @@ -2305,10 +2308,10 @@ deque<_Tp, _Allocator>::__add_front_capacity() for (__map_pointer __i = __map_.begin(); __i != __map_.end(); ++__i) __buf.push_back(*__i); - _VSTD::swap(__map_.__first_, __buf.__first_); - _VSTD::swap(__map_.__begin_, __buf.__begin_); - _VSTD::swap(__map_.__end_, __buf.__end_); - _VSTD::swap(__map_.__end_cap(), __buf.__end_cap()); + std::swap(__map_.__first_, __buf.__first_); + std::swap(__map_.__begin_, __buf.__begin_); + std::swap(__map_.__end_, __buf.__end_); + std::swap(__map_.__end_cap(), __buf.__end_cap()); __start_ = __map_.size() == 1 ? __block_size / 2 : __start_ + __block_size; @@ -2326,7 +2329,7 @@ deque<_Tp, _Allocator>::__add_front_capacity(size_type __n) size_type __nb = __recommend_blocks(__n + __map_.empty()); // Number of unused blocks at back: size_type __back_capacity = __back_spare() / __block_size; - __back_capacity = _VSTD::min(__back_capacity, __nb); // don't take more than you need + __back_capacity = std::min(__back_capacity, __nb); // don't take more than you need __nb -= __back_capacity; // number of blocks need to allocate // If __nb == 0, then we have sufficient capacity. if (__nb == 0) @@ -2401,10 +2404,10 @@ deque<_Tp, _Allocator>::__add_front_capacity(size_type __n) for (__map_pointer __i = __map_.begin(); __i != __map_.end(); ++__i) __buf.push_back(*__i); - _VSTD::swap(__map_.__first_, __buf.__first_); - _VSTD::swap(__map_.__begin_, __buf.__begin_); - _VSTD::swap(__map_.__end_, __buf.__end_); - _VSTD::swap(__map_.__end_cap(), __buf.__end_cap()); + std::swap(__map_.__first_, __buf.__first_); + std::swap(__map_.__begin_, __buf.__begin_); + std::swap(__map_.__end_, __buf.__end_); + std::swap(__map_.__end_cap(), __buf.__end_cap()); __start_ += __ds; } } @@ -2458,10 +2461,10 @@ deque<_Tp, _Allocator>::__add_back_capacity() for (__map_pointer __i = __map_.end(); __i != __map_.begin();) __buf.push_front(*--__i); - _VSTD::swap(__map_.__first_, __buf.__first_); - _VSTD::swap(__map_.__begin_, __buf.__begin_); - _VSTD::swap(__map_.__end_, __buf.__end_); - _VSTD::swap(__map_.__end_cap(), __buf.__end_cap()); + std::swap(__map_.__first_, __buf.__first_); + std::swap(__map_.__begin_, __buf.__begin_); + std::swap(__map_.__end_, __buf.__end_); + std::swap(__map_.__end_cap(), __buf.__end_cap()); __annotate_whole_block(__map_.size() - 1, __asan_poison); } } @@ -2476,7 +2479,7 @@ deque<_Tp, _Allocator>::__add_back_capacity(size_type __n) size_type __nb = __recommend_blocks(__n + __map_.empty()); // Number of unused blocks at front: size_type __front_capacity = __front_spare() / __block_size; - __front_capacity = _VSTD::min(__front_capacity, __nb); // don't take more than you need + __front_capacity = std::min(__front_capacity, __nb); // don't take more than you need __nb -= __front_capacity; // number of blocks need to allocate // If __nb == 0, then we have sufficient capacity. if (__nb == 0) @@ -2554,10 +2557,10 @@ deque<_Tp, _Allocator>::__add_back_capacity(size_type __n) for (__map_pointer __i = __map_.end(); __i != __map_.begin();) __buf.push_front(*--__i); - _VSTD::swap(__map_.__first_, __buf.__first_); - _VSTD::swap(__map_.__begin_, __buf.__begin_); - _VSTD::swap(__map_.__end_, __buf.__end_); - _VSTD::swap(__map_.__end_cap(), __buf.__end_cap()); + std::swap(__map_.__first_, __buf.__first_); + std::swap(__map_.__begin_, __buf.__begin_); + std::swap(__map_.__end_, __buf.__end_); + std::swap(__map_.__end_cap(), __buf.__end_cap()); __start_ -= __ds; } } @@ -2569,7 +2572,7 @@ deque<_Tp, _Allocator>::pop_front() size_type __old_sz = size(); size_type __old_start = __start_; allocator_type& __a = __alloc(); - __alloc_traits::destroy(__a, _VSTD::__to_address(*(__map_.begin() + + __alloc_traits::destroy(__a, std::__to_address(*(__map_.begin() + __start_ / __block_size) + __start_ % __block_size)); --__size(); @@ -2587,7 +2590,7 @@ deque<_Tp, _Allocator>::pop_back() size_type __old_start = __start_; allocator_type& __a = __alloc(); size_type __p = size() + __start_ - 1; - __alloc_traits::destroy(__a, _VSTD::__to_address(*(__map_.begin() + + __alloc_traits::destroy(__a, std::__to_address(*(__map_.begin() + __p / __block_size) + __p % __block_size)); --__size(); @@ -2604,7 +2607,7 @@ deque<_Tp, _Allocator>::__move_and_check(iterator __f, iterator __l, iterator __ { // as if // for (; __f != __l; ++__f, ++__r) - // *__r = _VSTD::move(*__f); + // *__r = std::move(*__f); difference_type __n = __l - __f; while (__n > 0) { @@ -2618,7 +2621,7 @@ deque<_Tp, _Allocator>::__move_and_check(iterator __f, iterator __l, iterator __ } if (__fb <= __vt && __vt < __fe) __vt = (const_iterator(static_cast<__map_const_pointer>(__f.__m_iter_), __vt) -= __f - __r).__ptr_; - __r = _VSTD::move(__fb, __fe, __r); + __r = std::move(__fb, __fe, __r); __n -= __bs; __f += __bs; } @@ -2634,7 +2637,7 @@ deque<_Tp, _Allocator>::__move_backward_and_check(iterator __f, iterator __l, it { // as if // while (__f != __l) - // *--__r = _VSTD::move(*--__l); + // *--__r = std::move(*--__l); difference_type __n = __l - __f; while (__n > 0) { @@ -2649,7 +2652,7 @@ deque<_Tp, _Allocator>::__move_backward_and_check(iterator __f, iterator __l, it } if (__lb <= __vt && __vt < __le) __vt = (const_iterator(static_cast<__map_const_pointer>(__l.__m_iter_), __vt) += __r - __l - 1).__ptr_; - __r = _VSTD::move_backward(__lb, __le, __r); + __r = std::move_backward(__lb, __le, __r); __n -= __bs; __l -= __bs - 1; } @@ -2666,7 +2669,7 @@ deque<_Tp, _Allocator>::__move_construct_and_check(iterator __f, iterator __l, allocator_type& __a = __alloc(); // as if // for (; __f != __l; ++__r, ++__f, ++__size()) - // __alloc_traits::construct(__a, _VSTD::addressof(*__r), _VSTD::move(*__f)); + // __alloc_traits::construct(__a, std::addressof(*__r), std::move(*__f)); difference_type __n = __l - __f; while (__n > 0) { @@ -2681,7 +2684,7 @@ deque<_Tp, _Allocator>::__move_construct_and_check(iterator __f, iterator __l, if (__fb <= __vt && __vt < __fe) __vt = (const_iterator(static_cast<__map_const_pointer>(__f.__m_iter_), __vt) += __r - __f).__ptr_; for (; __fb != __fe; ++__fb, ++__r, ++__size()) - __alloc_traits::construct(__a, _VSTD::addressof(*__r), _VSTD::move(*__fb)); + __alloc_traits::construct(__a, std::addressof(*__r), std::move(*__fb)); __n -= __bs; __f += __bs; } @@ -2698,7 +2701,7 @@ deque<_Tp, _Allocator>::__move_construct_backward_and_check(iterator __f, iterat // as if // for (iterator __j = __l; __j != __f;) // { - // __alloc_traitsconstruct(__a, _VSTD::addressof(*--__r), _VSTD::move(*--__j)); + // __alloc_traitsconstruct(__a, std::addressof(*--__r), std::move(*--__j)); // --__start_; // ++__size(); // } @@ -2718,7 +2721,7 @@ deque<_Tp, _Allocator>::__move_construct_backward_and_check(iterator __f, iterat __vt = (const_iterator(static_cast<__map_const_pointer>(__l.__m_iter_), __vt) -= __l - __r + 1).__ptr_; while (__le != __lb) { - __alloc_traits::construct(__a, _VSTD::addressof(*--__r), _VSTD::move(*--__le)); + __alloc_traits::construct(__a, std::addressof(*--__r), std::move(*--__le)); --__start_; ++__size(); } @@ -2739,8 +2742,8 @@ deque<_Tp, _Allocator>::erase(const_iterator __f) allocator_type& __a = __alloc(); if (static_cast(__pos) <= (size() - 1) / 2) { // erase from front - _VSTD::move_backward(__b, __p, _VSTD::next(__p)); - __alloc_traits::destroy(__a, _VSTD::addressof(*__b)); + std::move_backward(__b, __p, std::next(__p)); + __alloc_traits::destroy(__a, std::addressof(*__b)); --__size(); ++__start_; __annotate_shrink_front(__old_sz, __old_start); @@ -2748,8 +2751,8 @@ deque<_Tp, _Allocator>::erase(const_iterator __f) } else { // erase from back - iterator __i = _VSTD::move(_VSTD::next(__p), end(), __p); - __alloc_traits::destroy(__a, _VSTD::addressof(*__i)); + iterator __i = std::move(std::next(__p), end(), __p); + __alloc_traits::destroy(__a, std::addressof(*__i)); --__size(); __annotate_shrink_back(__old_sz, __old_start); __maybe_remove_back_spare(); @@ -2772,9 +2775,9 @@ deque<_Tp, _Allocator>::erase(const_iterator __f, const_iterator __l) allocator_type& __a = __alloc(); if (static_cast(__pos) <= (size() - __n) / 2) { // erase from front - iterator __i = _VSTD::move_backward(__b, __p, __p + __n); + iterator __i = std::move_backward(__b, __p, __p + __n); for (; __b != __i; ++__b) - __alloc_traits::destroy(__a, _VSTD::addressof(*__b)); + __alloc_traits::destroy(__a, std::addressof(*__b)); __size() -= __n; __start_ += __n; __annotate_shrink_front(__old_sz, __old_start); @@ -2783,9 +2786,9 @@ deque<_Tp, _Allocator>::erase(const_iterator __f, const_iterator __l) } else { // erase from back - iterator __i = _VSTD::move(__p + __n, end(), __p); + iterator __i = std::move(__p + __n, end(), __p); for (iterator __e = end(); __i != __e; ++__i) - __alloc_traits::destroy(__a, _VSTD::addressof(*__i)); + __alloc_traits::destroy(__a, std::addressof(*__i)); __size() -= __n; __annotate_shrink_back(__old_sz, __old_start); while (__maybe_remove_back_spare()) { @@ -2809,7 +2812,7 @@ deque<_Tp, _Allocator>::__erase_to_end(const_iterator __f) iterator __b = begin(); difference_type __pos = __f - __b; for (iterator __p = __b + __pos; __p != __e; ++__p) - __alloc_traits::destroy(__a, _VSTD::addressof(*__p)); + __alloc_traits::destroy(__a, std::addressof(*__p)); __size() -= __n; __annotate_shrink_back(__old_sz, __old_start); while (__maybe_remove_back_spare()) { @@ -2829,9 +2832,9 @@ deque<_Tp, _Allocator>::swap(deque& __c) #endif { __map_.swap(__c.__map_); - _VSTD::swap(__start_, __c.__start_); - _VSTD::swap(__size(), __c.__size()); - _VSTD::__swap_allocator(__alloc(), __c.__alloc()); + std::swap(__start_, __c.__start_); + std::swap(__size(), __c.__size()); + std::__swap_allocator(__alloc(), __c.__alloc()); } template @@ -2842,7 +2845,7 @@ deque<_Tp, _Allocator>::clear() _NOEXCEPT __annotate_delete(); allocator_type& __a = __alloc(); for (iterator __i = begin(), __e = end(); __i != __e; ++__i) - __alloc_traits::destroy(__a, _VSTD::addressof(*__i)); + __alloc_traits::destroy(__a, std::addressof(*__i)); __size() = 0; while (__map_.size() > 2) { @@ -2867,7 +2870,7 @@ bool operator==(const deque<_Tp, _Allocator>& __x, const deque<_Tp, _Allocator>& __y) { const typename deque<_Tp, _Allocator>::size_type __sz = __x.size(); - return __sz == __y.size() && _VSTD::equal(__x.begin(), __x.end(), __y.begin()); + return __sz == __y.size() && std::equal(__x.begin(), __x.end(), __y.begin()); } #if _LIBCPP_STD_VER <= 17 @@ -2885,7 +2888,7 @@ inline _LIBCPP_HIDE_FROM_ABI bool operator< (const deque<_Tp, _Allocator>& __x, const deque<_Tp, _Allocator>& __y) { - return _VSTD::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); + return std::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); } template @@ -2937,7 +2940,7 @@ template inline _LIBCPP_HIDE_FROM_ABI typename deque<_Tp, _Allocator>::size_type erase(deque<_Tp, _Allocator>& __c, const _Up& __v) { auto __old_size = __c.size(); - __c.erase(_VSTD::remove(__c.begin(), __c.end(), __v), __c.end()); + __c.erase(std::remove(__c.begin(), __c.end(), __v), __c.end()); return __old_size - __c.size(); } @@ -2945,7 +2948,7 @@ template inline _LIBCPP_HIDE_FROM_ABI typename deque<_Tp, _Allocator>::size_type erase_if(deque<_Tp, _Allocator>& __c, _Predicate __pred) { auto __old_size = __c.size(); - __c.erase(_VSTD::remove_if(__c.begin(), __c.end(), __pred), __c.end()); + __c.erase(std::remove_if(__c.begin(), __c.end(), __pred), __c.end()); return __old_size - __c.size(); } diff --git a/libcxx/include/experimental/__config b/libcxx/include/experimental/__config index c86fd36dc558..8bc4f5dd141a 100644 --- a/libcxx/include/experimental/__config +++ b/libcxx/include/experimental/__config @@ -18,15 +18,12 @@ #define _LIBCPP_BEGIN_NAMESPACE_EXPERIMENTAL namespace std { namespace experimental { #define _LIBCPP_END_NAMESPACE_EXPERIMENTAL } } -#define _VSTD_EXPERIMENTAL std::experimental #define _LIBCPP_BEGIN_NAMESPACE_LFTS _LIBCPP_BEGIN_NAMESPACE_EXPERIMENTAL inline namespace fundamentals_v1 { #define _LIBCPP_END_NAMESPACE_LFTS } } } -#define _VSTD_LFTS _VSTD_EXPERIMENTAL::fundamentals_v1 #define _LIBCPP_BEGIN_NAMESPACE_LFTS_V2 _LIBCPP_BEGIN_NAMESPACE_EXPERIMENTAL inline namespace fundamentals_v2 { #define _LIBCPP_END_NAMESPACE_LFTS_V2 } } } -#define _VSTD_LFTS_V2 _VSTD_EXPERIMENTAL::fundamentals_v2 // TODO: support more targets #if defined(__AVX__) diff --git a/libcxx/include/experimental/__memory b/libcxx/include/experimental/__memory index c1abe34280c8..fb82922d1eb2 100644 --- a/libcxx/include/experimental/__memory +++ b/libcxx/include/experimental/__memory @@ -85,7 +85,7 @@ template inline _LIBCPP_HIDE_FROM_ABI void __user_alloc_construct_impl (integral_constant, _Tp *__storage, const _Allocator &, _Args &&... __args ) { - new (__storage) _Tp (_VSTD::forward<_Args>(__args)...); + new (__storage) _Tp (std::forward<_Args>(__args)...); } // FIXME: This should have a version which takes a non-const alloc. @@ -93,7 +93,7 @@ template inline _LIBCPP_HIDE_FROM_ABI void __user_alloc_construct_impl (integral_constant, _Tp *__storage, const _Allocator &__a, _Args &&... __args ) { - new (__storage) _Tp (allocator_arg_t(), __a, _VSTD::forward<_Args>(__args)...); + new (__storage) _Tp (allocator_arg_t(), __a, std::forward<_Args>(__args)...); } // FIXME: This should have a version which takes a non-const alloc. @@ -101,7 +101,7 @@ template inline _LIBCPP_HIDE_FROM_ABI void __user_alloc_construct_impl (integral_constant, _Tp *__storage, const _Allocator &__a, _Args &&... __args ) { - new (__storage) _Tp (_VSTD::forward<_Args>(__args)..., __a); + new (__storage) _Tp (std::forward<_Args>(__args)..., __a); } template @@ -111,7 +111,7 @@ void __lfts_user_alloc_construct( { ::std::experimental::fundamentals_v1::__user_alloc_construct_impl( typename __lfts_uses_alloc_ctor<_Tp, _Alloc, _Args...>::type() - , __store, __a, _VSTD::forward<_Args>(__args)... + , __store, __a, std::forward<_Args>(__args)... ); } diff --git a/libcxx/include/experimental/iterator b/libcxx/include/experimental/iterator index 5f9842de4f7f..bca7d4c182ad 100644 --- a/libcxx/include/experimental/iterator +++ b/libcxx/include/experimental/iterator @@ -82,10 +82,10 @@ public: typedef void reference; _LIBCPP_HIDE_FROM_ABI ostream_joiner(ostream_type& __os, _Delim&& __d) - : __output_iter_(_VSTD::addressof(__os)), __delim_(_VSTD::move(__d)), __first_(true) {} + : __output_iter_(std::addressof(__os)), __delim_(std::move(__d)), __first_(true) {} _LIBCPP_HIDE_FROM_ABI ostream_joiner(ostream_type& __os, const _Delim& __d) - : __output_iter_(_VSTD::addressof(__os)), __delim_(__d), __first_(true) {} + : __output_iter_(std::addressof(__os)), __delim_(__d), __first_(true) {} template @@ -112,7 +112,7 @@ private: template _LIBCPP_HIDE_FROM_ABI ostream_joiner<__decay_t<_Delim>, _CharT, _Traits> make_ostream_joiner(basic_ostream<_CharT, _Traits>& __os, _Delim && __d) -{ return ostream_joiner<__decay_t<_Delim>, _CharT, _Traits>(__os, _VSTD::forward<_Delim>(__d)); } +{ return ostream_joiner<__decay_t<_Delim>, _CharT, _Traits>(__os, std::forward<_Delim>(__d)); } _LIBCPP_END_NAMESPACE_LFTS diff --git a/libcxx/include/experimental/propagate_const b/libcxx/include/experimental/propagate_const index 84809e78d3fd..fd58f6637af5 100644 --- a/libcxx/include/experimental/propagate_const +++ b/libcxx/include/experimental/propagate_const @@ -19,8 +19,8 @@ template class propagate_const; // [propagate_const.underlying], underlying pointer access - constexpr const _Tp& _VSTD_LFTS_V2::get_underlying(const propagate_const& pt) noexcept; - constexpr T& _VSTD_LFTS_V2::get_underlying(propagate_const& pt) noexcept; + constexpr const _Tp& get_underlying(const propagate_const& pt) noexcept; + constexpr T& get_underlying(propagate_const& pt) noexcept; // [propagate_const.relational], relational operators template constexpr bool operator==(const propagate_const& pt, nullptr_t); @@ -93,15 +93,15 @@ } // namespace experimental // [propagate_const.hash], hash support - template struct hash>; + template struct hash>; // [propagate_const.comparison_function_objects], comparison function objects - template struct equal_to>; - template struct not_equal_to>; - template struct less>; - template struct greater>; - template struct less_equal>; - template struct greater_equal>; + template struct equal_to>; + template struct not_equal_to>; + template struct less>; + template struct greater>; + template struct less_equal>; + template struct greater_equal>; } // namespace std @@ -207,8 +207,8 @@ private: public: - template friend _LIBCPP_CONSTEXPR const _Up& ::_VSTD_LFTS_V2::get_underlying(const propagate_const<_Up>& __pu) _NOEXCEPT; - template friend _LIBCPP_CONSTEXPR _Up& ::_VSTD_LFTS_V2::get_underlying(propagate_const<_Up>& __pu) _NOEXCEPT; + template friend _LIBCPP_CONSTEXPR const _Up& experimental::fundamentals_v2::get_underlying(const propagate_const<_Up>& __pu) _NOEXCEPT; + template friend _LIBCPP_CONSTEXPR _Up& experimental::fundamentals_v2::get_underlying(propagate_const<_Up>& __pu) _NOEXCEPT; _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR propagate_const() = default; @@ -219,14 +219,14 @@ public: template ::value && is_constructible<_Tp, _Up&&>::value,bool> = true> explicit _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR propagate_const(propagate_const<_Up>&& __pu) - : __t_(std::move(_VSTD_LFTS_V2::get_underlying(__pu))) + : __t_(std::move(experimental::get_underlying(__pu))) { } template ::value && is_constructible<_Tp, _Up&&>::value,bool> = false> _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR propagate_const(propagate_const<_Up>&& __pu) - : __t_(std::move(_VSTD_LFTS_V2::get_underlying(__pu))) + : __t_(std::move(experimental::get_underlying(__pu))) { } @@ -253,7 +253,7 @@ public: template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR propagate_const& operator=(propagate_const<_Up>&& __pu) { - __t_ = std::move(_VSTD_LFTS_V2::get_underlying(__pu)); + __t_ = std::move(experimental::get_underlying(__pu)); return *this; } @@ -313,7 +313,7 @@ public: _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR void swap(propagate_const& __pt) _NOEXCEPT_(__is_nothrow_swappable<_Tp>::value) { - using _VSTD::swap; + using std::swap; swap(__t_, __pt.__t_); } }; @@ -323,28 +323,28 @@ template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator==(const propagate_const<_Tp>& __pt, nullptr_t) { - return _VSTD_LFTS_V2::get_underlying(__pt) == nullptr; + return experimental::get_underlying(__pt) == nullptr; } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator==(nullptr_t, const propagate_const<_Tp>& __pt) { - return nullptr == _VSTD_LFTS_V2::get_underlying(__pt); + return nullptr == experimental::get_underlying(__pt); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator!=(const propagate_const<_Tp>& __pt, nullptr_t) { - return _VSTD_LFTS_V2::get_underlying(__pt) != nullptr; + return experimental::get_underlying(__pt) != nullptr; } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator!=(nullptr_t, const propagate_const<_Tp>& __pt) { - return nullptr != _VSTD_LFTS_V2::get_underlying(__pt); + return nullptr != experimental::get_underlying(__pt); } template @@ -352,7 +352,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator==(const propagate_const<_Tp>& __pt, const propagate_const<_Up>& __pu) { - return _VSTD_LFTS_V2::get_underlying(__pt) == _VSTD_LFTS_V2::get_underlying(__pu); + return experimental::get_underlying(__pt) == experimental::get_underlying(__pu); } template @@ -360,7 +360,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator!=(const propagate_const<_Tp>& __pt, const propagate_const<_Up>& __pu) { - return _VSTD_LFTS_V2::get_underlying(__pt) != _VSTD_LFTS_V2::get_underlying(__pu); + return experimental::get_underlying(__pt) != experimental::get_underlying(__pu); } template @@ -368,7 +368,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator<(const propagate_const<_Tp>& __pt, const propagate_const<_Up>& __pu) { - return _VSTD_LFTS_V2::get_underlying(__pt) < _VSTD_LFTS_V2::get_underlying(__pu); + return experimental::get_underlying(__pt) < experimental::get_underlying(__pu); } template @@ -376,7 +376,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator>(const propagate_const<_Tp>& __pt, const propagate_const<_Up>& __pu) { - return _VSTD_LFTS_V2::get_underlying(__pt) > _VSTD_LFTS_V2::get_underlying(__pu); + return experimental::get_underlying(__pt) > experimental::get_underlying(__pu); } template @@ -384,7 +384,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator<=(const propagate_const<_Tp>& __pt, const propagate_const<_Up>& __pu) { - return _VSTD_LFTS_V2::get_underlying(__pt) <= _VSTD_LFTS_V2::get_underlying(__pu); + return experimental::get_underlying(__pt) <= experimental::get_underlying(__pu); } template @@ -392,49 +392,49 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator>=(const propagate_const<_Tp>& __pt, const propagate_const<_Up>& __pu) { - return _VSTD_LFTS_V2::get_underlying(__pt) >= _VSTD_LFTS_V2::get_underlying(__pu); + return experimental::get_underlying(__pt) >= experimental::get_underlying(__pu); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator==(const propagate_const<_Tp>& __pt, const _Up& __u) { - return _VSTD_LFTS_V2::get_underlying(__pt) == __u; + return experimental::get_underlying(__pt) == __u; } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator!=(const propagate_const<_Tp>& __pt, const _Up& __u) { - return _VSTD_LFTS_V2::get_underlying(__pt) != __u; + return experimental::get_underlying(__pt) != __u; } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator<(const propagate_const<_Tp>& __pt, const _Up& __u) { - return _VSTD_LFTS_V2::get_underlying(__pt) < __u; + return experimental::get_underlying(__pt) < __u; } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator>(const propagate_const<_Tp>& __pt, const _Up& __u) { - return _VSTD_LFTS_V2::get_underlying(__pt) > __u; + return experimental::get_underlying(__pt) > __u; } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator<=(const propagate_const<_Tp>& __pt, const _Up& __u) { - return _VSTD_LFTS_V2::get_underlying(__pt) <= __u; + return experimental::get_underlying(__pt) <= __u; } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator>=(const propagate_const<_Tp>& __pt, const _Up& __u) { - return _VSTD_LFTS_V2::get_underlying(__pt) >= __u; + return experimental::get_underlying(__pt) >= __u; } @@ -442,42 +442,42 @@ template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator==(const _Tp& __t, const propagate_const<_Up>& __pu) { - return __t == _VSTD_LFTS_V2::get_underlying(__pu); + return __t == experimental::get_underlying(__pu); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator!=(const _Tp& __t, const propagate_const<_Up>& __pu) { - return __t != _VSTD_LFTS_V2::get_underlying(__pu); + return __t != experimental::get_underlying(__pu); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator<(const _Tp& __t, const propagate_const<_Up>& __pu) { - return __t < _VSTD_LFTS_V2::get_underlying(__pu); + return __t < experimental::get_underlying(__pu); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator>(const _Tp& __t, const propagate_const<_Up>& __pu) { - return __t > _VSTD_LFTS_V2::get_underlying(__pu); + return __t > experimental::get_underlying(__pu); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator<=(const _Tp& __t, const propagate_const<_Up>& __pu) { - return __t <= _VSTD_LFTS_V2::get_underlying(__pu); + return __t <= experimental::get_underlying(__pu); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR bool operator>=(const _Tp& __t, const propagate_const<_Up>& __pu) { - return __t >= _VSTD_LFTS_V2::get_underlying(__pu); + return __t >= experimental::get_underlying(__pu); } template @@ -504,92 +504,92 @@ _LIBCPP_END_NAMESPACE_LFTS_V2 _LIBCPP_BEGIN_NAMESPACE_STD template -struct hash> +struct hash> { typedef size_t result_type; - typedef experimental::fundamentals_v2::propagate_const<_Tp> argument_type; + typedef experimental::propagate_const<_Tp> argument_type; - _LIBCPP_HIDE_FROM_ABI size_t operator()(const experimental::fundamentals_v2::propagate_const<_Tp>& __pc1) const + _LIBCPP_HIDE_FROM_ABI size_t operator()(const experimental::propagate_const<_Tp>& __pc1) const { - return std::hash<_Tp>()(_VSTD_LFTS_V2::get_underlying(__pc1)); + return std::hash<_Tp>()(experimental::get_underlying(__pc1)); } }; template -struct equal_to> +struct equal_to> { - typedef experimental::fundamentals_v2::propagate_const<_Tp> first_argument_type; - typedef experimental::fundamentals_v2::propagate_const<_Tp> second_argument_type; + typedef experimental::propagate_const<_Tp> first_argument_type; + typedef experimental::propagate_const<_Tp> second_argument_type; - _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::fundamentals_v2::propagate_const<_Tp>& __pc1, - const experimental::fundamentals_v2::propagate_const<_Tp>& __pc2) const + _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::propagate_const<_Tp>& __pc1, + const experimental::propagate_const<_Tp>& __pc2) const { - return std::equal_to<_Tp>()(_VSTD_LFTS_V2::get_underlying(__pc1), _VSTD_LFTS_V2::get_underlying(__pc2)); + return std::equal_to<_Tp>()(experimental::get_underlying(__pc1), experimental::get_underlying(__pc2)); } }; template -struct not_equal_to> +struct not_equal_to> { - typedef experimental::fundamentals_v2::propagate_const<_Tp> first_argument_type; - typedef experimental::fundamentals_v2::propagate_const<_Tp> second_argument_type; + typedef experimental::propagate_const<_Tp> first_argument_type; + typedef experimental::propagate_const<_Tp> second_argument_type; - _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::fundamentals_v2::propagate_const<_Tp>& __pc1, - const experimental::fundamentals_v2::propagate_const<_Tp>& __pc2) const + _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::propagate_const<_Tp>& __pc1, + const experimental::propagate_const<_Tp>& __pc2) const { - return std::not_equal_to<_Tp>()(_VSTD_LFTS_V2::get_underlying(__pc1), _VSTD_LFTS_V2::get_underlying(__pc2)); + return std::not_equal_to<_Tp>()(experimental::get_underlying(__pc1), experimental::get_underlying(__pc2)); } }; template -struct less> +struct less> { - typedef experimental::fundamentals_v2::propagate_const<_Tp> first_argument_type; - typedef experimental::fundamentals_v2::propagate_const<_Tp> second_argument_type; + typedef experimental::propagate_const<_Tp> first_argument_type; + typedef experimental::propagate_const<_Tp> second_argument_type; - _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::fundamentals_v2::propagate_const<_Tp>& __pc1, - const experimental::fundamentals_v2::propagate_const<_Tp>& __pc2) const + _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::propagate_const<_Tp>& __pc1, + const experimental::propagate_const<_Tp>& __pc2) const { - return std::less<_Tp>()(_VSTD_LFTS_V2::get_underlying(__pc1), _VSTD_LFTS_V2::get_underlying(__pc2)); + return std::less<_Tp>()(experimental::get_underlying(__pc1), experimental::get_underlying(__pc2)); } }; template -struct greater> +struct greater> { - typedef experimental::fundamentals_v2::propagate_const<_Tp> first_argument_type; - typedef experimental::fundamentals_v2::propagate_const<_Tp> second_argument_type; + typedef experimental::propagate_const<_Tp> first_argument_type; + typedef experimental::propagate_const<_Tp> second_argument_type; - _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::fundamentals_v2::propagate_const<_Tp>& __pc1, - const experimental::fundamentals_v2::propagate_const<_Tp>& __pc2) const + _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::propagate_const<_Tp>& __pc1, + const experimental::propagate_const<_Tp>& __pc2) const { - return std::greater<_Tp>()(_VSTD_LFTS_V2::get_underlying(__pc1), _VSTD_LFTS_V2::get_underlying(__pc2)); + return std::greater<_Tp>()(experimental::get_underlying(__pc1), experimental::get_underlying(__pc2)); } }; template -struct less_equal> +struct less_equal> { - typedef experimental::fundamentals_v2::propagate_const<_Tp> first_argument_type; - typedef experimental::fundamentals_v2::propagate_const<_Tp> second_argument_type; + typedef experimental::propagate_const<_Tp> first_argument_type; + typedef experimental::propagate_const<_Tp> second_argument_type; - _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::fundamentals_v2::propagate_const<_Tp>& __pc1, - const experimental::fundamentals_v2::propagate_const<_Tp>& __pc2) const + _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::propagate_const<_Tp>& __pc1, + const experimental::propagate_const<_Tp>& __pc2) const { - return std::less_equal<_Tp>()(_VSTD_LFTS_V2::get_underlying(__pc1), _VSTD_LFTS_V2::get_underlying(__pc2)); + return std::less_equal<_Tp>()(experimental::get_underlying(__pc1), experimental::get_underlying(__pc2)); } }; template -struct greater_equal> +struct greater_equal> { - typedef experimental::fundamentals_v2::propagate_const<_Tp> first_argument_type; - typedef experimental::fundamentals_v2::propagate_const<_Tp> second_argument_type; + typedef experimental::propagate_const<_Tp> first_argument_type; + typedef experimental::propagate_const<_Tp> second_argument_type; - _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::fundamentals_v2::propagate_const<_Tp>& __pc1, - const experimental::fundamentals_v2::propagate_const<_Tp>& __pc2) const + _LIBCPP_HIDE_FROM_ABI bool operator()(const experimental::propagate_const<_Tp>& __pc1, + const experimental::propagate_const<_Tp>& __pc2) const { - return std::greater_equal<_Tp>()(_VSTD_LFTS_V2::get_underlying(__pc1), _VSTD_LFTS_V2::get_underlying(__pc2)); + return std::greater_equal<_Tp>()(experimental::get_underlying(__pc1), experimental::get_underlying(__pc2)); } }; diff --git a/libcxx/include/ext/hash_map b/libcxx/include/ext/hash_map index 2ea56e01ca47..176b59fa9ed6 100644 --- a/libcxx/include/ext/hash_map +++ b/libcxx/include/ext/hash_map @@ -356,9 +356,9 @@ public: void operator()(pointer __p) { if (__second_constructed) - __alloc_traits::destroy(__na_, _VSTD::addressof(__p->__get_value().second)); + __alloc_traits::destroy(__na_, std::addressof(__p->__get_value().second)); if (__first_constructed) - __alloc_traits::destroy(__na_, _VSTD::addressof(__p->__get_value().first)); + __alloc_traits::destroy(__na_, std::addressof(__p->__get_value().first)); if (__p) __alloc_traits::deallocate(__na_, __p, 1); } @@ -666,9 +666,9 @@ hash_map<_Key, _Tp, _Hash, _Pred, _Alloc>::__construct_node(const key_type& __k) { __node_allocator& __na = __table_.__node_alloc(); __node_holder __h(__node_traits::allocate(__na, 1), _Dp(__na)); - __node_traits::construct(__na, _VSTD::addressof(__h->__get_value().first), __k); + __node_traits::construct(__na, std::addressof(__h->__get_value().first), __k); __h.get_deleter().__first_constructed = true; - __node_traits::construct(__na, _VSTD::addressof(__h->__get_value().second)); + __node_traits::construct(__na, std::addressof(__h->__get_value().second)); __h.get_deleter().__second_constructed = true; return __h; } @@ -960,9 +960,9 @@ operator==(const hash_multimap<_Key, _Tp, _Hash, _Pred, _Alloc>& __x, { _EqRng __xeq = __x.equal_range(__i->first); _EqRng __yeq = __y.equal_range(__i->first); - if (_VSTD::distance(__xeq.first, __xeq.second) != - _VSTD::distance(__yeq.first, __yeq.second) || - !_VSTD::is_permutation(__xeq.first, __xeq.second, __yeq.first)) + if (std::distance(__xeq.first, __xeq.second) != + std::distance(__yeq.first, __yeq.second) || + !std::is_permutation(__xeq.first, __xeq.second, __yeq.first)) return false; __i = __xeq.second; } diff --git a/libcxx/include/ext/hash_set b/libcxx/include/ext/hash_set index 53f8c86b2f04..7166aa815ec7 100644 --- a/libcxx/include/ext/hash_set +++ b/libcxx/include/ext/hash_set @@ -642,9 +642,9 @@ operator==(const hash_multiset<_Value, _Hash, _Pred, _Alloc>& __x, { _EqRng __xeq = __x.equal_range(*__i); _EqRng __yeq = __y.equal_range(*__i); - if (_VSTD::distance(__xeq.first, __xeq.second) != - _VSTD::distance(__yeq.first, __yeq.second) || - !_VSTD::is_permutation(__xeq.first, __xeq.second, __yeq.first)) + if (std::distance(__xeq.first, __xeq.second) != + std::distance(__yeq.first, __yeq.second) || + !std::is_permutation(__xeq.first, __xeq.second, __yeq.first)) return false; __i = __xeq.second; } diff --git a/libcxx/include/forward_list b/libcxx/include/forward_list index 29fe3c0b8a1e..b8b793c98545 100644 --- a/libcxx/include/forward_list +++ b/libcxx/include/forward_list @@ -649,7 +649,7 @@ private: _LIBCPP_HIDE_FROM_ABI void __move_assign_alloc(__forward_list_base& __x, true_type) _NOEXCEPT_(is_nothrow_move_assignable<__node_allocator>::value) - {__alloc() = _VSTD::move(__x.__alloc());} + {__alloc() = std::move(__x.__alloc());} }; #ifndef _LIBCPP_CXX03_LANG @@ -658,7 +658,7 @@ template inline __forward_list_base<_Tp, _Alloc>::__forward_list_base(__forward_list_base&& __x) _NOEXCEPT_(is_nothrow_move_constructible<__node_allocator>::value) - : __before_begin_(_VSTD::move(__x.__before_begin_)) + : __before_begin_(std::move(__x.__before_begin_)) { __x.__before_begin()->__next_ = nullptr; } @@ -695,9 +695,9 @@ __forward_list_base<_Tp, _Alloc>::swap(__forward_list_base& __x) __is_nothrow_swappable<__node_allocator>::value) #endif { - _VSTD::__swap_allocator(__alloc(), __x.__alloc(), + std::__swap_allocator(__alloc(), __x.__alloc(), integral_constant()); - using _VSTD::swap; + using std::swap; swap(__before_begin()->__next_, __x.__before_begin()->__next_); } @@ -798,7 +798,7 @@ public: _LIBCPP_HIDE_FROM_ABI forward_list(forward_list&& __x) _NOEXCEPT_(is_nothrow_move_constructible::value) - : base(_VSTD::move(__x)) {} + : base(std::move(__x)) {} _LIBCPP_HIDE_FROM_ABI forward_list(forward_list&& __x, const __type_identity_t& __a); _LIBCPP_HIDE_FROM_ABI forward_list(initializer_list __il); @@ -872,7 +872,7 @@ public: {return base::__before_begin()->__next_ == nullptr;} _LIBCPP_HIDE_FROM_ABI size_type max_size() const _NOEXCEPT { - return _VSTD::min( + return std::min( __node_traits::max_size(base::__alloc()), numeric_limits::max()); } @@ -973,7 +973,7 @@ public: template _LIBCPP_HIDE_FROM_ABI void merge(forward_list&& __x, _Compare __comp) - {merge(__x, _VSTD::move(__comp));} + {merge(__x, std::move(__comp));} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI void merge(forward_list& __x) {merge(__x, __less<>());} @@ -1116,7 +1116,7 @@ template forward_list<_Tp, _Alloc>& forward_list<_Tp, _Alloc>::operator=(const forward_list& __x) { - if (this != _VSTD::addressof(__x)) + if (this != std::addressof(__x)) { base::__copy_assign_alloc(__x); assign(__x.begin(), __x.end()); @@ -1128,7 +1128,7 @@ forward_list<_Tp, _Alloc>::operator=(const forward_list& __x) template forward_list<_Tp, _Alloc>::forward_list(forward_list&& __x, const __type_identity_t& __a) - : base(_VSTD::move(__x), __a) + : base(std::move(__x), __a) { if (base::__alloc() != __x.__alloc()) { @@ -1212,7 +1212,7 @@ template _LIBCPP_HIDE_FROM_ABI void forward_list<_Tp, _Alloc>::__assign_with_sentinel(_Iter __f, _Sent __l) { iterator __i = before_begin(); - iterator __j = _VSTD::next(__i); + iterator __j = std::next(__i); iterator __e = end(); for (; __j != __e && __f != __l; ++__i, (void) ++__j, ++__f) *__j = *__f; @@ -1227,7 +1227,7 @@ void forward_list<_Tp, _Alloc>::assign(size_type __n, const value_type& __v) { iterator __i = before_begin(); - iterator __j = _VSTD::next(__i); + iterator __j = std::next(__i); iterator __e = end(); for (; __j != __e && __n > 0; --__n, ++__i, ++__j) *__j = __v; @@ -1520,7 +1520,7 @@ forward_list<_Tp, _Alloc>::splice_after(const_iterator __p, forward_list& /*__other*/, const_iterator __i) { - const_iterator __lm1 = _VSTD::next(__i); + const_iterator __lm1 = std::next(__i); if (__p != __i && __p != __lm1) { __i.__get_begin()->__next_ = __lm1.__get_begin()->__next_; @@ -1590,7 +1590,7 @@ forward_list<_Tp, _Alloc>::remove(const value_type& __v) if (__i.__get_begin()->__next_->__get_value() == __v) { ++__count_removed; - iterator __j = _VSTD::next(__i, 2); + iterator __j = std::next(__i, 2); for (; __j != __e && *__j == __v; ++__j) ++__count_removed; __deleted_nodes.splice_after(__deleted_nodes.before_begin(), *this, __i, __j); @@ -1618,7 +1618,7 @@ forward_list<_Tp, _Alloc>::remove_if(_Predicate __pred) if (__pred(__i.__get_begin()->__next_->__get_value())) { ++__count_removed; - iterator __j = _VSTD::next(__i, 2); + iterator __j = std::next(__i, 2); for (; __j != __e && __pred(*__j); ++__j) ++__count_removed; __deleted_nodes.splice_after(__deleted_nodes.before_begin(), *this, __i, __j); @@ -1642,7 +1642,7 @@ forward_list<_Tp, _Alloc>::unique(_BinaryPredicate __binary_pred) typename forward_list<_Tp, _Alloc>::size_type __count_removed = 0; for (iterator __i = begin(), __e = end(); __i != __e;) { - iterator __j = _VSTD::next(__i); + iterator __j = std::next(__i); for (; __j != __e && __binary_pred(*__i, *__j); ++__j) ++__count_removed; if (__i.__get_begin()->__next_ != __j.__get_unsafe_node_pointer()) @@ -1658,7 +1658,7 @@ template void forward_list<_Tp, _Alloc>::merge(forward_list& __x, _Compare __comp) { - if (this != _VSTD::addressof(__x)) + if (this != std::addressof(__x)) { base::__before_begin()->__next_ = __merge(base::__before_begin()->__next_, __x.__before_begin()->__next_, @@ -1719,7 +1719,7 @@ void forward_list<_Tp, _Alloc>::sort(_Compare __comp) { base::__before_begin()->__next_ = __sort(base::__before_begin()->__next_, - _VSTD::distance(begin(), end()), __comp); + std::distance(begin(), end()), __comp); } template @@ -1745,7 +1745,7 @@ forward_list<_Tp, _Alloc>::__sort(__node_pointer __f1, difference_type __sz, } difference_type __sz1 = __sz / 2; difference_type __sz2 = __sz - __sz1; - __node_pointer __t = _VSTD::next(iterator(__f1), __sz1 - 1).__get_unsafe_node_pointer(); + __node_pointer __t = std::next(iterator(__f1), __sz1 - 1).__get_unsafe_node_pointer(); __node_pointer __f2 = __t->__next_; __t->__next_ = nullptr; return __merge(__sort(__f1, __sz1, __comp), @@ -1804,7 +1804,7 @@ inline _LIBCPP_HIDE_FROM_ABI bool operator< (const forward_list<_Tp, _Alloc>& __x, const forward_list<_Tp, _Alloc>& __y) { - return _VSTD::lexicographical_compare(__x.begin(), __x.end(), + return std::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); } @@ -1864,7 +1864,7 @@ template inline _LIBCPP_HIDE_FROM_ABI typename forward_list<_Tp, _Allocator>::size_type erase(forward_list<_Tp, _Allocator>& __c, const _Up& __v) { - return _VSTD::erase_if(__c, [&](auto& __elem) { return __elem == __v; }); + return std::erase_if(__c, [&](auto& __elem) { return __elem == __v; }); } #endif diff --git a/libcxx/include/fstream b/libcxx/include/fstream index 4618c4956270..468ff42dc9bc 100644 --- a/libcxx/include/fstream +++ b/libcxx/include/fstream @@ -456,18 +456,18 @@ basic_filebuf<_CharT, _Traits>::swap(basic_filebuf& __rhs) __rhs.__extbufnext_ = __rhs.__extbuf_ + __ln; __rhs.__extbufend_ = __rhs.__extbuf_ + __le; } - _VSTD::swap(__ebs_, __rhs.__ebs_); - _VSTD::swap(__intbuf_, __rhs.__intbuf_); - _VSTD::swap(__ibs_, __rhs.__ibs_); - _VSTD::swap(__file_, __rhs.__file_); - _VSTD::swap(__cv_, __rhs.__cv_); - _VSTD::swap(__st_, __rhs.__st_); - _VSTD::swap(__st_last_, __rhs.__st_last_); - _VSTD::swap(__om_, __rhs.__om_); - _VSTD::swap(__cm_, __rhs.__cm_); - _VSTD::swap(__owns_eb_, __rhs.__owns_eb_); - _VSTD::swap(__owns_ib_, __rhs.__owns_ib_); - _VSTD::swap(__always_noconv_, __rhs.__always_noconv_); + std::swap(__ebs_, __rhs.__ebs_); + std::swap(__intbuf_, __rhs.__intbuf_); + std::swap(__ibs_, __rhs.__ibs_); + std::swap(__file_, __rhs.__file_); + std::swap(__cv_, __rhs.__cv_); + std::swap(__st_, __rhs.__st_); + std::swap(__st_last_, __rhs.__st_last_); + std::swap(__om_, __rhs.__om_); + std::swap(__cm_, __rhs.__cm_); + std::swap(__owns_eb_, __rhs.__owns_eb_); + std::swap(__owns_ib_, __rhs.__owns_ib_); + std::swap(__always_noconv_, __rhs.__always_noconv_); if (this->eback() == (char_type*)__rhs.__extbuf_min_) { ptrdiff_t __n = this->gptr() - this->eback(); @@ -762,7 +762,7 @@ basic_filebuf<_CharT, _Traits>::underflow() int_type __c = traits_type::eof(); if (this->gptr() == this->egptr()) { - _VSTD::memmove(this->eback(), this->egptr() - __unget_sz, __unget_sz * sizeof(char_type)); + std::memmove(this->eback(), this->egptr() - __unget_sz, __unget_sz * sizeof(char_type)); if (__always_noconv_) { size_t __nmemb = static_cast(this->egptr() - this->eback() - __unget_sz); @@ -780,11 +780,11 @@ basic_filebuf<_CharT, _Traits>::underflow() if (__extbufend_ != __extbufnext_) { _LIBCPP_ASSERT_NON_NULL(__extbufnext_ != nullptr, "underflow moving from nullptr"); _LIBCPP_ASSERT_NON_NULL(__extbuf_ != nullptr, "underflow moving into nullptr"); - _VSTD::memmove(__extbuf_, __extbufnext_, __extbufend_ - __extbufnext_); + std::memmove(__extbuf_, __extbufnext_, __extbufend_ - __extbufnext_); } __extbufnext_ = __extbuf_ + (__extbufend_ - __extbufnext_); __extbufend_ = __extbuf_ + (__extbuf_ == __extbuf_min_ ? sizeof(__extbuf_min_) : __ebs_); - size_t __nmemb = _VSTD::min(static_cast(__ibs_ - __unget_sz), + size_t __nmemb = std::min(static_cast(__ibs_ - __unget_sz), static_cast(__extbufend_ - __extbufnext_)); codecvt_base::result __r; __st_last_ = __st_; @@ -1270,8 +1270,8 @@ basic_ifstream<_CharT, _Traits>::basic_ifstream(const string& __s, ios_base::ope template inline basic_ifstream<_CharT, _Traits>::basic_ifstream(basic_ifstream&& __rhs) - : basic_istream(_VSTD::move(__rhs)), - __sb_(_VSTD::move(__rhs.__sb_)) + : basic_istream(std::move(__rhs)), + __sb_(std::move(__rhs.__sb_)) { this->set_rdbuf(&__sb_); } @@ -1281,8 +1281,8 @@ inline basic_ifstream<_CharT, _Traits>& basic_ifstream<_CharT, _Traits>::operator=(basic_ifstream&& __rhs) { - basic_istream::operator=(_VSTD::move(__rhs)); - __sb_ = _VSTD::move(__rhs.__sb_); + basic_istream::operator=(std::move(__rhs)); + __sb_ = std::move(__rhs.__sb_); return *this; } @@ -1471,8 +1471,8 @@ basic_ofstream<_CharT, _Traits>::basic_ofstream(const string& __s, ios_base::ope template inline basic_ofstream<_CharT, _Traits>::basic_ofstream(basic_ofstream&& __rhs) - : basic_ostream(_VSTD::move(__rhs)), - __sb_(_VSTD::move(__rhs.__sb_)) + : basic_ostream(std::move(__rhs)), + __sb_(std::move(__rhs.__sb_)) { this->set_rdbuf(&__sb_); } @@ -1482,8 +1482,8 @@ inline basic_ofstream<_CharT, _Traits>& basic_ofstream<_CharT, _Traits>::operator=(basic_ofstream&& __rhs) { - basic_ostream::operator=(_VSTD::move(__rhs)); - __sb_ = _VSTD::move(__rhs.__sb_); + basic_ostream::operator=(std::move(__rhs)); + __sb_ = std::move(__rhs.__sb_); return *this; } @@ -1672,8 +1672,8 @@ basic_fstream<_CharT, _Traits>::basic_fstream(const string& __s, ios_base::openm template inline basic_fstream<_CharT, _Traits>::basic_fstream(basic_fstream&& __rhs) - : basic_iostream(_VSTD::move(__rhs)), - __sb_(_VSTD::move(__rhs.__sb_)) + : basic_iostream(std::move(__rhs)), + __sb_(std::move(__rhs.__sb_)) { this->set_rdbuf(&__sb_); } @@ -1683,8 +1683,8 @@ inline basic_fstream<_CharT, _Traits>& basic_fstream<_CharT, _Traits>::operator=(basic_fstream&& __rhs) { - basic_iostream::operator=(_VSTD::move(__rhs)); - __sb_ = _VSTD::move(__rhs.__sb_); + basic_iostream::operator=(std::move(__rhs)); + __sb_ = std::move(__rhs.__sb_); return *this; } diff --git a/libcxx/include/future b/libcxx/include/future index 8e889c037615..ab645b7d3dcb 100644 --- a/libcxx/include/future +++ b/libcxx/include/future @@ -673,7 +673,7 @@ __assoc_state<_Rp>::set_value(_Arg&& __arg) unique_lock __lk(this->__mut_); if (this->__has_value()) __throw_future_error(future_errc::promise_already_satisfied); - ::new ((void*)&__value_) _Rp(_VSTD::forward<_Arg>(__arg)); + ::new ((void*)&__value_) _Rp(std::forward<_Arg>(__arg)); this->__state_ |= base::__constructed | base::ready; __cv_.notify_all(); } @@ -686,7 +686,7 @@ __assoc_state<_Rp>::set_value_at_thread_exit(_Arg&& __arg) unique_lock __lk(this->__mut_); if (this->__has_value()) __throw_future_error(future_errc::promise_already_satisfied); - ::new ((void*)&__value_) _Rp(_VSTD::forward<_Arg>(__arg)); + ::new ((void*)&__value_) _Rp(std::forward<_Arg>(__arg)); this->__state_ |= base::__constructed; __thread_local_data()->__make_ready_at_thread_exit(this); } @@ -699,7 +699,7 @@ __assoc_state<_Rp>::move() this->__sub_wait(__lk); if (this->__exception_ != nullptr) std::rethrow_exception(this->__exception_); - return _VSTD::move(*reinterpret_cast<_Rp*>(&__value_)); + return std::move(*reinterpret_cast<_Rp*>(&__value_)); } template @@ -744,7 +744,7 @@ __assoc_state<_Rp&>::set_value(_Rp& __arg) unique_lock __lk(this->__mut_); if (this->__has_value()) __throw_future_error(future_errc::promise_already_satisfied); - __value_ = _VSTD::addressof(__arg); + __value_ = std::addressof(__arg); this->__state_ |= base::__constructed | base::ready; __cv_.notify_all(); } @@ -756,7 +756,7 @@ __assoc_state<_Rp&>::set_value_at_thread_exit(_Rp& __arg) unique_lock __lk(this->__mut_); if (this->__has_value()) __throw_future_error(future_errc::promise_already_satisfied); - __value_ = _VSTD::addressof(__arg); + __value_ = std::addressof(__arg); this->__state_ |= base::__constructed; __thread_local_data()->__make_ready_at_thread_exit(this); } @@ -790,7 +790,7 @@ void __assoc_state_alloc<_Rp, _Alloc>::__on_zero_shared() _NOEXCEPT { if (this->__state_ & base::__constructed) - reinterpret_cast<_Rp*>(_VSTD::addressof(this->__value_))->~_Rp(); + reinterpret_cast<_Rp*>(std::addressof(this->__value_))->~_Rp(); typedef typename __allocator_traits_rebind<_Alloc, __assoc_state_alloc>::type _Al; typedef allocator_traits<_Al> _ATraits; typedef pointer_traits _PTraits; @@ -866,7 +866,7 @@ public: template inline __deferred_assoc_state<_Rp, _Fp>::__deferred_assoc_state(_Fp&& __f) - : __func_(_VSTD::forward<_Fp>(__f)) + : __func_(std::forward<_Fp>(__f)) { this->__set_deferred(); } @@ -906,7 +906,7 @@ public: template inline __deferred_assoc_state::__deferred_assoc_state(_Fp&& __f) - : __func_(_VSTD::forward<_Fp>(__f)) + : __func_(std::forward<_Fp>(__f)) { this->__set_deferred(); } @@ -948,7 +948,7 @@ public: template inline __async_assoc_state<_Rp, _Fp>::__async_assoc_state(_Fp&& __f) - : __func_(_VSTD::forward<_Fp>(__f)) + : __func_(std::forward<_Fp>(__f)) { } @@ -996,7 +996,7 @@ public: template inline __async_assoc_state::__async_assoc_state(_Fp&& __f) - : __func_(_VSTD::forward<_Fp>(__f)) + : __func_(std::forward<_Fp>(__f)) { } @@ -1068,7 +1068,7 @@ public: _LIBCPP_HIDE_FROM_ABI future& operator=(future&& __rhs) _NOEXCEPT { - future(_VSTD::move(__rhs)).swap(*this); + future(std::move(__rhs)).swap(*this); return *this; } @@ -1080,7 +1080,7 @@ public: _LIBCPP_HIDE_FROM_ABI _Rp get(); _LIBCPP_HIDE_FROM_ABI - void swap(future& __rhs) _NOEXCEPT {_VSTD::swap(__state_, __rhs.__state_);} + void swap(future& __rhs) _NOEXCEPT {std::swap(__state_, __rhs.__state_);} // functions to check state _LIBCPP_HIDE_FROM_ABI @@ -1155,7 +1155,7 @@ public: _LIBCPP_HIDE_FROM_ABI future& operator=(future&& __rhs) _NOEXCEPT { - future(_VSTD::move(__rhs)).swap(*this); + future(std::move(__rhs)).swap(*this); return *this; } @@ -1167,7 +1167,7 @@ public: _LIBCPP_HIDE_FROM_ABI _Rp& get(); _LIBCPP_HIDE_FROM_ABI - void swap(future& __rhs) _NOEXCEPT {_VSTD::swap(__state_, __rhs.__state_);} + void swap(future& __rhs) _NOEXCEPT {std::swap(__state_, __rhs.__state_);} // functions to check state _LIBCPP_HIDE_FROM_ABI @@ -1237,7 +1237,7 @@ public: _LIBCPP_HIDE_FROM_ABI future& operator=(future&& __rhs) _NOEXCEPT { - future(_VSTD::move(__rhs)).swap(*this); + future(std::move(__rhs)).swap(*this); return *this; } @@ -1249,7 +1249,7 @@ public: void get(); _LIBCPP_HIDE_FROM_ABI - void swap(future& __rhs) _NOEXCEPT {_VSTD::swap(__state_, __rhs.__state_);} + void swap(future& __rhs) _NOEXCEPT {std::swap(__state_, __rhs.__state_);} // functions to check state _LIBCPP_HIDE_FROM_ABI @@ -1304,13 +1304,13 @@ public: _LIBCPP_HIDE_FROM_ABI promise& operator=(promise&& __rhs) _NOEXCEPT { - promise(_VSTD::move(__rhs)).swap(*this); + promise(std::move(__rhs)).swap(*this); return *this; } promise& operator=(const promise& __rhs) = delete; _LIBCPP_HIDE_FROM_ABI - void swap(promise& __rhs) _NOEXCEPT {_VSTD::swap(__state_, __rhs.__state_);} + void swap(promise& __rhs) _NOEXCEPT {std::swap(__state_, __rhs.__state_);} // retrieving the result _LIBCPP_HIDE_FROM_ABI future<_Rp> get_future(); @@ -1341,8 +1341,8 @@ promise<_Rp>::promise(allocator_arg_t, const _Alloc& __a0) typedef __allocator_destructor<_A2> _D2; _A2 __a(__a0); unique_ptr<_State, _D2> __hold(__a.allocate(1), _D2(__a, 1)); - ::new ((void*)_VSTD::addressof(*__hold.get())) _State(__a0); - __state_ = _VSTD::addressof(*__hold.release()); + ::new ((void*)std::addressof(*__hold.get())) _State(__a0); + __state_ = std::addressof(*__hold.release()); } template @@ -1380,7 +1380,7 @@ promise<_Rp>::set_value(_Rp&& __r) { if (__state_ == nullptr) __throw_future_error(future_errc::no_state); - __state_->set_value(_VSTD::move(__r)); + __state_->set_value(std::move(__r)); } template @@ -1408,7 +1408,7 @@ promise<_Rp>::set_value_at_thread_exit(_Rp&& __r) { if (__state_ == nullptr) __throw_future_error(future_errc::no_state); - __state_->set_value_at_thread_exit(_VSTD::move(__r)); + __state_->set_value_at_thread_exit(std::move(__r)); } template @@ -1447,13 +1447,13 @@ public: _LIBCPP_HIDE_FROM_ABI promise& operator=(promise&& __rhs) _NOEXCEPT { - promise(_VSTD::move(__rhs)).swap(*this); + promise(std::move(__rhs)).swap(*this); return *this; } promise& operator=(const promise& __rhs) = delete; _LIBCPP_HIDE_FROM_ABI - void swap(promise& __rhs) _NOEXCEPT {_VSTD::swap(__state_, __rhs.__state_);} + void swap(promise& __rhs) _NOEXCEPT {std::swap(__state_, __rhs.__state_);} // retrieving the result _LIBCPP_HIDE_FROM_ABI future<_Rp&> get_future(); @@ -1482,8 +1482,8 @@ promise<_Rp&>::promise(allocator_arg_t, const _Alloc& __a0) typedef __allocator_destructor<_A2> _D2; _A2 __a(__a0); unique_ptr<_State, _D2> __hold(__a.allocate(1), _D2(__a, 1)); - ::new ((void*)_VSTD::addressof(*__hold.get())) _State(__a0); - __state_ = _VSTD::addressof(*__hold.release()); + ::new ((void*)std::addressof(*__hold.get())) _State(__a0); + __state_ = std::addressof(*__hold.release()); } template @@ -1571,13 +1571,13 @@ public: _LIBCPP_HIDE_FROM_ABI promise& operator=(promise&& __rhs) _NOEXCEPT { - promise(_VSTD::move(__rhs)).swap(*this); + promise(std::move(__rhs)).swap(*this); return *this; } promise& operator=(const promise& __rhs) = delete; _LIBCPP_HIDE_FROM_ABI - void swap(promise& __rhs) _NOEXCEPT {_VSTD::swap(__state_, __rhs.__state_);} + void swap(promise& __rhs) _NOEXCEPT {std::swap(__state_, __rhs.__state_);} // retrieving the result future get_future(); @@ -1599,8 +1599,8 @@ promise::promise(allocator_arg_t, const _Alloc& __a0) typedef __allocator_destructor<_A2> _D2; _A2 __a(__a0); unique_ptr<_State, _D2> __hold(__a.allocate(1), _D2(__a, 1)); - ::new ((void*)_VSTD::addressof(*__hold.get())) _State(__a0); - __state_ = _VSTD::addressof(*__hold.release()); + ::new ((void*)std::addressof(*__hold.get())) _State(__a0); + __state_ = std::addressof(*__hold.release()); } template @@ -1645,13 +1645,13 @@ public: _LIBCPP_HIDE_FROM_ABI explicit __packaged_task_func(const _Fp& __f) : __f_(__f, __default_init_tag()) {} _LIBCPP_HIDE_FROM_ABI - explicit __packaged_task_func(_Fp&& __f) : __f_(_VSTD::move(__f), __default_init_tag()) {} + explicit __packaged_task_func(_Fp&& __f) : __f_(std::move(__f), __default_init_tag()) {} _LIBCPP_HIDE_FROM_ABI __packaged_task_func(const _Fp& __f, const _Alloc& __a) : __f_(__f, __a) {} _LIBCPP_HIDE_FROM_ABI __packaged_task_func(_Fp&& __f, const _Alloc& __a) - : __f_(_VSTD::move(__f), __a) {} + : __f_(std::move(__f), __a) {} _LIBCPP_HIDE_FROM_ABI_VIRTUAL virtual void __move_to(__packaged_task_base<_Rp(_ArgTypes...)>*) _NOEXCEPT; _LIBCPP_HIDE_FROM_ABI_VIRTUAL virtual void destroy(); _LIBCPP_HIDE_FROM_ABI_VIRTUAL virtual void destroy_deallocate(); @@ -1663,7 +1663,7 @@ void __packaged_task_func<_Fp, _Alloc, _Rp(_ArgTypes...)>::__move_to( __packaged_task_base<_Rp(_ArgTypes...)>* __p) _NOEXCEPT { - ::new ((void*)__p) __packaged_task_func(_VSTD::move(__f_.first()), _VSTD::move(__f_.second())); + ::new ((void*)__p) __packaged_task_func(std::move(__f_.first()), std::move(__f_.second())); } template @@ -1689,7 +1689,7 @@ template _Rp __packaged_task_func<_Fp, _Alloc, _Rp(_ArgTypes...)>::operator()(_ArgTypes&& ... __arg) { - return _VSTD::__invoke(__f_.first(), _VSTD::forward<_ArgTypes>(__arg)...); + return std::__invoke(__f_.first(), std::forward<_ArgTypes>(__arg)...); } template class __packaged_task_function; @@ -1758,7 +1758,7 @@ __packaged_task_function<_Rp(_ArgTypes...)>::__packaged_task_function(_Fp&& __f) typedef __packaged_task_func<_FR, allocator<_FR>, _Rp(_ArgTypes...)> _FF; if (sizeof(_FF) <= sizeof(__buf_)) { - ::new ((void*)&__buf_) _FF(_VSTD::forward<_Fp>(__f)); + ::new ((void*)&__buf_) _FF(std::forward<_Fp>(__f)); __f_ = (__base*)&__buf_; } else @@ -1767,7 +1767,7 @@ __packaged_task_function<_Rp(_ArgTypes...)>::__packaged_task_function(_Fp&& __f) _Ap __a; typedef __allocator_destructor<_Ap> _Dp; unique_ptr<__base, _Dp> __hold(__a.allocate(1), _Dp(__a, 1)); - ::new ((void*)__hold.get()) _FF(_VSTD::forward<_Fp>(__f), allocator<_FR>(__a)); + ::new ((void*)__hold.get()) _FF(std::forward<_Fp>(__f), allocator<_FR>(__a)); __f_ = __hold.release(); } } @@ -1783,7 +1783,7 @@ __packaged_task_function<_Rp(_ArgTypes...)>::__packaged_task_function( if (sizeof(_FF) <= sizeof(__buf_)) { __f_ = (__base*)&__buf_; - ::new ((void*)__f_) _FF(_VSTD::forward<_Fp>(__f)); + ::new ((void*)__f_) _FF(std::forward<_Fp>(__f)); } else { @@ -1791,9 +1791,9 @@ __packaged_task_function<_Rp(_ArgTypes...)>::__packaged_task_function( _Ap __a(__a0); typedef __allocator_destructor<_Ap> _Dp; unique_ptr<__base, _Dp> __hold(__a.allocate(1), _Dp(__a, 1)); - ::new ((void*)_VSTD::addressof(*__hold.get())) - _FF(_VSTD::forward<_Fp>(__f), _Alloc(__a)); - __f_ = _VSTD::addressof(*__hold.release()); + ::new ((void*)std::addressof(*__hold.get())) + _FF(std::forward<_Fp>(__f), _Alloc(__a)); + __f_ = std::addressof(*__hold.release()); } } @@ -1867,7 +1867,7 @@ __packaged_task_function<_Rp(_ArgTypes...)>::swap(__packaged_task_function& __f) __f_ = (__base*)&__buf_; } else - _VSTD::swap(__f_, __f.__f_); + std::swap(__f_, __f.__f_); } template @@ -1875,7 +1875,7 @@ inline _Rp __packaged_task_function<_Rp(_ArgTypes...)>::operator()(_ArgTypes... __arg) const { - return (*__f_)(_VSTD::forward<_ArgTypes>(__arg)...); + return (*__f_)(std::forward<_ArgTypes>(__arg)...); } template @@ -1895,12 +1895,12 @@ public: template , packaged_task>::value> > _LIBCPP_HIDE_FROM_ABI - explicit packaged_task(_Fp&& __f) : __f_(_VSTD::forward<_Fp>(__f)) {} + explicit packaged_task(_Fp&& __f) : __f_(std::forward<_Fp>(__f)) {} template , packaged_task>::value> > _LIBCPP_HIDE_FROM_ABI packaged_task(allocator_arg_t, const _Allocator& __a, _Fp&& __f) - : __f_(allocator_arg_t(), __a, _VSTD::forward<_Fp>(__f)), + : __f_(allocator_arg_t(), __a, std::forward<_Fp>(__f)), __p_(allocator_arg_t(), __a) {} // ~packaged_task() = default; @@ -1911,12 +1911,12 @@ public: // move support _LIBCPP_HIDE_FROM_ABI packaged_task(packaged_task&& __other) _NOEXCEPT - : __f_(_VSTD::move(__other.__f_)), __p_(_VSTD::move(__other.__p_)) {} + : __f_(std::move(__other.__f_)), __p_(std::move(__other.__p_)) {} _LIBCPP_HIDE_FROM_ABI packaged_task& operator=(packaged_task&& __other) _NOEXCEPT { - __f_ = _VSTD::move(__other.__f_); - __p_ = _VSTD::move(__other.__p_); + __f_ = std::move(__other.__f_); + __p_ = std::move(__other.__p_); return *this; } _LIBCPP_HIDE_FROM_ABI @@ -1952,7 +1952,7 @@ packaged_task<_Rp(_ArgTypes...)>::operator()(_ArgTypes... __args) try { #endif // _LIBCPP_HAS_NO_EXCEPTIONS - __p_.set_value(__f_(_VSTD::forward<_ArgTypes>(__args)...)); + __p_.set_value(__f_(std::forward<_ArgTypes>(__args)...)); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) @@ -1974,7 +1974,7 @@ packaged_task<_Rp(_ArgTypes...)>::make_ready_at_thread_exit(_ArgTypes... __args) try { #endif // _LIBCPP_HAS_NO_EXCEPTIONS - __p_.set_value_at_thread_exit(__f_(_VSTD::forward<_ArgTypes>(__args)...)); + __p_.set_value_at_thread_exit(__f_(std::forward<_ArgTypes>(__args)...)); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) @@ -2010,12 +2010,12 @@ public: template , packaged_task>::value> > _LIBCPP_HIDE_FROM_ABI - explicit packaged_task(_Fp&& __f) : __f_(_VSTD::forward<_Fp>(__f)) {} + explicit packaged_task(_Fp&& __f) : __f_(std::forward<_Fp>(__f)) {} template , packaged_task>::value> > _LIBCPP_HIDE_FROM_ABI packaged_task(allocator_arg_t, const _Allocator& __a, _Fp&& __f) - : __f_(allocator_arg_t(), __a, _VSTD::forward<_Fp>(__f)), + : __f_(allocator_arg_t(), __a, std::forward<_Fp>(__f)), __p_(allocator_arg_t(), __a) {} // ~packaged_task() = default; @@ -2026,12 +2026,12 @@ public: // move support _LIBCPP_HIDE_FROM_ABI packaged_task(packaged_task&& __other) _NOEXCEPT - : __f_(_VSTD::move(__other.__f_)), __p_(_VSTD::move(__other.__p_)) {} + : __f_(std::move(__other.__f_)), __p_(std::move(__other.__p_)) {} _LIBCPP_HIDE_FROM_ABI packaged_task& operator=(packaged_task&& __other) _NOEXCEPT { - __f_ = _VSTD::move(__other.__f_); - __p_ = _VSTD::move(__other.__p_); + __f_ = std::move(__other.__f_); + __p_ = std::move(__other.__p_); return *this; } _LIBCPP_HIDE_FROM_ABI @@ -2077,7 +2077,7 @@ packaged_task::operator()(_ArgTypes... __args) try { #endif // _LIBCPP_HAS_NO_EXCEPTIONS - __f_(_VSTD::forward<_ArgTypes>(__args)...); + __f_(std::forward<_ArgTypes>(__args)...); __p_.set_value(); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } @@ -2100,7 +2100,7 @@ packaged_task::make_ready_at_thread_exit(_ArgTypes... __args try { #endif // _LIBCPP_HAS_NO_EXCEPTIONS - __f_(_VSTD::forward<_ArgTypes>(__args)...); + __f_(std::forward<_ArgTypes>(__args)...); __p_.set_value_at_thread_exit(); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } @@ -2137,7 +2137,7 @@ _LIBCPP_HIDE_FROM_ABI future<_Rp> __make_deferred_assoc_state(_Fp&& __f) { unique_ptr<__deferred_assoc_state<_Rp, _Fp>, __release_shared_count> - __h(new __deferred_assoc_state<_Rp, _Fp>(_VSTD::forward<_Fp>(__f))); + __h(new __deferred_assoc_state<_Rp, _Fp>(std::forward<_Fp>(__f))); return future<_Rp>(__h.get()); } @@ -2146,8 +2146,8 @@ _LIBCPP_HIDE_FROM_ABI future<_Rp> __make_async_assoc_state(_Fp&& __f) { unique_ptr<__async_assoc_state<_Rp, _Fp>, __release_shared_count> - __h(new __async_assoc_state<_Rp, _Fp>(_VSTD::forward<_Fp>(__f))); - _VSTD::thread(&__async_assoc_state<_Rp, _Fp>::__execute, __h.get()).detach(); + __h(new __async_assoc_state<_Rp, _Fp>(std::forward<_Fp>(__f))); + std::thread(&__async_assoc_state<_Rp, _Fp>::__execute, __h.get()).detach(); return future<_Rp>(__h.get()); } @@ -2163,10 +2163,10 @@ public: _LIBCPP_HIDE_FROM_ABI explicit __async_func(_Fp&& __f, _Args&&... __args) - : __f_(_VSTD::move(__f), _VSTD::move(__args)...) {} + : __f_(std::move(__f), std::move(__args)...) {} _LIBCPP_HIDE_FROM_ABI - __async_func(__async_func&& __f) : __f_(_VSTD::move(__f.__f_)) {} + __async_func(__async_func&& __f) : __f_(std::move(__f.__f_)) {} _LIBCPP_HIDE_FROM_ABI _Rp operator()() { @@ -2178,7 +2178,7 @@ private: _LIBCPP_HIDE_FROM_ABI _Rp __execute(__tuple_indices<_Indices...>) { - return _VSTD::__invoke(_VSTD::move(_VSTD::get<0>(__f_)), _VSTD::move(_VSTD::get<_Indices>(__f_))...); + return std::__invoke(std::move(std::get<0>(__f_)), std::move(std::get<_Indices>(__f_))...); } }; @@ -2198,16 +2198,16 @@ async(launch __policy, _Fp&& __f, _Args&&... __args) { #endif if (__does_policy_contain(__policy, launch::async)) - return _VSTD::__make_async_assoc_state<_Rp>(_BF(_LIBCPP_AUTO_CAST(_VSTD::forward<_Fp>(__f)), - _LIBCPP_AUTO_CAST(_VSTD::forward<_Args>(__args))...)); + return std::__make_async_assoc_state<_Rp>(_BF(_LIBCPP_AUTO_CAST(std::forward<_Fp>(__f)), + _LIBCPP_AUTO_CAST(std::forward<_Args>(__args))...)); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch ( ... ) { if (__policy == launch::async) throw ; } #endif if (__does_policy_contain(__policy, launch::deferred)) - return _VSTD::__make_deferred_assoc_state<_Rp>(_BF(_LIBCPP_AUTO_CAST(_VSTD::forward<_Fp>(__f)), - _LIBCPP_AUTO_CAST(_VSTD::forward<_Args>(__args))...)); + return std::__make_deferred_assoc_state<_Rp>(_BF(_LIBCPP_AUTO_CAST(std::forward<_Fp>(__f)), + _LIBCPP_AUTO_CAST(std::forward<_Args>(__args))...)); return future<_Rp>{}; } @@ -2216,8 +2216,8 @@ _LIBCPP_NODISCARD_AFTER_CXX17 inline _LIBCPP_HIDE_FROM_ABI future, __decay_t<_Args>...>::type> async(_Fp&& __f, _Args&&... __args) { - return _VSTD::async(launch::any, _VSTD::forward<_Fp>(__f), - _VSTD::forward<_Args>(__args)...); + return std::async(launch::any, std::forward<_Fp>(__f), + std::forward<_Args>(__args)...); } #endif // C++03 @@ -2246,7 +2246,7 @@ public: _LIBCPP_HIDE_FROM_ABI shared_future& operator=(shared_future&& __rhs) _NOEXCEPT { - shared_future(_VSTD::move(__rhs)).swap(*this); + shared_future(std::move(__rhs)).swap(*this); return *this; } @@ -2255,7 +2255,7 @@ public: const _Rp& get() const {return __state_->copy();} _LIBCPP_HIDE_FROM_ABI - void swap(shared_future& __rhs) _NOEXCEPT {_VSTD::swap(__state_, __rhs.__state_);} + void swap(shared_future& __rhs) _NOEXCEPT {std::swap(__state_, __rhs.__state_);} // functions to check state _LIBCPP_HIDE_FROM_ABI @@ -2316,7 +2316,7 @@ public: _LIBCPP_HIDE_FROM_ABI shared_future& operator=(shared_future&& __rhs) _NOEXCEPT { - shared_future(_VSTD::move(__rhs)).swap(*this); + shared_future(std::move(__rhs)).swap(*this); return *this; } @@ -2325,7 +2325,7 @@ public: _Rp& get() const {return __state_->copy();} _LIBCPP_HIDE_FROM_ABI - void swap(shared_future& __rhs) _NOEXCEPT {_VSTD::swap(__state_, __rhs.__state_);} + void swap(shared_future& __rhs) _NOEXCEPT {std::swap(__state_, __rhs.__state_);} // functions to check state _LIBCPP_HIDE_FROM_ABI @@ -2386,7 +2386,7 @@ public: _LIBCPP_HIDE_FROM_ABI shared_future& operator=(shared_future&& __rhs) _NOEXCEPT { - shared_future(_VSTD::move(__rhs)).swap(*this); + shared_future(std::move(__rhs)).swap(*this); return *this; } @@ -2395,7 +2395,7 @@ public: void get() const {__state_->copy();} _LIBCPP_HIDE_FROM_ABI - void swap(shared_future& __rhs) _NOEXCEPT {_VSTD::swap(__state_, __rhs.__state_);} + void swap(shared_future& __rhs) _NOEXCEPT {std::swap(__state_, __rhs.__state_);} // functions to check state _LIBCPP_HIDE_FROM_ABI @@ -2428,7 +2428,7 @@ inline shared_future<_Rp> future<_Rp>::share() _NOEXCEPT { - return shared_future<_Rp>(_VSTD::move(*this)); + return shared_future<_Rp>(std::move(*this)); } template @@ -2436,14 +2436,14 @@ inline shared_future<_Rp&> future<_Rp&>::share() _NOEXCEPT { - return shared_future<_Rp&>(_VSTD::move(*this)); + return shared_future<_Rp&>(std::move(*this)); } inline shared_future future::share() _NOEXCEPT { - return shared_future(_VSTD::move(*this)); + return shared_future(std::move(*this)); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/iomanip b/libcxx/include/iomanip index da2708452ba3..157d974c6356 100644 --- a/libcxx/include/iomanip +++ b/libcxx/include/iomanip @@ -526,7 +526,7 @@ __quoted_output(basic_ostream<_CharT, _Traits>& __os, __str.push_back(*__first); } __str.push_back(__delim); - return _VSTD::__put_character_sequence(__os, __str.data(), __str.size()); + return std::__put_character_sequence(__os, __str.data(), __str.size()); } template diff --git a/libcxx/include/ios b/libcxx/include/ios index bd8e22bcd321..63abebcded3c 100644 --- a/libcxx/include/ios +++ b/libcxx/include/ios @@ -295,8 +295,8 @@ public: typedef openmode open_mode; typedef seekdir seek_dir; - typedef _VSTD::streamoff streamoff; - typedef _VSTD::streampos streampos; + typedef std::streamoff streamoff; + typedef std::streampos streampos; #endif class _LIBCPP_EXPORTED_FROM_ABI Init; @@ -839,8 +839,8 @@ void basic_ios<_CharT, _Traits>::swap(basic_ios& __rhs) _NOEXCEPT { ios_base::swap(__rhs); - _VSTD::swap(__tie_, __rhs.__tie_); - _VSTD::swap(__fill_, __rhs.__fill_); + std::swap(__tie_, __rhs.__tie_); + std::swap(__fill_, __rhs.__fill_); } template diff --git a/libcxx/include/istream b/libcxx/include/istream index ed3a82f39ff7..0351257c7df8 100644 --- a/libcxx/include/istream +++ b/libcxx/include/istream @@ -213,7 +213,7 @@ protected: inline _LIBCPP_HIDE_FROM_ABI_AFTER_V1 void swap(basic_istream& __rhs) { - _VSTD::swap(__gc_, __rhs.__gc_); + std::swap(__gc_, __rhs.__gc_); basic_ios::swap(__rhs); } @@ -398,77 +398,77 @@ template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(unsigned short& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(unsigned int& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(long& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(unsigned long& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(long long& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(unsigned long long& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(float& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(double& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(long double& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(bool& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(void*& __n) { - return _VSTD::__input_arithmetic(*this, __n); + return std::__input_arithmetic(*this, __n); } template @@ -522,14 +522,14 @@ template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(short& __n) { - return _VSTD::__input_arithmetic_with_numeric_limits(*this, __n); + return std::__input_arithmetic_with_numeric_limits(*this, __n); } template basic_istream<_CharT, _Traits>& basic_istream<_CharT, _Traits>::operator>>(int& __n) { - return _VSTD::__input_arithmetic_with_numeric_limits(*this, __n); + return std::__input_arithmetic_with_numeric_limits(*this, __n); } template @@ -591,8 +591,8 @@ operator>>(basic_istream<_CharT, _Traits>& __is, _CharT (&__buf)[_Np]) { size_t __n = _Np; if (__is.width() > 0) - __n = _VSTD::min(size_t(__is.width()), _Np); - return _VSTD::__input_c_string(__is, __buf, __n); + __n = std::min(size_t(__is.width()), _Np); + return std::__input_c_string(__is, __buf, __n); } template @@ -621,7 +621,7 @@ operator>>(basic_istream<_CharT, _Traits>& __is, _CharT* __s) streamsize __n = __is.width(); if (__n <= 0) __n = numeric_limits::max() / sizeof(_CharT) - 1; - return _VSTD::__input_c_string(__is, __s, size_t(__n)); + return std::__input_c_string(__is, __s, size_t(__n)); } template @@ -1105,7 +1105,7 @@ basic_istream<_CharT, _Traits>::readsome(char_type* __s, streamsize __n) case 0: break; default: - __n = _VSTD::min(__c, __n); + __n = std::min(__c, __n); __gc_ = this->rdbuf()->sgetn(__s, __n); if (__gc_ != __n) __state |= ios_base::failbit | ios_base::eofbit; @@ -1393,8 +1393,8 @@ template >(_Stream&& __is, _Tp&& __x) { - __is >> _VSTD::forward<_Tp>(__x); - return _VSTD::move(__is); + __is >> std::forward<_Tp>(__x); + return std::move(__is); } template @@ -1432,7 +1432,7 @@ protected: template basic_iostream<_CharT, _Traits>::basic_iostream(basic_iostream&& __rhs) - : basic_istream<_CharT, _Traits>(_VSTD::move(__rhs)) + : basic_istream<_CharT, _Traits>(std::move(__rhs)) { } diff --git a/libcxx/include/limits b/libcxx/include/limits index a5cce05119fe..a31593fe03e7 100644 --- a/libcxx/include/limits +++ b/libcxx/include/limits @@ -233,7 +233,7 @@ protected: static _LIBCPP_CONSTEXPR const bool is_iec559 = false; static _LIBCPP_CONSTEXPR const bool is_bounded = true; - static _LIBCPP_CONSTEXPR const bool is_modulo = !_VSTD::is_signed<_Tp>::value; + static _LIBCPP_CONSTEXPR const bool is_modulo = !std::is_signed<_Tp>::value; #if defined(__i386__) || defined(__x86_64__) || defined(__pnacl__) || \ defined(__wasm__) diff --git a/libcxx/include/list b/libcxx/include/list index 2909bef56de9..922843ad571d 100644 --- a/libcxx/include/list +++ b/libcxx/include/list @@ -666,7 +666,7 @@ private: void __move_assign_alloc(__list_imp& __c, true_type) _NOEXCEPT_(is_nothrow_move_assignable<__node_allocator>::value) { - __node_alloc() = _VSTD::move(__c.__node_alloc()); + __node_alloc() = std::move(__c.__node_alloc()); } _LIBCPP_HIDE_FROM_ABI @@ -708,7 +708,7 @@ inline __list_imp<_Tp, _Alloc>::__list_imp(const __node_allocator& __a) #ifndef _LIBCPP_CXX03_LANG template inline __list_imp<_Tp, _Alloc>::__list_imp(__node_allocator&& __a) _NOEXCEPT - : __size_alloc_(0, _VSTD::move(__a)) {} + : __size_alloc_(0, std::move(__a)) {} #endif template @@ -749,8 +749,8 @@ __list_imp<_Tp, _Alloc>::swap(__list_imp& __c) this->__node_alloc() == __c.__node_alloc(), "list::swap: Either propagate_on_container_swap must be true" " or the allocators must compare equal"); - using _VSTD::swap; - _VSTD::__swap_allocator(__node_alloc(), __c.__node_alloc()); + using std::swap; + std::__swap_allocator(__node_alloc(), __c.__node_alloc()); swap(__sz(), __c.__sz()); swap(__end_, __c.__end_); if (__sz() == 0) @@ -789,8 +789,8 @@ public: typedef typename base::difference_type difference_type; typedef typename base::iterator iterator; typedef typename base::const_iterator const_iterator; - typedef _VSTD::reverse_iterator reverse_iterator; - typedef _VSTD::reverse_iterator const_reverse_iterator; + typedef std::reverse_iterator reverse_iterator; + typedef std::reverse_iterator const_reverse_iterator; #if _LIBCPP_STD_VER >= 20 typedef size_type __remove_return_type; #else @@ -889,7 +889,7 @@ public: _LIBCPP_HIDE_FROM_ABI size_type max_size() const _NOEXCEPT { - return _VSTD::min( + return std::min( base::__node_alloc_max_size(), numeric_limits::max()); } @@ -997,7 +997,7 @@ public: #ifndef _LIBCPP_CXX03_LANG template _LIBCPP_HIDE_FROM_ABI - void __emplace_back(_Arg&& __arg) { emplace_back(_VSTD::forward<_Arg>(__arg)); } + void __emplace_back(_Arg&& __arg) { emplace_back(std::forward<_Arg>(__arg)); } #else _LIBCPP_HIDE_FROM_ABI void __emplace_back(value_type const& __arg) { push_back(__arg); } @@ -1176,8 +1176,8 @@ inline typename list<_Tp, _Alloc>::iterator list<_Tp, _Alloc>::__iterator(size_type __n) { - return __n <= base::__sz() / 2 ? _VSTD::next(begin(), __n) - : _VSTD::prev(end(), base::__sz() - __n); + return __n <= base::__sz() / 2 ? std::next(begin(), __n) + : std::prev(end(), base::__sz() - __n); } template @@ -1264,7 +1264,7 @@ list<_Tp, _Alloc>::list(initializer_list __il) template inline list<_Tp, _Alloc>::list(list&& __c) _NOEXCEPT_(is_nothrow_move_constructible<__node_allocator>::value) - : base(_VSTD::move(__c.__node_alloc())) { + : base(std::move(__c.__node_alloc())) { splice(end(), __c); } @@ -1325,7 +1325,7 @@ inline list<_Tp, _Alloc>& list<_Tp, _Alloc>::operator=(const list& __c) { - if (this != _VSTD::addressof(__c)) + if (this != std::addressof(__c)) { base::__copy_assign_alloc(__c); assign(__c.begin(), __c.end()); @@ -1730,7 +1730,7 @@ template void list<_Tp, _Alloc>::splice(const_iterator __p, list& __c) { - _LIBCPP_ASSERT_VALID_INPUT_RANGE(this != _VSTD::addressof(__c), + _LIBCPP_ASSERT_VALID_INPUT_RANGE(this != std::addressof(__c), "list::splice(iterator, list) called with this == &list"); if (!__c.empty()) { @@ -1766,9 +1766,9 @@ list<_Tp, _Alloc>::splice(const_iterator __p, list& __c, const_iterator __f, con __link_pointer __first = __f.__ptr_; --__l; __link_pointer __last = __l.__ptr_; - if (this != _VSTD::addressof(__c)) + if (this != std::addressof(__c)) { - size_type __s = _VSTD::distance(__f, __l) + 1; + size_type __s = std::distance(__f, __l) + 1; __c.__sz() -= __s; base::__sz() += __s; } @@ -1786,7 +1786,7 @@ list<_Tp, _Alloc>::remove(const value_type& __x) { if (*__i == __x) { - const_iterator __j = _VSTD::next(__i); + const_iterator __j = std::next(__i); for (; __j != __e && *__j == __x; ++__j) ; __deleted_nodes.splice(__deleted_nodes.end(), *this, __i, __j); @@ -1811,7 +1811,7 @@ list<_Tp, _Alloc>::remove_if(_Pred __pred) { if (__pred(*__i)) { - iterator __j = _VSTD::next(__i); + iterator __j = std::next(__i); for (; __j != __e && __pred(*__j); ++__j) ; __deleted_nodes.splice(__deleted_nodes.end(), *this, __i, __j); @@ -1834,7 +1834,7 @@ list<_Tp, _Alloc>::unique(_BinaryPred __binary_pred) list<_Tp, _Alloc> __deleted_nodes(get_allocator()); // collect the nodes we're removing for (iterator __i = begin(), __e = end(); __i != __e;) { - iterator __j = _VSTD::next(__i); + iterator __j = std::next(__i); for (; __j != __e && __binary_pred(*__i, *__j); ++__j) ; if (++__i != __j) { @@ -1859,7 +1859,7 @@ template void list<_Tp, _Alloc>::merge(list& __c, _Comp __comp) { - if (this != _VSTD::addressof(__c)) + if (this != std::addressof(__c)) { iterator __f1 = begin(); iterator __e1 = end(); @@ -1870,7 +1870,7 @@ list<_Tp, _Alloc>::merge(list& __c, _Comp __comp) if (__comp(*__f2, *__f1)) { size_type __ds = 1; - iterator __m2 = _VSTD::next(__f2); + iterator __m2 = std::next(__f2); for (; __m2 != __e2 && __comp(*__m2, *__f1); ++__m2, (void) ++__ds) ; base::__sz() += __ds; @@ -1879,7 +1879,7 @@ list<_Tp, _Alloc>::merge(list& __c, _Comp __comp) __link_pointer __l = __m2.__ptr_->__prev_; __f2 = __m2; base::__unlink_nodes(__f, __l); - __m2 = _VSTD::next(__f1); + __m2 = std::next(__f1); __link_nodes(__f1.__ptr_, __f, __l); __f1 = __m2; } @@ -1928,12 +1928,12 @@ list<_Tp, _Alloc>::__sort(iterator __f1, iterator __e2, size_type __n, _Comp& __ return __f1; } size_type __n2 = __n / 2; - iterator __e1 = _VSTD::next(__f1, __n2); + iterator __e1 = std::next(__f1, __n2); iterator __r = __f1 = __sort(__f1, __e1, __n2, __comp); iterator __f2 = __e1 = __sort(__e1, __e2, __n - __n2, __comp); if (__comp(*__f2, *__f1)) { - iterator __m2 = _VSTD::next(__f2); + iterator __m2 = std::next(__f2); for (; __m2 != __e2 && __comp(*__m2, *__f1); ++__m2) ; __link_pointer __f = __f2.__ptr_; @@ -1941,7 +1941,7 @@ list<_Tp, _Alloc>::__sort(iterator __f1, iterator __e2, size_type __n, _Comp& __ __r = __f2; __e1 = __f2 = __m2; base::__unlink_nodes(__f, __l); - __m2 = _VSTD::next(__f1); + __m2 = std::next(__f1); __link_nodes(__f1.__ptr_, __f, __l); __f1 = __m2; } @@ -1951,7 +1951,7 @@ list<_Tp, _Alloc>::__sort(iterator __f1, iterator __e2, size_type __n, _Comp& __ { if (__comp(*__f2, *__f1)) { - iterator __m2 = _VSTD::next(__f2); + iterator __m2 = std::next(__f2); for (; __m2 != __e2 && __comp(*__m2, *__f1); ++__m2) ; __link_pointer __f = __f2.__ptr_; @@ -1960,7 +1960,7 @@ list<_Tp, _Alloc>::__sort(iterator __f1, iterator __e2, size_type __n, _Comp& __ __e1 = __m2; __f2 = __m2; base::__unlink_nodes(__f, __l); - __m2 = _VSTD::next(__f1); + __m2 = std::next(__f1); __link_nodes(__f1.__ptr_, __f, __l); __f1 = __m2; } @@ -1979,10 +1979,10 @@ list<_Tp, _Alloc>::reverse() _NOEXCEPT iterator __e = end(); for (iterator __i = begin(); __i.__ptr_ != __e.__ptr_;) { - _VSTD::swap(__i.__ptr_->__prev_, __i.__ptr_->__next_); + std::swap(__i.__ptr_->__prev_, __i.__ptr_->__next_); __i.__ptr_ = __i.__ptr_->__prev_; } - _VSTD::swap(__e.__ptr_->__prev_, __e.__ptr_->__next_); + std::swap(__e.__ptr_->__prev_, __e.__ptr_->__next_); } } @@ -1990,7 +1990,7 @@ template bool list<_Tp, _Alloc>::__invariants() const { - return size() == _VSTD::distance(begin(), end()); + return size() == std::distance(begin(), end()); } template @@ -1998,7 +1998,7 @@ inline _LIBCPP_HIDE_FROM_ABI bool operator==(const list<_Tp, _Alloc>& __x, const list<_Tp, _Alloc>& __y) { - return __x.size() == __y.size() && _VSTD::equal(__x.begin(), __x.end(), __y.begin()); + return __x.size() == __y.size() && std::equal(__x.begin(), __x.end(), __y.begin()); } #if _LIBCPP_STD_VER <= 17 @@ -2008,7 +2008,7 @@ inline _LIBCPP_HIDE_FROM_ABI bool operator< (const list<_Tp, _Alloc>& __x, const list<_Tp, _Alloc>& __y) { - return _VSTD::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); + return std::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); } template @@ -2073,7 +2073,7 @@ erase_if(list<_Tp, _Allocator>& __c, _Predicate __pred) { template inline _LIBCPP_HIDE_FROM_ABI typename list<_Tp, _Allocator>::size_type erase(list<_Tp, _Allocator>& __c, const _Up& __v) { - return _VSTD::erase_if(__c, [&](auto& __elem) { return __elem == __v; }); + return std::erase_if(__c, [&](auto& __elem) { return __elem == __v; }); } template <> diff --git a/libcxx/include/locale b/libcxx/include/locale index 659106c7ab9d..56fa8db91d2b 100644 --- a/libcxx/include/locale +++ b/libcxx/include/locale @@ -277,7 +277,7 @@ __scan_keyword(_InputIterator& __b, _InputIterator __e, bool __case_sensitive = true) { typedef typename iterator_traits<_InputIterator>::value_type _CharT; - size_t __nkw = static_cast(_VSTD::distance(__kb, __ke)); + size_t __nkw = static_cast(std::distance(__kb, __ke)); const unsigned char __doesnt_match = '\0'; const unsigned char __might_match = '\1'; const unsigned char __does_match = '\2'; @@ -899,7 +899,7 @@ num_get<_CharT, _InputIterator>::do_get(iter_type __b, iter_type __e, const numpunct<_CharT>& __np = std::use_facet >(__iob.getloc()); typedef typename numpunct<_CharT>::string_type string_type; const string_type __names[2] = {__np.truename(), __np.falsename()}; - const string_type* __i = _VSTD::__scan_keyword(__b, __e, __names, __names+2, + const string_type* __i = std::__scan_keyword(__b, __e, __names, __names+2, __ct, __err); __v = __i == __names; return __b; @@ -1881,7 +1881,7 @@ time_get<_CharT, _InputIterator>::__get_weekdayname(int& __w, { // Note: ignoring case comes from the POSIX strptime spec const string_type* __wk = this->__weeks(); - ptrdiff_t __i = _VSTD::__scan_keyword(__b, __e, __wk, __wk+14, __ct, __err, false) - __wk; + ptrdiff_t __i = std::__scan_keyword(__b, __e, __wk, __wk+14, __ct, __err, false) - __wk; if (__i < 14) __w = __i % 7; } @@ -1895,7 +1895,7 @@ time_get<_CharT, _InputIterator>::__get_monthname(int& __m, { // Note: ignoring case comes from the POSIX strptime spec const string_type* __month = this->__months(); - ptrdiff_t __i = _VSTD::__scan_keyword(__b, __e, __month, __month+24, __ct, __err, false) - __month; + ptrdiff_t __i = std::__scan_keyword(__b, __e, __month, __month+24, __ct, __err, false) - __month; if (__i < 24) __m = __i % 12; } @@ -1907,7 +1907,7 @@ time_get<_CharT, _InputIterator>::__get_day(int& __d, ios_base::iostate& __err, const ctype& __ct) const { - int __t = _VSTD::__get_up_to_n_digits(__b, __e, __err, __ct, 2); + int __t = std::__get_up_to_n_digits(__b, __e, __err, __ct, 2); if (!(__err & ios_base::failbit) && 1 <= __t && __t <= 31) __d = __t; else @@ -2067,7 +2067,7 @@ time_get<_CharT, _InputIterator>::__get_am_pm(int& __h, __err |= ios_base::failbit; return; } - ptrdiff_t __i = _VSTD::__scan_keyword(__b, __e, __ap, __ap+2, __ct, __err, false) - __ap; + ptrdiff_t __i = std::__scan_keyword(__b, __e, __ap, __ap+2, __ct, __err, false) - __ap; if (__i == 0 && __h == 12) __h = 0; else if (__i == 1 && __h < 12) @@ -2535,7 +2535,7 @@ time_put<_CharT, _OutputIterator>::do_put(iter_type __s, ios_base&, char_type* __nb = __nar; char_type* __ne = __nb + 100; __do_put(__nb, __ne, __tm, __fmt, __mod); - return _VSTD::copy(__nb, __ne, __s); + return std::copy(__nb, __ne, __s); } extern template class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS time_put; @@ -3071,7 +3071,7 @@ money_get<_CharT, _InputIterator>::do_get(iter_type __b, iter_type __e, if (__neg) *__nc++ = '-'; for (const char_type* __w = __wb.get(); __w < __wn; ++__w, ++__nc) - *__nc = __src[std::find(__atoms, _VSTD::end(__atoms), *__w) - __atoms]; + *__nc = __src[std::find(__atoms, std::end(__atoms), *__w) - __atoms]; *__nc = char(); if (sscanf(__nbuf, "%Lf", &__v) != 1) __throw_runtime_error("money_get error"); @@ -3224,7 +3224,7 @@ __money_put<_CharT>::__format(char_type* __mb, char_type*& __mi, char_type*& __m break; case money_base::symbol: if (!__sym.empty() && (__flags & ios_base::showbase)) - __me = _VSTD::copy(__sym.begin(), __sym.end(), __me); + __me = std::copy(__sym.begin(), __sym.end(), __me); break; case money_base::value: { @@ -3283,7 +3283,7 @@ __money_put<_CharT>::__format(char_type* __mb, char_type*& __mi, char_type*& __m } // print rest of sign, if any if (__sn.size() > 1) - __me = _VSTD::copy(__sn.begin()+1, __sn.end(), __me); + __me = std::copy(__sn.begin()+1, __sn.end(), __me); // set alignment if ((__flags & ios_base::adjustfield) == ios_base::left) __mi = __me; @@ -3534,7 +3534,7 @@ messages<_CharT>::do_get(catalog __c, int __set, int __msgid, char* __n = catgets(__cat, __set, __msgid, __ndflt.c_str()); string_type __w; __widen_from_utf8()(std::back_inserter(__w), - __n, __n + _VSTD::strlen(__n)); + __n, __n + std::strlen(__n)); return __w; #else // !_LIBCPP_HAS_CATOPEN (void)__c; @@ -3688,8 +3688,8 @@ template inline wstring_convert<_Codecvt, _Elem, _WideAlloc, _ByteAlloc>:: wstring_convert(wstring_convert&& __wc) - : __byte_err_string_(_VSTD::move(__wc.__byte_err_string_)), - __wide_err_string_(_VSTD::move(__wc.__wide_err_string_)), + : __byte_err_string_(std::move(__wc.__byte_err_string_)), + __wide_err_string_(std::move(__wc.__wide_err_string_)), __cvtptr_(__wc.__cvtptr_), __cvtstate_(__wc.__cvtstate_), __cvtcount_(__wc.__cvtcount_) { @@ -3981,7 +3981,7 @@ _LIBCPP_SUPPRESS_DEPRECATED_POP int_type __c = traits_type::eof(); if (this->gptr() == this->egptr()) { - _VSTD::memmove(this->eback(), this->egptr() - __unget_sz, __unget_sz * sizeof(char_type)); + std::memmove(this->eback(), this->egptr() - __unget_sz, __unget_sz * sizeof(char_type)); if (__always_noconv_) { streamsize __nmemb = static_cast(this->egptr() - this->eback() - __unget_sz); @@ -3999,11 +3999,11 @@ _LIBCPP_SUPPRESS_DEPRECATED_POP if (__extbufend_ != __extbufnext_) { _LIBCPP_ASSERT_NON_NULL(__extbufnext_ != nullptr, "underflow moving from nullptr"); _LIBCPP_ASSERT_NON_NULL(__extbuf_ != nullptr, "underflow moving into nullptr"); - _VSTD::memmove(__extbuf_, __extbufnext_, __extbufend_ - __extbufnext_); + std::memmove(__extbuf_, __extbufnext_, __extbufend_ - __extbufnext_); } __extbufnext_ = __extbuf_ + (__extbufend_ - __extbufnext_); __extbufend_ = __extbuf_ + (__extbuf_ == __extbuf_min_ ? sizeof(__extbuf_min_) : __ebs_); - streamsize __nmemb = _VSTD::min(static_cast(this->egptr() - this->eback() - __unget_sz), + streamsize __nmemb = std::min(static_cast(this->egptr() - this->eback() - __unget_sz), static_cast(__extbufend_ - __extbufnext_)); codecvt_base::result __r; // FIXME: Do we ever need to restore the state here? diff --git a/libcxx/include/map b/libcxx/include/map index ebef83a00f9f..82a296f9cb8d 100644 --- a/libcxx/include/map +++ b/libcxx/include/map @@ -647,7 +647,7 @@ public: _LIBCPP_HIDE_FROM_ABI void swap(__map_value_compare& __y) _NOEXCEPT_(__is_nothrow_swappable<_Compare>::value) { - using _VSTD::swap; + using std::swap; swap(static_cast<_Compare&>(*this), static_cast<_Compare&>(__y)); } @@ -693,7 +693,7 @@ public: void swap(__map_value_compare& __y) _NOEXCEPT_(__is_nothrow_swappable<_Compare>::value) { - using _VSTD::swap; + using std::swap; swap(__comp_, __y.__comp_); } @@ -760,9 +760,9 @@ public: void operator()(pointer __p) _NOEXCEPT { if (__second_constructed) - __alloc_traits::destroy(__na_, _VSTD::addressof(__p->__value_.__get_value().second)); + __alloc_traits::destroy(__na_, std::addressof(__p->__value_.__get_value().second)); if (__first_constructed) - __alloc_traits::destroy(__na_, _VSTD::addressof(__p->__value_.__get_value().first)); + __alloc_traits::destroy(__na_, std::addressof(__p->__value_.__get_value().first)); if (__p) __alloc_traits::deallocate(__na_, __p, 1); } @@ -793,7 +793,7 @@ public: value_type& __get_value() { #if _LIBCPP_STD_VER >= 17 - return *_VSTD::launder(_VSTD::addressof(__cc_)); + return *std::launder(std::addressof(__cc_)); #else return __cc_; #endif @@ -803,7 +803,7 @@ public: const value_type& __get_value() const { #if _LIBCPP_STD_VER >= 17 - return *_VSTD::launder(_VSTD::addressof(__cc_)); + return *std::launder(std::addressof(__cc_)); #else return __cc_; #endif @@ -821,8 +821,8 @@ public: { value_type& __v = __get_value(); return __nc_rref_pair_type( - _VSTD::move(const_cast(__v.first)), - _VSTD::move(__v.second)); + std::move(const_cast(__v.first)), + std::move(__v.second)); } _LIBCPP_HIDE_FROM_ABI @@ -845,7 +845,7 @@ public: _LIBCPP_HIDE_FROM_ABI __value_type& operator=(_ValueTp&& __v) { - __ref() = _VSTD::forward<_ValueTp>(__v); + __ref() = std::forward<_ValueTp>(__v); return *this; } @@ -1047,7 +1047,7 @@ public: private: - typedef _VSTD::__value_type __value_type; + typedef std::__value_type __value_type; typedef __map_value_compare __vc; typedef __rebind_alloc, __value_type> __allocator_type; typedef __tree<__value_type, __vc, __allocator_type> __base; @@ -1067,8 +1067,8 @@ public: typedef typename __alloc_traits::difference_type difference_type; typedef __map_iterator iterator; typedef __map_const_iterator const_iterator; - typedef _VSTD::reverse_iterator reverse_iterator; - typedef _VSTD::reverse_iterator const_reverse_iterator; + typedef std::reverse_iterator reverse_iterator; + typedef std::reverse_iterator const_reverse_iterator; #if _LIBCPP_STD_VER >= 17 typedef __map_node_handle node_type; @@ -1154,7 +1154,7 @@ public: #ifndef _LIBCPP_CXX03_LANG __tree_ = __m.__tree_; #else - if (this != _VSTD::addressof(__m)) { + if (this != std::addressof(__m)) { __tree_.clear(); __tree_.value_comp() = __m.__tree_.value_comp(); __tree_.__copy_assign_alloc(__m.__tree_); @@ -1169,7 +1169,7 @@ public: _LIBCPP_HIDE_FROM_ABI map(map&& __m) _NOEXCEPT_(is_nothrow_move_constructible<__base>::value) - : __tree_(_VSTD::move(__m.__tree_)) + : __tree_(std::move(__m.__tree_)) { } @@ -1179,7 +1179,7 @@ public: map& operator=(map&& __m) _NOEXCEPT_(is_nothrow_move_assignable<__base>::value) { - __tree_ = _VSTD::move(__m.__tree_); + __tree_ = std::move(__m.__tree_); return *this; } @@ -1286,26 +1286,26 @@ public: template _LIBCPP_HIDE_FROM_ABI pair emplace(_Args&& ...__args) { - return __tree_.__emplace_unique(_VSTD::forward<_Args>(__args)...); + return __tree_.__emplace_unique(std::forward<_Args>(__args)...); } template _LIBCPP_HIDE_FROM_ABI iterator emplace_hint(const_iterator __p, _Args&& ...__args) { - return __tree_.__emplace_hint_unique(__p.__i_, _VSTD::forward<_Args>(__args)...); + return __tree_.__emplace_hint_unique(__p.__i_, std::forward<_Args>(__args)...); } template ::value> > _LIBCPP_HIDE_FROM_ABI pair insert(_Pp&& __p) - {return __tree_.__insert_unique(_VSTD::forward<_Pp>(__p));} + {return __tree_.__insert_unique(std::forward<_Pp>(__p));} template ::value> > _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __pos, _Pp&& __p) - {return __tree_.__insert_unique(__pos.__i_, _VSTD::forward<_Pp>(__p));} + {return __tree_.__insert_unique(__pos.__i_, std::forward<_Pp>(__p));} #endif // _LIBCPP_CXX03_LANG @@ -1321,11 +1321,11 @@ public: #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI pair - insert(value_type&& __v) {return __tree_.__insert_unique(_VSTD::move(__v));} + insert(value_type&& __v) {return __tree_.__insert_unique(std::move(__v));} _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __p, value_type&& __v) - {return __tree_.__insert_unique(__p.__i_, _VSTD::move(__v));} + {return __tree_.__insert_unique(__p.__i_, std::move(__v));} _LIBCPP_HIDE_FROM_ABI void insert(initializer_list __il) @@ -1358,9 +1358,9 @@ public: pair try_emplace(const key_type& __k, _Args&&... __args) { return __tree_.__emplace_unique_key_args(__k, - _VSTD::piecewise_construct, - _VSTD::forward_as_tuple(__k), - _VSTD::forward_as_tuple(_VSTD::forward<_Args>(__args)...)); + std::piecewise_construct, + std::forward_as_tuple(__k), + std::forward_as_tuple(std::forward<_Args>(__args)...)); } template @@ -1368,9 +1368,9 @@ public: pair try_emplace(key_type&& __k, _Args&&... __args) { return __tree_.__emplace_unique_key_args(__k, - _VSTD::piecewise_construct, - _VSTD::forward_as_tuple(_VSTD::move(__k)), - _VSTD::forward_as_tuple(_VSTD::forward<_Args>(__args)...)); + std::piecewise_construct, + std::forward_as_tuple(std::move(__k)), + std::forward_as_tuple(std::forward<_Args>(__args)...)); } template @@ -1378,9 +1378,9 @@ public: iterator try_emplace(const_iterator __h, const key_type& __k, _Args&&... __args) { return __tree_.__emplace_hint_unique_key_args(__h.__i_, __k, - _VSTD::piecewise_construct, - _VSTD::forward_as_tuple(__k), - _VSTD::forward_as_tuple(_VSTD::forward<_Args>(__args)...)).first; + std::piecewise_construct, + std::forward_as_tuple(__k), + std::forward_as_tuple(std::forward<_Args>(__args)...)).first; } template @@ -1388,9 +1388,9 @@ public: iterator try_emplace(const_iterator __h, key_type&& __k, _Args&&... __args) { return __tree_.__emplace_hint_unique_key_args(__h.__i_, __k, - _VSTD::piecewise_construct, - _VSTD::forward_as_tuple(_VSTD::move(__k)), - _VSTD::forward_as_tuple(_VSTD::forward<_Args>(__args)...)).first; + std::piecewise_construct, + std::forward_as_tuple(std::move(__k)), + std::forward_as_tuple(std::forward<_Args>(__args)...)).first; } template @@ -1400,10 +1400,10 @@ public: iterator __p = lower_bound(__k); if ( __p != end() && !key_comp()(__k, __p->first)) { - __p->second = _VSTD::forward<_Vp>(__v); - return _VSTD::make_pair(__p, false); + __p->second = std::forward<_Vp>(__v); + return std::make_pair(__p, false); } - return _VSTD::make_pair(emplace_hint(__p, __k, _VSTD::forward<_Vp>(__v)), true); + return std::make_pair(emplace_hint(__p, __k, std::forward<_Vp>(__v)), true); } template @@ -1413,10 +1413,10 @@ public: iterator __p = lower_bound(__k); if ( __p != end() && !key_comp()(__k, __p->first)) { - __p->second = _VSTD::forward<_Vp>(__v); - return _VSTD::make_pair(__p, false); + __p->second = std::forward<_Vp>(__v); + return std::make_pair(__p, false); } - return _VSTD::make_pair(emplace_hint(__p, _VSTD::move(__k), _VSTD::forward<_Vp>(__v)), true); + return std::make_pair(emplace_hint(__p, std::move(__k), std::forward<_Vp>(__v)), true); } template @@ -1424,10 +1424,10 @@ public: const key_type& __k, _Vp&& __v) { auto [__r, __inserted] = __tree_.__emplace_hint_unique_key_args( - __h.__i_, __k, __k, _VSTD::forward<_Vp>(__v)); + __h.__i_, __k, __k, std::forward<_Vp>(__v)); if (!__inserted) - __r->__get_value().second = _VSTD::forward<_Vp>(__v); + __r->__get_value().second = std::forward<_Vp>(__v); return __r; } @@ -1437,10 +1437,10 @@ public: key_type&& __k, _Vp&& __v) { auto [__r, __inserted] = __tree_.__emplace_hint_unique_key_args( - __h.__i_, __k, _VSTD::move(__k), _VSTD::forward<_Vp>(__v)); + __h.__i_, __k, std::move(__k), std::forward<_Vp>(__v)); if (!__inserted) - __r->__get_value().second = _VSTD::forward<_Vp>(__v); + __r->__get_value().second = std::forward<_Vp>(__v); return __r; } @@ -1467,7 +1467,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to map::insert()"); return __tree_.template __node_handle_insert_unique< - node_type, insert_return_type>(_VSTD::move(__nh)); + node_type, insert_return_type>(std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __hint, node_type&& __nh) @@ -1475,7 +1475,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to map::insert()"); return __tree_.template __node_handle_insert_unique( - __hint.__i_, _VSTD::move(__nh)); + __hint.__i_, std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI node_type extract(key_type const& __key) @@ -1675,7 +1675,7 @@ map(initializer_list>, _Allocator) #ifndef _LIBCPP_CXX03_LANG template map<_Key, _Tp, _Compare, _Allocator>::map(map&& __m, const allocator_type& __a) - : __tree_(_VSTD::move(__m.__tree_), typename __base::allocator_type(__a)) + : __tree_(std::move(__m.__tree_), typename __base::allocator_type(__a)) { if (__a != __m.get_allocator()) { @@ -1691,9 +1691,9 @@ _Tp& map<_Key, _Tp, _Compare, _Allocator>::operator[](const key_type& __k) { return __tree_.__emplace_unique_key_args(__k, - _VSTD::piecewise_construct, - _VSTD::forward_as_tuple(__k), - _VSTD::forward_as_tuple()).first->__get_value().second; + std::piecewise_construct, + std::forward_as_tuple(__k), + std::forward_as_tuple()).first->__get_value().second; } template @@ -1703,9 +1703,9 @@ map<_Key, _Tp, _Compare, _Allocator>::operator[](key_type&& __k) // TODO investigate this clang-tidy warning. // NOLINTNEXTLINE(bugprone-use-after-move) return __tree_.__emplace_unique_key_args(__k, - _VSTD::piecewise_construct, - _VSTD::forward_as_tuple(_VSTD::move(__k)), - _VSTD::forward_as_tuple()).first->__get_value().second; + std::piecewise_construct, + std::forward_as_tuple(std::move(__k)), + std::forward_as_tuple()).first->__get_value().second; } #else // _LIBCPP_CXX03_LANG @@ -1716,9 +1716,9 @@ map<_Key, _Tp, _Compare, _Allocator>::__construct_node_with_key(const key_type& { __node_allocator& __na = __tree_.__node_alloc(); __node_holder __h(__node_traits::allocate(__na, 1), _Dp(__na)); - __node_traits::construct(__na, _VSTD::addressof(__h->__value_.__get_value().first), __k); + __node_traits::construct(__na, std::addressof(__h->__value_.__get_value().first), __k); __h.get_deleter().__first_constructed = true; - __node_traits::construct(__na, _VSTD::addressof(__h->__value_.__get_value().second)); + __node_traits::construct(__na, std::addressof(__h->__value_.__get_value().second)); __h.get_deleter().__second_constructed = true; return __h; } @@ -1770,7 +1770,7 @@ bool operator==(const map<_Key, _Tp, _Compare, _Allocator>& __x, const map<_Key, _Tp, _Compare, _Allocator>& __y) { - return __x.size() == __y.size() && _VSTD::equal(__x.begin(), __x.end(), __y.begin()); + return __x.size() == __y.size() && std::equal(__x.begin(), __x.end(), __y.begin()); } #if _LIBCPP_STD_VER <= 17 @@ -1781,7 +1781,7 @@ bool operator< (const map<_Key, _Tp, _Compare, _Allocator>& __x, const map<_Key, _Tp, _Compare, _Allocator>& __y) { - return _VSTD::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); + return std::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); } template @@ -1851,7 +1851,7 @@ template ::size_type erase_if(map<_Key, _Tp, _Compare, _Allocator>& __c, _Predicate __pred) { - return _VSTD::__libcpp_erase_if_container(__c, __pred); + return std::__libcpp_erase_if_container(__c, __pred); } #endif @@ -1890,7 +1890,7 @@ public: private: - typedef _VSTD::__value_type __value_type; + typedef std::__value_type __value_type; typedef __map_value_compare __vc; typedef __rebind_alloc, __value_type> __allocator_type; typedef __tree<__value_type, __vc, __allocator_type> __base; @@ -1910,8 +1910,8 @@ public: typedef typename __alloc_traits::difference_type difference_type; typedef __map_iterator iterator; typedef __map_const_iterator const_iterator; - typedef _VSTD::reverse_iterator reverse_iterator; - typedef _VSTD::reverse_iterator const_reverse_iterator; + typedef std::reverse_iterator reverse_iterator; + typedef std::reverse_iterator const_reverse_iterator; #if _LIBCPP_STD_VER >= 17 typedef __map_node_handle node_type; @@ -1997,7 +1997,7 @@ public: #ifndef _LIBCPP_CXX03_LANG __tree_ = __m.__tree_; #else - if (this != _VSTD::addressof(__m)) { + if (this != std::addressof(__m)) { __tree_.clear(); __tree_.value_comp() = __m.__tree_.value_comp(); __tree_.__copy_assign_alloc(__m.__tree_); @@ -2012,7 +2012,7 @@ public: _LIBCPP_HIDE_FROM_ABI multimap(multimap&& __m) _NOEXCEPT_(is_nothrow_move_constructible<__base>::value) - : __tree_(_VSTD::move(__m.__tree_)) + : __tree_(std::move(__m.__tree_)) { } @@ -2022,7 +2022,7 @@ public: multimap& operator=(multimap&& __m) _NOEXCEPT_(is_nothrow_move_assignable<__base>::value) { - __tree_ = _VSTD::move(__m.__tree_); + __tree_ = std::move(__m.__tree_); return *this; } @@ -2122,34 +2122,34 @@ public: template _LIBCPP_HIDE_FROM_ABI iterator emplace(_Args&& ...__args) { - return __tree_.__emplace_multi(_VSTD::forward<_Args>(__args)...); + return __tree_.__emplace_multi(std::forward<_Args>(__args)...); } template _LIBCPP_HIDE_FROM_ABI iterator emplace_hint(const_iterator __p, _Args&& ...__args) { - return __tree_.__emplace_hint_multi(__p.__i_, _VSTD::forward<_Args>(__args)...); + return __tree_.__emplace_hint_multi(__p.__i_, std::forward<_Args>(__args)...); } template ::value>> _LIBCPP_HIDE_FROM_ABI iterator insert(_Pp&& __p) - {return __tree_.__insert_multi(_VSTD::forward<_Pp>(__p));} + {return __tree_.__insert_multi(std::forward<_Pp>(__p));} template ::value>> _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __pos, _Pp&& __p) - {return __tree_.__insert_multi(__pos.__i_, _VSTD::forward<_Pp>(__p));} + {return __tree_.__insert_multi(__pos.__i_, std::forward<_Pp>(__p));} _LIBCPP_HIDE_FROM_ABI iterator insert(value_type&& __v) - {return __tree_.__insert_multi(_VSTD::move(__v));} + {return __tree_.__insert_multi(std::move(__v));} _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __p, value_type&& __v) - {return __tree_.__insert_multi(__p.__i_, _VSTD::move(__v));} + {return __tree_.__insert_multi(__p.__i_, std::move(__v));} _LIBCPP_HIDE_FROM_ABI @@ -2201,7 +2201,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to multimap::insert()"); return __tree_.template __node_handle_insert_multi( - _VSTD::move(__nh)); + std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __hint, node_type&& __nh) @@ -2209,7 +2209,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to multimap::insert()"); return __tree_.template __node_handle_insert_multi( - __hint.__i_, _VSTD::move(__nh)); + __hint.__i_, std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI node_type extract(key_type const& __key) @@ -2407,14 +2407,14 @@ multimap(initializer_list>, _Allocator) #ifndef _LIBCPP_CXX03_LANG template multimap<_Key, _Tp, _Compare, _Allocator>::multimap(multimap&& __m, const allocator_type& __a) - : __tree_(_VSTD::move(__m.__tree_), typename __base::allocator_type(__a)) + : __tree_(std::move(__m.__tree_), typename __base::allocator_type(__a)) { if (__a != __m.get_allocator()) { const_iterator __e = cend(); while (!__m.empty()) __tree_.__insert_multi(__e.__i_, - _VSTD::move(__m.__tree_.remove(__m.begin().__i_)->__value_.__move())); + std::move(__m.__tree_.remove(__m.begin().__i_)->__value_.__move())); } } #endif @@ -2425,7 +2425,7 @@ bool operator==(const multimap<_Key, _Tp, _Compare, _Allocator>& __x, const multimap<_Key, _Tp, _Compare, _Allocator>& __y) { - return __x.size() == __y.size() && _VSTD::equal(__x.begin(), __x.end(), __y.begin()); + return __x.size() == __y.size() && std::equal(__x.begin(), __x.end(), __y.begin()); } #if _LIBCPP_STD_VER <= 17 @@ -2436,7 +2436,7 @@ bool operator< (const multimap<_Key, _Tp, _Compare, _Allocator>& __x, const multimap<_Key, _Tp, _Compare, _Allocator>& __y) { - return _VSTD::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); + return std::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); } template @@ -2508,7 +2508,7 @@ inline _LIBCPP_HIDE_FROM_ABI typename multimap<_Key, _Tp, _Compare, _Allocator>::size_type erase_if(multimap<_Key, _Tp, _Compare, _Allocator>& __c, _Predicate __pred) { - return _VSTD::__libcpp_erase_if_container(__c, __pred); + return std::__libcpp_erase_if_container(__c, __pred); } #endif diff --git a/libcxx/include/memory b/libcxx/include/memory index 24ba82f43ddd..71e812064646 100644 --- a/libcxx/include/memory +++ b/libcxx/include/memory @@ -10,6 +10,8 @@ #ifndef _LIBCPP_MEMORY #define _LIBCPP_MEMORY +// clang-format off + /* memory synopsis @@ -914,6 +916,8 @@ template */ +// clang-format on + #include <__assert> // all public C++ headers provide the assertion handler #include <__config> #include <__memory/addressof.h> diff --git a/libcxx/include/mutex b/libcxx/include/mutex index d1d648ce0227..a15e61de04c9 100644 --- a/libcxx/include/mutex +++ b/libcxx/include/mutex @@ -471,7 +471,7 @@ inline _LIBCPP_HIDE_FROM_ABI void __unlock(_L0& __l0, _L1& __l1, _L2& __l2, _L3&... __l3) { __l0.unlock(); __l1.unlock(); - _VSTD::__unlock(__l2, __l3...); + std::__unlock(__l2, __l3...); } #endif // _LIBCPP_CXX03_LANG @@ -524,7 +524,7 @@ public: explicit scoped_lock(_MArgs&... __margs) : __t_(__margs...) { - _VSTD::lock(__margs...); + std::lock(__margs...); } _LIBCPP_HIDE_FROM_ABI @@ -546,7 +546,7 @@ private: template _LIBCPP_HIDE_FROM_ABI static void __unlock_unpack(__tuple_indices<_Indx...>, _MutexTuple& __mt) { - _VSTD::__unlock(_VSTD::get<_Indx>(__mt)...); + std::__unlock(std::get<_Indx>(__mt)...); } _MutexTuple __t_; diff --git a/libcxx/include/new b/libcxx/include/new index 180ce82f368f..18f397219c14 100644 --- a/libcxx/include/new +++ b/libcxx/include/new @@ -349,7 +349,7 @@ template _LIBCPP_NODISCARD_AFTER_CXX17 inline _LIBCPP_HIDE_FROM_ABI constexpr _Tp* launder(_Tp* __p) noexcept { - return _VSTD::__launder(__p); + return std::__launder(__p); } #endif diff --git a/libcxx/include/optional b/libcxx/include/optional index fc621aa49106..3f505b2a8fac 100644 --- a/libcxx/include/optional +++ b/libcxx/include/optional @@ -315,14 +315,14 @@ struct __optional_destruct_base<_Tp, false> template _LIBCPP_HIDE_FROM_ABI constexpr explicit __optional_destruct_base(in_place_t, _Args&&... __args) - : __val_(_VSTD::forward<_Args>(__args)...), + : __val_(std::forward<_Args>(__args)...), __engaged_(true) {} #if _LIBCPP_STD_VER >= 23 template _LIBCPP_HIDE_FROM_ABI constexpr __optional_destruct_base(__optional_construct_from_invoke_tag, _Fp&& __f, _Args&&... __args) - : __val_(_VSTD::invoke(_VSTD::forward<_Fp>(__f), _VSTD::forward<_Args>(__args)...)), __engaged_(true) {} + : __val_(std::invoke(std::forward<_Fp>(__f), std::forward<_Args>(__args)...)), __engaged_(true) {} #endif _LIBCPP_HIDE_FROM_ABI @@ -357,14 +357,14 @@ struct __optional_destruct_base<_Tp, true> template _LIBCPP_HIDE_FROM_ABI constexpr explicit __optional_destruct_base(in_place_t, _Args&&... __args) - : __val_(_VSTD::forward<_Args>(__args)...), + : __val_(std::forward<_Args>(__args)...), __engaged_(true) {} #if _LIBCPP_STD_VER >= 23 template _LIBCPP_HIDE_FROM_ABI constexpr __optional_destruct_base(__optional_construct_from_invoke_tag, _Fp&& __f, _Args&&... __args) - : __val_(_VSTD::invoke(_VSTD::forward<_Fp>(__f), _VSTD::forward<_Args>(__args)...)), __engaged_(true) {} + : __val_(std::invoke(std::forward<_Fp>(__f), std::forward<_Args>(__args)...)), __engaged_(true) {} #endif _LIBCPP_HIDE_FROM_ABI @@ -403,12 +403,12 @@ struct __optional_storage_base : __optional_destruct_base<_Tp> _LIBCPP_HIDE_FROM_ABI constexpr value_type&& __get() && noexcept { - return _VSTD::move(this->__val_); + return std::move(this->__val_); } _LIBCPP_HIDE_FROM_ABI constexpr const value_type&& __get() const&& noexcept { - return _VSTD::move(this->__val_); + return std::move(this->__val_); } template @@ -425,7 +425,7 @@ struct __optional_storage_base : __optional_destruct_base<_Tp> _LIBCPP_CONSTEXPR_SINCE_CXX20 void __construct_from(_That&& __opt) { if (__opt.has_value()) - __construct(_VSTD::forward<_That>(__opt).__get()); + __construct(std::forward<_That>(__opt).__get()); } template @@ -435,14 +435,14 @@ struct __optional_storage_base : __optional_destruct_base<_Tp> if (this->__engaged_ == __opt.has_value()) { if (this->__engaged_) - this->__val_ = _VSTD::forward<_That>(__opt).__get(); + this->__val_ = std::forward<_That>(__opt).__get(); } else { if (this->__engaged_) this->reset(); else - __construct(_VSTD::forward<_That>(__opt).__get()); + __construct(std::forward<_That>(__opt).__get()); } } }; @@ -480,7 +480,7 @@ struct __optional_storage_base<_Tp, true> template _LIBCPP_HIDE_FROM_ABI constexpr explicit __optional_storage_base(in_place_t, _UArg&& __uarg) - : __value_(_VSTD::addressof(__uarg)) + : __value_(std::addressof(__uarg)) { static_assert(__can_bind_reference<_UArg>(), "Attempted to construct a reference element in tuple from a " @@ -500,7 +500,7 @@ struct __optional_storage_base<_Tp, true> _LIBCPP_HIDE_FROM_ABI constexpr value_type&& __get() const&& noexcept - { return _VSTD::forward(*__value_); } + { return std::forward(*__value_); } template _LIBCPP_HIDE_FROM_ABI @@ -510,7 +510,7 @@ struct __optional_storage_base<_Tp, true> static_assert(__can_bind_reference<_UArg>(), "Attempted to construct a reference element in tuple from a " "possible temporary"); - __value_ = _VSTD::addressof(__val); + __value_ = std::addressof(__val); } template @@ -518,7 +518,7 @@ struct __optional_storage_base<_Tp, true> _LIBCPP_CONSTEXPR_SINCE_CXX20 void __construct_from(_That&& __opt) { if (__opt.has_value()) - __construct(_VSTD::forward<_That>(__opt).__get()); + __construct(std::forward<_That>(__opt).__get()); } template @@ -528,14 +528,14 @@ struct __optional_storage_base<_Tp, true> if (has_value() == __opt.has_value()) { if (has_value()) - *__value_ = _VSTD::forward<_That>(__opt).__get(); + *__value_ = std::forward<_That>(__opt).__get(); } else { if (has_value()) reset(); else - __construct(_VSTD::forward<_That>(__opt).__get()); + __construct(std::forward<_That>(__opt).__get()); } } }; @@ -589,7 +589,7 @@ struct __optional_move_base<_Tp, false> : __optional_copy_base<_Tp> _LIBCPP_CONSTEXPR_SINCE_CXX20 __optional_move_base(__optional_move_base&& __opt) noexcept(is_nothrow_move_constructible_v) { - this->__construct_from(_VSTD::move(__opt)); + this->__construct_from(std::move(__opt)); } _LIBCPP_HIDE_FROM_ABI @@ -659,7 +659,7 @@ struct __optional_move_assign_base<_Tp, false> : __optional_copy_assign_base<_Tp noexcept(is_nothrow_move_assignable_v && is_nothrow_move_constructible_v) { - this->__assign_from(_VSTD::move(__opt)); + this->__assign_from(std::move(__opt)); return *this; } }; @@ -810,28 +810,28 @@ public: > _LIBCPP_HIDE_FROM_ABI constexpr explicit optional(_InPlaceT, _Args&&... __args) - : __base(in_place, _VSTD::forward<_Args>(__args)...) {} + : __base(in_place, std::forward<_Args>(__args)...) {} template &, _Args...>> > _LIBCPP_HIDE_FROM_ABI constexpr explicit optional(in_place_t, initializer_list<_Up> __il, _Args&&... __args) - : __base(in_place, __il, _VSTD::forward<_Args>(__args)...) {} + : __base(in_place, __il, std::forward<_Args>(__args)...) {} template ::template __enable_implicit<_Up>() , int> = 0> _LIBCPP_HIDE_FROM_ABI constexpr optional(_Up&& __v) - : __base(in_place, _VSTD::forward<_Up>(__v)) {} + : __base(in_place, std::forward<_Up>(__v)) {} template ::template __enable_explicit<_Up>() , int> = 0> _LIBCPP_HIDE_FROM_ABI constexpr explicit optional(_Up&& __v) - : __base(in_place, _VSTD::forward<_Up>(__v)) {} + : __base(in_place, std::forward<_Up>(__v)) {} // LWG2756: conditionally explicit conversion from const optional<_Up>& template && __v) { - this->__construct_from(_VSTD::move(__v)); + this->__construct_from(std::move(__v)); } template ::template __enable_explicit<_Up>() @@ -866,14 +866,14 @@ public: _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 explicit optional(optional<_Up>&& __v) { - this->__construct_from(_VSTD::move(__v)); + this->__construct_from(std::move(__v)); } #if _LIBCPP_STD_VER >= 23 template _LIBCPP_HIDE_FROM_ABI constexpr explicit optional(__optional_construct_from_invoke_tag, _Fp&& __f, _Args&&... __args) - : __base(__optional_construct_from_invoke_tag{}, _VSTD::forward<_Fp>(__f), _VSTD::forward<_Args>(__args)...) { + : __base(__optional_construct_from_invoke_tag{}, std::forward<_Fp>(__f), std::forward<_Args>(__args)...) { } #endif @@ -905,9 +905,9 @@ public: operator=(_Up&& __v) { if (this->has_value()) - this->__get() = _VSTD::forward<_Up>(__v); + this->__get() = std::forward<_Up>(__v); else - this->__construct(_VSTD::forward<_Up>(__v)); + this->__construct(std::forward<_Up>(__v)); return *this; } @@ -931,7 +931,7 @@ public: _LIBCPP_CONSTEXPR_SINCE_CXX20 optional& operator=(optional<_Up>&& __v) { - this->__assign_from(_VSTD::move(__v)); + this->__assign_from(std::move(__v)); return *this; } @@ -946,7 +946,7 @@ public: emplace(_Args&&... __args) { reset(); - this->__construct(_VSTD::forward<_Args>(__args)...); + this->__construct(std::forward<_Args>(__args)...); return this->__get(); } @@ -961,7 +961,7 @@ public: emplace(initializer_list<_Up> __il, _Args&&... __args) { reset(); - this->__construct(__il, _VSTD::forward<_Args>(__args)...); + this->__construct(__il, std::forward<_Args>(__args)...); return this->__get(); } @@ -972,7 +972,7 @@ public: { if (this->has_value() == __opt.has_value()) { - using _VSTD::swap; + using std::swap; if (this->has_value()) swap(this->__get(), __opt.__get()); } @@ -980,12 +980,12 @@ public: { if (this->has_value()) { - __opt.__construct(_VSTD::move(this->__get())); + __opt.__construct(std::move(this->__get())); reset(); } else { - this->__construct(_VSTD::move(__opt.__get())); + this->__construct(std::move(__opt.__get())); __opt.reset(); } } @@ -997,7 +997,7 @@ public: operator->() const { _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(this->has_value(), "optional operator-> called on a disengaged value"); - return _VSTD::addressof(this->__get()); + return std::addressof(this->__get()); } _LIBCPP_HIDE_FROM_ABI @@ -1006,7 +1006,7 @@ public: operator->() { _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(this->has_value(), "optional operator-> called on a disengaged value"); - return _VSTD::addressof(this->__get()); + return std::addressof(this->__get()); } _LIBCPP_HIDE_FROM_ABI @@ -1033,7 +1033,7 @@ public: operator*() && noexcept { _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(this->has_value(), "optional operator* called on a disengaged value"); - return _VSTD::move(this->__get()); + return std::move(this->__get()); } _LIBCPP_HIDE_FROM_ABI @@ -1042,7 +1042,7 @@ public: operator*() const&& noexcept { _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(this->has_value(), "optional operator* called on a disengaged value"); - return _VSTD::move(this->__get()); + return std::move(this->__get()); } _LIBCPP_HIDE_FROM_ABI @@ -1075,7 +1075,7 @@ public: { if (!this->has_value()) __throw_bad_optional_access(); - return _VSTD::move(this->__get()); + return std::move(this->__get()); } _LIBCPP_HIDE_FROM_ABI @@ -1084,7 +1084,7 @@ public: { if (!this->has_value()) __throw_bad_optional_access(); - return _VSTD::move(this->__get()); + return std::move(this->__get()); } template @@ -1096,7 +1096,7 @@ public: static_assert(is_convertible_v<_Up, value_type>, "optional::value_or: U must be convertible to T"); return this->has_value() ? this->__get() : - static_cast(_VSTD::forward<_Up>(__v)); + static_cast(std::forward<_Up>(__v)); } template @@ -1107,8 +1107,8 @@ public: "optional::value_or: T must be move constructible"); static_assert(is_convertible_v<_Up, value_type>, "optional::value_or: U must be convertible to T"); - return this->has_value() ? _VSTD::move(this->__get()) : - static_cast(_VSTD::forward<_Up>(__v)); + return this->has_value() ? std::move(this->__get()) : + static_cast(std::forward<_Up>(__v)); } #if _LIBCPP_STD_VER >= 23 @@ -1119,7 +1119,7 @@ public: static_assert(__is_std_optional>::value, "Result of f(value()) must be a specialization of std::optional"); if (*this) - return _VSTD::invoke(_VSTD::forward<_Func>(__f), value()); + return std::invoke(std::forward<_Func>(__f), value()); return remove_cvref_t<_Up>(); } @@ -1130,7 +1130,7 @@ public: static_assert(__is_std_optional>::value, "Result of f(value()) must be a specialization of std::optional"); if (*this) - return _VSTD::invoke(_VSTD::forward<_Func>(__f), value()); + return std::invoke(std::forward<_Func>(__f), value()); return remove_cvref_t<_Up>(); } @@ -1141,7 +1141,7 @@ public: static_assert(__is_std_optional>::value, "Result of f(std::move(value())) must be a specialization of std::optional"); if (*this) - return _VSTD::invoke(_VSTD::forward<_Func>(__f), _VSTD::move(value())); + return std::invoke(std::forward<_Func>(__f), std::move(value())); return remove_cvref_t<_Up>(); } @@ -1152,7 +1152,7 @@ public: static_assert(__is_std_optional>::value, "Result of f(std::move(value())) must be a specialization of std::optional"); if (*this) - return _VSTD::invoke(_VSTD::forward<_Func>(__f), _VSTD::move(value())); + return std::invoke(std::forward<_Func>(__f), std::move(value())); return remove_cvref_t<_Up>(); } @@ -1167,7 +1167,7 @@ public: "Result of f(value()) should not be std::nullopt_t"); static_assert(is_object_v<_Up>, "Result of f(value()) should be an object type"); if (*this) - return optional<_Up>(__optional_construct_from_invoke_tag{}, _VSTD::forward<_Func>(__f), value()); + return optional<_Up>(__optional_construct_from_invoke_tag{}, std::forward<_Func>(__f), value()); return optional<_Up>(); } @@ -1182,7 +1182,7 @@ public: "Result of f(value()) should not be std::nullopt_t"); static_assert(is_object_v<_Up>, "Result of f(value()) should be an object type"); if (*this) - return optional<_Up>(__optional_construct_from_invoke_tag{}, _VSTD::forward<_Func>(__f), value()); + return optional<_Up>(__optional_construct_from_invoke_tag{}, std::forward<_Func>(__f), value()); return optional<_Up>(); } @@ -1197,7 +1197,7 @@ public: "Result of f(std::move(value())) should not be std::nullopt_t"); static_assert(is_object_v<_Up>, "Result of f(std::move(value())) should be an object type"); if (*this) - return optional<_Up>(__optional_construct_from_invoke_tag{}, _VSTD::forward<_Func>(__f), _VSTD::move(value())); + return optional<_Up>(__optional_construct_from_invoke_tag{}, std::forward<_Func>(__f), std::move(value())); return optional<_Up>(); } @@ -1212,7 +1212,7 @@ public: "Result of f(std::move(value())) should not be std::nullopt_t"); static_assert(is_object_v<_Up>, "Result of f(std::move(value())) should be an object type"); if (*this) - return optional<_Up>(__optional_construct_from_invoke_tag{}, _VSTD::forward<_Func>(__f), _VSTD::move(value())); + return optional<_Up>(__optional_construct_from_invoke_tag{}, std::forward<_Func>(__f), std::move(value())); return optional<_Up>(); } @@ -1223,7 +1223,7 @@ public: "Result of f() should be the same type as this optional"); if (*this) return *this; - return _VSTD::forward<_Func>(__f)(); + return std::forward<_Func>(__f)(); } template @@ -1232,8 +1232,8 @@ public: static_assert(is_same_v>, optional>, "Result of f() should be the same type as this optional"); if (*this) - return _VSTD::move(*this); - return _VSTD::forward<_Func>(__f)(); + return std::move(*this); + return std::forward<_Func>(__f)(); } #endif // _LIBCPP_STD_VER >= 23 @@ -1634,21 +1634,21 @@ template _LIBCPP_HIDE_FROM_ABI constexpr optional> make_optional(_Tp&& __v) { - return optional>(_VSTD::forward<_Tp>(__v)); + return optional>(std::forward<_Tp>(__v)); } template _LIBCPP_HIDE_FROM_ABI constexpr optional<_Tp> make_optional(_Args&&... __args) { - return optional<_Tp>(in_place, _VSTD::forward<_Args>(__args)...); + return optional<_Tp>(in_place, std::forward<_Args>(__args)...); } template _LIBCPP_HIDE_FROM_ABI constexpr optional<_Tp> make_optional(initializer_list<_Up> __il, _Args&&... __args) { - return optional<_Tp>(in_place, __il, _VSTD::forward<_Args>(__args)...); + return optional<_Tp>(in_place, __il, std::forward<_Args>(__args)...); } template diff --git a/libcxx/include/ostream b/libcxx/include/ostream index 9d7414d7b6f6..ef74f5ddc66c 100644 --- a/libcxx/include/ostream +++ b/libcxx/include/ostream @@ -792,7 +792,7 @@ template _LIBCPP_HIDE_FROM_ABI basic_ostream<_CharT, _Traits>& operator<<(basic_ostream<_CharT, _Traits>& __os, _CharT __c) { - return _VSTD::__put_character_sequence(__os, &__c, 1); + return std::__put_character_sequence(__os, &__c, 1); } template @@ -832,28 +832,28 @@ template _LIBCPP_HIDE_FROM_ABI basic_ostream& operator<<(basic_ostream& __os, char __c) { - return _VSTD::__put_character_sequence(__os, &__c, 1); + return std::__put_character_sequence(__os, &__c, 1); } template _LIBCPP_HIDE_FROM_ABI basic_ostream& operator<<(basic_ostream& __os, signed char __c) { - return _VSTD::__put_character_sequence(__os, (char *) &__c, 1); + return std::__put_character_sequence(__os, (char *) &__c, 1); } template _LIBCPP_HIDE_FROM_ABI basic_ostream& operator<<(basic_ostream& __os, unsigned char __c) { - return _VSTD::__put_character_sequence(__os, (char *) &__c, 1); + return std::__put_character_sequence(__os, (char *) &__c, 1); } template _LIBCPP_HIDE_FROM_ABI basic_ostream<_CharT, _Traits>& operator<<(basic_ostream<_CharT, _Traits>& __os, const _CharT* __str) { - return _VSTD::__put_character_sequence(__os, __str, _Traits::length(__str)); + return std::__put_character_sequence(__os, __str, _Traits::length(__str)); } template @@ -906,7 +906,7 @@ template _LIBCPP_HIDE_FROM_ABI basic_ostream& operator<<(basic_ostream& __os, const char* __str) { - return _VSTD::__put_character_sequence(__os, __str, _Traits::length(__str)); + return std::__put_character_sequence(__os, __str, _Traits::length(__str)); } template @@ -914,7 +914,7 @@ _LIBCPP_HIDE_FROM_ABI basic_ostream& operator<<(basic_ostream& __os, const signed char* __str) { const char *__s = (const char *) __str; - return _VSTD::__put_character_sequence(__os, __s, _Traits::length(__s)); + return std::__put_character_sequence(__os, __s, _Traits::length(__s)); } template @@ -922,7 +922,7 @@ _LIBCPP_HIDE_FROM_ABI basic_ostream& operator<<(basic_ostream& __os, const unsigned char* __str) { const char *__s = (const char *) __str; - return _VSTD::__put_character_sequence(__os, __s, _Traits::length(__s)); + return std::__put_character_sequence(__os, __s, _Traits::length(__s)); } template @@ -1081,7 +1081,7 @@ _LIBCPP_HIDE_FROM_ABI _Stream&& operator<<(_Stream&& __os, const _Tp& __x) { __os << __x; - return _VSTD::move(__os); + return std::move(__os); } template @@ -1089,7 +1089,7 @@ basic_ostream<_CharT, _Traits>& operator<<(basic_ostream<_CharT, _Traits>& __os, const basic_string<_CharT, _Traits, _Allocator>& __str) { - return _VSTD::__put_character_sequence(__os, __str.data(), __str.size()); + return std::__put_character_sequence(__os, __str.data(), __str.size()); } template @@ -1097,7 +1097,7 @@ _LIBCPP_HIDE_FROM_ABI basic_ostream<_CharT, _Traits>& operator<<(basic_ostream<_CharT, _Traits>& __os, basic_string_view<_CharT, _Traits> __sv) { - return _VSTD::__put_character_sequence(__os, __sv.data(), __sv.size()); + return std::__put_character_sequence(__os, __sv.data(), __sv.size()); } template diff --git a/libcxx/include/queue b/libcxx/include/queue index c091797e04a5..c9a4eb27a9a6 100644 --- a/libcxx/include/queue +++ b/libcxx/include/queue @@ -353,19 +353,19 @@ public: _LIBCPP_HIDE_FROM_ABI queue(queue&& __q) _NOEXCEPT_(is_nothrow_move_constructible::value) - : c(_VSTD::move(__q.c)) {} + : c(std::move(__q.c)) {} _LIBCPP_HIDE_FROM_ABI queue& operator=(queue&& __q) _NOEXCEPT_(is_nothrow_move_assignable::value) - {c = _VSTD::move(__q.c); return *this;} + {c = std::move(__q.c); return *this;} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI explicit queue(const container_type& __c) : c(__c) {} #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI - explicit queue(container_type&& __c) : c(_VSTD::move(__c)) {} + explicit queue(container_type&& __c) : c(std::move(__c)) {} #endif // _LIBCPP_CXX03_LANG template _LIBCPP_HIDE_FROM_ABI @@ -387,12 +387,12 @@ public: _LIBCPP_HIDE_FROM_ABI queue(container_type&& __c, const _Alloc& __a, __enable_if_t::value>* = 0) - : c(_VSTD::move(__c), __a) {} + : c(std::move(__c), __a) {} template _LIBCPP_HIDE_FROM_ABI queue(queue&& __q, const _Alloc& __a, __enable_if_t::value>* = 0) - : c(_VSTD::move(__q.c), __a) {} + : c(std::move(__q.c), __a) {} #endif // _LIBCPP_CXX03_LANG @@ -414,7 +414,7 @@ public: void push(const value_type& __v) {c.push_back(__v);} #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI - void push(value_type&& __v) {c.push_back(_VSTD::move(__v));} + void push(value_type&& __v) {c.push_back(std::move(__v));} #if _LIBCPP_STD_VER >= 23 template <_ContainerCompatibleRange<_Tp> _Range> @@ -434,10 +434,10 @@ public: _LIBCPP_HIDE_FROM_ABI #if _LIBCPP_STD_VER >= 17 decltype(auto) emplace(_Args&&... __args) - { return c.emplace_back(_VSTD::forward<_Args>(__args)...);} + { return c.emplace_back(std::forward<_Args>(__args)...);} #else void emplace(_Args&&... __args) - { c.emplace_back(_VSTD::forward<_Args>(__args)...);} + { c.emplace_back(std::forward<_Args>(__args)...);} #endif #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI @@ -447,7 +447,7 @@ public: void swap(queue& __q) _NOEXCEPT_(__is_nothrow_swappable::value) { - using _VSTD::swap; + using std::swap; swap(c, __q.c); } @@ -616,13 +616,13 @@ public: priority_queue(priority_queue&& __q) _NOEXCEPT_(is_nothrow_move_constructible::value && is_nothrow_move_constructible::value) - : c(_VSTD::move(__q.c)), comp(_VSTD::move(__q.comp)) {} + : c(std::move(__q.c)), comp(std::move(__q.comp)) {} _LIBCPP_HIDE_FROM_ABI priority_queue& operator=(priority_queue&& __q) _NOEXCEPT_(is_nothrow_move_assignable::value && is_nothrow_move_assignable::value) - {c = _VSTD::move(__q.c); comp = _VSTD::move(__q.comp); return *this;} + {c = std::move(__q.c); comp = std::move(__q.comp); return *this;} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI @@ -870,7 +870,7 @@ priority_queue<_Tp, _Container, _Compare>::priority_queue(const _Compare& __comp : c(__c), comp(__comp) { - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } #ifndef _LIBCPP_CXX03_LANG @@ -879,10 +879,10 @@ template inline priority_queue<_Tp, _Container, _Compare>::priority_queue(const value_compare& __comp, container_type&& __c) - : c(_VSTD::move(__c)), + : c(std::move(__c)), comp(__comp) { - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } #endif // _LIBCPP_CXX03_LANG @@ -895,7 +895,7 @@ priority_queue<_Tp, _Container, _Compare>::priority_queue(_InputIter __f, _Input : c(__f, __l), comp(__comp) { - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } template @@ -908,7 +908,7 @@ priority_queue<_Tp, _Container, _Compare>::priority_queue(_InputIter __f, _Input comp(__comp) { c.insert(c.end(), __f, __l); - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } #ifndef _LIBCPP_CXX03_LANG @@ -919,11 +919,11 @@ inline priority_queue<_Tp, _Container, _Compare>::priority_queue(_InputIter __f, _InputIter __l, const value_compare& __comp, container_type&& __c) - : c(_VSTD::move(__c)), + : c(std::move(__c)), comp(__comp) { c.insert(c.end(), __f, __l); - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } #endif // _LIBCPP_CXX03_LANG @@ -958,7 +958,7 @@ priority_queue<_Tp, _Container, _Compare>::priority_queue(const value_compare& _ : c(__c, __a), comp(__comp) { - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } template @@ -981,10 +981,10 @@ priority_queue<_Tp, _Container, _Compare>::priority_queue(const value_compare& _ container_type&& __c, const _Alloc& __a, __enable_if_t::value>*) - : c(_VSTD::move(__c), __a), + : c(std::move(__c), __a), comp(__comp) { - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } template @@ -993,8 +993,8 @@ inline priority_queue<_Tp, _Container, _Compare>::priority_queue(priority_queue&& __q, const _Alloc& __a, __enable_if_t::value>*) - : c(_VSTD::move(__q.c), __a), - comp(_VSTD::move(__q.comp)) + : c(std::move(__q.c), __a), + comp(std::move(__q.comp)) { } @@ -1009,7 +1009,7 @@ priority_queue<_Tp, _Container, _Compare>::priority_queue( : c(__f, __l, __a), comp() { - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } template @@ -1022,7 +1022,7 @@ priority_queue<_Tp, _Container, _Compare>::priority_queue( : c(__f, __l, __a), comp(__comp) { - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } template @@ -1036,7 +1036,7 @@ priority_queue<_Tp, _Container, _Compare>::priority_queue( comp(__comp) { c.insert(c.end(), __f, __l); - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } #ifndef _LIBCPP_CXX03_LANG @@ -1047,11 +1047,11 @@ priority_queue<_Tp, _Container, _Compare>::priority_queue( _InputIter __f, _InputIter __l, const value_compare& __comp, container_type&& __c, const _Alloc& __a, __enable_if_t::value>*) - : c(_VSTD::move(__c), __a), + : c(std::move(__c), __a), comp(__comp) { c.insert(c.end(), __f, __l); - _VSTD::make_heap(c.begin(), c.end(), comp); + std::make_heap(c.begin(), c.end(), comp); } #endif // _LIBCPP_CXX03_LANG @@ -1061,7 +1061,7 @@ void priority_queue<_Tp, _Container, _Compare>::push(const value_type& __v) { c.push_back(__v); - _VSTD::push_heap(c.begin(), c.end(), comp); + std::push_heap(c.begin(), c.end(), comp); } #ifndef _LIBCPP_CXX03_LANG @@ -1071,8 +1071,8 @@ inline void priority_queue<_Tp, _Container, _Compare>::push(value_type&& __v) { - c.push_back(_VSTD::move(__v)); - _VSTD::push_heap(c.begin(), c.end(), comp); + c.push_back(std::move(__v)); + std::push_heap(c.begin(), c.end(), comp); } template @@ -1081,8 +1081,8 @@ inline void priority_queue<_Tp, _Container, _Compare>::emplace(_Args&&... __args) { - c.emplace_back(_VSTD::forward<_Args>(__args)...); - _VSTD::push_heap(c.begin(), c.end(), comp); + c.emplace_back(std::forward<_Args>(__args)...); + std::push_heap(c.begin(), c.end(), comp); } #endif // _LIBCPP_CXX03_LANG @@ -1092,7 +1092,7 @@ inline void priority_queue<_Tp, _Container, _Compare>::pop() { - _VSTD::pop_heap(c.begin(), c.end(), comp); + std::pop_heap(c.begin(), c.end(), comp); c.pop_back(); } @@ -1103,7 +1103,7 @@ priority_queue<_Tp, _Container, _Compare>::swap(priority_queue& __q) _NOEXCEPT_(__is_nothrow_swappable::value && __is_nothrow_swappable::value) { - using _VSTD::swap; + using std::swap; swap(c, __q.c); swap(comp, __q.comp); } diff --git a/libcxx/include/regex b/libcxx/include/regex index 4424af8d37db..fcdd85f8c499 100644 --- a/libcxx/include/regex +++ b/libcxx/include/regex @@ -1470,7 +1470,7 @@ class __node __node(const __node&); __node& operator=(const __node&); public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __node() {} @@ -1490,7 +1490,7 @@ class __end_state : public __node<_CharT> { public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __end_state() {} @@ -1555,7 +1555,7 @@ class __empty_state typedef __owns_one_state<_CharT> base; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __empty_state(__node<_CharT>* __s) @@ -1581,7 +1581,7 @@ class __empty_non_own_state typedef __has_one_state<_CharT> base; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __empty_non_own_state(__node<_CharT>* __s) @@ -1607,7 +1607,7 @@ class __repeat_one_loop typedef __has_one_state<_CharT> base; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __repeat_one_loop(__node<_CharT>* __s) @@ -1669,7 +1669,7 @@ class __loop bool __greedy_; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __loop(unsigned __loop_id, @@ -1768,7 +1768,7 @@ class __alternate typedef __owns_two_states<_CharT> base; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __alternate(__owns_one_state<_CharT>* __s1, @@ -1807,7 +1807,7 @@ class __begin_marked_subexpression unsigned __mexp_; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __begin_marked_subexpression(unsigned __mexp, __node<_CharT>* __s) @@ -1835,7 +1835,7 @@ class __end_marked_subexpression unsigned __mexp_; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __end_marked_subexpression(unsigned __mexp, __node<_CharT>* __s) @@ -1864,7 +1864,7 @@ class __back_ref unsigned __mexp_; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __back_ref(unsigned __mexp, __node<_CharT>* __s) @@ -1884,7 +1884,7 @@ __back_ref<_CharT>::__exec(__state& __s) const { ptrdiff_t __len = __sm.second - __sm.first; if (__s.__last_ - __s.__current_ >= __len && - _VSTD::equal(__sm.first, __sm.second, __s.__current_)) + std::equal(__sm.first, __sm.second, __s.__current_)) { __s.__do_ = __state::__accept_but_not_consume; __s.__current_ += __len; @@ -1914,7 +1914,7 @@ class __back_ref_icase _Traits __traits_; unsigned __mexp_; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __back_ref_icase(const _Traits& __traits, unsigned __mexp, @@ -1969,7 +1969,7 @@ class __back_ref_collate _Traits __traits_; unsigned __mexp_; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __back_ref_collate(const _Traits& __traits, unsigned __mexp, @@ -2024,7 +2024,7 @@ class __word_boundary _Traits __traits_; bool __invert_; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI explicit __word_boundary(const _Traits& __traits, bool __invert, @@ -2101,7 +2101,7 @@ class __l_anchor_multiline bool __multiline_; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __l_anchor_multiline(bool __multiline, __node<_CharT>* __s) @@ -2122,7 +2122,7 @@ __l_anchor_multiline<_CharT>::__exec(__state& __s) const } else if (__multiline_ && !__s.__at_first_ && - std::__is_eol(*_VSTD::prev(__s.__current_))) + std::__is_eol(*std::prev(__s.__current_))) { __s.__do_ = __state::__accept_but_not_consume; __s.__node_ = this->first(); @@ -2145,7 +2145,7 @@ class __r_anchor_multiline bool __multiline_; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __r_anchor_multiline(bool __multiline, __node<_CharT>* __s) @@ -2185,7 +2185,7 @@ class __match_any typedef __owns_one_state<_CharT> base; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __match_any(__node<_CharT>* __s) @@ -2220,7 +2220,7 @@ class __match_any_but_newline typedef __owns_one_state<_CharT> base; public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __match_any_but_newline(__node<_CharT>* __s) @@ -2247,7 +2247,7 @@ class __match_char __match_char(const __match_char&); __match_char& operator=(const __match_char&); public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __match_char(_CharT __c, __node<_CharT>* __s) @@ -2287,7 +2287,7 @@ class __match_char_icase __match_char_icase(const __match_char_icase&); __match_char_icase& operator=(const __match_char_icase&); public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __match_char_icase(const _Traits& __traits, _CharT __c, __node<_CharT>* __s) @@ -2328,7 +2328,7 @@ class __match_char_collate __match_char_collate(const __match_char_collate&); __match_char_collate& operator=(const __match_char_collate&); public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __match_char_collate(const _Traits& __traits, _CharT __c, __node<_CharT>* __s) @@ -2380,7 +2380,7 @@ class __bracket_expression __bracket_expression(const __bracket_expression&); __bracket_expression& operator=(const __bracket_expression&); public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __bracket_expression(const _Traits& __traits, __node<_CharT>* __s, @@ -2446,7 +2446,7 @@ public: __b[0] = __traits_.translate_nocase(__b[0]); __e[0] = __traits_.translate_nocase(__e[0]); } - __ranges_.push_back(std::make_pair(_VSTD::move(__b), _VSTD::move(__e))); + __ranges_.push_back(std::make_pair(std::move(__b), std::move(__e))); } } _LIBCPP_HIDE_FROM_ABI @@ -2483,7 +2483,7 @@ __bracket_expression<_CharT, _Traits>::__exec(__state& __s) const ++__consumed; if (__might_have_digraph_) { - const _CharT* __next = _VSTD::next(__s.__current_); + const _CharT* __next = std::next(__s.__current_); if (__next != __s.__last_) { pair<_CharT, _CharT> __ch2(*__s.__current_, *__next); @@ -2577,7 +2577,7 @@ __bracket_expression<_CharT, _Traits>::__exec(__state& __s) const { const bool __in_neg_mask = __traits_.isctype(__ch, __neg_mask_); const bool __in_neg_chars = - _VSTD::find(__neg_chars_.begin(), __neg_chars_.end(), __ch) != + std::find(__neg_chars_.begin(), __neg_chars_.end(), __ch) != __neg_chars_.end(); if (!(__in_neg_mask || __in_neg_chars)) { @@ -2667,8 +2667,8 @@ private: shared_ptr<__empty_state<_CharT> > __start_; __owns_one_state<_CharT>* __end_; - typedef _VSTD::__state<_CharT> __state; - typedef _VSTD::__node<_CharT> __node; + typedef std::__state<_CharT> __state; + typedef std::__node<_CharT> __node; public: // constants: @@ -2762,7 +2762,7 @@ public: #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI basic_regex& assign(basic_regex&& __that) _NOEXCEPT - {return *this = _VSTD::move(__that);} + {return *this = std::move(__that);} #endif _LIBCPP_HIDE_FROM_ABI basic_regex& assign(const value_type* __p, flag_type __f = regex_constants::ECMAScript) @@ -3137,7 +3137,7 @@ template void basic_regex<_CharT, _Traits>::swap(basic_regex& __r) { - using _VSTD::swap; + using std::swap; swap(__traits_, __r.__traits_); swap(__flags_, __r.__flags_); swap(__marked_count_, __r.__marked_count_); @@ -3170,7 +3170,7 @@ class __lookahead __lookahead(const __lookahead&); __lookahead& operator=(const __lookahead&); public: - typedef _VSTD::__state<_CharT> __state; + typedef std::__state<_CharT> __state; _LIBCPP_HIDE_FROM_ABI __lookahead(const basic_regex<_CharT, _Traits>& __exp, bool __invert, __node<_CharT>* __s, unsigned __mexp) @@ -3271,7 +3271,7 @@ basic_regex<_CharT, _Traits>::__parse_basic_reg_exp(_ForwardIterator __first, __first = __parse_RE_expression(__first, __last); if (__first != __last) { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp == __last && *__first == '$') { __push_r_anchor(); @@ -3488,7 +3488,7 @@ basic_regex<_CharT, _Traits>::__parse_Back_open_paren(_ForwardIterator __first, { if (__first != __last) { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last) { if (*__first == '\\' && *__temp == '(') @@ -3506,7 +3506,7 @@ basic_regex<_CharT, _Traits>::__parse_Back_close_paren(_ForwardIterator __first, { if (__first != __last) { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last) { if (*__first == '\\' && *__temp == ')') @@ -3524,7 +3524,7 @@ basic_regex<_CharT, _Traits>::__parse_Back_open_brace(_ForwardIterator __first, { if (__first != __last) { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last) { if (*__first == '\\' && *__temp == '{') @@ -3542,7 +3542,7 @@ basic_regex<_CharT, _Traits>::__parse_Back_close_brace(_ForwardIterator __first, { if (__first != __last) { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last) { if (*__first == '\\' && *__temp == '}') @@ -3560,7 +3560,7 @@ basic_regex<_CharT, _Traits>::__parse_BACKREF(_ForwardIterator __first, { if (__first != __last) { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last && *__first == '\\' && __test_back_ref(*__temp)) __first = ++__temp; } @@ -3575,7 +3575,7 @@ basic_regex<_CharT, _Traits>::__parse_ORD_CHAR(_ForwardIterator __first, { if (__first != __last) { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp == __last && *__first == '$') return __first; // Not called inside a bracket @@ -3633,7 +3633,7 @@ basic_regex<_CharT, _Traits>::__parse_QUOTED_CHAR(_ForwardIterator __first, { if (__first != __last) { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last) { if (*__first == '\\') @@ -3664,7 +3664,7 @@ basic_regex<_CharT, _Traits>::__parse_QUOTED_CHAR_ERE(_ForwardIterator __first, { if (__first != __last) { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last) { if (*__first == '\\') @@ -3945,7 +3945,7 @@ basic_regex<_CharT, _Traits>::__parse_expression_term(_ForwardIterator __first, { if (__first != __last && *__first != ']') { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); basic_string<_CharT> __start_range; if (__temp != __last && *__first == '[') { @@ -3974,7 +3974,7 @@ basic_regex<_CharT, _Traits>::__parse_expression_term(_ForwardIterator __first, } if (__first != __last && *__first != ']') { - __temp = _VSTD::next(__first); + __temp = std::next(__first); if (__temp != __last && *__first == '-' && *__temp != ']') { // parse a range @@ -4000,7 +4000,7 @@ basic_regex<_CharT, _Traits>::__parse_expression_term(_ForwardIterator __first, ++__first; } } - __ml->__add_range(_VSTD::move(__start_range), _VSTD::move(__end_range)); + __ml->__add_range(std::move(__start_range), std::move(__end_range)); } else if (!__start_range.empty()) { @@ -4155,7 +4155,7 @@ basic_regex<_CharT, _Traits>::__parse_equivalence_class(_ForwardIterator __first // Found [= // This means =] must exist value_type __equal_close[2] = {'=', ']'}; - _ForwardIterator __temp = _VSTD::search(__first, __last, __equal_close, + _ForwardIterator __temp = std::search(__first, __last, __equal_close, __equal_close+2); if (__temp == __last) __throw_regex_error(); @@ -4183,7 +4183,7 @@ basic_regex<_CharT, _Traits>::__parse_equivalence_class(_ForwardIterator __first __throw_regex_error(); } } - __first = _VSTD::next(__temp, 2); + __first = std::next(__temp, 2); return __first; } @@ -4197,7 +4197,7 @@ basic_regex<_CharT, _Traits>::__parse_character_class(_ForwardIterator __first, // Found [: // This means :] must exist value_type __colon_close[2] = {':', ']'}; - _ForwardIterator __temp = _VSTD::search(__first, __last, __colon_close, + _ForwardIterator __temp = std::search(__first, __last, __colon_close, __colon_close+2); if (__temp == __last) __throw_regex_error(); @@ -4208,7 +4208,7 @@ basic_regex<_CharT, _Traits>::__parse_character_class(_ForwardIterator __first, if (__class_type == 0) __throw_regex_error(); __ml->__add_class(__class_type); - __first = _VSTD::next(__temp, 2); + __first = std::next(__temp, 2); return __first; } @@ -4222,7 +4222,7 @@ basic_regex<_CharT, _Traits>::__parse_collating_symbol(_ForwardIterator __first, // Found [. // This means .] must exist value_type __dot_close[2] = {'.', ']'}; - _ForwardIterator __temp = _VSTD::search(__first, __last, __dot_close, + _ForwardIterator __temp = std::search(__first, __last, __dot_close, __dot_close+2); if (__temp == __last) __throw_regex_error(); @@ -4236,7 +4236,7 @@ basic_regex<_CharT, _Traits>::__parse_collating_symbol(_ForwardIterator __first, default: __throw_regex_error(); } - __first = _VSTD::next(__temp, 2); + __first = std::next(__temp, 2); return __first; } @@ -4347,7 +4347,7 @@ basic_regex<_CharT, _Traits>::__parse_assertion(_ForwardIterator __first, break; case '\\': { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last) { if (*__temp == 'b') @@ -4365,7 +4365,7 @@ basic_regex<_CharT, _Traits>::__parse_assertion(_ForwardIterator __first, break; case '(': { - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last && *__temp == '?') { if (++__temp != __last) @@ -4378,7 +4378,7 @@ basic_regex<_CharT, _Traits>::__parse_assertion(_ForwardIterator __first, __exp.__flags_ = __flags_; __temp = __exp.__parse(++__temp, __last); unsigned __mexp = __exp.__marked_count_; - __push_lookahead(_VSTD::move(__exp), false, __marked_count_); + __push_lookahead(std::move(__exp), false, __marked_count_); __marked_count_ += __mexp; if (__temp == __last || *__temp != ')') __throw_regex_error(); @@ -4391,7 +4391,7 @@ basic_regex<_CharT, _Traits>::__parse_assertion(_ForwardIterator __first, __exp.__flags_ = __flags_; __temp = __exp.__parse(++__temp, __last); unsigned __mexp = __exp.__marked_count_; - __push_lookahead(_VSTD::move(__exp), true, __marked_count_); + __push_lookahead(std::move(__exp), true, __marked_count_); __marked_count_ += __mexp; if (__temp == __last || *__temp != ')') __throw_regex_error(); @@ -4433,7 +4433,7 @@ basic_regex<_CharT, _Traits>::__parse_atom(_ForwardIterator __first, ++__first; if (__first == __last) __throw_regex_error(); - _ForwardIterator __temp = _VSTD::next(__first); + _ForwardIterator __temp = std::next(__first); if (__temp != __last && *__first == '?' && *__temp == ':') { ++__open_count_; @@ -4479,7 +4479,7 @@ basic_regex<_CharT, _Traits>::__parse_atom_escape(_ForwardIterator __first, { if (__first != __last && *__first == '\\') { - _ForwardIterator __t1 = _VSTD::next(__first); + _ForwardIterator __t1 = std::next(__first); if (__t1 == __last) __throw_regex_error(); @@ -4631,7 +4631,7 @@ basic_regex<_CharT, _Traits>::__parse_character_escape(_ForwardIterator __first, ++__first; break; case 'c': - if ((__t = _VSTD::next(__first)) != __last) + if ((__t = std::next(__first)) != __last) { if (('A' <= *__t && *__t <= 'Z') || ('a' <= *__t && *__t <= 'z')) @@ -4750,7 +4750,7 @@ basic_regex<_CharT, _Traits>::__parse_grep(_ForwardIterator __first, _ForwardIterator __last) { __owns_one_state<_CharT>* __sa = __end_; - _ForwardIterator __t1 = _VSTD::find(__first, __last, _CharT('\n')); + _ForwardIterator __t1 = std::find(__first, __last, _CharT('\n')); if (__t1 != __first) __parse_basic_reg_exp(__first, __t1); else @@ -4760,7 +4760,7 @@ basic_regex<_CharT, _Traits>::__parse_grep(_ForwardIterator __first, ++__first; while (__first != __last) { - __t1 = _VSTD::find(__first, __last, _CharT('\n')); + __t1 = std::find(__first, __last, _CharT('\n')); __owns_one_state<_CharT>* __sb = __end_; if (__t1 != __first) __parse_basic_reg_exp(__first, __t1); @@ -4781,7 +4781,7 @@ basic_regex<_CharT, _Traits>::__parse_egrep(_ForwardIterator __first, _ForwardIterator __last) { __owns_one_state<_CharT>* __sa = __end_; - _ForwardIterator __t1 = _VSTD::find(__first, __last, _CharT('\n')); + _ForwardIterator __t1 = std::find(__first, __last, _CharT('\n')); if (__t1 != __first) __parse_extended_reg_exp(__first, __t1); else @@ -4791,7 +4791,7 @@ basic_regex<_CharT, _Traits>::__parse_egrep(_ForwardIterator __first, ++__first; while (__first != __last) { - __t1 = _VSTD::find(__first, __last, _CharT('\n')); + __t1 = std::find(__first, __last, _CharT('\n')); __owns_one_state<_CharT>* __sb = __end_; if (__t1 != __first) __parse_extended_reg_exp(__first, __t1); @@ -5015,7 +5015,7 @@ public: _LIBCPP_HIDE_FROM_ABI difference_type length() const - {return matched ? _VSTD::distance(this->first, this->second) : 0;} + {return matched ? std::distance(this->first, this->second) : 0;} _LIBCPP_HIDE_FROM_ABI string_type str() const {return matched ? string_type(this->first, this->second) : string_type();} @@ -5536,7 +5536,7 @@ public: difference_type position(size_type __sub = 0) const { _LIBCPP_ASSERT_UNCATEGORIZED(ready(), "match_results::position() called when not ready"); - return _VSTD::distance(__position_start_, (*this)[__sub].first); + return std::distance(__position_start_, (*this)[__sub].first); } _LIBCPP_HIDE_FROM_ABI string_type str(size_type __sub = 0) const @@ -5623,18 +5623,18 @@ public: __matches_.resize(__m.size()); for (size_type __i = 0; __i < __matches_.size(); ++__i) { - __matches_[__i].first = _VSTD::next(__f, _VSTD::distance(__mf, __m[__i].first)); - __matches_[__i].second = _VSTD::next(__f, _VSTD::distance(__mf, __m[__i].second)); + __matches_[__i].first = std::next(__f, std::distance(__mf, __m[__i].first)); + __matches_[__i].second = std::next(__f, std::distance(__mf, __m[__i].second)); __matches_[__i].matched = __m[__i].matched; } __unmatched_.first = __l; __unmatched_.second = __l; __unmatched_.matched = false; - __prefix_.first = _VSTD::next(__f, _VSTD::distance(__mf, __m.prefix().first)); - __prefix_.second = _VSTD::next(__f, _VSTD::distance(__mf, __m.prefix().second)); + __prefix_.first = std::next(__f, std::distance(__mf, __m.prefix().first)); + __prefix_.second = std::next(__f, std::distance(__mf, __m.prefix().second)); __prefix_.matched = __m.prefix().matched; - __suffix_.first = _VSTD::next(__f, _VSTD::distance(__mf, __m.suffix().first)); - __suffix_.second = _VSTD::next(__f, _VSTD::distance(__mf, __m.suffix().second)); + __suffix_.first = std::next(__f, std::distance(__mf, __m.suffix().first)); + __suffix_.second = std::next(__f, std::distance(__mf, __m.suffix().second)); __suffix_.matched = __m.suffix().matched; if (!__no_update_pos) __position_start_ = __prefix_.first; @@ -5706,7 +5706,7 @@ match_results<_BidirectionalIterator, _Allocator>::format(_OutputIter __output_i for (; __fmt_first != __fmt_last; ++__fmt_first) { if (*__fmt_first == '&') - __output_iter = _VSTD::copy(__matches_[0].first, __matches_[0].second, + __output_iter = std::copy(__matches_[0].first, __matches_[0].second, __output_iter); else if (*__fmt_first == '\\' && __fmt_first + 1 != __fmt_last) { @@ -5714,7 +5714,7 @@ match_results<_BidirectionalIterator, _Allocator>::format(_OutputIter __output_i if ('0' <= *__fmt_first && *__fmt_first <= '9') { size_t __i = *__fmt_first - '0'; - __output_iter = _VSTD::copy((*this)[__i].first, + __output_iter = std::copy((*this)[__i].first, (*this)[__i].second, __output_iter); } else @@ -5744,16 +5744,16 @@ match_results<_BidirectionalIterator, _Allocator>::format(_OutputIter __output_i break; case '&': ++__fmt_first; - __output_iter = _VSTD::copy(__matches_[0].first, __matches_[0].second, + __output_iter = std::copy(__matches_[0].first, __matches_[0].second, __output_iter); break; case '`': ++__fmt_first; - __output_iter = _VSTD::copy(__prefix_.first, __prefix_.second, __output_iter); + __output_iter = std::copy(__prefix_.first, __prefix_.second, __output_iter); break; case '\'': ++__fmt_first; - __output_iter = _VSTD::copy(__suffix_.first, __suffix_.second, __output_iter); + __output_iter = std::copy(__suffix_.first, __suffix_.second, __output_iter); break; default: if ('0' <= __fmt_first[1] && __fmt_first[1] <= '9') @@ -5768,7 +5768,7 @@ match_results<_BidirectionalIterator, _Allocator>::format(_OutputIter __output_i __throw_regex_error(); __idx = 10 * __idx + *__fmt_first - '0'; } - __output_iter = _VSTD::copy((*this)[__idx].first, + __output_iter = std::copy((*this)[__idx].first, (*this)[__idx].second, __output_iter); } else @@ -5793,7 +5793,7 @@ template void match_results<_BidirectionalIterator, _Allocator>::swap(match_results& __m) { - using _VSTD::swap; + using std::swap; swap(__matches_, __m.__matches_); swap(__unmatched_, __m.__unmatched_); swap(__prefix_, __m.__prefix_); @@ -5892,7 +5892,7 @@ basic_regex<_CharT, _Traits>::__match_at_start_ecma( break; } __m.__matches_[0].first = __first; - __m.__matches_[0].second = _VSTD::next(__first, __s.__current_ - __first); + __m.__matches_[0].second = std::next(__first, __s.__current_ - __first); __m.__matches_[0].matched = true; for (unsigned __i = 0; __i < __s.__sub_matches_.size(); ++__i) __m.__matches_[__i+1] = __s.__sub_matches_[__i]; @@ -5906,7 +5906,7 @@ basic_regex<_CharT, _Traits>::__match_at_start_ecma( __state __snext = __s; __s.__node_->__exec_split(true, __s); __snext.__node_->__exec_split(false, __snext); - __states.push_back(_VSTD::move(__snext)); + __states.push_back(std::move(__snext)); } break; case __state::__reject: @@ -5932,7 +5932,7 @@ basic_regex<_CharT, _Traits>::__match_at_start_posix_nosubs( { deque<__state> __states; ptrdiff_t __highest_j = 0; - ptrdiff_t __np = _VSTD::distance(__first, __last); + ptrdiff_t __np = std::distance(__first, __last); __node* __st = __start_.get(); if (__st) { @@ -5983,7 +5983,7 @@ basic_regex<_CharT, _Traits>::__match_at_start_posix_nosubs( case __state::__consume_input: break; case __state::__accept_and_consume: - __states.push_front(_VSTD::move(__s)); + __states.push_front(std::move(__s)); __states.pop_back(); break; case __state::__repeat: @@ -5994,7 +5994,7 @@ basic_regex<_CharT, _Traits>::__match_at_start_posix_nosubs( __state __snext = __s; __s.__node_->__exec_split(true, __s); __snext.__node_->__exec_split(false, __snext); - __states.push_back(_VSTD::move(__snext)); + __states.push_back(std::move(__snext)); } break; case __state::__reject: @@ -6008,7 +6008,7 @@ basic_regex<_CharT, _Traits>::__match_at_start_posix_nosubs( if (__matched) { __m.__matches_[0].first = __first; - __m.__matches_[0].second = _VSTD::next(__first, __highest_j); + __m.__matches_[0].second = std::next(__first, __highest_j); __m.__matches_[0].matched = true; return true; } @@ -6027,7 +6027,7 @@ basic_regex<_CharT, _Traits>::__match_at_start_posix_subs( vector<__state> __states; __state __best_state; ptrdiff_t __highest_j = 0; - ptrdiff_t __np = _VSTD::distance(__first, __last); + ptrdiff_t __np = std::distance(__first, __last); __node* __st = __start_.get(); if (__st) { @@ -6093,7 +6093,7 @@ basic_regex<_CharT, _Traits>::__match_at_start_posix_subs( __state __snext = __s; __s.__node_->__exec_split(true, __s); __snext.__node_->__exec_split(false, __snext); - __states.push_back(_VSTD::move(__snext)); + __states.push_back(std::move(__snext)); } break; case __state::__reject: @@ -6107,7 +6107,7 @@ basic_regex<_CharT, _Traits>::__match_at_start_posix_subs( if (__matched) { __m.__matches_[0].first = __first; - __m.__matches_[0].second = _VSTD::next(__first, __highest_j); + __m.__matches_[0].second = std::next(__first, __highest_j); __m.__matches_[0].matched = true; for (unsigned __i = 0; __i < __best_state.__sub_matches_.size(); ++__i) __m.__matches_[__i+1] = __best_state.__sub_matches_[__i]; @@ -6184,7 +6184,7 @@ regex_search(_BidirectionalIterator __first, _BidirectionalIterator __last, regex_constants::match_flag_type __flags = regex_constants::match_default) { int __offset = (__flags & regex_constants::match_prev_avail) ? 1 : 0; - basic_string<_CharT> __s(_VSTD::prev(__first, __offset), __last); + basic_string<_CharT> __s(std::prev(__first, __offset), __last); match_results __mc; bool __r = __e.__search(__s.data() + __offset, __s.data() + __s.size(), __mc, __flags); __m.__assign(__first, __last, __mc, __flags & regex_constants::__no_update_pos); @@ -6257,7 +6257,7 @@ regex_search(const _CharT* __str, const basic_regex<_CharT, _Traits>& __e, regex_constants::match_flag_type __flags = regex_constants::match_default) { match_results __m; - return _VSTD::regex_search(__str, __m, __e, __flags); + return std::regex_search(__str, __m, __e, __flags); } template @@ -6303,7 +6303,7 @@ regex_match(_BidirectionalIterator __first, _BidirectionalIterator __last, const basic_regex<_CharT, _Traits>& __e, regex_constants::match_flag_type __flags = regex_constants::match_default) { - bool __r = _VSTD::regex_search( + bool __r = std::regex_search( __first, __last, __m, __e, __flags | regex_constants::match_continuous | regex_constants::__full_match); @@ -6324,7 +6324,7 @@ regex_match(_BidirectionalIterator __first, _BidirectionalIterator __last, regex_constants::match_flag_type __flags = regex_constants::match_default) { match_results<_BidirectionalIterator> __m; - return _VSTD::regex_match(__first, __last, __m, __e, __flags); + return std::regex_match(__first, __last, __m, __e, __flags); } template @@ -6334,7 +6334,7 @@ regex_match(const _CharT* __str, match_results& __m, const basic_regex<_CharT, _Traits>& __e, regex_constants::match_flag_type __flags = regex_constants::match_default) { - return _VSTD::regex_match(__str, __str + _Traits::length(__str), __m, __e, __flags); + return std::regex_match(__str, __str + _Traits::length(__str), __m, __e, __flags); } template @@ -6345,7 +6345,7 @@ regex_match(const basic_string<_CharT, _ST, _SA>& __s, const basic_regex<_CharT, _Traits>& __e, regex_constants::match_flag_type __flags = regex_constants::match_default) { - return _VSTD::regex_match(__s.begin(), __s.end(), __m, __e, __flags); + return std::regex_match(__s.begin(), __s.end(), __m, __e, __flags); } #if _LIBCPP_STD_VER >= 14 @@ -6364,7 +6364,7 @@ bool regex_match(const _CharT* __str, const basic_regex<_CharT, _Traits>& __e, regex_constants::match_flag_type __flags = regex_constants::match_default) { - return _VSTD::regex_match(__str, __str + _Traits::length(__str), __e, __flags); + return std::regex_match(__str, __str + _Traits::length(__str), __e, __flags); } template @@ -6374,7 +6374,7 @@ regex_match(const basic_string<_CharT, _ST, _SA>& __s, const basic_regex<_CharT, _Traits>& __e, regex_constants::match_flag_type __flags = regex_constants::match_default) { - return _VSTD::regex_match(__s.begin(), __s.end(), __e, __flags); + return std::regex_match(__s.begin(), __s.end(), __e, __flags); } // regex_iterator @@ -6440,7 +6440,7 @@ public: _LIBCPP_HIDE_FROM_ABI reference operator*() const {return __match_;} _LIBCPP_HIDE_FROM_ABI - pointer operator->() const {return _VSTD::addressof(__match_);} + pointer operator->() const {return std::addressof(__match_);} regex_iterator& operator++(); _LIBCPP_HIDE_FROM_ABI @@ -6464,10 +6464,10 @@ regex_iterator<_BidirectionalIterator, _CharT, _Traits>:: const regex_type& __re, regex_constants::match_flag_type __m) : __begin_(__a), __end_(__b), - __pregex_(_VSTD::addressof(__re)), + __pregex_(std::addressof(__re)), __flags_(__m) { - _VSTD::regex_search(__begin_, __end_, __match_, *__pregex_, __flags_); + std::regex_search(__begin_, __end_, __match_, *__pregex_, __flags_); } template @@ -6499,7 +6499,7 @@ regex_iterator<_BidirectionalIterator, _CharT, _Traits>::operator++() __match_ = value_type(); return *this; } - else if (_VSTD::regex_search(__start, __end_, __match_, *__pregex_, + else if (std::regex_search(__start, __end_, __match_, *__pregex_, __flags_ | regex_constants::match_not_null | regex_constants::match_continuous)) return *this; @@ -6507,7 +6507,7 @@ regex_iterator<_BidirectionalIterator, _CharT, _Traits>::operator++() ++__start; } __flags_ |= regex_constants::match_prev_avail; - if (!_VSTD::regex_search(__start, __end_, __match_, *__pregex_, __flags_)) + if (!std::regex_search(__start, __end_, __match_, *__pregex_, __flags_)) __match_ = value_type(); return *this; } @@ -6803,7 +6803,7 @@ regex_token_iterator<_BidirectionalIterator, _CharT, _Traits>::operator++() __establish_result(); else { - if (_VSTD::find(__subs_.begin(), __subs_.end(), -1) != __subs_.end() + if (std::find(__subs_.begin(), __subs_.end(), -1) != __subs_.end() && __prev->suffix().length() != 0) { __suffix_.matched = true; @@ -6834,7 +6834,7 @@ regex_replace(_OutputIterator __output_iter, if (__i == __eof) { if (!(__flags & regex_constants::format_no_copy)) - __output_iter = _VSTD::copy(__first, __last, __output_iter); + __output_iter = std::copy(__first, __last, __output_iter); } else { @@ -6842,14 +6842,14 @@ regex_replace(_OutputIterator __output_iter, for (size_t __len = char_traits<_CharT>::length(__fmt); __i != __eof; ++__i) { if (!(__flags & regex_constants::format_no_copy)) - __output_iter = _VSTD::copy(__i->prefix().first, __i->prefix().second, __output_iter); + __output_iter = std::copy(__i->prefix().first, __i->prefix().second, __output_iter); __output_iter = __i->format(__output_iter, __fmt, __fmt + __len, __flags); __lm = __i->suffix(); if (__flags & regex_constants::format_first_only) break; } if (!(__flags & regex_constants::format_no_copy)) - __output_iter = _VSTD::copy(__lm.first, __lm.second, __output_iter); + __output_iter = std::copy(__lm.first, __lm.second, __output_iter); } return __output_iter; } @@ -6864,7 +6864,7 @@ regex_replace(_OutputIterator __output_iter, const basic_string<_CharT, _ST, _SA>& __fmt, regex_constants::match_flag_type __flags = regex_constants::match_default) { - return _VSTD::regex_replace(__output_iter, __first, __last, __e, __fmt.c_str(), __flags); + return std::regex_replace(__output_iter, __first, __last, __e, __fmt.c_str(), __flags); } template & __s, regex_constants::match_flag_type __flags = regex_constants::match_default) { basic_string<_CharT, _ST, _SA> __r; - _VSTD::regex_replace(std::back_inserter(__r), __s.begin(), __s.end(), __e, + std::regex_replace(std::back_inserter(__r), __s.begin(), __s.end(), __e, __fmt.c_str(), __flags); return __r; } @@ -6890,7 +6890,7 @@ regex_replace(const basic_string<_CharT, _ST, _SA>& __s, regex_constants::match_flag_type __flags = regex_constants::match_default) { basic_string<_CharT, _ST, _SA> __r; - _VSTD::regex_replace(std::back_inserter(__r), __s.begin(), __s.end(), __e, + std::regex_replace(std::back_inserter(__r), __s.begin(), __s.end(), __e, __fmt, __flags); return __r; } @@ -6904,7 +6904,7 @@ regex_replace(const _CharT* __s, regex_constants::match_flag_type __flags = regex_constants::match_default) { basic_string<_CharT> __r; - _VSTD::regex_replace(std::back_inserter(__r), __s, + std::regex_replace(std::back_inserter(__r), __s, __s + char_traits<_CharT>::length(__s), __e, __fmt.c_str(), __flags); return __r; @@ -6919,7 +6919,7 @@ regex_replace(const _CharT* __s, regex_constants::match_flag_type __flags = regex_constants::match_default) { basic_string<_CharT> __r; - _VSTD::regex_replace(std::back_inserter(__r), __s, + std::regex_replace(std::back_inserter(__r), __s, __s + char_traits<_CharT>::length(__s), __e, __fmt, __flags); return __r; diff --git a/libcxx/include/scoped_allocator b/libcxx/include/scoped_allocator index ffea730b01eb..d0bc847332e8 100644 --- a/libcxx/include/scoped_allocator +++ b/libcxx/include/scoped_allocator @@ -233,7 +233,7 @@ protected: _LIBCPP_HIDE_FROM_ABI __scoped_allocator_storage(_OuterA2&& __outer_alloc, const _InnerAllocs& ...__inner_allocs) _NOEXCEPT - : outer_allocator_type(_VSTD::forward<_OuterA2>(__outer_alloc)), + : outer_allocator_type(std::forward<_OuterA2>(__outer_alloc)), __inner_(__inner_allocs...) {} template && __other) _NOEXCEPT - : outer_allocator_type(_VSTD::move(__other.outer_allocator())), - __inner_(_VSTD::move(__other.inner_allocator())) {} + : outer_allocator_type(std::move(__other.outer_allocator())), + __inner_(std::move(__other.inner_allocator())) {} template ::value, int> = 0> _LIBCPP_HIDE_FROM_ABI __scoped_allocator_storage(_OuterA2&& __o, const inner_allocator_type& __i) _NOEXCEPT - : outer_allocator_type(_VSTD::forward<_OuterA2>(__o)), + : outer_allocator_type(std::forward<_OuterA2>(__o)), __inner_(__i) { } @@ -305,7 +305,7 @@ protected: __enable_if_t::value, int> = 0> _LIBCPP_HIDE_FROM_ABI __scoped_allocator_storage(_OuterA2&& __outer_alloc) _NOEXCEPT - : outer_allocator_type(_VSTD::forward<_OuterA2>(__outer_alloc)) {} + : outer_allocator_type(std::forward<_OuterA2>(__outer_alloc)) {} template ::value, int> = 0> @@ -319,7 +319,7 @@ protected: _LIBCPP_HIDE_FROM_ABI __scoped_allocator_storage( __scoped_allocator_storage<_OuterA2>&& __other) _NOEXCEPT - : outer_allocator_type(_VSTD::move(__other.outer_allocator())) {} + : outer_allocator_type(std::move(__other.outer_allocator())) {} _LIBCPP_HIDE_FROM_ABI inner_allocator_type& inner_allocator() _NOEXCEPT @@ -444,7 +444,7 @@ public: _LIBCPP_HIDE_FROM_ABI scoped_allocator_adaptor(_OuterA2&& __outer_alloc, const _InnerAllocs& ...__inner_allocs) _NOEXCEPT - : base(_VSTD::forward<_OuterA2>(__outer_alloc), __inner_allocs...) {} + : base(std::forward<_OuterA2>(__outer_alloc), __inner_allocs...) {} // scoped_allocator_adaptor(const scoped_allocator_adaptor& __other) = default; template ::value, int> = 0> @@ -457,7 +457,7 @@ public: _LIBCPP_HIDE_FROM_ABI scoped_allocator_adaptor( scoped_allocator_adaptor<_OuterA2, _InnerAllocs...>&& __other) _NOEXCEPT - : base(_VSTD::move(__other)) {} + : base(std::move(__other)) {} // scoped_allocator_adaptor& operator=(const scoped_allocator_adaptor&) = default; // scoped_allocator_adaptor& operator=(scoped_allocator_adaptor&&) = default; @@ -511,7 +511,7 @@ public: _LIBCPP_HIDE_FROM_ABI void construct(_Tp* __p, _Args&& ...__args) {__construct(__uses_alloc_ctor<_Tp, inner_allocator_type&, _Args...>(), - __p, _VSTD::forward<_Args>(__args)...);} + __p, std::forward<_Args>(__args)...);} template _LIBCPP_HIDE_FROM_ABI void construct(pair<_T1, _T2>* __p, piecewise_construct_t, @@ -524,14 +524,14 @@ public: typename __uses_alloc_ctor< _T1, inner_allocator_type&, _Args1... >::type() - , _VSTD::move(__x) + , std::move(__x) , typename __make_tuple_indices::type{} ) , __transform_tuple( typename __uses_alloc_ctor< _T2, inner_allocator_type&, _Args2... >::type() - , _VSTD::move(__y) + , std::move(__y) , typename __make_tuple_indices::type{} ) ); @@ -544,22 +544,22 @@ public: template _LIBCPP_HIDE_FROM_ABI void construct(pair<_T1, _T2>* __p, _Up&& __x, _Vp&& __y) { construct(__p, piecewise_construct, - _VSTD::forward_as_tuple(_VSTD::forward<_Up>(__x)), - _VSTD::forward_as_tuple(_VSTD::forward<_Vp>(__y))); + std::forward_as_tuple(std::forward<_Up>(__x)), + std::forward_as_tuple(std::forward<_Vp>(__y))); } template _LIBCPP_HIDE_FROM_ABI void construct(pair<_T1, _T2>* __p, const pair<_Up, _Vp>& __x) { construct(__p, piecewise_construct, - _VSTD::forward_as_tuple(__x.first), - _VSTD::forward_as_tuple(__x.second)); + std::forward_as_tuple(__x.first), + std::forward_as_tuple(__x.second)); } template _LIBCPP_HIDE_FROM_ABI void construct(pair<_T1, _T2>* __p, pair<_Up, _Vp>&& __x) { construct(__p, piecewise_construct, - _VSTD::forward_as_tuple(_VSTD::forward<_Up>(__x.first)), - _VSTD::forward_as_tuple(_VSTD::forward<_Vp>(__x.second))); + std::forward_as_tuple(std::forward<_Up>(__x.first)), + std::forward_as_tuple(std::forward<_Vp>(__x.second))); } #endif @@ -584,7 +584,7 @@ private: _LIBCPP_HIDE_FROM_ABI scoped_allocator_adaptor(_OuterA2&& __o, const inner_allocator_type& __i) _NOEXCEPT - : base(_VSTD::forward<_OuterA2>(__o), __i) {} + : base(std::forward<_OuterA2>(__o), __i) {} template _LIBCPP_HIDE_FROM_ABI @@ -595,7 +595,7 @@ private: ( _OM()(outer_allocator()), __p, - _VSTD::forward<_Args>(__args)... + std::forward<_Args>(__args)... ); } @@ -608,7 +608,7 @@ private: ( _OM()(outer_allocator()), __p, allocator_arg, inner_allocator(), - _VSTD::forward<_Args>(__args)... + std::forward<_Args>(__args)... ); } @@ -621,7 +621,7 @@ private: ( _OM()(outer_allocator()), __p, - _VSTD::forward<_Args>(__args)..., + std::forward<_Args>(__args)..., inner_allocator() ); } @@ -632,7 +632,7 @@ private: __transform_tuple(integral_constant, tuple<_Args...>&& __t, __tuple_indices<_Idx...>) { - return _VSTD::forward_as_tuple(_VSTD::get<_Idx>(_VSTD::move(__t))...); + return std::forward_as_tuple(std::get<_Idx>(std::move(__t))...); } template @@ -643,7 +643,7 @@ private: { using _Tup = tuple; return _Tup(allocator_arg, inner_allocator(), - _VSTD::get<_Idx>(_VSTD::move(__t))...); + std::get<_Idx>(std::move(__t))...); } template @@ -653,7 +653,7 @@ private: __tuple_indices<_Idx...>) { using _Tup = tuple<_Args&&..., inner_allocator_type&>; - return _Tup(_VSTD::get<_Idx>(_VSTD::move(__t))..., inner_allocator()); + return _Tup(std::get<_Idx>(std::move(__t))..., inner_allocator()); } template friend class __scoped_allocator_storage; diff --git a/libcxx/include/set b/libcxx/include/set index 59e4e3bae2d3..b2d87b93f38d 100644 --- a/libcxx/include/set +++ b/libcxx/include/set @@ -591,8 +591,8 @@ public: typedef typename __base::difference_type difference_type; typedef typename __base::const_iterator iterator; typedef typename __base::const_iterator const_iterator; - typedef _VSTD::reverse_iterator reverse_iterator; - typedef _VSTD::reverse_iterator const_reverse_iterator; + typedef std::reverse_iterator reverse_iterator; + typedef std::reverse_iterator const_reverse_iterator; #if _LIBCPP_STD_VER >= 17 typedef __set_node_handle node_type; @@ -682,7 +682,7 @@ public: _LIBCPP_HIDE_FROM_ABI set(set&& __s) _NOEXCEPT_(is_nothrow_move_constructible<__base>::value) - : __tree_(_VSTD::move(__s.__tree_)) {} + : __tree_(std::move(__s.__tree_)) {} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI @@ -731,7 +731,7 @@ public: set& operator=(set&& __s) _NOEXCEPT_(is_nothrow_move_assignable<__base>::value) { - __tree_ = _VSTD::move(__s.__tree_); + __tree_ = std::move(__s.__tree_); return *this; } #endif // _LIBCPP_CXX03_LANG @@ -784,11 +784,11 @@ public: template _LIBCPP_HIDE_FROM_ABI pair emplace(_Args&&... __args) - {return __tree_.__emplace_unique(_VSTD::forward<_Args>(__args)...);} + {return __tree_.__emplace_unique(std::forward<_Args>(__args)...);} template _LIBCPP_HIDE_FROM_ABI iterator emplace_hint(const_iterator __p, _Args&&... __args) - {return __tree_.__emplace_hint_unique(__p, _VSTD::forward<_Args>(__args)...);} + {return __tree_.__emplace_hint_unique(__p, std::forward<_Args>(__args)...);} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI @@ -820,11 +820,11 @@ public: #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI pair insert(value_type&& __v) - {return __tree_.__insert_unique(_VSTD::move(__v));} + {return __tree_.__insert_unique(std::move(__v));} _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __p, value_type&& __v) - {return __tree_.__insert_unique(__p, _VSTD::move(__v));} + {return __tree_.__insert_unique(__p, std::move(__v));} _LIBCPP_HIDE_FROM_ABI void insert(initializer_list __il) @@ -849,7 +849,7 @@ public: _LIBCPP_ASSERT_UNCATEGORIZED(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to set::insert()"); return __tree_.template __node_handle_insert_unique< - node_type, insert_return_type>(_VSTD::move(__nh)); + node_type, insert_return_type>(std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __hint, node_type&& __nh) @@ -857,7 +857,7 @@ public: _LIBCPP_ASSERT_UNCATEGORIZED(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to set::insert()"); return __tree_.template __node_handle_insert_unique( - __hint, _VSTD::move(__nh)); + __hint, std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI node_type extract(key_type const& __key) @@ -1052,13 +1052,13 @@ set(initializer_list<_Key>, _Allocator) template set<_Key, _Compare, _Allocator>::set(set&& __s, const allocator_type& __a) - : __tree_(_VSTD::move(__s.__tree_), __a) + : __tree_(std::move(__s.__tree_), __a) { if (__a != __s.get_allocator()) { const_iterator __e = cend(); while (!__s.empty()) - insert(__e, _VSTD::move(__s.__tree_.remove(__s.begin())->__value_)); + insert(__e, std::move(__s.__tree_.remove(__s.begin())->__value_)); } } @@ -1070,7 +1070,7 @@ bool operator==(const set<_Key, _Compare, _Allocator>& __x, const set<_Key, _Compare, _Allocator>& __y) { - return __x.size() == __y.size() && _VSTD::equal(__x.begin(), __x.end(), __y.begin()); + return __x.size() == __y.size() && std::equal(__x.begin(), __x.end(), __y.begin()); } #if _LIBCPP_STD_VER <= 17 @@ -1081,7 +1081,7 @@ bool operator< (const set<_Key, _Compare, _Allocator>& __x, const set<_Key, _Compare, _Allocator>& __y) { - return _VSTD::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); + return std::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); } template @@ -1147,7 +1147,7 @@ template inline _LIBCPP_HIDE_FROM_ABI typename set<_Key, _Compare, _Allocator>::size_type erase_if(set<_Key, _Compare, _Allocator>& __c, _Predicate __pred) { - return _VSTD::__libcpp_erase_if_container(__c, __pred); + return std::__libcpp_erase_if_container(__c, __pred); } #endif @@ -1185,8 +1185,8 @@ public: typedef typename __base::difference_type difference_type; typedef typename __base::const_iterator iterator; typedef typename __base::const_iterator const_iterator; - typedef _VSTD::reverse_iterator reverse_iterator; - typedef _VSTD::reverse_iterator const_reverse_iterator; + typedef std::reverse_iterator reverse_iterator; + typedef std::reverse_iterator const_reverse_iterator; #if _LIBCPP_STD_VER >= 17 typedef __set_node_handle node_type; @@ -1275,7 +1275,7 @@ public: _LIBCPP_HIDE_FROM_ABI multiset(multiset&& __s) _NOEXCEPT_(is_nothrow_move_constructible<__base>::value) - : __tree_(_VSTD::move(__s.__tree_)) {} + : __tree_(std::move(__s.__tree_)) {} _LIBCPP_HIDE_FROM_ABI multiset(multiset&& __s, const allocator_type& __a); #endif // _LIBCPP_CXX03_LANG @@ -1322,7 +1322,7 @@ public: multiset& operator=(multiset&& __s) _NOEXCEPT_(is_nothrow_move_assignable<__base>::value) { - __tree_ = _VSTD::move(__s.__tree_); + __tree_ = std::move(__s.__tree_); return *this; } #endif // _LIBCPP_CXX03_LANG @@ -1375,11 +1375,11 @@ public: template _LIBCPP_HIDE_FROM_ABI iterator emplace(_Args&&... __args) - {return __tree_.__emplace_multi(_VSTD::forward<_Args>(__args)...);} + {return __tree_.__emplace_multi(std::forward<_Args>(__args)...);} template _LIBCPP_HIDE_FROM_ABI iterator emplace_hint(const_iterator __p, _Args&&... __args) - {return __tree_.__emplace_hint_multi(__p, _VSTD::forward<_Args>(__args)...);} + {return __tree_.__emplace_hint_multi(__p, std::forward<_Args>(__args)...);} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI @@ -1411,11 +1411,11 @@ public: #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI iterator insert(value_type&& __v) - {return __tree_.__insert_multi(_VSTD::move(__v));} + {return __tree_.__insert_multi(std::move(__v));} _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __p, value_type&& __v) - {return __tree_.__insert_multi(__p, _VSTD::move(__v));} + {return __tree_.__insert_multi(__p, std::move(__v));} _LIBCPP_HIDE_FROM_ABI void insert(initializer_list __il) @@ -1439,7 +1439,7 @@ public: _LIBCPP_ASSERT_UNCATEGORIZED(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to multiset::insert()"); return __tree_.template __node_handle_insert_multi( - _VSTD::move(__nh)); + std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __hint, node_type&& __nh) @@ -1447,7 +1447,7 @@ public: _LIBCPP_ASSERT_UNCATEGORIZED(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to multiset::insert()"); return __tree_.template __node_handle_insert_multi( - __hint, _VSTD::move(__nh)); + __hint, std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI node_type extract(key_type const& __key) @@ -1643,13 +1643,13 @@ multiset(initializer_list<_Key>, _Allocator) template multiset<_Key, _Compare, _Allocator>::multiset(multiset&& __s, const allocator_type& __a) - : __tree_(_VSTD::move(__s.__tree_), __a) + : __tree_(std::move(__s.__tree_), __a) { if (__a != __s.get_allocator()) { const_iterator __e = cend(); while (!__s.empty()) - insert(__e, _VSTD::move(__s.__tree_.remove(__s.begin())->__value_)); + insert(__e, std::move(__s.__tree_.remove(__s.begin())->__value_)); } } @@ -1661,7 +1661,7 @@ bool operator==(const multiset<_Key, _Compare, _Allocator>& __x, const multiset<_Key, _Compare, _Allocator>& __y) { - return __x.size() == __y.size() && _VSTD::equal(__x.begin(), __x.end(), __y.begin()); + return __x.size() == __y.size() && std::equal(__x.begin(), __x.end(), __y.begin()); } #if _LIBCPP_STD_VER <= 17 @@ -1672,7 +1672,7 @@ bool operator< (const multiset<_Key, _Compare, _Allocator>& __x, const multiset<_Key, _Compare, _Allocator>& __y) { - return _VSTD::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); + return std::lexicographical_compare(__x.begin(), __x.end(), __y.begin(), __y.end()); } template @@ -1737,7 +1737,7 @@ template inline _LIBCPP_HIDE_FROM_ABI typename multiset<_Key, _Compare, _Allocator>::size_type erase_if(multiset<_Key, _Compare, _Allocator>& __c, _Predicate __pred) { - return _VSTD::__libcpp_erase_if_container(__c, __pred); + return std::__libcpp_erase_if_container(__c, __pred); } #endif diff --git a/libcxx/include/shared_mutex b/libcxx/include/shared_mutex index 3118676d4e6b..1528d108d749 100644 --- a/libcxx/include/shared_mutex +++ b/libcxx/include/shared_mutex @@ -321,26 +321,26 @@ private: public: _LIBCPP_HIDE_FROM_ABI shared_lock() _NOEXCEPT : __m_(nullptr), __owns_(false) {} - _LIBCPP_HIDE_FROM_ABI explicit shared_lock(mutex_type& __m) : __m_(_VSTD::addressof(__m)), __owns_(true) { + _LIBCPP_HIDE_FROM_ABI explicit shared_lock(mutex_type& __m) : __m_(std::addressof(__m)), __owns_(true) { __m_->lock_shared(); } _LIBCPP_HIDE_FROM_ABI shared_lock(mutex_type& __m, defer_lock_t) _NOEXCEPT - : __m_(_VSTD::addressof(__m)), + : __m_(std::addressof(__m)), __owns_(false) {} _LIBCPP_HIDE_FROM_ABI shared_lock(mutex_type& __m, try_to_lock_t) - : __m_(_VSTD::addressof(__m)), __owns_(__m.try_lock_shared()) {} + : __m_(std::addressof(__m)), __owns_(__m.try_lock_shared()) {} - _LIBCPP_HIDE_FROM_ABI shared_lock(mutex_type& __m, adopt_lock_t) : __m_(_VSTD::addressof(__m)), __owns_(true) {} + _LIBCPP_HIDE_FROM_ABI shared_lock(mutex_type& __m, adopt_lock_t) : __m_(std::addressof(__m)), __owns_(true) {} template _LIBCPP_HIDE_FROM_ABI shared_lock(mutex_type& __m, const chrono::time_point<_Clock, _Duration>& __abs_time) - : __m_(_VSTD::addressof(__m)), __owns_(__m.try_lock_shared_until(__abs_time)) {} + : __m_(std::addressof(__m)), __owns_(__m.try_lock_shared_until(__abs_time)) {} template _LIBCPP_HIDE_FROM_ABI shared_lock(mutex_type& __m, const chrono::duration<_Rep, _Period>& __rel_time) - : __m_(_VSTD::addressof(__m)), __owns_(__m.try_lock_shared_for(__rel_time)) {} + : __m_(std::addressof(__m)), __owns_(__m.try_lock_shared_for(__rel_time)) {} _LIBCPP_HIDE_FROM_ABI ~shared_lock() { if (__owns_) @@ -377,8 +377,8 @@ public: // Setters _LIBCPP_HIDE_FROM_ABI void swap(shared_lock& __u) _NOEXCEPT { - _VSTD::swap(__m_, __u.__m_); - _VSTD::swap(__owns_, __u.__owns_); + std::swap(__m_, __u.__m_); + std::swap(__owns_, __u.__owns_); } _LIBCPP_HIDE_FROM_ABI mutex_type* release() _NOEXCEPT { diff --git a/libcxx/include/source_location b/libcxx/include/source_location index e9e852a6e461..d16e3c46fce5 100644 --- a/libcxx/include/source_location +++ b/libcxx/include/source_location @@ -35,8 +35,7 @@ namespace std { _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER >= 20 && __has_builtin(__builtin_source_location) && \ - !(defined(_LIBCPP_APPLE_CLANG_VER) && _LIBCPP_APPLE_CLANG_VER <= 1403) +#if _LIBCPP_STD_VER >= 20 class source_location { // The names source_location::__impl, _M_file_name, _M_function_name, _M_line, and _M_column @@ -79,8 +78,7 @@ public: } }; -#endif // _LIBCPP_STD_VER >= 20 && __has_builtin(__builtin_source_location) && !(defined(_LIBCPP_APPLE_CLANG_VER) && - // _LIBCPP_APPLE_CLANG_VER <= 1403) +#endif // _LIBCPP_STD_VER >= 20 _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/span b/libcxx/include/span index 179bdd08ee65..f94bda40fa73 100644 --- a/libcxx/include/span +++ b/libcxx/include/span @@ -182,12 +182,12 @@ struct __is_std_span> : true_type {}; template concept __span_compatible_range = - ranges::contiguous_range<_Range> && - ranges::sized_range<_Range> && - (ranges::borrowed_range<_Range> || is_const_v<_ElementType>) && - !__is_std_span>::value && - !__is_std_array>::value && - !is_array_v> && + ranges::contiguous_range<_Range> && // + ranges::sized_range<_Range> && // + (ranges::borrowed_range<_Range> || is_const_v<_ElementType>) && // + !__is_std_span>::value && // + !__is_std_array>::value && // + !is_array_v> && // is_convertible_v>(*)[], _ElementType(*)[]>; template @@ -216,7 +216,7 @@ public: #else using iterator = __wrap_iter; #endif - using reverse_iterator = _VSTD::reverse_iterator; + using reverse_iterator = std::reverse_iterator; static constexpr size_type extent = _Extent; @@ -230,14 +230,14 @@ public: template <__span_compatible_iterator _It> _LIBCPP_HIDE_FROM_ABI constexpr explicit span(_It __first, size_type __count) - : __data_{_VSTD::to_address(__first)} { + : __data_{std::to_address(__first)} { (void)__count; _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(_Extent == __count, "size mismatch in span's constructor (iterator, len)"); } template <__span_compatible_iterator _It, __span_compatible_sentinel_for<_It> _End> _LIBCPP_HIDE_FROM_ABI - constexpr explicit span(_It __first, _End __last) : __data_{_VSTD::to_address(__first)} { + constexpr explicit span(_It __first, _End __last) : __data_{std::to_address(__first)} { // [span.cons]/10 // Throws: When and what last - first throws. [[maybe_unused]] auto __dist = __last - __first; @@ -403,7 +403,7 @@ public: #else using iterator = __wrap_iter; #endif - using reverse_iterator = _VSTD::reverse_iterator; + using reverse_iterator = std::reverse_iterator; static constexpr size_type extent = dynamic_extent; @@ -416,11 +416,11 @@ public: template <__span_compatible_iterator _It> _LIBCPP_HIDE_FROM_ABI constexpr span(_It __first, size_type __count) - : __data_{_VSTD::to_address(__first)}, __size_{__count} {} + : __data_{std::to_address(__first)}, __size_{__count} {} template <__span_compatible_iterator _It, __span_compatible_sentinel_for<_It> _End> _LIBCPP_HIDE_FROM_ABI constexpr span(_It __first, _End __last) - : __data_(_VSTD::to_address(__first)), __size_(__last - __first) { + : __data_(std::to_address(__first)), __size_(__last - __first) { _LIBCPP_ASSERT_VALID_INPUT_RANGE( __last - __first >= 0, "invalid range in span's constructor (iterator, sentinel)"); } diff --git a/libcxx/include/sstream b/libcxx/include/sstream index 202ca745a22b..0f4fb33a66fd 100644 --- a/libcxx/include/sstream +++ b/libcxx/include/sstream @@ -10,6 +10,8 @@ #ifndef _LIBCPP_SSTREAM #define _LIBCPP_SSTREAM +// clang-format off + /* sstream synopsis [sstream.syn] @@ -266,6 +268,8 @@ typedef basic_stringstream wstringstream; */ +// clang-format on + #include <__assert> // all public C++ headers provide the assertion handler #include <__availability> #include <__config> @@ -477,7 +481,7 @@ _LIBCPP_HIDE_FROM_ABI void basic_stringbuf<_CharT, _Traits, _Allocator>::__move_ __eout = __rhs.epptr() - __p; } ptrdiff_t __hm = __rhs.__hm_ == nullptr ? -1 : __rhs.__hm_ - __p; - __str_ = _VSTD::move(__rhs.__str_); + __str_ = std::move(__rhs.__str_); __p = const_cast(__str_.data()); if (__binp != -1) this->setg(__p + __binp, __p + __ninp, __p + __einp); @@ -518,7 +522,7 @@ basic_stringbuf<_CharT, _Traits, _Allocator>::operator=(basic_stringbuf&& __rhs) __eout = __rhs.epptr() - __p; } ptrdiff_t __hm = __rhs.__hm_ == nullptr ? -1 : __rhs.__hm_ - __p; - __str_ = _VSTD::move(__rhs.__str_); + __str_ = std::move(__rhs.__str_); __p = const_cast(__str_.data()); if (__binp != -1) this->setg(__p + __binp, __p + __ninp, __p + __einp); @@ -590,7 +594,7 @@ basic_stringbuf<_CharT, _Traits, _Allocator>::swap(basic_stringbuf& __rhs) __leout = this->epptr() - __p; } ptrdiff_t __lhm = __hm_ == nullptr ? -1 : __hm_ - __p; - _VSTD::swap(__mode_, __rhs.__mode_); + std::swap(__mode_, __rhs.__mode_); __str_.swap(__rhs.__str_); __p = const_cast(__str_.data()); if (__rbinp != -1) @@ -758,7 +762,7 @@ basic_stringbuf<_CharT, _Traits, _Allocator>::overflow(int_type __c) } #endif // _LIBCPP_HAS_NO_EXCEPTIONS } - __hm_ = _VSTD::max(this->pptr() + 1, __hm_); + __hm_ = std::max(this->pptr() + 1, __hm_); if (__mode_ & ios_base::in) { char_type* __p = const_cast(__str_.data()); @@ -881,16 +885,16 @@ public: _LIBCPP_HIDE_FROM_ABI basic_istringstream(basic_istringstream&& __rhs) - : basic_istream<_CharT, _Traits>(_VSTD::move(__rhs)) - , __sb_(_VSTD::move(__rhs.__sb_)) + : basic_istream<_CharT, _Traits>(std::move(__rhs)) + , __sb_(std::move(__rhs.__sb_)) { basic_istream<_CharT, _Traits>::set_rdbuf(&__sb_); } // [istringstream.assign] Assign and swap: basic_istringstream& operator=(basic_istringstream&& __rhs) { - basic_istream::operator=(_VSTD::move(__rhs)); - __sb_ = _VSTD::move(__rhs.__sb_); + basic_istream::operator=(std::move(__rhs)); + __sb_ = std::move(__rhs.__sb_); return *this; } _LIBCPP_HIDE_FROM_ABI @@ -1005,16 +1009,16 @@ public: _LIBCPP_HIDE_FROM_ABI basic_ostringstream(basic_ostringstream&& __rhs) - : basic_ostream<_CharT, _Traits>(_VSTD::move(__rhs)) - , __sb_(_VSTD::move(__rhs.__sb_)) + : basic_ostream<_CharT, _Traits>(std::move(__rhs)) + , __sb_(std::move(__rhs.__sb_)) { basic_ostream<_CharT, _Traits>::set_rdbuf(&__sb_); } // [ostringstream.assign] Assign and swap: basic_ostringstream& operator=(basic_ostringstream&& __rhs) { - basic_ostream::operator=(_VSTD::move(__rhs)); - __sb_ = _VSTD::move(__rhs.__sb_); + basic_ostream::operator=(std::move(__rhs)); + __sb_ = std::move(__rhs.__sb_); return *this; } @@ -1130,16 +1134,16 @@ public: _LIBCPP_HIDE_FROM_ABI basic_stringstream(basic_stringstream&& __rhs) - : basic_iostream<_CharT, _Traits>(_VSTD::move(__rhs)) - , __sb_(_VSTD::move(__rhs.__sb_)) + : basic_iostream<_CharT, _Traits>(std::move(__rhs)) + , __sb_(std::move(__rhs.__sb_)) { basic_istream<_CharT, _Traits>::set_rdbuf(&__sb_); } // [stringstream.assign] Assign and swap: basic_stringstream& operator=(basic_stringstream&& __rhs) { - basic_iostream::operator=(_VSTD::move(__rhs)); - __sb_ = _VSTD::move(__rhs.__sb_); + basic_iostream::operator=(std::move(__rhs)); + __sb_ = std::move(__rhs.__sb_); return *this; } _LIBCPP_HIDE_FROM_ABI diff --git a/libcxx/include/stack b/libcxx/include/stack index f0fb8c4e4d1d..63cd7dead78e 100644 --- a/libcxx/include/stack +++ b/libcxx/include/stack @@ -183,15 +183,15 @@ public: _LIBCPP_HIDE_FROM_ABI stack(stack&& __q) _NOEXCEPT_(is_nothrow_move_constructible::value) - : c(_VSTD::move(__q.c)) {} + : c(std::move(__q.c)) {} _LIBCPP_HIDE_FROM_ABI stack& operator=(stack&& __q) _NOEXCEPT_(is_nothrow_move_assignable::value) - {c = _VSTD::move(__q.c); return *this;} + {c = std::move(__q.c); return *this;} _LIBCPP_HIDE_FROM_ABI - explicit stack(container_type&& __c) : c(_VSTD::move(__c)) {} + explicit stack(container_type&& __c) : c(std::move(__c)) {} #endif // _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI @@ -217,12 +217,12 @@ public: _LIBCPP_HIDE_FROM_ABI stack(container_type&& __c, const _Alloc& __a, __enable_if_t::value>* = 0) - : c(_VSTD::move(__c), __a) {} + : c(std::move(__c), __a) {} template _LIBCPP_HIDE_FROM_ABI stack(stack&& __s, const _Alloc& __a, __enable_if_t::value>* = 0) - : c(_VSTD::move(__s.c), __a) {} + : c(std::move(__s.c), __a) {} #endif // _LIBCPP_CXX03_LANG #if _LIBCPP_STD_VER >= 23 @@ -264,7 +264,7 @@ public: void push(const value_type& __v) {c.push_back(__v);} #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI - void push(value_type&& __v) {c.push_back(_VSTD::move(__v));} + void push(value_type&& __v) {c.push_back(std::move(__v));} #if _LIBCPP_STD_VER >= 23 template <_ContainerCompatibleRange<_Tp> _Range> @@ -284,10 +284,10 @@ public: _LIBCPP_HIDE_FROM_ABI #if _LIBCPP_STD_VER >= 17 decltype(auto) emplace(_Args&&... __args) - { return c.emplace_back(_VSTD::forward<_Args>(__args)...);} + { return c.emplace_back(std::forward<_Args>(__args)...);} #else void emplace(_Args&&... __args) - { c.emplace_back(_VSTD::forward<_Args>(__args)...);} + { c.emplace_back(std::forward<_Args>(__args)...);} #endif #endif // _LIBCPP_CXX03_LANG @@ -298,7 +298,7 @@ public: void swap(stack& __s) _NOEXCEPT_(__is_nothrow_swappable::value) { - using _VSTD::swap; + using std::swap; swap(c, __s.c); } diff --git a/libcxx/include/stdexcept b/libcxx/include/stdexcept index ec07304ce244..d41e94a5f9e8 100644 --- a/libcxx/include/stdexcept +++ b/libcxx/include/stdexcept @@ -79,7 +79,7 @@ class _LIBCPP_EXPORTED_FROM_ABI logic_error { #ifndef _LIBCPP_ABI_VCRUNTIME private: - _VSTD::__libcpp_refstring __imp_; + std::__libcpp_refstring __imp_; public: explicit logic_error(const string&); explicit logic_error(const char*); @@ -92,7 +92,7 @@ public: const char* what() const _NOEXCEPT override; #else public: - explicit logic_error(const _VSTD::string&); // Symbol uses versioned std::string + explicit logic_error(const std::string&); // Symbol uses versioned std::string _LIBCPP_HIDE_FROM_ABI explicit logic_error(const char* __s) : exception(__s) {} #endif }; @@ -102,7 +102,7 @@ class _LIBCPP_EXPORTED_FROM_ABI runtime_error { #ifndef _LIBCPP_ABI_VCRUNTIME private: - _VSTD::__libcpp_refstring __imp_; + std::__libcpp_refstring __imp_; public: explicit runtime_error(const string&); explicit runtime_error(const char*); @@ -115,7 +115,7 @@ public: const char* what() const _NOEXCEPT override; #else public: - explicit runtime_error(const _VSTD::string&); // Symbol uses versioned std::string + explicit runtime_error(const std::string&); // Symbol uses versioned std::string _LIBCPP_HIDE_FROM_ABI explicit runtime_error(const char* __s) : exception(__s) {} #endif // _LIBCPP_ABI_VCRUNTIME }; diff --git a/libcxx/include/streambuf b/libcxx/include/streambuf index b9a3d00110a1..b0e65b13151f 100644 --- a/libcxx/include/streambuf +++ b/libcxx/include/streambuf @@ -351,13 +351,13 @@ template void basic_streambuf<_CharT, _Traits>::swap(basic_streambuf& __sb) { - _VSTD::swap(__loc_, __sb.__loc_); - _VSTD::swap(__binp_, __sb.__binp_); - _VSTD::swap(__ninp_, __sb.__ninp_); - _VSTD::swap(__einp_, __sb.__einp_); - _VSTD::swap(__bout_, __sb.__bout_); - _VSTD::swap(__nout_, __sb.__nout_); - _VSTD::swap(__eout_, __sb.__eout_); + std::swap(__loc_, __sb.__loc_); + std::swap(__binp_, __sb.__binp_); + std::swap(__ninp_, __sb.__ninp_); + std::swap(__einp_, __sb.__einp_); + std::swap(__bout_, __sb.__bout_); + std::swap(__nout_, __sb.__nout_); + std::swap(__eout_, __sb.__eout_); } template @@ -413,8 +413,8 @@ basic_streambuf<_CharT, _Traits>::xsgetn(char_type* __s, streamsize __n) { if (__ninp_ < __einp_) { - const streamsize __len = _VSTD::min(static_cast(INT_MAX), - _VSTD::min(__einp_ - __ninp_, __n - __i)); + const streamsize __len = std::min(static_cast(INT_MAX), + std::min(__einp_ - __ninp_, __n - __i)); traits_type::copy(__s, __ninp_, __len); __s += __len; __i += __len; @@ -472,7 +472,7 @@ basic_streambuf<_CharT, _Traits>::xsputn(const char_type* __s, streamsize __n) } else { - streamsize __chunk_size = _VSTD::min(__eout_ - __nout_, __n - __i); + streamsize __chunk_size = std::min(__eout_ - __nout_, __n - __i); traits_type::copy(__nout_, __s, __chunk_size); __nout_ += __chunk_size; __s += __chunk_size; diff --git a/libcxx/include/string b/libcxx/include/string index 25f307825fa2..9c97abefcb8d 100644 --- a/libcxx/include/string +++ b/libcxx/include/string @@ -10,6 +10,8 @@ #ifndef _LIBCPP_STRING #define _LIBCPP_STRING +// clang-format off + /* string synopsis @@ -564,6 +566,8 @@ basic_string operator""s( const char32_t *str, size_t len ); */ +// clang-format on + #include <__algorithm/max.h> #include <__algorithm/min.h> #include <__algorithm/remove.h> diff --git a/libcxx/include/string_view b/libcxx/include/string_view index 1961f920bb5b..3712584a6666 100644 --- a/libcxx/include/string_view +++ b/libcxx/include/string_view @@ -10,6 +10,8 @@ #ifndef _LIBCPP_STRING_VIEW #define _LIBCPP_STRING_VIEW +// clang-format off + /* string_view synopsis @@ -199,9 +201,10 @@ namespace std { } // namespace std - */ +// clang-format on + #include <__algorithm/min.h> #include <__assert> // all public C++ headers provide the assertion handler #include <__config> @@ -282,7 +285,7 @@ public: using const_iterator = const_pointer; // See [string.view.iterators] #endif using iterator = const_iterator; - using const_reverse_iterator = _VSTD::reverse_iterator; + using const_reverse_iterator = std::reverse_iterator; using reverse_iterator = const_reverse_iterator; using size_type = size_t; using difference_type = ptrdiff_t; @@ -321,7 +324,7 @@ public: template _End> requires (is_same_v, _CharT> && !is_convertible_v<_End, size_type>) constexpr _LIBCPP_HIDE_FROM_ABI basic_string_view(_It __begin, _End __end) - : __data_(_VSTD::to_address(__begin)), __size_(__end - __begin) + : __data_(std::to_address(__begin)), __size_(__end - __begin) { _LIBCPP_ASSERT_VALID_INPUT_RANGE((__end - __begin) >= 0, "std::string_view::string_view(iterator, sentinel) received invalid range"); @@ -337,7 +340,7 @@ public: is_same_v, _CharT> && !is_convertible_v<_Range, const _CharT*> && (!requires(remove_cvref_t<_Range>& __d) { - __d.operator _VSTD::basic_string_view<_CharT, _Traits>(); + __d.operator std::basic_string_view<_CharT, _Traits>(); }) ) constexpr explicit _LIBCPP_HIDE_FROM_ABI @@ -346,7 +349,7 @@ public: _LIBCPP_CONSTEXPR _LIBCPP_HIDE_FROM_ABI basic_string_view(const _CharT* __s) - : __data_(__s), __size_(_VSTD::__char_traits_length_checked<_Traits>(__s)) {} + : __data_(__s), __size_(std::__char_traits_length_checked<_Traits>(__s)) {} #if _LIBCPP_STD_VER >= 23 basic_string_view(nullptr_t) = delete; @@ -465,7 +468,7 @@ public: { if (__pos > size()) __throw_out_of_range("string_view::copy"); - size_type __rlen = _VSTD::min(__n, size() - __pos); + size_type __rlen = std::min(__n, size() - __pos); _Traits::copy(__s, data() + __pos, __rlen); return __rlen; } @@ -475,12 +478,12 @@ public: { return __pos > size() ? (__throw_out_of_range("string_view::substr"), basic_string_view()) - : basic_string_view(data() + __pos, _VSTD::min(__n, size() - __pos)); + : basic_string_view(data() + __pos, std::min(__n, size() - __pos)); } _LIBCPP_CONSTEXPR_SINCE_CXX14 int compare(basic_string_view __sv) const _NOEXCEPT { - size_type __rlen = _VSTD::min(size(), __sv.size()); + size_type __rlen = std::min(size(), __sv.size()); int __retval = _Traits::compare(data(), __sv.data(), __rlen); if (__retval == 0) // first __rlen chars matched __retval = size() == __sv.size() ? 0 : (size() < __sv.size() ? -1 : 1); diff --git a/libcxx/include/strstream b/libcxx/include/strstream index 8ee412955937..d42ca7e9271c 100644 --- a/libcxx/include/strstream +++ b/libcxx/include/strstream @@ -257,8 +257,8 @@ public: #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI istrstream(istrstream&& __rhs) // extension - : istream(_VSTD::move(static_cast(__rhs))), - __sb_(_VSTD::move(__rhs.__sb_)) + : istream(std::move(static_cast(__rhs))), + __sb_(std::move(__rhs.__sb_)) { istream::set_rdbuf(&__sb_); } @@ -266,8 +266,8 @@ public: _LIBCPP_HIDE_FROM_ABI istrstream& operator=(istrstream&& __rhs) { - __sb_ = _VSTD::move(__rhs.__sb_); - istream::operator=(_VSTD::move(__rhs)); + __sb_ = std::move(__rhs.__sb_); + istream::operator=(std::move(__rhs)); return *this; } #endif // _LIBCPP_CXX03_LANG @@ -300,14 +300,14 @@ public: _LIBCPP_HIDE_FROM_ABI ostrstream(char* __s, int __n, ios_base::openmode __mode = ios_base::out) : ostream(&__sb_), - __sb_(__s, __n, __s + (__mode & ios::app ? _VSTD::strlen(__s) : 0)) + __sb_(__s, __n, __s + (__mode & ios::app ? std::strlen(__s) : 0)) {} #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI ostrstream(ostrstream&& __rhs) // extension - : ostream(_VSTD::move(static_cast(__rhs))), - __sb_(_VSTD::move(__rhs.__sb_)) + : ostream(std::move(static_cast(__rhs))), + __sb_(std::move(__rhs.__sb_)) { ostream::set_rdbuf(&__sb_); } @@ -315,8 +315,8 @@ public: _LIBCPP_HIDE_FROM_ABI ostrstream& operator=(ostrstream&& __rhs) { - __sb_ = _VSTD::move(__rhs.__sb_); - ostream::operator=(_VSTD::move(__rhs)); + __sb_ = std::move(__rhs.__sb_); + ostream::operator=(std::move(__rhs)); return *this; } #endif // _LIBCPP_CXX03_LANG @@ -360,14 +360,14 @@ public: _LIBCPP_HIDE_FROM_ABI strstream(char* __s, int __n, ios_base::openmode __mode = ios_base::in | ios_base::out) : iostream(&__sb_), - __sb_(__s, __n, __s + (__mode & ios::app ? _VSTD::strlen(__s) : 0)) + __sb_(__s, __n, __s + (__mode & ios::app ? std::strlen(__s) : 0)) {} #ifndef _LIBCPP_CXX03_LANG _LIBCPP_HIDE_FROM_ABI strstream(strstream&& __rhs) // extension - : iostream(_VSTD::move(static_cast(__rhs))), - __sb_(_VSTD::move(__rhs.__sb_)) + : iostream(std::move(static_cast(__rhs))), + __sb_(std::move(__rhs.__sb_)) { iostream::set_rdbuf(&__sb_); } @@ -375,8 +375,8 @@ public: _LIBCPP_HIDE_FROM_ABI strstream& operator=(strstream&& __rhs) { - __sb_ = _VSTD::move(__rhs.__sb_); - iostream::operator=(_VSTD::move(__rhs)); + __sb_ = std::move(__rhs.__sb_); + iostream::operator=(std::move(__rhs)); return *this; } #endif // _LIBCPP_CXX03_LANG diff --git a/libcxx/include/tuple b/libcxx/include/tuple index c1ae7b565c71..194138f7076c 100644 --- a/libcxx/include/tuple +++ b/libcxx/include/tuple @@ -10,6 +10,8 @@ #ifndef _LIBCPP_TUPLE #define _LIBCPP_TUPLE +// clang-format off + /* tuple synopsis @@ -201,6 +203,8 @@ template */ +// clang-format on + #include <__assert> // all public C++ headers provide the assertion handler #include <__compare/common_comparison_category.h> #include <__compare/synth_three_way.h> @@ -354,28 +358,28 @@ public: > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 explicit __tuple_leaf(_Tp&& __t) _NOEXCEPT_((is_nothrow_constructible<_Hp, _Tp>::value)) - : __value_(_VSTD::forward<_Tp>(__t)) + : __value_(std::forward<_Tp>(__t)) {static_assert(__can_bind_reference<_Tp&&>(), "Attempted construction of reference element binds to a temporary whose lifetime has ended");} template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 explicit __tuple_leaf(integral_constant, const _Alloc&, _Tp&& __t) - : __value_(_VSTD::forward<_Tp>(__t)) + : __value_(std::forward<_Tp>(__t)) {static_assert(__can_bind_reference<_Tp&&>(), "Attempted construction of reference element binds to a temporary whose lifetime has ended");} template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 explicit __tuple_leaf(integral_constant, const _Alloc& __a, _Tp&& __t) - : __value_(allocator_arg_t(), __a, _VSTD::forward<_Tp>(__t)) + : __value_(allocator_arg_t(), __a, std::forward<_Tp>(__t)) {static_assert(!is_reference<_Hp>::value, "Attempted to uses-allocator construct a reference element in a tuple");} template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 explicit __tuple_leaf(integral_constant, const _Alloc& __a, _Tp&& __t) - : __value_(_VSTD::forward<_Tp>(__t), __a) + : __value_(std::forward<_Tp>(__t), __a) {static_assert(!is_reference<_Hp>::value, "Attempted to uses-allocator construct a reference element in a tuple");} @@ -385,13 +389,13 @@ public: _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 int swap(__tuple_leaf& __t) _NOEXCEPT_(__is_nothrow_swappable<__tuple_leaf>::value) { - _VSTD::swap(*this, __t); + std::swap(*this, __t); return 0; } _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 int swap(const __tuple_leaf& __t) const _NOEXCEPT_(__is_nothrow_swappable::value) { - _VSTD::swap(*this, __t); + std::swap(*this, __t); return 0; } @@ -433,22 +437,22 @@ public: > _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 explicit __tuple_leaf(_Tp&& __t) _NOEXCEPT_((is_nothrow_constructible<_Hp, _Tp>::value)) - : _Hp(_VSTD::forward<_Tp>(__t)) {} + : _Hp(std::forward<_Tp>(__t)) {} template _LIBCPP_HIDE_FROM_ABI constexpr explicit __tuple_leaf(integral_constant, const _Alloc&, _Tp&& __t) - : _Hp(_VSTD::forward<_Tp>(__t)) {} + : _Hp(std::forward<_Tp>(__t)) {} template _LIBCPP_HIDE_FROM_ABI constexpr explicit __tuple_leaf(integral_constant, const _Alloc& __a, _Tp&& __t) - : _Hp(allocator_arg_t(), __a, _VSTD::forward<_Tp>(__t)) {} + : _Hp(allocator_arg_t(), __a, std::forward<_Tp>(__t)) {} template _LIBCPP_HIDE_FROM_ABI constexpr explicit __tuple_leaf(integral_constant, const _Alloc& __a, _Tp&& __t) - : _Hp(_VSTD::forward<_Tp>(__t), __a) {} + : _Hp(std::forward<_Tp>(__t), __a) {} __tuple_leaf(__tuple_leaf const &) = default; __tuple_leaf(__tuple_leaf &&) = default; @@ -457,13 +461,13 @@ public: int swap(__tuple_leaf& __t) _NOEXCEPT_(__is_nothrow_swappable<__tuple_leaf>::value) { - _VSTD::swap(*this, __t); + std::swap(*this, __t); return 0; } _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 int swap(const __tuple_leaf& __rhs) const _NOEXCEPT_(__is_nothrow_swappable::value) { - _VSTD::swap(*this, __rhs); + std::swap(*this, __rhs); return 0; } @@ -504,7 +508,7 @@ struct _LIBCPP_DECLSPEC_EMPTY_BASES __tuple_impl<__tuple_indices<_Indx...>, _Tp. _Up&&... __u) _NOEXCEPT_((__all::value...>::value && __all::value...>::value)) : - __tuple_leaf<_Uf, _Tf>(_VSTD::forward<_Up>(__u))..., + __tuple_leaf<_Uf, _Tf>(std::forward<_Up>(__u))..., __tuple_leaf<_Ul, _Tl>()... {} @@ -517,7 +521,7 @@ struct _LIBCPP_DECLSPEC_EMPTY_BASES __tuple_impl<__tuple_indices<_Indx...>, _Tp. __tuple_indices<_Ul...>, __tuple_types<_Tl...>, _Up&&... __u) : __tuple_leaf<_Uf, _Tf>(__uses_alloc_ctor<_Tf, _Alloc, _Up>(), __a, - _VSTD::forward<_Up>(__u))..., + std::forward<_Up>(__u))..., __tuple_leaf<_Ul, _Tl>(__uses_alloc_ctor<_Tl, _Alloc>(), __a)... {} @@ -527,8 +531,8 @@ struct _LIBCPP_DECLSPEC_EMPTY_BASES __tuple_impl<__tuple_indices<_Indx...>, _Tp. _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 __tuple_impl(_Tuple&& __t) _NOEXCEPT_((__all::type>::type>::value...>::value)) - : __tuple_leaf<_Indx, _Tp>(_VSTD::forward::type>::type>(_VSTD::get<_Indx>(__t)))... + : __tuple_leaf<_Indx, _Tp>(std::forward::type>::type>(std::get<_Indx>(__t)))... {} template , _Tp. __tuple_impl(allocator_arg_t, const _Alloc& __a, _Tuple&& __t) : __tuple_leaf<_Indx, _Tp>(__uses_alloc_ctor<_Tp, _Alloc, typename tuple_element<_Indx, typename __make_tuple_types<_Tuple>::type>::type>(), __a, - _VSTD::forward::type>::type>(_VSTD::get<_Indx>(__t)))... + std::forward::type>::type>(std::get<_Indx>(__t)))... {} __tuple_impl(const __tuple_impl&) = default; @@ -549,28 +553,28 @@ struct _LIBCPP_DECLSPEC_EMPTY_BASES __tuple_impl<__tuple_indices<_Indx...>, _Tp. void swap(__tuple_impl& __t) _NOEXCEPT_(__all<__is_nothrow_swappable<_Tp>::value...>::value) { - _VSTD::__swallow(__tuple_leaf<_Indx, _Tp>::swap(static_cast<__tuple_leaf<_Indx, _Tp>&>(__t))...); + std::__swallow(__tuple_leaf<_Indx, _Tp>::swap(static_cast<__tuple_leaf<_Indx, _Tp>&>(__t))...); } _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 void swap(const __tuple_impl& __t) const _NOEXCEPT_(__all<__is_nothrow_swappable::value...>::value) { - _VSTD::__swallow(__tuple_leaf<_Indx, _Tp>::swap(static_cast&>(__t))...); + std::__swallow(__tuple_leaf<_Indx, _Tp>::swap(static_cast&>(__t))...); } }; template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 void __memberwise_copy_assign(_Dest& __dest, _Source const& __source, __tuple_indices<_Np...>) { - _VSTD::__swallow(((_VSTD::get<_Np>(__dest) = _VSTD::get<_Np>(__source)), void(), 0)...); + std::__swallow(((std::get<_Np>(__dest) = std::get<_Np>(__source)), void(), 0)...); } template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 void __memberwise_forward_assign(_Dest& __dest, _Source&& __source, __tuple_types<_Up...>, __tuple_indices<_Np...>) { - _VSTD::__swallow((( - _VSTD::get<_Np>(__dest) = _VSTD::forward<_Up>(_VSTD::get<_Np>(__source)) + std::__swallow((( + std::get<_Np>(__dest) = std::forward<_Up>(std::get<_Np>(__source)) ), void(), 0)...); } @@ -679,7 +683,7 @@ _LIBCPP_GCC_DIAGNOSTIC_IGNORED("-Wc++20-extensions") typename __make_tuple_types::type(), typename __make_tuple_indices::type(), typename __make_tuple_types::type(), - _VSTD::forward<_Up>(__u)...) {} + std::forward<_Up>(__u)...) {} template ::type(), typename __make_tuple_indices::type(), typename __make_tuple_types::type(), - _VSTD::forward<_Up>(__u)...) {} + std::forward<_Up>(__u)...) {} // Copy and move constructors (including the allocator_arg_t variants) tuple(const tuple&) = default; @@ -713,7 +717,7 @@ _LIBCPP_GCC_DIAGNOSTIC_IGNORED("-Wc++20-extensions") , int> = 0> _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 tuple(allocator_arg_t, const _Alloc& __alloc, tuple&& __t) - : __base_(allocator_arg_t(), __alloc, _VSTD::move(__t)) + : __base_(allocator_arg_t(), __alloc, std::move(__t)) { } // tuple(const tuple&) constructors (including allocator_arg_t variants) @@ -787,7 +791,7 @@ _LIBCPP_GCC_DIAGNOSTIC_IGNORED("-Wc++20-extensions") _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 explicit(_Not<_Lazy<_And, is_convertible<_Up, _Tp>...> >::value) tuple(tuple<_Up...>&& __t) _NOEXCEPT_((_And...>::value)) - : __base_(_VSTD::move(__t)) + : __base_(std::move(__t)) { } template = 0> _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 explicit(_Not<_Lazy<_And, is_convertible<_Up, _Tp>...> >::value) tuple(allocator_arg_t, const _Alloc& __a, tuple<_Up...>&& __t) - : __base_(allocator_arg_t(), __a, _VSTD::move(__t)) + : __base_(allocator_arg_t(), __a, std::move(__t)) { } #if _LIBCPP_STD_VER >= 23 @@ -890,7 +894,7 @@ _LIBCPP_GCC_DIAGNOSTIC_IGNORED("-Wc++20-extensions") _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 explicit(_Not<_BothImplicitlyConvertible&&> >::value) tuple(pair<_Up1, _Up2>&& __p) _NOEXCEPT_((_NothrowConstructibleFromPair&&>::value)) - : __base_(_VSTD::move(__p)) + : __base_(std::move(__p)) { } template class _And = _And, __enable_if_t< @@ -900,7 +904,7 @@ _LIBCPP_GCC_DIAGNOSTIC_IGNORED("-Wc++20-extensions") , int> = 0> _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 explicit(_Not<_BothImplicitlyConvertible&&> >::value) tuple(allocator_arg_t, const _Alloc& __a, pair<_Up1, _Up2>&& __p) - : __base_(allocator_arg_t(), __a, _VSTD::move(__p)) + : __base_(allocator_arg_t(), __a, std::move(__p)) { } #if _LIBCPP_STD_VER >= 23 @@ -927,7 +931,7 @@ _LIBCPP_DIAGNOSTIC_POP tuple& operator=(_If<_And...>::value, tuple, __nat> const& __tuple) _NOEXCEPT_((_And...>::value)) { - _VSTD::__memberwise_copy_assign(*this, __tuple, + std::__memberwise_copy_assign(*this, __tuple, typename __make_tuple_indices::type()); return *this; } @@ -955,7 +959,7 @@ _LIBCPP_DIAGNOSTIC_POP tuple& operator=(_If<_And...>::value, tuple, __nat>&& __tuple) _NOEXCEPT_((_And...>::value)) { - _VSTD::__memberwise_forward_assign(*this, _VSTD::move(__tuple), + std::__memberwise_forward_assign(*this, std::move(__tuple), __tuple_types<_Tp...>(), typename __make_tuple_indices::type()); return *this; @@ -971,7 +975,7 @@ _LIBCPP_DIAGNOSTIC_POP tuple& operator=(tuple<_Up...> const& __tuple) _NOEXCEPT_((_And...>::value)) { - _VSTD::__memberwise_copy_assign(*this, __tuple, + std::__memberwise_copy_assign(*this, __tuple, typename __make_tuple_indices::type()); return *this; } @@ -986,7 +990,7 @@ _LIBCPP_DIAGNOSTIC_POP tuple& operator=(tuple<_Up...>&& __tuple) _NOEXCEPT_((_And...>::value)) { - _VSTD::__memberwise_forward_assign(*this, _VSTD::move(__tuple), + std::__memberwise_forward_assign(*this, std::move(__tuple), __tuple_types<_Up...>(), typename __make_tuple_indices::type()); return *this; @@ -1064,8 +1068,8 @@ _LIBCPP_DIAGNOSTIC_POP tuple& operator=(pair<_Up1, _Up2> const& __pair) _NOEXCEPT_((_NothrowAssignFromPair const&>::value)) { - _VSTD::get<0>(*this) = __pair.first; - _VSTD::get<1>(*this) = __pair.second; + std::get<0>(*this) = __pair.first; + std::get<1>(*this) = __pair.second; return *this; } @@ -1076,8 +1080,8 @@ _LIBCPP_DIAGNOSTIC_POP tuple& operator=(pair<_Up1, _Up2>&& __pair) _NOEXCEPT_((_NothrowAssignFromPair&&>::value)) { - _VSTD::get<0>(*this) = _VSTD::forward<_Up1>(__pair.first); - _VSTD::get<1>(*this) = _VSTD::forward<_Up2>(__pair.second); + std::get<0>(*this) = std::forward<_Up1>(__pair.first); + std::get<1>(*this) = std::forward<_Up2>(__pair.second); return *this; } @@ -1092,7 +1096,7 @@ _LIBCPP_DIAGNOSTIC_POP tuple& operator=(array<_Up, _Np> const& __array) _NOEXCEPT_((_And...>::value)) { - _VSTD::__memberwise_copy_assign(*this, __array, + std::__memberwise_copy_assign(*this, __array, typename __make_tuple_indices::type()); return *this; } @@ -1108,7 +1112,7 @@ _LIBCPP_DIAGNOSTIC_POP tuple& operator=(array<_Up, _Np>&& __array) _NOEXCEPT_((_And...>::value)) { - _VSTD::__memberwise_forward_assign(*this, _VSTD::move(__array), + std::__memberwise_forward_assign(*this, std::move(__array), __tuple_types<_If...>(), typename __make_tuple_indices::type()); return *this; @@ -1279,28 +1283,28 @@ template inline _LIBCPP_HIDE_FROM_ABI constexpr _T1& get(tuple<_Args...>& __tup) noexcept { - return _VSTD::get<__find_exactly_one_t<_T1, _Args...>::value>(__tup); + return std::get<__find_exactly_one_t<_T1, _Args...>::value>(__tup); } template inline _LIBCPP_HIDE_FROM_ABI constexpr _T1 const& get(tuple<_Args...> const& __tup) noexcept { - return _VSTD::get<__find_exactly_one_t<_T1, _Args...>::value>(__tup); + return std::get<__find_exactly_one_t<_T1, _Args...>::value>(__tup); } template inline _LIBCPP_HIDE_FROM_ABI constexpr _T1&& get(tuple<_Args...>&& __tup) noexcept { - return _VSTD::get<__find_exactly_one_t<_T1, _Args...>::value>(_VSTD::move(__tup)); + return std::get<__find_exactly_one_t<_T1, _Args...>::value>(std::move(__tup)); } template inline _LIBCPP_HIDE_FROM_ABI constexpr _T1 const&& get(tuple<_Args...> const&& __tup) noexcept { - return _VSTD::get<__find_exactly_one_t<_T1, _Args...>::value>(_VSTD::move(__tup)); + return std::get<__find_exactly_one_t<_T1, _Args...>::value>(std::move(__tup)); } #endif @@ -1336,7 +1340,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 tuple::type...> make_tuple(_Tp&&... __t) { - return tuple::type...>(_VSTD::forward<_Tp>(__t)...); + return tuple::type...>(std::forward<_Tp>(__t)...); } template @@ -1344,7 +1348,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 tuple<_Tp&&...> forward_as_tuple(_Tp&&... __t) _NOEXCEPT { - return tuple<_Tp&&...>(_VSTD::forward<_Tp>(__t)...); + return tuple<_Tp&&...>(std::forward<_Tp>(__t)...); } template @@ -1354,7 +1358,7 @@ struct __tuple_equal _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 bool operator()(const _Tp& __x, const _Up& __y) { - return __tuple_equal<_Ip - 1>()(__x, __y) && _VSTD::get<_Ip-1>(__x) == _VSTD::get<_Ip-1>(__y); + return __tuple_equal<_Ip - 1>()(__x, __y) && std::get<_Ip-1>(__x) == std::get<_Ip-1>(__y); } }; @@ -1387,7 +1391,7 @@ _LIBCPP_HIDE_FROM_ABI constexpr auto __tuple_compare_three_way(const tuple<_Tp...>& __x, const tuple<_Up...>& __y, index_sequence<_Is...>) { common_comparison_category_t<__synth_three_way_result<_Tp, _Up>...> __result = strong_ordering::equal; - static_cast(((__result = _VSTD::__synth_three_way(_VSTD::get<_Is>(__x), _VSTD::get<_Is>(__y)), __result != 0) || ...)); + static_cast(((__result = std::__synth_three_way(std::get<_Is>(__x), std::get<_Is>(__y)), __result != 0) || ...)); return __result; } @@ -1397,7 +1401,7 @@ _LIBCPP_HIDE_FROM_ABI constexpr common_comparison_category_t<__synth_three_way_result<_Tp, _Up>...> operator<=>(const tuple<_Tp...>& __x, const tuple<_Up...>& __y) { - return _VSTD::__tuple_compare_three_way(__x, __y, index_sequence_for<_Tp...>{}); + return std::__tuple_compare_three_way(__x, __y, index_sequence_for<_Tp...>{}); } #else // _LIBCPP_STD_VER >= 20 @@ -1418,9 +1422,9 @@ struct __tuple_less bool operator()(const _Tp& __x, const _Up& __y) { const size_t __idx = tuple_size<_Tp>::value - _Ip; - if (_VSTD::get<__idx>(__x) < _VSTD::get<__idx>(__y)) + if (std::get<__idx>(__x) < std::get<__idx>(__y)) return true; - if (_VSTD::get<__idx>(__y) < _VSTD::get<__idx>(__x)) + if (std::get<__idx>(__y) < std::get<__idx>(__x)) return false; return __tuple_less<_Ip-1>()(__x, __y); } @@ -1573,9 +1577,9 @@ struct __tuple_cat, __tuple_indices<_I0...>, __tuple_indices<_J operator()(tuple<_Types...> __t, _Tuple0&& __t0) { (void)__t; // avoid unused parameter warning on GCC when _I0 is empty - return _VSTD::forward_as_tuple( - _VSTD::forward<_Types>(_VSTD::get<_I0>(__t))..., - _VSTD::get<_J0>(_VSTD::forward<_Tuple0>(__t0))...); + return std::forward_as_tuple( + std::forward<_Types>(std::get<_I0>(__t))..., + std::get<_J0>(std::forward<_Tuple0>(__t0))...); } template @@ -1589,10 +1593,10 @@ struct __tuple_cat, __tuple_indices<_I0...>, __tuple_indices<_J return __tuple_cat::type>&&...>, typename __make_tuple_indices::value>::type, typename __make_tuple_indices::value>::type>()( - _VSTD::forward_as_tuple( - _VSTD::forward<_Types>(_VSTD::get<_I0>(__t))..., - _VSTD::get<_J0>(_VSTD::forward<_Tuple0>(__t0))...), - _VSTD::forward<_Tuple1>(__t1), _VSTD::forward<_Tuples>(__tpls)...); + std::forward_as_tuple( + std::forward<_Types>(std::get<_I0>(__t))..., + std::get<_J0>(std::forward<_Tuple0>(__t0))...), + std::forward<_Tuple1>(__t1), std::forward<_Tuples>(__tpls)...); } }; @@ -1604,8 +1608,8 @@ tuple_cat(_Tuple0&& __t0, _Tuples&&... __tpls) typedef _LIBCPP_NODEBUG __libcpp_remove_reference_t<_Tuple0> _T0; return __tuple_cat, __tuple_indices<>, typename __make_tuple_indices::value>::type>() - (tuple<>(), _VSTD::forward<_Tuple0>(__t0), - _VSTD::forward<_Tuples>(__tpls)...); + (tuple<>(), std::forward<_Tuple0>(__t0), + std::forward<_Tuples>(__tpls)...); } template @@ -1618,8 +1622,8 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 pair<_T1, _T2>::pair(piecewise_construct_t, tuple<_Args1...>& __first_args, tuple<_Args2...>& __second_args, __tuple_indices<_I1...>, __tuple_indices<_I2...>) - : first(_VSTD::forward<_Args1>(_VSTD::get<_I1>( __first_args))...), - second(_VSTD::forward<_Args2>(_VSTD::get<_I2>(__second_args))...) + : first(std::forward<_Args1>(std::get<_I1>( __first_args))...), + second(std::forward<_Args2>(std::get<_I2>(__second_args))...) { } @@ -1634,17 +1638,17 @@ inline _LIBCPP_HIDE_FROM_ABI constexpr decltype(auto) __apply_tuple_impl(_Fn && __f, _Tuple && __t, __tuple_indices<_Id...>) _LIBCPP_NOEXCEPT_RETURN( - _VSTD::__invoke( - _VSTD::forward<_Fn>(__f), - _VSTD::get<_Id>(_VSTD::forward<_Tuple>(__t))...) + std::__invoke( + std::forward<_Fn>(__f), + std::get<_Id>(std::forward<_Tuple>(__t))...) ) template inline _LIBCPP_HIDE_FROM_ABI constexpr decltype(auto) apply(_Fn && __f, _Tuple && __t) _LIBCPP_NOEXCEPT_RETURN( - _VSTD::__apply_tuple_impl( - _VSTD::forward<_Fn>(__f), _VSTD::forward<_Tuple>(__t), + std::__apply_tuple_impl( + std::forward<_Fn>(__f), std::forward<_Tuple>(__t), typename __make_tuple_indices>>::type{}) ) @@ -1652,14 +1656,14 @@ template inline _LIBCPP_HIDE_FROM_ABI constexpr _Tp __make_from_tuple_impl(_Tuple&& __t, __tuple_indices<_Idx...>) _LIBCPP_NOEXCEPT_RETURN( - _Tp(_VSTD::get<_Idx>(_VSTD::forward<_Tuple>(__t))...) + _Tp(std::get<_Idx>(std::forward<_Tuple>(__t))...) ) template inline _LIBCPP_HIDE_FROM_ABI constexpr _Tp make_from_tuple(_Tuple&& __t) _LIBCPP_NOEXCEPT_RETURN( - _VSTD::__make_from_tuple_impl<_Tp>(_VSTD::forward<_Tuple>(__t), + std::__make_from_tuple_impl<_Tp>(std::forward<_Tuple>(__t), typename __make_tuple_indices>>::type{}) ) diff --git a/libcxx/include/unordered_map b/libcxx/include/unordered_map index f86216a3ac14..c8abefd9ead5 100644 --- a/libcxx/include/unordered_map +++ b/libcxx/include/unordered_map @@ -659,7 +659,7 @@ public: void swap(__unordered_map_hasher& __y) _NOEXCEPT_(__is_nothrow_swappable<_Hash>::value) { - using _VSTD::swap; + using std::swap; swap(static_cast<_Hash&>(*this), static_cast<_Hash&>(__y)); } }; @@ -695,7 +695,7 @@ public: void swap(__unordered_map_hasher& __y) _NOEXCEPT_(__is_nothrow_swappable<_Hash>::value) { - using _VSTD::swap; + using std::swap; swap(__hash_, __y.__hash_); } }; @@ -757,7 +757,7 @@ public: void swap(__unordered_map_equal& __y) _NOEXCEPT_(__is_nothrow_swappable<_Pred>::value) { - using _VSTD::swap; + using std::swap; swap(static_cast<_Pred&>(*this), static_cast<_Pred&>(__y)); } }; @@ -808,7 +808,7 @@ public: void swap(__unordered_map_equal& __y) _NOEXCEPT_(__is_nothrow_swappable<_Pred>::value) { - using _VSTD::swap; + using std::swap; swap(__pred_, __y.__pred_); } }; @@ -874,9 +874,9 @@ public: void operator()(pointer __p) _NOEXCEPT { if (__second_constructed) - __alloc_traits::destroy(__na_, _VSTD::addressof(__p->__get_value().__get_value().second)); + __alloc_traits::destroy(__na_, std::addressof(__p->__get_value().__get_value().second)); if (__first_constructed) - __alloc_traits::destroy(__na_, _VSTD::addressof(__p->__get_value().__get_value().first)); + __alloc_traits::destroy(__na_, std::addressof(__p->__get_value().__get_value().first)); if (__p) __alloc_traits::deallocate(__na_, __p, 1); } @@ -900,7 +900,7 @@ public: value_type& __get_value() { #if _LIBCPP_STD_VER >= 17 - return *_VSTD::launder(_VSTD::addressof(__cc_)); + return *std::launder(std::addressof(__cc_)); #else return __cc_; #endif @@ -910,7 +910,7 @@ public: const value_type& __get_value() const { #if _LIBCPP_STD_VER >= 17 - return *_VSTD::launder(_VSTD::addressof(__cc_)); + return *std::launder(std::addressof(__cc_)); #else return __cc_; #endif @@ -928,8 +928,8 @@ public: { value_type& __v = __get_value(); return __nc_rref_pair_type( - _VSTD::move(const_cast(__v.first)), - _VSTD::move(__v.second)); + std::move(const_cast(__v.first)), + std::move(__v.second)); } _LIBCPP_HIDE_FROM_ABI @@ -952,7 +952,7 @@ public: _LIBCPP_HIDE_FROM_ABI __hash_value_type& operator=(_ValueTp&& __v) { - __ref() = _VSTD::forward<_ValueTp>(__v); + __ref() = std::forward<_ValueTp>(__v); return *this; } @@ -1263,7 +1263,7 @@ public: #ifndef _LIBCPP_CXX03_LANG __table_ = __u.__table_; #else - if (this != _VSTD::addressof(__u)) { + if (this != std::addressof(__u)) { __table_.clear(); __table_.hash_function() = __u.__table_.hash_function(); __table_.key_eq() = __u.__table_.key_eq(); @@ -1335,36 +1335,36 @@ public: _LIBCPP_HIDE_FROM_ABI pair insert(value_type&& __x) - {return __table_.__insert_unique(_VSTD::move(__x));} + {return __table_.__insert_unique(std::move(__x));} _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator, value_type&& __x) { - return __table_.__insert_unique(_VSTD::move(__x)).first; + return __table_.__insert_unique(std::move(__x)).first; } template ::value> > _LIBCPP_HIDE_FROM_ABI pair insert(_Pp&& __x) - {return __table_.__insert_unique(_VSTD::forward<_Pp>(__x));} + {return __table_.__insert_unique(std::forward<_Pp>(__x));} template ::value> > _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator, _Pp&& __x) { - return insert(_VSTD::forward<_Pp>(__x)).first; + return insert(std::forward<_Pp>(__x)).first; } template _LIBCPP_HIDE_FROM_ABI pair emplace(_Args&&... __args) { - return __table_.__emplace_unique(_VSTD::forward<_Args>(__args)...); + return __table_.__emplace_unique(std::forward<_Args>(__args)...); } template _LIBCPP_HIDE_FROM_ABI iterator emplace_hint(const_iterator, _Args&&... __args) { - return __table_.__emplace_unique(_VSTD::forward<_Args>(__args)...).first; + return __table_.__emplace_unique(std::forward<_Args>(__args)...).first; } #endif // _LIBCPP_CXX03_LANG @@ -1375,8 +1375,8 @@ public: pair try_emplace(const key_type& __k, _Args&&... __args) { return __table_.__emplace_unique_key_args(__k, piecewise_construct, - _VSTD::forward_as_tuple(__k), - _VSTD::forward_as_tuple(_VSTD::forward<_Args>(__args)...)); + std::forward_as_tuple(__k), + std::forward_as_tuple(std::forward<_Args>(__args)...)); } template @@ -1384,22 +1384,22 @@ public: pair try_emplace(key_type&& __k, _Args&&... __args) { return __table_.__emplace_unique_key_args(__k, piecewise_construct, - _VSTD::forward_as_tuple(_VSTD::move(__k)), - _VSTD::forward_as_tuple(_VSTD::forward<_Args>(__args)...)); + std::forward_as_tuple(std::move(__k)), + std::forward_as_tuple(std::forward<_Args>(__args)...)); } template _LIBCPP_HIDE_FROM_ABI iterator try_emplace(const_iterator, const key_type& __k, _Args&&... __args) { - return try_emplace(__k, _VSTD::forward<_Args>(__args)...).first; + return try_emplace(__k, std::forward<_Args>(__args)...).first; } template _LIBCPP_HIDE_FROM_ABI iterator try_emplace(const_iterator, key_type&& __k, _Args&&... __args) { - return try_emplace(_VSTD::move(__k), _VSTD::forward<_Args>(__args)...).first; + return try_emplace(std::move(__k), std::forward<_Args>(__args)...).first; } template @@ -1407,9 +1407,9 @@ public: pair insert_or_assign(const key_type& __k, _Vp&& __v) { pair __res = __table_.__emplace_unique_key_args(__k, - __k, _VSTD::forward<_Vp>(__v)); + __k, std::forward<_Vp>(__v)); if (!__res.second) { - __res.first->second = _VSTD::forward<_Vp>(__v); + __res.first->second = std::forward<_Vp>(__v); } return __res; } @@ -1419,9 +1419,9 @@ public: pair insert_or_assign(key_type&& __k, _Vp&& __v) { pair __res = __table_.__emplace_unique_key_args(__k, - _VSTD::move(__k), _VSTD::forward<_Vp>(__v)); + std::move(__k), std::forward<_Vp>(__v)); if (!__res.second) { - __res.first->second = _VSTD::forward<_Vp>(__v); + __res.first->second = std::forward<_Vp>(__v); } return __res; } @@ -1430,14 +1430,14 @@ public: _LIBCPP_HIDE_FROM_ABI iterator insert_or_assign(const_iterator, const key_type& __k, _Vp&& __v) { - return insert_or_assign(__k, _VSTD::forward<_Vp>(__v)).first; + return insert_or_assign(__k, std::forward<_Vp>(__v)).first; } template _LIBCPP_HIDE_FROM_ABI iterator insert_or_assign(const_iterator, key_type&& __k, _Vp&& __v) { - return insert_or_assign(_VSTD::move(__k), _VSTD::forward<_Vp>(__v)).first; + return insert_or_assign(std::move(__k), std::forward<_Vp>(__v)).first; } #endif // _LIBCPP_STD_VER >= 17 @@ -1460,7 +1460,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to unordered_map::insert()"); return __table_.template __node_handle_insert_unique< - node_type, insert_return_type>(_VSTD::move(__nh)); + node_type, insert_return_type>(std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __hint, node_type&& __nh) @@ -1468,7 +1468,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to unordered_map::insert()"); return __table_.template __node_handle_insert_unique( - __hint.__i_, _VSTD::move(__nh)); + __hint.__i_, std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI node_type extract(key_type const& __key) @@ -1814,14 +1814,14 @@ inline unordered_map<_Key, _Tp, _Hash, _Pred, _Alloc>::unordered_map( unordered_map&& __u) _NOEXCEPT_(is_nothrow_move_constructible<__table>::value) - : __table_(_VSTD::move(__u.__table_)) + : __table_(std::move(__u.__table_)) { } template unordered_map<_Key, _Tp, _Hash, _Pred, _Alloc>::unordered_map( unordered_map&& __u, const allocator_type& __a) - : __table_(_VSTD::move(__u.__table_), typename __table::allocator_type(__a)) + : __table_(std::move(__u.__table_), typename __table::allocator_type(__a)) { if (__a != __u.get_allocator()) { @@ -1866,7 +1866,7 @@ unordered_map<_Key, _Tp, _Hash, _Pred, _Alloc>& unordered_map<_Key, _Tp, _Hash, _Pred, _Alloc>::operator=(unordered_map&& __u) _NOEXCEPT_(is_nothrow_move_assignable<__table>::value) { - __table_ = _VSTD::move(__u.__table_); + __table_ = std::move(__u.__table_); return *this; } @@ -1900,8 +1900,8 @@ _Tp& unordered_map<_Key, _Tp, _Hash, _Pred, _Alloc>::operator[](const key_type& __k) { return __table_.__emplace_unique_key_args(__k, - piecewise_construct, _VSTD::forward_as_tuple(__k), - _VSTD::forward_as_tuple()).first->__get_value().second; + piecewise_construct, std::forward_as_tuple(__k), + std::forward_as_tuple()).first->__get_value().second; } template @@ -1909,8 +1909,8 @@ _Tp& unordered_map<_Key, _Tp, _Hash, _Pred, _Alloc>::operator[](key_type&& __k) { return __table_.__emplace_unique_key_args(__k, - piecewise_construct, _VSTD::forward_as_tuple(_VSTD::move(__k)), - _VSTD::forward_as_tuple()).first->__get_value().second; + piecewise_construct, std::forward_as_tuple(std::move(__k)), + std::forward_as_tuple()).first->__get_value().second; } #else // _LIBCPP_CXX03_LANG @@ -1920,9 +1920,9 @@ unordered_map<_Key, _Tp, _Hash, _Pred, _Alloc>::__construct_node_with_key(const { __node_allocator& __na = __table_.__node_alloc(); __node_holder __h(__node_traits::allocate(__na, 1), _Dp(__na)); - __node_traits::construct(__na, _VSTD::addressof(__h->__get_value().__get_value().first), __k); + __node_traits::construct(__na, std::addressof(__h->__get_value().__get_value().first), __k); __h.get_deleter().__first_constructed = true; - __node_traits::construct(__na, _VSTD::addressof(__h->__get_value().__get_value().second)); + __node_traits::construct(__na, std::addressof(__h->__get_value().__get_value().second)); __h.get_deleter().__second_constructed = true; return __h; } @@ -1979,7 +1979,7 @@ inline _LIBCPP_HIDE_FROM_ABI typename unordered_map<_Key, _Tp, _Hash, _Pred, _Alloc>::size_type erase_if(unordered_map<_Key, _Tp, _Hash, _Pred, _Alloc>& __c, _Predicate __pred) { - return _VSTD::__libcpp_erase_if_container(__c, __pred); + return std::__libcpp_erase_if_container(__c, __pred); } #endif @@ -2179,7 +2179,7 @@ private: #ifndef _LIBCPP_CXX03_LANG __table_ = __u.__table_; #else - if (this != _VSTD::addressof(__u)) { + if (this != std::addressof(__u)) { __table_.clear(); __table_.hash_function() = __u.__table_.hash_function(); __table_.key_eq() = __u.__table_.key_eq(); @@ -2248,32 +2248,32 @@ private: void insert(initializer_list __il) {insert(__il.begin(), __il.end());} _LIBCPP_HIDE_FROM_ABI - iterator insert(value_type&& __x) {return __table_.__insert_multi(_VSTD::move(__x));} + iterator insert(value_type&& __x) {return __table_.__insert_multi(std::move(__x));} _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __p, value_type&& __x) - {return __table_.__insert_multi(__p.__i_, _VSTD::move(__x));} + {return __table_.__insert_multi(__p.__i_, std::move(__x));} template ::value> > _LIBCPP_HIDE_FROM_ABI iterator insert(_Pp&& __x) - {return __table_.__insert_multi(_VSTD::forward<_Pp>(__x));} + {return __table_.__insert_multi(std::forward<_Pp>(__x));} template ::value> > _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __p, _Pp&& __x) - {return __table_.__insert_multi(__p.__i_, _VSTD::forward<_Pp>(__x));} + {return __table_.__insert_multi(__p.__i_, std::forward<_Pp>(__x));} template _LIBCPP_HIDE_FROM_ABI iterator emplace(_Args&&... __args) { - return __table_.__emplace_multi(_VSTD::forward<_Args>(__args)...); + return __table_.__emplace_multi(std::forward<_Args>(__args)...); } template _LIBCPP_HIDE_FROM_ABI iterator emplace_hint(const_iterator __p, _Args&&... __args) { - return __table_.__emplace_hint_multi(__p.__i_, _VSTD::forward<_Args>(__args)...); + return __table_.__emplace_hint_multi(__p.__i_, std::forward<_Args>(__args)...); } #endif // _LIBCPP_CXX03_LANG @@ -2297,7 +2297,7 @@ private: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to unordered_multimap::insert()"); return __table_.template __node_handle_insert_multi( - _VSTD::move(__nh)); + std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __hint, node_type&& __nh) @@ -2305,7 +2305,7 @@ private: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to unordered_multimap::insert()"); return __table_.template __node_handle_insert_multi( - __hint.__i_, _VSTD::move(__nh)); + __hint.__i_, std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI node_type extract(key_type const& __key) @@ -2638,14 +2638,14 @@ inline unordered_multimap<_Key, _Tp, _Hash, _Pred, _Alloc>::unordered_multimap( unordered_multimap&& __u) _NOEXCEPT_(is_nothrow_move_constructible<__table>::value) - : __table_(_VSTD::move(__u.__table_)) + : __table_(std::move(__u.__table_)) { } template unordered_multimap<_Key, _Tp, _Hash, _Pred, _Alloc>::unordered_multimap( unordered_multimap&& __u, const allocator_type& __a) - : __table_(_VSTD::move(__u.__table_), typename __table::allocator_type(__a)) + : __table_(std::move(__u.__table_), typename __table::allocator_type(__a)) { if (__a != __u.get_allocator()) { @@ -2691,7 +2691,7 @@ unordered_multimap<_Key, _Tp, _Hash, _Pred, _Alloc>& unordered_multimap<_Key, _Tp, _Hash, _Pred, _Alloc>::operator=(unordered_multimap&& __u) _NOEXCEPT_(is_nothrow_move_assignable<__table>::value) { - __table_ = _VSTD::move(__u.__table_); + __table_ = std::move(__u.__table_); return *this; } @@ -2737,7 +2737,7 @@ inline _LIBCPP_HIDE_FROM_ABI typename unordered_multimap<_Key, _Tp, _Hash, _Pred, _Alloc>::size_type erase_if(unordered_multimap<_Key, _Tp, _Hash, _Pred, _Alloc>& __c, _Predicate __pred) { - return _VSTD::__libcpp_erase_if_container(__c, __pred); + return std::__libcpp_erase_if_container(__c, __pred); } #endif @@ -2755,9 +2755,9 @@ operator==(const unordered_multimap<_Key, _Tp, _Hash, _Pred, _Alloc>& __x, { _EqRng __xeq = __x.equal_range(__i->first); _EqRng __yeq = __y.equal_range(__i->first); - if (_VSTD::distance(__xeq.first, __xeq.second) != - _VSTD::distance(__yeq.first, __yeq.second) || - !_VSTD::is_permutation(__xeq.first, __xeq.second, __yeq.first)) + if (std::distance(__xeq.first, __xeq.second) != + std::distance(__yeq.first, __yeq.second) || + !std::is_permutation(__xeq.first, __xeq.second, __yeq.first)) return false; __i = __xeq.second; } diff --git a/libcxx/include/unordered_set b/libcxx/include/unordered_set index ec5fb50331ca..4f78bfde11af 100644 --- a/libcxx/include/unordered_set +++ b/libcxx/include/unordered_set @@ -10,6 +10,8 @@ #ifndef _LIBCPP_UNORDERED_SET #define _LIBCPP_UNORDERED_SET +// clang-format off + /* unordered_set synopsis @@ -527,6 +529,8 @@ template */ +// clang-format on + #include <__algorithm/is_permutation.h> #include <__assert> // all public C++ headers provide the assertion handler #include <__availability> @@ -757,7 +761,7 @@ public: template _LIBCPP_HIDE_FROM_ABI pair emplace(_Args&&... __args) - {return __table_.__emplace_unique(_VSTD::forward<_Args>(__args)...);} + {return __table_.__emplace_unique(std::forward<_Args>(__args)...);} template _LIBCPP_HIDE_FROM_ABI iterator emplace_hint(const_iterator, _Args&&... __args) { @@ -766,7 +770,7 @@ public: _LIBCPP_HIDE_FROM_ABI pair insert(value_type&& __x) - {return __table_.__insert_unique(_VSTD::move(__x));} + {return __table_.__insert_unique(std::move(__x));} _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator, value_type&& __x) { return insert(std::move(__x)).first; @@ -815,7 +819,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to unordered_set::insert()"); return __table_.template __node_handle_insert_unique< - node_type, insert_return_type>(_VSTD::move(__nh)); + node_type, insert_return_type>(std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __h, node_type&& __nh) @@ -823,7 +827,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to unordered_set::insert()"); return __table_.template __node_handle_insert_unique( - __h, _VSTD::move(__nh)); + __h, std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI node_type extract(key_type const& __key) @@ -1137,20 +1141,20 @@ inline unordered_set<_Value, _Hash, _Pred, _Alloc>::unordered_set( unordered_set&& __u) _NOEXCEPT_(is_nothrow_move_constructible<__table>::value) - : __table_(_VSTD::move(__u.__table_)) + : __table_(std::move(__u.__table_)) { } template unordered_set<_Value, _Hash, _Pred, _Alloc>::unordered_set( unordered_set&& __u, const allocator_type& __a) - : __table_(_VSTD::move(__u.__table_), __a) + : __table_(std::move(__u.__table_), __a) { if (__a != __u.get_allocator()) { iterator __i = __u.begin(); while (__u.size() != 0) - __table_.__insert_unique(_VSTD::move(__u.__table_.remove(__i++)->__get_value())); + __table_.__insert_unique(std::move(__u.__table_.remove(__i++)->__get_value())); } } @@ -1187,7 +1191,7 @@ unordered_set<_Value, _Hash, _Pred, _Alloc>& unordered_set<_Value, _Hash, _Pred, _Alloc>::operator=(unordered_set&& __u) _NOEXCEPT_(is_nothrow_move_assignable<__table>::value) { - __table_ = _VSTD::move(__u.__table_); + __table_ = std::move(__u.__table_); return *this; } @@ -1231,7 +1235,7 @@ inline _LIBCPP_HIDE_FROM_ABI typename unordered_set<_Value, _Hash, _Pred, _Alloc>::size_type erase_if(unordered_set<_Value, _Hash, _Pred, _Alloc>& __c, _Predicate __pred) { - return _VSTD::__libcpp_erase_if_container(__c, __pred); + return std::__libcpp_erase_if_container(__c, __pred); } #endif @@ -1446,17 +1450,17 @@ public: template _LIBCPP_HIDE_FROM_ABI iterator emplace(_Args&&... __args) - {return __table_.__emplace_multi(_VSTD::forward<_Args>(__args)...);} + {return __table_.__emplace_multi(std::forward<_Args>(__args)...);} template _LIBCPP_HIDE_FROM_ABI iterator emplace_hint(const_iterator __p, _Args&&... __args) - {return __table_.__emplace_hint_multi(__p, _VSTD::forward<_Args>(__args)...);} + {return __table_.__emplace_hint_multi(__p, std::forward<_Args>(__args)...);} _LIBCPP_HIDE_FROM_ABI - iterator insert(value_type&& __x) {return __table_.__insert_multi(_VSTD::move(__x));} + iterator insert(value_type&& __x) {return __table_.__insert_multi(std::move(__x));} _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __p, value_type&& __x) - {return __table_.__insert_multi(__p, _VSTD::move(__x));} + {return __table_.__insert_multi(__p, std::move(__x));} _LIBCPP_HIDE_FROM_ABI void insert(initializer_list __il) {insert(__il.begin(), __il.end());} @@ -1490,7 +1494,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to unordered_multiset::insert()"); return __table_.template __node_handle_insert_multi( - _VSTD::move(__nh)); + std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI iterator insert(const_iterator __hint, node_type&& __nh) @@ -1498,7 +1502,7 @@ public: _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(__nh.empty() || __nh.get_allocator() == get_allocator(), "node_type with incompatible allocator passed to unordered_multiset::insert()"); return __table_.template __node_handle_insert_multi( - __hint, _VSTD::move(__nh)); + __hint, std::move(__nh)); } _LIBCPP_HIDE_FROM_ABI node_type extract(const_iterator __position) @@ -1822,20 +1826,20 @@ inline unordered_multiset<_Value, _Hash, _Pred, _Alloc>::unordered_multiset( unordered_multiset&& __u) _NOEXCEPT_(is_nothrow_move_constructible<__table>::value) - : __table_(_VSTD::move(__u.__table_)) + : __table_(std::move(__u.__table_)) { } template unordered_multiset<_Value, _Hash, _Pred, _Alloc>::unordered_multiset( unordered_multiset&& __u, const allocator_type& __a) - : __table_(_VSTD::move(__u.__table_), __a) + : __table_(std::move(__u.__table_), __a) { if (__a != __u.get_allocator()) { iterator __i = __u.begin(); while (__u.size() != 0) - __table_.__insert_multi(_VSTD::move(__u.__table_.remove(__i++)->__get_value())); + __table_.__insert_multi(std::move(__u.__table_.remove(__i++)->__get_value())); } } @@ -1873,7 +1877,7 @@ unordered_multiset<_Value, _Hash, _Pred, _Alloc>::operator=( unordered_multiset&& __u) _NOEXCEPT_(is_nothrow_move_assignable<__table>::value) { - __table_ = _VSTD::move(__u.__table_); + __table_ = std::move(__u.__table_); return *this; } @@ -1917,7 +1921,7 @@ inline _LIBCPP_HIDE_FROM_ABI typename unordered_multiset<_Value, _Hash, _Pred, _Alloc>::size_type erase_if(unordered_multiset<_Value, _Hash, _Pred, _Alloc>& __c, _Predicate __pred) { - return _VSTD::__libcpp_erase_if_container(__c, __pred); + return std::__libcpp_erase_if_container(__c, __pred); } #endif @@ -1935,9 +1939,9 @@ operator==(const unordered_multiset<_Value, _Hash, _Pred, _Alloc>& __x, { _EqRng __xeq = __x.equal_range(*__i); _EqRng __yeq = __y.equal_range(*__i); - if (_VSTD::distance(__xeq.first, __xeq.second) != - _VSTD::distance(__yeq.first, __yeq.second) || - !_VSTD::is_permutation(__xeq.first, __xeq.second, __yeq.first)) + if (std::distance(__xeq.first, __xeq.second) != + std::distance(__yeq.first, __yeq.second) || + !std::is_permutation(__xeq.first, __xeq.second, __yeq.first)) return false; __i = __xeq.second; } diff --git a/libcxx/include/valarray b/libcxx/include/valarray index d307c95bbd09..19f26d0940a0 100644 --- a/libcxx/include/valarray +++ b/libcxx/include/valarray @@ -2674,9 +2674,9 @@ valarray<_Tp>::__assign_range(const value_type* __f, const value_type* __l) __clear(size()); __begin_ = allocator().allocate(__n); __end_ = __begin_ + __n; - _VSTD::uninitialized_copy(__f, __l, __begin_); + std::uninitialized_copy(__f, __l, __begin_); } else { - _VSTD::copy(__f, __l, __begin_); + std::copy(__f, __l, __begin_); } return *this; } @@ -2685,7 +2685,7 @@ template valarray<_Tp>& valarray<_Tp>::operator=(const valarray& __v) { - if (this != _VSTD::addressof(__v)) + if (this != std::addressof(__v)) return __assign_range(__v.__begin_, __v.__end_); return *this; } @@ -2720,7 +2720,7 @@ inline valarray<_Tp>& valarray<_Tp>::operator=(const value_type& __x) { - _VSTD::fill(__begin_, __end_, __x); + std::fill(__begin_, __end_, __x); return *this; } @@ -3178,8 +3178,8 @@ inline void valarray<_Tp>::swap(valarray& __v) _NOEXCEPT { - _VSTD::swap(__begin_, __v.__begin_); - _VSTD::swap(__end_, __v.__end_); + std::swap(__begin_, __v.__begin_); + std::swap(__end_, __v.__end_); } template @@ -3203,7 +3203,7 @@ valarray<_Tp>::min() const { if (__begin_ == __end_) return value_type(); - return *_VSTD::min_element(__begin_, __end_); + return *std::min_element(__begin_, __end_); } template @@ -3213,7 +3213,7 @@ valarray<_Tp>::max() const { if (__begin_ == __end_) return value_type(); - return *_VSTD::max_element(__begin_, __end_); + return *std::max_element(__begin_, __end_); } template @@ -3230,14 +3230,14 @@ valarray<_Tp>::shift(int __i) const value_type* __te; if (__i >= 0) { - __i = _VSTD::min(__i, static_cast(__n)); + __i = std::min(__i, static_cast(__n)); __sb = __begin_ + __i; __tb = __r.__begin_; __te = __r.__begin_ + (__n - __i); } else { - __i = _VSTD::min(-__i, static_cast(__n)); + __i = std::min(-__i, static_cast(__n)); __sb = __begin_; __tb = __r.__begin_ + __i; __te = __r.__begin_ + __n; diff --git a/libcxx/include/variant b/libcxx/include/variant index edf302a2746a..3b01e5e126d9 100644 --- a/libcxx/include/variant +++ b/libcxx/include/variant @@ -384,13 +384,13 @@ __as_variant(const variant<_Types...>& __vs) noexcept { template _LIBCPP_HIDE_FROM_ABI constexpr variant<_Types...>&& __as_variant(variant<_Types...>&& __vs) noexcept { - return _VSTD::move(__vs); + return std::move(__vs); } template _LIBCPP_HIDE_FROM_ABI constexpr const variant<_Types...>&& __as_variant(const variant<_Types...>&& __vs) noexcept { - return _VSTD::move(__vs); + return std::move(__vs); } namespace __find_detail { @@ -482,13 +482,13 @@ struct __union { template _LIBCPP_HIDE_FROM_ABI static constexpr auto&& __get_alt(_Vp&& __v, in_place_index_t<0>) { - return _VSTD::forward<_Vp>(__v).__head; + return std::forward<_Vp>(__v).__head; } template _LIBCPP_HIDE_FROM_ABI static constexpr auto&& __get_alt(_Vp&& __v, in_place_index_t<_Ip>) { - return __get_alt(_VSTD::forward<_Vp>(__v).__tail, in_place_index<_Ip - 1>); + return __get_alt(std::forward<_Vp>(__v).__tail, in_place_index<_Ip - 1>); } }; @@ -496,7 +496,7 @@ struct __base { template _LIBCPP_HIDE_FROM_ABI static constexpr auto&& __get_alt(_Vp&& __v) { - return __union::__get_alt(_VSTD::forward<_Vp>(__v).__data, + return __union::__get_alt(std::forward<_Vp>(__v).__data, in_place_index<_Ip>); } }; @@ -505,7 +505,7 @@ struct __variant { template _LIBCPP_HIDE_FROM_ABI static constexpr auto&& __get_alt(_Vp&& __v) { - return __base::__get_alt<_Ip>(_VSTD::forward<_Vp>(__v).__impl_); + return __base::__get_alt<_Ip>(std::forward<_Vp>(__v).__impl_); } }; @@ -520,9 +520,9 @@ struct __base { __visit_alt_at(size_t __index, _Visitor&& __visitor, _Vs&&... __vs) { constexpr auto __fdiagonal = __make_fdiagonal<_Visitor&&, - decltype(_VSTD::forward<_Vs>(__vs).__as_base())...>(); - return __fdiagonal[__index](_VSTD::forward<_Visitor>(__visitor), - _VSTD::forward<_Vs>(__vs).__as_base()...); + decltype(std::forward<_Vs>(__vs).__as_base())...>(); + return __fdiagonal[__index](std::forward<_Visitor>(__visitor), + std::forward<_Vs>(__vs).__as_base()...); } template @@ -531,10 +531,10 @@ struct __base { _Vs&&... __vs) { constexpr auto __fmatrix = __make_fmatrix<_Visitor&&, - decltype(_VSTD::forward<_Vs>(__vs).__as_base())...>(); + decltype(std::forward<_Vs>(__vs).__as_base())...>(); return __at(__fmatrix, __vs.index()...)( - _VSTD::forward<_Visitor>(__visitor), - _VSTD::forward<_Vs>(__vs).__as_base()...); + std::forward<_Visitor>(__visitor), + std::forward<_Vs>(__vs).__as_base()...); } private: @@ -561,7 +561,7 @@ private: static constexpr auto __make_farray(_Fs&&... __fs) { __std_visit_visitor_return_type_check<__remove_cvref_t<_Fs>...>(); using __result = __farray...>, sizeof...(_Fs)>; - return __result{{_VSTD::forward<_Fs>(__fs)...}}; + return __result{{std::forward<_Fs>(__fs)...}}; } template @@ -569,7 +569,7 @@ private: template _LIBCPP_HIDE_FROM_ABI static constexpr decltype(auto) __dispatch(_Fp __f, _Vs... __vs) { - return _VSTD::__invoke( + return std::__invoke( static_cast<_Fp>(__f), __access::__base::__get_alt<_Is>(static_cast<_Vs>(__vs))...); } @@ -631,8 +631,8 @@ struct __variant { static constexpr decltype(auto) __visit_alt_at(size_t __index, _Visitor&& __visitor, _Vs&&... __vs) { return __base::__visit_alt_at(__index, - _VSTD::forward<_Visitor>(__visitor), - _VSTD::forward<_Vs>(__vs).__impl_...); + std::forward<_Visitor>(__visitor), + std::forward<_Vs>(__vs).__impl_...); } template @@ -640,8 +640,8 @@ struct __variant { static constexpr decltype(auto) __visit_alt(_Visitor&& __visitor, _Vs&&... __vs) { return __base::__visit_alt( - _VSTD::forward<_Visitor>(__visitor), - _VSTD::__as_variant(_VSTD::forward<_Vs>(__vs)).__impl_...); + std::forward<_Visitor>(__visitor), + std::__as_variant(std::forward<_Vs>(__vs)).__impl_...); } template @@ -650,8 +650,8 @@ struct __variant { __visit_value_at(size_t __index, _Visitor&& __visitor, _Vs&&... __vs) { return __visit_alt_at( __index, - __make_value_visitor(_VSTD::forward<_Visitor>(__visitor)), - _VSTD::forward<_Vs>(__vs)...); + __make_value_visitor(std::forward<_Visitor>(__visitor)), + std::forward<_Vs>(__vs)...); } template @@ -659,8 +659,8 @@ struct __variant { static constexpr decltype(auto) __visit_value(_Visitor&& __visitor, _Vs&&... __vs) { return __visit_alt( - __make_value_visitor(_VSTD::forward<_Visitor>(__visitor)), - _VSTD::forward<_Vs>(__vs)...); + __make_value_visitor(std::forward<_Visitor>(__visitor)), + std::forward<_Vs>(__vs)...); } #if _LIBCPP_STD_VER >= 20 @@ -669,8 +669,8 @@ struct __variant { static constexpr _Rp __visit_value(_Visitor&& __visitor, _Vs&&... __vs) { return __visit_alt( - __make_value_visitor<_Rp>(_VSTD::forward<_Visitor>(__visitor)), - _VSTD::forward<_Vs>(__vs)...); + __make_value_visitor<_Rp>(std::forward<_Visitor>(__visitor)), + std::forward<_Vs>(__vs)...); } #endif @@ -688,9 +688,9 @@ private: constexpr decltype(auto) operator()(_Alts&&... __alts) const { __std_visit_exhaustive_visitor_check< _Visitor, - decltype((_VSTD::forward<_Alts>(__alts).__value))...>(); - return _VSTD::__invoke(_VSTD::forward<_Visitor>(__visitor), - _VSTD::forward<_Alts>(__alts).__value...); + decltype((std::forward<_Alts>(__alts).__value))...>(); + return std::__invoke(std::forward<_Visitor>(__visitor), + std::forward<_Alts>(__alts).__value...); } _Visitor&& __visitor; }; @@ -703,14 +703,14 @@ private: constexpr _Rp operator()(_Alts&&... __alts) const { __std_visit_exhaustive_visitor_check< _Visitor, - decltype((_VSTD::forward<_Alts>(__alts).__value))...>(); + decltype((std::forward<_Alts>(__alts).__value))...>(); if constexpr (is_void_v<_Rp>) { - _VSTD::__invoke(_VSTD::forward<_Visitor>(__visitor), - _VSTD::forward<_Alts>(__alts).__value...); + std::__invoke(std::forward<_Visitor>(__visitor), + std::forward<_Alts>(__alts).__value...); } else { - return _VSTD::__invoke(_VSTD::forward<_Visitor>(__visitor), - _VSTD::forward<_Alts>(__alts).__value...); + return std::__invoke(std::forward<_Visitor>(__visitor), + std::forward<_Alts>(__alts).__value...); } } @@ -721,14 +721,14 @@ private: template _LIBCPP_HIDE_FROM_ABI static constexpr auto __make_value_visitor(_Visitor&& __visitor) { - return __value_visitor<_Visitor>{_VSTD::forward<_Visitor>(__visitor)}; + return __value_visitor<_Visitor>{std::forward<_Visitor>(__visitor)}; } #if _LIBCPP_STD_VER >= 20 template _LIBCPP_HIDE_FROM_ABI static constexpr auto __make_value_visitor(_Visitor&& __visitor) { - return __value_visitor_return_type<_Rp, _Visitor>{_VSTD::forward<_Visitor>(__visitor)}; + return __value_visitor_return_type<_Rp, _Visitor>{std::forward<_Visitor>(__visitor)}; } #endif }; @@ -742,7 +742,7 @@ struct _LIBCPP_TEMPLATE_VIS __alt { template _LIBCPP_HIDE_FROM_ABI explicit constexpr __alt(in_place_t, _Args&&... __args) - : __value(_VSTD::forward<_Args>(__args)...) {} + : __value(std::forward<_Args>(__args)...) {} __value_type __value; }; @@ -766,12 +766,12 @@ union _LIBCPP_TEMPLATE_VIS __union<_DestructibleTrait, _Index> {}; template \ _LIBCPP_HIDE_FROM_ABI \ explicit constexpr __union(in_place_index_t<0>, _Args&&... __args) \ - : __head(in_place, _VSTD::forward<_Args>(__args)...) {} \ + : __head(in_place, std::forward<_Args>(__args)...) {} \ \ template \ _LIBCPP_HIDE_FROM_ABI \ explicit constexpr __union(in_place_index_t<_Ip>, _Args&&... __args) \ - : __tail(in_place_index<_Ip - 1>, _VSTD::forward<_Args>(__args)...) {} \ + : __tail(in_place_index<_Ip - 1>, std::forward<_Args>(__args)...) {} \ \ __union(const __union&) = default; \ __union(__union&&) = default; \ @@ -808,7 +808,7 @@ public: _LIBCPP_HIDE_FROM_ABI explicit constexpr __base(in_place_index_t<_Ip>, _Args&&... __args) : - __data(in_place_index<_Ip>, _VSTD::forward<_Args>(__args)...), + __data(in_place_index<_Ip>, std::forward<_Args>(__args)...), __index(_Ip) {} _LIBCPP_HIDE_FROM_ABI @@ -826,13 +826,13 @@ protected: constexpr auto&& __as_base() & { return *this; } _LIBCPP_HIDE_FROM_ABI - constexpr auto&& __as_base() && { return _VSTD::move(*this); } + constexpr auto&& __as_base() && { return std::move(*this); } _LIBCPP_HIDE_FROM_ABI constexpr auto&& __as_base() const & { return *this; } _LIBCPP_HIDE_FROM_ABI - constexpr auto&& __as_base() const && { return _VSTD::move(*this); } + constexpr auto&& __as_base() const && { return std::move(*this); } _LIBCPP_HIDE_FROM_ABI static constexpr size_t __size() { return sizeof...(_Types); } @@ -909,8 +909,8 @@ protected: template _LIBCPP_HIDE_FROM_ABI static _Tp& __construct_alt(__alt<_Ip, _Tp>& __a, _Args&&... __args) { - ::new ((void*)_VSTD::addressof(__a)) - __alt<_Ip, _Tp>(in_place, _VSTD::forward<_Args>(__args)...); + ::new ((void*)std::addressof(__a)) + __alt<_Ip, _Tp>(in_place, std::forward<_Args>(__args)...); return __a.__value; } @@ -924,9 +924,9 @@ protected: [](auto& __lhs_alt, auto&& __rhs_alt) { __construct_alt( __lhs_alt, - _VSTD::forward(__rhs_alt).__value); + std::forward(__rhs_alt).__value); }, - __lhs, _VSTD::forward<_Rhs>(__rhs)); + __lhs, std::forward<_Rhs>(__rhs)); __lhs.__index = __rhs.index(); } } @@ -963,7 +963,7 @@ _LIBCPP_VARIANT_MOVE_CONSTRUCTOR( __move_constructor(__move_constructor&& __that) noexcept( __all...>::value) : __move_constructor(__valueless_t{}) { - this->__generic_construct(*this, _VSTD::move(__that)); + this->__generic_construct(*this, std::move(__that)); }); _LIBCPP_VARIANT_MOVE_CONSTRUCTOR( @@ -1024,7 +1024,7 @@ public: auto& __emplace(_Args&&... __args) { this->__destroy(); auto& __res = this->__construct_alt(__access::__base::__get_alt<_Ip>(*this), - _VSTD::forward<_Args>(__args)...); + std::forward<_Args>(__args)...); this->__index = _Ip; return __res; } @@ -1034,18 +1034,18 @@ protected: _LIBCPP_HIDE_FROM_ABI void __assign_alt(__alt<_Ip, _Tp>& __a, _Arg&& __arg) { if (this->index() == _Ip) { - __a.__value = _VSTD::forward<_Arg>(__arg); + __a.__value = std::forward<_Arg>(__arg); } else { struct { _LIBCPP_HIDE_FROM_ABI void operator()(true_type) const { - __this->__emplace<_Ip>(_VSTD::forward<_Arg>(__arg)); + __this->__emplace<_Ip>(std::forward<_Arg>(__arg)); } _LIBCPP_HIDE_FROM_ABI void operator()(false_type) const { - __this->__emplace<_Ip>(_Tp(_VSTD::forward<_Arg>(__arg))); + __this->__emplace<_Ip>(_Tp(std::forward<_Arg>(__arg))); } __assignment* __this; _Arg&& __arg; - } __impl{this, _VSTD::forward<_Arg>(__arg)}; + } __impl{this, std::forward<_Arg>(__arg)}; __impl(bool_constant || !is_nothrow_move_constructible_v<_Tp>>{}); } @@ -1064,9 +1064,9 @@ protected: [this](auto& __this_alt, auto&& __that_alt) { this->__assign_alt( __this_alt, - _VSTD::forward(__that_alt).__value); + std::forward(__that_alt).__value); }, - *this, _VSTD::forward<_That>(__that)); + *this, std::forward<_That>(__that)); } } }; @@ -1102,7 +1102,7 @@ _LIBCPP_VARIANT_MOVE_ASSIGNMENT( __move_assignment& operator=(__move_assignment&& __that) noexcept( __all<(is_nothrow_move_constructible_v<_Types> && is_nothrow_move_assignable_v<_Types>)...>::value) { - this->__generic_assign(_VSTD::move(__that)); + this->__generic_assign(std::move(__that)); return *this; }); @@ -1167,7 +1167,7 @@ public: _LIBCPP_HIDE_FROM_ABI void __assign(_Arg&& __arg) { this->__assign_alt(__access::__base::__get_alt<_Ip>(*this), - _VSTD::forward<_Arg>(__arg)); + std::forward<_Arg>(__arg)); } inline _LIBCPP_HIDE_FROM_ABI @@ -1178,30 +1178,30 @@ public: __visitation::__base::__visit_alt_at( this->index(), [](auto& __this_alt, auto& __that_alt) { - using _VSTD::swap; + using std::swap; swap(__this_alt.__value, __that_alt.__value); }, *this, __that); } else { __impl* __lhs = this; - __impl* __rhs = _VSTD::addressof(__that); + __impl* __rhs = std::addressof(__that); if (__lhs->__move_nothrow() && !__rhs->__move_nothrow()) { - _VSTD::swap(__lhs, __rhs); + std::swap(__lhs, __rhs); } - __impl __tmp(_VSTD::move(*__rhs)); + __impl __tmp(std::move(*__rhs)); #ifndef _LIBCPP_HAS_NO_EXCEPTIONS if constexpr (__all...>::value) { - this->__generic_construct(*__rhs, _VSTD::move(*__lhs)); + this->__generic_construct(*__rhs, std::move(*__lhs)); } else { // EXTENSION: When the move construction of `__lhs` into `__rhs` throws // and `__tmp` is nothrow move constructible then we move `__tmp` back // into `__rhs` and provide the strong exception safety guarantee. try { - this->__generic_construct(*__rhs, _VSTD::move(*__lhs)); + this->__generic_construct(*__rhs, std::move(*__lhs)); } catch (...) { if (__tmp.__move_nothrow()) { - this->__generic_construct(*__rhs, _VSTD::move(__tmp)); + this->__generic_construct(*__rhs, std::move(__tmp)); } throw; } @@ -1209,9 +1209,9 @@ public: #else // this isn't consolidated with the `if constexpr` branch above due to // `throw` being ill-formed with exceptions disabled even when discarded. - this->__generic_construct(*__rhs, _VSTD::move(*__lhs)); + this->__generic_construct(*__rhs, std::move(*__lhs)); #endif - this->__generic_construct(*__lhs, _VSTD::move(__tmp)); + this->__generic_construct(*__lhs, std::move(__tmp)); } } @@ -1344,7 +1344,7 @@ public: _LIBCPP_HIDE_FROM_ABI constexpr variant(_Arg&& __arg) noexcept( is_nothrow_constructible_v<_Tp, _Arg>) - : __impl_(in_place_index<_Ip>, _VSTD::forward<_Arg>(__arg)) {} + : __impl_(in_place_index<_Ip>, std::forward<_Arg>(__arg)) {} template , @@ -1354,7 +1354,7 @@ public: explicit constexpr variant( in_place_index_t<_Ip>, _Args&&... __args) noexcept(is_nothrow_constructible_v<_Tp, _Args...>) - : __impl_(in_place_index<_Ip>, _VSTD::forward<_Args>(__args)...) {} + : __impl_(in_place_index<_Ip>, std::forward<_Args>(__args)...) {} template < size_t _Ip, @@ -1370,7 +1370,7 @@ public: initializer_list<_Up> __il, _Args&&... __args) noexcept( is_nothrow_constructible_v<_Tp, initializer_list<_Up>&, _Args...>) - : __impl_(in_place_index<_Ip>, __il, _VSTD::forward<_Args>(__args)...) {} + : __impl_(in_place_index<_Ip>, __il, std::forward<_Args>(__args)...) {} template < class _Tp, @@ -1381,7 +1381,7 @@ public: _LIBCPP_HIDE_FROM_ABI explicit constexpr variant(in_place_type_t<_Tp>, _Args&&... __args) noexcept( is_nothrow_constructible_v<_Tp, _Args...>) - : __impl_(in_place_index<_Ip>, _VSTD::forward<_Args>(__args)...) {} + : __impl_(in_place_index<_Ip>, std::forward<_Args>(__args)...) {} template < class _Tp, @@ -1397,7 +1397,7 @@ public: initializer_list<_Up> __il, _Args&&... __args) noexcept( is_nothrow_constructible_v<_Tp, initializer_list< _Up>&, _Args...>) - : __impl_(in_place_index<_Ip>, __il, _VSTD::forward<_Args>(__args)...) {} + : __impl_(in_place_index<_Ip>, __il, std::forward<_Args>(__args)...) {} _LIBCPP_HIDE_FROM_ABI ~variant() = default; @@ -1416,7 +1416,7 @@ public: variant& operator=(_Arg&& __arg) noexcept( is_nothrow_assignable_v<_Tp&, _Arg> && is_nothrow_constructible_v<_Tp, _Arg>) { - __impl_.template __assign<_Ip>(_VSTD::forward<_Arg>(__arg)); + __impl_.template __assign<_Ip>(std::forward<_Arg>(__arg)); return *this; } @@ -1428,7 +1428,7 @@ public: enable_if_t, int> = 0> _LIBCPP_HIDE_FROM_ABI _Tp& emplace(_Args&&... __args) { - return __impl_.template __emplace<_Ip>(_VSTD::forward<_Args>(__args)...); + return __impl_.template __emplace<_Ip>(std::forward<_Args>(__args)...); } template < @@ -1441,7 +1441,7 @@ public: int> = 0> _LIBCPP_HIDE_FROM_ABI _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { - return __impl_.template __emplace<_Ip>(__il, _VSTD::forward<_Args>(__args)...); + return __impl_.template __emplace<_Ip>(__il, std::forward<_Args>(__args)...); } template < @@ -1452,7 +1452,7 @@ public: enable_if_t, int> = 0> _LIBCPP_HIDE_FROM_ABI _Tp& emplace(_Args&&... __args) { - return __impl_.template __emplace<_Ip>(_VSTD::forward<_Args>(__args)...); + return __impl_.template __emplace<_Ip>(std::forward<_Args>(__args)...); } template < @@ -1465,7 +1465,7 @@ public: int> = 0> _LIBCPP_HIDE_FROM_ABI _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { - return __impl_.template __emplace<_Ip>(__il, _VSTD::forward<_Args>(__args)...); + return __impl_.template __emplace<_Ip>(__il, std::forward<_Args>(__args)...); } _LIBCPP_HIDE_FROM_ABI @@ -1517,7 +1517,7 @@ constexpr auto&& __generic_get(_Vp&& __v) { if (!std::__holds_alternative<_Ip>(__v)) { __throw_bad_variant_access(); } - return __variant::__get_alt<_Ip>(_VSTD::forward<_Vp>(__v)).__value; + return __variant::__get_alt<_Ip>(std::forward<_Vp>(__v)).__value; } template @@ -1537,7 +1537,7 @@ constexpr variant_alternative_t<_Ip, variant<_Types...>>&& get( variant<_Types...>&& __v) { static_assert(_Ip < sizeof...(_Types)); static_assert(!is_void_v>>); - return std::__generic_get<_Ip>(_VSTD::move(__v)); + return std::__generic_get<_Ip>(std::move(__v)); } template @@ -1557,7 +1557,7 @@ constexpr const variant_alternative_t<_Ip, variant<_Types...>>&& get( const variant<_Types...>&& __v) { static_assert(_Ip < sizeof...(_Types)); static_assert(!is_void_v>>); - return std::__generic_get<_Ip>(_VSTD::move(__v)); + return std::__generic_get<_Ip>(std::move(__v)); } template @@ -1565,7 +1565,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr _Tp& get(variant<_Types...>& __v) { static_assert(!is_void_v<_Tp>); - return _VSTD::get<__find_exactly_one_t<_Tp, _Types...>::value>(__v); + return std::get<__find_exactly_one_t<_Tp, _Types...>::value>(__v); } template @@ -1573,8 +1573,8 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr _Tp&& get(variant<_Types...>&& __v) { static_assert(!is_void_v<_Tp>); - return _VSTD::get<__find_exactly_one_t<_Tp, _Types...>::value>( - _VSTD::move(__v)); + return std::get<__find_exactly_one_t<_Tp, _Types...>::value>( + std::move(__v)); } template @@ -1582,7 +1582,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr const _Tp& get(const variant<_Types...>& __v) { static_assert(!is_void_v<_Tp>); - return _VSTD::get<__find_exactly_one_t<_Tp, _Types...>::value>(__v); + return std::get<__find_exactly_one_t<_Tp, _Types...>::value>(__v); } template @@ -1590,8 +1590,8 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr const _Tp&& get(const variant<_Types...>&& __v) { static_assert(!is_void_v<_Tp>); - return _VSTD::get<__find_exactly_one_t<_Tp, _Types...>::value>( - _VSTD::move(__v)); + return std::get<__find_exactly_one_t<_Tp, _Types...>::value>( + std::move(__v)); } template @@ -1599,7 +1599,7 @@ _LIBCPP_HIDE_FROM_ABI constexpr auto* __generic_get_if(_Vp* __v) noexcept { using __variant_detail::__access::__variant; return __v && std::__holds_alternative<_Ip>(*__v) - ? _VSTD::addressof(__variant::__get_alt<_Ip>(*__v).__value) + ? std::addressof(__variant::__get_alt<_Ip>(*__v).__value) : nullptr; } @@ -1626,7 +1626,7 @@ _LIBCPP_HIDE_FROM_ABI constexpr add_pointer_t<_Tp> get_if(variant<_Types...>* __v) noexcept { static_assert(!is_void_v<_Tp>); - return _VSTD::get_if<__find_exactly_one_t<_Tp, _Types...>::value>(__v); + return std::get_if<__find_exactly_one_t<_Tp, _Types...>::value>(__v); } template @@ -1634,7 +1634,7 @@ _LIBCPP_HIDE_FROM_ABI constexpr add_pointer_t get_if(const variant<_Types...>* __v) noexcept { static_assert(!is_void_v<_Tp>); - return _VSTD::get_if<__find_exactly_one_t<_Tp, _Types...>::value>(__v); + return std::get_if<__find_exactly_one_t<_Tp, _Types...>::value>(__v); } template @@ -1642,9 +1642,9 @@ struct __convert_to_bool { template _LIBCPP_HIDE_FROM_ABI constexpr bool operator()(_T1 && __t1, _T2&& __t2) const { - static_assert(is_convertible(__t1), _VSTD::forward<_T2>(__t2))), bool>::value, + static_assert(is_convertible(__t1), std::forward<_T2>(__t2))), bool>::value, "the relational operator does not return a type which is implicitly convertible to bool"); - return _Operator{}(_VSTD::forward<_T1>(__t1), _VSTD::forward<_T2>(__t2)); + return _Operator{}(std::forward<_T1>(__t1), std::forward<_T2>(__t2)); } }; @@ -1745,7 +1745,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr void __throw_if_valueless(_Vs&&... __vs) { const bool __valueless = - (... || _VSTD::__as_variant(__vs).valueless_by_exception()); + (... || std::__as_variant(__vs).valueless_by_exception()); if (__valueless) { __throw_bad_variant_access(); } @@ -1753,27 +1753,27 @@ constexpr void __throw_if_valueless(_Vs&&... __vs) { template < class _Visitor, class... _Vs, - typename = void_t()))...> > + typename = void_t()))...> > _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr decltype(auto) visit(_Visitor&& __visitor, _Vs&&... __vs) { using __variant_detail::__visitation::__variant; - _VSTD::__throw_if_valueless(_VSTD::forward<_Vs>(__vs)...); - return __variant::__visit_value(_VSTD::forward<_Visitor>(__visitor), - _VSTD::forward<_Vs>(__vs)...); + std::__throw_if_valueless(std::forward<_Vs>(__vs)...); + return __variant::__visit_value(std::forward<_Visitor>(__visitor), + std::forward<_Vs>(__vs)...); } #if _LIBCPP_STD_VER >= 20 template < class _Rp, class _Visitor, class... _Vs, - typename = void_t()))...> > + typename = void_t()))...> > _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr _Rp visit(_Visitor&& __visitor, _Vs&&... __vs) { using __variant_detail::__visitation::__variant; - _VSTD::__throw_if_valueless(_VSTD::forward<_Vs>(__vs)...); - return __variant::__visit_value<_Rp>(_VSTD::forward<_Visitor>(__visitor), - _VSTD::forward<_Vs>(__vs)...); + std::__throw_if_valueless(std::forward<_Vs>(__vs)...); + return __variant::__visit_value<_Rp>(std::forward<_Visitor>(__visitor), + std::forward<_Vs>(__vs)...); } #endif @@ -1815,7 +1815,7 @@ template _LIBCPP_HIDE_FROM_ABI constexpr auto&& __unchecked_get(_Vp&& __v) noexcept { using __variant_detail::__access::__variant; - return __variant::__get_alt<_Ip>(_VSTD::forward<_Vp>(__v)).__value; + return __variant::__get_alt<_Ip>(std::forward<_Vp>(__v)).__value; } template diff --git a/libcxx/include/vector b/libcxx/include/vector index 4ec6b602371e..fd2d5e11f0ea 100644 --- a/libcxx/include/vector +++ b/libcxx/include/vector @@ -10,6 +10,8 @@ #ifndef _LIBCPP_VECTOR #define _LIBCPP_VECTOR +// clang-format off + /* vector synopsis @@ -301,6 +303,8 @@ template requires is-vector-bool-reference // Since C++ */ +// clang-format on + #include <__algorithm/copy.h> #include <__algorithm/equal.h> #include <__algorithm/fill_n.h> @@ -846,20 +850,19 @@ private: // __asan_annotate_container_with_allocator to false. // For more details, see the "Using libc++" documentation page or // the documentation for __sanitizer_annotate_contiguous_container. -#ifndef _LIBCPP_HAS_NO_ASAN - _LIBCPP_CONSTEXPR_SINCE_CXX20 - void __annotate_contiguous_container(const void *__beg, const void *__end, - const void *__old_mid, - const void *__new_mid) const + + _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI + void __annotate_contiguous_container([[__maybe_unused__]] const void *__beg, + [[__maybe_unused__]] const void *__end, + [[__maybe_unused__]] const void *__old_mid, + [[__maybe_unused__]] const void *__new_mid) const { +#ifndef _LIBCPP_HAS_NO_ASAN if (!__libcpp_is_constant_evaluated() && __beg != nullptr && __asan_annotate_container_with_allocator<_Allocator>::value) __sanitizer_annotate_contiguous_container(__beg, __end, __old_mid, __new_mid); - } -#else - _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI - void __annotate_contiguous_container(const void*, const void*, const void*, - const void*) const _NOEXCEPT {} #endif + } + _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __annotate_new(size_type __current_size) const _NOEXCEPT { __annotate_contiguous_container(data(), data() + capacity(), diff --git a/libcxx/include/version b/libcxx/include/version index e84790b888d3..a91c344c4360 100644 --- a/libcxx/include/version +++ b/libcxx/include/version @@ -414,9 +414,7 @@ __cpp_lib_within_lifetime 202306L # define __cpp_lib_shared_ptr_arrays 201707L # define __cpp_lib_shift 201806L // # define __cpp_lib_smart_ptr_for_overwrite 202002L -# if __has_builtin(__builtin_source_location) && !(defined(_LIBCPP_APPLE_CLANG_VER) && _LIBCPP_APPLE_CLANG_VER <= 1403) -# define __cpp_lib_source_location 201907L -# endif +# define __cpp_lib_source_location 201907L # define __cpp_lib_span 202002L # define __cpp_lib_ssize 201902L # define __cpp_lib_starts_ends_with 201711L diff --git a/libcxx/src/chrono.cpp b/libcxx/src/chrono.cpp index b31ef19c0a3d..c4446070d0a4 100644 --- a/libcxx/src/chrono.cpp +++ b/libcxx/src/chrono.cpp @@ -94,8 +94,8 @@ public: static system_clock::time_point __libcpp_system_clock_now() { // FILETIME is in 100ns units using filetime_duration = - _VSTD::chrono::duration<__int64, - _VSTD::ratio_multiply<_VSTD::ratio<100, 1>, + std::chrono::duration<__int64, + std::ratio_multiply, nanoseconds::period>>; // The Windows epoch is Jan 1 1601, the Unix epoch Jan 1 1970. diff --git a/libcxx/src/include/to_chars_floating_point.h b/libcxx/src/include/to_chars_floating_point.h index e2409338b9d1..3110bc20e160 100644 --- a/libcxx/src/include/to_chars_floating_point.h +++ b/libcxx/src/include/to_chars_floating_point.h @@ -37,7 +37,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD namespace __itoa { inline constexpr char _Charconv_digits[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z'}; -static_assert(_VSTD::size(_Charconv_digits) == 36); +static_assert(std::size(_Charconv_digits) == 36); } // __itoa // vvvvvvvvvv DERIVED FROM corecrt_internal_fltintrn.h vvvvvvvvvv @@ -119,7 +119,7 @@ to_chars_result _Floating_to_chars_hex_precision( using _Traits = _Floating_type_traits<_Floating>; using _Uint_type = typename _Traits::_Uint_type; - const _Uint_type _Uint_value = _VSTD::bit_cast<_Uint_type>(_Value); + const _Uint_type _Uint_value = std::bit_cast<_Uint_type>(_Value); const _Uint_type _Ieee_mantissa = _Uint_value & _Traits::_Denormal_mantissa_mask; const int32_t _Ieee_exponent = static_cast(_Uint_value >> _Traits::_Exponent_shift); @@ -307,7 +307,7 @@ to_chars_result _Floating_to_chars_hex_precision( if (_Number_of_bits_remaining == 0) { // We've finished printing _Adjusted_mantissa, so all remaining hexits are '0'. - _VSTD::memset(_First, '0', static_cast(_Precision)); + std::memset(_First, '0', static_cast(_Precision)); _First += _Precision; break; } @@ -330,7 +330,7 @@ to_chars_result _Floating_to_chars_hex_precision( *_First++ = _Sign_character; // We've already printed '-' if necessary, so uint32_t _Absolute_exponent avoids testing that again. - return _VSTD::to_chars(_First, _Last, _Absolute_exponent); + return std::to_chars(_First, _Last, _Absolute_exponent); } template @@ -347,7 +347,7 @@ to_chars_result _Floating_to_chars_hex_shortest( using _Traits = _Floating_type_traits<_Floating>; using _Uint_type = typename _Traits::_Uint_type; - const _Uint_type _Uint_value = _VSTD::bit_cast<_Uint_type>(_Value); + const _Uint_type _Uint_value = std::bit_cast<_Uint_type>(_Value); if (_Uint_value == 0) { // zero detected; write "0p+0" and return // C11 7.21.6.1 "The fprintf function"/8: "If the value is zero, the exponent is zero." @@ -359,7 +359,7 @@ to_chars_result _Floating_to_chars_hex_shortest( return {_Last, errc::value_too_large}; } - _VSTD::memcpy(_First, _Str, _Len); + std::memcpy(_First, _Str, _Len); return {_First + _Len, errc{}}; } @@ -457,7 +457,7 @@ to_chars_result _Floating_to_chars_hex_shortest( } // We've already printed '-' if necessary, so static_cast avoids testing that again. - return _VSTD::to_chars(_First, _Last, static_cast(_Unbiased_exponent)); + return std::to_chars(_First, _Last, static_cast(_Unbiased_exponent)); } // For general precision, we can use lookup tables to avoid performing trial formatting. @@ -839,7 +839,7 @@ to_chars_result _Floating_to_chars_general_precision( using _Traits = _Floating_type_traits<_Floating>; using _Uint_type = typename _Traits::_Uint_type; - const _Uint_type _Uint_value = _VSTD::bit_cast<_Uint_type>(_Value); + const _Uint_type _Uint_value = std::bit_cast<_Uint_type>(_Value); if (_Uint_value == 0) { // zero detected; write "0" and return; _Precision is irrelevant due to zero-trimming if (_First == _Last) { @@ -890,7 +890,7 @@ to_chars_result _Floating_to_chars_general_precision( _Table_end = _Table_begin + _Precision + 5; } else { _Table_begin = _Tables::_Ordinary_X_table; - _Table_end = _Table_begin + _VSTD::min(_Precision, _Tables::_Max_P) + 5; + _Table_end = _Table_begin + std::min(_Precision, _Tables::_Max_P) + 5; } // Profiling indicates that linear search is faster than binary search for small tables. @@ -898,11 +898,11 @@ to_chars_result _Floating_to_chars_general_precision( const _Uint_type* const _Table_lower_bound = [=] { if constexpr (!_IsSame<_Floating, float>::value) { if (_Precision > 155) { // threshold determined via profiling - return _VSTD::lower_bound(_Table_begin, _Table_end, _Uint_value, less{}); + return std::lower_bound(_Table_begin, _Table_end, _Uint_value, less{}); } } - return _VSTD::find_if(_Table_begin, _Table_end, [=](const _Uint_type _Elem) { return _Uint_value <= _Elem; }); + return std::find_if(_Table_begin, _Table_end, [=](const _Uint_type _Elem) { return _Uint_value <= _Elem; }); }(); const ptrdiff_t _Table_index = _Table_lower_bound - _Table_begin; @@ -937,17 +937,17 @@ to_chars_result _Floating_to_chars_general_precision( // Write into the local buffer. // Clamping _Effective_precision allows _Buffer to be as small as possible, and increases efficiency. if (_Use_fixed_notation) { - _Effective_precision = _VSTD::min(_Precision - (_Scientific_exponent_X + 1), _Max_fixed_precision); + _Effective_precision = std::min(_Precision - (_Scientific_exponent_X + 1), _Max_fixed_precision); const to_chars_result _Buf_result = - _Floating_to_chars_fixed_precision(_Buffer, _VSTD::end(_Buffer), _Value, _Effective_precision); + _Floating_to_chars_fixed_precision(_Buffer, std::end(_Buffer), _Value, _Effective_precision); _LIBCPP_ASSERT_UNCATEGORIZED(_Buf_result.ec == errc{}, ""); _Significand_last = _Buf_result.ptr; } else { - _Effective_precision = _VSTD::min(_Precision - 1, _Max_scientific_precision); + _Effective_precision = std::min(_Precision - 1, _Max_scientific_precision); const to_chars_result _Buf_result = - _Floating_to_chars_scientific_precision(_Buffer, _VSTD::end(_Buffer), _Value, _Effective_precision); + _Floating_to_chars_scientific_precision(_Buffer, std::end(_Buffer), _Value, _Effective_precision); _LIBCPP_ASSERT_UNCATEGORIZED(_Buf_result.ec == errc{}, ""); - _Significand_last = _VSTD::find(_Buffer, _Buf_result.ptr, 'e'); + _Significand_last = std::find(_Buffer, _Buf_result.ptr, 'e'); _Exponent_first = _Significand_last; _Exponent_last = _Buf_result.ptr; } @@ -968,7 +968,7 @@ to_chars_result _Floating_to_chars_general_precision( if (_Last - _First < _Significand_distance) { return {_Last, errc::value_too_large}; } - _VSTD::memcpy(_First, _Significand_first, static_cast(_Significand_distance)); + std::memcpy(_First, _Significand_first, static_cast(_Significand_distance)); _First += _Significand_distance; // Copy the exponent to the output range. @@ -977,7 +977,7 @@ to_chars_result _Floating_to_chars_general_precision( if (_Last - _First < _Exponent_distance) { return {_Last, errc::value_too_large}; } - _VSTD::memcpy(_First, _Exponent_first, static_cast(_Exponent_distance)); + std::memcpy(_First, _Exponent_first, static_cast(_Exponent_distance)); _First += _Exponent_distance; } @@ -1002,7 +1002,7 @@ to_chars_result _Floating_to_chars( using _Traits = _Floating_type_traits<_Floating>; using _Uint_type = typename _Traits::_Uint_type; - _Uint_type _Uint_value = _VSTD::bit_cast<_Uint_type>(_Value); + _Uint_type _Uint_value = std::bit_cast<_Uint_type>(_Value); const bool _Was_negative = (_Uint_value & _Traits::_Shifted_sign_mask) != 0; @@ -1014,7 +1014,7 @@ to_chars_result _Floating_to_chars( *_First++ = '-'; _Uint_value &= ~_Traits::_Shifted_sign_mask; - _Value = _VSTD::bit_cast<_Floating>(_Uint_value); + _Value = std::bit_cast<_Floating>(_Uint_value); } if ((_Uint_value & _Traits::_Shifted_exponent_mask) == _Traits::_Shifted_exponent_mask) { @@ -1044,7 +1044,7 @@ to_chars_result _Floating_to_chars( return {_Last, errc::value_too_large}; } - _VSTD::memcpy(_First, _Str, _Len); + std::memcpy(_First, _Str, _Len); return {_First + _Len, errc{}}; } diff --git a/libcxx/src/ios.cpp b/libcxx/src/ios.cpp index f17cd6e1dbbb..e80007d42c9d 100644 --- a/libcxx/src/ios.cpp +++ b/libcxx/src/ios.cpp @@ -152,7 +152,7 @@ static size_t __ios_new_cap(size_t __req_size, size_t __current_cap) { // Precondition: __req_size > __current_cap const size_t mx = std::numeric_limits::max() / sizeof(_Tp); if (__req_size < mx/2) - return _VSTD::max(2 * __current_cap, __req_size); + return std::max(2 * __current_cap, __req_size); else return mx; } @@ -394,24 +394,24 @@ ios_base::move(ios_base& rhs) void ios_base::swap(ios_base& rhs) noexcept { - _VSTD::swap(__fmtflags_, rhs.__fmtflags_); - _VSTD::swap(__precision_, rhs.__precision_); - _VSTD::swap(__width_, rhs.__width_); - _VSTD::swap(__rdstate_, rhs.__rdstate_); - _VSTD::swap(__exceptions_, rhs.__exceptions_); + std::swap(__fmtflags_, rhs.__fmtflags_); + std::swap(__precision_, rhs.__precision_); + std::swap(__width_, rhs.__width_); + std::swap(__rdstate_, rhs.__rdstate_); + std::swap(__exceptions_, rhs.__exceptions_); locale& lhs_loc = *reinterpret_cast(&__loc_); locale& rhs_loc = *reinterpret_cast(&rhs.__loc_); - _VSTD::swap(lhs_loc, rhs_loc); - _VSTD::swap(__fn_, rhs.__fn_); - _VSTD::swap(__index_, rhs.__index_); - _VSTD::swap(__event_size_, rhs.__event_size_); - _VSTD::swap(__event_cap_, rhs.__event_cap_); - _VSTD::swap(__iarray_, rhs.__iarray_); - _VSTD::swap(__iarray_size_, rhs.__iarray_size_); - _VSTD::swap(__iarray_cap_, rhs.__iarray_cap_); - _VSTD::swap(__parray_, rhs.__parray_); - _VSTD::swap(__parray_size_, rhs.__parray_size_); - _VSTD::swap(__parray_cap_, rhs.__parray_cap_); + std::swap(lhs_loc, rhs_loc); + std::swap(__fn_, rhs.__fn_); + std::swap(__index_, rhs.__index_); + std::swap(__event_size_, rhs.__event_size_); + std::swap(__event_cap_, rhs.__event_cap_); + std::swap(__iarray_, rhs.__iarray_); + std::swap(__iarray_size_, rhs.__iarray_size_); + std::swap(__iarray_cap_, rhs.__iarray_cap_); + std::swap(__parray_, rhs.__parray_); + std::swap(__parray_size_, rhs.__parray_size_); + std::swap(__parray_cap_, rhs.__parray_cap_); } void diff --git a/libcxx/src/iostream.cpp b/libcxx/src/iostream.cpp index 13e6aeeb2b27..83ee7a6408a1 100644 --- a/libcxx/src/iostream.cpp +++ b/libcxx/src/iostream.cpp @@ -126,7 +126,7 @@ DoIOSInit::DoIOSInit() ostream* cerr_ptr = ::new(cerr) ostream(::new(__cerr) __stdoutbuf(stderr, &mb_cerr)); ::new(clog) ostream(cerr_ptr->rdbuf()); cin_ptr->tie(cout_ptr); - _VSTD::unitbuf(*cerr_ptr); + std::unitbuf(*cerr_ptr); cerr_ptr->tie(cout_ptr); #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS @@ -136,7 +136,7 @@ DoIOSInit::DoIOSInit() ::new(wclog) wostream(wcerr_ptr->rdbuf()); wcin_ptr->tie(wcout_ptr); - _VSTD::unitbuf(*wcerr_ptr); + std::unitbuf(*wcerr_ptr); wcerr_ptr->tie(wcout_ptr); #endif } diff --git a/libcxx/src/locale.cpp b/libcxx/src/locale.cpp index d3de81b95c34..71f7ca482d50 100644 --- a/libcxx/src/locale.cpp +++ b/libcxx/src/locale.cpp @@ -171,13 +171,13 @@ locale::__imp::__imp(size_t refs) name_("C") { facets_.clear(); - install(&make<_VSTD::collate >(1u)); + install(&make >(1u)); #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - install(&make<_VSTD::collate >(1u)); + install(&make >(1u)); #endif - install(&make<_VSTD::ctype >(nullptr, false, 1u)); + install(&make >(nullptr, false, 1u)); #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - install(&make<_VSTD::ctype >(1u)); + install(&make >(1u)); #endif install(&make >(1u)); #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS @@ -225,9 +225,9 @@ _LIBCPP_SUPPRESS_DEPRECATED_POP #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS install(&make >(1u)); #endif - install(&make<_VSTD::messages >(1u)); + install(&make >(1u)); #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - install(&make<_VSTD::messages >(1u)); + install(&make >(1u)); #endif } @@ -413,28 +413,28 @@ locale::__imp::__imp(const __imp& other, const __imp& one, locale::category c) #endif // _LIBCPP_HAS_NO_EXCEPTIONS if (c & locale::collate) { - install_from<_VSTD::collate >(one); + install_from >(one); #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - install_from<_VSTD::collate >(one); + install_from >(one); #endif } if (c & locale::ctype) { - install_from<_VSTD::ctype >(one); + install_from >(one); #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - install_from<_VSTD::ctype >(one); + install_from >(one); #endif - install_from<_VSTD::codecvt >(one); + install_from >(one); _LIBCPP_SUPPRESS_DEPRECATED_PUSH - install_from<_VSTD::codecvt >(one); - install_from<_VSTD::codecvt >(one); + install_from >(one); + install_from >(one); _LIBCPP_SUPPRESS_DEPRECATED_POP #ifndef _LIBCPP_HAS_NO_CHAR8_T - install_from<_VSTD::codecvt >(one); - install_from<_VSTD::codecvt >(one); + install_from >(one); + install_from >(one); #endif #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - install_from<_VSTD::codecvt >(one); + install_from >(one); #endif } if (c & locale::monetary) @@ -482,9 +482,9 @@ _LIBCPP_SUPPRESS_DEPRECATED_POP } if (c & locale::messages) { - install_from<_VSTD::messages >(one); + install_from >(one); #ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - install_from<_VSTD::messages >(one); + install_from >(one); #endif } #ifndef _LIBCPP_HAS_NO_EXCEPTIONS @@ -1058,6 +1058,7 @@ extern "C" const int ** __ctype_toupper_loc(); const ctype::mask* ctype::classic_table() noexcept { + // clang-format off static constexpr const ctype::mask builtin_table[table_size] = { cntrl, cntrl, cntrl, cntrl, @@ -1132,6 +1133,7 @@ ctype::classic_table() noexcept 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + // clang-format on return builtin_table; } #else diff --git a/libcxx/src/regex.cpp b/libcxx/src/regex.cpp index e53d32418690..0825c758bf0c 100644 --- a/libcxx/src/regex.cpp +++ b/libcxx/src/regex.cpp @@ -350,7 +350,7 @@ string __get_collation_name(const char* s) { const collationnames* i = - _VSTD::lower_bound(begin(collatenames), end(collatenames), s, use_strcmp()); + std::lower_bound(begin(collatenames), end(collatenames), s, use_strcmp()); string r; if (i != end(collatenames) && strcmp(s, i->elem_) == 0) r = char(i->char_); @@ -361,7 +361,7 @@ regex_traits::char_class_type __get_classname(const char* s, bool __icase) { const classnames* i = - _VSTD::lower_bound(begin(ClassNames), end(ClassNames), s, use_strcmp()); + std::lower_bound(begin(ClassNames), end(ClassNames), s, use_strcmp()); regex_traits::char_class_type r = 0; if (i != end(ClassNames) && strcmp(s, i->elem_) == 0) { diff --git a/libcxx/src/std_stream.h b/libcxx/src/std_stream.h index 37b4ffd1b4f6..39a2b70b4f47 100644 --- a/libcxx/src/std_stream.h +++ b/libcxx/src/std_stream.h @@ -172,7 +172,7 @@ __stdinbuf<_CharT>::__getchar(bool __consume) } char __extbuf[__limit]; - int __nread = _VSTD::max(1, __encoding_); + int __nread = std::max(1, __encoding_); for (int __i = 0; __i < __nread; ++__i) { int __c = getc(__file_); @@ -191,7 +191,7 @@ __stdinbuf<_CharT>::__getchar(bool __consume) &__1buf, &__1buf + 1, __inxt); switch (__r) { - case _VSTD::codecvt_base::ok: + case std::codecvt_base::ok: break; case codecvt_base::partial: *__st_ = __sv_st; @@ -207,11 +207,11 @@ __stdinbuf<_CharT>::__getchar(bool __consume) break; case codecvt_base::error: return traits_type::eof(); - case _VSTD::codecvt_base::noconv: + case std::codecvt_base::noconv: __1buf = static_cast(__extbuf[0]); break; } - } while (__r == _VSTD::codecvt_base::partial); + } while (__r == std::codecvt_base::partial); if (!__consume) { for (int __i = __nread; __i > 0;) @@ -251,9 +251,9 @@ __stdinbuf<_CharT>::pbackfail(int_type __c) switch (__cv_->out(*__st_, &__ci, &__ci + 1, __inxt, __extbuf, __extbuf + sizeof(__extbuf), __enxt)) { - case _VSTD::codecvt_base::ok: + case std::codecvt_base::ok: break; - case _VSTD::codecvt_base::noconv: + case std::codecvt_base::noconv: __extbuf[0] = static_cast(__last_consumed_); __enxt = __extbuf + 1; break; diff --git a/libcxx/src/strstream.cpp b/libcxx/src/strstream.cpp index c97db698c0a1..a9b5989ec495 100644 --- a/libcxx/src/strstream.cpp +++ b/libcxx/src/strstream.cpp @@ -79,10 +79,10 @@ strstreambuf::~strstreambuf() { void strstreambuf::swap(strstreambuf& __rhs) { streambuf::swap(__rhs); - _VSTD::swap(__strmode_, __rhs.__strmode_); - _VSTD::swap(__alsize_, __rhs.__alsize_); - _VSTD::swap(__palloc_, __rhs.__palloc_); - _VSTD::swap(__pfree_, __rhs.__pfree_); + std::swap(__strmode_, __rhs.__strmode_); + std::swap(__alsize_, __rhs.__alsize_); + std::swap(__palloc_, __rhs.__palloc_); + std::swap(__pfree_, __rhs.__pfree_); } void strstreambuf::freeze(bool __freezefl) { @@ -211,7 +211,7 @@ strstreambuf::pos_type strstreambuf::seekoff(off_type __off, ios_base::seekdir _ char* newpos = eback() + newoff; if (pos_in) - setg(eback(), newpos, _VSTD::max(newpos, egptr())); + setg(eback(), newpos, std::max(newpos, egptr())); if (pos_out) { // min(pbase, newpos), newpos, epptr() __off = epptr() - newpos; @@ -237,7 +237,7 @@ strstreambuf::pos_type strstreambuf::seekpos(pos_type __sp, ios_base::openmode _ char* newpos = eback() + newoff; if (pos_in) - setg(eback(), newpos, _VSTD::max(newpos, egptr())); + setg(eback(), newpos, std::max(newpos, egptr())); if (pos_out) { // min(pbase, newpos), newpos, epptr() off_type temp = epptr() - newpos; diff --git a/libcxx/src/support/win32/thread_win32.cpp b/libcxx/src/support/win32/thread_win32.cpp index c2955f9c8d19..848ed99cf0c4 100644 --- a/libcxx/src/support/win32/thread_win32.cpp +++ b/libcxx/src/support/win32/thread_win32.cpp @@ -115,7 +115,7 @@ int __libcpp_condvar_wait(__libcpp_condvar_t *__cv, __libcpp_mutex_t *__m) int __libcpp_condvar_timedwait(__libcpp_condvar_t *__cv, __libcpp_mutex_t *__m, __libcpp_timespec_t *__ts) { - using namespace _VSTD::chrono; + using namespace std::chrono; auto duration = seconds(__ts->tv_sec) + nanoseconds(__ts->tv_nsec); auto abstime = diff --git a/libcxx/src/vector.cpp b/libcxx/src/vector.cpp index fa63d5c5e31c..b09db92cf862 100644 --- a/libcxx/src/vector.cpp +++ b/libcxx/src/vector.cpp @@ -22,11 +22,11 @@ struct __vector_base_common { }; void __vector_base_common::__throw_length_error() const { - _VSTD::__throw_length_error("vector"); + std::__throw_length_error("vector"); } void __vector_base_common::__throw_out_of_range() const { - _VSTD::__throw_out_of_range("vector"); + std::__throw_out_of_range("vector"); } #endif // _LIBCPP_ABI_DO_NOT_EXPORT_VECTOR_BASE_COMMON diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.conversion.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.conversion.pass.cpp index 44e11d625897..94d49f13e9b8 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.conversion.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.conversion.pass.cpp @@ -52,7 +52,7 @@ int main(int, char**) { [[maybe_unused]] std::extents e(arg_exts); // but the product is not, so we can't use it for layout_left TEST_LIBCPP_ASSERT_FAILURE( - ([=] { std::layout_left::template mapping> m(arg); }()), + ([=] { std::layout_left::mapping> m(arg); }()), "layout_left::mapping converting ctor: other.required_span_size() must be representable as index_type."); } return 0; diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.ctor.extents.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.ctor.extents.pass.cpp index a225a323d125..e73a167a51be 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.ctor.extents.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.ctor.extents.pass.cpp @@ -32,7 +32,7 @@ int main(int, char**) { { // the extents are representable but the product is not, so we can't use it for layout_left TEST_LIBCPP_ASSERT_FAILURE( - ([=] { std::layout_left::template mapping> m(std::extents(100)); }()), + ([=] { std::layout_left::mapping> m(std::extents(100)); }()), "layout_left::mapping extents ctor: product of extents must be representable as index_type."); } return 0; diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.index_operator.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.index_operator.pass.cpp index 6718c231877b..c514a532a1a0 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.index_operator.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.index_operator.pass.cpp @@ -31,35 +31,35 @@ int main(int, char**) { // value out of range { - std::layout_left::template mapping> m; + std::layout_left::mapping> m; TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_left::mapping: out of bounds indexing"); } { - std::layout_left::template mapping> m; + std::layout_left::mapping> m; TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_left::mapping: out of bounds indexing"); } { - std::layout_left::template mapping> m(std::dextents(5)); + std::layout_left::mapping> m(std::dextents(5)); TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_left::mapping: out of bounds indexing"); } { - std::layout_left::template mapping> m(std::dextents(5)); + std::layout_left::mapping> m(std::dextents(5)); TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_left::mapping: out of bounds indexing"); } { - std::layout_left::template mapping> m(std::dextents(5, 7, 9)); + std::layout_left::mapping> m(std::dextents(5, 7, 9)); TEST_LIBCPP_ASSERT_FAILURE(m(-1, -1, -1), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-1, 0, 0), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(0, -1, 0), "layout_left::mapping: out of bounds indexing"); @@ -70,7 +70,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE(m(5, 7, 9), "layout_left::mapping: out of bounds indexing"); } { - std::layout_left::template mapping> m(std::dextents(5, 7, 9)); + std::layout_left::mapping> m(std::dextents(5, 7, 9)); TEST_LIBCPP_ASSERT_FAILURE(m(-1, -1, -1), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-1, 0, 0), "layout_left::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(0, -1, 0), "layout_left::mapping: out of bounds indexing"); diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.stride.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.stride.pass.cpp index e06ec0c4fc42..96af460d695d 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.stride.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.stride.pass.cpp @@ -33,7 +33,7 @@ int main(int, char**) { // value out of range { - std::layout_left::template mapping> m{std::dextents{100, 100, 100}}; + std::layout_left::mapping> m{std::dextents{100, 100, 100}}; TEST_LIBCPP_ASSERT_FAILURE(m.stride(4), "invalid rank index"); } diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.conversion.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.conversion.pass.cpp index 2d877a50781b..f3ee1a63be36 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.conversion.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.conversion.pass.cpp @@ -52,7 +52,7 @@ int main(int, char**) { [[maybe_unused]] std::extents e(arg_exts); // but the product is not, so we can't use it for layout_right TEST_LIBCPP_ASSERT_FAILURE( - ([=] { std::layout_right::template mapping> m(arg); }()), + ([=] { std::layout_right::mapping> m(arg); }()), "layout_right::mapping converting ctor: other.required_span_size() must be representable as index_type."); } return 0; diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.ctor.extents.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.ctor.extents.pass.cpp index 83fb320edf2c..824c0b0f5793 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.ctor.extents.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.ctor.extents.pass.cpp @@ -31,7 +31,7 @@ int main(int, char**) { { // the extents are representable but the product is not, so we can't use it for layout_right TEST_LIBCPP_ASSERT_FAILURE( - ([=] { std::layout_right::template mapping> m(std::extents(100)); }()), + ([=] { std::layout_right::mapping> m(std::extents(100)); }()), "layout_right::mapping extents ctor: product of extents must be representable as index_type."); } return 0; diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.index_operator.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.index_operator.pass.cpp index fa7eb4a54758..756234f157f2 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.index_operator.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.index_operator.pass.cpp @@ -31,35 +31,35 @@ int main(int, char**) { // value out of range { - std::layout_right::template mapping> m; + std::layout_right::mapping> m; TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_right::mapping: out of bounds indexing"); } { - std::layout_right::template mapping> m; + std::layout_right::mapping> m; TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_right::mapping: out of bounds indexing"); } { - std::layout_right::template mapping> m(std::dextents(5)); + std::layout_right::mapping> m(std::dextents(5)); TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_right::mapping: out of bounds indexing"); } { - std::layout_right::template mapping> m(std::dextents(5)); + std::layout_right::mapping> m(std::dextents(5)); TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_right::mapping: out of bounds indexing"); } { - std::layout_right::template mapping> m(std::dextents(5, 7, 9)); + std::layout_right::mapping> m(std::dextents(5, 7, 9)); TEST_LIBCPP_ASSERT_FAILURE(m(-1, -1, -1), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-1, 0, 0), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(0, -1, 0), "layout_right::mapping: out of bounds indexing"); @@ -70,7 +70,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE(m(5, 7, 9), "layout_right::mapping: out of bounds indexing"); } { - std::layout_right::template mapping> m(std::dextents(5, 7, 9)); + std::layout_right::mapping> m(std::dextents(5, 7, 9)); TEST_LIBCPP_ASSERT_FAILURE(m(-1, -1, -1), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-1, 0, 0), "layout_right::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(0, -1, 0), "layout_right::mapping: out of bounds indexing"); diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.stride.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.stride.pass.cpp index 95179cdc31ac..fe5376b480c0 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.stride.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.stride.pass.cpp @@ -33,7 +33,7 @@ int main(int, char**) { // value out of range { - std::layout_right::template mapping> m{std::dextents{100, 100, 100}}; + std::layout_right::mapping> m{std::dextents{100, 100, 100}}; TEST_LIBCPP_ASSERT_FAILURE(m.stride(4), "invalid rank index"); } diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.conversion.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.conversion.pass.cpp index d696206021e2..c6d3e4fe97f6 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.conversion.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.conversion.pass.cpp @@ -73,9 +73,8 @@ int main(int, char**) { // all strides must be larger than zero { always_convertible_layout::mapping> offset_map(std::dextents{10, 10}, 100, -1); - TEST_LIBCPP_ASSERT_FAILURE( - ([=] { std::layout_stride::template mapping> m(offset_map); }()), - "layout_stride::mapping converting ctor: all strides must be greater than 0"); + TEST_LIBCPP_ASSERT_FAILURE(([=] { std::layout_stride::mapping> m(offset_map); }()), + "layout_stride::mapping converting ctor: all strides must be greater than 0"); } // required_span_size not representable, while individual extents are { @@ -85,7 +84,7 @@ int main(int, char**) { [[maybe_unused]] std::extents e(arg_exts); // but the product is not, so we can't use it for layout_stride TEST_LIBCPP_ASSERT_FAILURE( - ([=] { std::layout_stride::template mapping> m(arg); }()), + ([=] { std::layout_stride::mapping> m(arg); }()), "layout_stride::mapping converting ctor: other.required_span_size() must be representable as index_type."); } // required_span_size not representable, while individual extents are, edge case @@ -99,15 +98,14 @@ int main(int, char**) { [[maybe_unused]] std::extents e(arg_exts); // but the product is not, so we can't use it for layout_stride TEST_LIBCPP_ASSERT_FAILURE( - ([=] { std::layout_stride::template mapping> m(arg); }()), + ([=] { std::layout_stride::mapping> m(arg); }()), "layout_stride::mapping converting ctor: other.required_span_size() must be representable as index_type."); } // base offset must be 0 (i.e. mapping(0,...,0)==0) for a strided layout with positive strides { always_convertible_layout::mapping> offset_map(std::dextents{10, 10}, 3); - TEST_LIBCPP_ASSERT_FAILURE( - ([=] { std::layout_stride::template mapping> m(offset_map); }()), - "layout_stride::mapping converting ctor: base offset of mapping must be zero."); + TEST_LIBCPP_ASSERT_FAILURE(([=] { std::layout_stride::mapping> m(offset_map); }()), + "layout_stride::mapping converting ctor: base offset of mapping must be zero."); } return 0; } diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_array.non_unique.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_array.non_unique.pass.cpp index ba1c81d35d8d..34b333ec3d14 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_array.non_unique.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_array.non_unique.pass.cpp @@ -42,7 +42,7 @@ int main(int, char**) { { TEST_LIBCPP_ASSERT_FAILURE( ([=] { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::extents(20), std::array{4, 1, 200}); }()), "layout_stride::mapping ctor: the provided extents and strides lead to a non-unique mapping"); @@ -50,15 +50,15 @@ int main(int, char**) { // equal strides { // should work because one of the equal strides is associated with an extent of 1 - [[maybe_unused]] std::layout_stride::template mapping> m1( + [[maybe_unused]] std::layout_stride::mapping> m1( std::extents(2), std::array{5, 1, 5}); - [[maybe_unused]] std::layout_stride::template mapping> m2( + [[maybe_unused]] std::layout_stride::mapping> m2( std::extents(1), std::array{5, 1, 5}); // will fail because neither of the equal strides is associated with an extent of 1 TEST_LIBCPP_ASSERT_FAILURE( ([=] { - std::layout_stride::template mapping> m3( + std::layout_stride::mapping> m3( std::extents(2), std::array{5, 1, 5}); }()), "layout_stride::mapping ctor: the provided extents and strides lead to a non-unique mapping"); diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_array.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_array.pass.cpp index c7a7febd0904..eab1c67ed697 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_array.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_array.pass.cpp @@ -41,7 +41,7 @@ int main(int, char**) { // the extents are representable but the product with strides is not, so we can't use it for layout_stride TEST_LIBCPP_ASSERT_FAILURE( ([=] { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::extents(20), std::array{20, 1}); }()), "layout_stride::mapping ctor: required span size is not representable as index_type."); @@ -50,7 +50,7 @@ int main(int, char**) { static_assert(static_cast(257u) == 1); TEST_LIBCPP_ASSERT_FAILURE( ([=] { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::extents(20), std::array{257, 1}); }()), "layout_stride::mapping ctor: required span size is not representable as index_type."); @@ -58,14 +58,14 @@ int main(int, char**) { // negative strides are not allowed, check with unsigned index_type so we make sure we catch that TEST_LIBCPP_ASSERT_FAILURE( ([=] { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::extents(20), std::array{20, -1}); }()), "layout_stride::mapping ctor: all strides must be greater than 0"); // zero strides are not allowed, check with unsigned index_type so we make sure we catch that TEST_LIBCPP_ASSERT_FAILURE( ([=] { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::extents(20), std::array{20, 0}); }()), "layout_stride::mapping ctor: all strides must be greater than 0"); diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_span.non_unique.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_span.non_unique.pass.cpp index b20f65762407..9e1de537682d 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_span.non_unique.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_span.non_unique.pass.cpp @@ -43,7 +43,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE( ([=] { std::array strides{4, 1, 200}; - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::extents(20), std::span(strides)); }()), "layout_stride::mapping ctor: the provided extents and strides lead to a non-unique mapping"); @@ -53,15 +53,15 @@ int main(int, char**) { { // should work because one of the equal strides is associated with an extent of 1 std::array strides{5, 1, 5}; - [[maybe_unused]] std::layout_stride::template mapping> m1( + [[maybe_unused]] std::layout_stride::mapping> m1( std::extents(2), std::span(strides)); - [[maybe_unused]] std::layout_stride::template mapping> m2( + [[maybe_unused]] std::layout_stride::mapping> m2( std::extents(1), std::span(strides)); // will fail because neither of the equal strides is associated with an extent of 1 TEST_LIBCPP_ASSERT_FAILURE( ([=] { - std::layout_stride::template mapping> m3( + std::layout_stride::mapping> m3( std::extents(2), std::span(strides)); }()), "layout_stride::mapping ctor: the provided extents and strides lead to a non-unique mapping"); diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_span.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_span.pass.cpp index c6cd8d9f980a..3b7338449a7f 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_span.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.ctor.extents_span.pass.cpp @@ -44,8 +44,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE( ([=] { std::array strides{20, 1}; - std::layout_stride::template mapping> m( - std::extents(20), std::span(strides)); + std::layout_stride::mapping> m(std::extents(20), std::span(strides)); }()), "layout_stride::mapping ctor: required span size is not representable as index_type."); @@ -54,7 +53,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE( ([=] { std::array strides{257, 1}; - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::extents(20), std::span(strides)); }()), "layout_stride::mapping ctor: required span size is not representable as index_type."); @@ -63,7 +62,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE( ([=] { std::array strides{20, -1}; - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::extents(20), std::span(strides)); }()), "layout_stride::mapping ctor: all strides must be greater than 0"); @@ -71,7 +70,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE( ([=] { std::array strides{20, 0}; - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::extents(20), std::span(strides)); }()), "layout_stride::mapping ctor: all strides must be greater than 0"); diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.index_operator.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.index_operator.pass.cpp index 72e44bd97984..f507b14ca45e 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.index_operator.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.index_operator.pass.cpp @@ -31,21 +31,21 @@ int main(int, char**) { // value out of range { - std::layout_stride::template mapping> m; + std::layout_stride::mapping> m; TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_stride::mapping: out of bounds indexing"); } { - std::layout_stride::template mapping> m; + std::layout_stride::mapping> m; TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(5), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_stride::mapping: out of bounds indexing"); } { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::dextents(5), std::array{1}); TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_stride::mapping: out of bounds indexing"); @@ -53,7 +53,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_stride::mapping: out of bounds indexing"); } { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::dextents(5), std::array{1}); TEST_LIBCPP_ASSERT_FAILURE(m(-1), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-130), "layout_stride::mapping: out of bounds indexing"); @@ -61,7 +61,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE(m(1000), "layout_stride::mapping: out of bounds indexing"); } { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::dextents(5, 7, 9), std::array{1, 10, 100}); TEST_LIBCPP_ASSERT_FAILURE(m(-1, -1, -1), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-1, 0, 0), "layout_stride::mapping: out of bounds indexing"); @@ -73,7 +73,7 @@ int main(int, char**) { TEST_LIBCPP_ASSERT_FAILURE(m(5, 7, 9), "layout_stride::mapping: out of bounds indexing"); } { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::dextents(5, 7, 9), std::array{1, 10, 100}); TEST_LIBCPP_ASSERT_FAILURE(m(-1, -1, -1), "layout_stride::mapping: out of bounds indexing"); TEST_LIBCPP_ASSERT_FAILURE(m(-1, 0, 0), "layout_stride::mapping: out of bounds indexing"); diff --git a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.stride.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.stride.pass.cpp index b88ceb7240c2..b3b69549b2eb 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.stride.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/layout_stride/assert.stride.pass.cpp @@ -27,7 +27,7 @@ int main(int, char**) { // value out of range { - std::layout_stride::template mapping> m( + std::layout_stride::mapping> m( std::dextents(100, 100, 100), std::array{1, 100, 10000}); TEST_LIBCPP_ASSERT_FAILURE(m.stride(4), "invalid rank index"); diff --git a/libcxx/test/libcxx/containers/views/mdspan/mdspan/assert.conversion.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/mdspan/assert.conversion.pass.cpp index 22bceb8e177e..860bf19af45c 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/mdspan/assert.conversion.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/mdspan/assert.conversion.pass.cpp @@ -48,7 +48,7 @@ int main(int, char**) { constexpr size_t D = std::dynamic_extent; std::array data; - typename layout_wrapping_integral<4>::template mapping> src_map( + layout_wrapping_integral<4>::mapping> src_map( std::dextents(5, 2), not_extents_constructible_tag()); std::mdspan, layout_wrapping_integral<4>> arg(data.data(), src_map); diff --git a/libcxx/test/libcxx/containers/views/mdspan/mdspan/assert.size.pass.cpp b/libcxx/test/libcxx/containers/views/mdspan/mdspan/assert.size.pass.cpp index 3ff5a5f4d690..ee3114e228a0 100644 --- a/libcxx/test/libcxx/containers/views/mdspan/mdspan/assert.size.pass.cpp +++ b/libcxx/test/libcxx/containers/views/mdspan/mdspan/assert.size.pass.cpp @@ -29,15 +29,15 @@ int main(int, char**) { std::array data; // make sure we are not failing because of using index_type instead of size_type { - typename layout_wrapping_integral<4>::template mapping> map( - std::dextents(100, 2), not_extents_constructible_tag()); + layout_wrapping_integral<4>::mapping> map( + std::dextents(100, 2), not_extents_constructible_tag()); std::mdspan, layout_wrapping_integral<4>> mds(data.data(), map); assert(map.required_span_size() == char(8)); assert((static_cast(200) == mds.size())); } { - typename layout_wrapping_integral<4>::template mapping> map( - std::dextents(100, 3), not_extents_constructible_tag()); + layout_wrapping_integral<4>::mapping> map( + std::dextents(100, 3), not_extents_constructible_tag()); std::mdspan, layout_wrapping_integral<4>> mds(data.data(), map); // sanity check assert(map.required_span_size() == char(12)); diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/move.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/move.pass.cpp index ce5cf0560fc8..b1ad6873bc5e 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/move.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/move.pass.cpp @@ -94,7 +94,7 @@ struct Test1OutIters { TEST_CONSTEXPR_CXX20 bool test() { types::for_each(types::cpp17_input_iterator_list(), TestOutIters()); - if (TEST_STD_VER >= 23 || !TEST_IS_CONSTANT_EVALUATED) + if (TEST_STD_AT_LEAST_23_OR_RUNTIME_EVALUATED) types::for_each(types::cpp17_input_iterator_list*>(), Test1OutIters()); { // Make sure that padding bits aren't copied diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/move_backward.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/move_backward.pass.cpp index 2ed4d37b9dbe..61dea47b5107 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/move_backward.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.move/move_backward.pass.cpp @@ -92,7 +92,7 @@ struct Test1OutIters { TEST_CONSTEXPR_CXX20 bool test() { types::for_each(types::bidirectional_iterator_list(), TestOutIters()); - if (TEST_STD_VER >= 23 || !TEST_IS_CONSTANT_EVALUATED) + if (TEST_STD_AT_LEAST_23_OR_RUNTIME_EVALUATED) types::for_each(types::bidirectional_iterator_list*>(), Test1OutIters()); { // Make sure that padding bits aren't copied diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace.pass.cpp index 751d6b74b012..833d5b0f6b2b 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace.pass.cpp @@ -29,35 +29,35 @@ struct Test { void operator()(ExecutionPolicy&& policy) { { // simple test std::array a = {1, 2, 3, 4, 5, 6, 7, 8}; - std::replace(policy, Iter(std::begin(a)), Iter(std::end(a)), 3, 6); + std::replace(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), 3, 6); assert((a == std::array{1, 2, 6, 4, 5, 6, 7, 8})); } { // empty range works std::array a = {}; - std::replace(policy, Iter(std::begin(a)), Iter(std::end(a)), 3, 6); + std::replace(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), 3, 6); } { // non-empty range without a match works std::array a = {1, 2}; - std::replace(policy, Iter(std::begin(a)), Iter(std::end(a)), 3, 6); + std::replace(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), 3, 6); } { // single element range works std::array a = {3}; - std::replace(policy, Iter(std::begin(a)), Iter(std::end(a)), 3, 6); + std::replace(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), 3, 6); assert((a == std::array{6})); } { // two element range works std::array a = {3, 4}; - std::replace(policy, Iter(std::begin(a)), Iter(std::end(a)), 3, 6); + std::replace(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), 3, 6); assert((a == std::array{6, 4})); } { // multiple matching elements work std::array a = {1, 2, 3, 4, 3, 3, 5, 6, 3}; - std::replace(policy, Iter(std::begin(a)), Iter(std::end(a)), 3, 9); + std::replace(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), 3, 9); assert((a == std::array{1, 2, 9, 4, 9, 9, 5, 6, 9})); } diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_copy.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_copy.pass.cpp index f24bedabebcc..18d4446f5d2a 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_copy.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_copy.pass.cpp @@ -32,40 +32,40 @@ struct Test { { // simple test std::array a = {1, 2, 3, 4, 5, 6, 7, 8}; std::array out; - std::replace_copy(policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(out)), 3, 6); + std::replace_copy(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), Iter(std::data(out)), 3, 6); assert((out == std::array{1, 2, 6, 4, 5, 6, 7, 8})); } { // empty range works std::array a = {}; - std::replace_copy(policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(a)), 3, 6); + std::replace_copy(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), Iter(std::data(a)), 3, 6); } { // non-empty range without a match works std::array a = {1, 2}; std::array out; - std::replace_copy(policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(out.data()), 3, 6); + std::replace_copy(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), Iter(out.data()), 3, 6); assert((out == std::array{1, 2})); } { // single element range works std::array a = {3}; std::array out; - std::replace_copy(policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(out)), 3, 6); + std::replace_copy(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), Iter(std::data(out)), 3, 6); assert((out == std::array{6})); } { // two element range works std::array a = {3, 4}; std::array out; - std::replace_copy(policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(out)), 3, 6); + std::replace_copy(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), Iter(std::data(out)), 3, 6); assert((out == std::array{6, 4})); } { // multiple matching elements work std::array a = {1, 2, 3, 4, 3, 3, 5, 6, 3}; std::array out; - std::replace_copy(policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(out)), 3, 9); + std::replace_copy(policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), Iter(std::data(out)), 3, 9); assert((out == std::array{1, 2, 9, 4, 9, 9, 5, 6, 9})); } diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_copy_if.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_copy_if.pass.cpp index f7c746f382d1..00b40a4e159a 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_copy_if.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_copy_if.pass.cpp @@ -34,21 +34,36 @@ struct Test { std::array a = {1, 2, 3, 4, 5, 6, 7, 8}; std::array out; std::replace_copy_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(out)), [](int i) { return i == 3; }, 6); + policy, + Iter(std::data(a)), + Iter(std::data(a) + std::size(a)), + Iter(std::data(out)), + [](int i) { return i == 3; }, + 6); assert((out == std::array{1, 2, 6, 4, 5, 6, 7, 8})); } { // empty range works std::array a = {}; std::replace_copy_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(a)), [](int i) { return i == 3; }, 6); + policy, + Iter(std::data(a)), + Iter(std::data(a) + std::size(a)), + Iter(std::data(a)), + [](int i) { return i == 3; }, + 6); } { // non-empty range without a match works std::array a = {1, 2}; std::array out; std::replace_copy_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(out.data()), [](int i) { return i == 3; }, 6); + policy, + Iter(std::data(a)), + Iter(std::data(a) + std::size(a)), + Iter(out.data()), + [](int i) { return i == 3; }, + 6); assert((out == std::array{1, 2})); } @@ -56,7 +71,12 @@ struct Test { std::array a = {3}; std::array out; std::replace_copy_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(out)), [](int i) { return i == 3; }, 6); + policy, + Iter(std::data(a)), + Iter(std::data(a) + std::size(a)), + Iter(std::data(out)), + [](int i) { return i == 3; }, + 6); assert((out == std::array{6})); } @@ -64,7 +84,12 @@ struct Test { std::array a = {3, 4}; std::array out; std::replace_copy_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(out)), [](int i) { return i == 3; }, 6); + policy, + Iter(std::data(a)), + Iter(std::data(a) + std::size(a)), + Iter(std::data(out)), + [](int i) { return i == 3; }, + 6); assert((out == std::array{6, 4})); } @@ -72,7 +97,12 @@ struct Test { std::array a = {1, 2, 3, 4, 3, 3, 5, 6, 3}; std::array out; std::replace_copy_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), Iter(std::begin(out)), [](int i) { return i == 3; }, 9); + policy, + Iter(std::data(a)), + Iter(std::data(a) + std::size(a)), + Iter(std::data(out)), + [](int i) { return i == 3; }, + 9); assert((out == std::array{1, 2, 9, 4, 9, 9, 5, 6, 9})); } diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_if.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_if.pass.cpp index 3ffc1c021bb9..9e4f4d3f0345 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_if.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.replace_if.pass.cpp @@ -30,38 +30,40 @@ struct Test { { // simple test std::array a = {1, 2, 3, 4, 5, 6, 7, 8}; std::replace_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), [](int i) { return i == 3 || i == 7; }, 6); + policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), [](int i) { return i == 3 || i == 7; }, 6); assert((a == std::array{1, 2, 6, 4, 5, 6, 6, 8})); } { // empty range works std::array a = {}; std::replace_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), [](int) { return false; }, 6); + policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), [](int) { return false; }, 6); } { // non-empty range without a match works std::array a = {1, 2}; - std::replace_if(policy, Iter(std::begin(a)), Iter(std::end(a)), [](int) { return false; }, 6); + std::replace_if( + policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), [](int) { return false; }, 6); } { // single element range works std::array a = {3}; std::replace_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), [](int i) { return i == 3; }, 6); + policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), [](int i) { return i == 3; }, 6); assert((a == std::array{6})); } { // two element range works std::array a = {3, 4}; std::replace_if( - policy, Iter(std::begin(a)), Iter(std::end(a)), [](int i) { return i == 3; }, 6); + policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), [](int i) { return i == 3; }, 6); assert((a == std::array{6, 4})); } { // multiple matching elements work std::array a = {1, 2, 3, 4, 3, 3, 5, 6, 3}; - std::replace_if(policy, Iter(std::begin(a)), Iter(std::end(a)), [](int i) { return i == 3; }, 9); + std::replace_if( + policy, Iter(std::data(a)), Iter(std::data(a) + std::size(a)), [](int i) { return i == 3; }, 9); assert((a == std::array{1, 2, 9, 4, 9, 9, 5, 6, 9})); } diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/ranges.rotate_copy.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/ranges.rotate_copy.pass.cpp index 1f18d787c2f4..58b0f75d9b5f 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/ranges.rotate_copy.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/ranges.rotate_copy.pass.cpp @@ -34,16 +34,16 @@ template concept HasRotateCopyR = requires(Range range, Out out) { std::ranges::rotate_copy(range, nullptr, out); }; static_assert(HasRotateCopyIt); -static_assert(!HasRotateCopyIt); -static_assert(!HasRotateCopyIt); +static_assert(!HasRotateCopyIt); +static_assert(!HasRotateCopyIt); static_assert(!HasRotateCopyIt); static_assert(!HasRotateCopyIt); static_assert(!HasRotateCopyIt); static_assert(!HasRotateCopyIt); static_assert(HasRotateCopyR>); -static_assert(!HasRotateCopyR); -static_assert(!HasRotateCopyR); +static_assert(!HasRotateCopyR); +static_assert(!HasRotateCopyR); static_assert(!HasRotateCopyR>); static_assert(!HasRotateCopyR, OutputIteratorNotIndirectlyWritable>); static_assert(!HasRotateCopyR, OutputIteratorNotInputOrOutputIterator>); @@ -112,6 +112,7 @@ constexpr void test_out_iterators() { } constexpr bool test() { + test_out_iterators>(); test_out_iterators>(); test_out_iterators>(); test_out_iterators>(); diff --git a/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp b/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp index cc832febdba7..904100c1cf0b 100644 --- a/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp +++ b/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp @@ -38,7 +38,7 @@ struct Test { TEST_CONSTEXPR_CXX20 bool test() { types::for_each(types::cpp17_input_iterator_list(), Test()); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { std::vector vec(256 + 64); for (ptrdiff_t i = 0; i != 256; ++i) { for (size_t offset = 0; offset != 64; ++offset) { diff --git a/libcxx/test/std/algorithms/alg.sorting/alg.merge/pstl.merge.pass.cpp b/libcxx/test/std/algorithms/alg.sorting/alg.merge/pstl.merge.pass.cpp index 1feadfb377a6..ade15ce0b708 100644 --- a/libcxx/test/std/algorithms/alg.sorting/alg.merge/pstl.merge.pass.cpp +++ b/libcxx/test/std/algorithms/alg.sorting/alg.merge/pstl.merge.pass.cpp @@ -53,15 +53,23 @@ struct Test { std::array a; std::array b; std::array out; - std::merge( - policy, Iter1(std::begin(a)), Iter1(std::end(a)), Iter2(std::begin(b)), Iter2(std::end(b)), std::begin(out)); + std::merge(policy, + Iter1(std::data(a)), + Iter1(std::data(a) + std::size(a)), + Iter2(std::data(b)), + Iter2(std::data(b) + std::size(b)), + std::begin(out)); } { // check that it works with the first range being empty std::array a; int b[] = {2, 4, 6, 8, 10}; std::array out; - std::merge( - policy, Iter1(std::begin(a)), Iter1(std::end(a)), Iter2(std::begin(b)), Iter2(std::end(b)), std::begin(out)); + std::merge(policy, + Iter1(std::data(a)), + Iter1(std::data(a) + std::size(a)), + Iter2(std::begin(b)), + Iter2(std::end(b)), + std::begin(out)); assert((out == std::array{2, 4, 6, 8, 10})); } @@ -69,8 +77,12 @@ struct Test { int a[] = {2, 4, 6, 8, 10}; std::array b; std::array out; - std::merge( - policy, Iter1(std::begin(a)), Iter1(std::end(a)), Iter2(std::begin(b)), Iter2(std::end(b)), std::begin(out)); + std::merge(policy, + Iter1(std::begin(a)), + Iter1(std::end(a)), + Iter2(std::data(b)), + Iter2(std::data(b) + std::size(b)), + std::begin(out)); assert((out == std::array{2, 4, 6, 8, 10})); } diff --git a/libcxx/test/std/algorithms/alg.sorting/alg.three.way/lexicographical_compare_three_way.pass.cpp b/libcxx/test/std/algorithms/alg.sorting/alg.three.way/lexicographical_compare_three_way.pass.cpp index 0bd1d7452953..d7cd49987689 100644 --- a/libcxx/test/std/algorithms/alg.sorting/alg.three.way/lexicographical_compare_three_way.pass.cpp +++ b/libcxx/test/std/algorithms/alg.sorting/alg.three.way/lexicographical_compare_three_way.pass.cpp @@ -27,8 +27,8 @@ template constexpr void test_lexicographical_compare(C1 a, C2 b, Order expected) { - std::same_as decltype(auto) result = - std::lexicographical_compare_three_way(Iter1{a.begin()}, Iter1{a.end()}, Iter2{b.begin()}, Iter2{b.end()}); + std::same_as decltype(auto) result = std::lexicographical_compare_three_way( + Iter1{a.data()}, Iter1{a.data() + a.size()}, Iter2{b.data()}, Iter2{b.data() + b.size()}); assert(expected == result); } diff --git a/libcxx/test/std/algorithms/alg.sorting/alg.three.way/lexicographical_compare_three_way_comp.pass.cpp b/libcxx/test/std/algorithms/alg.sorting/alg.three.way/lexicographical_compare_three_way_comp.pass.cpp index d3c2814d642a..f2f7d538d773 100644 --- a/libcxx/test/std/algorithms/alg.sorting/alg.three.way/lexicographical_compare_three_way_comp.pass.cpp +++ b/libcxx/test/std/algorithms/alg.sorting/alg.three.way/lexicographical_compare_three_way_comp.pass.cpp @@ -56,8 +56,8 @@ static_assert(has_lexicographical_compare); template constexpr void test_lexicographical_compare(C1 a, C2 b, Comparator comp, Order expected) { - std::same_as decltype(auto) result = - std::lexicographical_compare_three_way(Iter1{a.begin()}, Iter1{a.end()}, Iter2{b.begin()}, Iter2{b.end()}, comp); + std::same_as decltype(auto) result = std::lexicographical_compare_three_way( + Iter1{a.data()}, Iter1{a.data() + a.size()}, Iter2{b.data()}, Iter2{b.data() + b.size()}, comp); assert(expected == result); } diff --git a/libcxx/test/std/containers/from_range_helpers.h b/libcxx/test/std/containers/from_range_helpers.h index 7fff99da1e15..e17ea247618b 100644 --- a/libcxx/test/std/containers/from_range_helpers.h +++ b/libcxx/test/std/containers/from_range_helpers.h @@ -9,9 +9,11 @@ #ifndef SUPPORT_FROM_RANGE_HELPERS_H #define SUPPORT_FROM_RANGE_HELPERS_H +#include #include #include #include +#include #include "min_allocator.h" #include "test_allocator.h" @@ -34,6 +36,13 @@ constexpr auto wrap_input(Range&& input) { return std::ranges::subrange(std::move(b), std::move(e)); } +template +constexpr auto wrap_input(std::array& input) { + auto b = Iter(input.data()); + auto e = Sent(Iter(input.data() + input.size())); + return std::ranges::subrange(std::move(b), std::move(e)); +} + template constexpr auto wrap_input(std::vector& input) { auto b = Iter(input.data()); diff --git a/libcxx/test/std/containers/views/mdspan/ConvertibleToIntegral.h b/libcxx/test/std/containers/views/mdspan/ConvertibleToIntegral.h index 470f5d8e7246..0ca5c330a390 100644 --- a/libcxx/test/std/containers/views/mdspan/ConvertibleToIntegral.h +++ b/libcxx/test/std/containers/views/mdspan/ConvertibleToIntegral.h @@ -16,8 +16,8 @@ struct IntType { constexpr bool operator==(const IntType& rhs) const { return val == rhs.val; } constexpr operator int() const noexcept { return val; } - constexpr operator unsigned char() const { return val; } - constexpr operator signed char() const noexcept { return val; } + constexpr operator unsigned char() const { return static_cast(val); } + constexpr operator signed char() const noexcept { return static_cast(val); } }; // only non-const convertible @@ -28,8 +28,8 @@ struct IntTypeNC { constexpr bool operator==(const IntType& rhs) const { return val == rhs.val; } constexpr operator int() noexcept { return val; } - constexpr operator unsigned() { return val; } - constexpr operator char() noexcept { return val; } + constexpr operator unsigned() { return static_cast(val); } + constexpr operator char() noexcept { return static_cast(val); } }; // weird configurability of convertibility to int diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_right.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_right.pass.cpp index 7e686cd9688f..1b5a985c1eb3 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_right.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_right.pass.cpp @@ -64,9 +64,9 @@ constexpr void test_conversion() { } template -using lr_mapping_t = typename std::layout_right::template mapping>; +using lr_mapping_t = std::layout_right::mapping>; template -using ll_mapping_t = typename std::layout_left::template mapping>; +using ll_mapping_t = std::layout_left::mapping>; constexpr void test_no_implicit_conversion() { constexpr size_t D = std::dynamic_extent; diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_stride.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_stride.pass.cpp index e85270ad023d..40ecef865477 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_stride.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_stride.pass.cpp @@ -76,9 +76,9 @@ constexpr void test_conversion() { } template -using ll_mapping_t = typename std::layout_left::template mapping>; +using ll_mapping_t = std::layout_left::mapping>; template -using ls_mapping_t = typename std::layout_stride::template mapping>; +using ls_mapping_t = std::layout_stride::mapping>; constexpr void test_rank_mismatch() { constexpr size_t D = std::dynamic_extent; diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.mapping.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.mapping.pass.cpp index 40666ae960f4..ecfbd3fef705 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.mapping.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.mapping.pass.cpp @@ -71,7 +71,7 @@ constexpr void test_conversion() { } template -using mapping_t = typename std::layout_left::template mapping>; +using mapping_t = std::layout_left::mapping>; constexpr void test_no_implicit_conversion() { constexpr size_t D = std::dynamic_extent; diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/properties.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/properties.pass.cpp index cbf1b5c29076..e4ab972cb109 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/properties.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/properties.pass.cpp @@ -35,7 +35,7 @@ template constexpr void test_layout_mapping_left() { - using M = std::layout_left::template mapping; + using M = std::layout_left::mapping; assert(M::is_unique() == true); assert(M::is_exhaustive() == true); assert(M::is_strided() == true); diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_left.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_left.pass.cpp index 5ab8d05926c6..13f2354c6140 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_left.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_left.pass.cpp @@ -64,9 +64,9 @@ constexpr void test_conversion() { } template -using lr_mapping_t = typename std::layout_right::template mapping>; +using lr_mapping_t = std::layout_right::mapping>; template -using ll_mapping_t = typename std::layout_left::template mapping>; +using ll_mapping_t = std::layout_left::mapping>; constexpr void test_no_implicit_conversion() { constexpr size_t D = std::dynamic_extent; diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_stride.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_stride.pass.cpp index 9d9677d54011..3b7e793c69a1 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_stride.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_stride.pass.cpp @@ -76,9 +76,9 @@ constexpr void test_conversion() { } template -using lr_mapping_t = typename std::layout_right::template mapping>; +using lr_mapping_t = std::layout_right::mapping>; template -using ls_mapping_t = typename std::layout_stride::template mapping>; +using ls_mapping_t = std::layout_stride::mapping>; constexpr void test_rank_mismatch() { constexpr size_t D = std::dynamic_extent; diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.mapping.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.mapping.pass.cpp index 1f2461a53902..dd71f3b2af5f 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.mapping.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.mapping.pass.cpp @@ -71,7 +71,7 @@ constexpr void test_conversion() { } template -using mapping_t = typename std::layout_right::template mapping>; +using mapping_t = std::layout_right::mapping>; constexpr void test_no_implicit_conversion() { constexpr size_t D = std::dynamic_extent; diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/properties.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/properties.pass.cpp index e10e073c8fb1..94ffb1a4db5b 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/properties.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/properties.pass.cpp @@ -35,7 +35,7 @@ template constexpr void test_layout_mapping_right() { - using M = std::layout_right::template mapping; + using M = std::layout_right::mapping; assert(M::is_unique() == true); assert(M::is_exhaustive() == true); assert(M::is_strided() == true); diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/comparison.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/comparison.pass.cpp index e624e49df5a6..7b452cc43f97 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/comparison.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/comparison.pass.cpp @@ -142,7 +142,7 @@ constexpr void test_comparison_same_rank() { template constexpr void test_comparison_with( bool expect_equal, E1 e1, std::array strides, E2 e2, OtherArgs... other_args) { - typename std::layout_stride::template mapping map(e1, strides); + std::layout_stride::mapping map(e1, strides); typename OtherLayout::template mapping other_map(e2, other_args...); assert((map == other_map) == expect_equal); diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.strided_mapping.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.strided_mapping.pass.cpp index 7c9b3f34a41f..2f73ed512fe4 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.strided_mapping.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.strided_mapping.pass.cpp @@ -106,7 +106,7 @@ constexpr void test_conversion() { } template -using ToM = typename std::layout_stride::template mapping>; +using ToM = std::layout_stride::mapping>; template using FromM = typename FromL::template mapping>; diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/deduction.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/deduction.pass.cpp index ebe31d9d0ece..0e0a079b598b 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/deduction.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/deduction.pass.cpp @@ -27,24 +27,24 @@ constexpr bool test() { constexpr size_t D = std::dynamic_extent; ASSERT_SAME_TYPE(decltype(std::layout_stride::mapping(std::extents(), std::array())), - std::layout_stride::template mapping>); + std::layout_stride::mapping>); ASSERT_SAME_TYPE(decltype(std::layout_stride::mapping(std::extents(), std::array{1})), - std::layout_stride::template mapping>); + std::layout_stride::mapping>); ASSERT_SAME_TYPE(decltype(std::layout_stride::mapping(std::extents(), std::array{1})), - std::layout_stride::template mapping>); + std::layout_stride::mapping>); ASSERT_SAME_TYPE( decltype(std::layout_stride::mapping(std::extents(), std::array{3, 100})), - std::layout_stride::template mapping>); + std::layout_stride::mapping>); ASSERT_SAME_TYPE(decltype(std::layout_stride::mapping(std::extents(), std::span())), - std::layout_stride::template mapping>); + std::layout_stride::mapping>); ASSERT_SAME_TYPE(decltype(std::layout_stride::mapping(std::extents(), std::declval>())), - std::layout_stride::template mapping>); + std::layout_stride::mapping>); ASSERT_SAME_TYPE(decltype(std::layout_stride::mapping(std::extents(), std::declval>())), - std::layout_stride::template mapping>); + std::layout_stride::mapping>); ASSERT_SAME_TYPE( decltype(std::layout_stride::mapping(std::extents(), std::declval>())), - std::layout_stride::template mapping>); + std::layout_stride::mapping>); return true; } diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/is_exhaustive_corner_case.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/is_exhaustive_corner_case.pass.cpp index d13db91ac5a1..a4218f34105a 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/is_exhaustive_corner_case.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/is_exhaustive_corner_case.pass.cpp @@ -29,7 +29,7 @@ template constexpr void test_layout_mapping_stride(E ext, std::array strides, bool exhaustive) { - using M = std::layout_stride::template mapping; + using M = std::layout_stride::mapping; M m(ext, strides); assert(m.is_exhaustive() == exhaustive); } diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/properties.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/properties.pass.cpp index 8dba35cd9d33..a5f77a668547 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/properties.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/properties.pass.cpp @@ -48,7 +48,7 @@ template constexpr void test_layout_mapping_stride(E ext, std::array strides, bool exhaustive) { - using M = std::layout_stride::template mapping; + using M = std::layout_stride::mapping; M m(ext, strides); const M c_m = m; assert(m.strides() == strides); diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/assign.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/assign.pass.cpp index b282277d0dc0..9e128f518078 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/assign.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/assign.pass.cpp @@ -67,14 +67,13 @@ constexpr void mixin_extents(const H& handle, const L& layout, const A& acc) { template constexpr void mixin_layout(const H& handle, const A& acc) { // make sure we test a trivially assignable mapping - static_assert(std::is_trivially_assignable_v>, - const typename std::layout_left::template mapping>&>); + static_assert(std::is_trivially_assignable_v>, + const std::layout_left::mapping>&>); mixin_extents(handle, std::layout_left(), acc); mixin_extents(handle, std::layout_right(), acc); // make sure we test a not trivially assignable mapping - static_assert(!std::is_trivially_assignable_v< - typename layout_wrapping_integral<4>::template mapping>, - const typename layout_wrapping_integral<4>::template mapping>&>); + static_assert(!std::is_trivially_assignable_v< layout_wrapping_integral<4>::mapping>, + const layout_wrapping_integral<4>::mapping>&>); mixin_extents(handle, layout_wrapping_integral<4>(), acc); } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.copy.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.copy.pass.cpp index 75f2fc3dd603..6d88e9ff02f9 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.copy.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.copy.pass.cpp @@ -57,12 +57,11 @@ constexpr void mixin_extents(const H& handle, const L& layout, const A& acc) { template constexpr void mixin_layout(const H& handle, const A& acc) { // make sure we test a trivially copyable mapping - static_assert(std::is_trivially_copyable_v>>); + static_assert(std::is_trivially_copyable_v>>); mixin_extents(handle, std::layout_left(), acc); mixin_extents(handle, std::layout_right(), acc); // make sure we test a not trivially copyable mapping - static_assert( - !std::is_trivially_copyable_v::template mapping>>); + static_assert(!std::is_trivially_copyable_v::mapping>>); mixin_extents(handle, layout_wrapping_integral<4>(), acc); } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.default.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.default.pass.cpp index 5c0ae126dff2..dbb2ad8b41bd 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.default.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.default.pass.cpp @@ -74,8 +74,7 @@ constexpr void mixin_layout(const H& handle, const A& acc) { // Use weird layout, make sure it has the properties we want to test constexpr size_t D = std::dynamic_extent; - static_assert(!std::is_default_constructible_v< - typename layout_wrapping_integral<4>::template mapping>>); + static_assert(!std::is_default_constructible_v< layout_wrapping_integral<4>::mapping>>); mixin_extents(handle, layout_wrapping_integral<4>(), acc); } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_array.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_array.pass.cpp index 2e5c842b50d4..bbf8137a7cb8 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_array.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_array.pass.cpp @@ -119,16 +119,14 @@ constexpr void mixin_layout(const H& handle, const A& acc) { mixin_extents(handle, std::layout_right(), acc); // Sanity check that this layouts mapping is constructible from extents (via its move constructor) - static_assert(std::is_constructible_v::template mapping>, - std::extents>); - static_assert(!std::is_constructible_v::template mapping>, - const std::extents&>); + static_assert(std::is_constructible_v::mapping>, std::extents>); + static_assert( + !std::is_constructible_v::mapping>, const std::extents&>); mixin_extents(handle, layout_wrapping_integral<8>(), acc); // Sanity check that this layouts mapping is not constructible from extents - static_assert(!std::is_constructible_v::template mapping>, - std::extents>); - static_assert(!std::is_constructible_v::template mapping>, - const std::extents&>); + static_assert(!std::is_constructible_v::mapping>, std::extents>); + static_assert( + !std::is_constructible_v::mapping>, const std::extents&>); mixin_extents(handle, layout_wrapping_integral<4>(), acc); } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_extents.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_extents.pass.cpp index 007ab9cdc636..0a8918028d13 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_extents.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_extents.pass.cpp @@ -83,16 +83,14 @@ constexpr void mixin_layout(const H& handle, const A& acc) { // Use weird layout, make sure it has the properties we want to test // Sanity check that this layouts mapping is constructible from extents (via its move constructor) - static_assert(std::is_constructible_v::template mapping>, - std::extents>); - static_assert(!std::is_constructible_v::template mapping>, - const std::extents&>); + static_assert(std::is_constructible_v::mapping>, std::extents>); + static_assert( + !std::is_constructible_v::mapping>, const std::extents&>); mixin_extents(handle, layout_wrapping_integral<8>(), acc); // Sanity check that this layouts mapping is not constructible from extents - static_assert(!std::is_constructible_v::template mapping>, - std::extents>); - static_assert(!std::is_constructible_v::template mapping>, - const std::extents&>); + static_assert(!std::is_constructible_v::mapping>, std::extents>); + static_assert( + !std::is_constructible_v::mapping>, const std::extents&>); mixin_extents(handle, layout_wrapping_integral<4>(), acc); } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_integers.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_integers.pass.cpp index 985a8911e15b..c2e8d26cd87f 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_integers.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_integers.pass.cpp @@ -106,16 +106,14 @@ constexpr void mixin_layout(const H& handle, const A& acc) { // Use weird layout, make sure it has the properties we want to test // Sanity check that this layouts mapping is constructible from extents (via its move constructor) - static_assert(std::is_constructible_v::template mapping>, - std::extents>); - static_assert(!std::is_constructible_v::template mapping>, - const std::extents&>); + static_assert(std::is_constructible_v::mapping>, std::extents>); + static_assert( + !std::is_constructible_v::mapping>, const std::extents&>); mixin_extents(handle, layout_wrapping_integral<8>(), acc); // Sanity check that this layouts mapping is not constructible from extents - static_assert(!std::is_constructible_v::template mapping>, - std::extents>); - static_assert(!std::is_constructible_v::template mapping>, - const std::extents&>); + static_assert(!std::is_constructible_v::mapping>, std::extents>); + static_assert( + !std::is_constructible_v::mapping>, const std::extents&>); mixin_extents(handle, layout_wrapping_integral<4>(), acc); } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map.pass.cpp index 4c636255c1c7..75b7722b445e 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map.pass.cpp @@ -93,7 +93,7 @@ constexpr void mixin_accessor() { } template -using mapping_t = typename std::layout_right::template mapping; +using mapping_t = std::layout_right::mapping; constexpr bool test() { mixin_accessor(); diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map_acc.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map_acc.pass.cpp index 76ca7810963d..c2210f1dba90 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map_acc.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_map_acc.pass.cpp @@ -87,7 +87,7 @@ constexpr void mixin_accessor() { } template -using mapping_t = typename std::layout_right::template mapping; +using mapping_t = std::layout_right::mapping; constexpr bool test() { mixin_accessor(); diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_span.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_span.pass.cpp index ad4da40630c9..980619795b5d 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_span.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.dh_span.pass.cpp @@ -119,16 +119,14 @@ constexpr void mixin_layout(const H& handle, const A& acc) { mixin_extents(handle, std::layout_right(), acc); // Sanity check that this layouts mapping is constructible from extents (via its move constructor) - static_assert(std::is_constructible_v::template mapping>, - std::extents>); - static_assert(!std::is_constructible_v::template mapping>, - const std::extents&>); + static_assert(std::is_constructible_v::mapping>, std::extents>); + static_assert( + !std::is_constructible_v::mapping>, const std::extents&>); mixin_extents(handle, layout_wrapping_integral<8>(), acc); // Sanity check that this layouts mapping is not constructible from extents - static_assert(!std::is_constructible_v::template mapping>, - std::extents>); - static_assert(!std::is_constructible_v::template mapping>, - const std::extents&>); + static_assert(!std::is_constructible_v::mapping>, std::extents>); + static_assert( + !std::is_constructible_v::mapping>, const std::extents&>); mixin_extents(handle, layout_wrapping_integral<4>(), acc); } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.move.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.move.pass.cpp index a65d0f448417..c843c6033524 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/ctor.move.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/ctor.move.pass.cpp @@ -56,12 +56,11 @@ constexpr void mixin_extents(const H& handle, const L& layout, const A& acc) { template constexpr void mixin_layout(const H& handle, const A& acc) { // make sure we test a trivially copyable mapping - static_assert(std::is_trivially_move_constructible_v>>); + static_assert(std::is_trivially_move_constructible_v>>); mixin_extents(handle, std::layout_left(), acc); mixin_extents(handle, std::layout_right(), acc); // make sure we test a not trivially copyable mapping - static_assert(!std::is_trivially_move_constructible_v< - typename layout_wrapping_integral<4>::template mapping>>); + static_assert(!std::is_trivially_move_constructible_v< layout_wrapping_integral<4>::mapping>>); mixin_extents(handle, layout_wrapping_integral<4>(), acc); } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/mapping.verify.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/mapping.verify.cpp index 4121fd6ad468..5270b503fe9f 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/mapping.verify.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/mapping.verify.cpp @@ -19,5 +19,5 @@ void not_layout_policy() { // expected-error-re@*:* {{static assertion failed {{.*}}mdspan: LayoutPolicy template parameter is invalid. A common mistake is to pass a layout mapping instead of a layout policy}} - [[maybe_unused]] std::mdspan, std::layout_left::template mapping>> m; + [[maybe_unused]] std::mdspan, std::layout_left::mapping>> m; } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/move.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/move.pass.cpp index 1c5f404d49fb..9e1805431cd7 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/move.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/move.pass.cpp @@ -59,12 +59,11 @@ constexpr void mixin_extents(const H& handle, const L& layout, const A& acc) { template constexpr void mixin_layout(const H& handle, const A& acc) { // make sure we test a trivially copyable mapping - static_assert(std::is_trivially_move_assignable_v>>); + static_assert(std::is_trivially_move_assignable_v>>); mixin_extents(handle, std::layout_left(), acc); mixin_extents(handle, std::layout_right(), acc); // make sure we test a not trivially copyable mapping - static_assert( - !std::is_trivially_move_assignable_v::template mapping>>); + static_assert(!std::is_trivially_move_assignable_v::mapping>>); mixin_extents(handle, layout_wrapping_integral<4>(), acc); } diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/swap.pass.cpp b/libcxx/test/std/containers/views/mdspan/mdspan/swap.pass.cpp index 983a789cb310..a9a8e9a264c1 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/swap.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/mdspan/swap.pass.cpp @@ -60,7 +60,7 @@ constexpr bool test() { test_swap(a, b); } { - layout_wrapping_integral<4>::template mapping map_a(extents_t(12), not_extents_constructible_tag()), + layout_wrapping_integral<4>::mapping map_a(extents_t(12), not_extents_constructible_tag()), map_b(extents_t(5), not_extents_constructible_tag()); std::mdspan a(data_a, map_a); std::mdspan b(data_b, map_b); diff --git a/libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.pass.cpp b/libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.pass.cpp index 4e1db3df5b83..73b13ccc34cf 100644 --- a/libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.pass.cpp +++ b/libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.pass.cpp @@ -71,7 +71,7 @@ public: typedef typename std::iterator_traits::difference_type difference_type; typedef It pointer; typedef typename std::iterator_traits::reference reference; - typedef typename std::remove_pointer::type element_type; + typedef std::remove_reference_t element_type; throw_operator_minus() : it_() {} explicit throw_operator_minus(It it) : it_(it) {} diff --git a/libcxx/test/std/diagnostics/syserr/syserr.errcat/syserr.errcat.objects/generic_category.pass.cpp b/libcxx/test/std/diagnostics/syserr/syserr.errcat/syserr.errcat.objects/generic_category.pass.cpp index 3f49c36f8ba2..068202c6e415 100644 --- a/libcxx/test/std/diagnostics/syserr/syserr.errcat/syserr.errcat.objects/generic_category.pass.cpp +++ b/libcxx/test/std/diagnostics/syserr/syserr.errcat/syserr.errcat.objects/generic_category.pass.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// // XFAIL: stdlib=apple-libc++ && target={{.+}}-apple-macosx10.{{9|10|11|12}} -// XFAIL: LIBCXX-PICOLIBC-FIXME // @@ -48,6 +47,8 @@ int main(int, char**) // Exact message format varies by platform. #if defined(_AIX) LIBCPP_ASSERT(msg.rfind("Error -1 occurred", 0) == 0); +#elif defined(_NEWLIB_VERSION) + LIBCPP_ASSERT(msg.empty()); #else LIBCPP_ASSERT(msg.rfind("Unknown error", 0) == 0); #endif diff --git a/libcxx/test/std/diagnostics/syserr/syserr.errcat/syserr.errcat.objects/system_category.pass.cpp b/libcxx/test/std/diagnostics/syserr/syserr.errcat/syserr.errcat.objects/system_category.pass.cpp index 4a29e1baa808..7c98a42b5201 100644 --- a/libcxx/test/std/diagnostics/syserr/syserr.errcat/syserr.errcat.objects/system_category.pass.cpp +++ b/libcxx/test/std/diagnostics/syserr/syserr.errcat/syserr.errcat.objects/system_category.pass.cpp @@ -13,7 +13,6 @@ // const error_category& system_category(); // XFAIL: stdlib=apple-libc++ && target={{.+}}-apple-macosx10.{{9|10|11|12}} -// XFAIL: LIBCXX-PICOLIBC-FIXME #include #include @@ -52,6 +51,8 @@ int main(int, char**) // Exact message format varies by platform. #if defined(_AIX) LIBCPP_ASSERT(msg.rfind("Error -1 occurred", 0) == 0); +#elif defined(_NEWLIB_VERSION) + LIBCPP_ASSERT(msg.empty()); #else LIBCPP_ASSERT(msg.rfind("Unknown error", 0) == 0); #endif diff --git a/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/member_swap_noexcept.pass.cpp b/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/member_swap_noexcept.pass.cpp index cdb09df7c7a9..0a0128e44658 100644 --- a/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/member_swap_noexcept.pass.cpp +++ b/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/member_swap_noexcept.pass.cpp @@ -27,7 +27,7 @@ struct test_alloc { using value_type = T; [[nodiscard]] constexpr T* allocate(std::size_t) { return nullptr; } - void deallocate(void*, unsigned) {} + void deallocate(void*, std::size_t) {} }; template diff --git a/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/nonmember_swap_noexcept.pass.cpp b/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/nonmember_swap_noexcept.pass.cpp index fdefc5ebe9af..4f41e3a4d716 100644 --- a/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/nonmember_swap_noexcept.pass.cpp +++ b/libcxx/test/std/input.output/string.streams/stringbuf/stringbuf.assign/nonmember_swap_noexcept.pass.cpp @@ -26,7 +26,7 @@ struct test_alloc { using value_type = T; [[nodiscard]] constexpr T* allocate(std::size_t) { return nullptr; } - void deallocate(void*, unsigned) {} + void deallocate(void*, std::size_t) {} }; template diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/source_location.version.compile.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/source_location.version.compile.pass.cpp index b0ccf795bb72..7c5d882a37e6 100644 --- a/libcxx/test/std/language.support/support.limits/support.limits.general/source_location.version.compile.pass.cpp +++ b/libcxx/test/std/language.support/support.limits/support.limits.general/source_location.version.compile.pass.cpp @@ -42,47 +42,29 @@ #elif TEST_STD_VER == 20 -# if __has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403) -# ifndef __cpp_lib_source_location -# error "__cpp_lib_source_location should be defined in c++20" -# endif -# if __cpp_lib_source_location != 201907L -# error "__cpp_lib_source_location should have the value 201907L in c++20" -# endif -# else -# ifdef __cpp_lib_source_location -# error "__cpp_lib_source_location should not be defined when the requirement '__has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403)' is not met!" -# endif +# ifndef __cpp_lib_source_location +# error "__cpp_lib_source_location should be defined in c++20" +# endif +# if __cpp_lib_source_location != 201907L +# error "__cpp_lib_source_location should have the value 201907L in c++20" # endif #elif TEST_STD_VER == 23 -# if __has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403) -# ifndef __cpp_lib_source_location -# error "__cpp_lib_source_location should be defined in c++23" -# endif -# if __cpp_lib_source_location != 201907L -# error "__cpp_lib_source_location should have the value 201907L in c++23" -# endif -# else -# ifdef __cpp_lib_source_location -# error "__cpp_lib_source_location should not be defined when the requirement '__has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403)' is not met!" -# endif +# ifndef __cpp_lib_source_location +# error "__cpp_lib_source_location should be defined in c++23" +# endif +# if __cpp_lib_source_location != 201907L +# error "__cpp_lib_source_location should have the value 201907L in c++23" # endif #elif TEST_STD_VER > 23 -# if __has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403) -# ifndef __cpp_lib_source_location -# error "__cpp_lib_source_location should be defined in c++26" -# endif -# if __cpp_lib_source_location != 201907L -# error "__cpp_lib_source_location should have the value 201907L in c++26" -# endif -# else -# ifdef __cpp_lib_source_location -# error "__cpp_lib_source_location should not be defined when the requirement '__has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403)' is not met!" -# endif +# ifndef __cpp_lib_source_location +# error "__cpp_lib_source_location should be defined in c++26" +# endif +# if __cpp_lib_source_location != 201907L +# error "__cpp_lib_source_location should have the value 201907L in c++26" # endif #endif // TEST_STD_VER > 23 diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp index 0b00469892f6..c0d3d554dcf0 100644 --- a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp +++ b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp @@ -4015,17 +4015,11 @@ # error "__cpp_lib_smart_ptr_owner_equality should not be defined before c++26" # endif -# if __has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403) -# ifndef __cpp_lib_source_location -# error "__cpp_lib_source_location should be defined in c++20" -# endif -# if __cpp_lib_source_location != 201907L -# error "__cpp_lib_source_location should have the value 201907L in c++20" -# endif -# else -# ifdef __cpp_lib_source_location -# error "__cpp_lib_source_location should not be defined when the requirement '__has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403)' is not met!" -# endif +# ifndef __cpp_lib_source_location +# error "__cpp_lib_source_location should be defined in c++20" +# endif +# if __cpp_lib_source_location != 201907L +# error "__cpp_lib_source_location should have the value 201907L in c++20" # endif # ifndef __cpp_lib_span @@ -5539,17 +5533,11 @@ # error "__cpp_lib_smart_ptr_owner_equality should not be defined before c++26" # endif -# if __has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403) -# ifndef __cpp_lib_source_location -# error "__cpp_lib_source_location should be defined in c++23" -# endif -# if __cpp_lib_source_location != 201907L -# error "__cpp_lib_source_location should have the value 201907L in c++23" -# endif -# else -# ifdef __cpp_lib_source_location -# error "__cpp_lib_source_location should not be defined when the requirement '__has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403)' is not met!" -# endif +# ifndef __cpp_lib_source_location +# error "__cpp_lib_source_location should be defined in c++23" +# endif +# if __cpp_lib_source_location != 201907L +# error "__cpp_lib_source_location should have the value 201907L in c++23" # endif # ifndef __cpp_lib_span @@ -7282,17 +7270,11 @@ # endif # endif -# if __has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403) -# ifndef __cpp_lib_source_location -# error "__cpp_lib_source_location should be defined in c++26" -# endif -# if __cpp_lib_source_location != 201907L -# error "__cpp_lib_source_location should have the value 201907L in c++26" -# endif -# else -# ifdef __cpp_lib_source_location -# error "__cpp_lib_source_location should not be defined when the requirement '__has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403)' is not met!" -# endif +# ifndef __cpp_lib_source_location +# error "__cpp_lib_source_location should be defined in c++26" +# endif +# if __cpp_lib_source_location != 201907L +# error "__cpp_lib_source_location should have the value 201907L in c++26" # endif # ifndef __cpp_lib_span diff --git a/libcxx/test/std/numerics/rand/rand.device/ctor.pass.cpp b/libcxx/test/std/numerics/rand/rand.device/ctor.pass.cpp index a2d46ab1b94c..796ab41716dd 100644 --- a/libcxx/test/std/numerics/rand/rand.device/ctor.pass.cpp +++ b/libcxx/test/std/numerics/rand/rand.device/ctor.pass.cpp @@ -61,6 +61,7 @@ void check_random_device_invalid(const std::string &token) { int main(int, char**) { { std::random_device r; + (void)r; } // Check the validity of various tokens { diff --git a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/compare.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/compare.pass.cpp index 38b6346e0061..a3a51c79ccd1 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/compare.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/compare.pass.cpp @@ -31,15 +31,15 @@ constexpr void test() { using ChunkByView = std::ranges::chunk_by_view; using ChunkByIterator = std::ranges::iterator_t; - auto make_chunk_by_view = [](auto begin, auto end) { - View view{Iterator(begin), Sentinel(Iterator(end))}; + auto make_chunk_by_view = [](auto& arr) { + View view{Iterator(arr.data()), Sentinel(Iterator(arr.data() + arr.size()))}; return ChunkByView(std::move(view), std::ranges::less_equal{}); }; // Test operator== { std::array array{0, 1, 2}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator i = view.begin(); ChunkByIterator j = view.begin(); @@ -52,7 +52,7 @@ constexpr void test() { // Test synthesized operator!= { std::array array{0, 1, 2}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator i = view.begin(); ChunkByIterator j = view.begin(); @@ -65,7 +65,7 @@ constexpr void test() { // Test operator== with std::default_sentinel_t { std::array array{0, 1, 2}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator i = view.begin(); std::same_as decltype(auto) result = (i == std::default_sentinel); @@ -77,7 +77,7 @@ constexpr void test() { // Test synthesized operator!= with std::default_sentinel_t { std::array array{0, 1, 2}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator i = view.begin(); std::same_as decltype(auto) result = (i != std::default_sentinel); diff --git a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/decrement.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/decrement.pass.cpp index 167f3f753bfa..c6c036363d3d 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/decrement.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/decrement.pass.cpp @@ -51,107 +51,107 @@ constexpr void test() { static_assert(HasPostDecrement); static_assert(HasPreDecrement); - auto make_chunk_by_view = [](auto begin, auto end) { - View view{Iterator{begin}, Sentinel{Iterator{end}}}; + auto make_chunk_by_view = [](auto& arr) { + View view{Iterator{arr.data()}, Sentinel{Iterator{arr.data() + arr.size()}}}; return ChunkByView{std::move(view), std::ranges::less_equal{}}; }; // Test with a single chunk { std::array array{0, 1, 2, 3, 4}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = std::ranges::next(view.begin(), view.end()); std::same_as decltype(auto) result = --it; assert(&result == &it); - assert(base((*result).begin()) == array.begin()); + assert(base((*result).begin()) == array.data()); } // Test with two chunks { std::array array{0, 1, 2, 0, 1, 2}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = std::ranges::next(view.begin(), view.end()); std::same_as decltype(auto) result = --it; assert(&result == &it); - assert(base((*result).begin()) == array.begin() + 3); + assert(base((*result).begin()) == array.data() + 3); --it; - assert(base((*result).begin()) == array.begin()); + assert(base((*result).begin()) == array.data()); } // Test going forward and then backward on the same iterator { std::array array{7, 8, 9, 4, 5, 6, 1, 2, 3, 0}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = view.begin(); ++it; --it; - assert(base((*it).begin()) == array.begin()); - assert(base((*it).end()) == array.begin() + 3); + assert(base((*it).begin()) == array.data()); + assert(base((*it).end()) == array.data() + 3); ++it; ++it; --it; - assert(base((*it).begin()) == array.begin() + 3); - assert(base((*it).end()) == array.begin() + 6); + assert(base((*it).begin()) == array.data() + 3); + assert(base((*it).end()) == array.data() + 6); ++it; ++it; --it; - assert(base((*it).begin()) == array.begin() + 6); - assert(base((*it).end()) == array.begin() + 9); + assert(base((*it).begin()) == array.data() + 6); + assert(base((*it).end()) == array.data() + 9); ++it; ++it; --it; - assert(base((*it).begin()) == array.begin() + 9); + assert(base((*it).begin()) == array.data() + 9); } // Decrement an iterator multiple times if constexpr (std::ranges::common_range) { std::array array{1, 2, 1, 2, 1}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = view.end(); --it; --it; --it; - assert(base((*it).begin()) == array.begin()); + assert(base((*it).begin()) == array.data()); } // Test with a predicate that takes by non-const reference if constexpr (!std::to_underlying(Constant)) { std::array array{1, 2, 3, -3, -2, -1}; - View v{Iterator{array.begin()}, Sentinel{Iterator{array.end()}}}; + View v{Iterator{array.data()}, Sentinel{Iterator{array.data() + array.size()}}}; auto view = std::views::chunk_by(std::move(v), [](int& x, int& y) { return x <= y; }); auto it = std::ranges::next(view.begin()); - assert(base((*it).begin()) == array.begin() + 3); + assert(base((*it).begin()) == array.data() + 3); --it; - assert(base((*it).begin()) == array.begin()); + assert(base((*it).begin()) == array.data()); } // Test with a predicate that is invocable but not callable (i.e. cannot be called like regular function 'f()') { std::array array = {1, 2, 3, -3, -2, -1}; - auto v = View{Iterator{array.begin()}, Sentinel{Iterator{array.end()}}} - | std::views::transform([](int x) { return IntWrapper{x}; }); + auto v = View{Iterator{array.data()}, Sentinel{Iterator{array.data() + array.size()}}} | + std::views::transform([](int x) { return IntWrapper{x}; }); auto view = std::views::chunk_by(std::move(v), &IntWrapper::lessEqual); auto it = std::ranges::next(view.begin()); - assert(base((*it).begin().base()) == array.begin() + 3); + assert(base((*it).begin().base()) == array.data() + 3); --it; - assert(base((*it).begin().base()) == array.begin()); + assert(base((*it).begin().base()) == array.data()); } // Make sure we do not make a copy of the predicate when we decrement if constexpr (std::ranges::common_range) { bool moved = false, copied = false; std::array array{1, 2, 1, 3}; - View v{Iterator(array.begin()), Sentinel(Iterator(array.end()))}; + View v{Iterator(array.data()), Sentinel(Iterator(array.data() + array.size()))}; auto view = std::views::chunk_by(std::move(v), TrackingPred(&moved, &copied)); assert(std::exchange(moved, false)); auto it = view.end(); @@ -164,21 +164,21 @@ constexpr void test() { // Check post-decrement { std::array array{0, 1, 2, -3, -2, -1, -6, -5, -4}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = std::ranges::next(view.begin(), view.end()); std::same_as decltype(auto) result = it--; assert(result != it); assert(result == std::default_sentinel); - assert(base((*it).begin()) == array.begin() + 6); + assert(base((*it).begin()) == array.data() + 6); result = it--; - assert(base((*it).begin()) == array.begin() + 3); - assert(base((*result).begin()) == array.begin() + 6); + assert(base((*it).begin()) == array.data() + 3); + assert(base((*result).begin()) == array.data() + 6); result = it--; - assert(base((*it).begin()) == array.begin()); - assert(base((*result).begin()) == array.begin() + 3); + assert(base((*it).begin()) == array.data()); + assert(base((*result).begin()) == array.data() + 3); } } diff --git a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/deref.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/deref.pass.cpp index 3f8c073e7b3b..8cc9bdac0b1d 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/deref.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/deref.pass.cpp @@ -33,7 +33,7 @@ constexpr void test() { std::array array{0, 1, 2, 3, -1, 0, 1, 2, -2, 3, 4, 5}; std::array expected{std::array{0, 1, 2, 3}, std::array{-1, 0, 1, 2}, std::array{-2, 3, 4, 5}}; - Underlying underlying{Iter{array.begin()}, Sent{Iter{array.end()}}}; + Underlying underlying{Iter{array.data()}, Sent{Iter{array.data() + array.size()}}}; ChunkByView view{underlying, std::ranges::less_equal{}}; size_t idx = 0; diff --git a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/increment.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/increment.pass.cpp index 454e9e7503a5..3a9262cb2ad7 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/increment.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/increment.pass.cpp @@ -39,15 +39,15 @@ constexpr void test() { using ChunkByView = std::ranges::chunk_by_view; using ChunkByIterator = std::ranges::iterator_t; - auto make_chunk_by_view = [](auto begin, auto end) { - View view{Iterator{begin}, Sentinel{Iterator{end}}}; + auto make_chunk_by_view = [](auto& arr) { + View view{Iterator{arr.data()}, Sentinel{Iterator{arr.data() + arr.size()}}}; return ChunkByView{std::move(view), std::ranges::less_equal{}}; }; // Increment the iterator when it won't find another satisfied value after begin() { std::array array{0, 1, 2, 3, 4}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = view.begin(); std::same_as decltype(auto) result = ++it; @@ -59,8 +59,8 @@ constexpr void test() { // Increment the iterator and it finds another value after begin() { std::array array{1, 2, 3, -1, -2, -3}; - int const* second_chunk = array.begin() + 3; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + int const* second_chunk = array.data() + 3; + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = view.begin(); ++it; @@ -70,26 +70,26 @@ constexpr void test() { // Increment advances all the way to the end of the range { std::array array{1, 2, 3, 4, 1}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = view.begin(); ++it; - assert(base((*it).begin()) == array.begin() + 4); + assert(base((*it).begin()) == array.data() + 4); } // Increment an iterator multiple times { std::array array{0, 1, 0, 2, 0, 3, 0, 4}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = view.begin(); - assert(base((*it).begin()) == array.begin()); + assert(base((*it).begin()) == array.data()); ++it; - assert(base((*it).begin()) == array.begin() + 2); + assert(base((*it).begin()) == array.data() + 2); ++it; - assert(base((*it).begin()) == array.begin() + 4); + assert(base((*it).begin()) == array.data() + 4); ++it; - assert(base((*it).begin()) == array.begin() + 6); + assert(base((*it).begin()) == array.data() + 6); ++it; assert(it == std::default_sentinel); } @@ -97,26 +97,26 @@ constexpr void test() { // Test with a predicate that takes by non-const reference if constexpr (!std::to_underlying(Constant)) { std::array array{1, 2, 3, -3, -2, -1}; - View v{Iterator{array.begin()}, Sentinel{Iterator{array.end()}}}; + View v{Iterator{array.data()}, Sentinel{Iterator{array.data() + array.size()}}}; auto view = std::views::chunk_by(std::move(v), [](int& x, int& y) { return x <= y; }); auto it = view.begin(); - assert(base((*it).begin()) == array.begin()); + assert(base((*it).begin()) == array.data()); ++it; - assert(base((*it).begin()) == array.begin() + 3); + assert(base((*it).begin()) == array.data() + 3); } // Test with a predicate that is invocable but not callable (i.e. cannot be called like regular function 'f()') { std::array array = {1, 2, 3, -3, -2, -1}; - auto v = View{Iterator{array.begin()}, Sentinel{Iterator{array.end()}}} - | std::views::transform([](int x) { return IntWrapper{x}; }); + auto v = View{Iterator{array.data()}, Sentinel{Iterator{array.data() + array.size()}}} | + std::views::transform([](int x) { return IntWrapper{x}; }); auto view = std::views::chunk_by(std::move(v), &IntWrapper::lessEqual); auto it = view.begin(); - assert(base((*it).begin().base()) == array.begin()); + assert(base((*it).begin().base()) == array.data()); ++it; - assert(base((*it).begin().base()) == array.begin() + 3); + assert(base((*it).begin().base()) == array.data() + 3); } // Make sure we do not make a copy of the predicate when we increment @@ -124,7 +124,7 @@ constexpr void test() { { bool moved = false, copied = false; std::array array{1, 2, 1, 3}; - View v{Iterator(array.begin()), Sentinel(Iterator(array.end()))}; + View v{Iterator(array.data()), Sentinel(Iterator(array.data() + array.size()))}; auto view = std::views::chunk_by(std::move(v), TrackingPred(&moved, &copied)); assert(std::exchange(moved, false)); auto it = view.begin(); @@ -137,20 +137,20 @@ constexpr void test() { // Check post-increment { std::array array{0, 1, 2, -3, -2, -1, -6, -5, -4}; - ChunkByView view = make_chunk_by_view(array.begin(), array.end()); + ChunkByView view = make_chunk_by_view(array); ChunkByIterator it = view.begin(); std::same_as decltype(auto) result = it++; assert(result != it); - assert(base((*result).begin()) == array.begin()); - assert(base((*it).begin()) == array.begin() + 3); + assert(base((*result).begin()) == array.data()); + assert(base((*it).begin()) == array.data() + 3); result = it++; - assert(base((*result).begin()) == array.begin() + 3); - assert(base((*it).begin()) == array.begin() + 6); + assert(base((*result).begin()) == array.data() + 3); + assert(base((*it).begin()) == array.data() + 6); result = it++; - assert(base((*result).begin()) == array.begin() + 6); + assert(base((*result).begin()) == array.data() + 6); assert(it == std::default_sentinel); } } diff --git a/libcxx/test/std/ranges/range.adaptors/range.filter/iterator/arrow.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.filter/iterator/arrow.pass.cpp index f139226b875f..0c02cfdb76ad 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.filter/iterator/arrow.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.filter/iterator/arrow.pass.cpp @@ -59,7 +59,7 @@ struct WithNonCopyableIterator : std::ranges::view_base { iterator(iterator&&); iterator& operator=(iterator&&); XYPoint& operator*() const; - iterator operator->() const; + XYPoint* operator->() const; iterator& operator++(); iterator operator++(int); diff --git a/libcxx/test/std/ranges/range.factories/range.repeat.view/size.pass.cpp b/libcxx/test/std/ranges/range.factories/range.repeat.view/size.pass.cpp index 72531b059aa2..6f24b3b9bf75 100644 --- a/libcxx/test/std/ranges/range.factories/range.repeat.view/size.pass.cpp +++ b/libcxx/test/std/ranges/range.factories/range.repeat.view/size.pass.cpp @@ -31,8 +31,9 @@ constexpr bool test() { } { - std::ranges::repeat_view rv(10, std::numeric_limits::max()); - assert(rv.size() == std::numeric_limits::max()); + constexpr int int_max = std::numeric_limits::max(); + std::ranges::repeat_view rv(10, int_max); + assert(rv.size() == int_max); } return true; diff --git a/libcxx/test/std/strings/string.view/string.view.comparison/equal.pass.cpp b/libcxx/test/std/strings/string.view/string.view.comparison/equal.pass.cpp index 4f00bd7f6edf..fc99df407213 100644 --- a/libcxx/test/std/strings/string.view/string.view.comparison/equal.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.comparison/equal.pass.cpp @@ -51,7 +51,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((ConvertibleTo(v[i]) == v[j]) == expected); assert((v[i] == ConvertibleTo(v[j])) == expected); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(v[i]) == v[j]) == expected); assert((v[i] == std::basic_string(v[j])) == expected); } @@ -72,7 +72,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((abc.data() == abc0def) == false); assert((abc0def == abc.data()) == false); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(abc) == abc0def) == false); assert((abc0def == std::basic_string(abc)) == false); } diff --git a/libcxx/test/std/strings/string.view/string.view.comparison/greater.pass.cpp b/libcxx/test/std/strings/string.view/string.view.comparison/greater.pass.cpp index b965c155ec51..fd3a43816799 100644 --- a/libcxx/test/std/strings/string.view/string.view.comparison/greater.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.comparison/greater.pass.cpp @@ -51,7 +51,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((ConvertibleTo(v[i]) > v[j]) == expected); assert((v[i] > ConvertibleTo(v[j])) == expected); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(v[i]) > v[j]) == expected); assert((v[i] > std::basic_string(v[j])) == expected); } @@ -72,7 +72,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((abc.data() > abc0def) == false); assert((abc0def > abc.data()) == true); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(abc) > abc0def) == false); assert((abc0def > std::basic_string(abc)) == true); } diff --git a/libcxx/test/std/strings/string.view/string.view.comparison/greater_equal.pass.cpp b/libcxx/test/std/strings/string.view/string.view.comparison/greater_equal.pass.cpp index 435e7db77319..0d9081e1c01d 100644 --- a/libcxx/test/std/strings/string.view/string.view.comparison/greater_equal.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.comparison/greater_equal.pass.cpp @@ -51,7 +51,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((ConvertibleTo(v[i]) >= v[j]) == expected); assert((v[i] >= ConvertibleTo(v[j])) == expected); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(v[i]) >= v[j]) == expected); assert((v[i] >= std::basic_string(v[j])) == expected); } @@ -72,7 +72,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((abc.data() >= abc0def) == false); assert((abc0def >= abc.data()) == true); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(abc) >= abc0def) == false); assert((abc0def >= std::basic_string(abc)) == true); } diff --git a/libcxx/test/std/strings/string.view/string.view.comparison/less.pass.cpp b/libcxx/test/std/strings/string.view/string.view.comparison/less.pass.cpp index 7461b05ce308..bb61b1df193e 100644 --- a/libcxx/test/std/strings/string.view/string.view.comparison/less.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.comparison/less.pass.cpp @@ -51,7 +51,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((ConvertibleTo(v[i]) < v[j]) == expected); assert((v[i] < ConvertibleTo(v[j])) == expected); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(v[i]) < v[j]) == expected); assert((v[i] < std::basic_string(v[j])) == expected); } @@ -72,7 +72,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((abc.data() < abc0def) == true); assert((abc0def < abc.data()) == false); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(abc) < abc0def) == true); assert((abc0def < std::basic_string(abc)) == false); } diff --git a/libcxx/test/std/strings/string.view/string.view.comparison/less_equal.pass.cpp b/libcxx/test/std/strings/string.view/string.view.comparison/less_equal.pass.cpp index 3192db0dc7d7..d91e112d6dab 100644 --- a/libcxx/test/std/strings/string.view/string.view.comparison/less_equal.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.comparison/less_equal.pass.cpp @@ -51,7 +51,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((ConvertibleTo(v[i]) <= v[j]) == expected); assert((v[i] <= ConvertibleTo(v[j])) == expected); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(v[i]) <= v[j]) == expected); assert((v[i] <= std::basic_string(v[j])) == expected); } @@ -72,7 +72,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((abc.data() <= abc0def) == true); assert((abc0def <= abc.data()) == false); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(abc) <= abc0def) == true); assert((abc0def <= std::basic_string(abc)) == false); } diff --git a/libcxx/test/std/strings/string.view/string.view.comparison/not_equal.pass.cpp b/libcxx/test/std/strings/string.view/string.view.comparison/not_equal.pass.cpp index 0082a5683933..a4c8be9f878f 100644 --- a/libcxx/test/std/strings/string.view/string.view.comparison/not_equal.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.comparison/not_equal.pass.cpp @@ -51,7 +51,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((ConvertibleTo(v[i]) != v[j]) == expected); assert((v[i] != ConvertibleTo(v[j])) == expected); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(v[i]) != v[j]) == expected); assert((v[i] != std::basic_string(v[j])) == expected); } @@ -72,7 +72,7 @@ TEST_CONSTEXPR_CXX14 bool test() { assert((abc.data() != abc0def) == true); assert((abc0def != abc.data()) == true); - if (!TEST_IS_CONSTANT_EVALUATED || TEST_STD_VER >= 20) { + if (TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED) { assert((std::basic_string(abc) != abc0def) == true); assert((abc0def != std::basic_string(abc)) == true); } diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.scoped/mutex.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.scoped/mutex.pass.cpp index 48a96f90254e..f953fa4f8d6d 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.scoped/mutex.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.scoped/mutex.pass.cpp @@ -66,6 +66,7 @@ int main(int, char**) { using LG = std::scoped_lock<>; LG lg; + (void)lg; } { using LG = std::scoped_lock; diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/default.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/default.pass.cpp index 91320a52b62a..5504645bb31f 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/default.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/default.pass.cpp @@ -22,6 +22,7 @@ int main(int, char**) { std::shared_mutex m; + (void)m; - return 0; + return 0; } diff --git a/libcxx/test/support/container_debug_tests.h b/libcxx/test/support/container_debug_tests.h index c35da37a87da..757ae28eff9f 100644 --- a/libcxx/test/support/container_debug_tests.h +++ b/libcxx/test/support/container_debug_tests.h @@ -9,7 +9,8 @@ #ifndef TEST_SUPPORT_CONTAINER_DEBUG_TESTS_H #define TEST_SUPPORT_CONTAINER_DEBUG_TESTS_H -#include +#include "test_macros.h" + #ifndef _LIBCPP_VERSION #error This header may only be used for libc++ tests #endif @@ -25,7 +26,6 @@ #include "check_assertion.h" #include "test_allocator.h" -#include "test_macros.h" // These test make use of 'if constexpr'. #if TEST_STD_VER <= 14 diff --git a/libcxx/test/support/msvc_stdlib_force_include.h b/libcxx/test/support/msvc_stdlib_force_include.h index 3c61f0b880b1..b5ba33bd281c 100644 --- a/libcxx/test/support/msvc_stdlib_force_include.h +++ b/libcxx/test/support/msvc_stdlib_force_include.h @@ -13,29 +13,38 @@ // MSVC standard library. #ifndef _LIBCXX_IN_DEVCRT - // Silence warnings about CRT machinery. - #define _CRT_SECURE_NO_WARNINGS 1 +// Silence warnings about CRT machinery. +# define _CRT_SECURE_NO_WARNINGS 1 - // Avoid assertion dialogs. - #define _CRT_SECURE_INVALID_PARAMETER(EXPR) ::abort() +// Avoid assertion dialogs. +# define _CRT_SECURE_INVALID_PARAMETER(EXPR) ::abort() + +// Declare POSIX function names. (By default, Clang -fno-ms-compatibility causes them to be omitted.) +# define _CRT_DECLARE_NONSTDC_NAMES 1 + +// Silence warnings about POSIX function names. +# define _CRT_NONSTDC_NO_WARNINGS 1 + +// Avoid Windows.h macroizing min() and max(). +# define NOMINMAX 1 #endif // _LIBCXX_IN_DEVCRT #include #include #if defined(_LIBCPP_VERSION) - #error This header may not be used when targeting libc++ +# error This header may not be used when targeting libc++ #endif #ifndef _LIBCXX_IN_DEVCRT struct AssertionDialogAvoider { - AssertionDialogAvoider() { - _CrtSetReportMode(_CRT_ASSERT, _CRTDBG_MODE_FILE); - _CrtSetReportFile(_CRT_ASSERT, _CRTDBG_FILE_STDERR); + AssertionDialogAvoider() { + _CrtSetReportMode(_CRT_ASSERT, _CRTDBG_MODE_FILE); + _CrtSetReportFile(_CRT_ASSERT, _CRTDBG_FILE_STDERR); - _CrtSetReportMode(_CRT_ERROR, _CRTDBG_MODE_FILE); - _CrtSetReportFile(_CRT_ERROR, _CRTDBG_FILE_STDERR); - } + _CrtSetReportMode(_CRT_ERROR, _CRTDBG_MODE_FILE); + _CrtSetReportFile(_CRT_ERROR, _CRTDBG_FILE_STDERR); + } }; const AssertionDialogAvoider assertion_dialog_avoider{}; @@ -43,68 +52,64 @@ const AssertionDialogAvoider assertion_dialog_avoider{}; // MSVC frontend only configurations #if !defined(__clang__) - // Simulate feature-test macros. - #define __has_feature(X) _MSVC_HAS_FEATURE_ ## X - #define _MSVC_HAS_FEATURE_cxx_exceptions 1 - #define _MSVC_HAS_FEATURE_cxx_rtti 1 - #define _MSVC_HAS_FEATURE_address_sanitizer 0 - #define _MSVC_HAS_FEATURE_memory_sanitizer 0 - #define _MSVC_HAS_FEATURE_thread_sanitizer 0 - - #define __has_attribute(X) _MSVC_HAS_ATTRIBUTE_ ## X - #define _MSVC_HAS_ATTRIBUTE_vector_size 0 - - // Silence compiler warnings. - #pragma warning(disable: 4180) // qualifier applied to function type has no meaning; ignored - #pragma warning(disable: 4324) // structure was padded due to alignment specifier - #pragma warning(disable: 4521) // multiple copy constructors specified - #pragma warning(disable: 4702) // unreachable code - #pragma warning(disable: 28251) // Inconsistent annotation for 'new': this instance has no annotations. -#endif // !defined(__clang__) +// Simulate feature-test macros. +# define __has_feature(X) _MSVC_HAS_FEATURE_##X +# define _MSVC_HAS_FEATURE_cxx_exceptions 1 +# define _MSVC_HAS_FEATURE_cxx_rtti 1 +# define _MSVC_HAS_FEATURE_address_sanitizer 0 +# define _MSVC_HAS_FEATURE_hwaddress_sanitizer 0 +# define _MSVC_HAS_FEATURE_memory_sanitizer 0 +# define _MSVC_HAS_FEATURE_thread_sanitizer 0 + +# define __has_attribute(X) _MSVC_HAS_ATTRIBUTE_##X +# define _MSVC_HAS_ATTRIBUTE_vector_size 0 + +// Silence compiler warnings. +# pragma warning(disable : 4180) // qualifier applied to function type has no meaning; ignored +# pragma warning(disable : 4324) // structure was padded due to alignment specifier +# pragma warning(disable : 4521) // multiple copy constructors specified +# pragma warning(disable : 4702) // unreachable code +# pragma warning(disable : 28251) // Inconsistent annotation for 'new': this instance has no annotations. +#endif // !defined(__clang__) #ifndef _LIBCXX_IN_DEVCRT - // atomic_is_lock_free.pass.cpp needs this VS 2015 Update 2 fix. - #define _ENABLE_ATOMIC_ALIGNMENT_FIX +// atomic_is_lock_free.pass.cpp needs this VS 2015 Update 2 fix. +# define _ENABLE_ATOMIC_ALIGNMENT_FIX - // Restore features that are removed in C++20. - #define _HAS_FEATURES_REMOVED_IN_CXX20 1 +// Restore features that are removed in C++20. +# define _HAS_FEATURES_REMOVED_IN_CXX20 1 - // Silence warnings about the unspecified complex - #define _SILENCE_NONFLOATING_COMPLEX_DEPRECATION_WARNING +// Silence warnings about the unspecified complex +# define _SILENCE_NONFLOATING_COMPLEX_DEPRECATION_WARNING - // Silence warnings about features that are deprecated in non-default language modes. - #define _SILENCE_ALL_CXX17_DEPRECATION_WARNINGS - #define _SILENCE_ALL_CXX20_DEPRECATION_WARNINGS - #define _SILENCE_ALL_CXX23_DEPRECATION_WARNINGS +// Silence warnings about features that are deprecated in non-default language modes. +# define _SILENCE_ALL_CXX17_DEPRECATION_WARNINGS +# define _SILENCE_ALL_CXX20_DEPRECATION_WARNINGS +# define _SILENCE_ALL_CXX23_DEPRECATION_WARNINGS #endif // _LIBCXX_IN_DEVCRT #include #if _HAS_CXX23 - #define TEST_STD_VER 99 +# define TEST_STD_VER 99 #elif _HAS_CXX20 - #define TEST_STD_VER 20 +# define TEST_STD_VER 20 #elif _HAS_CXX17 - #define TEST_STD_VER 17 +# define TEST_STD_VER 17 #else - #define TEST_STD_VER 14 +# define TEST_STD_VER 14 #endif #define _LIBCPP_AVAILABILITY_THROW_BAD_ANY_CAST #ifdef __clang__ -#define _LIBCPP_SUPPRESS_DEPRECATED_PUSH \ - _Pragma("GCC diagnostic push") \ - _Pragma("GCC diagnostic ignored \"-Wdeprecated\"") -#define _LIBCPP_SUPPRESS_DEPRECATED_POP \ - _Pragma("GCC diagnostic pop") +# define _LIBCPP_SUPPRESS_DEPRECATED_PUSH \ + _Pragma("GCC diagnostic push") _Pragma("GCC diagnostic ignored \"-Wdeprecated\"") +# define _LIBCPP_SUPPRESS_DEPRECATED_POP _Pragma("GCC diagnostic pop") #else // ^^^ clang / MSVC vvv -#define _LIBCPP_SUPPRESS_DEPRECATED_PUSH \ - __pragma(warning(push)) \ - __pragma(warning(disable : 4996)) \ - __pragma(warning(disable : 5215)) -#define _LIBCPP_SUPPRESS_DEPRECATED_POP \ - __pragma(warning(pop)) +# define _LIBCPP_SUPPRESS_DEPRECATED_PUSH \ + __pragma(warning(push)) __pragma(warning(disable : 4996)) __pragma(warning(disable : 5215)) +# define _LIBCPP_SUPPRESS_DEPRECATED_POP __pragma(warning(pop)) #endif // __clang__ #endif // SUPPORT_MSVC_STDLIB_FORCE_INCLUDE_H diff --git a/libcxx/test/support/test_macros.h b/libcxx/test/support/test_macros.h index f3c6d8080ff6..ea289f0432e6 100644 --- a/libcxx/test/support/test_macros.h +++ b/libcxx/test/support/test_macros.h @@ -10,17 +10,14 @@ #ifndef SUPPORT_TEST_MACROS_HPP #define SUPPORT_TEST_MACROS_HPP -// Attempt to get STL specific macros like _LIBCPP_VERSION using the most -// minimal header possible. If we're testing libc++, we should use `<__config>`. -// If <__config> isn't available, fall back to . #ifdef __has_include -# if __has_include("<__config>") -# include <__config> -# define TEST_IMP_INCLUDED_HEADER -# endif -#endif -#ifndef TEST_IMP_INCLUDED_HEADER -#include +# if __has_include("") +# include +# else +# include +# endif +#else +# include #endif #define TEST_STRINGIZE_IMPL(...) #__VA_ARGS__ @@ -151,6 +148,18 @@ # define TEST_IS_CONSTANT_EVALUATED false #endif +#if TEST_STD_VER >= 23 +# define TEST_STD_AT_LEAST_23_OR_RUNTIME_EVALUATED true +#else +# define TEST_STD_AT_LEAST_23_OR_RUNTIME_EVALUATED (!TEST_IS_CONSTANT_EVALUATED) +#endif + +#if TEST_STD_VER >= 20 +# define TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED true +#else +# define TEST_STD_AT_LEAST_20_OR_RUNTIME_EVALUATED (!TEST_IS_CONSTANT_EVALUATED) +#endif + #if TEST_STD_VER >= 14 # define TEST_CONSTEXPR_CXX14 constexpr #else diff --git a/libcxx/utils/clang-format-merge-driver.sh b/libcxx/utils/clang-format-merge-driver.sh new file mode 100755 index 000000000000..5abb8ee3e436 --- /dev/null +++ b/libcxx/utils/clang-format-merge-driver.sh @@ -0,0 +1,37 @@ +#!/usr/bin/env bash + +# This script can be installed in .git/config to allow rebasing old patches across +# libc++'s clang-format of the whole tree. Most contributors should not require that +# since they don't have many pre-clang-format patches lying around. This script is to +# make it easier for contributors that do have such patches. +# +# The script is installed by running the following from the root of your repository: +# +# $ git config merge.libcxx-reformat.name "Run clang-format when rebasing libc++ patches" +# $ git config merge.libcxx-reformat.driver "libcxx/utils/clang-format-merge-driver.sh %O %A %B %P" +# +# This is based on https://github.com/nico/hack/blob/main/notes/auto_git_rebase_across_mechanical_changes.md. +# Many thanks to Nico Weber for paving the way here. + +# Path to the file's contents at the ancestor's version. +base="$1" + +# Path to the file's contents at the current version. +current="$2" + +# Path to the file's contents at the other branch's version (for nonlinear histories, there might be multiple other branches). +other="$3" + +# The path of the file in the repository. +path="$4" + +clang-format --style=file --assume-filename="$path" < "$base" > "$base.tmp" +mv "$base.tmp" "$base" + +clang-format --style=file --assume-filename="$path" < "$current" > "$current.tmp" +mv "$current.tmp" "$current" + +clang-format --style=file --assume-filename="$path" < "$other" > "$other.tmp" +mv "$other.tmp" "$other" + +git merge-file -Lcurrent -Lbase -Lother "$current" "$base" "$other" diff --git a/libcxx/utils/generate_escaped_output_table.py b/libcxx/utils/generate_escaped_output_table.py index 8588570c133f..5816435c96ca 100755 --- a/libcxx/utils/generate_escaped_output_table.py +++ b/libcxx/utils/generate_escaped_output_table.py @@ -231,7 +231,9 @@ _LIBCPP_BEGIN_NAMESPACE_STD #if _LIBCPP_STD_VER >= 23 namespace __escaped_output_table {{ +// clang-format off {content} +// clang-format on }} // namespace __escaped_output_table #endif //_LIBCPP_STD_VER >= 23 diff --git a/libcxx/utils/generate_extended_grapheme_cluster_table.py b/libcxx/utils/generate_extended_grapheme_cluster_table.py index 6f2c4f3e505f..b0074b58cd20 100755 --- a/libcxx/utils/generate_extended_grapheme_cluster_table.py +++ b/libcxx/utils/generate_extended_grapheme_cluster_table.py @@ -112,8 +112,10 @@ DATA_ARRAY_TEMPLATE = """ /// this approach uses less space for the data and is about 4% faster in the /// following benchmark. /// libcxx/benchmarks/std_format_spec_string_unicode.bench.cpp +// clang-format off inline constexpr uint32_t __entries[{size}] = {{ {entries}}}; +// clang-format on /// Returns the extended grapheme cluster bondary property of a code point. [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr __property __get_property(const char32_t __code_point) noexcept {{ diff --git a/libcxx/utils/generate_feature_test_macro_components.py b/libcxx/utils/generate_feature_test_macro_components.py index 8943ad255743..6a3032439788 100755 --- a/libcxx/utils/generate_feature_test_macro_components.py +++ b/libcxx/utils/generate_feature_test_macro_components.py @@ -1072,8 +1072,6 @@ feature_test_macros = [ "name": "__cpp_lib_source_location", "values": {"c++20": 201907}, "headers": ["source_location"], - "test_suite_guard": "__has_builtin(__builtin_source_location) && !(defined(TEST_APPLE_CLANG_VER) && TEST_APPLE_CLANG_VER <= 1403)", - "libcxx_guard": "__has_builtin(__builtin_source_location) && !(defined(_LIBCPP_APPLE_CLANG_VER) && _LIBCPP_APPLE_CLANG_VER <= 1403)", }, { "name": "__cpp_lib_span", diff --git a/libcxxabi/src/demangle/DemangleConfig.h b/libcxxabi/src/demangle/DemangleConfig.h index dec382d0d38f..d67d89bdb069 100644 --- a/libcxxabi/src/demangle/DemangleConfig.h +++ b/libcxxabi/src/demangle/DemangleConfig.h @@ -19,7 +19,7 @@ #include "../abort_message.h" #endif -#include +#include #ifdef _MSC_VER // snprintf is implemented in VS 2015 diff --git a/lld/COFF/Config.h b/lld/COFF/Config.h index bee6dc3ec3ca..24126f635a06 100644 --- a/lld/COFF/Config.h +++ b/lld/COFF/Config.h @@ -102,6 +102,12 @@ enum class ICFLevel { // behavior. }; +enum class BuildIDHash { + None, + PDB, + Binary, +}; + // Global configuration. struct Configuration { enum ManifestKind { Default, SideBySide, Embed, No }; @@ -318,6 +324,7 @@ struct Configuration { bool writeCheckSum = false; EmitKind emit = EmitKind::Obj; bool allowDuplicateWeak = false; + BuildIDHash buildIDHash = BuildIDHash::None; }; } // namespace lld::coff diff --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp index 327df6078fef..99c1a60735ad 100644 --- a/lld/COFF/Driver.cpp +++ b/lld/COFF/Driver.cpp @@ -2314,6 +2314,11 @@ void LinkerDriver::linkerMain(ArrayRef argsArr) { config->lldmapFile.clear(); } + // If should create PDB, use the hash of PDB content for build id. Otherwise, + // generate using the hash of executable content. + if (args.hasFlag(OPT_build_id, OPT_build_id_no, false)) + config->buildIDHash = BuildIDHash::Binary; + if (shouldCreatePDB) { // Put the PDB next to the image if no /pdb flag was passed. if (config->pdbPath.empty()) { @@ -2335,6 +2340,7 @@ void LinkerDriver::linkerMain(ArrayRef argsArr) { // Don't do this earlier, so that ctx.OutputFile is ready. parsePDBAltPath(); } + config->buildIDHash = BuildIDHash::PDB; } // Set default image base if /base is not given. @@ -2361,6 +2367,8 @@ void LinkerDriver::linkerMain(ArrayRef argsArr) { ctx.symtab.addAbsolute(mangle("__guard_eh_cont_table"), 0); if (isArm64EC(config->machine)) { + ctx.symtab.addAbsolute("__arm64x_extra_rfe_table", 0); + ctx.symtab.addAbsolute("__arm64x_extra_rfe_table_size", 0); ctx.symtab.addAbsolute("__hybrid_code_map", 0); ctx.symtab.addAbsolute("__hybrid_code_map_count", 0); } diff --git a/lld/COFF/InputFiles.cpp b/lld/COFF/InputFiles.cpp index 132a3ccfaffb..dd2e1419bb10 100644 --- a/lld/COFF/InputFiles.cpp +++ b/lld/COFF/InputFiles.cpp @@ -1042,6 +1042,19 @@ void BitcodeFile::parse() { sym = ctx.symtab.addUndefined(symName, this, false); if (objSym.isWeak()) sym->deferUndefined = true; + // If one LTO object file references (i.e. has an undefined reference to) + // a symbol with an __imp_ prefix, the LTO compilation itself sees it + // as unprefixed but with a dllimport attribute instead, and doesn't + // understand the relation to a concrete IR symbol with the __imp_ prefix. + // + // For such cases, mark the symbol as used in a regular object (i.e. the + // symbol must be retained) so that the linker can associate the + // references in the end. If the symbol is defined in an import library + // or in a regular object file, this has no effect, but if it is defined + // in another LTO object file, this makes sure it is kept, to fulfill + // the reference when linking the output of the LTO compilation. + if (symName.starts_with("__imp_")) + sym->isUsedInRegularObj = true; } else if (objSym.isCommon()) { sym = ctx.symtab.addCommon(this, symName, objSym.getCommonSize()); } else if (objSym.isWeak() && objSym.isIndirect()) { @@ -1063,12 +1076,6 @@ void BitcodeFile::parse() { } else { sym = ctx.symtab.addRegular(this, symName, nullptr, fakeSC, 0, objSym.isWeak()); - // Model all symbols with the __imp_ prefix as having external - // references. If one LTO object defines a __imp_ symbol, and - // another LTO object refers to with dllimport, make sure the - // __imp_ symbol is kept. - if (symName.starts_with("__imp_")) - sym->isUsedInRegularObj = true; } symbols.push_back(sym); if (objSym.isUsed()) diff --git a/lld/COFF/Options.td b/lld/COFF/Options.td index abee66027268..4dab4a207173 100644 --- a/lld/COFF/Options.td +++ b/lld/COFF/Options.td @@ -302,6 +302,11 @@ def : Flag<["--"], "time-trace">, Alias, def time_trace_granularity_eq: Joined<["--"], "time-trace-granularity=">, HelpText<"Minimum time granularity (in microseconds) traced by time profiler">; +defm build_id: B< + "build-id", + "Generate build ID (always on when generating PDB)", + "Do not Generate build ID">; + // Flags for debugging def lldmap : F<"lldmap">; def lldmap_file : P_priv<"lldmap">; diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp index 3490ff1b3c29..7b1ff8071e2e 100644 --- a/lld/COFF/Writer.cpp +++ b/lld/COFF/Writer.cpp @@ -247,6 +247,7 @@ private: void maybeAddRVATable(SymbolRVASet tableSymbols, StringRef tableSym, StringRef countSym, bool hasFlag=false); void setSectionPermissions(); + void setECSymbols(); void writeSections(); void writeBuildId(); void writePEChecksum(); @@ -314,6 +315,8 @@ private: OutputSection *relocSec; OutputSection *ctorsSec; OutputSection *dtorsSec; + // Either .rdata section or .buildid section. + OutputSection *debugInfoSec; // The range of .pdata sections in the output file. // @@ -326,6 +329,9 @@ private: // files, so we need to keep track of them separately. ChunkRange pdata; + // x86_64 .pdata sections on ARM64EC/ARM64X targets. + ChunkRange hybridPdata; + COFFLinkerContext &ctx; }; } // anonymous namespace @@ -741,6 +747,7 @@ void Writer::run() { removeEmptySections(); assignOutputSectionIndices(); setSectionPermissions(); + setECSymbols(); createSymbolAndStringTable(); if (fileSize > UINT32_MAX) @@ -1098,15 +1105,16 @@ void Writer::createMiscChunks() { } // Create Debug Information Chunks - OutputSection *debugInfoSec = config->mingw ? buildidSec : rdataSec; - if (config->debug || config->repro || config->cetCompat) { + debugInfoSec = config->mingw ? buildidSec : rdataSec; + if (config->buildIDHash != BuildIDHash::None || config->debug || + config->repro || config->cetCompat) { debugDirectory = make(ctx, debugRecords, config->repro); debugDirectory->setAlignment(4); debugInfoSec->addChunk(debugDirectory); } - if (config->debug) { + if (config->debug || config->buildIDHash != BuildIDHash::None) { // Make a CVDebugRecordChunk even when /DEBUG:CV is not specified. We // output a PDB no matter what, and this chunk provides the only means of // allowing a debugger to match a PDB and an executable. So we need it even @@ -1411,8 +1419,28 @@ void Writer::createSymbolAndStringTable() { void Writer::mergeSections() { llvm::TimeTraceScope timeScope("Merge sections"); if (!pdataSec->chunks.empty()) { - pdata.first = pdataSec->chunks.front(); - pdata.last = pdataSec->chunks.back(); + if (isArm64EC(ctx.config.machine)) { + // On ARM64EC .pdata may contain both ARM64 and X64 data. Split them by + // sorting and store their regions separately. + llvm::stable_sort(pdataSec->chunks, [=](const Chunk *a, const Chunk *b) { + return (a->getMachine() == AMD64) < (b->getMachine() == AMD64); + }); + + for (auto chunk : pdataSec->chunks) { + if (chunk->getMachine() == AMD64) { + hybridPdata.first = chunk; + hybridPdata.last = pdataSec->chunks.back(); + break; + } + + if (!pdata.first) + pdata.first = chunk; + pdata.last = chunk; + } + } else { + pdata.first = pdataSec->chunks.front(); + pdata.last = pdataSec->chunks.back(); + } } for (auto &p : ctx.config.merge) { @@ -1668,10 +1696,15 @@ template void Writer::writeHeader() { dir[RESOURCE_TABLE].RelativeVirtualAddress = rsrcSec->getRVA(); dir[RESOURCE_TABLE].Size = rsrcSec->getVirtualSize(); } - if (pdata.first) { - dir[EXCEPTION_TABLE].RelativeVirtualAddress = pdata.first->getRVA(); - dir[EXCEPTION_TABLE].Size = - pdata.last->getRVA() + pdata.last->getSize() - pdata.first->getRVA(); + // ARM64EC (but not ARM64X) contains x86_64 exception table in data directory. + ChunkRange &exceptionTable = + ctx.config.machine == ARM64EC ? hybridPdata : pdata; + if (exceptionTable.first) { + dir[EXCEPTION_TABLE].RelativeVirtualAddress = + exceptionTable.first->getRVA(); + dir[EXCEPTION_TABLE].Size = exceptionTable.last->getRVA() + + exceptionTable.last->getSize() - + exceptionTable.first->getRVA(); } if (relocSec->getVirtualSize()) { dir[BASE_RELOCATION_TABLE].RelativeVirtualAddress = relocSec->getRVA(); @@ -2084,6 +2117,24 @@ void Writer::setSectionPermissions() { } } +// Set symbols used by ARM64EC metadata. +void Writer::setECSymbols() { + if (!isArm64EC(ctx.config.machine)) + return; + + Symbol *rfeTableSym = ctx.symtab.findUnderscore("__arm64x_extra_rfe_table"); + replaceSymbol(rfeTableSym, "__arm64x_extra_rfe_table", + pdata.first); + + if (pdata.first) { + Symbol *rfeSizeSym = + ctx.symtab.findUnderscore("__arm64x_extra_rfe_table_size"); + cast(rfeSizeSym) + ->setVA(pdata.last->getRVA() + pdata.last->getSize() - + pdata.first->getRVA()); + } +} + // Write section contents to a mmap'ed file. void Writer::writeSections() { llvm::TimeTraceScope timeScope("Write sections"); @@ -2122,8 +2173,8 @@ void Writer::writeBuildId() { // For reproducibility, instead of a timestamp we want to use a hash of the // PE contents. Configuration *config = &ctx.config; - - if (config->debug) { + bool generateSyntheticBuildId = config->buildIDHash == BuildIDHash::Binary; + if (generateSyntheticBuildId) { assert(buildId && "BuildId is not set!"); // BuildId->BuildId was filled in when the PDB was written. } @@ -2138,8 +2189,6 @@ void Writer::writeBuildId() { uint32_t timestamp = config->timestamp; uint64_t hash = 0; - bool generateSyntheticBuildId = - config->mingw && config->debug && config->pdbPath.empty(); if (config->repro || generateSyntheticBuildId) hash = xxh3_64bits(outputFileData); @@ -2148,8 +2197,6 @@ void Writer::writeBuildId() { timestamp = static_cast(hash); if (generateSyntheticBuildId) { - // For MinGW builds without a PDB file, we still generate a build id - // to allow associating a crash dump to the executable. buildId->buildId->PDB70.CVSignature = OMF::Signature::PDB70; buildId->buildId->PDB70.Age = 1; memcpy(buildId->buildId->PDB70.Signature, &hash, 8); @@ -2206,6 +2253,10 @@ void Writer::sortExceptionTables() { case AMD64: sortExceptionTable(pdata); break; + case ARM64EC: + case ARM64X: + sortExceptionTable(hybridPdata); + [[fallthrough]]; case ARMNT: case ARM64: sortExceptionTable(pdata); diff --git a/lld/MinGW/Driver.cpp b/lld/MinGW/Driver.cpp index 19bf2d161705..d22b617cf2f0 100644 --- a/lld/MinGW/Driver.cpp +++ b/lld/MinGW/Driver.cpp @@ -302,6 +302,21 @@ bool link(ArrayRef argsArr, llvm::raw_ostream &stdoutOS, } else if (!args.hasArg(OPT_strip_all)) { add("-debug:dwarf"); } + if (auto *a = args.getLastArg(OPT_build_id)) { + StringRef v = a->getValue(); + if (v == "none") + add("-build-id:no"); + else { + if (!v.empty()) + warn("unsupported build id hashing: " + v + ", using default hashing."); + add("-build-id"); + } + } else { + if (args.hasArg(OPT_strip_debug) || args.hasArg(OPT_strip_all)) + add("-build-id:no"); + else + add("-build-id"); + } if (args.hasFlag(OPT_fatal_warnings, OPT_no_fatal_warnings, false)) add("-WX"); diff --git a/lld/MinGW/Options.td b/lld/MinGW/Options.td index fa4c4ecc75d6..d4a49cdbd535 100644 --- a/lld/MinGW/Options.td +++ b/lld/MinGW/Options.td @@ -196,6 +196,9 @@ defm guard_longjmp : B<"guard-longjmp", "Do not enable Control Flow Guard long jump hardening">; defm error_limit: EqLong<"error-limit", "Maximum number of errors to emit before stopping (0 = no limit)">; +def build_id: J<"build-id=">, HelpText<"Generate build ID note (pass none to disable)">, + MetaVarName<"">; +def : F<"build-id">, Alias, HelpText<"Alias for --build-id=">; // Alias def alias_Bdynamic_call_shared: Flag<["-"], "call_shared">, Alias; @@ -213,7 +216,6 @@ def alias_undefined_u: JoinedOrSeparate<["-"], "u">, Alias; // Ignored options def: Joined<["-"], "O">; def: F<"as-needed">; -def: F<"build-id">; def: F<"disable-auto-image-base">; def: F<"enable-auto-image-base">; def: F<"end-group">; diff --git a/lld/test/COFF/Inputs/loadconfig-arm64ec.s b/lld/test/COFF/Inputs/loadconfig-arm64ec.s index 78ae594a21ef..8bb5ccfed8eb 100644 --- a/lld/test/COFF/Inputs/loadconfig-arm64ec.s +++ b/lld/test/COFF/Inputs/loadconfig-arm64ec.s @@ -79,8 +79,8 @@ __chpe_metadata: .word 0 // __arm64x_redirection_metadata_count .rva __os_arm64x_get_x64_information .rva __os_arm64x_set_x64_information - .word 0 // __arm64x_extra_rfe_table - .word 0 // __arm64x_extra_rfe_table_size + .rva __arm64x_extra_rfe_table + .word __arm64x_extra_rfe_table_size .rva __os_arm64x_dispatch_fptr .word 0 // __hybrid_auxiliary_iat_copy .rva __os_arm64x_helper0 diff --git a/lld/test/COFF/debug-reloc.s b/lld/test/COFF/debug-reloc.s index bdf256315654..68992414bd97 100644 --- a/lld/test/COFF/debug-reloc.s +++ b/lld/test/COFF/debug-reloc.s @@ -2,7 +2,7 @@ # RUN: llvm-mc -triple=x86_64-windows-gnu %s -filetype=obj -o %t.obj -# RUN: lld-link -lldmingw -debug:dwarf -out:%t.exe -entry:mainfunc -subsystem:console %t.obj +# RUN: lld-link -lldmingw -debug:dwarf -build-id -out:%t.exe -entry:mainfunc -subsystem:console %t.obj # RUN: llvm-readobj --sections %t.exe | FileCheck %s -check-prefix SECTIONS # RUN: llvm-readobj --coff-basereloc %t.exe | FileCheck %s -check-prefix RELOCS # RUN: llvm-readobj --file-headers %t.exe | FileCheck %s -check-prefix HEADERS diff --git a/lld/test/COFF/lto-imp-prefix.ll b/lld/test/COFF/lto-imp-prefix.ll index 56a7c48cc9d1..d617a6ef5810 100644 --- a/lld/test/COFF/lto-imp-prefix.ll +++ b/lld/test/COFF/lto-imp-prefix.ll @@ -8,13 +8,9 @@ ; RUN: lld-link /entry:entry %t.main.obj %t.other1.obj /out:%t1.exe /subsystem:console /debug:symtab -;; The current implementation for handling __imp_ symbols retains all of them. -;; Observe that this currently produces __imp_unusedFunc even if nothing -;; references unusedFunc in any form. - +;; Check that we don't retain __imp_ prefixed symbols we don't need. ; RUN: llvm-nm %t1.exe | FileCheck %s - -; CHECK: __imp_unusedFunc +; CHECK-NOT: __imp_unusedFunc ; RUN: lld-link /entry:entry %t.main.obj %t.other2.obj /out:%t2.exe /subsystem:console diff --git a/lld/test/COFF/pdata-arm64ec.test b/lld/test/COFF/pdata-arm64ec.test new file mode 100644 index 000000000000..7f20c460dc10 --- /dev/null +++ b/lld/test/COFF/pdata-arm64ec.test @@ -0,0 +1,132 @@ +REQUIRES: aarch64, x86 +RUN: split-file %s %t.dir && cd %t.dir + +Test handlign of hybrid .pdata section on ARM64EC target. + +RUN: llvm-mc -filetype=obj -triple=arm64-windows arm64-func-sym.s -o arm64-func-sym.obj +RUN: llvm-mc -filetype=obj -triple=arm64ec-windows arm64ec-func-sym.s -o arm64ec-func-sym.obj +RUN: llvm-mc -filetype=obj -triple=x86_64-windows x86_64-func-sym.s -o x86_64-func-sym.obj +RUN: llvm-mc -filetype=obj -triple=arm64ec-windows %p/Inputs/loadconfig-arm64ec.s -o loadconfig-arm64ec.obj + +Only arm64ec code: + +RUN: lld-link -out:test1.dll -machine:arm64ec arm64ec-func-sym.obj loadconfig-arm64ec.obj -dll -noentry + +RUN: llvm-readobj --coff-load-config test1.dll | FileCheck -check-prefix=LOADCFG %s +LOADCFG: ExtraRFETable: 0x4000 +LOADCFG-NEXT: ExtraRFETableSize: 0x8 + +RUN: llvm-readobj --headers test1.dll | FileCheck -check-prefix=NODIR %s +NODIR: ExceptionTableSize: 0x0 + +RUN: llvm-objdump -s --section=.pdata test1.dll | FileCheck -check-prefix=DATA %s +DATA: 180004000 00100000 11000001 + +Only x86_64 code: + +RUN: lld-link -out:test2.dll -machine:arm64ec x86_64-func-sym.obj loadconfig-arm64ec.obj -dll -noentry + +RUN: llvm-readobj --coff-load-config test2.dll | FileCheck -check-prefix=NOLOADCFG %s +NOLOADCFG: ExtraRFETableSize: 0x0 + +RUN: llvm-readobj --headers test2.dll | FileCheck -check-prefix=DIR %s +DIR: ExceptionTableRVA: 0x4000 +DIR-NEXT: ExceptionTableSize: 0xC + +RUN: llvm-objdump -s --section=.pdata test2.dll | FileCheck -check-prefix=DATA2 %s +DATA2: 180004000 00100000 0e100000 + +Mixed arm64ec and x86_64 code: + +RUN: lld-link -out:test3.dll -machine:arm64ec arm64ec-func-sym.obj x86_64-func-sym.obj \ +RUN: loadconfig-arm64ec.obj -dll -noentry + +RUN: llvm-readobj --coff-load-config test3.dll | FileCheck -check-prefix=LOADCFG2 %s +LOADCFG2: ExtraRFETable: 0x5000 +LOADCFG2-NEXT: ExtraRFETableSize: 0x8 + +RUN: llvm-readobj --headers test3.dll | FileCheck -check-prefix=DIR2 %s +DIR2: ExceptionTableRVA: 0x5008 +DIR2-NEXT: ExceptionTableSize: 0xC + +RUN: llvm-objdump -s --section=.pdata test3.dll | FileCheck -check-prefix=DATA3 %s +DATA3: 180005000 00100000 11000001 00200000 0e200000 + +Mixed arm64x code: + +RUN: lld-link -out:test4.dll -machine:arm64x arm64-func-sym.obj arm64ec-func-sym.obj \ +RUN: x86_64-func-sym.obj loadconfig-arm64ec.obj -dll -noentry + +RUN: llvm-readobj --headers test4.dll | FileCheck -check-prefix=DIR3 %s +DIR3: ExceptionTableRVA: 0x6000 +DIR3-NEXT: ExceptionTableSize: 0x10 + +RUN: llvm-objdump -s --section=.pdata test4.dll | FileCheck -check-prefix=DATA4 %s +DATA4: 180006000 00100000 11000001 00200000 11000001 ......... ...... +DATA4: 180006010 00300000 0e300000 + +Order of inputs doesn't matter, the data is sorted by type and RVA: + +RUN: lld-link -out:test5.dll -machine:arm64ec x86_64-func-sym.obj arm64ec-func-sym.obj \ +RUN: loadconfig-arm64ec.obj -dll -noentry +RUN: llvm-readobj --coff-load-config test5.dll | FileCheck -check-prefix=LOADCFG2 %s +RUN: llvm-readobj --headers test5.dll | FileCheck -check-prefix=DIR2 %s +RUN: llvm-objdump -s --section=.pdata test5.dll | FileCheck -check-prefix=DATA3 %s + +RUN: lld-link -out:test6.dll -machine:arm64x arm64ec-func-sym.obj x86_64-func-sym.obj \ +RUN: arm64-func-sym.obj loadconfig-arm64ec.obj -dll -noentry +RUN: llvm-readobj --headers test6.dll | FileCheck -check-prefix=DIR3 %s +RUN: llvm-objdump -s --section=.pdata test6.dll | FileCheck -check-prefix=DATA4 %s + +RUN: lld-link -out:test7.dll -machine:arm64x x86_64-func-sym.obj arm64ec-func-sym.obj \ +RUN: arm64-func-sym.obj loadconfig-arm64ec.obj -dll -noentry +RUN: llvm-readobj --headers test7.dll | FileCheck -check-prefix=DIR3 %s +RUN: llvm-objdump -s --section=.pdata test7.dll | FileCheck -check-prefix=DATA4 %s + +#--- arm64-func-sym.s + .text + .globl arm64_func_sym + .p2align 2, 0x0 +arm64_func_sym: + .seh_proc arm64_func_sym + sub sp, sp, #32 + .seh_stackalloc 32 + .seh_endprologue + mov w0, #2 + .seh_startepilogue + add sp, sp, #32 + .seh_stackalloc 32 + .seh_endepilogue + ret + .seh_endproc + +#--- arm64ec-func-sym.s + .text + .globl arm64ec_func_sym + .p2align 2, 0x0 +arm64ec_func_sym: + .seh_proc arm64ec_func_sym + sub sp, sp, #32 + .seh_stackalloc 32 + .seh_endprologue + mov w0, #3 + .seh_startepilogue + add sp, sp, #32 + .seh_stackalloc 32 + .seh_endepilogue + ret + .seh_endproc + +#--- x86_64-func-sym.s + .text + .globl x86_64_func_sym + .p2align 2, 0x0 +x86_64_func_sym: + .seh_proc x86_64_func_sym + subq $40, %rsp + .seh_stackalloc 40 + .seh_endprologue + movl $4, %eax + addq $40, %rsp + retq + .seh_endproc diff --git a/lld/test/COFF/rsds.test b/lld/test/COFF/rsds.test index 475249ca4056..3b611c091e2e 100644 --- a/lld/test/COFF/rsds.test +++ b/lld/test/COFF/rsds.test @@ -22,9 +22,30 @@ # RUN: lld-link /Brepro /debug /dll /out:%t.dll /entry:DllMain %t.obj # RUN: llvm-readobj --coff-debug-directory %t.dll | FileCheck --check-prefix REPRODEBUG %s +# Generate .buildid section using binary hash under /lldmingw and /build-id # RUN: rm -f %t.dll %t.pdb -# RUN: lld-link /lldmingw /debug:dwarf /dll /out:%t.dll /entry:DllMain %t.obj -# RUN: llvm-readobj --coff-debug-directory %t.dll | FileCheck --check-prefix MINGW %s +# RUN: lld-link /lldmingw /build-id /dll /out:%t.dll /entry:DllMain %t.obj +# RUN: llvm-readobj --coff-debug-directory %t.dll | FileCheck --check-prefix BUILDID %s + +# Generate debug directory with use binary hash when /build-id is given and not +# generating PDB. +# RUN: rm -f %t.dll %t.pdb +# RUN: lld-link /build-id /dll /out:%t.dll /entry:DllMain %t.obj +# RUN: llvm-readobj --coff-debug-directory %t.dll | FileCheck --check-prefix BUILDID %s + +# If generate PDB, PDB hash is used and /build-id is ignored. +# RUN: rm -f %t.dll %t.pdb +# RUN: lld-link /build-id /debug /pdbaltpath:test.pdb /dll /out:%t.dll /entry:DllMain %t.obj +# RUN: llvm-readobj --coff-debug-directory %t.dll | FileCheck --check-prefix BUILDID %s + +# Do not generate .buildid section under /build-id:no +# RUN: rm -f %t.dll %t.pdb +# RUN: lld-link /build-id:no /dll /out:%t.dll /entry:DllMain %t.obj +# RUN: llvm-readobj --coff-debug-directory %t.dll | FileCheck --check-prefix NO_BUILDID %s + +# RUN: rm -f %t.dll %t.pdb +# RUN: lld-link /dll /out:%t.dll /entry:DllMain %t.obj +# RUN: llvm-readobj --coff-debug-directory %t.dll | FileCheck --check-prefix NO_BUILDID %s # CHECK: File: [[FILE:.*]].dll # CHECK: DebugDirectory [ @@ -148,25 +169,30 @@ # REPRODEBUG: } # REPRODEBUG: ] -# MINGW: File: {{.*}}.dll -# MINGW: DebugDirectory [ -# MINGW: DebugEntry { -# MINGW: Characteristics: 0x0 -# MINGW: TimeDateStamp: -# MINGW: MajorVersion: 0x0 -# MINGW: MinorVersion: 0x0 -# MINGW: Type: CodeView (0x2) -# MINGW: SizeOfData: 0x{{[^0]}} -# MINGW: AddressOfRawData: 0x{{[^0]}} -# MINGW: PointerToRawData: 0x{{[^0]}} -# MINGW: PDBInfo { -# MINGW: PDBSignature: 0x53445352 -# MINGW: PDBGUID: [[GUID:\(([A-Za-z0-9]{2} ?){16}\)]] -# MINGW: PDBAge: 1 -# MINGW: PDBFileName: -# MINGW: } -# MINGW: } -# MINGW: ] +# BUILDID: File: {{.*}}.dll +# BUILDID: DebugDirectory [ +# BUILDID: DebugEntry { +# BUILDID: Characteristics: 0x0 +# BUILDID: TimeDateStamp: +# BUILDID: MajorVersion: 0x0 +# BUILDID: MinorVersion: 0x0 +# BUILDID: Type: CodeView (0x2) +# BUILDID: SizeOfData: 0x{{[^0]}} +# BUILDID: AddressOfRawData: 0x{{[^0]}} +# BUILDID: PointerToRawData: 0x{{[^0]}} +# BUILDID: PDBInfo { +# BUILDID: PDBSignature: 0x53445352 +# BUILDID: PDBGUID: [[GUID:\(([A-Za-z0-9]{2} ?){16}\)]] +# BUILDID: PDBAge: 1 +# BUILDID: PDBFileName: +# BUILDID: } +# BUILDID: } +# BUILDID: ] + +# NO_BUILDID: DebugDirectory [ +# NO_BUILDID-NEXT: ] + +# BUILDID_SEC: Name: .buildid --- !COFF header: Machine: IMAGE_FILE_MACHINE_I386 diff --git a/lld/test/MinGW/driver.test b/lld/test/MinGW/driver.test index a07c95edb580..d08c64258be8 100644 --- a/lld/test/MinGW/driver.test +++ b/lld/test/MinGW/driver.test @@ -389,3 +389,16 @@ Test GCC specific LTO options that GCC passes unconditionally, that we ignore. RUN: ld.lld -### foo.o -m i386pep -plugin /usr/lib/gcc/x86_64-w64-mingw32/10-posix/liblto_plugin.so -plugin-opt=/usr/lib/gcc/x86_64-w64-mingw32/10-posix/lto-wrapper -plugin-opt=-fresolution=/tmp/ccM9d4fP.res -plugin-opt=-pass-through=-lmingw32 2> /dev/null RUN: ld.lld -### foo.o -m i386pep -plugin C:/msys64/mingw64/bin/../lib/gcc/x86_64-w64-mingw32/13.2.0/liblto_plugin.dll -plugin-opt=C:/msys64/mingw64/bin/../lib/gcc/x86_64-w64-mingw32/13.2.0/lto-wrapper.exe -plugin-opt=-fresolution=C:/msys64/tmp/cckbC7wB.res -plugin-opt=-pass-through=-lmingw32 2> /dev/null + +RUN: ld.lld -### foo.o -m i386pep 2>&1 | FileCheck -check-prefix=BUILD_ID %s +RUN: ld.lld -### foo.o -m i386pep --build-id 2>&1 | FileCheck -check-prefix=BUILD_ID %s +BUILD_ID: -build-id{{ }} + +RUN: ld.lld -### foo.o -m i386pep --build-id=fast 2>&1 | FileCheck -check-prefix=BUILD_ID_WARN %s +BUILD_ID_WARN: unsupported build id hashing: fast, using default hashing. +BUILD_ID_WARN: -build-id{{ }} + +RUN: ld.lld -### foo.o -m i386pep --build-id=none 2>&1 | FileCheck -check-prefix=NO_BUILD_ID %s +RUN: ld.lld -### foo.o -m i386pep -s 2>&1 | FileCheck -check-prefix=NO_BUILD_ID %s +RUN: ld.lld -### foo.o -m i386pep -S 2>&1 | FileCheck -check-prefix=NO_BUILD_ID %s +NO_BUILD_ID: -build-id:no diff --git a/lldb/include/lldb/Core/PluginManager.h b/lldb/include/lldb/Core/PluginManager.h index 318f8b63c251..f2296e292023 100644 --- a/lldb/include/lldb/Core/PluginManager.h +++ b/lldb/include/lldb/Core/PluginManager.h @@ -355,7 +355,8 @@ public: nullptr, SymbolLocatorDownloadObjectAndSymbolFile download_object_symbol_file = nullptr, - SymbolLocatorFindSymbolFileInBundle find_symbol_file_in_bundle = nullptr); + SymbolLocatorFindSymbolFileInBundle find_symbol_file_in_bundle = nullptr, + DebuggerInitializeCallback debugger_init_callback = nullptr); static bool UnregisterPlugin(SymbolLocatorCreateInstance create_callback); @@ -528,6 +529,14 @@ public: Debugger &debugger, const lldb::OptionValuePropertiesSP &properties_sp, llvm::StringRef description, bool is_global_property); + static lldb::OptionValuePropertiesSP + GetSettingForSymbolLocatorPlugin(Debugger &debugger, + llvm::StringRef setting_name); + + static bool CreateSettingForSymbolLocatorPlugin( + Debugger &debugger, const lldb::OptionValuePropertiesSP &properties_sp, + llvm::StringRef description, bool is_global_property); + static bool CreateSettingForTracePlugin( Debugger &debugger, const lldb::OptionValuePropertiesSP &properties_sp, llvm::StringRef description, bool is_global_property); diff --git a/lldb/include/lldb/Expression/DiagnosticManager.h b/lldb/include/lldb/Expression/DiagnosticManager.h index df9ba3b245f5..06bf1d115f15 100644 --- a/lldb/include/lldb/Expression/DiagnosticManager.h +++ b/lldb/include/lldb/Expression/DiagnosticManager.h @@ -118,6 +118,15 @@ public: m_diagnostics.push_back(std::move(diagnostic)); } + /// Moves over the contents of a second diagnostic manager over. Leaves other + /// diagnostic manager in an empty state. + void Consume(DiagnosticManager &&other) { + std::move(other.m_diagnostics.begin(), other.m_diagnostics.end(), + std::back_inserter(m_diagnostics)); + m_fixed_expression = std::move(other.m_fixed_expression); + other.Clear(); + } + size_t Printf(DiagnosticSeverity severity, const char *format, ...) __attribute__((format(printf, 3, 4))); void PutString(DiagnosticSeverity severity, llvm::StringRef str); diff --git a/lldb/include/lldb/Host/netbsd/HostInfoNetBSD.h b/lldb/include/lldb/Host/netbsd/HostInfoNetBSD.h index 01daefaedbad..d41be8124296 100644 --- a/lldb/include/lldb/Host/netbsd/HostInfoNetBSD.h +++ b/lldb/include/lldb/Host/netbsd/HostInfoNetBSD.h @@ -1,4 +1,4 @@ -//===-- HostInfoNetBSD.h ---------------------------------------*- C++ -*-===// +//===-- HostInfoNetBSD.h ----------------------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/lldb/source/Core/CoreProperties.td b/lldb/source/Core/CoreProperties.td index 92884258347e..0e0f468d3ecd 100644 --- a/lldb/source/Core/CoreProperties.td +++ b/lldb/source/Core/CoreProperties.td @@ -4,7 +4,7 @@ let Definition = "modulelist" in { def EnableExternalLookup: Property<"enable-external-lookup", "Boolean">, Global, DefaultTrue, - Desc<"Control the use of external tools and repositories to locate symbol files. Directories listed in target.debug-file-search-paths and directory of the executable are always checked first for separate debug info files. Then depending on this setting: On macOS, Spotlight would be also used to locate a matching .dSYM bundle based on the UUID of the executable. On NetBSD, directory /usr/libdata/debug would be also searched. On platforms other than NetBSD directory /usr/lib/debug would be also searched.">; + Desc<"Control the use of external tools and repositories to locate symbol files. Directories listed in target.debug-file-search-paths and directory of the executable are always checked first for separate debug info files. Then depending on this setting: On macOS, Spotlight would be also used to locate a matching .dSYM bundle based on the UUID of the executable. On NetBSD, directory /usr/libdata/debug would be also searched. On platforms other than NetBSD directory /usr/lib/debug would be also searched. If all other methods fail there may be symbol-locator plugins that, if configured properly, will also attempt to acquire symbols. The debuginfod plugin defaults to the DEGUFINFOD_URLS environment variable which is configurable through the 'plugin.symbol-locator.debuginfod.server_urls' setting.">; def EnableBackgroundLookup: Property<"enable-background-lookup", "Boolean">, Global, DefaultFalse, diff --git a/lldb/source/Core/FormatEntity.cpp b/lldb/source/Core/FormatEntity.cpp index d8047b424206..94986457552d 100644 --- a/lldb/source/Core/FormatEntity.cpp +++ b/lldb/source/Core/FormatEntity.cpp @@ -1245,9 +1245,10 @@ bool FormatEntity::Format(const Entry &entry, Stream &s, llvm::Triple::OSType ostype = arch.IsValid() ? arch.GetTriple().getOS() : llvm::Triple::UnknownOS; - if ((ostype == llvm::Triple::FreeBSD) || - (ostype == llvm::Triple::Linux) || - (ostype == llvm::Triple::NetBSD)) { + if (ostype == llvm::Triple::FreeBSD || + ostype == llvm::Triple::Linux || + ostype == llvm::Triple::NetBSD || + ostype == llvm::Triple::OpenBSD) { format = "%" PRIu64; } } else { diff --git a/lldb/source/Core/PluginManager.cpp b/lldb/source/Core/PluginManager.cpp index 23c06357e2f9..dea380e47f4e 100644 --- a/lldb/source/Core/PluginManager.cpp +++ b/lldb/source/Core/PluginManager.cpp @@ -1091,9 +1091,10 @@ struct SymbolLocatorInstance SymbolLocatorLocateExecutableObjectFile locate_executable_object_file, SymbolLocatorLocateExecutableSymbolFile locate_executable_symbol_file, SymbolLocatorDownloadObjectAndSymbolFile download_object_symbol_file, - SymbolLocatorFindSymbolFileInBundle find_symbol_file_in_bundle) - : PluginInstance(name, description, - create_callback), + SymbolLocatorFindSymbolFileInBundle find_symbol_file_in_bundle, + DebuggerInitializeCallback debugger_init_callback) + : PluginInstance( + name, description, create_callback, debugger_init_callback), locate_executable_object_file(locate_executable_object_file), locate_executable_symbol_file(locate_executable_symbol_file), download_object_symbol_file(download_object_symbol_file), @@ -1117,11 +1118,12 @@ bool PluginManager::RegisterPlugin( SymbolLocatorLocateExecutableObjectFile locate_executable_object_file, SymbolLocatorLocateExecutableSymbolFile locate_executable_symbol_file, SymbolLocatorDownloadObjectAndSymbolFile download_object_symbol_file, - SymbolLocatorFindSymbolFileInBundle find_symbol_file_in_bundle) { + SymbolLocatorFindSymbolFileInBundle find_symbol_file_in_bundle, + DebuggerInitializeCallback debugger_init_callback) { return GetSymbolLocatorInstances().RegisterPlugin( name, description, create_callback, locate_executable_object_file, locate_executable_symbol_file, download_object_symbol_file, - find_symbol_file_in_bundle); + find_symbol_file_in_bundle, debugger_init_callback); } bool PluginManager::UnregisterPlugin( @@ -1533,6 +1535,7 @@ void PluginManager::DebuggerInitialize(Debugger &debugger) { GetPlatformInstances().PerformDebuggerCallback(debugger); GetProcessInstances().PerformDebuggerCallback(debugger); GetSymbolFileInstances().PerformDebuggerCallback(debugger); + GetSymbolLocatorInstances().PerformDebuggerCallback(debugger); GetOperatingSystemInstances().PerformDebuggerCallback(debugger); GetStructuredDataPluginInstances().PerformDebuggerCallback(debugger); GetTracePluginInstances().PerformDebuggerCallback(debugger); @@ -1660,6 +1663,7 @@ static constexpr llvm::StringLiteral kProcessPluginName("process"); static constexpr llvm::StringLiteral kTracePluginName("trace"); static constexpr llvm::StringLiteral kObjectFilePluginName("object-file"); static constexpr llvm::StringLiteral kSymbolFilePluginName("symbol-file"); +static constexpr llvm::StringLiteral kSymbolLocatorPluginName("symbol-locator"); static constexpr llvm::StringLiteral kJITLoaderPluginName("jit-loader"); static constexpr llvm::StringLiteral kStructuredDataPluginName("structured-data"); @@ -1708,6 +1712,20 @@ bool PluginManager::CreateSettingForProcessPlugin( description, is_global_property); } +lldb::OptionValuePropertiesSP +PluginManager::GetSettingForSymbolLocatorPlugin(Debugger &debugger, + llvm::StringRef setting_name) { + return GetSettingForPlugin(debugger, setting_name, kSymbolLocatorPluginName); +} + +bool PluginManager::CreateSettingForSymbolLocatorPlugin( + Debugger &debugger, const lldb::OptionValuePropertiesSP &properties_sp, + llvm::StringRef description, bool is_global_property) { + return CreateSettingForPlugin(debugger, kSymbolLocatorPluginName, + "Settings for symbol locator plug-ins", + properties_sp, description, is_global_property); +} + bool PluginManager::CreateSettingForTracePlugin( Debugger &debugger, const lldb::OptionValuePropertiesSP &properties_sp, llvm::StringRef description, bool is_global_property) { diff --git a/lldb/source/Host/common/SocketAddress.cpp b/lldb/source/Host/common/SocketAddress.cpp index 3f47d32d4652..6a23c633e54b 100644 --- a/lldb/source/Host/common/SocketAddress.cpp +++ b/lldb/source/Host/common/SocketAddress.cpp @@ -113,7 +113,8 @@ static socklen_t GetFamilyLength(sa_family_t family) { } socklen_t SocketAddress::GetLength() const { -#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__NetBSD__) +#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__NetBSD__) || \ + defined(__OpenBSD__) return m_socket_addr.sa.sa_len; #else return GetFamilyLength(GetFamily()); @@ -128,7 +129,8 @@ sa_family_t SocketAddress::GetFamily() const { void SocketAddress::SetFamily(sa_family_t family) { m_socket_addr.sa.sa_family = family; -#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__NetBSD__) +#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__NetBSD__) || \ + defined(__OpenBSD__) m_socket_addr.sa.sa_len = GetFamilyLength(family); #endif } diff --git a/lldb/source/Host/netbsd/HostInfoNetBSD.cpp b/lldb/source/Host/netbsd/HostInfoNetBSD.cpp index 0de4f2530bba..6a4aacc88f1e 100644 --- a/lldb/source/Host/netbsd/HostInfoNetBSD.cpp +++ b/lldb/source/Host/netbsd/HostInfoNetBSD.cpp @@ -45,7 +45,6 @@ llvm::VersionTuple HostInfoNetBSD::GetOSVersion() { std::optional HostInfoNetBSD::GetOSBuildString() { int mib[2] = {CTL_KERN, KERN_OSREV}; - char osrev_str[12]; int osrev = 0; size_t osrev_len = sizeof(osrev); diff --git a/lldb/source/Host/openbsd/HostInfoOpenBSD.cpp b/lldb/source/Host/openbsd/HostInfoOpenBSD.cpp index 43f22be51ef9..b30c7a83243c 100644 --- a/lldb/source/Host/openbsd/HostInfoOpenBSD.cpp +++ b/lldb/source/Host/openbsd/HostInfoOpenBSD.cpp @@ -20,19 +20,23 @@ using namespace lldb_private; llvm::VersionTuple HostInfoOpenBSD::GetOSVersion() { struct utsname un; - ::memset(&un, 0, sizeof(utsname)); - if (uname(&un) < 0) + ::memset(&un, 0, sizeof(un)); + if (::uname(&un) < 0) return llvm::VersionTuple(); - unsigned major, minor; - if (2 == sscanf(un.release, "%u.%u", &major, &minor)) + uint32_t major, minor; + int status = ::sscanf(un.release, "%" PRIu32 ".%" PRIu32, &major, &minor); + switch (status) { + case 1: + return llvm::VersionTuple(major); + case 2: return llvm::VersionTuple(major, minor); + } return llvm::VersionTuple(); } std::optional HostInfoOpenBSD::GetOSBuildString() { int mib[2] = {CTL_KERN, KERN_OSREV}; - char osrev_str[12]; uint32_t osrev = 0; size_t osrev_len = sizeof(osrev); diff --git a/lldb/source/Host/posix/DomainSocket.cpp b/lldb/source/Host/posix/DomainSocket.cpp index ddbd983abb81..9b44c2a8368e 100644 --- a/lldb/source/Host/posix/DomainSocket.cpp +++ b/lldb/source/Host/posix/DomainSocket.cpp @@ -48,7 +48,8 @@ static bool SetSockAddr(llvm::StringRef name, const size_t name_offset, saddr_un_len = offsetof(struct sockaddr_un, sun_path) + name_offset + name.size(); -#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__NetBSD__) +#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__NetBSD__) || \ + defined(__OpenBSD__) saddr_un->sun_len = saddr_un_len; #endif diff --git a/lldb/source/Initialization/SystemInitializerCommon.cpp b/lldb/source/Initialization/SystemInitializerCommon.cpp index 40e54cd7f0e0..1a172a95aa14 100644 --- a/lldb/source/Initialization/SystemInitializerCommon.cpp +++ b/lldb/source/Initialization/SystemInitializerCommon.cpp @@ -18,7 +18,8 @@ #include "lldb/Utility/Timer.h" #include "lldb/Version/Version.h" -#if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) +#if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || \ + defined(__OpenBSD__) #include "Plugins/Process/POSIX/ProcessPOSIXLog.h" #endif @@ -77,7 +78,8 @@ llvm::Error SystemInitializerCommon::Initialize() { process_gdb_remote::ProcessGDBRemoteLog::Initialize(); -#if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) +#if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || \ + defined(__OpenBSD__) ProcessPOSIXLog::Initialize(); #endif #if defined(_WIN32) diff --git a/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DYLDRendezvous.cpp b/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DYLDRendezvous.cpp index a0b6f44bed0e..1a9c4593b1b4 100644 --- a/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DYLDRendezvous.cpp +++ b/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DYLDRendezvous.cpp @@ -549,6 +549,7 @@ bool DYLDRendezvous::SOEntryIsMainExecutable(const SOEntry &entry) { switch (triple.getOS()) { case llvm::Triple::FreeBSD: case llvm::Triple::NetBSD: + case llvm::Triple::OpenBSD: return entry.file_spec == m_exe_file_spec; case llvm::Triple::Linux: if (triple.isAndroid()) diff --git a/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp b/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp index 3d65f4967420..9baf86da4dc7 100644 --- a/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp +++ b/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp @@ -53,7 +53,8 @@ DynamicLoader *DynamicLoaderPOSIXDYLD::CreateInstance(Process *process, process->GetTarget().GetArchitecture().GetTriple(); if (triple_ref.getOS() == llvm::Triple::FreeBSD || triple_ref.getOS() == llvm::Triple::Linux || - triple_ref.getOS() == llvm::Triple::NetBSD) + triple_ref.getOS() == llvm::Triple::NetBSD || + triple_ref.getOS() == llvm::Triple::OpenBSD) create = true; } diff --git a/lldb/source/Plugins/Process/Utility/NetBSDSignals.h b/lldb/source/Plugins/Process/Utility/NetBSDSignals.h index e6740a304a02..94bad7c19a49 100644 --- a/lldb/source/Plugins/Process/Utility/NetBSDSignals.h +++ b/lldb/source/Plugins/Process/Utility/NetBSDSignals.h @@ -1,4 +1,4 @@ -//===-- NetBSDSignals.h ----------------------------------------*- C++ -*-===// +//===-- NetBSDSignals.h -----------------------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextNetBSD_i386.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextNetBSD_i386.cpp index ba089190bd22..a160c87db6cf 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterContextNetBSD_i386.cpp +++ b/lldb/source/Plugins/Process/Utility/RegisterContextNetBSD_i386.cpp @@ -1,10 +1,10 @@ -//===-- RegisterContextNetBSD_i386.cpp -------------------------*- C++ -*-===// +//===-- RegisterContextNetBSD_i386.cpp --------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// #include "RegisterContextNetBSD_i386.h" #include "RegisterContextPOSIX_x86.h" diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextNetBSD_x86_64.h b/lldb/source/Plugins/Process/Utility/RegisterContextNetBSD_x86_64.h index b7b8d33b7c37..6f9787506013 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterContextNetBSD_x86_64.h +++ b/lldb/source/Plugins/Process/Utility/RegisterContextNetBSD_x86_64.h @@ -1,4 +1,4 @@ -//===-- RegisterContextNetBSD_x86_64.h -------------------------*- C++ -*-===// +//===-- RegisterContextNetBSD_x86_64.h --------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp index c3b22f889c2f..e3c64640c791 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp @@ -142,54 +142,6 @@ static bool ShouldIgnoreArtificialField(llvm::StringRef FieldName) { || FieldName.starts_with("_vptr."); } -std::optional -DWARFASTParserClang::FindConstantOnVariableDefinition(DWARFDIE die) { - assert(die.Tag() == DW_TAG_member || die.Tag() == DW_TAG_variable); - - auto *dwarf = die.GetDWARF(); - if (!dwarf) - return {}; - - ConstString name{die.GetName()}; - if (!name) - return {}; - - auto *CU = die.GetCU(); - if (!CU) - return {}; - - DWARFASTParser *dwarf_ast = dwarf->GetDWARFParser(*CU); - auto parent_decl_ctx = dwarf_ast->GetDeclContextContainingUIDFromDWARF(die); - - // Make sure we populate the GetDieToVariable cache. - VariableList variables; - dwarf->FindGlobalVariables(name, parent_decl_ctx, UINT_MAX, variables); - - // The cache contains the variable definition whose DW_AT_specification - // points to our declaration DIE. Look up that definition using our - // declaration. - auto const &die_to_var = dwarf->GetDIEToVariable(); - auto it = die_to_var.find(die.GetDIE()); - if (it == die_to_var.end()) - return {}; - - auto var_sp = it->getSecond(); - assert(var_sp != nullptr); - - if (!var_sp->GetLocationIsConstantValueData()) - return {}; - - auto def = dwarf->GetDIE(var_sp->GetID()); - auto def_attrs = def.GetAttributes(); - DWARFFormValue form_value; - if (!def_attrs.ExtractFormValueAtIndex( - def_attrs.FindAttributeIndex(llvm::dwarf::DW_AT_const_value), - form_value)) - return {}; - - return form_value; -} - TypeSP DWARFASTParserClang::ParseTypeFromClangModule(const SymbolContext &sc, const DWARFDIE &die, Log *log) { @@ -2916,23 +2868,11 @@ void DWARFASTParserClang::CreateStaticMemberVariable( bool unused; // TODO: Support float/double static members as well. - if (!ct.IsIntegerOrEnumerationType(unused)) + if (!ct.IsIntegerOrEnumerationType(unused) || !attrs.const_value_form) return; - auto maybe_const_form_value = attrs.const_value_form; - - // Newer versions of Clang don't emit the DW_AT_const_value - // on the declaration of an inline static data member. Instead - // it's attached to the definition DIE. If that's the case, - // try and fetch it. - if (!maybe_const_form_value) { - maybe_const_form_value = FindConstantOnVariableDefinition(die); - if (!maybe_const_form_value) - return; - } - llvm::Expected const_value_or_err = - ExtractIntFromFormValue(ct, *maybe_const_form_value); + ExtractIntFromFormValue(ct, *attrs.const_value_form); if (!const_value_or_err) { LLDB_LOG_ERROR(log, const_value_or_err.takeError(), "Failed to add const value to variable {1}: {0}", diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h index 7b495419cf32..3e28e54d6220 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h @@ -413,17 +413,6 @@ private: lldb_private::CompilerType &class_clang_type, const lldb::AccessType default_accesibility, lldb_private::ClangASTImporter::LayoutInfo &layout_info); - - /// Tries to find the definition DW_TAG_variable DIE of the the specified - /// DW_TAG_member 'die'. If such definition exists, returns the - /// DW_AT_const_value of that definition if available. Returns std::nullopt - /// otherwise. - /// - /// In newer versions of clang, DW_AT_const_value attributes are not attached - /// to the declaration of a inline static data-member anymore, but rather on - /// its definition. This function is used to locate said constant. - std::optional - FindConstantOnVariableDefinition(lldb_private::plugin::dwarf::DWARFDIE die); }; /// Parsed form of all attributes that are relevant for type reconstruction. diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp index b8b2eb58a8bd..d4cc26a3c329 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp @@ -3120,7 +3120,8 @@ SymbolFileDWARF::FindDefinitionTypeForDWARFDeclContext(const DWARFDIE &die) { template_params = dwarf_ast->GetDIEClassTemplateParams(die); } - m_index->GetTypes(GetDWARFDeclContext(die), [&](DWARFDIE type_die) { + const DWARFDeclContext die_dwarf_decl_ctx = GetDWARFDeclContext(die); + m_index->GetTypes(die_dwarf_decl_ctx, [&](DWARFDIE type_die) { // Make sure type_die's language matches the type system we are // looking for. We don't want to find a "Foo" type from Java if we // are looking for a "Foo" type for C, C++, ObjC, or ObjC++. @@ -3184,7 +3185,7 @@ SymbolFileDWARF::FindDefinitionTypeForDWARFDeclContext(const DWARFDIE &die) { } // Make sure the decl contexts match all the way up - if (GetDWARFDeclContext(die) != type_dwarf_decl_ctx) + if (die_dwarf_decl_ctx != type_dwarf_decl_ctx) return true; Type *resolved_type = ResolveType(type_die, false); @@ -4339,6 +4340,7 @@ const std::shared_ptr &SymbolFileDWARF::GetDwpSymbolFile() { module_spec.GetSymbolFileSpec() = FileSpec(m_objfile_sp->GetModule()->GetFileSpec().GetPath() + ".dwp"); + module_spec.GetUUID() = m_objfile_sp->GetUUID(); FileSpecList search_paths = Target::GetDefaultDebugFileSearchPaths(); FileSpec dwp_filespec = PluginManager::LocateExecutableSymbolFile(module_spec, search_paths); diff --git a/lldb/source/Plugins/SymbolLocator/CMakeLists.txt b/lldb/source/Plugins/SymbolLocator/CMakeLists.txt index 74abecd79694..ca969626f4ff 100644 --- a/lldb/source/Plugins/SymbolLocator/CMakeLists.txt +++ b/lldb/source/Plugins/SymbolLocator/CMakeLists.txt @@ -2,3 +2,4 @@ add_subdirectory(Default) if (CMAKE_SYSTEM_NAME MATCHES "Darwin") add_subdirectory(DebugSymbols) endif() +add_subdirectory(Debuginfod) diff --git a/lldb/source/Plugins/SymbolLocator/Debuginfod/CMakeLists.txt b/lldb/source/Plugins/SymbolLocator/Debuginfod/CMakeLists.txt new file mode 100644 index 000000000000..f07e93e13137 --- /dev/null +++ b/lldb/source/Plugins/SymbolLocator/Debuginfod/CMakeLists.txt @@ -0,0 +1,21 @@ +lldb_tablegen(SymbolLocatorDebuginfodProperties.inc -gen-lldb-property-defs + SOURCE SymbolLocatorDebuginfodProperties.td + TARGET LLDBPluginSymbolLocatorDebuginfodPropertiesGen) + +lldb_tablegen(SymbolLocatorDebuginfodPropertiesEnum.inc -gen-lldb-property-enum-defs + SOURCE SymbolLocatorDebuginfodProperties.td + TARGET LLDBPluginSymbolLocatorDebuginfodPropertiesEnumGen) + +add_lldb_library(lldbPluginSymbolLocatorDebuginfod PLUGIN + SymbolLocatorDebuginfod.cpp + + LINK_LIBS + lldbCore + lldbHost + lldbSymbol + LLVMDebuginfod + ) + +add_dependencies(lldbPluginSymbolLocatorDebuginfod + LLDBPluginSymbolLocatorDebuginfodPropertiesGen + LLDBPluginSymbolLocatorDebuginfodPropertiesEnumGen) diff --git a/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp new file mode 100644 index 000000000000..111be6be3652 --- /dev/null +++ b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp @@ -0,0 +1,142 @@ +//===-- SymbolLocatorDebuginfod.cpp ---------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "SymbolLocatorDebuginfod.h" + +#include "lldb/Core/PluginManager.h" +#include "lldb/Utility/Args.h" + +#include "llvm/Debuginfod/Debuginfod.h" +#include "llvm/Debuginfod/HTTPClient.h" + +using namespace lldb; +using namespace lldb_private; + +LLDB_PLUGIN_DEFINE(SymbolLocatorDebuginfod) + +namespace { + +#define LLDB_PROPERTIES_symbollocatordebuginfod +#include "SymbolLocatorDebuginfodProperties.inc" + +enum { +#define LLDB_PROPERTIES_symbollocatordebuginfod +#include "SymbolLocatorDebuginfodPropertiesEnum.inc" +}; + +class PluginProperties : public Properties { +public: + static llvm::StringRef GetSettingName() { + return SymbolLocatorDebuginfod::GetPluginNameStatic(); + } + + PluginProperties() { + m_collection_sp = std::make_shared(GetSettingName()); + m_collection_sp->Initialize(g_symbollocatordebuginfod_properties); + + // We need to read the default value first to read the environment variable. + llvm::SmallVector urls = llvm::getDefaultDebuginfodUrls(); + Args arg_urls{urls}; + m_collection_sp->SetPropertyAtIndexFromArgs(ePropertyServerURLs, arg_urls); + + m_collection_sp->SetValueChangedCallback( + ePropertyServerURLs, [this] { ServerURLsChangedCallback(); }); + } + + Args GetDebugInfoDURLs() const { + Args urls; + m_collection_sp->GetPropertyAtIndexAsArgs(ePropertyServerURLs, urls); + return urls; + } + +private: + void ServerURLsChangedCallback() { + m_server_urls = GetDebugInfoDURLs(); + llvm::SmallVector dbginfod_urls; + llvm::for_each(m_server_urls, [&](const auto &obj) { + dbginfod_urls.push_back(obj.ref()); + }); + llvm::setDefaultDebuginfodUrls(dbginfod_urls); + } + // Storage for the StringRef's used within the Debuginfod library. + Args m_server_urls; +}; + +} // namespace + +static PluginProperties &GetGlobalPluginProperties() { + static PluginProperties g_settings; + return g_settings; +} + +SymbolLocatorDebuginfod::SymbolLocatorDebuginfod() : SymbolLocator() {} + +void SymbolLocatorDebuginfod::Initialize() { + static llvm::once_flag g_once_flag; + + llvm::call_once(g_once_flag, []() { + PluginManager::RegisterPlugin( + GetPluginNameStatic(), GetPluginDescriptionStatic(), CreateInstance, + LocateExecutableObjectFile, LocateExecutableSymbolFile, nullptr, + nullptr, SymbolLocatorDebuginfod::DebuggerInitialize); + llvm::HTTPClient::initialize(); + }); +} + +void SymbolLocatorDebuginfod::DebuggerInitialize(Debugger &debugger) { + if (!PluginManager::GetSettingForSymbolLocatorPlugin( + debugger, PluginProperties::GetSettingName())) { + const bool is_global_setting = true; + PluginManager::CreateSettingForSymbolLocatorPlugin( + debugger, GetGlobalPluginProperties().GetValueProperties(), + "Properties for the Debuginfod Symbol Locator plug-in.", + is_global_setting); + } +} + +void SymbolLocatorDebuginfod::Terminate() { + PluginManager::UnregisterPlugin(CreateInstance); + llvm::HTTPClient::cleanup(); +} + +llvm::StringRef SymbolLocatorDebuginfod::GetPluginDescriptionStatic() { + return "Debuginfod symbol locator."; +} + +SymbolLocator *SymbolLocatorDebuginfod::CreateInstance() { + return new SymbolLocatorDebuginfod(); +} + +static std::optional GetFileForModule( + const ModuleSpec &module_spec, + std::function(llvm::object::BuildIDRef)> + PullFromServer) { + if (!ModuleList::GetGlobalModuleListProperties().GetEnableExternalLookup()) + return {}; + const UUID &module_uuid = module_spec.GetUUID(); + if (module_uuid.IsValid() && llvm::canUseDebuginfod()) { + llvm::object::BuildID build_id(module_uuid.GetBytes()); + llvm::Expected result = PullFromServer(build_id); + if (result) + return FileSpec(*result); + // An error here should be logged as a failure in the Debuginfod library, + // so just consume it here + consumeError(result.takeError()); + } + return {}; +} + +std::optional SymbolLocatorDebuginfod::LocateExecutableObjectFile( + const ModuleSpec &module_spec) { + return GetFileForModule(module_spec, llvm::getCachedOrDownloadExecutable); +} + +std::optional SymbolLocatorDebuginfod::LocateExecutableSymbolFile( + const ModuleSpec &module_spec, const FileSpecList &default_search_paths) { + return GetFileForModule(module_spec, llvm::getCachedOrDownloadDebuginfo); +} diff --git a/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.h b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.h new file mode 100644 index 000000000000..0ea79fa1df2a --- /dev/null +++ b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.h @@ -0,0 +1,54 @@ +//===-- SymbolLocatorDebuginfod.h -------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_SOURCE_PLUGINS_SYMBOLLOCATOR_DEBUGINFOD_SYMBOLLOCATORDEBUGINFOD_H +#define LLDB_SOURCE_PLUGINS_SYMBOLLOCATOR_DEBUGINFOD_SYMBOLLOCATORDEBUGINFOD_H + +#include "lldb/Core/Debugger.h" +#include "lldb/Symbol/SymbolLocator.h" +#include "lldb/lldb-private.h" + +namespace lldb_private { + +class SymbolLocatorDebuginfod : public SymbolLocator { +public: + SymbolLocatorDebuginfod(); + + static void Initialize(); + static void Terminate(); + static void DebuggerInitialize(Debugger &debugger); + + static llvm::StringRef GetPluginNameStatic() { return "debuginfod"; } + static llvm::StringRef GetPluginDescriptionStatic(); + + static lldb_private::SymbolLocator *CreateInstance(); + + /// PluginInterface protocol. + /// \{ + llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); } + /// \} + + // Locate the executable file given a module specification. + // + // Locating the file should happen only on the local computer or using the + // current computers global settings. + static std::optional + LocateExecutableObjectFile(const ModuleSpec &module_spec); + + // Locate the symbol file given a module specification. + // + // Locating the file should happen only on the local computer or using the + // current computers global settings. + static std::optional + LocateExecutableSymbolFile(const ModuleSpec &module_spec, + const FileSpecList &default_search_paths); +}; + +} // namespace lldb_private + +#endif // LLDB_SOURCE_PLUGINS_SYMBOLLOCATOR_DEBUGINFOD_SYMBOLLOCATORDEBUGINFOD_H diff --git a/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfodProperties.td b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfodProperties.td new file mode 100644 index 000000000000..1c668b001a16 --- /dev/null +++ b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfodProperties.td @@ -0,0 +1,7 @@ +include "../../../../include/lldb/Core/PropertiesBase.td" + +let Definition = "symbollocatordebuginfod" in { + def ServerURLs : Property<"server_urls", "Array">, + ElementType<"String">, + Desc<"An ordered list of Debuginfod server URLs to query for symbols. This defaults to the contents of the DEBUGINFOD_URLS environment variable.">; +} diff --git a/lldb/test/API/api/multithreaded/common.h b/lldb/test/API/api/multithreaded/common.h index dad8bba07a3f..2ef1cb7c5664 100644 --- a/lldb/test/API/api/multithreaded/common.h +++ b/lldb/test/API/api/multithreaded/common.h @@ -58,7 +58,8 @@ public: /// Allocates a char buffer with the current working directory inline char* get_working_dir() { -#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__NetBSD__) +#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__NetBSD__) || \ + defined(__OpenBSD__) return getwd(0); #else return get_current_dir_name(); diff --git a/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py b/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py index e63a26f543cc..60e116b42207 100644 --- a/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py +++ b/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py @@ -102,12 +102,9 @@ class TestCase(TestBase): # it does not crash. self.expect("image lookup -t A") - # For debug-info produced by older versions of clang, dsymutil strips the - # debug info for classes that only have const static data members without - # definitions. - @expectedFailureAll( - debug_info=["dsym"], compiler=["clang"], compiler_version=["<", "18.0"] - ) + # dsymutil strips the debug info for classes that only have const static + # data members without locations. + @expectedFailureAll(debug_info=["dsym"]) def test_class_with_only_const_static(self): self.build() lldbutil.run_to_source_breakpoint( @@ -123,10 +120,6 @@ class TestCase(TestBase): self.assertEqual(varobj.type.name, expect_type) self.assertEqual(varobj.value, expect_val) - # For debug-info produced by older versions of clang, inline static data members - # wouldn't get indexed into the Names accelerator table preventing LLDB from finding - # them. - @expectedFailureAll(compiler=["clang"], compiler_version=["<", "18.0"]) def test_inline_static_members(self): self.build() lldbutil.run_to_source_breakpoint( @@ -174,9 +167,6 @@ class TestCase(TestBase): "ClassWithEnumAlias::enum_alias_alias", result_value="scoped_enum_case1" ) - # With older versions of Clang, LLDB fails to evaluate classes with only - # constexpr members when dsymutil is enabled - @expectedFailureAll(compiler=["clang"], compiler_version=["<", "18.0"]) def test_shadowed_static_inline_members(self): """Tests that the expression evaluator and SBAPI can both correctly determine the requested inline static variable diff --git a/lldb/test/API/tools/lldb-server/thread-name/main.cpp b/lldb/test/API/tools/lldb-server/thread-name/main.cpp index 02eea12ca98a..17756ed7943b 100644 --- a/lldb/test/API/tools/lldb-server/thread-name/main.cpp +++ b/lldb/test/API/tools/lldb-server/thread-name/main.cpp @@ -1,4 +1,7 @@ #include +#if defined(__OpenBSD__) +#include +#endif #include void set_thread_name(const char *name) { @@ -8,6 +11,8 @@ void set_thread_name(const char *name) { ::pthread_setname_np(::pthread_self(), name); #elif defined(__NetBSD__) ::pthread_setname_np(::pthread_self(), "%s", const_cast(name)); +#elif defined(__OpenBSD__) + ::pthread_set_name_np(::pthread_self(), name); #endif } diff --git a/llvm/docs/GettingStarted.rst b/llvm/docs/GettingStarted.rst index 048d521670f5..24ed7118ee81 100644 --- a/llvm/docs/GettingStarted.rst +++ b/llvm/docs/GettingStarted.rst @@ -40,6 +40,11 @@ Getting the Source Code and Building LLVM ``git clone --depth 1 https://github.com/llvm/llvm-project.git`` + * You are likely only interested in the main branch moving forward, if + you don't want `git fetch` (or `git pull`) to download user branches, use: + + ``sed 's#fetch = +refs/heads/\*:refs/remotes/origin/\*#fetch = +refs/heads/main:refs/remotes/origin/main# -i llvm-project/.git/config`` + #. Configure and build LLVM and Clang: * ``cd llvm-project`` diff --git a/llvm/docs/GitHub.rst b/llvm/docs/GitHub.rst index 67fea9520aab..a89a4d955fc0 100644 --- a/llvm/docs/GitHub.rst +++ b/llvm/docs/GitHub.rst @@ -17,10 +17,11 @@ participate in the project using GitHub. Branches ======== -Do not create any branches in the llvm/llvm-project repository. This repository -is reserved for official project branches only. We may relax this rule in -the future if needed to support "stacked" pull request, but in that case only -branches being used for "stacked" pull requests will be allowed. + +It is possible to create branches that starts with `users//`, however this is +intended to be able to support "stacked" pull-request. Do not create any branches in the +llvm/llvm-project repository otherwise, please use a fork (see below). User branches that +aren't associated with a pull-request **will be deleted**. Pull Requests ============= diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index af064d7ac219..f5e8065ca1dc 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -365,8 +365,9 @@ added in the future: - On X86-64 the callee preserves all general purpose registers, except for R11 and return registers, if any. R11 can be used as a scratch register. - Floating-point registers (XMMs/YMMs) are not preserved and need to be - saved by the caller. + The treatment of floating-point registers (XMMs/YMMs) matches the OS's C + calling convention: on most platforms, they are not preserved and need to + be saved by the caller, but on Windows, xmm6-xmm15 are preserved. - On AArch64 the callee preserve all general purpose registers, except X0-X8 and X16-X18. @@ -636,6 +637,12 @@ appropriate fencing is inserted. Since the appropriate fencing is implementation defined, the optimizer can't do the latter. The former is challenging as many commonly expected properties, such as ``ptrtoint(v)-ptrtoint(v) == 0``, don't hold for non-integral types. +Similar restrictions apply to intrinsics that might examine the pointer bits, +such as :ref:`llvm.ptrmask`. + +The alignment information provided by the frontend for a non-integral pointer +(typically using attributes or metadata) must be valid for every possible +representation of the pointer. .. _globalvars: @@ -704,6 +711,13 @@ information. Attaching section information to an external declaration is an assertion that its definition is located in the specified section. If the definition is located in a different section, the behavior is undefined. +LLVM allows an explicit code model to be specified for globals. If the +target supports it, it will emit globals in the code model specified, +overriding the code model used to compile the translation unit. +The allowed values are "tiny", "small", "kernel", "medium", "large". +This may be extended in the future to specify global data layout that +doesn't cleanly fit into a specific code model. + By default, global initializers are optimized by assuming that global variables defined within the module are not modified from their initial values before the start of the global initializer. This is @@ -760,6 +774,7 @@ Syntax:: [] [, section "name"] [, partition "name"] [, comdat [($name)]] [, align ] + [, code_model "model"] [, no_sanitize_address] [, no_sanitize_hwaddress] [, sanitize_address_dyninit] [, sanitize_memtag] (, !name !N)* @@ -777,6 +792,13 @@ The following example just declares a global variable @G = external global i32 +The following example defines a global variable with the +``large`` code model: + +.. code-block:: llvm + + @G = internal global i32 0, code_model "large" + The following example defines a thread-local global with the ``initialexec`` TLS model: diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 3c7a40ebd295..f58ae03a6efc 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -200,8 +200,9 @@ Changes to the C API The option structure exposes an additional setting (i.e., the target ABI) and provides default values for unspecified settings. -* Added ``LLVMGetNNeg`` and ``LLVMSetNNeg`` for setting/getting the new nneg flag - on zext instructions +* Added ``LLVMGetNNeg`` and ``LLVMSetNNeg`` for getting/setting the new nneg flag + on zext instructions, and ``LLVMGetIsDisjoint`` and ``LLVMSetIsDisjoint`` + for getting/setting the new disjoint flag on or instructions. Changes to the CodeGen infrastructure ------------------------------------- @@ -262,6 +263,13 @@ Changes to LLDB (SME) and Scalable Matrix Extension 2 (SME2) for both live processes and core files. For details refer to the `AArch64 Linux documentation `_. +* LLDB now supports symbol and binary acquisition automatically using the + DEBUFINFOD protocol. The standard mechanism of specifying DEBUFINOD servers in + the ``DEBUGINFOD_URLS`` environment variable is used by default. In addition, + users can specify servers to request symbols from using the LLDB setting + ``plugin.symbol-locator.debuginfod.server_urls``, override or adding to the + environment variable. + * When running on AArch64 Linux, ``lldb-server`` now provides register field information for the following registers: ``cpsr``, ``fpcr``, diff --git a/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst b/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst index 33ee7d209d4c..17bf8a47c84c 100644 --- a/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst +++ b/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst @@ -105,8 +105,8 @@ To see which features and CPUs that LLVM knows about, we can use 3dnowa - Enable 3DNow! Athlon instructions. ... -For our example, we'll use the generic CPU without any additional -features, options or relocation model. +For our example, we'll use the generic CPU without any additional feature or +target option. .. code-block:: c++ @@ -114,8 +114,7 @@ features, options or relocation model. auto Features = ""; TargetOptions opt; - auto RM = std::optional(); - auto TargetMachine = Target->createTargetMachine(TargetTriple, CPU, Features, opt, RM); + auto TargetMachine = Target->createTargetMachine(TargetTriple, CPU, Features, opt, Reloc::PIC_); Configuring the Module diff --git a/llvm/examples/Kaleidoscope/Chapter8/toy.cpp b/llvm/examples/Kaleidoscope/Chapter8/toy.cpp index 1d36a7e67e3d..ae2f9c7059e5 100644 --- a/llvm/examples/Kaleidoscope/Chapter8/toy.cpp +++ b/llvm/examples/Kaleidoscope/Chapter8/toy.cpp @@ -1242,9 +1242,8 @@ int main() { auto Features = ""; TargetOptions opt; - auto RM = std::optional(); - auto TheTargetMachine = - Target->createTargetMachine(TargetTriple, CPU, Features, opt, RM); + auto TheTargetMachine = Target->createTargetMachine( + TargetTriple, CPU, Features, opt, Reloc::PIC_); TheModule->setDataLayout(TheTargetMachine->createDataLayout()); diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h index b16f67ef02f3..a575ec3709fe 100644 --- a/llvm/include/llvm-c/Core.h +++ b/llvm/include/llvm-c/Core.h @@ -3975,16 +3975,27 @@ LLVMBool LLVMGetExact(LLVMValueRef DivOrShrInst); void LLVMSetExact(LLVMValueRef DivOrShrInst, LLVMBool IsExact); /** - * Gets if the instruction has the non-negative flag set - * Only valid for zext instructions + * Gets if the instruction has the non-negative flag set. + * Only valid for zext instructions. */ LLVMBool LLVMGetNNeg(LLVMValueRef NonNegInst); /** - * Sets the non-negative flag for the instruction - * Only valid for zext instructions + * Sets the non-negative flag for the instruction. + * Only valid for zext instructions. */ void LLVMSetNNeg(LLVMValueRef NonNegInst, LLVMBool IsNonNeg); +/** + * Gets whether the instruction has the disjoint flag set. + * Only valid for or instructions. + */ +LLVMBool LLVMGetIsDisjoint(LLVMValueRef Inst); +/** + * Sets the disjoint flag for the instruction. + * Only valid for or instructions. + */ +void LLVMSetIsDisjoint(LLVMValueRef Inst, LLVMBool IsDisjoint); + /* Memory */ LLVMValueRef LLVMBuildMalloc(LLVMBuilderRef, LLVMTypeRef Ty, const char *Name); LLVMValueRef LLVMBuildArrayMalloc(LLVMBuilderRef, LLVMTypeRef Ty, diff --git a/llvm/include/llvm/Analysis/DomConditionCache.h b/llvm/include/llvm/Analysis/DomConditionCache.h new file mode 100644 index 000000000000..68e34f773af8 --- /dev/null +++ b/llvm/include/llvm/Analysis/DomConditionCache.h @@ -0,0 +1,56 @@ +//===- llvm/Analysis/DomConditionCache.h ------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Cache for branch conditions that affect a certain value for use by +// ValueTracking. Unlike AssumptionCache, this class does not perform any +// automatic analysis or invalidation. The caller is responsible for registering +// all relevant branches (and re-registering them if they change), and for +// removing invalidated values from the cache. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ANALYSIS_DOMCONDITIONCACHE_H +#define LLVM_ANALYSIS_DOMCONDITIONCACHE_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseMapInfo.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/IR/ValueHandle.h" + +namespace llvm { + +class Value; +class BranchInst; + +class DomConditionCache { +private: + /// A map of values about which a branch might be providing information. + using AffectedValuesMap = DenseMap>; + AffectedValuesMap AffectedValues; + +public: + /// Add a branch condition to the cache. + void registerBranch(BranchInst *BI); + + /// Remove a value from the cache, e.g. because it will be erased. + void removeValue(Value *V) { AffectedValues.erase(V); } + + /// Access the list of branches which affect this value. + ArrayRef conditionsFor(const Value *V) const { + auto AVI = AffectedValues.find_as(const_cast(V)); + if (AVI == AffectedValues.end()) + return ArrayRef(); + + return AVI->second; + } +}; + +} // end namespace llvm + +#endif // LLVM_ANALYSIS_DOMCONDITIONCACHE_H diff --git a/llvm/include/llvm/Analysis/SimplifyQuery.h b/llvm/include/llvm/Analysis/SimplifyQuery.h index f9cc3029221d..e5e6ae0d3d8e 100644 --- a/llvm/include/llvm/Analysis/SimplifyQuery.h +++ b/llvm/include/llvm/Analysis/SimplifyQuery.h @@ -14,6 +14,7 @@ namespace llvm { class AssumptionCache; +class DomConditionCache; class DominatorTree; class TargetLibraryInfo; @@ -62,6 +63,7 @@ struct SimplifyQuery { const DominatorTree *DT = nullptr; AssumptionCache *AC = nullptr; const Instruction *CxtI = nullptr; + const DomConditionCache *DC = nullptr; // Wrapper to query additional information for instructions like metadata or // keywords like nsw, which provides conservative results if those cannot @@ -80,8 +82,8 @@ struct SimplifyQuery { const DominatorTree *DT = nullptr, AssumptionCache *AC = nullptr, const Instruction *CXTI = nullptr, bool UseInstrInfo = true, - bool CanUseUndef = true) - : DL(DL), TLI(TLI), DT(DT), AC(AC), CxtI(CXTI), IIQ(UseInstrInfo), + bool CanUseUndef = true, const DomConditionCache *DC = nullptr) + : DL(DL), TLI(TLI), DT(DT), AC(AC), CxtI(CXTI), DC(DC), IIQ(UseInstrInfo), CanUseUndef(CanUseUndef) {} SimplifyQuery(const DataLayout &DL, const DominatorTree *DT, diff --git a/llvm/include/llvm/Analysis/ValueTracking.h b/llvm/include/llvm/Analysis/ValueTracking.h index c25dcad5e224..a3186e61b94a 100644 --- a/llvm/include/llvm/Analysis/ValueTracking.h +++ b/llvm/include/llvm/Analysis/ValueTracking.h @@ -214,27 +214,6 @@ std::pair fcmpToClassTest(CmpInst::Predicate Pred, const APFloat *ConstRHS, bool LookThroughSrc = true); -/// Compute the possible floating-point classes that \p LHS could be based on an -/// fcmp returning true. Returns { TestedValue, ClassesIfTrue, ClassesIfFalse } -/// -/// If the compare returns an exact class test, ClassesIfTrue == ~ClassesIfFalse -/// -/// This is a less exact version of fcmpToClassTest (e.g. fcmpToClassTest will -/// only succeed for a test of x > 0 implies positive, but not x > 1). -/// -/// If \p LookThroughSrc is true, consider the input value when computing the -/// mask. This may look through sign bit operations. -/// -/// If \p LookThroughSrc is false, ignore the source value (i.e. the first pair -/// element will always be LHS. -/// -std::tuple -fcmpImpliesClass(CmpInst::Predicate Pred, const Function &F, Value *LHS, - const APFloat *ConstRHS, bool LookThroughSrc = true); -std::tuple -fcmpImpliesClass(CmpInst::Predicate Pred, const Function &F, Value *LHS, - Value *RHS, bool LookThroughSrc = true); - struct KnownFPClass { /// Floating-point classes the value could be one of. FPClassTest KnownFPClasses = fcAllFlags; diff --git a/llvm/include/llvm/Analysis/VectorUtils.h b/llvm/include/llvm/Analysis/VectorUtils.h index d54b63fd4f53..55a6aa645a86 100644 --- a/llvm/include/llvm/Analysis/VectorUtils.h +++ b/llvm/include/llvm/Analysis/VectorUtils.h @@ -94,24 +94,24 @@ struct VFShape { assert(hasValidParameterList() && "Invalid parameter list"); } - // Retrieve the VFShape that can be used to map a (scalar) function to itself, - // with VF = 1. - static VFShape getScalarShape(const CallInst &CI) { - return VFShape::get(CI, ElementCount::getFixed(1), + /// Retrieve the VFShape that can be used to map a scalar function to itself, + /// with VF = 1. + static VFShape getScalarShape(const FunctionType *FTy) { + return VFShape::get(FTy, ElementCount::getFixed(1), /*HasGlobalPredicate*/ false); } - // Retrieve the basic vectorization shape of the function, where all - // parameters are mapped to VFParamKind::Vector with \p EC - // lanes. Specifies whether the function has a Global Predicate - // argument via \p HasGlobalPred. - static VFShape get(const CallInst &CI, ElementCount EC, bool HasGlobalPred) { + /// Retrieve the basic vectorization shape of the function, where all + /// parameters are mapped to VFParamKind::Vector with \p EC lanes. Specifies + /// whether the function has a Global Predicate argument via \p HasGlobalPred. + static VFShape get(const FunctionType *FTy, ElementCount EC, + bool HasGlobalPred) { SmallVector Parameters; - for (unsigned I = 0; I < CI.arg_size(); ++I) + for (unsigned I = 0; I < FTy->getNumParams(); ++I) Parameters.push_back(VFParameter({I, VFParamKind::Vector})); if (HasGlobalPred) Parameters.push_back( - VFParameter({CI.arg_size(), VFParamKind::GlobalPredicate})); + VFParameter({FTy->getNumParams(), VFParamKind::GlobalPredicate})); return {EC, Parameters}; } @@ -174,13 +174,13 @@ static constexpr char const *_LLVM_Scalarize_ = "_LLVM_Scalarize_"; /// /// \param MangledName -> input string in the format /// _ZGV_[()]. -/// \param CI -> A call to the scalar function which we're trying to find +/// \param FTy -> FunctionType of the scalar function which we're trying to find /// a vectorized variant for. This is required to determine the vectorization /// factor for scalable vectors, since the mangled name doesn't encode that; /// it needs to be derived from the widest element types of vector arguments /// or return values. std::optional tryDemangleForVFABI(StringRef MangledName, - const CallInst &CI); + const FunctionType *FTy); /// Retrieve the `VFParamKind` from a string token. VFParamKind getVFParamKindFromString(const StringRef Token); @@ -227,7 +227,7 @@ class VFDatabase { return; for (const auto &MangledName : ListOfStrings) { const std::optional Shape = - VFABI::tryDemangleForVFABI(MangledName, CI); + VFABI::tryDemangleForVFABI(MangledName, CI.getFunctionType()); // A match is found via scalar and vector names, and also by // ensuring that the variant described in the attribute has a // corresponding definition or declaration of the vector @@ -276,7 +276,7 @@ public: /// @{ /// Retrieve the Function with VFShape \p Shape. Function *getVectorizedFunction(const VFShape &Shape) const { - if (Shape == VFShape::getScalarShape(CI)) + if (Shape == VFShape::getScalarShape(CI.getFunctionType())) return CI.getCalledFunction(); for (const auto &Info : ScalarToVectorMappings) diff --git a/llvm/include/llvm/AsmParser/LLParser.h b/llvm/include/llvm/AsmParser/LLParser.h index 810f3668d05d..793287c772b5 100644 --- a/llvm/include/llvm/AsmParser/LLParser.h +++ b/llvm/include/llvm/AsmParser/LLParser.h @@ -290,6 +290,7 @@ namespace llvm { bool parseOptionalCallingConv(unsigned &CC); bool parseOptionalAlignment(MaybeAlign &Alignment, bool AllowParens = false); + bool parseOptionalCodeModel(CodeModel::Model &model); bool parseOptionalDerefAttrBytes(lltok::Kind AttrKind, uint64_t &Bytes); bool parseOptionalUWTableKind(UWTableKind &Kind); bool parseAllocKind(AllocFnKind &Kind); diff --git a/llvm/include/llvm/AsmParser/LLToken.h b/llvm/include/llvm/AsmParser/LLToken.h index 0683291faae7..0aa0093e8efb 100644 --- a/llvm/include/llvm/AsmParser/LLToken.h +++ b/llvm/include/llvm/AsmParser/LLToken.h @@ -116,6 +116,7 @@ enum Kind { kw_addrspace, kw_section, kw_partition, + kw_code_model, kw_alias, kw_ifunc, kw_module, diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def index 02bce3c71712..df3a342151fb 100644 --- a/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def +++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/LoongArch.def @@ -109,12 +109,20 @@ ELF_RELOC(R_LARCH_RELAX, 100) // // Spec addition: https://github.com/loongson/la-abi-specs/pull/1 // Binutils commit 57a930e3bfe4b2c7fd6463ed39311e1938513138 -ELF_RELOC(R_LARCH_DELETE, 101) +// Note that the 101 and 104 relocation numbers are defined as R_LARCH_DELETE +// and R_LARCH_CFA respectively in psABI 2.10. But they are marked as reserved +// in psABI v2.20 because they were proved not necessary to be exposed outside +// of the linker. ELF_RELOC(R_LARCH_ALIGN, 102) ELF_RELOC(R_LARCH_PCREL20_S2, 103) -ELF_RELOC(R_LARCH_CFA, 104) ELF_RELOC(R_LARCH_ADD6, 105) ELF_RELOC(R_LARCH_SUB6, 106) ELF_RELOC(R_LARCH_ADD_ULEB128, 107) ELF_RELOC(R_LARCH_SUB_ULEB128, 108) ELF_RELOC(R_LARCH_64_PCREL, 109) + +// Relocs added in ELF for the LoongArch™ Architecture v20231102, part of the +// v2.20 LoongArch ABI specs. +// +// Spec addition: https://github.com/loongson/la-abi-specs/pull/4 +ELF_RELOC(R_LARCH_CALL36, 110) diff --git a/llvm/include/llvm/Bitcode/LLVMBitCodes.h b/llvm/include/llvm/Bitcode/LLVMBitCodes.h index 99a41fa107d0..6549f5660cc3 100644 --- a/llvm/include/llvm/Bitcode/LLVMBitCodes.h +++ b/llvm/include/llvm/Bitcode/LLVMBitCodes.h @@ -210,7 +210,7 @@ enum GlobalValueSummarySymtabCodes { FS_PERMODULE = 1, // PERMODULE_PROFILE: [valueid, flags, instcount, numrefs, // numrefs x valueid, - // n x (valueid, hotness)] + // n x (valueid, hotness+tailcall)] FS_PERMODULE_PROFILE = 2, // PERMODULE_GLOBALVAR_INIT_REFS: [valueid, flags, n x valueid] FS_PERMODULE_GLOBALVAR_INIT_REFS = 3, @@ -219,7 +219,7 @@ enum GlobalValueSummarySymtabCodes { FS_COMBINED = 4, // COMBINED_PROFILE: [valueid, modid, flags, instcount, numrefs, // numrefs x valueid, - // n x (valueid, hotness)] + // n x (valueid, hotness+tailcall)] FS_COMBINED_PROFILE = 5, // COMBINED_GLOBALVAR_INIT_REFS: [valueid, modid, flags, n x valueid] FS_COMBINED_GLOBALVAR_INIT_REFS = 6, @@ -268,7 +268,7 @@ enum GlobalValueSummarySymtabCodes { // Per-module summary that also adds relative block frequency to callee info. // PERMODULE_RELBF: [valueid, flags, instcount, numrefs, // numrefs x valueid, - // n x (valueid, relblockfreq)] + // n x (valueid, relblockfreq+tailcall)] FS_PERMODULE_RELBF = 19, // Index-wide flags FS_FLAGS = 20, diff --git a/llvm/include/llvm/CodeGen/AccelTable.h b/llvm/include/llvm/CodeGen/AccelTable.h index 6a69a01a8c78..0f35fd3514fa 100644 --- a/llvm/include/llvm/CodeGen/AccelTable.h +++ b/llvm/include/llvm/CodeGen/AccelTable.h @@ -297,15 +297,15 @@ protected: }; struct TypeUnitMetaInfo { - // Symbol for start of the TU section. - MCSymbol *Label; + // Symbol for start of the TU section or signature if this is SplitDwarf. + std::variant LabelOrSignature; // Unique ID of Type Unit. unsigned UniqueID; }; using TUVectorTy = SmallVector; class DWARF5AccelTable : public AccelTable { // Symbols to start of all the TU sections that were generated. - TUVectorTy TUSymbols; + TUVectorTy TUSymbolsOrHashes; public: struct UnitIndexAndEncoding { @@ -313,9 +313,11 @@ public: DWARF5AccelTableData::AttributeEncoding Endoding; }; /// Returns type units that were constructed. - const TUVectorTy &getTypeUnitsSymbols() { return TUSymbols; } + const TUVectorTy &getTypeUnitsSymbols() { return TUSymbolsOrHashes; } /// Add a type unit start symbol. void addTypeUnitSymbol(DwarfTypeUnit &U); + /// Add a type unit Signature. + void addTypeUnitSignature(DwarfTypeUnit &U); /// Convert DIE entries to explicit offset. /// Needs to be called after DIE offsets are computed. void convertDieToOffset() { diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index fd3410586e17..e05ce2890a08 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -342,6 +342,10 @@ public: return getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace, I); } + int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) { + return getTLI()->getPreferredLargeGEPBaseOffset(MinOffset, MaxOffset); + } + unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const { auto &&IsSupportedByTarget = [this, ScalarMemTy, ScalarValTy](unsigned VF) { diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index a8ab670ad77b..076719abd035 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -29,6 +29,7 @@ #include "llvm/CodeGen/ReplaceWithVeclib.h" #include "llvm/CodeGen/SafeStack.h" #include "llvm/CodeGen/UnreachableBlockElim.h" +#include "llvm/CodeGen/WasmEHPrepare.h" #include "llvm/CodeGen/WinEHPrepare.h" #include "llvm/IR/PassManager.h" #include "llvm/IR/Verifier.h" @@ -691,7 +692,7 @@ void CodeGenPassBuilder::addPassesToHandleExceptions( // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we // should remove PHIs there. addPass(WinEHPreparePass(/*DemoteCatchSwitchPHIOnly=*/false)); - addPass(WasmEHPass()); + addPass(WasmEHPreparePass()); break; case ExceptionHandling::None: addPass(LowerInvokePass()); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h index ba72a3b71ffd..a4e9c92b4897 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h @@ -196,6 +196,10 @@ public: /// Match (and (load x), mask) -> zextload x bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo); + /// Combine a G_EXTRACT_VECTOR_ELT of a load into a narrowed + /// load. + bool matchCombineExtractedVectorLoad(MachineInstr &MI, BuildFnTy &MatchInfo); + bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo); void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo); diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def index 4c6706cf4253..1e9e5838841b 100644 --- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def +++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def @@ -54,6 +54,7 @@ FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass, ()) FUNCTION_PASS("tlshoist", TLSVariableHoistPass, ()) FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass, ()) FUNCTION_PASS("verify", VerifierPass, ()) +FUNCTION_PASS("wasm-eh-prepare", WasmEHPreparePass, ()) FUNCTION_PASS("win-eh-prepare", WinEHPreparePass, ()) #undef FUNCTION_PASS @@ -131,7 +132,6 @@ DUMMY_FUNCTION_PASS("select-optimize", SelectOptimizePass, ()) DUMMY_FUNCTION_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ()) DUMMY_FUNCTION_PASS("sjljehprepare", SjLjEHPreparePass, ()) DUMMY_FUNCTION_PASS("stack-protector", StackProtectorPass, ()) -DUMMY_FUNCTION_PASS("wasmehprepare", WasmEHPass, ()) #undef DUMMY_FUNCTION_PASS #ifndef DUMMY_MODULE_PASS diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index 282fecc3ea81..2bbe430dc68d 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -140,7 +140,8 @@ public: /// registers so that the instructions result is independent of the place /// in the function. bool isTriviallyReMaterializable(const MachineInstr &MI) const { - return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF || + return (MI.getOpcode() == TargetOpcode::IMPLICIT_DEF && + MI.getNumOperands() == 1) || (MI.getDesc().isRematerializable() && isReallyTriviallyReMaterializable(MI)); } @@ -1414,6 +1415,8 @@ public: /// Get the base operand and byte offset of an instruction that reads/writes /// memory. This is a convenience function for callers that are only prepared /// to handle a single base operand. + /// FIXME: Move Offset and OffsetIsScalable to some ElementCount-style + /// abstraction that supports negative offsets. bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, @@ -1426,6 +1429,8 @@ public: /// It returns false if base operands and offset could not be determined. /// It is not guaranteed to always recognize base operands and offsets in all /// cases. + /// FIXME: Move Offset and OffsetIsScalable to some ElementCount-style + /// abstraction that supports negative offsets. virtual bool getMemOperandsWithOffsetWidth( const MachineInstr &MI, SmallVectorImpl &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, @@ -1496,12 +1501,18 @@ public: /// to TargetPassConfig::createMachineScheduler() to have an effect. /// /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations. + /// \p Offset1 and \p Offset2 are the byte offsets for the memory + /// operations. + /// \p OffsetIsScalable1 and \p OffsetIsScalable2 indicate if the offset is + /// scaled by a runtime quantity. /// \p ClusterSize is the number of operations in the resulting load/store /// cluster if this hook returns true. /// \p NumBytes is the number of bytes that will be loaded from all the /// clustered loads if this hook returns true. virtual bool shouldClusterMemOps(ArrayRef BaseOps1, + int64_t Offset1, bool OffsetIsScalable1, ArrayRef BaseOps2, + int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const { llvm_unreachable("target did not implement shouldClusterMemOps()"); diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 77ee6b89ed8a..490125164ab3 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -30,8 +30,8 @@ #include "llvm/CodeGen/DAGCombine.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/LowLevelTypeUtils.h" -#include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/RuntimeLibcalls.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGNodes.h" @@ -2721,6 +2721,12 @@ public: Type *Ty, unsigned AddrSpace, Instruction *I = nullptr) const; + /// Return the prefered common base offset. + virtual int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, + int64_t MaxOffset) const { + return 0; + } + /// Return true if the specified immediate is legal icmp immediate, that is /// the target has icmp instructions which can compare a register against the /// immediate without having to materialize the immediate into a register. @@ -4709,25 +4715,6 @@ public: return Chain; } - /// Should SelectionDAG lower an atomic store of the given kind as a normal - /// StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to - /// eventually migrate all targets to the using StoreSDNodes, but porting is - /// being done target at a time. - virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const { - assert(SI.isAtomic() && "violated precondition"); - return false; - } - - /// Should SelectionDAG lower an atomic load of the given kind as a normal - /// LoadSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to - /// eventually migrate all targets to the using LoadSDNodes, but porting is - /// being done target at a time. - virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const { - assert(LI.isAtomic() && "violated precondition"); - return false; - } - - /// This callback is invoked by the type legalizer to legalize nodes with an /// illegal operand type but legal result types. It replaces the /// LowerOperation callback in the type Legalizer. The reason we can not do diff --git a/llvm/include/llvm/CodeGen/WasmEHPrepare.h b/llvm/include/llvm/CodeGen/WasmEHPrepare.h new file mode 100644 index 000000000000..8b3c07573a0d --- /dev/null +++ b/llvm/include/llvm/CodeGen/WasmEHPrepare.h @@ -0,0 +1,23 @@ +//===--- llvm/CodeGen/WasmEHPrepare.h ---------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_WASMEHPREPARE_H +#define LLVM_CODEGEN_WASMEHPREPARE_H + +#include "llvm/IR/PassManager.h" + +namespace llvm { + +class WasmEHPreparePass : public PassInfoMixin { +public: + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_WASMEHPREPARE_H diff --git a/llvm/include/llvm/Debuginfod/Debuginfod.h b/llvm/include/llvm/Debuginfod/Debuginfod.h index ec7f5691dda4..251fd7005305 100644 --- a/llvm/include/llvm/Debuginfod/Debuginfod.h +++ b/llvm/include/llvm/Debuginfod/Debuginfod.h @@ -46,6 +46,10 @@ bool canUseDebuginfod(); /// environment variable. SmallVector getDefaultDebuginfodUrls(); +/// Sets the list of debuginfod server URLs to query. This overrides the +/// environment variable DEBUGINFOD_URLS. +void setDefaultDebuginfodUrls(const SmallVector &URLs); + /// Finds a default local file caching directory for the debuginfod client, /// first checking DEBUGINFOD_CACHE_PATH. Expected getDefaultDebuginfodCacheDirectory(); diff --git a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h index 37c044a7415d..7203b80052b5 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h @@ -207,12 +207,12 @@ private: Error prepareSymbolTableRegistration(jitlink::LinkGraph &G, JITSymTabVector &JITSymTabInfo); Error addSymbolTableRegistration(jitlink::LinkGraph &G, + MaterializationResponsibility &MR, JITSymTabVector &JITSymTabInfo, bool InBootstrapPhase); std::mutex PluginMutex; MachOPlatform &MP; - ExecutorAddr HeaderAddr; // FIXME: ObjCImageInfos and HeaderAddrs need to be cleared when // JITDylibs are removed. diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPConstants.h b/llvm/include/llvm/Frontend/OpenMP/OMPConstants.h index 32dcdd587f3b..f8812e7955b8 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPConstants.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMPConstants.h @@ -277,6 +277,16 @@ enum class RTLDependenceKindTy { DepOmpAllMem = 0x80, }; +/// A type of worksharing loop construct +enum class WorksharingLoopType { + // Worksharing `for`-loop + ForStaticLoop, + // Worksharing `distrbute`-loop + DistributeStaticLoop, + // Worksharing `distrbute parallel for`-loop + DistributeForStaticLoop +}; + } // end namespace omp } // end namespace llvm diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h index 334eaf01a59c..abbef03d02cb 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h @@ -900,6 +900,28 @@ public: omp::OpenMPOffloadMappingFlags MemberOfFlag); private: + /// Modifies the canonical loop to be a statically-scheduled workshare loop + /// which is executed on the device + /// + /// This takes a \p CLI representing a canonical loop, such as the one + /// created by \see createCanonicalLoop and emits additional instructions to + /// turn it into a workshare loop. In particular, it calls to an OpenMP + /// runtime function in the preheader to call OpenMP device rtl function + /// which handles worksharing of loop body interations. + /// + /// \param DL Debug location for instructions added for the + /// workshare-loop construct itself. + /// \param CLI A descriptor of the canonical loop to workshare. + /// \param AllocaIP An insertion point for Alloca instructions usable in the + /// preheader of the loop. + /// \param LoopType Information about type of loop worksharing. + /// It corresponds to type of loop workshare OpenMP pragma. + /// + /// \returns Point where to insert code after the workshare construct. + InsertPointTy applyWorkshareLoopTarget(DebugLoc DL, CanonicalLoopInfo *CLI, + InsertPointTy AllocaIP, + omp::WorksharingLoopType LoopType); + /// Modifies the canonical loop to be a statically-scheduled workshare loop. /// /// This takes a \p LoopInfo representing a canonical loop, such as the one @@ -1012,6 +1034,8 @@ public: /// present in the schedule clause. /// \param HasOrderedClause Whether the (parameterless) ordered clause is /// present. + /// \param LoopType Information about type of loop worksharing. + /// It corresponds to type of loop workshare OpenMP pragma. /// /// \returns Point where to insert code after the workshare construct. InsertPointTy applyWorkshareLoop( @@ -1020,7 +1044,9 @@ public: llvm::omp::ScheduleKind SchedKind = llvm::omp::OMP_SCHEDULE_Default, Value *ChunkSize = nullptr, bool HasSimdModifier = false, bool HasMonotonicModifier = false, bool HasNonmonotonicModifier = false, - bool HasOrderedClause = false); + bool HasOrderedClause = false, + omp::WorksharingLoopType LoopType = + omp::WorksharingLoopType::ForStaticLoop); /// Tile a loop nest. /// diff --git a/llvm/include/llvm/IR/Constants.h b/llvm/include/llvm/IR/Constants.h index 2f7fc5652c2c..0b9f89830b79 100644 --- a/llvm/include/llvm/IR/Constants.h +++ b/llvm/include/llvm/IR/Constants.h @@ -27,6 +27,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/IR/Constant.h" #include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Intrinsics.h" #include "llvm/IR/OperandTraits.h" #include "llvm/IR/User.h" #include "llvm/IR/Value.h" @@ -1095,18 +1096,24 @@ public: static Constant *getExactLogBase2(Constant *C); /// Return the identity constant for a binary opcode. - /// The identity constant C is defined as X op C = X and C op X = X for every - /// X when the binary operation is commutative. If the binop is not - /// commutative, callers can acquire the operand 1 identity constant by - /// setting AllowRHSConstant to true. For example, any shift has a zero - /// identity constant for operand 1: X shift 0 = X. - /// If this is a fadd/fsub operation and we don't care about signed zeros, - /// then setting NSZ to true returns the identity +0.0 instead of -0.0. - /// Return nullptr if the operator does not have an identity constant. + /// If the binop is not commutative, callers can acquire the operand 1 + /// identity constant by setting AllowRHSConstant to true. For example, any + /// shift has a zero identity constant for operand 1: X shift 0 = X. If this + /// is a fadd/fsub operation and we don't care about signed zeros, then + /// setting NSZ to true returns the identity +0.0 instead of -0.0. Return + /// nullptr if the operator does not have an identity constant. static Constant *getBinOpIdentity(unsigned Opcode, Type *Ty, bool AllowRHSConstant = false, bool NSZ = false); + static Constant *getIntrinsicIdentity(Intrinsic::ID, Type *Ty); + + /// Return the identity constant for a binary or intrinsic Instruction. + /// The identity constant C is defined as X op C = X and C op X = X where C + /// and X are the first two operands, and the operation is commutative. + static Constant *getIdentity(Instruction *I, Type *Ty, + bool AllowRHSConstant = false, bool NSZ = false); + /// Return the absorbing element for the given binary /// operation, i.e. a constant C such that X op C = C and C op X = C for /// every X. For example, this returns zero for integer multiplication. diff --git a/llvm/include/llvm/IR/DerivedTypes.h b/llvm/include/llvm/IR/DerivedTypes.h index f7a09fda8ccb..443fb7de3b82 100644 --- a/llvm/include/llvm/IR/DerivedTypes.h +++ b/llvm/include/llvm/IR/DerivedTypes.h @@ -669,20 +669,6 @@ public: return PointerType::get(C, 0); } - /// This constructs a pointer type with the same pointee type as input - /// PointerType (or opaque pointer if the input PointerType is opaque) and the - /// given address space. This is only useful during the opaque pointer - /// transition. - /// TODO: remove after opaque pointer transition is complete. - [[deprecated("Use PointerType::get() with LLVMContext argument instead")]] - static PointerType *getWithSamePointeeType(PointerType *PT, - unsigned AddressSpace) { - return get(PT->getContext(), AddressSpace); - } - - [[deprecated("Always returns true")]] - bool isOpaque() const { return true; } - /// Return true if the specified type is valid as a element type. static bool isValidElementType(Type *ElemTy); @@ -692,24 +678,6 @@ public: /// Return the address space of the Pointer type. inline unsigned getAddressSpace() const { return getSubclassData(); } - /// Return true if either this is an opaque pointer type or if this pointee - /// type matches Ty. Primarily used for checking if an instruction's pointer - /// operands are valid types. Will be useless after non-opaque pointers are - /// removed. - [[deprecated("Always returns true")]] - bool isOpaqueOrPointeeTypeMatches(Type *) { - return true; - } - - /// Return true if both pointer types have the same element type. Two opaque - /// pointers are considered to have the same element type, while an opaque - /// and a non-opaque pointer have different element types. - /// TODO: Remove after opaque pointer transition is complete. - [[deprecated("Always returns true")]] - bool hasSameElementTypeAs(PointerType *Other) { - return true; - } - /// Implement support type inquiry through isa, cast, and dyn_cast. static bool classof(const Type *T) { return T->getTypeID() == PointerTyID; diff --git a/llvm/include/llvm/IR/GlobalObject.h b/llvm/include/llvm/IR/GlobalObject.h index 889bd3a28e12..ae8e61682444 100644 --- a/llvm/include/llvm/IR/GlobalObject.h +++ b/llvm/include/llvm/IR/GlobalObject.h @@ -51,6 +51,7 @@ protected: Comdat *ObjComdat = nullptr; enum { LastAlignmentBit = 5, + LastCodeModelBit = 8, HasSectionHashEntryBit, GlobalObjectBits, diff --git a/llvm/include/llvm/IR/GlobalVariable.h b/llvm/include/llvm/IR/GlobalVariable.h index 5ddffd16acc6..bcaf8e91432b 100644 --- a/llvm/include/llvm/IR/GlobalVariable.h +++ b/llvm/include/llvm/IR/GlobalVariable.h @@ -47,6 +47,11 @@ class GlobalVariable : public GlobalObject, public ilist_node { // global initializers are run? bool isExternallyInitializedConstant : 1; +private: + static const unsigned CodeModelBits = LastCodeModelBit - LastAlignmentBit; + static const unsigned CodeModelMask = (1 << CodeModelBits) - 1; + static const unsigned CodeModelShift = LastAlignmentBit + 1; + public: /// GlobalVariable ctor - If a parent module is specified, the global is /// automatically inserted into the end of the specified modules global list. @@ -247,6 +252,28 @@ public: getAttributes().hasAttribute("rodata-section"); } + /// Get the custom code model raw value of this global. + /// + unsigned getCodeModelRaw() const { + unsigned Data = getGlobalValueSubClassData(); + return (Data >> CodeModelShift) & CodeModelMask; + } + + /// Get the custom code model of this global if it has one. + /// + /// If this global does not have a custom code model, the empty instance + /// will be returned. + std::optional getCodeModel() const { + unsigned CodeModelData = getCodeModelRaw(); + if (CodeModelData > 0) + return static_cast(CodeModelData - 1); + return {}; + } + + /// Change the code model for this global. + /// + void setCodeModel(CodeModel::Model CM); + // Methods for support type inquiry through isa, cast, and dyn_cast: static bool classof(const Value *V) { return V->getValueID() == Value::GlobalVariableVal; diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h index ddae3e4f43f4..6eba902fa041 100644 --- a/llvm/include/llvm/IR/InstrTypes.h +++ b/llvm/include/llvm/IR/InstrTypes.h @@ -336,6 +336,15 @@ public: return BO; } + static inline BinaryOperator * + CreateDisjoint(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = ""); + static inline BinaryOperator *CreateDisjoint(BinaryOps Opc, Value *V1, + Value *V2, const Twine &Name, + BasicBlock *BB); + static inline BinaryOperator *CreateDisjoint(BinaryOps Opc, Value *V1, + Value *V2, const Twine &Name, + Instruction *I); + #define DEFINE_HELPERS(OPC, NUWNSWEXACT) \ static BinaryOperator *Create##NUWNSWEXACT##OPC(Value *V1, Value *V2, \ const Twine &Name = "") { \ @@ -364,6 +373,8 @@ public: DEFINE_HELPERS(AShr, Exact) // CreateExactAShr DEFINE_HELPERS(LShr, Exact) // CreateExactLShr + DEFINE_HELPERS(Or, Disjoint) // CreateDisjointOr + #undef DEFINE_HELPERS /// Helper functions to construct and inspect unary operations (NEG and NOT) @@ -438,6 +449,27 @@ public: } }; +BinaryOperator *BinaryOperator::CreateDisjoint(BinaryOps Opc, Value *V1, + Value *V2, const Twine &Name) { + BinaryOperator *BO = Create(Opc, V1, V2, Name); + cast(BO)->setIsDisjoint(true); + return BO; +} +BinaryOperator *BinaryOperator::CreateDisjoint(BinaryOps Opc, Value *V1, + Value *V2, const Twine &Name, + BasicBlock *BB) { + BinaryOperator *BO = Create(Opc, V1, V2, Name, BB); + cast(BO)->setIsDisjoint(true); + return BO; +} +BinaryOperator *BinaryOperator::CreateDisjoint(BinaryOps Opc, Value *V1, + Value *V2, const Twine &Name, + Instruction *I) { + BinaryOperator *BO = Create(Opc, V1, V2, Name, I); + cast(BO)->setIsDisjoint(true); + return BO; +} + //===----------------------------------------------------------------------===// // CastInst Class //===----------------------------------------------------------------------===// diff --git a/llvm/include/llvm/IR/IntrinsicInst.h b/llvm/include/llvm/IR/IntrinsicInst.h index c26ecef6eaae..8940bebd2c9a 100644 --- a/llvm/include/llvm/IR/IntrinsicInst.h +++ b/llvm/include/llvm/IR/IntrinsicInst.h @@ -55,6 +55,18 @@ public: return getCalledFunction()->getIntrinsicID(); } + bool isAssociative() const { + switch (getIntrinsicID()) { + case Intrinsic::smax: + case Intrinsic::smin: + case Intrinsic::umax: + case Intrinsic::umin: + return true; + default: + return false; + } + } + /// Return true if swapping the first two arguments to the intrinsic produces /// the same result. bool isCommutative() const { diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index 060e964f77bf..b54c697296b2 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -2469,6 +2469,10 @@ def int_preserve_struct_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [IntrNoMem, ImmArg>, ImmArg>]>; +def int_preserve_static_offset : DefaultAttrsIntrinsic<[llvm_ptr_ty], + [llvm_ptr_ty], + [IntrNoMem, IntrSpeculatable, + ReadNone >]>; //===------------ Intrinsics to perform common vector shuffles ------------===// diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index 3c0a07be5060..83fc208e7f7e 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -3548,6 +3548,37 @@ let TargetPrefix = "aarch64" in { // Zero ZT0 // def int_aarch64_sme_zero_zt : DefaultAttrsIntrinsic<[], [llvm_i32_ty], [ImmArg>, IntrWriteMem]>; + + // + // Lookup table expand one register + // + def int_aarch64_sme_luti2_lane_zt + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, IntrReadMem]>; + def int_aarch64_sme_luti4_lane_zt + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, IntrReadMem]>; + + // Lookup table expand two registers + // + def int_aarch64_sme_luti2_lane_zt_x2 + : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, IntrReadMem]>; + def int_aarch64_sme_luti4_lane_zt_x2 + : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, IntrReadMem]>; + + // + // Lookup table expand four registers + // + def int_aarch64_sme_luti2_lane_zt_x4 + : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], + [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, IntrReadMem]>; + def int_aarch64_sme_luti4_lane_zt_x4 + : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], + [llvm_i32_ty, llvm_nxv16i8_ty, llvm_i32_ty], + [ImmArg>, ImmArg>, IntrReadMem]>; } // SVE2.1 - ZIPQ1, ZIPQ2, UZPQ1, UZPQ2 diff --git a/llvm/include/llvm/IR/IntrinsicsBPF.td b/llvm/include/llvm/IR/IntrinsicsBPF.td index 8916b60d2be3..c7ec0916f1d1 100644 --- a/llvm/include/llvm/IR/IntrinsicsBPF.td +++ b/llvm/include/llvm/IR/IntrinsicsBPF.td @@ -37,4 +37,43 @@ let TargetPrefix = "bpf" in { // All intrinsics start with "llvm.bpf." def int_bpf_compare : ClangBuiltin<"__builtin_bpf_compare">, Intrinsic<[llvm_i1_ty], [llvm_i32_ty, llvm_anyint_ty, llvm_anyint_ty], [IntrNoMem]>; + def int_bpf_getelementptr_and_load : ClangBuiltin<"__builtin_bpf_getelementptr_and_load">, + Intrinsic<[llvm_any_ty], + [llvm_ptr_ty, // base ptr for getelementptr + llvm_i1_ty, // volatile + llvm_i8_ty, // atomic order + llvm_i8_ty, // synscope id + llvm_i8_ty, // alignment + llvm_i1_ty, // inbounds + llvm_vararg_ty], // indices for getelementptr insn + [IntrNoCallback, + IntrNoFree, + IntrWillReturn, + NoCapture >, + ImmArg >, // volatile + ImmArg >, // atomic order + ImmArg >, // synscope id + ImmArg >, // alignment + ImmArg >, // inbounds + ]>; + def int_bpf_getelementptr_and_store : ClangBuiltin<"__builtin_bpf_getelementptr_and_store">, + Intrinsic<[], + [llvm_any_ty, // value to store + llvm_ptr_ty, // base ptr for getelementptr + llvm_i1_ty, // volatile + llvm_i8_ty, // atomic order + llvm_i8_ty, // syncscope id + llvm_i8_ty, // alignment + llvm_i1_ty, // inbounds + llvm_vararg_ty], // indexes for getelementptr insn + [IntrNoCallback, + IntrNoFree, + IntrWillReturn, + NoCapture >, + ImmArg >, // volatile + ImmArg >, // atomic order + ImmArg >, // syncscope id + ImmArg >, // alignment + ImmArg >, // inbounds + ]>; } diff --git a/llvm/include/llvm/IR/ModuleSummaryIndex.h b/llvm/include/llvm/IR/ModuleSummaryIndex.h index cd02c71adddf..e72f74ad4adb 100644 --- a/llvm/include/llvm/IR/ModuleSummaryIndex.h +++ b/llvm/include/llvm/IR/ModuleSummaryIndex.h @@ -68,21 +68,31 @@ struct CalleeInfo { // added to HotnessType enum. uint32_t Hotness : 3; + // True if at least one of the calls to the callee is a tail call. + bool HasTailCall : 1; + /// The value stored in RelBlockFreq has to be interpreted as the digits of /// a scaled number with a scale of \p -ScaleShift. - uint32_t RelBlockFreq : 29; + static constexpr unsigned RelBlockFreqBits = 28; + uint32_t RelBlockFreq : RelBlockFreqBits; static constexpr int32_t ScaleShift = 8; - static constexpr uint64_t MaxRelBlockFreq = (1 << 29) - 1; + static constexpr uint64_t MaxRelBlockFreq = (1 << RelBlockFreqBits) - 1; CalleeInfo() - : Hotness(static_cast(HotnessType::Unknown)), RelBlockFreq(0) {} - explicit CalleeInfo(HotnessType Hotness, uint64_t RelBF) - : Hotness(static_cast(Hotness)), RelBlockFreq(RelBF) {} + : Hotness(static_cast(HotnessType::Unknown)), + HasTailCall(false), RelBlockFreq(0) {} + explicit CalleeInfo(HotnessType Hotness, bool HasTC, uint64_t RelBF) + : Hotness(static_cast(Hotness)), HasTailCall(HasTC), + RelBlockFreq(RelBF) {} void updateHotness(const HotnessType OtherHotness) { Hotness = std::max(Hotness, static_cast(OtherHotness)); } + bool hasTailCall() const { return HasTailCall; } + + void setHasTailCall(const bool HasTC) { HasTailCall = HasTC; } + HotnessType getHotness() const { return HotnessType(Hotness); } /// Update \p RelBlockFreq from \p BlockFreq and \p EntryFreq diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h index f709a5ac52a4..07f950a9f452 100644 --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -1239,6 +1239,37 @@ inline SpecificBinaryOp_match m_BinOp(unsigned Opcode, const LHS &L, return SpecificBinaryOp_match(Opcode, L, R); } +template +struct DisjointOr_match { + LHS L; + RHS R; + + DisjointOr_match(const LHS &L, const RHS &R) : L(L), R(R) {} + + template bool match(OpTy *V) { + if (auto *PDI = dyn_cast(V)) { + assert(PDI->getOpcode() == Instruction::Or && "Only or can be disjoint"); + if (!PDI->isDisjoint()) + return false; + return (L.match(PDI->getOperand(0)) && R.match(PDI->getOperand(1))) || + (Commutable && L.match(PDI->getOperand(1)) && + R.match(PDI->getOperand(0))); + } + return false; + } +}; + +template +inline DisjointOr_match m_DisjointOr(const LHS &L, const RHS &R) { + return DisjointOr_match(L, R); +} + +template +inline DisjointOr_match m_c_DisjointOr(const LHS &L, + const RHS &R) { + return DisjointOr_match(L, R); +} + //===----------------------------------------------------------------------===// // Class that matches a group of binary opcodes. // diff --git a/llvm/include/llvm/MC/MCSectionXCOFF.h b/llvm/include/llvm/MC/MCSectionXCOFF.h index 68832f5daad5..7b7a58f26bca 100644 --- a/llvm/include/llvm/MC/MCSectionXCOFF.h +++ b/llvm/include/llvm/MC/MCSectionXCOFF.h @@ -115,6 +115,7 @@ public: bool useCodeAlign() const override; bool isVirtualSection() const override; StringRef getSymbolTableName() const { return SymbolTableName; } + void setSymbolTableName(StringRef STN) { SymbolTableName = STN; } bool isMultiSymbolsAllowed() const { return MultiSymbolsAllowed; } bool isCsect() const { return CsectProp.has_value(); } bool isDwarfSect() const { return DwarfSubtypeFlags.has_value(); } diff --git a/llvm/include/llvm/MC/MCSymbolXCOFF.h b/llvm/include/llvm/MC/MCSymbolXCOFF.h index af5759f72618..ef14b0b5c243 100644 --- a/llvm/include/llvm/MC/MCSymbolXCOFF.h +++ b/llvm/include/llvm/MC/MCSymbolXCOFF.h @@ -52,9 +52,12 @@ public: XCOFF::VisibilityType getVisibilityType() const { return VisibilityType; } - bool hasRename() const { return !SymbolTableName.empty(); } + bool hasRename() const { return HasRename; } - void setSymbolTableName(StringRef STN) { SymbolTableName = STN; } + void setSymbolTableName(StringRef STN) { + SymbolTableName = STN; + HasRename = true; + } StringRef getSymbolTableName() const { if (hasRename()) @@ -67,6 +70,7 @@ private: MCSectionXCOFF *RepresentedCsect = nullptr; XCOFF::VisibilityType VisibilityType = XCOFF::SYM_V_UNSPECIFIED; StringRef SymbolTableName; + bool HasRename = false; }; } // end namespace llvm diff --git a/llvm/include/llvm/MC/MCXCOFFStreamer.h b/llvm/include/llvm/MC/MCXCOFFStreamer.h index 041bbbfa474b..8cae64fa33be 100644 --- a/llvm/include/llvm/MC/MCXCOFFStreamer.h +++ b/llvm/include/llvm/MC/MCXCOFFStreamer.h @@ -33,10 +33,7 @@ public: MCSymbolAttr Visibility) override; void emitXCOFFRefDirective(const MCSymbol *Symbol) override; void emitXCOFFRenameDirective(const MCSymbol *Name, - StringRef Rename) override { - report_fatal_error("emitXCOFFRenameDirective is not implemented yet on " - "object generation path"); - } + StringRef Rename) override; void emitXCOFFExceptDirective(const MCSymbol *Symbol, const MCSymbol *Trap, unsigned Lang, unsigned Reason, unsigned FunctionSize, bool hasDebug) override; diff --git a/llvm/include/llvm/Support/Compiler.h b/llvm/include/llvm/Support/Compiler.h index 6b13952bb2f4..8c315d255bb7 100644 --- a/llvm/include/llvm/Support/Compiler.h +++ b/llvm/include/llvm/Support/Compiler.h @@ -157,6 +157,25 @@ #define LLVM_DEPRECATED(MSG, FIX) [[deprecated(MSG)]] #endif +// clang-format off +#if defined(__clang__) || defined(__GNUC__) +#define LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_PUSH \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"") +#define LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_POP \ + _Pragma("GCC diagnostic pop") +#elif defined(_MSC_VER) +#define LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_PUSH \ + _Pragma("warning(push)") \ + _Pragma("warning(disable : 4996)") +#define LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_POP \ + _Pragma("warning(pop)") +#else +#define LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_PUSH +#define LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_POP +#endif +// clang-format on + // Indicate that a non-static, non-const C++ member function reinitializes // the entire object to a known state, independent of the previous state of // the object. diff --git a/llvm/include/llvm/Support/Host.h b/llvm/include/llvm/Support/Host.h deleted file mode 100644 index 113a252a12de..000000000000 --- a/llvm/include/llvm/Support/Host.h +++ /dev/null @@ -1,18 +0,0 @@ -//===-- llvm/Support/Host.h -------------------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -/// -/// \file -/// This header is deprecated in favour of `llvm/TargetParser/Host.h`. -/// -//===----------------------------------------------------------------------===// - -#ifdef __GNUC__ -#pragma GCC warning \ - "This header is deprecated, please use llvm/TargetParser/Host.h" -#endif -#include "llvm/TargetParser/Host.h" diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td index 9a84ab80157f..77db371adaf7 100644 --- a/llvm/include/llvm/Target/GlobalISel/Combine.td +++ b/llvm/include/llvm/Target/GlobalISel/Combine.td @@ -259,6 +259,12 @@ def sext_inreg_to_zext_inreg : GICombineRule< }]) >; +def combine_extracted_vector_load : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (wip_match_opcode G_EXTRACT_VECTOR_ELT):$root, + [{ return Helper.matchCombineExtractedVectorLoad(*${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>; + def combine_indexed_load_store : GICombineRule< (defs root:$root, indexed_load_store_matchdata:$matchinfo), (match (wip_match_opcode G_LOAD, G_SEXTLOAD, G_ZEXTLOAD, G_STORE):$root, @@ -1291,8 +1297,8 @@ def constant_fold_binops : GICombineGroup<[constant_fold_binop, constant_fold_fp_binop]>; def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines, - extract_vec_elt_combines, combines_for_extload, - undef_combines, identity_combines, phi_combines, + extract_vec_elt_combines, combines_for_extload, combine_extracted_vector_load, + undef_combines, identity_combines, phi_combines, simplify_add_to_sub, hoist_logic_op_with_same_opcode_hands, shifts_too_big, reassocs, ptr_add_immed_chain, shl_ashr_to_sext_inreg, sext_inreg_of_load, diff --git a/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h b/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h index e33afd20cfb2..950cc8c9d165 100644 --- a/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h +++ b/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h @@ -18,6 +18,7 @@ #ifndef LLVM_TRANSFORMS_INSTCOMBINE_INSTCOMBINER_H #define LLVM_TRANSFORMS_INSTCOMBINE_INSTCOMBINER_H +#include "llvm/Analysis/DomConditionCache.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/TargetFolder.h" #include "llvm/Analysis/ValueTracking.h" @@ -72,10 +73,11 @@ protected: TargetLibraryInfo &TLI; DominatorTree &DT; const DataLayout &DL; - const SimplifyQuery SQ; + SimplifyQuery SQ; OptimizationRemarkEmitter &ORE; BlockFrequencyInfo *BFI; ProfileSummaryInfo *PSI; + DomConditionCache DC; // Optional analyses. When non-null, these can both be used to do better // combining and will be updated to reflect any changes. @@ -98,7 +100,9 @@ public: const DataLayout &DL, LoopInfo *LI) : TTI(TTI), Builder(Builder), Worklist(Worklist), MinimizeSize(MinimizeSize), AA(AA), AC(AC), TLI(TLI), DT(DT), DL(DL), - SQ(DL, &TLI, &DT, &AC), ORE(ORE), BFI(BFI), PSI(PSI), LI(LI) {} + SQ(DL, &TLI, &DT, &AC, nullptr, /*UseInstrInfo*/ true, + /*CanUseUndef*/ true, &DC), + ORE(ORE), BFI(BFI), PSI(PSI), LI(LI) {} virtual ~InstCombiner() = default; diff --git a/llvm/include/llvm/XRay/BlockVerifier.h b/llvm/include/llvm/XRay/BlockVerifier.h index 0bfbbb6c5b07..2450ad89ffe3 100644 --- a/llvm/include/llvm/XRay/BlockVerifier.h +++ b/llvm/include/llvm/XRay/BlockVerifier.h @@ -14,7 +14,6 @@ #define LLVM_XRAY_BLOCKVERIFIER_H #include "llvm/XRay/FDRRecords.h" -#include namespace llvm { namespace xray { diff --git a/llvm/include/module.modulemap b/llvm/include/module.modulemap index 4c2ba437edb9..8930fa8c087c 100644 --- a/llvm/include/module.modulemap +++ b/llvm/include/module.modulemap @@ -380,9 +380,6 @@ module LLVM_Utils { umbrella "llvm/Support" module * { export * } - // Exclude this; deprecated. - exclude header "llvm/Support/Host.h" - // Exclude this; it should only be used on Windows. exclude header "llvm/Support/Windows/WindowsSupport.h" diff --git a/llvm/lib/Analysis/CMakeLists.txt b/llvm/lib/Analysis/CMakeLists.txt index 9d8c9cfda66c..34ff6bb74c10 100644 --- a/llvm/lib/Analysis/CMakeLists.txt +++ b/llvm/lib/Analysis/CMakeLists.txt @@ -55,6 +55,7 @@ add_llvm_component_library(LLVMAnalysis DependenceAnalysis.cpp DependenceGraphBuilder.cpp DevelopmentModeInlineAdvisor.cpp + DomConditionCache.cpp DomPrinter.cpp DomTreeUpdater.cpp DominanceFrontier.cpp diff --git a/llvm/lib/Analysis/CaptureTracking.cpp b/llvm/lib/Analysis/CaptureTracking.cpp index 0d6d30923bb5..7f8f7b26f8fe 100644 --- a/llvm/lib/Analysis/CaptureTracking.cpp +++ b/llvm/lib/Analysis/CaptureTracking.cpp @@ -361,8 +361,13 @@ UseCaptureKind llvm::DetermineUseCaptureKind( return UseCaptureKind::MAY_CAPTURE; return UseCaptureKind::NO_CAPTURE; } - case Instruction::BitCast: case Instruction::GetElementPtr: + // AA does not support pointers of vectors, so GEP vector splats need to + // be considered as captures. + if (I->getType()->isVectorTy()) + return UseCaptureKind::MAY_CAPTURE; + return UseCaptureKind::PASSTHROUGH; + case Instruction::BitCast: case Instruction::PHI: case Instruction::Select: case Instruction::AddrSpaceCast: diff --git a/llvm/lib/Analysis/DomConditionCache.cpp b/llvm/lib/Analysis/DomConditionCache.cpp new file mode 100644 index 000000000000..351881fe9e1f --- /dev/null +++ b/llvm/lib/Analysis/DomConditionCache.cpp @@ -0,0 +1,68 @@ +//===- DomConditionCache.cpp ----------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/Analysis/DomConditionCache.h" +#include "llvm/IR/PatternMatch.h" + +using namespace llvm; +using namespace llvm::PatternMatch; + +// TODO: This code is very similar to findAffectedValues() in +// AssumptionCache, but currently specialized to just the patterns that +// computeKnownBits() supports, and without the notion of result elem indices +// that are AC specific. Deduplicate this code once we have a clearer picture +// of how much they can be shared. +static void findAffectedValues(Value *Cond, + SmallVectorImpl &Affected) { + auto AddAffected = [&Affected](Value *V) { + if (isa(V) || isa(V)) { + Affected.push_back(V); + } else if (auto *I = dyn_cast(V)) { + Affected.push_back(I); + + // Peek through unary operators to find the source of the condition. + Value *Op; + if (match(I, m_PtrToInt(m_Value(Op)))) { + if (isa(Op) || isa(Op)) + Affected.push_back(Op); + } + } + }; + + ICmpInst::Predicate Pred; + Value *A; + Constant *C; + if (match(Cond, m_ICmp(Pred, m_Value(A), m_Constant(C)))) { + AddAffected(A); + + if (ICmpInst::isEquality(Pred)) { + Value *X; + // (X & C) or (X | C) or (X ^ C). + // (X << C) or (X >>_s C) or (X >>_u C). + if (match(A, m_BitwiseLogic(m_Value(X), m_ConstantInt())) || + match(A, m_Shift(m_Value(X), m_ConstantInt()))) + AddAffected(X); + } else { + Value *X; + // Handle (A + C1) u< C2, which is the canonical form of A > C3 && A < C4. + if (match(A, m_Add(m_Value(X), m_ConstantInt()))) + AddAffected(X); + } + } +} + +void DomConditionCache::registerBranch(BranchInst *BI) { + assert(BI->isConditional() && "Must be conditional branch"); + SmallVector Affected; + findAffectedValues(BI->getCondition(), Affected); + for (Value *V : Affected) { + auto &AV = AffectedValues[V]; + if (!is_contained(AV, BI)) + AV.push_back(BI); + } +} diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index 91f5eab03b03..a8dbb66c4a9f 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -1916,15 +1916,12 @@ getDependenceDistanceStrideAndSize( const SCEV *Src = PSE.getSCEV(APtr); const SCEV *Sink = PSE.getSCEV(BPtr); - // If the induction step is negative we have to invert source and sink of - // the dependence. + // If the induction step is negative we have to invert source and sink of the + // dependence when measuring the distance between them. We should not swap + // AIsWrite with BIsWrite, as their uses expect them in program order. if (StrideAPtr < 0) { - std::swap(APtr, BPtr); - std::swap(ATy, BTy); std::swap(Src, Sink); - std::swap(AIsWrite, BIsWrite); std::swap(AInst, BInst); - std::swap(StrideAPtr, StrideBPtr); } const SCEV *Dist = SE.getMinusSCEV(Sink, Src); diff --git a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp index 058a10769167..1f15e9478324 100644 --- a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp +++ b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp @@ -409,6 +409,8 @@ static void computeFunctionSummary( auto &ValueInfo = CallGraphEdges[Index.getOrInsertValueInfo( cast(CalledValue))]; ValueInfo.updateHotness(Hotness); + if (CB->isTailCall()) + ValueInfo.setHasTailCall(true); // Add the relative block frequency to CalleeInfo if there is no profile // information. if (BFI != nullptr && Hotness == CalleeInfo::HotnessType::Unknown) { diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp index 9670e5309b32..451ae73dbd60 100644 --- a/llvm/lib/Analysis/ScalarEvolution.cpp +++ b/llvm/lib/Analysis/ScalarEvolution.cpp @@ -5223,11 +5223,8 @@ static std::optional MatchBinaryOp(Value *V, const DataLayout &DL, return BinaryOp(Op); case Instruction::Or: { - // LLVM loves to convert `add` of operands with no common bits - // into an `or`. But SCEV really doesn't deal with `or` that well, - // so try extra hard to recognize this `or` as an `add`. - if (haveNoCommonBitsSet(Op->getOperand(0), Op->getOperand(1), - SimplifyQuery(DL, &DT, &AC, CxtI))) + // Convert or disjoint into add nuw nsw. + if (cast(Op)->isDisjoint()) return BinaryOp(Instruction::Add, Op->getOperand(0), Op->getOperand(1), /*IsNSW=*/true, /*IsNUW=*/true); return BinaryOp(Op); diff --git a/llvm/lib/Analysis/VFABIDemangling.cpp b/llvm/lib/Analysis/VFABIDemangling.cpp index 88f61cfeb9ba..92af314a41ca 100644 --- a/llvm/lib/Analysis/VFABIDemangling.cpp +++ b/llvm/lib/Analysis/VFABIDemangling.cpp @@ -369,7 +369,7 @@ getScalableECFromSignature(const FunctionType *Signature, const VFISAKind ISA, // Format of the ABI name: // _ZGV_[()] std::optional VFABI::tryDemangleForVFABI(StringRef MangledName, - const CallInst &CI) { + const FunctionType *FTy) { const StringRef OriginalName = MangledName; // Assume there is no custom name , and therefore the // vector name consists of @@ -434,7 +434,7 @@ std::optional VFABI::tryDemangleForVFABI(StringRef MangledName, // demangled parameter types and the scalar function signature. std::optional EC; if (ParsedVF.second) { - EC = getScalableECFromSignature(CI.getFunctionType(), ISA, Parameters); + EC = getScalableECFromSignature(FTy, ISA, Parameters); if (!EC) return std::nullopt; } else diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 8e7f0c6b8103..ee4f97f3bf5e 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -26,6 +26,7 @@ #include "llvm/Analysis/AssumeBundleQueries.h" #include "llvm/Analysis/AssumptionCache.h" #include "llvm/Analysis/ConstantFolding.h" +#include "llvm/Analysis/DomConditionCache.h" #include "llvm/Analysis/GuardUtils.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/Loads.h" @@ -186,37 +187,45 @@ KnownBits llvm::computeKnownBits(const Value *V, const APInt &DemandedElts, SimplifyQuery(DL, DT, AC, safeCxtI(V, CxtI), UseInstrInfo)); } -static bool haveNoCommonBitsSetSpecialCases(const Value *LHS, - const Value *RHS) { +static bool haveNoCommonBitsSetSpecialCases(const Value *LHS, const Value *RHS, + const SimplifyQuery &SQ) { // Look for an inverted mask: (X & ~M) op (Y & M). { Value *M; if (match(LHS, m_c_And(m_Not(m_Value(M)), m_Value())) && - match(RHS, m_c_And(m_Specific(M), m_Value()))) + match(RHS, m_c_And(m_Specific(M), m_Value())) && + isGuaranteedNotToBeUndef(M, SQ.AC, SQ.CxtI, SQ.DT)) return true; } // X op (Y & ~X) - if (match(RHS, m_c_And(m_Not(m_Specific(LHS)), m_Value()))) + if (match(RHS, m_c_And(m_Not(m_Specific(LHS)), m_Value())) && + isGuaranteedNotToBeUndef(LHS, SQ.AC, SQ.CxtI, SQ.DT)) return true; // X op ((X & Y) ^ Y) -- this is the canonical form of the previous pattern // for constant Y. Value *Y; - if (match(RHS, m_c_Xor(m_c_And(m_Specific(LHS), m_Value(Y)), m_Deferred(Y)))) + if (match(RHS, + m_c_Xor(m_c_And(m_Specific(LHS), m_Value(Y)), m_Deferred(Y))) && + isGuaranteedNotToBeUndef(LHS, SQ.AC, SQ.CxtI, SQ.DT) && + isGuaranteedNotToBeUndef(Y, SQ.AC, SQ.CxtI, SQ.DT)) return true; // Peek through extends to find a 'not' of the other side: // (ext Y) op ext(~Y) if (match(LHS, m_ZExtOrSExt(m_Value(Y))) && - match(RHS, m_ZExtOrSExt(m_Not(m_Specific(Y))))) + match(RHS, m_ZExtOrSExt(m_Not(m_Specific(Y)))) && + isGuaranteedNotToBeUndef(Y, SQ.AC, SQ.CxtI, SQ.DT)) return true; // Look for: (A & B) op ~(A | B) { Value *A, *B; if (match(LHS, m_And(m_Value(A), m_Value(B))) && - match(RHS, m_Not(m_c_Or(m_Specific(A), m_Specific(B))))) + match(RHS, m_Not(m_c_Or(m_Specific(A), m_Specific(B)))) && + isGuaranteedNotToBeUndef(A, SQ.AC, SQ.CxtI, SQ.DT) && + isGuaranteedNotToBeUndef(B, SQ.AC, SQ.CxtI, SQ.DT)) return true; } @@ -234,8 +243,8 @@ bool llvm::haveNoCommonBitsSet(const WithCache &LHSCache, assert(LHS->getType()->isIntOrIntVectorTy() && "LHS and RHS should be integers"); - if (haveNoCommonBitsSetSpecialCases(LHS, RHS) || - haveNoCommonBitsSetSpecialCases(RHS, LHS)) + if (haveNoCommonBitsSetSpecialCases(LHS, RHS, SQ) || + haveNoCommonBitsSetSpecialCases(RHS, LHS, SQ)) return true; return KnownBits::haveNoCommonBitsSet(LHSCache.getKnownBits(SQ), @@ -698,9 +707,33 @@ static void computeKnownBitsFromCmp(const Value *V, CmpInst::Predicate Pred, void llvm::computeKnownBitsFromContext(const Value *V, KnownBits &Known, unsigned Depth, const SimplifyQuery &Q) { - // Use of assumptions is context-sensitive. If we don't have a context, we - // cannot use them! - if (!Q.AC || !Q.CxtI) + if (!Q.CxtI) + return; + + if (Q.DC && Q.DT) { + // Handle dominating conditions. + for (BranchInst *BI : Q.DC->conditionsFor(V)) { + auto *Cmp = dyn_cast(BI->getCondition()); + if (!Cmp) + continue; + + BasicBlockEdge Edge0(BI->getParent(), BI->getSuccessor(0)); + if (Q.DT->dominates(Edge0, Q.CxtI->getParent())) + computeKnownBitsFromCmp(V, Cmp->getPredicate(), Cmp->getOperand(0), + Cmp->getOperand(1), Known, Depth, Q); + + BasicBlockEdge Edge1(BI->getParent(), BI->getSuccessor(1)); + if (Q.DT->dominates(Edge1, Q.CxtI->getParent())) + computeKnownBitsFromCmp(V, Cmp->getInversePredicate(), + Cmp->getOperand(0), Cmp->getOperand(1), Known, + Depth, Q); + } + + if (Known.hasConflict()) + Known.resetAll(); + } + + if (!Q.AC) return; unsigned BitWidth = Known.getBitWidth(); @@ -1563,7 +1596,7 @@ static void computeKnownBitsFromOperator(const Operator *I, break; case Intrinsic::riscv_vsetvli: case Intrinsic::riscv_vsetvlimax: - // Assume that VL output is >= 65536. + // Assume that VL output is <= 65536. // TODO: Take SEW and LMUL into account. if (BitWidth > 17) Known.Zero.setBitsFrom(17); @@ -4161,147 +4194,6 @@ llvm::fcmpToClassTest(FCmpInst::Predicate Pred, const Function &F, Value *LHS, return {Src, Mask}; } -std::tuple -llvm::fcmpImpliesClass(CmpInst::Predicate Pred, const Function &F, Value *LHS, - const APFloat *ConstRHS, bool LookThroughSrc) { - auto [Val, ClassMask] = - fcmpToClassTest(Pred, F, LHS, ConstRHS, LookThroughSrc); - if (Val) - return {Val, ClassMask, ~ClassMask}; - - FPClassTest RHSClass = ConstRHS->classify(); - - // If we see a zero here, we are using dynamic denormal-fp-math, and can't - // treat comparisons to 0 as an exact class test. - // - // TODO: We could do better and still recognize non-equality cases. - if (RHSClass == fcPosZero || RHSClass == fcNegZero) - return {nullptr, fcAllFlags, fcAllFlags}; - - assert((RHSClass == fcPosNormal || RHSClass == fcNegNormal || - RHSClass == fcPosSubnormal || RHSClass == fcNegSubnormal) && - "should have been recognized as an exact class test"); - - const bool IsNegativeRHS = (RHSClass & fcNegative) == RHSClass; - const bool IsPositiveRHS = (RHSClass & fcPositive) == RHSClass; - - assert(IsNegativeRHS == ConstRHS->isNegative()); - assert(IsPositiveRHS == !ConstRHS->isNegative()); - - Value *Src = LHS; - const bool IsFabs = LookThroughSrc && match(LHS, m_FAbs(m_Value(Src))); - - if (IsFabs) - RHSClass = llvm::inverse_fabs(RHSClass); - - if (Pred == FCmpInst::FCMP_OEQ) - return {Src, RHSClass, fcAllFlags}; - - if (Pred == FCmpInst::FCMP_UEQ) { - FPClassTest Class = RHSClass | fcNan; - return {Src, Class, ~fcNan}; - } - - if (Pred == FCmpInst::FCMP_ONE) - return {Src, ~fcNan, RHSClass}; - - if (Pred == FCmpInst::FCMP_UNE) - return {Src, fcAllFlags, RHSClass}; - - if (IsNegativeRHS) { - // TODO: Handle fneg(fabs) - if (IsFabs) { - // fabs(x) o> -k -> fcmp ord x, x - // fabs(x) u> -k -> true - // fabs(x) o< -k -> false - // fabs(x) u< -k -> fcmp uno x, x - switch (Pred) { - case FCmpInst::FCMP_OGT: - case FCmpInst::FCMP_OGE: - return {Src, ~fcNan, fcNan}; - case FCmpInst::FCMP_UGT: - case FCmpInst::FCMP_UGE: - return {Src, fcAllFlags, fcNone}; - case FCmpInst::FCMP_OLT: - case FCmpInst::FCMP_OLE: - return {Src, fcNone, fcAllFlags}; - case FCmpInst::FCMP_ULT: - case FCmpInst::FCMP_ULE: - return {Src, fcNan, ~fcNan}; - default: - break; - } - - return {nullptr, fcAllFlags, fcAllFlags}; - } - - FPClassTest ClassesLE = fcNegInf | fcNegNormal; - FPClassTest ClassesGE = fcPositive | fcNegZero | fcNegSubnormal; - - if (ConstRHS->isDenormal()) - ClassesLE |= fcNegSubnormal; - else - ClassesGE |= fcNegNormal; - - switch (Pred) { - case FCmpInst::FCMP_OGT: - case FCmpInst::FCMP_OGE: - return {Src, ClassesGE, ~ClassesGE | RHSClass}; - case FCmpInst::FCMP_UGT: - case FCmpInst::FCMP_UGE: - return {Src, ClassesGE | fcNan, ~(ClassesGE | fcNan) | RHSClass}; - case FCmpInst::FCMP_OLT: - case FCmpInst::FCMP_OLE: - return {Src, ClassesLE, ~ClassesLE | RHSClass}; - case FCmpInst::FCMP_ULT: - case FCmpInst::FCMP_ULE: - return {Src, ClassesLE | fcNan, ~(ClassesLE | fcNan) | RHSClass}; - default: - break; - } - } else if (IsPositiveRHS) { - FPClassTest ClassesGE = fcPosNormal | fcPosInf; - FPClassTest ClassesLE = fcNegative | fcPosZero | fcPosNormal; - if (ConstRHS->isDenormal()) - ClassesGE |= fcPosNormal; - else - ClassesLE |= fcPosSubnormal; - - if (IsFabs) { - ClassesGE = llvm::inverse_fabs(ClassesGE); - ClassesLE = llvm::inverse_fabs(ClassesLE); - } - - switch (Pred) { - case FCmpInst::FCMP_OGT: - case FCmpInst::FCMP_OGE: - return {Src, ClassesGE, ~ClassesGE | RHSClass}; - case FCmpInst::FCMP_UGT: - case FCmpInst::FCMP_UGE: - return {Src, ClassesGE | fcNan, ~(ClassesGE | fcNan) | RHSClass}; - case FCmpInst::FCMP_OLT: - case FCmpInst::FCMP_OLE: - return {Src, ClassesLE, ~ClassesLE | RHSClass}; - case FCmpInst::FCMP_ULT: - case FCmpInst::FCMP_ULE: - return {Src, ClassesLE | fcNan, ~(ClassesLE | fcNan) | RHSClass}; - default: - break; - } - } - - return {nullptr, fcAllFlags, fcAllFlags}; -} - -std::tuple -llvm::fcmpImpliesClass(CmpInst::Predicate Pred, const Function &F, Value *LHS, - Value *RHS, bool LookThroughSrc) { - const APFloat *ConstRHS; - if (!match(RHS, m_APFloatAllowUndef(ConstRHS))) - return {nullptr, fcAllFlags, fcNone}; - return fcmpImpliesClass(Pred, F, LHS, ConstRHS, LookThroughSrc); -} - static FPClassTest computeKnownFPClassFromAssumes(const Value *V, const SimplifyQuery &Q) { FPClassTest KnownFromAssume = fcAllFlags; @@ -4326,21 +4218,18 @@ static FPClassTest computeKnownFPClassFromAssumes(const Value *V, Value *LHS, *RHS; uint64_t ClassVal = 0; if (match(I->getArgOperand(0), m_FCmp(Pred, m_Value(LHS), m_Value(RHS)))) { - const APFloat *CRHS; - if (match(RHS, m_APFloat(CRHS))) { - // First see if we can fold in fabs/fneg into the test. - auto [CmpVal, MaskIfTrue, MaskIfFalse] = - fcmpImpliesClass(Pred, *F, LHS, CRHS, true); - if (CmpVal == V) - KnownFromAssume &= MaskIfTrue; - else { - // Try again without the lookthrough if we found a different source - // value. - auto [CmpVal, MaskIfTrue, MaskIfFalse] = - fcmpImpliesClass(Pred, *F, LHS, CRHS, false); - if (CmpVal == V) - KnownFromAssume &= MaskIfTrue; - } + auto [TestedValue, TestedMask] = + fcmpToClassTest(Pred, *F, LHS, RHS, true); + // First see if we can fold in fabs/fneg into the test. + if (TestedValue == V) + KnownFromAssume &= TestedMask; + else { + // Try again without the lookthrough if we found a different source + // value. + auto [TestedValue, TestedMask] = + fcmpToClassTest(Pred, *F, LHS, RHS, false); + if (TestedValue == V) + KnownFromAssume &= TestedMask; } } else if (match(I->getArgOperand(0), m_Intrinsic( @@ -4488,8 +4377,7 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, FPClassTest FilterRHS = fcAllFlags; Value *TestedValue = nullptr; - FPClassTest MaskIfTrue = fcAllFlags; - FPClassTest MaskIfFalse = fcAllFlags; + FPClassTest TestedMask = fcNone; uint64_t ClassVal = 0; const Function *F = cast(Op)->getFunction(); CmpInst::Predicate Pred; @@ -4501,22 +4389,20 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, // TODO: In some degenerate cases we can infer something if we try again // without looking through sign operations. bool LookThroughFAbsFNeg = CmpLHS != LHS && CmpLHS != RHS; - std::tie(TestedValue, MaskIfTrue, MaskIfFalse) = - fcmpImpliesClass(Pred, *F, CmpLHS, CmpRHS, LookThroughFAbsFNeg); + std::tie(TestedValue, TestedMask) = + fcmpToClassTest(Pred, *F, CmpLHS, CmpRHS, LookThroughFAbsFNeg); } else if (match(Cond, m_Intrinsic( m_Value(TestedValue), m_ConstantInt(ClassVal)))) { - FPClassTest TestedMask = static_cast(ClassVal); - MaskIfTrue = TestedMask; - MaskIfFalse = ~TestedMask; + TestedMask = static_cast(ClassVal); } if (TestedValue == LHS) { // match !isnan(x) ? x : y - FilterLHS = MaskIfTrue; - } else if (TestedValue == RHS) { // && IsExactClass + FilterLHS = TestedMask; + } else if (TestedValue == RHS) { // match !isnan(x) ? y : x - FilterRHS = MaskIfFalse; + FilterRHS = ~TestedMask; } KnownFPClass Known2; diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp index 96f39ff7e409..91d8c31fa062 100644 --- a/llvm/lib/Analysis/VectorUtils.cpp +++ b/llvm/lib/Analysis/VectorUtils.cpp @@ -1466,7 +1466,8 @@ void VFABI::getVectorVariantNames( S.split(ListAttr, ","); for (const auto &S : SetVector(ListAttr.begin(), ListAttr.end())) { - std::optional Info = VFABI::tryDemangleForVFABI(S, CI); + std::optional Info = + VFABI::tryDemangleForVFABI(S, CI.getFunctionType()); if (Info && CI.getModule()->getFunction(Info->VectorName)) { LLVM_DEBUG(dbgs() << "VFABI: Adding mapping '" << S << "' for " << CI << "\n"); diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp index 09a205c445db..bf01b39e6f97 100644 --- a/llvm/lib/AsmParser/LLLexer.cpp +++ b/llvm/lib/AsmParser/LLLexer.cpp @@ -571,6 +571,7 @@ lltok::Kind LLLexer::LexIdentifier() { KEYWORD(addrspace); KEYWORD(section); KEYWORD(partition); + KEYWORD(code_model); KEYWORD(alias); KEYWORD(ifunc); KEYWORD(module); diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index d236b6cfa900..5aa00225170b 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -1286,6 +1286,11 @@ bool LLParser::parseGlobal(const std::string &Name, LocTy NameLoc, return true; if (Alignment) GV->setAlignment(*Alignment); + } else if (Lex.getKind() == lltok::kw_code_model) { + CodeModel::Model CodeModel; + if (parseOptionalCodeModel(CodeModel)) + return true; + GV->setCodeModel(CodeModel); } else if (Lex.getKind() == lltok::MetadataVar) { if (parseGlobalObjectMetadataAttachment(*GV)) return true; @@ -2168,6 +2173,30 @@ bool LLParser::parseOptionalAlignment(MaybeAlign &Alignment, bool AllowParens) { return false; } +/// parseOptionalCodeModel +/// ::= /* empty */ +/// ::= 'code_model' "large" +bool LLParser::parseOptionalCodeModel(CodeModel::Model &model) { + Lex.Lex(); + auto StrVal = Lex.getStrVal(); + auto ErrMsg = "expected global code model string"; + if (StrVal == "tiny") + model = CodeModel::Tiny; + else if (StrVal == "small") + model = CodeModel::Small; + else if (StrVal == "kernel") + model = CodeModel::Kernel; + else if (StrVal == "medium") + model = CodeModel::Medium; + else if (StrVal == "large") + model = CodeModel::Large; + else + return tokError(ErrMsg); + if (parseToken(lltok::StringConstant, ErrMsg)) + return true; + return false; +} + /// parseOptionalDerefAttrBytes /// ::= /* empty */ /// ::= AttrKind '(' 4 ')' @@ -9067,7 +9096,8 @@ bool LLParser::parseOptionalFFlags(FunctionSummary::FFlags &FFlags) { /// OptionalCalls /// := 'calls' ':' '(' Call [',' Call]* ')' /// Call ::= '(' 'callee' ':' GVReference -/// [( ',' 'hotness' ':' Hotness | ',' 'relbf' ':' UInt32 )]? ')' +/// [( ',' 'hotness' ':' Hotness | ',' 'relbf' ':' UInt32 )]? +/// [ ',' 'tail' ]? ')' bool LLParser::parseOptionalCalls(std::vector &Calls) { assert(Lex.getKind() == lltok::kw_calls); Lex.Lex(); @@ -9092,23 +9122,39 @@ bool LLParser::parseOptionalCalls(std::vector &Calls) { CalleeInfo::HotnessType Hotness = CalleeInfo::HotnessType::Unknown; unsigned RelBF = 0; - if (EatIfPresent(lltok::comma)) { - // Expect either hotness or relbf - if (EatIfPresent(lltok::kw_hotness)) { + unsigned HasTailCall = false; + + // parse optional fields + while (EatIfPresent(lltok::comma)) { + switch (Lex.getKind()) { + case lltok::kw_hotness: + Lex.Lex(); if (parseToken(lltok::colon, "expected ':'") || parseHotness(Hotness)) return true; - } else { - if (parseToken(lltok::kw_relbf, "expected relbf") || - parseToken(lltok::colon, "expected ':'") || parseUInt32(RelBF)) + break; + case lltok::kw_relbf: + Lex.Lex(); + if (parseToken(lltok::colon, "expected ':'") || parseUInt32(RelBF)) return true; + break; + case lltok::kw_tail: + Lex.Lex(); + if (parseToken(lltok::colon, "expected ':'") || parseFlag(HasTailCall)) + return true; + break; + default: + return error(Lex.getLoc(), "expected hotness, relbf, or tail"); } } + if (Hotness != CalleeInfo::HotnessType::Unknown && RelBF > 0) + return tokError("Expected only one of hotness or relbf"); // Keep track of the Call array index needing a forward reference. // We will save the location of the ValueInfo needing an update, but // can only do so once the std::vector is finalized. if (VI.getRef() == FwdVIRef) IdToIndexMap[GVId].push_back(std::make_pair(Calls.size(), Loc)); - Calls.push_back(FunctionSummary::EdgeTy{VI, CalleeInfo(Hotness, RelBF)}); + Calls.push_back( + FunctionSummary::EdgeTy{VI, CalleeInfo(Hotness, HasTailCall, RelBF)}); if (parseToken(lltok::rparen, "expected ')' in call")) return true; @@ -9782,7 +9828,7 @@ bool LLParser::parseGVReference(ValueInfo &VI, unsigned &GVId) { GVId = Lex.getUIntVal(); // Check if we already have a VI for this GV - if (GVId < NumberedValueInfos.size()) { + if (GVId < NumberedValueInfos.size() && NumberedValueInfos[GVId]) { assert(NumberedValueInfos[GVId].getRef() != FwdVIRef); VI = NumberedValueInfos[GVId]; } else diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index e4c3770946b3..9d7e838733b5 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -1117,6 +1117,22 @@ static GlobalVarSummary::GVarFlags getDecodedGVarFlags(uint64_t RawFlags) { (GlobalObject::VCallVisibility)(RawFlags >> 3)); } +static std::pair +getDecodedHotnessCallEdgeInfo(uint64_t RawFlags) { + CalleeInfo::HotnessType Hotness = + static_cast(RawFlags & 0x7); // 3 bits + bool HasTailCall = (RawFlags & 0x8); // 1 bit + return {Hotness, HasTailCall}; +} + +static void getDecodedRelBFCallEdgeInfo(uint64_t RawFlags, uint64_t &RelBF, + bool &HasTailCall) { + static constexpr uint64_t RelBlockFreqMask = + (1 << CalleeInfo::RelBlockFreqBits) - 1; + RelBF = RawFlags & RelBlockFreqMask; // RelBlockFreqBits bits + HasTailCall = (RawFlags & (1 << CalleeInfo::RelBlockFreqBits)); // 1 bit +} + static GlobalValue::VisibilityTypes getDecodedVisibility(unsigned Val) { switch (Val) { default: // Map unknown visibilities to default. @@ -1144,6 +1160,23 @@ static bool getDecodedDSOLocal(unsigned Val) { } } +static std::optional getDecodedCodeModel(unsigned Val) { + switch (Val) { + case 1: + return CodeModel::Tiny; + case 2: + return CodeModel::Small; + case 3: + return CodeModel::Kernel; + case 4: + return CodeModel::Medium; + case 5: + return CodeModel::Large; + } + + return {}; +} + static GlobalVariable::ThreadLocalMode getDecodedThreadLocalMode(unsigned Val) { switch (Val) { case 0: return GlobalVariable::NotThreadLocal; @@ -3805,6 +3838,7 @@ Error BitcodeReader::parseGlobalVarRecord(ArrayRef Record) { // dllstorageclass, comdat, attributes, preemption specifier, // partition strtab offset, partition strtab size] (name in VST) // v2: [strtab_offset, strtab_size, v1] + // v3: [v2, code_model] StringRef Name; std::tie(Name, Record) = readNameFromStrtab(Record); @@ -3913,6 +3947,13 @@ Error BitcodeReader::parseGlobalVarRecord(ArrayRef Record) { NewGV->setSanitizerMetadata(Meta); } + if (Record.size() > 17 && Record[17]) { + if (auto CM = getDecodedCodeModel(Record[17])) + NewGV->setCodeModel(*CM); + else + return error("Invalid global variable code model"); + } + return Error::success(); } @@ -5943,10 +5984,11 @@ Error BitcodeReader::parseFunctionBody(Function *F) { } else { ResTypeID = getContainedTypeID(OpTypeID); Ty = getTypeByID(ResTypeID); - if (!Ty) - return error("Missing element type for old-style load"); } + if (!Ty) + return error("Missing load type"); + if (Error Err = typeCheckLoadStoreInst(Ty, Op->getType())) return Err; @@ -5981,10 +6023,11 @@ Error BitcodeReader::parseFunctionBody(Function *F) { } else { ResTypeID = getContainedTypeID(OpTypeID); Ty = getTypeByID(ResTypeID); - if (!Ty) - return error("Missing element type for old style atomic load"); } + if (!Ty) + return error("Missing atomic load type"); + if (Error Err = typeCheckLoadStoreInst(Ty, Op->getType())) return Err; @@ -7005,6 +7048,7 @@ ModuleSummaryIndexBitcodeReader::makeCallList(ArrayRef Record, Ret.reserve(Record.size()); for (unsigned I = 0, E = Record.size(); I != E; ++I) { CalleeInfo::HotnessType Hotness = CalleeInfo::HotnessType::Unknown; + bool HasTailCall = false; uint64_t RelBF = 0; ValueInfo Callee = std::get<0>(getValueInfoFromValueId(Record[I])); if (IsOldProfileFormat) { @@ -7012,10 +7056,12 @@ ModuleSummaryIndexBitcodeReader::makeCallList(ArrayRef Record, if (HasProfile) I += 1; // Skip old profilecount field } else if (HasProfile) - Hotness = static_cast(Record[++I]); + std::tie(Hotness, HasTailCall) = + getDecodedHotnessCallEdgeInfo(Record[++I]); else if (HasRelBF) - RelBF = Record[++I]; - Ret.push_back(FunctionSummary::EdgeTy{Callee, CalleeInfo(Hotness, RelBF)}); + getDecodedRelBFCallEdgeInfo(Record[++I], RelBF, HasTailCall); + Ret.push_back(FunctionSummary::EdgeTy{ + Callee, CalleeInfo(Hotness, HasTailCall, RelBF)}); } return Ret; } @@ -7229,14 +7275,15 @@ Error ModuleSummaryIndexBitcodeReader::parseEntireSummary(unsigned ID) { TheIndex.getOrInsertValueInfo(RefGUID), RefGUID, RefGUID); break; } + // FS_PERMODULE is legacy and does not have support for the tail call flag. // FS_PERMODULE: [valueid, flags, instcount, fflags, numrefs, // numrefs x valueid, n x (valueid)] // FS_PERMODULE_PROFILE: [valueid, flags, instcount, fflags, numrefs, // numrefs x valueid, - // n x (valueid, hotness)] + // n x (valueid, hotness+tailcall flags)] // FS_PERMODULE_RELBF: [valueid, flags, instcount, fflags, numrefs, // numrefs x valueid, - // n x (valueid, relblockfreq)] + // n x (valueid, relblockfreq+tailcall)] case bitc::FS_PERMODULE: case bitc::FS_PERMODULE_RELBF: case bitc::FS_PERMODULE_PROFILE: { @@ -7383,10 +7430,12 @@ Error ModuleSummaryIndexBitcodeReader::parseEntireSummary(unsigned ID) { TheIndex.addGlobalValueSummary(std::get<0>(GUID), std::move(VS)); break; } + // FS_COMBINED is legacy and does not have support for the tail call flag. // FS_COMBINED: [valueid, modid, flags, instcount, fflags, numrefs, // numrefs x valueid, n x (valueid)] // FS_COMBINED_PROFILE: [valueid, modid, flags, instcount, fflags, numrefs, - // numrefs x valueid, n x (valueid, hotness)] + // numrefs x valueid, + // n x (valueid, hotness+tailcall flags)] case bitc::FS_COMBINED: case bitc::FS_COMBINED_PROFILE: { unsigned ValueID = Record[0]; diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index 8239775d0486..4e0379f5f407 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -1157,6 +1157,24 @@ static uint64_t getEncodedGVarFlags(GlobalVarSummary::GVarFlags Flags) { return RawFlags; } +static uint64_t getEncodedHotnessCallEdgeInfo(const CalleeInfo &CI) { + uint64_t RawFlags = 0; + + RawFlags |= CI.Hotness; // 3 bits + RawFlags |= (CI.HasTailCall << 3); // 1 bit + + return RawFlags; +} + +static uint64_t getEncodedRelBFCallEdgeInfo(const CalleeInfo &CI) { + uint64_t RawFlags = 0; + + RawFlags |= CI.RelBlockFreq; // CalleeInfo::RelBlockFreqBits bits + RawFlags |= (CI.HasTailCall << CalleeInfo::RelBlockFreqBits); // 1 bit + + return RawFlags; +} + static unsigned getEncodedVisibility(const GlobalValue &GV) { switch (GV.getVisibility()) { case GlobalValue::DefaultVisibility: return 0; @@ -1403,7 +1421,7 @@ void ModuleBitcodeWriter::writeModuleInfo() { // GLOBALVAR: [strtab offset, strtab size, type, isconst, initid, // linkage, alignment, section, visibility, threadlocal, // unnamed_addr, externally_initialized, dllstorageclass, - // comdat, attributes, DSO_Local, GlobalSanitizer] + // comdat, attributes, DSO_Local, GlobalSanitizer, code_model] Vals.push_back(addToStrtab(GV.getName())); Vals.push_back(GV.getName().size()); Vals.push_back(VE.getTypeID(GV.getValueType())); @@ -1420,7 +1438,7 @@ void ModuleBitcodeWriter::writeModuleInfo() { GV.isExternallyInitialized() || GV.getDLLStorageClass() != GlobalValue::DefaultStorageClass || GV.hasComdat() || GV.hasAttributes() || GV.isDSOLocal() || - GV.hasPartition() || GV.hasSanitizerMetadata()) { + GV.hasPartition() || GV.hasSanitizerMetadata() || GV.getCodeModel()) { Vals.push_back(getEncodedVisibility(GV)); Vals.push_back(getEncodedThreadLocalMode(GV)); Vals.push_back(getEncodedUnnamedAddr(GV)); @@ -1438,6 +1456,7 @@ void ModuleBitcodeWriter::writeModuleInfo() { Vals.push_back((GV.hasSanitizerMetadata() ? serializeSanitizerMetadata( GV.getSanitizerMetadata()) : 0)); + Vals.push_back(GV.getCodeModelRaw()); } else { AbbrevToUse = SimpleGVarAbbrev; } @@ -4008,8 +4027,9 @@ static void writeFunctionHeapProfileRecords( // Helper to emit a single function summary record. void ModuleBitcodeWriterBase::writePerModuleFunctionSummaryRecord( SmallVector &NameVals, GlobalValueSummary *Summary, - unsigned ValueID, unsigned FSCallsAbbrev, unsigned FSCallsProfileAbbrev, - unsigned CallsiteAbbrev, unsigned AllocAbbrev, const Function &F) { + unsigned ValueID, unsigned FSCallsRelBFAbbrev, + unsigned FSCallsProfileAbbrev, unsigned CallsiteAbbrev, + unsigned AllocAbbrev, const Function &F) { NameVals.push_back(ValueID); FunctionSummary *FS = cast(Summary); @@ -4036,21 +4056,21 @@ void ModuleBitcodeWriterBase::writePerModuleFunctionSummaryRecord( for (auto &RI : FS->refs()) NameVals.push_back(VE.getValueID(RI.getValue())); - bool HasProfileData = - F.hasProfileData() || ForceSummaryEdgesCold != FunctionSummary::FSHT_None; + const bool UseRelBFRecord = + WriteRelBFToSummary && !F.hasProfileData() && + ForceSummaryEdgesCold == FunctionSummary::FSHT_None; for (auto &ECI : FS->calls()) { NameVals.push_back(getValueId(ECI.first)); - if (HasProfileData) - NameVals.push_back(static_cast(ECI.second.Hotness)); - else if (WriteRelBFToSummary) - NameVals.push_back(ECI.second.RelBlockFreq); + if (UseRelBFRecord) + NameVals.push_back(getEncodedRelBFCallEdgeInfo(ECI.second)); + else + NameVals.push_back(getEncodedHotnessCallEdgeInfo(ECI.second)); } - unsigned FSAbbrev = (HasProfileData ? FSCallsProfileAbbrev : FSCallsAbbrev); + unsigned FSAbbrev = + (UseRelBFRecord ? FSCallsRelBFAbbrev : FSCallsProfileAbbrev); unsigned Code = - (HasProfileData ? bitc::FS_PERMODULE_PROFILE - : (WriteRelBFToSummary ? bitc::FS_PERMODULE_RELBF - : bitc::FS_PERMODULE)); + (UseRelBFRecord ? bitc::FS_PERMODULE_RELBF : bitc::FS_PERMODULE_PROFILE); // Emit the finished record. Stream.EmitRecord(Code, NameVals, FSAbbrev); @@ -4159,17 +4179,14 @@ void ModuleBitcodeWriterBase::writePerModuleGlobalValueSummary() { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // numrefs Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // rorefcnt Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // worefcnt - // numrefs x valueid, n x (valueid, hotness) + // numrefs x valueid, n x (valueid, hotness+tailcall flags) Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); unsigned FSCallsProfileAbbrev = Stream.EmitAbbrev(std::move(Abbv)); - // Abbrev for FS_PERMODULE or FS_PERMODULE_RELBF. + // Abbrev for FS_PERMODULE_RELBF. Abbv = std::make_shared(); - if (WriteRelBFToSummary) - Abbv->Add(BitCodeAbbrevOp(bitc::FS_PERMODULE_RELBF)); - else - Abbv->Add(BitCodeAbbrevOp(bitc::FS_PERMODULE)); + Abbv->Add(BitCodeAbbrevOp(bitc::FS_PERMODULE_RELBF)); Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); // valueid Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // flags Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); // instcount @@ -4177,10 +4194,10 @@ void ModuleBitcodeWriterBase::writePerModuleGlobalValueSummary() { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // numrefs Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // rorefcnt Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // worefcnt - // numrefs x valueid, n x (valueid [, rel_block_freq]) + // numrefs x valueid, n x (valueid, rel_block_freq+tailcall]) Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); - unsigned FSCallsAbbrev = Stream.EmitAbbrev(std::move(Abbv)); + unsigned FSCallsRelBFAbbrev = Stream.EmitAbbrev(std::move(Abbv)); // Abbrev for FS_PERMODULE_GLOBALVAR_INIT_REFS. Abbv = std::make_shared(); @@ -4252,9 +4269,9 @@ void ModuleBitcodeWriterBase::writePerModuleGlobalValueSummary() { continue; } auto *Summary = VI.getSummaryList()[0].get(); - writePerModuleFunctionSummaryRecord(NameVals, Summary, VE.getValueID(&F), - FSCallsAbbrev, FSCallsProfileAbbrev, - CallsiteAbbrev, AllocAbbrev, F); + writePerModuleFunctionSummaryRecord( + NameVals, Summary, VE.getValueID(&F), FSCallsRelBFAbbrev, + FSCallsProfileAbbrev, CallsiteAbbrev, AllocAbbrev, F); } // Capture references from GlobalVariable initializers, which are outside @@ -4325,25 +4342,8 @@ void IndexBitcodeWriter::writeCombinedGlobalValueSummary() { Stream.EmitRecord(bitc::FS_STACK_IDS, StackIds, StackIdAbbvId); } - // Abbrev for FS_COMBINED. - auto Abbv = std::make_shared(); - Abbv->Add(BitCodeAbbrevOp(bitc::FS_COMBINED)); - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); // valueid - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); // modid - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // flags - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); // instcount - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // fflags - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); // entrycount - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // numrefs - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // rorefcnt - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // worefcnt - // numrefs x valueid, n x (valueid) - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); - unsigned FSCallsAbbrev = Stream.EmitAbbrev(std::move(Abbv)); - // Abbrev for FS_COMBINED_PROFILE. - Abbv = std::make_shared(); + auto Abbv = std::make_shared(); Abbv->Add(BitCodeAbbrevOp(bitc::FS_COMBINED_PROFILE)); Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); // valueid Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); // modid @@ -4354,7 +4354,7 @@ void IndexBitcodeWriter::writeCombinedGlobalValueSummary() { Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // numrefs Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // rorefcnt Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 4)); // worefcnt - // numrefs x valueid, n x (valueid, hotness) + // numrefs x valueid, n x (valueid, hotness+tailcall flags) Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8)); unsigned FSCallsProfileAbbrev = Stream.EmitAbbrev(std::move(Abbv)); @@ -4534,14 +4534,6 @@ void IndexBitcodeWriter::writeCombinedGlobalValueSummary() { NameVals[7] = RORefCnt; NameVals[8] = WORefCnt; - bool HasProfileData = false; - for (auto &EI : FS->calls()) { - HasProfileData |= - EI.second.getHotness() != CalleeInfo::HotnessType::Unknown; - if (HasProfileData) - break; - } - for (auto &EI : FS->calls()) { // If this GUID doesn't have a value id, it doesn't have a function // summary and we don't need to record any calls to it. @@ -4549,16 +4541,12 @@ void IndexBitcodeWriter::writeCombinedGlobalValueSummary() { if (!CallValueId) continue; NameVals.push_back(*CallValueId); - if (HasProfileData) - NameVals.push_back(static_cast(EI.second.Hotness)); + NameVals.push_back(getEncodedHotnessCallEdgeInfo(EI.second)); } - unsigned FSAbbrev = (HasProfileData ? FSCallsProfileAbbrev : FSCallsAbbrev); - unsigned Code = - (HasProfileData ? bitc::FS_COMBINED_PROFILE : bitc::FS_COMBINED); - // Emit the finished record. - Stream.EmitRecord(Code, NameVals, FSAbbrev); + Stream.EmitRecord(bitc::FS_COMBINED_PROFILE, NameVals, + FSCallsProfileAbbrev); NameVals.clear(); MaybeEmitOriginalName(*S); }); diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp index 60c54687c966..d6f487c18b03 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp @@ -201,9 +201,11 @@ class Dwarf5AccelTableWriter : public AccelTableWriter { char AugmentationString[8] = {'L', 'L', 'V', 'M', '0', '7', '0', '0'}; Header(uint32_t CompUnitCount, uint32_t LocalTypeUnitCount, - uint32_t BucketCount, uint32_t NameCount) + uint32_t ForeignTypeUnitCount, uint32_t BucketCount, + uint32_t NameCount) : CompUnitCount(CompUnitCount), LocalTypeUnitCount(LocalTypeUnitCount), - BucketCount(BucketCount), NameCount(NameCount) {} + ForeignTypeUnitCount(ForeignTypeUnitCount), BucketCount(BucketCount), + NameCount(NameCount) {} void emit(Dwarf5AccelTableWriter &Ctx); }; @@ -220,6 +222,8 @@ class Dwarf5AccelTableWriter : public AccelTableWriter { MCSymbol *AbbrevStart = Asm->createTempSymbol("names_abbrev_start"); MCSymbol *AbbrevEnd = Asm->createTempSymbol("names_abbrev_end"); MCSymbol *EntryPool = Asm->createTempSymbol("names_entries"); + // Indicates if this module is built with Split Dwarf enabled. + bool IsSplitDwarf = false; void populateAbbrevsMap(); @@ -238,7 +242,8 @@ public: ArrayRef> TypeUnits, llvm::function_ref< std::optional(const DataT &)> - getIndexForEntry); + getIndexForEntry, + bool IsSplitDwarf); void emit(); }; @@ -450,6 +455,8 @@ void Dwarf5AccelTableWriter::emitTUList() const { Asm->OutStreamer->AddComment("Type unit " + Twine(TU.index())); if (std::holds_alternative(TU.value())) Asm->emitDwarfSymbolReference(std::get(TU.value())); + else if (IsSplitDwarf) + Asm->emitInt64(std::get(TU.value())); else Asm->emitDwarfLengthOrOffset(std::get(TU.value())); } @@ -551,12 +558,15 @@ Dwarf5AccelTableWriter::Dwarf5AccelTableWriter( ArrayRef> TypeUnits, llvm::function_ref< std::optional(const DataT &)> - getIndexForEntry) + getIndexForEntry, + bool IsSplitDwarf) : AccelTableWriter(Asm, Contents, false), - Header(CompUnits.size(), TypeUnits.size(), Contents.getBucketCount(), + Header(CompUnits.size(), IsSplitDwarf ? 0 : TypeUnits.size(), + IsSplitDwarf ? TypeUnits.size() : 0, Contents.getBucketCount(), Contents.getUniqueNameCount()), CompUnits(CompUnits), TypeUnits(TypeUnits), - getIndexForEntry(std::move(getIndexForEntry)) { + getIndexForEntry(std::move(getIndexForEntry)), + IsSplitDwarf(IsSplitDwarf) { populateAbbrevsMap(); } @@ -608,7 +618,10 @@ void llvm::emitDWARF5AccelTable( for (const auto &TU : TUSymbols) { TUIndex[TU.UniqueID] = TUCount++; - TypeUnits.push_back(TU.Label); + if (DD.useSplitDwarf()) + TypeUnits.push_back(std::get(TU.LabelOrSignature)); + else + TypeUnits.push_back(std::get(TU.LabelOrSignature)); } if (CompUnits.empty()) @@ -633,12 +646,17 @@ void llvm::emitDWARF5AccelTable( return {{CUIndex[Entry.getUnitID()], {dwarf::DW_IDX_compile_unit, CUIndexForm}}}; return std::nullopt; - }) + }, + DD.useSplitDwarf()) .emit(); } void DWARF5AccelTable::addTypeUnitSymbol(DwarfTypeUnit &U) { - TUSymbols.push_back({U.getLabelBegin(), U.getUniqueID()}); + TUSymbolsOrHashes.push_back({U.getLabelBegin(), U.getUniqueID()}); +} + +void DWARF5AccelTable::addTypeUnitSignature(DwarfTypeUnit &U) { + TUSymbolsOrHashes.push_back({U.getTypeSignature(), U.getUniqueID()}); } void llvm::emitDWARF5AccelTable( @@ -650,7 +668,7 @@ void llvm::emitDWARF5AccelTable( std::vector> TypeUnits; Contents.finalize(Asm, "names"); Dwarf5AccelTableWriter(Asm, Contents, CUs, TypeUnits, - getIndexForEntry) + getIndexForEntry, false) .emit(); } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 15ff39883680..3a679f1576b7 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -93,6 +93,7 @@ #include "llvm/MC/MCSectionCOFF.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSectionMachO.h" +#include "llvm/MC/MCSectionXCOFF.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" @@ -444,7 +445,7 @@ bool AsmPrinter::doInitialization(Module &M) { .getModuleMetadata(M); // On AIX, we delay emitting any section information until - // after emitting the .file pseudo-op. This allows additional + // after emitting the .file pseudo-op. This allows additional // information (such as the embedded command line) to be associated // with all sections in the object file rather than a single section. if (!TM.getTargetTriple().isOSBinFormatXCOFF()) @@ -496,8 +497,18 @@ bool AsmPrinter::doInitialization(Module &M) { // C_INFO symbol is preserved if any csect is kept by the linker. if (TM.getTargetTriple().isOSBinFormatXCOFF()) { emitModuleCommandLines(M); - // Now we can generate section information + // Now we can generate section information. OutStreamer->initSections(false, *TM.getMCSubtargetInfo()); + + // To work around an AIX assembler and/or linker bug, generate + // a rename for the default text-section symbol name. This call has + // no effect when generating object code directly. + MCSection *TextSection = + OutStreamer->getContext().getObjectFileInfo()->getTextSection(); + MCSymbolXCOFF *XSym = + static_cast(TextSection)->getQualNameSymbol(); + if (XSym->hasRename()) + OutStreamer->emitXCOFFRenameDirective(XSym, XSym->getSymbolTableName()); } GCModuleInfo *MI = getAnalysisIfAvailable(); diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index f311931a41aa..ab29020bf1d7 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -305,7 +305,6 @@ void Loc::MMI::addFrameIndexExpr(const DIExpression *Expr, int FI) { static AccelTableKind computeAccelTableKind(unsigned DwarfVersion, bool GenerateTypeUnits, - bool HasSplitDwarf, DebuggerKind Tuning, const Triple &TT) { // Honor an explicit request. @@ -314,8 +313,7 @@ static AccelTableKind computeAccelTableKind(unsigned DwarfVersion, // Generating DWARF5 acceleration table. // Currently Split dwarf and non ELF format is not supported. - if (GenerateTypeUnits && - (DwarfVersion < 5 || HasSplitDwarf || !TT.isOSBinFormatELF())) + if (GenerateTypeUnits && (DwarfVersion < 5 || !TT.isOSBinFormatELF())) return AccelTableKind::None; // Accelerator tables get emitted if targetting DWARF v5 or LLDB. DWARF v5 @@ -403,9 +401,8 @@ DwarfDebug::DwarfDebug(AsmPrinter *A) A->TM.getTargetTriple().isOSBinFormatWasm()) && GenerateDwarfTypeUnits; - TheAccelTableKind = - computeAccelTableKind(DwarfVersion, GenerateTypeUnits, HasSplitDwarf, - DebuggerTuning, A->TM.getTargetTriple()); + TheAccelTableKind = computeAccelTableKind( + DwarfVersion, GenerateTypeUnits, DebuggerTuning, A->TM.getTargetTriple()); // Work around a GDB bug. GDB doesn't support the standard opcode; // SCE doesn't support GNU's; LLDB prefers the standard opcode, which @@ -3532,8 +3529,12 @@ void DwarfDebug::addDwarfTypeUnitType(DwarfCompileUnit &CU, InfoHolder.computeSizeAndOffsetsForUnit(TU.first.get()); InfoHolder.emitUnit(TU.first.get(), useSplitDwarf()); if (getDwarfVersion() >= 5 && - getAccelTableKind() == AccelTableKind::Dwarf) - AccelDebugNames.addTypeUnitSymbol(*TU.first); + getAccelTableKind() == AccelTableKind::Dwarf) { + if (useSplitDwarf()) + AccelDebugNames.addTypeUnitSignature(*TU.first); + else + AccelDebugNames.addTypeUnitSymbol(*TU.first); + } } AccelTypeUnitsDebugNames.convertDieToOffset(); AccelDebugNames.addTypeEntries(AccelTypeUnitsDebugNames); diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index 885d2d3ce248..aa5cdd2e04a9 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -460,6 +460,7 @@ private: bool dupRetToEnableTailCallOpts(BasicBlock *BB, ModifyDT &ModifiedDT); bool fixupDbgValue(Instruction *I); bool fixupDPValue(DPValue &I); + bool fixupDPValuesOnInst(Instruction &I); bool placeDbgValues(Function &F); bool placePseudoProbes(Function &F); bool canFormExtLd(const SmallVectorImpl &MovedExts, @@ -6121,6 +6122,55 @@ bool CodeGenPrepare::splitLargeGEPOffsets() { int64_t BaseOffset = LargeOffsetGEPs.begin()->second; Value *NewBaseGEP = nullptr; + auto createNewBase = [&](int64_t BaseOffset, Value *OldBase, + GetElementPtrInst *GEP) { + LLVMContext &Ctx = GEP->getContext(); + Type *PtrIdxTy = DL->getIndexType(GEP->getType()); + Type *I8PtrTy = + PointerType::get(Ctx, GEP->getType()->getPointerAddressSpace()); + Type *I8Ty = Type::getInt8Ty(Ctx); + + BasicBlock::iterator NewBaseInsertPt; + BasicBlock *NewBaseInsertBB; + if (auto *BaseI = dyn_cast(OldBase)) { + // If the base of the struct is an instruction, the new base will be + // inserted close to it. + NewBaseInsertBB = BaseI->getParent(); + if (isa(BaseI)) + NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt(); + else if (InvokeInst *Invoke = dyn_cast(BaseI)) { + NewBaseInsertBB = + SplitEdge(NewBaseInsertBB, Invoke->getNormalDest(), DT.get(), LI); + NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt(); + } else + NewBaseInsertPt = std::next(BaseI->getIterator()); + } else { + // If the current base is an argument or global value, the new base + // will be inserted to the entry block. + NewBaseInsertBB = &BaseGEP->getFunction()->getEntryBlock(); + NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt(); + } + IRBuilder<> NewBaseBuilder(NewBaseInsertBB, NewBaseInsertPt); + // Create a new base. + Value *BaseIndex = ConstantInt::get(PtrIdxTy, BaseOffset); + NewBaseGEP = OldBase; + if (NewBaseGEP->getType() != I8PtrTy) + NewBaseGEP = NewBaseBuilder.CreatePointerCast(NewBaseGEP, I8PtrTy); + NewBaseGEP = + NewBaseBuilder.CreateGEP(I8Ty, NewBaseGEP, BaseIndex, "splitgep"); + NewGEPBases.insert(NewBaseGEP); + return; + }; + + // Check whether all the offsets can be encoded with prefered common base. + if (int64_t PreferBase = TLI->getPreferredLargeGEPBaseOffset( + LargeOffsetGEPs.front().second, LargeOffsetGEPs.back().second)) { + BaseOffset = PreferBase; + // Create a new base if the offset of the BaseGEP can be decoded with one + // instruction. + createNewBase(BaseOffset, OldBase, BaseGEP); + } + auto *LargeOffsetGEP = LargeOffsetGEPs.begin(); while (LargeOffsetGEP != LargeOffsetGEPs.end()) { GetElementPtrInst *GEP = LargeOffsetGEP->first; @@ -6153,35 +6203,7 @@ bool CodeGenPrepare::splitLargeGEPOffsets() { if (!NewBaseGEP) { // Create a new base if we don't have one yet. Find the insertion // pointer for the new base first. - BasicBlock::iterator NewBaseInsertPt; - BasicBlock *NewBaseInsertBB; - if (auto *BaseI = dyn_cast(OldBase)) { - // If the base of the struct is an instruction, the new base will be - // inserted close to it. - NewBaseInsertBB = BaseI->getParent(); - if (isa(BaseI)) - NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt(); - else if (InvokeInst *Invoke = dyn_cast(BaseI)) { - NewBaseInsertBB = - SplitEdge(NewBaseInsertBB, Invoke->getNormalDest(), DT.get(), LI); - NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt(); - } else - NewBaseInsertPt = std::next(BaseI->getIterator()); - } else { - // If the current base is an argument or global value, the new base - // will be inserted to the entry block. - NewBaseInsertBB = &BaseGEP->getFunction()->getEntryBlock(); - NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt(); - } - IRBuilder<> NewBaseBuilder(NewBaseInsertBB, NewBaseInsertPt); - // Create a new base. - Value *BaseIndex = ConstantInt::get(PtrIdxTy, BaseOffset); - NewBaseGEP = OldBase; - if (NewBaseGEP->getType() != I8PtrTy) - NewBaseGEP = NewBaseBuilder.CreatePointerCast(NewBaseGEP, I8PtrTy); - NewBaseGEP = - NewBaseBuilder.CreateGEP(I8Ty, NewBaseGEP, BaseIndex, "splitgep"); - NewGEPBases.insert(NewBaseGEP); + createNewBase(BaseOffset, OldBase, GEP); } IRBuilder<> Builder(GEP); @@ -6965,6 +6987,11 @@ bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) { // Increment the current iterator to skip all the rest of select instructions // because they will be either "not lowered" or "all lowered" to branch. CurInstIterator = std::next(LastSI->getIterator()); + // Examine debug-info attached to the consecutive select instructions. They + // won't be individually optimised by optimizeInst, so we need to perform + // DPValue maintenence here instead. + for (SelectInst *SI : ArrayRef(ASI).drop_front()) + fixupDPValuesOnInst(*SI); bool VectorCond = !SI->getCondition()->getType()->isIntegerTy(1); @@ -8120,8 +8147,7 @@ static bool optimizeBranch(BranchInst *Branch, const TargetLowering &TLI, bool CodeGenPrepare::optimizeInst(Instruction *I, ModifyDT &ModifiedDT) { bool AnyChange = false; - for (DPValue &DPV : I->getDbgValueRange()) - AnyChange |= fixupDPValue(DPV); + AnyChange = fixupDPValuesOnInst(*I); // Bail out if we inserted the instruction to prevent optimizations from // stepping on each other's toes. @@ -8387,6 +8413,13 @@ bool CodeGenPrepare::fixupDbgValue(Instruction *I) { return AnyChange; } +bool CodeGenPrepare::fixupDPValuesOnInst(Instruction &I) { + bool AnyChange = false; + for (DPValue &DPV : I.getDbgValueRange()) + AnyChange |= fixupDPValue(DPV); + return AnyChange; +} + // FIXME: should updating debug-info really cause the "changed" flag to fire, // which can cause a function to be reprocessed? bool CodeGenPrepare::fixupDPValue(DPValue &DPV) { diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index c2a7c2d01188..91a64d59e154 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -1165,6 +1165,100 @@ bool CombinerHelper::findPreIndexCandidate(GLoadStore &LdSt, Register &Addr, return RealUse; } +bool CombinerHelper::matchCombineExtractedVectorLoad(MachineInstr &MI, + BuildFnTy &MatchInfo) { + assert(MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT); + + // Check if there is a load that defines the vector being extracted from. + auto *LoadMI = getOpcodeDef(MI.getOperand(1).getReg(), MRI); + if (!LoadMI) + return false; + + Register Vector = MI.getOperand(1).getReg(); + LLT VecEltTy = MRI.getType(Vector).getElementType(); + + assert(MRI.getType(MI.getOperand(0).getReg()) == VecEltTy); + + // Checking whether we should reduce the load width. + if (!MRI.hasOneNonDBGUse(Vector)) + return false; + + // Check if the defining load is simple. + if (!LoadMI->isSimple()) + return false; + + // If the vector element type is not a multiple of a byte then we are unable + // to correctly compute an address to load only the extracted element as a + // scalar. + if (!VecEltTy.isByteSized()) + return false; + + // Check if the new load that we are going to create is legal + // if we are in the post-legalization phase. + MachineMemOperand MMO = LoadMI->getMMO(); + Align Alignment = MMO.getAlign(); + MachinePointerInfo PtrInfo; + uint64_t Offset; + + // Finding the appropriate PtrInfo if offset is a known constant. + // This is required to create the memory operand for the narrowed load. + // This machine memory operand object helps us infer about legality + // before we proceed to combine the instruction. + if (auto CVal = getIConstantVRegVal(Vector, MRI)) { + int Elt = CVal->getZExtValue(); + // FIXME: should be (ABI size)*Elt. + Offset = VecEltTy.getSizeInBits() * Elt / 8; + PtrInfo = MMO.getPointerInfo().getWithOffset(Offset); + } else { + // Discard the pointer info except the address space because the memory + // operand can't represent this new access since the offset is variable. + Offset = VecEltTy.getSizeInBits() / 8; + PtrInfo = MachinePointerInfo(MMO.getPointerInfo().getAddrSpace()); + } + + Alignment = commonAlignment(Alignment, Offset); + + Register VecPtr = LoadMI->getPointerReg(); + LLT PtrTy = MRI.getType(VecPtr); + + MachineFunction &MF = *MI.getMF(); + auto *NewMMO = MF.getMachineMemOperand(&MMO, PtrInfo, VecEltTy); + + LegalityQuery::MemDesc MMDesc(*NewMMO); + + LegalityQuery Q = {TargetOpcode::G_LOAD, {VecEltTy, PtrTy}, {MMDesc}}; + + if (!isLegalOrBeforeLegalizer(Q)) + return false; + + // Load must be allowed and fast on the target. + LLVMContext &C = MF.getFunction().getContext(); + auto &DL = MF.getDataLayout(); + unsigned Fast = 0; + if (!getTargetLowering().allowsMemoryAccess(C, DL, VecEltTy, *NewMMO, + &Fast) || + !Fast) + return false; + + Register Result = MI.getOperand(0).getReg(); + Register Index = MI.getOperand(2).getReg(); + + MatchInfo = [=](MachineIRBuilder &B) { + GISelObserverWrapper DummyObserver; + LegalizerHelper Helper(B.getMF(), DummyObserver, B); + //// Get pointer to the vector element. + Register finalPtr = Helper.getVectorElementPointer( + LoadMI->getPointerReg(), MRI.getType(LoadMI->getOperand(0).getReg()), + Index); + // New G_LOAD instruction. + B.buildLoad(Result, finalPtr, PtrInfo, Alignment); + // Remove original GLOAD instruction. + LoadMI->eraseFromParent(); + }; + + return true; +} + bool CombinerHelper::matchCombineIndexedLoadStore( MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo) { auto &LdSt = cast(MI); diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 56118e5bef35..045fc78218da 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -2406,6 +2406,16 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { Observer.changedInstr(MI); return Legalized; + case TargetOpcode::G_ROTR: + case TargetOpcode::G_ROTL: + if (TypeIdx != 1) + return UnableToLegalize; + + Observer.changingInstr(MI); + widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); + Observer.changedInstr(MI); + return Legalized; + case TargetOpcode::G_SDIV: case TargetOpcode::G_SREM: case TargetOpcode::G_SMIN: diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp index 9b5f3a4b6fa1..de9931d1c240 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp @@ -77,13 +77,11 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, LegalizeAction Action) { } raw_ostream &LegalityQuery::print(raw_ostream &OS) const { - OS << Opcode << ", Tys={"; + OS << "Opcode=" << Opcode << ", Tys={"; for (const auto &Type : Types) { OS << Type << ", "; } - OS << "}, Opcode="; - - OS << Opcode << ", MMOs={"; + OS << "}, MMOs={"; for (const auto &MMODescr : MMODescrs) { OS << MMODescr.MemoryTy << ", "; } diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp index ff49e080090c..0203034b5a01 100644 --- a/llvm/lib/CodeGen/LiveRangeEdit.cpp +++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp @@ -190,7 +190,7 @@ SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB, // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg // to false anyway in case the isDead flag of RM.OrigMI's dest register // is true. - (*--MI).getOperand(0).setIsDead(false); + (*--MI).clearRegisterDeads(DestReg); Rematted.insert(RM.ParentVNI); ++NumReMaterialization; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 4add33ba0996..c51ef33bfe54 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -1698,11 +1698,12 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation { SmallVector BaseOps; int64_t Offset; unsigned Width; + bool OffsetIsScalable; MemOpInfo(SUnit *SU, ArrayRef BaseOps, - int64_t Offset, unsigned Width) + int64_t Offset, bool OffsetIsScalable, unsigned Width) : SU(SU), BaseOps(BaseOps.begin(), BaseOps.end()), Offset(Offset), - Width(Width) {} + Width(Width), OffsetIsScalable(OffsetIsScalable) {} static bool Compare(const MachineOperand *const &A, const MachineOperand *const &B) { @@ -1831,8 +1832,10 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps( SUnit2ClusterInfo[MemOpa.SU->NodeNum].second + MemOpb.Width; } - if (!TII->shouldClusterMemOps(MemOpa.BaseOps, MemOpb.BaseOps, ClusterLength, - CurrentClusterBytes)) + if (!TII->shouldClusterMemOps(MemOpa.BaseOps, MemOpa.Offset, + MemOpa.OffsetIsScalable, MemOpb.BaseOps, + MemOpb.Offset, MemOpb.OffsetIsScalable, + ClusterLength, CurrentClusterBytes)) continue; SUnit *SUa = MemOpa.SU; @@ -1899,7 +1902,8 @@ void BaseMemOpClusterMutation::collectMemOpRecords( unsigned Width; if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable, Width, TRI)) { - MemOpRecords.push_back(MemOpInfo(&SU, BaseOps, Offset, Width)); + MemOpRecords.push_back( + MemOpInfo(&SU, BaseOps, Offset, OffsetIsScalable, Width)); LLVM_DEBUG(dbgs() << "Num BaseOps: " << BaseOps.size() << ", Offset: " << Offset << ", OffsetIsScalable: " << OffsetIsScalable diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index 1d0a03ccfcdc..1128ecfd860d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -64,11 +64,18 @@ static ISD::NodeType getPreferredExtendForValue(const Instruction *I) { // can be exposed. ISD::NodeType ExtendKind = ISD::ANY_EXTEND; unsigned NumOfSigned = 0, NumOfUnsigned = 0; - for (const User *U : I->users()) { - if (const auto *CI = dyn_cast(U)) { + for (const Use &U : I->uses()) { + if (const auto *CI = dyn_cast(U.getUser())) { NumOfSigned += CI->isSigned(); NumOfUnsigned += CI->isUnsigned(); } + if (const auto *CallI = dyn_cast(U.getUser())) { + if (!CallI->isArgOperand(&U)) + continue; + unsigned ArgNo = CallI->getArgOperandNo(&U); + NumOfUnsigned += CallI->paramHasAttr(ArgNo, Attribute::ZExt); + NumOfSigned += CallI->paramHasAttr(ArgNo, Attribute::SExt); + } } if (NumOfSigned > NumOfUnsigned) ExtendKind = ISD::SIGN_EXTEND; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 54698edce7d6..362fa92dd44b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -3830,20 +3830,7 @@ void DAGTypeLegalizer::ExpandIntRes_XROUND_XRINT(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi) { - if (N->isAtomic()) { - // It's typical to have larger CAS than atomic load instructions. - SDLoc dl(N); - EVT VT = N->getMemoryVT(); - SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other); - SDValue Zero = DAG.getConstant(0, dl, VT); - SDValue Swap = DAG.getAtomicCmpSwap( - ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, - VT, VTs, N->getOperand(0), - N->getOperand(1), Zero, Zero, N->getMemOperand()); - ReplaceValueWith(SDValue(N, 0), Swap.getValue(0)); - ReplaceValueWith(SDValue(N, 1), Swap.getValue(2)); - return; - } + assert(!N->isAtomic() && "Should have been a ATOMIC_LOAD?"); if (ISD::isNormalLoad(N)) { ExpandRes_NormalLoad(N, Lo, Hi); @@ -5398,16 +5385,8 @@ SDValue DAGTypeLegalizer::ExpandIntOp_XINT_TO_FP(SDNode *N) { } SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { - if (N->isAtomic()) { - // It's typical to have larger CAS than atomic store instructions. - SDLoc dl(N); - SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, - N->getMemoryVT(), - N->getOperand(0), N->getOperand(2), - N->getOperand(1), - N->getMemOperand()); - return Swap.getValue(1); - } + assert(!N->isAtomic() && "Should have been a ATOMIC_STORE?"); + if (ISD::isNormalStore(N)) return ExpandOp_NormalStore(N, OpNo); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index da7d9ace4114..ed1c96a87374 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -4857,23 +4857,6 @@ void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG); SDValue Ptr = getValue(I.getPointerOperand()); - - if (TLI.lowerAtomicLoadAsLoadSDNode(I)) { - // TODO: Once this is better exercised by tests, it should be merged with - // the normal path for loads to prevent future divergence. - SDValue L = DAG.getLoad(MemVT, dl, InChain, Ptr, MMO); - if (MemVT != VT) - L = DAG.getPtrExtOrTrunc(L, dl, VT); - - setValue(&I, L); - SDValue OutChain = L.getValue(1); - if (!I.isUnordered()) - DAG.setRoot(OutChain); - else - PendingLoads.push_back(OutChain); - return; - } - SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain, Ptr, MMO); @@ -4913,14 +4896,6 @@ void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { Val = DAG.getPtrExtOrTrunc(Val, dl, MemVT); SDValue Ptr = getValue(I.getPointerOperand()); - if (TLI.lowerAtomicStoreAsStoreSDNode(I)) { - // TODO: Once this is better exercised by tests, it should be merged with - // the normal path for stores to prevent future divergence. - SDValue S = DAG.getStore(InChain, dl, Val, Ptr, MMO); - setValue(&I, S); - DAG.setRoot(S); - return; - } SDValue OutChain = DAG.getAtomic(ISD::ATOMIC_STORE, dl, MemVT, InChain, Val, Ptr, MMO); diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 4bd5c910b298..4783742a14ad 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -1462,7 +1462,7 @@ bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, unsigned DefClass = DefMI.getDesc().getSchedClass(); std::optional DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); - return DefCycle <= 1U; + return DefCycle && DefCycle <= 1U; } bool TargetInstrInfo::isFunctionSafeToSplit(const MachineFunction &MF) const { diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp index a25d4ff78f4d..ce59b096992d 100644 --- a/llvm/lib/CodeGen/TargetSchedule.cpp +++ b/llvm/lib/CodeGen/TargetSchedule.cpp @@ -178,7 +178,7 @@ unsigned TargetSchedModel::computeOperandLatency( const unsigned DefaultDefLatency = TII->defaultDefLatency(SchedModel, *DefMI); if (!hasInstrSchedModel() && !hasInstrItineraries()) - return InstrLatency; + return DefaultDefLatency; if (hasInstrItineraries()) { std::optional OperLatency; diff --git a/llvm/lib/CodeGen/WasmEHPrepare.cpp b/llvm/lib/CodeGen/WasmEHPrepare.cpp index d99b10f4207f..1a9e1ba869c3 100644 --- a/llvm/lib/CodeGen/WasmEHPrepare.cpp +++ b/llvm/lib/CodeGen/WasmEHPrepare.cpp @@ -77,6 +77,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/WasmEHPrepare.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/WasmEHFuncInfo.h" @@ -88,10 +89,12 @@ using namespace llvm; -#define DEBUG_TYPE "wasmehprepare" +#define DEBUG_TYPE "wasm-eh-prepare" namespace { -class WasmEHPrepare : public FunctionPass { +class WasmEHPrepareImpl { + friend class WasmEHPrepare; + Type *LPadContextTy = nullptr; // type of 'struct _Unwind_LandingPadContext' GlobalVariable *LPadContextGV = nullptr; // __wasm_lpad_context @@ -113,19 +116,41 @@ class WasmEHPrepare : public FunctionPass { bool prepareEHPads(Function &F); void prepareEHPad(BasicBlock *BB, bool NeedPersonality, unsigned Index = 0); +public: + WasmEHPrepareImpl() = default; + WasmEHPrepareImpl(Type *LPadContextTy_) : LPadContextTy(LPadContextTy_) {} + bool runOnFunction(Function &F); +}; + +class WasmEHPrepare : public FunctionPass { + WasmEHPrepareImpl P; + public: static char ID; // Pass identification, replacement for typeid WasmEHPrepare() : FunctionPass(ID) {} bool doInitialization(Module &M) override; - bool runOnFunction(Function &F) override; + bool runOnFunction(Function &F) override { return P.runOnFunction(F); } StringRef getPassName() const override { return "WebAssembly Exception handling preparation"; } }; + } // end anonymous namespace +PreservedAnalyses WasmEHPreparePass::run(Function &F, + FunctionAnalysisManager &) { + auto &Context = F.getContext(); + auto *I32Ty = Type::getInt32Ty(Context); + auto *PtrTy = PointerType::get(Context, 0); + auto *LPadContextTy = + StructType::get(I32Ty /*lpad_index*/, PtrTy /*lsda*/, I32Ty /*selector*/); + WasmEHPrepareImpl P(LPadContextTy); + bool Changed = P.runOnFunction(F); + return Changed ? PreservedAnalyses::none() : PreservedAnalyses ::all(); +} + char WasmEHPrepare::ID = 0; INITIALIZE_PASS_BEGIN(WasmEHPrepare, DEBUG_TYPE, "Prepare WebAssembly exceptions", false, false) @@ -136,9 +161,9 @@ FunctionPass *llvm::createWasmEHPass() { return new WasmEHPrepare(); } bool WasmEHPrepare::doInitialization(Module &M) { IRBuilder<> IRB(M.getContext()); - LPadContextTy = StructType::get(IRB.getInt32Ty(), // lpad_index - IRB.getPtrTy(), // lsda - IRB.getInt32Ty() // selector + P.LPadContextTy = StructType::get(IRB.getInt32Ty(), // lpad_index + IRB.getPtrTy(), // lsda + IRB.getInt32Ty() // selector ); return false; } @@ -157,14 +182,14 @@ static void eraseDeadBBsAndChildren(const Container &BBs) { } } -bool WasmEHPrepare::runOnFunction(Function &F) { +bool WasmEHPrepareImpl::runOnFunction(Function &F) { bool Changed = false; Changed |= prepareThrows(F); Changed |= prepareEHPads(F); return Changed; } -bool WasmEHPrepare::prepareThrows(Function &F) { +bool WasmEHPrepareImpl::prepareThrows(Function &F) { Module &M = *F.getParent(); IRBuilder<> IRB(F.getContext()); bool Changed = false; @@ -192,7 +217,7 @@ bool WasmEHPrepare::prepareThrows(Function &F) { return Changed; } -bool WasmEHPrepare::prepareEHPads(Function &F) { +bool WasmEHPrepareImpl::prepareEHPads(Function &F) { Module &M = *F.getParent(); IRBuilder<> IRB(F.getContext()); @@ -275,8 +300,8 @@ bool WasmEHPrepare::prepareEHPads(Function &F) { // Prepare an EH pad for Wasm EH handling. If NeedPersonality is false, Index is // ignored. -void WasmEHPrepare::prepareEHPad(BasicBlock *BB, bool NeedPersonality, - unsigned Index) { +void WasmEHPrepareImpl::prepareEHPad(BasicBlock *BB, bool NeedPersonality, + unsigned Index) { assert(BB->isEHPad() && "BB is not an EHPad!"); IRBuilder<> IRB(BB->getContext()); IRB.SetInsertPoint(BB, BB->getFirstInsertionPt()); diff --git a/llvm/lib/Debuginfod/Debuginfod.cpp b/llvm/lib/Debuginfod/Debuginfod.cpp index fa4c1a0499f0..9df30ab55cba 100644 --- a/llvm/lib/Debuginfod/Debuginfod.cpp +++ b/llvm/lib/Debuginfod/Debuginfod.cpp @@ -41,12 +41,19 @@ #include "llvm/Support/xxhash.h" #include +#include #include namespace llvm { using llvm::object::BuildIDRef; +namespace { +std::optional> DebuginfodUrls; +// Many Readers/Single Writer lock protecting the global debuginfod URL list. +llvm::sys::RWMutex UrlsMutex; +} // namespace + static std::string uniqueKey(llvm::StringRef S) { return utostr(xxh3_64bits(S)); } @@ -62,13 +69,27 @@ bool canUseDebuginfod() { } SmallVector getDefaultDebuginfodUrls() { - const char *DebuginfodUrlsEnv = std::getenv("DEBUGINFOD_URLS"); - if (DebuginfodUrlsEnv == nullptr) - return SmallVector(); + std::shared_lock ReadGuard(UrlsMutex); + if (!DebuginfodUrls) { + // Only read from the environment variable if the user hasn't already + // set the value + ReadGuard.unlock(); + std::unique_lock WriteGuard(UrlsMutex); + DebuginfodUrls = SmallVector(); + if (const char *DebuginfodUrlsEnv = std::getenv("DEBUGINFOD_URLS")) { + StringRef(DebuginfodUrlsEnv) + .split(DebuginfodUrls.value(), " ", -1, false); + } + WriteGuard.unlock(); + ReadGuard.lock(); + } + return DebuginfodUrls.value(); +} - SmallVector DebuginfodUrls; - StringRef(DebuginfodUrlsEnv).split(DebuginfodUrls, " "); - return DebuginfodUrls; +// Set the default debuginfod URL list, override the environment variable +void setDefaultDebuginfodUrls(const SmallVector &URLs) { + std::unique_lock WriteGuard(UrlsMutex); + DebuginfodUrls = URLs; } /// Finds a default local file caching directory for the debuginfod client, diff --git a/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp b/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp index eb8e6825fad4..7316b2dce8ab 100644 --- a/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp +++ b/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp @@ -284,7 +284,7 @@ StaticLibraryDefinitionGenerator::Load( // If this is a universal binary then search for a slice matching the given // Triple. - if (auto *UB = cast(B->getBinary())) { + if (auto *UB = dyn_cast(B->getBinary())) { const auto &TT = L.getExecutionSession().getTargetTriple(); @@ -347,7 +347,7 @@ StaticLibraryDefinitionGenerator::Create( // If this is a universal binary then search for a slice matching the given // Triple. - if (auto *UB = cast(B->get())) { + if (auto *UB = dyn_cast(B->get())) { const auto &TT = L.getExecutionSession().getTargetTriple(); diff --git a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp index 850e29cf9952..a0bd9b6266ff 100644 --- a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp +++ b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp @@ -754,12 +754,6 @@ void MachOPlatform::rt_pushInitializers(PushInitializersSendResultFn SendResult, void MachOPlatform::rt_pushSymbols( PushSymbolsInSendResultFn SendResult, ExecutorAddr Handle, const std::vector> &SymbolNames) { - LLVM_DEBUG({ - dbgs() << "MachOPlatform::rt_pushSymbols(" << Handle << ", [ "; - for (auto &Name : SymbolNames) - dbgs() << "\"" << Name.first << "\" "; - dbgs() << "])\n"; - }); JITDylib *JD = nullptr; @@ -769,6 +763,16 @@ void MachOPlatform::rt_pushSymbols( if (I != HeaderAddrToJITDylib.end()) JD = I->second; } + LLVM_DEBUG({ + dbgs() << "MachOPlatform::rt_pushSymbols("; + if (JD) + dbgs() << "\"" << JD->getName() << "\", [ "; + else + dbgs() << ", [ "; + for (auto &Name : SymbolNames) + dbgs() << "\"" << Name.first << "\" "; + dbgs() << "])\n"; + }); if (!JD) { SendResult(make_error("No JITDylib associated with handle " + @@ -787,7 +791,6 @@ void MachOPlatform::rt_pushSymbols( LookupKind::DLSym, {{JD, JITDylibLookupFlags::MatchExportedSymbolsOnly}}, std::move(LS), SymbolState::Ready, [SendResult = std::move(SendResult)](Expected Result) mutable { - dbgs() << "Sending result pushSymbols result...\n"; SendResult(Result.takeError()); }, NoDependenciesToRegister); @@ -813,14 +816,6 @@ void MachOPlatform::MachOPlatformPlugin::modifyPassConfig( using namespace jitlink; - // Check for a header address. - { - std::lock_guard Lock(MP.PlatformMutex); - auto I = MP.JITDylibToHeaderAddr.find(&MR.getTargetJITDylib()); - if (I != MP.JITDylibToHeaderAddr.end()) - HeaderAddr = I->second; - } - bool InBootstrapPhase = &MR.getTargetJITDylib() == &MP.PlatformJD && MP.Bootstrap; @@ -875,10 +870,10 @@ void MachOPlatform::MachOPlatformPlugin::modifyPassConfig( Config.PostPrunePasses.push_back([this, JITSymTabInfo](LinkGraph &G) { return prepareSymbolTableRegistration(G, *JITSymTabInfo); }); - Config.PostFixupPasses.push_back( - [this, JITSymTabInfo, InBootstrapPhase](LinkGraph &G) { - return addSymbolTableRegistration(G, *JITSymTabInfo, InBootstrapPhase); - }); + Config.PostFixupPasses.push_back([this, &MR, JITSymTabInfo, + InBootstrapPhase](LinkGraph &G) { + return addSymbolTableRegistration(G, MR, *JITSymTabInfo, InBootstrapPhase); + }); // Add a pass to register the final addresses of any special sections in the // object with the runtime. @@ -1427,7 +1422,15 @@ Error MachOPlatform::MachOPlatformPlugin::registerObjectPlatformSections( ? G.allocActions() : MP.Bootstrap.load()->DeferredAAs; - assert(HeaderAddr && "No HeaderAddr for JITDylib"); + ExecutorAddr HeaderAddr; + { + std::lock_guard Lock(MP.PlatformMutex); + auto I = MP.JITDylibToHeaderAddr.find(&JD); + assert(I != MP.JITDylibToHeaderAddr.end() && + "No header registered for JD"); + assert(I->second && "Null header registered for JD"); + HeaderAddr = I->second; + } allocActions.push_back( {cantFail( WrapperFunctionCall::Create( @@ -1699,16 +1702,23 @@ Error MachOPlatform::MachOPlatformPlugin::prepareSymbolTableRegistration( } Error MachOPlatform::MachOPlatformPlugin::addSymbolTableRegistration( - jitlink::LinkGraph &G, JITSymTabVector &JITSymTabInfo, - bool InBootstrapPhase) { + jitlink::LinkGraph &G, MaterializationResponsibility &MR, + JITSymTabVector &JITSymTabInfo, bool InBootstrapPhase) { + + ExecutorAddr HeaderAddr; + { + std::lock_guard Lock(MP.PlatformMutex); + auto I = MP.JITDylibToHeaderAddr.find(&MR.getTargetJITDylib()); + assert(I != MP.JITDylibToHeaderAddr.end() && "No header registered for JD"); + assert(I->second && "Null header registered for JD"); + HeaderAddr = I->second; + } SmallVector> SymTab; - for (auto &[OriginalSymbol, NameSym] : JITSymTabInfo) { - // dbgs() << "Original symbol: \"" << OriginalSymbol->getName() << "\"\n"; + for (auto &[OriginalSymbol, NameSym] : JITSymTabInfo) SymTab.push_back({NameSym->getAddress(), OriginalSymbol->getAddress(), flagsForSymbol(*OriginalSymbol)}); - } using SPSRegisterSymbolsArgs = SPSArgListgetFirstInsertionPt()}; } +// Returns an LLVM function to call for executing an OpenMP static worksharing +// for loop depending on `type`. Only i32 and i64 are supported by the runtime. +// Always interpret integers as unsigned similarly to CanonicalLoopInfo. +static FunctionCallee +getKmpcForStaticLoopForType(Type *Ty, OpenMPIRBuilder *OMPBuilder, + WorksharingLoopType LoopType) { + unsigned Bitwidth = Ty->getIntegerBitWidth(); + Module &M = OMPBuilder->M; + switch (LoopType) { + case WorksharingLoopType::ForStaticLoop: + if (Bitwidth == 32) + return OMPBuilder->getOrCreateRuntimeFunction( + M, omp::RuntimeFunction::OMPRTL___kmpc_for_static_loop_4u); + if (Bitwidth == 64) + return OMPBuilder->getOrCreateRuntimeFunction( + M, omp::RuntimeFunction::OMPRTL___kmpc_for_static_loop_8u); + break; + case WorksharingLoopType::DistributeStaticLoop: + if (Bitwidth == 32) + return OMPBuilder->getOrCreateRuntimeFunction( + M, omp::RuntimeFunction::OMPRTL___kmpc_distribute_static_loop_4u); + if (Bitwidth == 64) + return OMPBuilder->getOrCreateRuntimeFunction( + M, omp::RuntimeFunction::OMPRTL___kmpc_distribute_static_loop_8u); + break; + case WorksharingLoopType::DistributeForStaticLoop: + if (Bitwidth == 32) + return OMPBuilder->getOrCreateRuntimeFunction( + M, omp::RuntimeFunction::OMPRTL___kmpc_distribute_for_static_loop_4u); + if (Bitwidth == 64) + return OMPBuilder->getOrCreateRuntimeFunction( + M, omp::RuntimeFunction::OMPRTL___kmpc_distribute_for_static_loop_8u); + break; + } + if (Bitwidth != 32 && Bitwidth != 64) { + llvm_unreachable("Unknown OpenMP loop iterator bitwidth"); + } + llvm_unreachable("Unknown type of OpenMP worksharing loop"); +} + +// Inserts a call to proper OpenMP Device RTL function which handles +// loop worksharing. +static void createTargetLoopWorkshareCall( + OpenMPIRBuilder *OMPBuilder, WorksharingLoopType LoopType, + BasicBlock *InsertBlock, Value *Ident, Value *LoopBodyArg, + Type *ParallelTaskPtr, Value *TripCount, Function &LoopBodyFn) { + Type *TripCountTy = TripCount->getType(); + Module &M = OMPBuilder->M; + IRBuilder<> &Builder = OMPBuilder->Builder; + FunctionCallee RTLFn = + getKmpcForStaticLoopForType(TripCountTy, OMPBuilder, LoopType); + SmallVector RealArgs; + RealArgs.push_back(Ident); + RealArgs.push_back(Builder.CreateBitCast(&LoopBodyFn, ParallelTaskPtr)); + RealArgs.push_back(LoopBodyArg); + RealArgs.push_back(TripCount); + if (LoopType == WorksharingLoopType::DistributeStaticLoop) { + RealArgs.push_back(ConstantInt::get(TripCountTy, 0)); + Builder.CreateCall(RTLFn, RealArgs); + return; + } + FunctionCallee RTLNumThreads = OMPBuilder->getOrCreateRuntimeFunction( + M, omp::RuntimeFunction::OMPRTL_omp_get_num_threads); + Builder.restoreIP({InsertBlock, std::prev(InsertBlock->end())}); + Value *NumThreads = Builder.CreateCall(RTLNumThreads, {}); + + RealArgs.push_back( + Builder.CreateZExtOrTrunc(NumThreads, TripCountTy, "num.threads.cast")); + RealArgs.push_back(ConstantInt::get(TripCountTy, 0)); + if (LoopType == WorksharingLoopType::DistributeForStaticLoop) { + RealArgs.push_back(ConstantInt::get(TripCountTy, 0)); + } + + Builder.CreateCall(RTLFn, RealArgs); +} + +static void +workshareLoopTargetCallback(OpenMPIRBuilder *OMPIRBuilder, + CanonicalLoopInfo *CLI, Value *Ident, + Function &OutlinedFn, Type *ParallelTaskPtr, + const SmallVector &ToBeDeleted, + WorksharingLoopType LoopType) { + IRBuilder<> &Builder = OMPIRBuilder->Builder; + BasicBlock *Preheader = CLI->getPreheader(); + Value *TripCount = CLI->getTripCount(); + + // After loop body outling, the loop body contains only set up + // of loop body argument structure and the call to the outlined + // loop body function. Firstly, we need to move setup of loop body args + // into loop preheader. + Preheader->splice(std::prev(Preheader->end()), CLI->getBody(), + CLI->getBody()->begin(), std::prev(CLI->getBody()->end())); + + // The next step is to remove the whole loop. We do not it need anymore. + // That's why make an unconditional branch from loop preheader to loop + // exit block + Builder.restoreIP({Preheader, Preheader->end()}); + Preheader->getTerminator()->eraseFromParent(); + Builder.CreateBr(CLI->getExit()); + + // Delete dead loop blocks + OpenMPIRBuilder::OutlineInfo CleanUpInfo; + SmallPtrSet RegionBlockSet; + SmallVector BlocksToBeRemoved; + CleanUpInfo.EntryBB = CLI->getHeader(); + CleanUpInfo.ExitBB = CLI->getExit(); + CleanUpInfo.collectBlocks(RegionBlockSet, BlocksToBeRemoved); + DeleteDeadBlocks(BlocksToBeRemoved); + + // Find the instruction which corresponds to loop body argument structure + // and remove the call to loop body function instruction. + Value *LoopBodyArg; + User *OutlinedFnUser = OutlinedFn.getUniqueUndroppableUser(); + assert(OutlinedFnUser && + "Expected unique undroppable user of outlined function"); + CallInst *OutlinedFnCallInstruction = dyn_cast(OutlinedFnUser); + assert(OutlinedFnCallInstruction && "Expected outlined function call"); + assert((OutlinedFnCallInstruction->getParent() == Preheader) && + "Expected outlined function call to be located in loop preheader"); + // Check in case no argument structure has been passed. + if (OutlinedFnCallInstruction->arg_size() > 1) + LoopBodyArg = OutlinedFnCallInstruction->getArgOperand(1); + else + LoopBodyArg = Constant::getNullValue(Builder.getPtrTy()); + OutlinedFnCallInstruction->eraseFromParent(); + + createTargetLoopWorkshareCall(OMPIRBuilder, LoopType, Preheader, Ident, + LoopBodyArg, ParallelTaskPtr, TripCount, + OutlinedFn); + + for (auto &ToBeDeletedItem : ToBeDeleted) + ToBeDeletedItem->eraseFromParent(); + CLI->invalidate(); +} + +OpenMPIRBuilder::InsertPointTy +OpenMPIRBuilder::applyWorkshareLoopTarget(DebugLoc DL, CanonicalLoopInfo *CLI, + InsertPointTy AllocaIP, + WorksharingLoopType LoopType) { + uint32_t SrcLocStrSize; + Constant *SrcLocStr = getOrCreateSrcLocStr(DL, SrcLocStrSize); + Value *Ident = getOrCreateIdent(SrcLocStr, SrcLocStrSize); + + OutlineInfo OI; + OI.OuterAllocaBB = CLI->getPreheader(); + Function *OuterFn = CLI->getPreheader()->getParent(); + + // Instructions which need to be deleted at the end of code generation + SmallVector ToBeDeleted; + + OI.OuterAllocaBB = AllocaIP.getBlock(); + + // Mark the body loop as region which needs to be extracted + OI.EntryBB = CLI->getBody(); + OI.ExitBB = CLI->getLatch()->splitBasicBlock(CLI->getLatch()->begin(), + "omp.prelatch", true); + + // Prepare loop body for extraction + Builder.restoreIP({CLI->getPreheader(), CLI->getPreheader()->begin()}); + + // Insert new loop counter variable which will be used only in loop + // body. + AllocaInst *NewLoopCnt = Builder.CreateAlloca(CLI->getIndVarType(), 0, ""); + Instruction *NewLoopCntLoad = + Builder.CreateLoad(CLI->getIndVarType(), NewLoopCnt); + // New loop counter instructions are redundant in the loop preheader when + // code generation for workshare loop is finshed. That's why mark them as + // ready for deletion. + ToBeDeleted.push_back(NewLoopCntLoad); + ToBeDeleted.push_back(NewLoopCnt); + + // Analyse loop body region. Find all input variables which are used inside + // loop body region. + SmallPtrSet ParallelRegionBlockSet; + SmallVector Blocks; + OI.collectBlocks(ParallelRegionBlockSet, Blocks); + SmallVector BlocksT(ParallelRegionBlockSet.begin(), + ParallelRegionBlockSet.end()); + + CodeExtractorAnalysisCache CEAC(*OuterFn); + CodeExtractor Extractor(Blocks, + /* DominatorTree */ nullptr, + /* AggregateArgs */ true, + /* BlockFrequencyInfo */ nullptr, + /* BranchProbabilityInfo */ nullptr, + /* AssumptionCache */ nullptr, + /* AllowVarArgs */ true, + /* AllowAlloca */ true, + /* AllocationBlock */ CLI->getPreheader(), + /* Suffix */ ".omp_wsloop", + /* AggrArgsIn0AddrSpace */ true); + + BasicBlock *CommonExit = nullptr; + SetVector Inputs, Outputs, SinkingCands, HoistingCands; + + // Find allocas outside the loop body region which are used inside loop + // body + Extractor.findAllocas(CEAC, SinkingCands, HoistingCands, CommonExit); + + // We need to model loop body region as the function f(cnt, loop_arg). + // That's why we replace loop induction variable by the new counter + // which will be one of loop body function argument + for (auto Use = CLI->getIndVar()->user_begin(); + Use != CLI->getIndVar()->user_end(); ++Use) { + if (Instruction *Inst = dyn_cast(*Use)) { + if (ParallelRegionBlockSet.count(Inst->getParent())) { + Inst->replaceUsesOfWith(CLI->getIndVar(), NewLoopCntLoad); + } + } + } + // Make sure that loop counter variable is not merged into loop body + // function argument structure and it is passed as separate variable + OI.ExcludeArgsFromAggregate.push_back(NewLoopCntLoad); + + // PostOutline CB is invoked when loop body function is outlined and + // loop body is replaced by call to outlined function. We need to add + // call to OpenMP device rtl inside loop preheader. OpenMP device rtl + // function will handle loop control logic. + // + OI.PostOutlineCB = [=, ToBeDeletedVec = + std::move(ToBeDeleted)](Function &OutlinedFn) { + workshareLoopTargetCallback(this, CLI, Ident, OutlinedFn, ParallelTaskPtr, + ToBeDeletedVec, LoopType); + }; + addOutlineInfo(std::move(OI)); + return CLI->getAfterIP(); +} + OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::applyWorkshareLoop( DebugLoc DL, CanonicalLoopInfo *CLI, InsertPointTy AllocaIP, - bool NeedsBarrier, llvm::omp::ScheduleKind SchedKind, - llvm::Value *ChunkSize, bool HasSimdModifier, bool HasMonotonicModifier, - bool HasNonmonotonicModifier, bool HasOrderedClause) { + bool NeedsBarrier, omp::ScheduleKind SchedKind, Value *ChunkSize, + bool HasSimdModifier, bool HasMonotonicModifier, + bool HasNonmonotonicModifier, bool HasOrderedClause, + WorksharingLoopType LoopType) { + if (Config.isTargetDevice()) + return applyWorkshareLoopTarget(DL, CLI, AllocaIP, LoopType); OMPScheduleType EffectiveScheduleType = computeOpenMPScheduleType( SchedKind, ChunkSize, HasSimdModifier, HasMonotonicModifier, HasNonmonotonicModifier, HasOrderedClause); @@ -5568,8 +5799,8 @@ OpenMPIRBuilder::createAtomicWrite(const LocationDescription &Loc, if (!updateToLocation(Loc)) return Loc.IP; - Type *XTy = X.Var->getType(); - assert(XTy->isPointerTy() && "OMP Atomic expects a pointer to target memory"); + assert(X.Var->getType()->isPointerTy() && + "OMP Atomic expects a pointer to target memory"); Type *XElemTy = X.ElemTy; assert((XElemTy->isFloatingPointTy() || XElemTy->isIntegerTy() || XElemTy->isPointerTy()) && @@ -5580,14 +5811,11 @@ OpenMPIRBuilder::createAtomicWrite(const LocationDescription &Loc, XSt->setAtomic(AO); } else { // We need to bitcast and perform atomic op as integers - unsigned Addrspace = cast(XTy)->getAddressSpace(); IntegerType *IntCastTy = IntegerType::get(M.getContext(), XElemTy->getScalarSizeInBits()); - Value *XBCast = Builder.CreateBitCast( - X.Var, IntCastTy->getPointerTo(Addrspace), "atomic.dst.int.cast"); Value *ExprCast = Builder.CreateBitCast(Expr, IntCastTy, "atomic.src.int.cast"); - StoreInst *XSt = Builder.CreateStore(ExprCast, XBCast, X.IsVolatile); + StoreInst *XSt = Builder.CreateStore(ExprCast, X.Var, X.IsVolatile); XSt->setAtomic(AO); } diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index fabc79adbd33..bff64e3a15a2 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -3243,6 +3243,10 @@ void AssemblyWriter::printFunctionSummary(const FunctionSummary *FS) { Out << ", hotness: " << getHotnessName(Call.second.getHotness()); else if (Call.second.RelBlockFreq) Out << ", relbf: " << Call.second.RelBlockFreq; + // Follow the convention of emitting flags as a boolean value, but only + // emit if true to avoid unnecessary verbosity and test churn. + if (Call.second.HasTailCall) + Out << ", tail: 1"; Out << ")"; } Out << ")"; @@ -3672,6 +3676,27 @@ void AssemblyWriter::printGlobal(const GlobalVariable *GV) { printEscapedString(GV->getPartition(), Out); Out << '"'; } + if (auto CM = GV->getCodeModel()) { + Out << ", code_model \""; + switch (*CM) { + case CodeModel::Tiny: + Out << "tiny"; + break; + case CodeModel::Small: + Out << "small"; + break; + case CodeModel::Kernel: + Out << "kernel"; + break; + case CodeModel::Medium: + Out << "medium"; + break; + case CodeModel::Large: + Out << "large"; + break; + } + Out << '"'; + } using SanitizerMetadata = llvm::GlobalValue::SanitizerMetadata; if (GV->hasSanitizerMetadata()) { diff --git a/llvm/lib/IR/BasicBlock.cpp b/llvm/lib/IR/BasicBlock.cpp index 3ac5fafd887d..f364c56a42c5 100644 --- a/llvm/lib/IR/BasicBlock.cpp +++ b/llvm/lib/IR/BasicBlock.cpp @@ -770,6 +770,7 @@ void BasicBlock::flushTerminatorDbgValues() { // Transfer DPValues from the trailing position onto the terminator. Term->DbgMarker->absorbDebugValues(*TrailingDPValues, false); + TrailingDPValues->eraseFromParent(); deleteTrailingDPValues(); } @@ -813,6 +814,7 @@ void BasicBlock::spliceDebugInfoEmptyBlock(BasicBlock::iterator Dest, DPMarker *M = Dest->DbgMarker; M->absorbDebugValues(*SrcTrailingDPValues, InsertAtHead); + SrcTrailingDPValues->eraseFromParent(); Src->deleteTrailingDPValues(); return; } @@ -920,6 +922,7 @@ void BasicBlock::spliceDebugInfoImpl(BasicBlock::iterator Dest, BasicBlock *Src, // Use this flag to signal the abnormal case, where we don't want to copy the // DPValues ahead of the "Last" position. bool ReadFromTail = !Last.getTailBit(); + bool LastIsEnd = (Last == Src->end()); /* Here's an illustration of what we're about to do. We have two blocks, this @@ -995,12 +998,16 @@ void BasicBlock::spliceDebugInfoImpl(BasicBlock::iterator Dest, BasicBlock *Src, DPMarker *OntoDest = getMarker(Dest); DPMarker *FromLast = Src->getMarker(Last); OntoDest->absorbDebugValues(*FromLast, true); + if (LastIsEnd) { + FromLast->eraseFromParent(); + Src->deleteTrailingDPValues(); + } } // If we're _not_ reading from the head of First, i.e. the "++++" DPValues, // move their markers onto Last. They remain in the Src block. No action // needed. - if (!ReadFromHead) { + if (!ReadFromHead && First->hasDbgValues()) { DPMarker *OntoLast = Src->createMarker(Last); DPMarker *FromFirst = Src->createMarker(First); OntoLast->absorbDebugValues(*FromFirst, @@ -1030,6 +1037,7 @@ void BasicBlock::spliceDebugInfoImpl(BasicBlock::iterator Dest, BasicBlock *Src, DPMarker *TrailingDPValues = getTrailingDPValues(); if (TrailingDPValues) { FirstMarker->absorbDebugValues(*TrailingDPValues, true); + TrailingDPValues->eraseFromParent(); deleteTrailingDPValues(); } } diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp index bc55d5b48527..a38b912164b1 100644 --- a/llvm/lib/IR/Constants.cpp +++ b/llvm/lib/IR/Constants.cpp @@ -2556,6 +2556,32 @@ Constant *ConstantExpr::getBinOpIdentity(unsigned Opcode, Type *Ty, } } +Constant *ConstantExpr::getIntrinsicIdentity(Intrinsic::ID ID, Type *Ty) { + switch (ID) { + case Intrinsic::umax: + return Constant::getNullValue(Ty); + case Intrinsic::umin: + return Constant::getAllOnesValue(Ty); + case Intrinsic::smax: + return Constant::getIntegerValue( + Ty, APInt::getSignedMinValue(Ty->getIntegerBitWidth())); + case Intrinsic::smin: + return Constant::getIntegerValue( + Ty, APInt::getSignedMaxValue(Ty->getIntegerBitWidth())); + default: + return nullptr; + } +} + +Constant *ConstantExpr::getIdentity(Instruction *I, Type *Ty, + bool AllowRHSConstant, bool NSZ) { + if (I->isBinaryOp()) + return getBinOpIdentity(I->getOpcode(), Ty, AllowRHSConstant, NSZ); + if (IntrinsicInst *II = dyn_cast(I)) + return getIntrinsicIdentity(II->getIntrinsicID(), Ty); + return nullptr; +} + Constant *ConstantExpr::getBinOpAbsorber(unsigned Opcode, Type *Ty) { switch (Opcode) { default: diff --git a/llvm/lib/IR/Core.cpp b/llvm/lib/IR/Core.cpp index e07664f8a17c..7832028bf367 100644 --- a/llvm/lib/IR/Core.cpp +++ b/llvm/lib/IR/Core.cpp @@ -3464,6 +3464,16 @@ void LLVMSetNNeg(LLVMValueRef NonNegInst, LLVMBool IsNonNeg) { cast(P)->setNonNeg(IsNonNeg); } +LLVMBool LLVMGetIsDisjoint(LLVMValueRef Inst) { + Value *P = unwrap(Inst); + return cast(P)->isDisjoint(); +} + +void LLVMSetIsDisjoint(LLVMValueRef Inst, LLVMBool IsDisjoint) { + Value *P = unwrap(Inst); + cast(P)->setIsDisjoint(IsDisjoint); +} + /*--.. Memory ..............................................................--*/ LLVMValueRef LLVMBuildMalloc(LLVMBuilderRef B, LLVMTypeRef Ty, diff --git a/llvm/lib/IR/Globals.cpp b/llvm/lib/IR/Globals.cpp index 7bd4503a689e..51bdbeb0abf2 100644 --- a/llvm/lib/IR/Globals.cpp +++ b/llvm/lib/IR/Globals.cpp @@ -482,6 +482,8 @@ void GlobalVariable::copyAttributesFrom(const GlobalVariable *Src) { GlobalObject::copyAttributesFrom(Src); setExternallyInitialized(Src->isExternallyInitialized()); setAttributes(Src->getAttributes()); + if (auto CM = Src->getCodeModel()) + setCodeModel(*CM); } void GlobalVariable::dropAllReferences() { @@ -489,6 +491,15 @@ void GlobalVariable::dropAllReferences() { clearMetadata(); } +void GlobalVariable::setCodeModel(CodeModel::Model CM) { + unsigned CodeModelData = static_cast(CM) + 1; + unsigned OldData = getGlobalValueSubClassData(); + unsigned NewData = (OldData & ~(CodeModelMask << CodeModelShift)) | + (CodeModelData << CodeModelShift); + setGlobalValueSubClassData(NewData); + assert(getCodeModel() == CM && "Code model representation error!"); +} + //===----------------------------------------------------------------------===// // GlobalAlias Implementation //===----------------------------------------------------------------------===// diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp index 4b5349856b8d..717e33f1857b 100644 --- a/llvm/lib/IR/Instruction.cpp +++ b/llvm/lib/IR/Instruction.cpp @@ -200,8 +200,9 @@ void Instruction::moveBeforeImpl(BasicBlock &BB, InstListType::iterator I, // If we've been given the "Preserve" flag, then just move the DPValues with // the instruction, no more special handling needed. if (BB.IsNewDbgInfoFormat && DbgMarker && !Preserve) { - if (I != this->getIterator()) { - // "this" is definitely moving; detach any existing DPValues. + if (I != this->getIterator() || InsertAtHead) { + // "this" is definitely moving in the list, or it's moving ahead of its + // attached DPValues. Detach any existing DPValues. handleMarkerRemoval(); } } @@ -217,7 +218,7 @@ void Instruction::moveBeforeImpl(BasicBlock &BB, InstListType::iterator I, // If we're inserting at point I, and not in front of the DPValues attached // there, then we should absorb the DPValues attached to I. - if (!InsertAtHead) + if (NextMarker && !InsertAtHead) DbgMarker->absorbDebugValues(*NextMarker, false); } @@ -1091,6 +1092,8 @@ const DebugLoc &Instruction::getStableDebugLoc() const { } bool Instruction::isAssociative() const { + if (auto *II = dyn_cast(this)) + return II->isAssociative(); unsigned Opcode = getOpcode(); if (isAssociative(Opcode)) return true; diff --git a/llvm/lib/IR/Metadata.cpp b/llvm/lib/IR/Metadata.cpp index 415e256c817b..7bc25e30b893 100644 --- a/llvm/lib/IR/Metadata.cpp +++ b/llvm/lib/IR/Metadata.cpp @@ -249,8 +249,13 @@ SmallVector ReplaceableMetadataImpl::getAllDPValueUsers() { continue; DPVUsersWithID.push_back(&UseMap[Pair.first]); } + // Order DPValue users in reverse-creation order. Normal dbg.value users + // of MetadataAsValues are ordered by their UseList, i.e. reverse order of + // when they were added: we need to replicate that here. The structure of + // debug-info output depends on the ordering of intrinsics, thus we need + // to keep them consistent for comparisons sake. llvm::sort(DPVUsersWithID, [](auto UserA, auto UserB) { - return UserA->second < UserB->second; + return UserA->second > UserB->second; }); SmallVector DPVUsers; for (auto UserWithID : DPVUsersWithID) diff --git a/llvm/lib/MC/MCObjectFileInfo.cpp b/llvm/lib/MC/MCObjectFileInfo.cpp index 1b30645cea3c..a79759557b2e 100644 --- a/llvm/lib/MC/MCObjectFileInfo.cpp +++ b/llvm/lib/MC/MCObjectFileInfo.cpp @@ -933,10 +933,16 @@ void MCObjectFileInfo::initXCOFFMCObjectFileInfo(const Triple &T) { // the ABI or object file format, but various tools rely on the section // name being empty (considering named symbols to be "user symbol names"). TextSection = Ctx->getXCOFFSection( - "", SectionKind::getText(), + "..text..", // Use a non-null name to work around an AIX assembler bug... + SectionKind::getText(), XCOFF::CsectProperties(XCOFF::StorageMappingClass::XMC_PR, XCOFF::XTY_SD), /* MultiSymbolsAllowed*/ true); + // ... but use a null name when generating the symbol table. + MCSectionXCOFF *TS = static_cast(TextSection); + TS->getQualNameSymbol()->setSymbolTableName(""); + TS->setSymbolTableName(""); + DataSection = Ctx->getXCOFFSection( ".data", SectionKind::getData(), XCOFF::CsectProperties(XCOFF::StorageMappingClass::XMC_RW, XCOFF::XTY_SD), diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp index 2371cb238441..0062d0835314 100644 --- a/llvm/lib/MC/MCStreamer.cpp +++ b/llvm/lib/MC/MCStreamer.cpp @@ -1190,10 +1190,7 @@ void MCStreamer::emitXCOFFSymbolLinkageWithVisibility(MCSymbol *Symbol, } void MCStreamer::emitXCOFFRenameDirective(const MCSymbol *Name, - StringRef Rename) { - llvm_unreachable("emitXCOFFRenameDirective is only supported on " - "XCOFF targets"); -} + StringRef Rename) {} void MCStreamer::emitXCOFFRefDirective(const MCSymbol *Symbol) { llvm_unreachable("emitXCOFFRefDirective is only supported on XCOFF targets"); diff --git a/llvm/lib/MC/MCXCOFFStreamer.cpp b/llvm/lib/MC/MCXCOFFStreamer.cpp index 8585416cd081..458b4be61983 100644 --- a/llvm/lib/MC/MCXCOFFStreamer.cpp +++ b/llvm/lib/MC/MCXCOFFStreamer.cpp @@ -96,6 +96,13 @@ void MCXCOFFStreamer::emitXCOFFRefDirective(const MCSymbol *Symbol) { DF->getFixups().push_back(Fixup); } +void MCXCOFFStreamer::emitXCOFFRenameDirective(const MCSymbol *Name, + StringRef Rename) { + const MCSymbolXCOFF *Symbol = cast(Name); + if (!Symbol->hasRename()) + report_fatal_error("Only explicit .rename is supported for XCOFF."); +} + void MCXCOFFStreamer::emitXCOFFExceptDirective(const MCSymbol *Symbol, const MCSymbol *Trap, unsigned Lang, unsigned Reason, diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 729b050c5d1d..a5f9b5424358 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -79,6 +79,7 @@ #include "llvm/CodeGen/HardwareLoops.h" #include "llvm/CodeGen/SafeStack.h" #include "llvm/CodeGen/TypePromotion.h" +#include "llvm/CodeGen/WasmEHPrepare.h" #include "llvm/CodeGen/WinEHPrepare.h" #include "llvm/IR/DebugInfo.h" #include "llvm/IR/Dominators.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 37c0d6c29b42..7462704ec2df 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -423,6 +423,7 @@ FUNCTION_PASS("view-dom", DomViewer()) FUNCTION_PASS("view-dom-only", DomOnlyViewer()) FUNCTION_PASS("view-post-dom", PostDomViewer()) FUNCTION_PASS("view-post-dom-only", PostDomOnlyViewer()) +FUNCTION_PASS("wasm-eh-prepare", WasmEHPreparePass()) #undef FUNCTION_PASS #ifndef FUNCTION_PASS_WITH_PARAMS diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 7a2572da8ea0..caab59201a8d 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -992,6 +992,16 @@ void AArch64FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero, } } +static void getLiveRegsForEntryMBB(LivePhysRegs &LiveRegs, + const MachineBasicBlock &MBB) { + const MachineFunction *MF = MBB.getParent(); + LiveRegs.addLiveIns(MBB); + // Mark callee saved registers as used so we will not choose them. + const MCPhysReg *CSRegs = MF->getRegInfo().getCalleeSavedRegs(); + for (unsigned i = 0; CSRegs[i]; ++i) + LiveRegs.addReg(CSRegs[i]); +} + // Find a scratch register that we can use at the start of the prologue to // re-align the stack pointer. We avoid using callee-save registers since they // may appear to be free when this is called from canUseAsPrologue (during @@ -1013,12 +1023,7 @@ static unsigned findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB) { const AArch64Subtarget &Subtarget = MF->getSubtarget(); const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo(); LivePhysRegs LiveRegs(TRI); - LiveRegs.addLiveIns(*MBB); - - // Mark callee saved registers as used so we will not choose them. - const MCPhysReg *CSRegs = MF->getRegInfo().getCalleeSavedRegs(); - for (unsigned i = 0; CSRegs[i]; ++i) - LiveRegs.addReg(CSRegs[i]); + getLiveRegsForEntryMBB(LiveRegs, *MBB); // Prefer X9 since it was historically used for the prologue scratch reg. const MachineRegisterInfo &MRI = MF->getRegInfo(); @@ -1039,6 +1044,19 @@ bool AArch64FrameLowering::canUseAsPrologue( const AArch64Subtarget &Subtarget = MF->getSubtarget(); const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); const AArch64TargetLowering *TLI = Subtarget.getTargetLowering(); + const AArch64FunctionInfo *AFI = MF->getInfo(); + + if (AFI->hasSwiftAsyncContext()) { + const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo(); + const MachineRegisterInfo &MRI = MF->getRegInfo(); + LivePhysRegs LiveRegs(TRI); + getLiveRegsForEntryMBB(LiveRegs, MBB); + // The StoreSwiftAsyncContext clobbers X16 and X17. Make sure they are + // available. + if (!LiveRegs.available(MRI, AArch64::X16) || + !LiveRegs.available(MRI, AArch64::X17)) + return false; + } // Don't need a scratch register if we're not going to re-align the stack or // emit stack probes. diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 2f49e9a6b37c..d05d22a7164e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -327,7 +327,7 @@ public: } template - bool ImmToTile(SDValue N, SDValue &Imm) { + bool ImmToReg(SDValue N, SDValue &Imm) { if (auto *CI = dyn_cast(N)) { uint64_t C = CI->getZExtValue(); @@ -404,6 +404,9 @@ public: return SelectSVERegRegAddrMode(N, Scale, Base, Offset); } + void SelectMultiVectorLuti(SDNode *Node, unsigned NumOutVecs, unsigned Opc, + uint32_t MaxImm); + template bool SelectSMETileSlice(SDValue N, SDValue &Vector, SDValue &Offset) { return SelectSMETileSlice(N, MaxIdx, Vector, Offset, Scale); @@ -1864,6 +1867,34 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N, unsigned NumVecs, SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode); } +void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node, + unsigned NumOutVecs, + unsigned Opc, uint32_t MaxImm) { + if (ConstantSDNode *Imm = dyn_cast(Node->getOperand(4))) + if (Imm->getZExtValue() > MaxImm) + return; + + SDValue ZtValue; + if (!ImmToReg(Node->getOperand(2), ZtValue)) + return; + SDValue Ops[] = {ZtValue, Node->getOperand(3), Node->getOperand(4)}; + SDLoc DL(Node); + EVT VT = Node->getValueType(0); + + SDNode *Instruction = + CurDAG->getMachineNode(Opc, DL, {MVT::Untyped, MVT::Other}, Ops); + SDValue SuperReg = SDValue(Instruction, 0); + + for (unsigned I = 0; I < NumOutVecs; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg( + AArch64::zsub0 + I, DL, VT, SuperReg)); + + // Copy chain + unsigned ChainIdx = NumOutVecs; + ReplaceUses(SDValue(Node, ChainIdx), SDValue(Instruction, 1)); + CurDAG->RemoveDeadNode(Node); +} + void AArch64DAGToDAGISel::SelectClamp(SDNode *N, unsigned NumVecs, unsigned Op) { SDLoc DL(N); @@ -5072,6 +5103,41 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) { MF.getInfo()->setHasSwiftAsyncContext(true); return; } + case Intrinsic::aarch64_sme_luti2_lane_zt_x4: { + if (auto Opc = SelectOpcodeFromVT( + Node->getValueType(0), + {AArch64::LUTI2_4ZTZI_B, AArch64::LUTI2_4ZTZI_H, + AArch64::LUTI2_4ZTZI_S})) + // Second Immediate must be <= 3: + SelectMultiVectorLuti(Node, 4, Opc, 3); + return; + } + case Intrinsic::aarch64_sme_luti4_lane_zt_x4: { + if (auto Opc = SelectOpcodeFromVT( + Node->getValueType(0), + {0, AArch64::LUTI4_4ZTZI_H, AArch64::LUTI4_4ZTZI_S})) + // Second Immediate must be <= 1: + SelectMultiVectorLuti(Node, 4, Opc, 1); + return; + } + case Intrinsic::aarch64_sme_luti2_lane_zt_x2: { + if (auto Opc = SelectOpcodeFromVT( + Node->getValueType(0), + {AArch64::LUTI2_2ZTZI_B, AArch64::LUTI2_2ZTZI_H, + AArch64::LUTI2_2ZTZI_S})) + // Second Immediate must be <= 7: + SelectMultiVectorLuti(Node, 2, Opc, 7); + return; + } + case Intrinsic::aarch64_sme_luti4_lane_zt_x2: { + if (auto Opc = SelectOpcodeFromVT( + Node->getValueType(0), + {AArch64::LUTI4_2ZTZI_B, AArch64::LUTI4_2ZTZI_H, + AArch64::LUTI4_2ZTZI_S})) + // Second Immediate must be <= 3: + SelectMultiVectorLuti(Node, 2, Opc, 3); + return; + } } } break; case ISD::INTRINSIC_WO_CHAIN: { diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b6a16217dfae..f36607b03e76 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -16070,6 +16070,20 @@ bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL, AM.Scale); } +// Check whether the 2 offsets belong to the same imm24 range, and their high +// 12bits are same, then their high part can be decoded with the offset of add. +int64_t +AArch64TargetLowering::getPreferredLargeGEPBaseOffset(int64_t MinOffset, + int64_t MaxOffset) const { + int64_t HighPart = MinOffset & ~0xfffULL; + if (MinOffset >> 12 == MaxOffset >> 12 && isLegalAddImmediate(HighPart)) { + // Rebase the value to an integer multiple of imm12. + return HighPart; + } + + return 0; +} + bool AArch64TargetLowering::shouldConsiderGEPOffsetSplit() const { // Consider splitting large offset of struct or array. return true; @@ -24287,10 +24301,7 @@ void AArch64TargetLowering::ReplaceExtractSubVectorResults( // Create an even/odd pair of X registers holding integer value V. static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V) { SDLoc dl(V.getNode()); - SDValue VLo = DAG.getAnyExtOrTrunc(V, dl, MVT::i64); - SDValue VHi = DAG.getAnyExtOrTrunc( - DAG.getNode(ISD::SRL, dl, MVT::i128, V, DAG.getConstant(64, dl, MVT::i64)), - dl, MVT::i64); + auto [VLo, VHi] = DAG.SplitScalar(V, dl, MVT::i64, MVT::i64); if (DAG.getDataLayout().isBigEndian()) std::swap (VLo, VHi); SDValue RegClass = diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 3c8479e1f6e3..6ddbcd41dcb7 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -699,6 +699,9 @@ public: unsigned AS, Instruction *I = nullptr) const override; + int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, + int64_t MaxOffset) const override; + /// Return true if an FMA operation is faster than a pair of fmul and fadd /// instructions. fmuladd intrinsics will be expanded to FMAs when this method /// returns true, otherwise fmuladd is expanded to fmul + fadd. diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 6f4c6f5ad073..93b8295f4f3e 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -4238,8 +4238,9 @@ static bool shouldClusterFI(const MachineFrameInfo &MFI, int FI1, /// /// Only called for LdSt for which getMemOperandWithOffset returns true. bool AArch64InstrInfo::shouldClusterMemOps( - ArrayRef BaseOps1, - ArrayRef BaseOps2, unsigned ClusterSize, + ArrayRef BaseOps1, int64_t OpOffset1, + bool OffsetIsScalable1, ArrayRef BaseOps2, + int64_t OpOffset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const { assert(BaseOps1.size() == 1 && BaseOps2.size() == 1); const MachineOperand &BaseOp1 = *BaseOps1.front(); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index b259efb9f2e7..e97ff0a9758d 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -179,7 +179,9 @@ public: int64_t &MinOffset, int64_t &MaxOffset); bool shouldClusterMemOps(ArrayRef BaseOps1, + int64_t Offset1, bool OffsetIsScalable1, ArrayRef BaseOps2, + int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override; diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index a58799116003..738a52eebad2 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -549,11 +549,11 @@ defm STR_TX : sme2_spill_fill_vector<"str", 0b11111100, int_aarch64_sme_str_zt>; def MOVT_XTI : sme2_movt_zt_to_scalar<"movt", 0b0011111>; def MOVT_TIX : sme2_movt_scalar_to_zt<"movt", 0b0011111>; -defm LUTI2_ZTZI : sme2_luti2_vector_index<"luti2">; +defm LUTI2_ZTZI : sme2_luti2_vector_index<"luti2", int_aarch64_sme_luti2_lane_zt>; defm LUTI2_2ZTZI : sme2_luti2_vector_vg2_index<"luti2">; defm LUTI2_4ZTZI : sme2_luti2_vector_vg4_index<"luti2">; -defm LUTI4_ZTZI : sme2_luti4_vector_index<"luti4">; +defm LUTI4_ZTZI : sme2_luti4_vector_index<"luti4", int_aarch64_sme_luti4_lane_zt>; defm LUTI4_2ZTZI : sme2_luti4_vector_vg2_index<"luti4">; defm LUTI4_4ZTZI : sme2_luti4_vector_vg4_index<"luti4">; diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 408b897070af..4f8917618ea4 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -10,12 +10,12 @@ // //===----------------------------------------------------------------------===// -def imm_to_tile8 : ComplexPattern", []>; -def imm_to_tile16 : ComplexPattern", []>; -def imm_to_tile32 : ComplexPattern", []>; -def imm_to_tile64 : ComplexPattern", []>; -def imm_to_tile128 : ComplexPattern", []>; -def imm_to_zt : ComplexPattern", []>; +def imm_to_tile8 : ComplexPattern", []>; +def imm_to_tile16 : ComplexPattern", []>; +def imm_to_tile32 : ComplexPattern", []>; +def imm_to_tile64 : ComplexPattern", []>; +def imm_to_tile128 : ComplexPattern", []>; +def imm_to_zt : ComplexPattern", []>; def tileslice8 : ComplexPattern", []>; def tileslice16 : ComplexPattern", []>; @@ -3227,28 +3227,54 @@ class sme2_luti_vector_index sz, bits<7> opc, RegisterOperand vector_ty, class sme2_luti2_vector_index sz, RegisterOperand vector_ty, string mnemonic> - : sme2_luti_vector_index { + : sme2_luti_vector_index { bits<4> i; let Inst{17-14} = i; } -multiclass sme2_luti2_vector_index { +multiclass sme2_luti2_vector_index { def _B : sme2_luti2_vector_index<0b00, ZPR8, mnemonic>; def _H : sme2_luti2_vector_index<0b01, ZPR16, mnemonic>; def _S : sme2_luti2_vector_index<0b10, ZPR32, mnemonic>; + + def : Pat<(nxv16i8 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))), + (!cast(NAME # _B) $zt, nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))>; + def : Pat<(nxv8i16 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))), + (!cast(NAME # _H) $zt, nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))>; + def : Pat<(nxv4i32 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))), + (!cast(NAME # _S) $zt, nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))>; + def : Pat<(nxv8f16 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))), + (!cast(NAME # _H) $zt, nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))>; + def : Pat<(nxv8bf16 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))), + (!cast(NAME # _H) $zt, nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))>; + def : Pat<(nxv4f32 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))), + (!cast(NAME # _S) $zt, nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))>; } class sme2_luti4_vector_index sz, RegisterOperand vector_ty, string mnemonic> - : sme2_luti_vector_index { + : sme2_luti_vector_index { bits<3> i; let Inst{16-14} = i; } -multiclass sme2_luti4_vector_index { +multiclass sme2_luti4_vector_index { def _B : sme2_luti4_vector_index<0b00, ZPR8, mnemonic>; def _H : sme2_luti4_vector_index<0b01, ZPR16, mnemonic>; def _S : sme2_luti4_vector_index<0b10, ZPR32, mnemonic>; + + def : Pat<(nxv16i8 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))), + (!cast(NAME # _B) $zt, nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))>; + def : Pat<(nxv8i16 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))), + (!cast(NAME # _H) $zt, nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))>; + def : Pat<(nxv4i32 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))), + (!cast(NAME # _S) $zt, nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))>; + def : Pat<(nxv8f16 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))), + (!cast(NAME # _H) $zt, nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))>; + def : Pat<(nxv8bf16 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))), + (!cast(NAME # _H) $zt, nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))>; + def : Pat<(nxv4f32 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))), + (!cast(NAME # _S) $zt, nxv16i8:$zn, (i32 VectorIndexH32b_timm:$imm))>; } // SME2 lookup table expand two contiguous registers diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index f7315ecb9fa6..799e102d5617 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -1460,6 +1460,8 @@ def FeatureISAVersion12 : FeatureSet< FeatureExtendedImageInsts, FeaturePackedTID, FeatureVcmpxPermlaneHazard, + FeatureSALUFloatInsts, + FeatureVGPRSingleUseHintInsts, FeatureMADIntraFwdBug]>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index eb30f31af6d6..4bf1f1357b69 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -939,6 +939,17 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, ProgInfo.Occupancy = STM.computeOccupancy(MF.getFunction(), ProgInfo.LDSSize, ProgInfo.NumSGPRsForWavesPerEU, ProgInfo.NumVGPRsForWavesPerEU); + const auto [MinWEU, MaxWEU] = + AMDGPU::getIntegerPairAttribute(F, "amdgpu-waves-per-eu", {0, 0}, true); + if (ProgInfo.Occupancy < MinWEU) { + DiagnosticInfoOptimizationFailure Diag( + F, F.getSubprogram(), + "failed to meet occupancy target given by 'amdgpu-waves-per-eu' in " + "'" + + F.getName() + "': desired occupancy was " + Twine(MinWEU) + + ", final occupancy is " + Twine(ProgInfo.Occupancy)); + F.getContext().diagnose(Diag); + } } static unsigned getRsrcReg(CallingConv::ID CallConv) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h index 06d4a6c0d027..25c0b4953ab7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h @@ -90,6 +90,11 @@ public: bool isChainFunction() const { return IsChainFunction; } + // The stack is empty upon entry to this function. + bool isBottomOfStack() const { + return isEntryFunction() || isChainFunction(); + } + bool hasNoSignedZerosFPMath() const { return NoSignedZerosFPMath; } diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 649ca9d3e748..092845d391a3 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -4199,8 +4199,9 @@ bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst, return true; Error(getSMEMOffsetLoc(Operands), - (isVI() || IsBuffer) ? "expected a 20-bit unsigned offset" : - "expected a 21-bit signed offset"); + isGFX12Plus() ? "expected a 24-bit signed offset" + : (isVI() || IsBuffer) ? "expected a 20-bit unsigned offset" + : "expected a 21-bit signed offset"); return false; } diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 6f7dd8cd947f..3175f6358a04 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -91,9 +91,11 @@ static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) { auto DAsm = static_cast(Decoder); int64_t Offset; - if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. + if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. + Offset = SignExtend64<24>(Imm); + } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. Offset = Imm & 0xFFFFF; - } else { // GFX9+ supports 21-bit signed offsets. + } else { // GFX9+ supports 21-bit signed offsets. Offset = SignExtend64<21>(Imm); } return addOperand(Inst, MCOperand::createImm(Offset)); @@ -610,6 +612,10 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, Address, CS); if (Res) break; + Res = tryDecodeInst(DecoderTableGFX1232, MI, DW, Address, CS); + if (Res) + break; + if (Bytes.size() < 4) break; const uint64_t QW = ((uint64_t)eatBytes(Bytes) << 32) | DW; @@ -637,6 +643,10 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); if (Res) break; + Res = tryDecodeInst(DecoderTableGFX1264, MI, QW, Address, CS); + if (Res) + break; + Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, Address, CS); if (Res) diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index 659ff75e13d0..47dc59e77dc4 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -478,6 +478,9 @@ enum Id { // HwRegCode, (6) [5:0] ID_GPR_ALLOC = 5, ID_LDS_ALLOC = 6, ID_IB_STS = 7, + ID_PERF_SNAPSHOT_DATA_gfx12 = 10, + ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11, + ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12, ID_MEM_BASES = 15, ID_TBA_LO = 16, ID_TBA_HI = 17, @@ -489,12 +492,23 @@ enum Id { // HwRegCode, (6) [5:0] ID_HW_ID1 = 23, ID_HW_ID2 = 24, ID_POPS_PACKER = 25, - ID_PERF_SNAPSHOT_DATA = 27, + ID_PERF_SNAPSHOT_DATA_gfx11 = 27, ID_SHADER_CYCLES = 29, - - // Register numbers reused in GFX11+ - ID_PERF_SNAPSHOT_PC_LO = 18, - ID_PERF_SNAPSHOT_PC_HI = 19, + ID_SHADER_CYCLES_HI = 30, + ID_DVGPR_ALLOC_LO = 31, + ID_DVGPR_ALLOC_HI = 32, + + // Register numbers reused in GFX11 + ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18, + ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19, + + // Register numbers reused in GFX12+ + ID_STATE_PRIV = 4, + ID_PERF_SNAPSHOT_DATA1 = 15, + ID_PERF_SNAPSHOT_DATA2 = 16, + ID_EXCP_FLAG_PRIV = 17, + ID_EXCP_FLAG_USER = 18, + ID_TRAP_CTRL = 19, // GFX940 specific registers ID_XCC_ID = 20, diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 53ab5da01353..a7f4d63229b7 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1322,7 +1322,9 @@ bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II, } } -bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const { +bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM, + unsigned AddrSpace, + uint64_t FlatVariant) const { if (!Subtarget->hasFlatInstOffsets()) { // Flat instructions do not have offsets, and only have the register // address. @@ -1330,29 +1332,27 @@ bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const { } return AM.Scale == 0 && - (AM.BaseOffs == 0 || - Subtarget->getInstrInfo()->isLegalFLATOffset( - AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS, SIInstrFlags::FLAT)); + (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset( + AM.BaseOffs, AddrSpace, FlatVariant)); } bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const { if (Subtarget->hasFlatGlobalInsts()) - return AM.Scale == 0 && - (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset( - AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS, - SIInstrFlags::FlatGlobal)); + return isLegalFlatAddressingMode(AM, AMDGPUAS::GLOBAL_ADDRESS, + SIInstrFlags::FlatGlobal); if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) { - // Assume the we will use FLAT for all global memory accesses - // on VI. - // FIXME: This assumption is currently wrong. On VI we still use - // MUBUF instructions for the r + i addressing mode. As currently - // implemented, the MUBUF instructions only work on buffer < 4GB. - // It may be possible to support > 4GB buffers with MUBUF instructions, - // by setting the stride value in the resource descriptor which would - // increase the size limit to (stride * 4GB). However, this is risky, - // because it has never been validated. - return isLegalFlatAddressingMode(AM); + // Assume the we will use FLAT for all global memory accesses + // on VI. + // FIXME: This assumption is currently wrong. On VI we still use + // MUBUF instructions for the r + i addressing mode. As currently + // implemented, the MUBUF instructions only work on buffer < 4GB. + // It may be possible to support > 4GB buffers with MUBUF instructions, + // by setting the stride value in the resource descriptor which would + // increase the size limit to (stride * 4GB). However, this is risky, + // because it has never been validated. + return isLegalFlatAddressingMode(AM, AMDGPUAS::FLAT_ADDRESS, + SIInstrFlags::FLAT); } return isLegalMUBUFAddressingMode(AM); @@ -1449,7 +1449,10 @@ bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL, } if (AS == AMDGPUAS::PRIVATE_ADDRESS) - return isLegalMUBUFAddressingMode(AM); + return Subtarget->enableFlatScratch() + ? isLegalFlatAddressingMode(AM, AMDGPUAS::PRIVATE_ADDRESS, + SIInstrFlags::FlatScratch) + : isLegalMUBUFAddressingMode(AM); if (AS == AMDGPUAS::LOCAL_ADDRESS || (AS == AMDGPUAS::REGION_ADDRESS && Subtarget->hasGDS())) { @@ -1475,7 +1478,8 @@ bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL, // computation. We don't have instructions that compute pointers with any // addressing modes, so treat them as having no offset like flat // instructions. - return isLegalFlatAddressingMode(AM); + return isLegalFlatAddressingMode(AM, AMDGPUAS::FLAT_ADDRESS, + SIInstrFlags::FLAT); } // Assume a user alias of global for unknown address spaces. diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index 746a88c5ea13..c9cc149218a9 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -221,7 +221,8 @@ private: SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; - bool isLegalFlatAddressingMode(const AddrMode &AM) const; + bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace, + uint64_t FlatVariant) const; bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; unsigned isCFIntrinsic(const SDNode *Intr) const; diff --git a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp index 50f8ad4433c6..442ae4dd7b34 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp @@ -232,7 +232,10 @@ public: // scheduler it limits the size of the cluster to avoid increasing // register pressure too much, but this pass runs after register // allocation so there is no need for that kind of limit. - !SII->shouldClusterMemOps(CI.BaseOps, BaseOps, 2, 2)))) { + // We also lie about the Offset and OffsetIsScalable parameters, + // as they aren't used in the SIInstrInfo implementation. + !SII->shouldClusterMemOps(CI.BaseOps, 0, false, BaseOps, 0, false, + 2, 2)))) { // Finish the current clause. Changed |= emitClause(CI, SII); CI = ClauseInfo(); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index b5b456d69125..0a06fa88b6b1 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -541,7 +541,9 @@ static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, } bool SIInstrInfo::shouldClusterMemOps(ArrayRef BaseOps1, + int64_t Offset1, bool OffsetIsScalable1, ArrayRef BaseOps2, + int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const { // If the mem ops (to be clustered) do not have the same base ptr, then they diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index e388b5550cb1..0ce31ac6d54e 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -234,7 +234,9 @@ public: const TargetRegisterInfo *TRI) const final; bool shouldClusterMemOps(ArrayRef BaseOps1, + int64_t Offset1, bool OffsetIsScalable1, ArrayRef BaseOps2, + int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override; diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 7645c6da0338..f8eb67199f62 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -519,7 +519,7 @@ int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI) { if (ScavengeFI) return *ScavengeFI; - if (isEntryFunction() || isChainFunction()) { + if (isBottomOfStack()) { ScavengeFI = MFI.CreateFixedObject( TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false); } else { diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index a7b0dfda7852..1ce596de0403 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -503,7 +503,7 @@ Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const { // functions, but never actually want to reference it when accessing our own // frame. If we need a frame pointer we use it, but otherwise we can just use // an immediate "0" which we represent by returning NoRegister. - if (FuncInfo->isEntryFunction() || FuncInfo->isChainFunction()) { + if (FuncInfo->isBottomOfStack()) { return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg() : Register(); } return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg() @@ -738,7 +738,7 @@ bool SIRegisterInfo::shouldRealignStack(const MachineFunction &MF) const { // FIXME: Should be able to specify the entry frame alignment per calling // convention instead. - if (Info->isEntryFunction() || Info->isChainFunction()) + if (Info->isBottomOfStack()) return false; return TargetRegisterInfo::shouldRealignStack(MF); @@ -1649,7 +1649,7 @@ void SIRegisterInfo::buildSpillLoadStore( if (UseVGPROffset && ScratchOffsetReg) { MIB.addReg(ScratchOffsetReg); } else { - assert(FuncInfo->isEntryFunction() || FuncInfo->isChainFunction()); + assert(FuncInfo->isBottomOfStack()); MIB.addImm(0); } } @@ -2424,7 +2424,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, bool IsMUBUF = TII->isMUBUF(*MI); - if (!IsMUBUF && !MFI->isEntryFunction() && !MFI->isChainFunction()) { + if (!IsMUBUF && !MFI->isBottomOfStack()) { // Convert to a swizzled stack address by scaling by the wave size. // In an entry function/kernel the offset is already swizzled. bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index 6235965b6e16..c18846483cf9 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -211,6 +211,23 @@ class SM_WaveId_Pseudo : SM_Pseudo< let has_sbase = 0; } +class SM_Prefetch_Pseudo + : SM_Pseudo { + // Mark prefetches as both load and store to prevent reordering with loads + // and stores. This is also needed for pattern to match prefetch intrinsic. + let mayLoad = 1; + let mayStore = 1; + let has_glc = 0; + let LGKM_CNT = 0; + let has_sbase = hasSBase; + let ScalarStore = 0; + let has_offset = 1; + let has_soffset = 1; + let PseudoInstr = opName; +} + //===----------------------------------------------------------------------===// // Scalar Atomic Memory Classes //===----------------------------------------------------------------------===// @@ -415,6 +432,16 @@ defm S_DCACHE_DISCARD : SM_Pseudo_Discards; defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards; } +let SubtargetPredicate = isGFX12Plus in { +def S_PREFETCH_INST : SM_Prefetch_Pseudo <"s_prefetch_inst", SReg_64, 1>; +def S_PREFETCH_INST_PC_REL : SM_Prefetch_Pseudo <"s_prefetch_inst_pc_rel", SReg_64, 0>; +def S_PREFETCH_DATA : SM_Prefetch_Pseudo <"s_prefetch_data", SReg_64, 1>; +def S_PREFETCH_DATA_PC_REL : SM_Prefetch_Pseudo <"s_prefetch_data_pc_rel", SReg_64, 0>; +def S_BUFFER_PREFETCH_DATA : SM_Prefetch_Pseudo <"s_buffer_prefetch_data", SReg_128, 1> { + let is_buffer = 1; +} +} // end let SubtargetPredicate = isGFX12Plus + //===----------------------------------------------------------------------===// // Targets //===----------------------------------------------------------------------===// @@ -1203,3 +1230,33 @@ multiclass SM_Real_Probe_gfx11 op> { defm S_ATC_PROBE : SM_Real_Probe_gfx11 <0x22>; defm S_ATC_PROBE_BUFFER : SM_Real_Probe_gfx11 <0x23>; + +//===----------------------------------------------------------------------===// +// GFX12. +//===----------------------------------------------------------------------===// + +class SMEM_Real_gfx12 op, SM_Pseudo ps, string opName = ps.Mnemonic> : + SMEM_Real_10Plus_common { + let AssemblerPredicate = isGFX12Plus; + let DecoderNamespace = "GFX12"; + let Inst{18-13} = op{5-0}; + let Inst{19} = !if(ps.has_dlc, cpol{CPolBit.DLC}, 0); + let Inst{24-20} = ?; // TODO-GFX12: Add new bits {24-20}: TH, Scope, NV + let Inst{25} = !if(ps.has_glc, cpol{CPolBit.GLC}, 0); + let Inst{55-32} = offset{23-0}; +} + +class SMEM_Real_Prefetch_gfx12 op, SM_Pseudo ps> : SMEM_Real_gfx12 { + bits<7> sdata; // Only 5 bits of sdata are supported. + + let sdst = ?; + let Inst{12-11} = 0; // Unused sdata bits. + let Inst{10-6} = !if(ps.has_sdst, sdata{4-0}, ?); +} + +def S_PREFETCH_INST_gfx12 : SMEM_Real_Prefetch_gfx12<0x24, S_PREFETCH_INST>; +def S_PREFETCH_INST_PC_REL_gfx12 : SMEM_Real_Prefetch_gfx12<0x25, S_PREFETCH_INST_PC_REL>; +def S_PREFETCH_DATA_gfx12 : SMEM_Real_Prefetch_gfx12<0x26, S_PREFETCH_DATA>; +def S_BUFFER_PREFETCH_DATA_gfx12 : SMEM_Real_Prefetch_gfx12<0x27, S_BUFFER_PREFETCH_DATA>; +def S_PREFETCH_DATA_PC_REL_gfx12 : SMEM_Real_Prefetch_gfx12<0x28, S_PREFETCH_DATA_PC_REL>; diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 9e10efd1b07e..9ff64968ef01 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -578,6 +578,20 @@ def S_MAX_U32 : SOP2_32 <"s_max_u32", } // End isCommutable = 1 } // End Defs = [SCC] +let SubtargetPredicate = isGFX12Plus in { + def S_ADD_U64 : SOP2_64<"s_add_u64">{ + let isCommutable = 1; + } + + def S_SUB_U64 : SOP2_64<"s_sub_u64">; + + def S_MUL_U64 : SOP2_64 <"s_mul_u64", + [(set i64:$sdst, (UniformBinFrag i64:$src0, i64:$src1))]> { + let isCommutable = 1; + } + +} // End SubtargetPredicate = isGFX12Plus + def SelectPat : PatFrag < (ops node:$src1, node:$src2), (select SCC, $src1, $src2), @@ -852,9 +866,9 @@ class SOPK_Pseudo : +class SOPK_Real : InstSI { + real_name # ps.AsmOperands> { let SALU = 1; let SOPK = 1; let isPseudo = 0; @@ -878,8 +892,8 @@ class SOPK_Real : bits<32> imm; } -class SOPK_Real32 op, SOPK_Pseudo ps> : - SOPK_Real , +class SOPK_Real32 op, SOPK_Pseudo ps, string real_name = ps.Mnemonic> : + SOPK_Real , Enc32 { let Inst{15-0} = simm16; let Inst{22-16} = !if(ps.has_sdst, sdst, ?); @@ -1086,10 +1100,14 @@ let SubtargetPredicate = isGFX10Plus in { "$simm16"> { let has_sdst = 0; } +} // End SubtargetPredicate = isGFX10Plus +let SubtargetPredicate = isGFX10GFX11 in { def S_SUBVECTOR_LOOP_BEGIN : SOPK_32_BR<"s_subvector_loop_begin">; def S_SUBVECTOR_LOOP_END : SOPK_32_BR<"s_subvector_loop_end">; +} // End SubtargetPredicate = isGFX10GFX11 +let SubtargetPredicate = isGFX10Plus in { def S_WAITCNT_VSCNT : SOPK_WAITCNT<"s_waitcnt_vscnt">; def S_WAITCNT_VMCNT : SOPK_WAITCNT<"s_waitcnt_vmcnt">; def S_WAITCNT_EXPCNT : SOPK_WAITCNT<"s_waitcnt_expcnt">; @@ -1730,6 +1748,11 @@ def : ScalarNot2Pat; // Target-specific instruction encodings. //===----------------------------------------------------------------------===// +class Select_gfx12 : SIMCInstr { + Predicate AssemblerPredicate = isGFX12Only; + string DecoderNamespace = "GFX12"; +} + class Select_gfx11 : SIMCInstr { Predicate AssemblerPredicate = isGFX11Only; string DecoderNamespace = "GFX11"; @@ -1751,105 +1774,130 @@ class Select_gfx6_gfx7 : SIMCInstr { } //===----------------------------------------------------------------------===// -// GFX11. +// SOP1 - GFX11, GFX12 //===----------------------------------------------------------------------===// +multiclass SOP1_Real_gfx12 op> { + def _gfx12 : SOP1_Real(NAME)>, + Select_gfx12(NAME).Mnemonic>; +} + +multiclass SOP1_M0_Real_gfx12 op> { + def _gfx12 : SOP1_Real(NAME)>, + Select_gfx12(NAME).Mnemonic> { + let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0 + } +} + multiclass SOP1_Real_gfx11 op> { def _gfx11 : SOP1_Real(NAME)>, Select_gfx11(NAME).Mnemonic>; } +multiclass SOP1_Real_Renamed_gfx12 op, SOP1_Pseudo backing_pseudo, string real_name> { + def _gfx12 : SOP1_Real, + Select_gfx12, + MnemonicAlias, Requires<[isGFX12Plus]>; +} + multiclass SOP1_Real_Renamed_gfx11 op, SOP1_Pseudo backing_pseudo, string real_name> { def _gfx11 : SOP1_Real, Select_gfx11, - MnemonicAlias, Requires<[isGFX11Plus]>; -} - -defm S_MOV_B32 : SOP1_Real_gfx11<0x000>; -defm S_MOV_B64 : SOP1_Real_gfx11<0x001>; -defm S_CMOV_B32 : SOP1_Real_gfx11<0x002>; -defm S_CMOV_B64 : SOP1_Real_gfx11<0x003>; -defm S_BREV_B32 : SOP1_Real_gfx11<0x004>; -defm S_BREV_B64 : SOP1_Real_gfx11<0x005>; -defm S_CTZ_I32_B32 : SOP1_Real_Renamed_gfx11<0x008, S_FF1_I32_B32, "s_ctz_i32_b32">; -defm S_CTZ_I32_B64 : SOP1_Real_Renamed_gfx11<0x009, S_FF1_I32_B64, "s_ctz_i32_b64">; -defm S_CLZ_I32_U32 : SOP1_Real_Renamed_gfx11<0x00a, S_FLBIT_I32_B32, "s_clz_i32_u32">; -defm S_CLZ_I32_U64 : SOP1_Real_Renamed_gfx11<0x00b, S_FLBIT_I32_B64, "s_clz_i32_u64">; -defm S_CLS_I32 : SOP1_Real_Renamed_gfx11<0x00c, S_FLBIT_I32, "s_cls_i32">; -defm S_CLS_I32_I64 : SOP1_Real_Renamed_gfx11<0x00d, S_FLBIT_I32_I64, "s_cls_i32_i64">; -defm S_SEXT_I32_I8 : SOP1_Real_gfx11<0x00e>; -defm S_SEXT_I32_I16 : SOP1_Real_gfx11<0x00f>; -defm S_BITSET0_B32 : SOP1_Real_gfx11<0x010>; -defm S_BITSET0_B64 : SOP1_Real_gfx11<0x011>; -defm S_BITSET1_B32 : SOP1_Real_gfx11<0x012>; -defm S_BITSET1_B64 : SOP1_Real_gfx11<0x013>; -defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx11<0x014>; -defm S_ABS_I32 : SOP1_Real_gfx11<0x015>; -defm S_BCNT0_I32_B32 : SOP1_Real_gfx11<0x016>; -defm S_BCNT0_I32_B64 : SOP1_Real_gfx11<0x017>; -defm S_BCNT1_I32_B32 : SOP1_Real_gfx11<0x018>; -defm S_BCNT1_I32_B64 : SOP1_Real_gfx11<0x019>; -defm S_QUADMASK_B32 : SOP1_Real_gfx11<0x01a>; -defm S_QUADMASK_B64 : SOP1_Real_gfx11<0x01b>; -defm S_WQM_B32 : SOP1_Real_gfx11<0x01c>; -defm S_WQM_B64 : SOP1_Real_gfx11<0x01d>; -defm S_NOT_B32 : SOP1_Real_gfx11<0x01e>; -defm S_NOT_B64 : SOP1_Real_gfx11<0x01f>; -defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx11<0x020>; -defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx11<0x021>; -defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx11<0x022>; -defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx11<0x023>; -defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx11<0x024>; -defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx11<0x025>; -defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx11<0x026>; -defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx11<0x027>; -defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx11<0x028>; -defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx11<0x029>; -defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx11<0x02a>; -/*defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx11<0x02b>; //same as older arch, handled there*/ -defm S_AND_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11<0x02c, S_ANDN1_SAVEEXEC_B32, "s_and_not0_saveexec_b32">; -defm S_AND_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11<0x02d, S_ANDN1_SAVEEXEC_B64, "s_and_not0_saveexec_b64">; -defm S_OR_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11<0x02e, S_ORN1_SAVEEXEC_B32, "s_or_not0_saveexec_b32">; -defm S_OR_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11<0x02f, S_ORN1_SAVEEXEC_B64, "s_or_not0_saveexec_b64">; -defm S_AND_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11<0x030, S_ANDN2_SAVEEXEC_B32, "s_and_not1_saveexec_b32">; -defm S_AND_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11<0x031, S_ANDN2_SAVEEXEC_B64, "s_and_not1_saveexec_b64">; -defm S_OR_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11<0x032, S_ORN2_SAVEEXEC_B32, "s_or_not1_saveexec_b32">; -defm S_OR_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11<0x033, S_ORN2_SAVEEXEC_B64, "s_or_not1_saveexec_b64">; -defm S_AND_NOT0_WREXEC_B32 : SOP1_Real_Renamed_gfx11<0x034, S_ANDN1_WREXEC_B32, "s_and_not0_wrexec_b32">; -defm S_AND_NOT0_WREXEC_B64 : SOP1_Real_Renamed_gfx11<0x035, S_ANDN1_WREXEC_B64, "s_and_not0_wrexec_b64">; -defm S_AND_NOT1_WREXEC_B32 : SOP1_Real_Renamed_gfx11<0x036, S_ANDN2_WREXEC_B32, "s_and_not1_wrexec_b32">; -defm S_AND_NOT1_WREXEC_B64 : SOP1_Real_Renamed_gfx11<0x037, S_ANDN2_WREXEC_B64, "s_and_not1_wrexec_b64">; -defm S_MOVRELS_B32 : SOP1_Real_gfx11<0x040>; -defm S_MOVRELS_B64 : SOP1_Real_gfx11<0x041>; -defm S_MOVRELD_B32 : SOP1_Real_gfx11<0x042>; -defm S_MOVRELD_B64 : SOP1_Real_gfx11<0x043>; -defm S_MOVRELSD_2_B32 : SOP1_Real_gfx11<0x044>; -defm S_GETPC_B64 : SOP1_Real_gfx11<0x047>; -defm S_SETPC_B64 : SOP1_Real_gfx11<0x048>; -defm S_SWAPPC_B64 : SOP1_Real_gfx11<0x049>; -defm S_RFE_B64 : SOP1_Real_gfx11<0x04a>; -defm S_SENDMSG_RTN_B32 : SOP1_Real_gfx11<0x04c>; -defm S_SENDMSG_RTN_B64 : SOP1_Real_gfx11<0x04d>; + MnemonicAlias, Requires<[isGFX11Only]>; +} + +multiclass SOP1_Real_gfx11_gfx12 op> : + SOP1_Real_gfx11, SOP1_Real_gfx12; + +multiclass SOP1_Real_Renamed_gfx11_gfx12 op, SOP1_Pseudo backing_pseudo, string real_name> : + SOP1_Real_Renamed_gfx11, + SOP1_Real_Renamed_gfx12; + +defm S_MOV_B32 : SOP1_Real_gfx11_gfx12<0x000>; +defm S_MOV_B64 : SOP1_Real_gfx11_gfx12<0x001>; +defm S_CMOV_B32 : SOP1_Real_gfx11_gfx12<0x002>; +defm S_CMOV_B64 : SOP1_Real_gfx11_gfx12<0x003>; +defm S_BREV_B32 : SOP1_Real_gfx11_gfx12<0x004>; +defm S_BREV_B64 : SOP1_Real_gfx11_gfx12<0x005>; +defm S_CTZ_I32_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x008, S_FF1_I32_B32, "s_ctz_i32_b32">; +defm S_CTZ_I32_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x009, S_FF1_I32_B64, "s_ctz_i32_b64">; +defm S_CLZ_I32_U32 : SOP1_Real_Renamed_gfx11_gfx12<0x00a, S_FLBIT_I32_B32, "s_clz_i32_u32">; +defm S_CLZ_I32_U64 : SOP1_Real_Renamed_gfx11_gfx12<0x00b, S_FLBIT_I32_B64, "s_clz_i32_u64">; +defm S_CLS_I32 : SOP1_Real_Renamed_gfx11_gfx12<0x00c, S_FLBIT_I32, "s_cls_i32">; +defm S_CLS_I32_I64 : SOP1_Real_Renamed_gfx11_gfx12<0x00d, S_FLBIT_I32_I64, "s_cls_i32_i64">; +defm S_SEXT_I32_I8 : SOP1_Real_gfx11_gfx12<0x00e>; +defm S_SEXT_I32_I16 : SOP1_Real_gfx11_gfx12<0x00f>; +defm S_BITSET0_B32 : SOP1_Real_gfx11_gfx12<0x010>; +defm S_BITSET0_B64 : SOP1_Real_gfx11_gfx12<0x011>; +defm S_BITSET1_B32 : SOP1_Real_gfx11_gfx12<0x012>; +defm S_BITSET1_B64 : SOP1_Real_gfx11_gfx12<0x013>; +defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx11_gfx12<0x014>; +defm S_ABS_I32 : SOP1_Real_gfx11_gfx12<0x015>; +defm S_BCNT0_I32_B32 : SOP1_Real_gfx11_gfx12<0x016>; +defm S_BCNT0_I32_B64 : SOP1_Real_gfx11_gfx12<0x017>; +defm S_BCNT1_I32_B32 : SOP1_Real_gfx11_gfx12<0x018>; +defm S_BCNT1_I32_B64 : SOP1_Real_gfx11_gfx12<0x019>; +defm S_QUADMASK_B32 : SOP1_Real_gfx11_gfx12<0x01a>; +defm S_QUADMASK_B64 : SOP1_Real_gfx11_gfx12<0x01b>; +defm S_WQM_B32 : SOP1_Real_gfx11_gfx12<0x01c>; +defm S_WQM_B64 : SOP1_Real_gfx11_gfx12<0x01d>; +defm S_NOT_B32 : SOP1_Real_gfx11_gfx12<0x01e>; +defm S_NOT_B64 : SOP1_Real_gfx11_gfx12<0x01f>; +defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x020>; +defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x021>; +defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x022>; +defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x023>; +defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x024>; +defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x025>; +defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x026>; +defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x027>; +defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x028>; +defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x029>; +defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02a>; +/*defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02b>; //same as older arch, handled there*/ +defm S_AND_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02c, S_ANDN1_SAVEEXEC_B32, "s_and_not0_saveexec_b32">; +defm S_AND_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02d, S_ANDN1_SAVEEXEC_B64, "s_and_not0_saveexec_b64">; +defm S_OR_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02e, S_ORN1_SAVEEXEC_B32, "s_or_not0_saveexec_b32">; +defm S_OR_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02f, S_ORN1_SAVEEXEC_B64, "s_or_not0_saveexec_b64">; +defm S_AND_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x030, S_ANDN2_SAVEEXEC_B32, "s_and_not1_saveexec_b32">; +defm S_AND_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x031, S_ANDN2_SAVEEXEC_B64, "s_and_not1_saveexec_b64">; +defm S_OR_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x032, S_ORN2_SAVEEXEC_B32, "s_or_not1_saveexec_b32">; +defm S_OR_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x033, S_ORN2_SAVEEXEC_B64, "s_or_not1_saveexec_b64">; +defm S_AND_NOT0_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x034, S_ANDN1_WREXEC_B32, "s_and_not0_wrexec_b32">; +defm S_AND_NOT0_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x035, S_ANDN1_WREXEC_B64, "s_and_not0_wrexec_b64">; +defm S_AND_NOT1_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x036, S_ANDN2_WREXEC_B32, "s_and_not1_wrexec_b32">; +defm S_AND_NOT1_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x037, S_ANDN2_WREXEC_B64, "s_and_not1_wrexec_b64">; +defm S_MOVRELS_B32 : SOP1_Real_gfx11_gfx12<0x040>; +defm S_MOVRELS_B64 : SOP1_Real_gfx11_gfx12<0x041>; +defm S_MOVRELD_B32 : SOP1_Real_gfx11_gfx12<0x042>; +defm S_MOVRELD_B64 : SOP1_Real_gfx11_gfx12<0x043>; +defm S_MOVRELSD_2_B32 : SOP1_Real_gfx11_gfx12<0x044>; +defm S_GETPC_B64 : SOP1_Real_gfx11_gfx12<0x047>; +defm S_SETPC_B64 : SOP1_Real_gfx11_gfx12<0x048>; +defm S_SWAPPC_B64 : SOP1_Real_gfx11_gfx12<0x049>; +defm S_RFE_B64 : SOP1_Real_gfx11_gfx12<0x04a>; +defm S_SENDMSG_RTN_B32 : SOP1_Real_gfx11_gfx12<0x04c>; +defm S_SENDMSG_RTN_B64 : SOP1_Real_gfx11_gfx12<0x04d>; //===----------------------------------------------------------------------===// -// SOP1 - GFX1150 +// SOP1 - GFX1150, GFX12 //===----------------------------------------------------------------------===// -defm S_CEIL_F32 : SOP1_Real_gfx11<0x060>; -defm S_FLOOR_F32 : SOP1_Real_gfx11<0x061>; -defm S_TRUNC_F32 : SOP1_Real_gfx11<0x062>; -defm S_RNDNE_F32 : SOP1_Real_gfx11<0x063>; -defm S_CVT_F32_I32 : SOP1_Real_gfx11<0x064>; -defm S_CVT_F32_U32 : SOP1_Real_gfx11<0x065>; -defm S_CVT_I32_F32 : SOP1_Real_gfx11<0x066>; -defm S_CVT_U32_F32 : SOP1_Real_gfx11<0x067>; -defm S_CVT_F16_F32 : SOP1_Real_gfx11<0x068>; -defm S_CVT_F32_F16 : SOP1_Real_gfx11<0x069>; -defm S_CVT_HI_F32_F16 : SOP1_Real_gfx11<0x06a>; -defm S_CEIL_F16 : SOP1_Real_gfx11<0x06b>; -defm S_FLOOR_F16 : SOP1_Real_gfx11<0x06c>; -defm S_TRUNC_F16 : SOP1_Real_gfx11<0x06d>; -defm S_RNDNE_F16 : SOP1_Real_gfx11<0x06e>; +defm S_CEIL_F32 : SOP1_Real_gfx11_gfx12<0x060>; +defm S_FLOOR_F32 : SOP1_Real_gfx11_gfx12<0x061>; +defm S_TRUNC_F32 : SOP1_Real_gfx11_gfx12<0x062>; +defm S_RNDNE_F32 : SOP1_Real_gfx11_gfx12<0x063>; +defm S_CVT_F32_I32 : SOP1_Real_gfx11_gfx12<0x064>; +defm S_CVT_F32_U32 : SOP1_Real_gfx11_gfx12<0x065>; +defm S_CVT_I32_F32 : SOP1_Real_gfx11_gfx12<0x066>; +defm S_CVT_U32_F32 : SOP1_Real_gfx11_gfx12<0x067>; +defm S_CVT_F16_F32 : SOP1_Real_gfx11_gfx12<0x068>; +defm S_CVT_F32_F16 : SOP1_Real_gfx11_gfx12<0x069>; +defm S_CVT_HI_F32_F16 : SOP1_Real_gfx11_gfx12<0x06a>; +defm S_CEIL_F16 : SOP1_Real_gfx11_gfx12<0x06b>; +defm S_FLOOR_F16 : SOP1_Real_gfx11_gfx12<0x06c>; +defm S_TRUNC_F16 : SOP1_Real_gfx11_gfx12<0x06d>; +defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12<0x06e>; //===----------------------------------------------------------------------===// // SOP1 - GFX10. @@ -1861,8 +1909,8 @@ multiclass SOP1_Real_gfx10 op> { Select_gfx10; } -multiclass SOP1_Real_gfx10_gfx11 op> : - SOP1_Real_gfx10, SOP1_Real_gfx11; +multiclass SOP1_Real_gfx10_gfx11_gfx12 op> : + SOP1_Real_gfx10, SOP1_Real_gfx11_gfx12; defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x037>; defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x038>; @@ -1897,8 +1945,8 @@ multiclass SOP1_Real_gfx6_gfx7 op> { multiclass SOP1_Real_gfx6_gfx7_gfx10 op> : SOP1_Real_gfx6_gfx7, SOP1_Real_gfx10; -multiclass SOP1_Real_gfx6_gfx7_gfx10_gfx11 op> : - SOP1_Real_gfx6_gfx7, SOP1_Real_gfx10_gfx11; +multiclass SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12 op> : + SOP1_Real_gfx6_gfx7, SOP1_Real_gfx10_gfx11_gfx12; defm S_CBRANCH_JOIN : SOP1_Real_gfx6_gfx7<0x032>; @@ -1941,7 +1989,7 @@ defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x027>; defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x028>; defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x029>; defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02a>; -defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx11<0x02b>; +defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02b>; defm S_QUADMASK_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02c>; defm S_QUADMASK_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02d>; defm S_MOVRELS_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02e>; @@ -1951,7 +1999,34 @@ defm S_MOVRELD_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x031>; defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>; //===----------------------------------------------------------------------===// -// SOP2 - GFX11. +// SOP2 - GFX12 +//===----------------------------------------------------------------------===// + +multiclass SOP2_Real_gfx12 op> { + def _gfx12 : SOP2_Real32(NAME)>, + Select_gfx12(NAME).Mnemonic>; +} + +multiclass SOP2_Real_Renamed_gfx12 op, SOP2_Pseudo backing_pseudo, string real_name> { + def _gfx12 : SOP2_Real32, + Select_gfx12, + MnemonicAlias, Requires<[isGFX12Plus]>; +} + +defm S_MIN_NUM_F32 : SOP2_Real_Renamed_gfx12<0x042, S_MIN_F32, "s_min_num_f32">; +defm S_MAX_NUM_F32 : SOP2_Real_Renamed_gfx12<0x043, S_MAX_F32, "s_max_num_f32">; +defm S_MIN_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04b, S_MIN_F16, "s_min_num_f16">; +defm S_MAX_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04c, S_MAX_F16, "s_max_num_f16">; + +defm S_ADD_CO_U32 : SOP2_Real_Renamed_gfx12<0x000, S_ADD_U32, "s_add_co_u32">; +defm S_SUB_CO_U32 : SOP2_Real_Renamed_gfx12<0x001, S_SUB_U32, "s_sub_co_u32">; +defm S_ADD_CO_I32 : SOP2_Real_Renamed_gfx12<0x002, S_ADD_I32, "s_add_co_i32">; +defm S_SUB_CO_I32 : SOP2_Real_Renamed_gfx12<0x003, S_SUB_I32, "s_sub_co_i32">; +defm S_ADD_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x004, S_ADDC_U32, "s_add_co_ci_u32">; +defm S_SUB_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x005, S_SUBB_U32, "s_sub_co_ci_u32">; + +//===----------------------------------------------------------------------===// +// SOP2 - GFX11, GFX12. //===----------------------------------------------------------------------===// multiclass SOP2_Real_gfx11 op> { @@ -1962,77 +2037,100 @@ multiclass SOP2_Real_gfx11 op> { multiclass SOP2_Real_Renamed_gfx11 op, SOP2_Pseudo backing_pseudo, string real_name> { def _gfx11 : SOP2_Real32, Select_gfx11, - MnemonicAlias, Requires<[isGFX11Plus]>; -} - -defm S_ABSDIFF_I32 : SOP2_Real_gfx11<0x006>; -defm S_LSHL_B32 : SOP2_Real_gfx11<0x008>; -defm S_LSHL_B64 : SOP2_Real_gfx11<0x009>; -defm S_LSHR_B32 : SOP2_Real_gfx11<0x00a>; -defm S_LSHR_B64 : SOP2_Real_gfx11<0x00b>; -defm S_ASHR_I32 : SOP2_Real_gfx11<0x00c>; -defm S_ASHR_I64 : SOP2_Real_gfx11<0x00d>; -defm S_LSHL1_ADD_U32 : SOP2_Real_gfx11<0x00e>; -defm S_LSHL2_ADD_U32 : SOP2_Real_gfx11<0x00f>; -defm S_LSHL3_ADD_U32 : SOP2_Real_gfx11<0x010>; -defm S_LSHL4_ADD_U32 : SOP2_Real_gfx11<0x011>; -defm S_MIN_I32 : SOP2_Real_gfx11<0x012>; -defm S_MIN_U32 : SOP2_Real_gfx11<0x013>; -defm S_MAX_I32 : SOP2_Real_gfx11<0x014>; -defm S_MAX_U32 : SOP2_Real_gfx11<0x015>; -defm S_AND_B32 : SOP2_Real_gfx11<0x016>; -defm S_AND_B64 : SOP2_Real_gfx11<0x017>; -defm S_OR_B32 : SOP2_Real_gfx11<0x018>; -defm S_OR_B64 : SOP2_Real_gfx11<0x019>; -defm S_XOR_B32 : SOP2_Real_gfx11<0x01a>; -defm S_XOR_B64 : SOP2_Real_gfx11<0x01b>; -defm S_NAND_B32 : SOP2_Real_gfx11<0x01c>; -defm S_NAND_B64 : SOP2_Real_gfx11<0x01d>; -defm S_NOR_B32 : SOP2_Real_gfx11<0x01e>; -defm S_NOR_B64 : SOP2_Real_gfx11<0x01f>; -defm S_XNOR_B32 : SOP2_Real_gfx11<0x020>; -defm S_XNOR_B64 : SOP2_Real_gfx11<0x021>; -defm S_AND_NOT1_B32 : SOP2_Real_Renamed_gfx11<0x022, S_ANDN2_B32, "s_and_not1_b32">; -defm S_AND_NOT1_B64 : SOP2_Real_Renamed_gfx11<0x023, S_ANDN2_B64, "s_and_not1_b64">; -defm S_OR_NOT1_B32 : SOP2_Real_Renamed_gfx11<0x024, S_ORN2_B32, "s_or_not1_b32">; -defm S_OR_NOT1_B64 : SOP2_Real_Renamed_gfx11<0x025, S_ORN2_B64, "s_or_not1_b64">; -defm S_BFE_U32 : SOP2_Real_gfx11<0x026>; -defm S_BFE_I32 : SOP2_Real_gfx11<0x027>; -defm S_BFE_U64 : SOP2_Real_gfx11<0x028>; -defm S_BFE_I64 : SOP2_Real_gfx11<0x029>; -defm S_BFM_B32 : SOP2_Real_gfx11<0x02a>; -defm S_BFM_B64 : SOP2_Real_gfx11<0x02b>; -defm S_MUL_I32 : SOP2_Real_gfx11<0x02c>; -defm S_MUL_HI_U32 : SOP2_Real_gfx11<0x02d>; -defm S_MUL_HI_I32 : SOP2_Real_gfx11<0x02e>; -defm S_CSELECT_B32 : SOP2_Real_gfx11<0x030>; -defm S_CSELECT_B64 : SOP2_Real_gfx11<0x031>; -defm S_PACK_HL_B32_B16 : SOP2_Real_gfx11<0x035>; + MnemonicAlias, Requires<[isGFX11Only]>; +} + +multiclass SOP2_Real_gfx11_gfx12 op> : + SOP2_Real_gfx11, SOP2_Real_gfx12; + +multiclass SOP2_Real_Renamed_gfx11_gfx12 op, SOP2_Pseudo backing_pseudo, string real_name> : + SOP2_Real_Renamed_gfx11, + SOP2_Real_Renamed_gfx12; + +defm S_ABSDIFF_I32 : SOP2_Real_gfx11_gfx12<0x006>; +defm S_LSHL_B32 : SOP2_Real_gfx11_gfx12<0x008>; +defm S_LSHL_B64 : SOP2_Real_gfx11_gfx12<0x009>; +defm S_LSHR_B32 : SOP2_Real_gfx11_gfx12<0x00a>; +defm S_LSHR_B64 : SOP2_Real_gfx11_gfx12<0x00b>; +defm S_ASHR_I32 : SOP2_Real_gfx11_gfx12<0x00c>; +defm S_ASHR_I64 : SOP2_Real_gfx11_gfx12<0x00d>; +defm S_LSHL1_ADD_U32 : SOP2_Real_gfx11_gfx12<0x00e>; +defm S_LSHL2_ADD_U32 : SOP2_Real_gfx11_gfx12<0x00f>; +defm S_LSHL3_ADD_U32 : SOP2_Real_gfx11_gfx12<0x010>; +defm S_LSHL4_ADD_U32 : SOP2_Real_gfx11_gfx12<0x011>; +defm S_MIN_I32 : SOP2_Real_gfx11_gfx12<0x012>; +defm S_MIN_U32 : SOP2_Real_gfx11_gfx12<0x013>; +defm S_MAX_I32 : SOP2_Real_gfx11_gfx12<0x014>; +defm S_MAX_U32 : SOP2_Real_gfx11_gfx12<0x015>; +defm S_AND_B32 : SOP2_Real_gfx11_gfx12<0x016>; +defm S_AND_B64 : SOP2_Real_gfx11_gfx12<0x017>; +defm S_OR_B32 : SOP2_Real_gfx11_gfx12<0x018>; +defm S_OR_B64 : SOP2_Real_gfx11_gfx12<0x019>; +defm S_XOR_B32 : SOP2_Real_gfx11_gfx12<0x01a>; +defm S_XOR_B64 : SOP2_Real_gfx11_gfx12<0x01b>; +defm S_NAND_B32 : SOP2_Real_gfx11_gfx12<0x01c>; +defm S_NAND_B64 : SOP2_Real_gfx11_gfx12<0x01d>; +defm S_NOR_B32 : SOP2_Real_gfx11_gfx12<0x01e>; +defm S_NOR_B64 : SOP2_Real_gfx11_gfx12<0x01f>; +defm S_XNOR_B32 : SOP2_Real_gfx11_gfx12<0x020>; +defm S_XNOR_B64 : SOP2_Real_gfx11_gfx12<0x021>; +defm S_AND_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x022, S_ANDN2_B32, "s_and_not1_b32">; +defm S_AND_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x023, S_ANDN2_B64, "s_and_not1_b64">; +defm S_OR_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x024, S_ORN2_B32, "s_or_not1_b32">; +defm S_OR_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x025, S_ORN2_B64, "s_or_not1_b64">; +defm S_BFE_U32 : SOP2_Real_gfx11_gfx12<0x026>; +defm S_BFE_I32 : SOP2_Real_gfx11_gfx12<0x027>; +defm S_BFE_U64 : SOP2_Real_gfx11_gfx12<0x028>; +defm S_BFE_I64 : SOP2_Real_gfx11_gfx12<0x029>; +defm S_BFM_B32 : SOP2_Real_gfx11_gfx12<0x02a>; +defm S_BFM_B64 : SOP2_Real_gfx11_gfx12<0x02b>; +defm S_MUL_I32 : SOP2_Real_gfx11_gfx12<0x02c>; +defm S_MUL_HI_U32 : SOP2_Real_gfx11_gfx12<0x02d>; +defm S_MUL_HI_I32 : SOP2_Real_gfx11_gfx12<0x02e>; +defm S_CSELECT_B32 : SOP2_Real_gfx11_gfx12<0x030>; +defm S_CSELECT_B64 : SOP2_Real_gfx11_gfx12<0x031>; +defm S_PACK_HL_B32_B16 : SOP2_Real_gfx11_gfx12<0x035>; +defm S_ADD_NC_U64 : SOP2_Real_Renamed_gfx12<0x053, S_ADD_U64, "s_add_nc_u64">; +defm S_SUB_NC_U64 : SOP2_Real_Renamed_gfx12<0x054, S_SUB_U64, "s_sub_nc_u64">; +defm S_MUL_U64 : SOP2_Real_gfx12<0x055>; //===----------------------------------------------------------------------===// -// SOP2 - GFX1150 +// SOP2 - GFX1150, GFX12 //===----------------------------------------------------------------------===// +multiclass SOP2_Real_FMAK_gfx12 op> { + def _gfx12 : SOP2_Real64(NAME)>, + Select_gfx12(NAME).Mnemonic>; +} + multiclass SOP2_Real_FMAK_gfx11 op> { def _gfx11 : SOP2_Real64(NAME)>, Select_gfx11(NAME).Mnemonic>; } -defm S_ADD_F32 : SOP2_Real_gfx11<0x040>; -defm S_SUB_F32 : SOP2_Real_gfx11<0x041>; -defm S_MIN_F32 : SOP2_Real_gfx11<0x042>; -defm S_MAX_F32 : SOP2_Real_gfx11<0x043>; -defm S_MUL_F32 : SOP2_Real_gfx11<0x044>; -defm S_FMAAK_F32 : SOP2_Real_FMAK_gfx11<0x045>; -defm S_FMAMK_F32 : SOP2_Real_FMAK_gfx11<0x046>; -defm S_FMAC_F32 : SOP2_Real_gfx11<0x047>; -defm S_CVT_PK_RTZ_F16_F32 : SOP2_Real_gfx11<0x048>; -defm S_ADD_F16 : SOP2_Real_gfx11<0x049>; -defm S_SUB_F16 : SOP2_Real_gfx11<0x04a>; -defm S_MIN_F16 : SOP2_Real_gfx11<0x04b>; -defm S_MAX_F16 : SOP2_Real_gfx11<0x04c>; -defm S_MUL_F16 : SOP2_Real_gfx11<0x04d>; -defm S_FMAC_F16 : SOP2_Real_gfx11<0x04e>; +multiclass SOP2_Real_FMAK_gfx11_gfx12 op> : + SOP2_Real_FMAK_gfx11, SOP2_Real_FMAK_gfx12; + +defm S_ADD_F32 : SOP2_Real_gfx11_gfx12<0x040>; +defm S_SUB_F32 : SOP2_Real_gfx11_gfx12<0x041>; +defm S_MUL_F32 : SOP2_Real_gfx11_gfx12<0x044>; +defm S_FMAAK_F32 : SOP2_Real_FMAK_gfx11_gfx12<0x045>; +defm S_FMAMK_F32 : SOP2_Real_FMAK_gfx11_gfx12<0x046>; +defm S_FMAC_F32 : SOP2_Real_gfx11_gfx12<0x047>; +defm S_CVT_PK_RTZ_F16_F32 : SOP2_Real_gfx11_gfx12<0x048>; +defm S_ADD_F16 : SOP2_Real_gfx11_gfx12<0x049>; +defm S_SUB_F16 : SOP2_Real_gfx11_gfx12<0x04a>; +defm S_MUL_F16 : SOP2_Real_gfx11_gfx12<0x04d>; +defm S_FMAC_F16 : SOP2_Real_gfx11_gfx12<0x04e>; + +//===----------------------------------------------------------------------===// +// SOP2 - GFX1150 +//===----------------------------------------------------------------------===// + +defm S_MIN_F32 : SOP2_Real_gfx11<0x042>; +defm S_MAX_F32 : SOP2_Real_gfx11<0x043>; +defm S_MIN_F16 : SOP2_Real_gfx11<0x04b>; +defm S_MAX_F16 : SOP2_Real_gfx11<0x04c>; //===----------------------------------------------------------------------===// // SOP2 - GFX10. @@ -2044,16 +2142,16 @@ multiclass SOP2_Real_gfx10 op> { Select_gfx10; } -multiclass SOP2_Real_gfx10_gfx11 op> : - SOP2_Real_gfx10, SOP2_Real_gfx11; +multiclass SOP2_Real_gfx10_gfx11_gfx12 op> : + SOP2_Real_gfx10, SOP2_Real_gfx11_gfx12; defm S_LSHL1_ADD_U32 : SOP2_Real_gfx10<0x02e>; defm S_LSHL2_ADD_U32 : SOP2_Real_gfx10<0x02f>; defm S_LSHL3_ADD_U32 : SOP2_Real_gfx10<0x030>; defm S_LSHL4_ADD_U32 : SOP2_Real_gfx10<0x031>; -defm S_PACK_LL_B32_B16 : SOP2_Real_gfx10_gfx11<0x032>; -defm S_PACK_LH_B32_B16 : SOP2_Real_gfx10_gfx11<0x033>; -defm S_PACK_HH_B32_B16 : SOP2_Real_gfx10_gfx11<0x034>; +defm S_PACK_LL_B32_B16 : SOP2_Real_gfx10_gfx11_gfx12<0x032>; +defm S_PACK_LH_B32_B16 : SOP2_Real_gfx10_gfx11_gfx12<0x033>; +defm S_PACK_HH_B32_B16 : SOP2_Real_gfx10_gfx11_gfx12<0x034>; defm S_MUL_HI_U32 : SOP2_Real_gfx10<0x035>; defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>; @@ -2071,7 +2169,10 @@ multiclass SOP2_Real_gfx6_gfx7_gfx10 op> : SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10; multiclass SOP2_Real_gfx6_gfx7_gfx10_gfx11 op> : - SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10_gfx11; + SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10, SOP2_Real_gfx11; + +multiclass SOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12 op> : + SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10_gfx11_gfx12; defm S_CBRANCH_G_FORK : SOP2_Real_gfx6_gfx7<0x02b>; @@ -2119,29 +2220,52 @@ defm S_BFE_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x02a>; defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>; //===----------------------------------------------------------------------===// -// SOPK - GFX11. +// SOPK - GFX11, GFX12. //===----------------------------------------------------------------------===// +multiclass SOPK_Real32_gfx12 op> { + def _gfx12 : SOPK_Real32(NAME)>, + Select_gfx12(NAME).Mnemonic>; +} + +multiclass SOPK_Real32_Renamed_gfx12 op, SOPK_Pseudo backing_pseudo, string real_name> { + def _gfx12 : SOPK_Real32, + Select_gfx12, + MnemonicAlias, Requires<[isGFX12Plus]>; +} + multiclass SOPK_Real32_gfx11 op> { def _gfx11 : SOPK_Real32(NAME)>, Select_gfx11(NAME).Mnemonic>; } +multiclass SOPK_Real64_gfx12 op> { + def _gfx12 : SOPK_Real64(NAME)>, + Select_gfx12(NAME).Mnemonic>; +} + multiclass SOPK_Real64_gfx11 op> { def _gfx11 : SOPK_Real64(NAME)>, Select_gfx11(NAME).Mnemonic>; } -defm S_GETREG_B32 : SOPK_Real32_gfx11<0x011>; -defm S_SETREG_B32 : SOPK_Real32_gfx11<0x012>; -defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11<0x013>; -defm S_CALL_B64 : SOPK_Real32_gfx11<0x014>; +multiclass SOPK_Real32_gfx11_gfx12 op> : + SOPK_Real32_gfx11, SOPK_Real32_gfx12; + +multiclass SOPK_Real64_gfx11_gfx12 op> : + SOPK_Real64_gfx11, SOPK_Real64_gfx12; + +defm S_ADDK_CO_I32 : SOPK_Real32_Renamed_gfx12<0x00f, S_ADDK_I32, "s_addk_co_i32">; +defm S_GETREG_B32 : SOPK_Real32_gfx11_gfx12<0x011>; +defm S_SETREG_B32 : SOPK_Real32_gfx11_gfx12<0x012>; +defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11_gfx12<0x013>; +defm S_CALL_B64 : SOPK_Real32_gfx11_gfx12<0x014>; defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx11<0x016>; defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx11<0x017>; -defm S_WAITCNT_VSCNT : SOPK_Real32_gfx11<0x018>; -defm S_WAITCNT_VMCNT : SOPK_Real32_gfx11<0x019>; -defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx11<0x01a>; -defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>; +defm S_WAITCNT_VSCNT : SOPK_Real32_gfx11_gfx12<0x018>; +defm S_WAITCNT_VMCNT : SOPK_Real32_gfx11_gfx12<0x019>; +defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx11_gfx12<0x01a>; +defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11_gfx12<0x01b>; //===----------------------------------------------------------------------===// // SOPK - GFX10. @@ -2162,7 +2286,10 @@ multiclass SOPK_Real64_gfx10 op> { multiclass SOPK_Real32_gfx10_gfx11 op> : SOPK_Real32_gfx10, SOPK_Real32_gfx11; -defm S_VERSION : SOPK_Real32_gfx10_gfx11<0x001>; +multiclass SOPK_Real32_gfx10_gfx11_gfx12 op> : + SOPK_Real32_gfx10, SOPK_Real32_gfx11_gfx12; + +defm S_VERSION : SOPK_Real32_gfx10_gfx11_gfx12<0x001>; defm S_CALL_B64 : SOPK_Real32_gfx10<0x016>; defm S_WAITCNT_VSCNT : SOPK_Real32_gfx10<0x017>; defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>; @@ -2196,10 +2323,13 @@ multiclass SOPK_Real64_gfx6_gfx7_gfx10 op> : multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11 op> : SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10_gfx11; +multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12 op> : + SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10_gfx11_gfx12; + defm S_CBRANCH_I_FORK : SOPK_Real32_gfx6_gfx7<0x011>; -defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x000>; -defm S_CMOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x002>; +defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x000>; +defm S_CMOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x002>; defm S_CMPK_EQ_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x003>; defm S_CMPK_LG_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x004>; defm S_CMPK_GT_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x005>; @@ -2213,21 +2343,46 @@ defm S_CMPK_GE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00c>; defm S_CMPK_LT_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00d>; defm S_CMPK_LE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00e>; defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00f>; -defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x010>; +defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x010>; defm S_GETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x012>; defm S_SETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x013>; defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>; //===----------------------------------------------------------------------===// -// SOPP - GFX11 +// SOPP - GFX12 only. //===----------------------------------------------------------------------===// +multiclass SOPP_Real_32_gfx12 op> { + def _gfx12 : SOPP_Real_32(NAME), !cast(NAME).Mnemonic>, + Select_gfx12(NAME).Mnemonic>, + SOPPRelaxTable<0, !cast(NAME).KeyName, "_gfx12">; +} + +multiclass SOPP_Real_32_Renamed_gfx12 op, SOPP_Pseudo backing_pseudo, string real_name> { + def _gfx12 : SOPP_Real_32, + Select_gfx12, + MnemonicAlias, Requires<[isGFX12Plus]>; +} + +defm S_WAIT_ALU : SOPP_Real_32_Renamed_gfx12<0x008, S_WAITCNT_DEPCTR, "s_wait_alu">; + +//===----------------------------------------------------------------------===// +// SOPP - GFX11, GFX12. +//===----------------------------------------------------------------------===// + + multiclass SOPP_Real_32_gfx11 op> { def _gfx11 : SOPP_Real_32(NAME), !cast(NAME).Mnemonic>, Select_gfx11(NAME).Mnemonic>, SOPPRelaxTable<0, !cast(NAME).KeyName, "_gfx11">; } +multiclass SOPP_Real_64_gfx12 op> { + def _gfx12 : SOPP_Real_64(NAME), !cast(NAME).Mnemonic>, + Select_gfx12(NAME).Mnemonic>, + SOPPRelaxTable<1, !cast(NAME).KeyName, "_gfx12">; +} + multiclass SOPP_Real_64_gfx11 op> { def _gfx11 : SOPP_Real_64(NAME), !cast(NAME).Mnemonic>, Select_gfx11(NAME).Mnemonic>, @@ -2237,7 +2392,22 @@ multiclass SOPP_Real_64_gfx11 op> { multiclass SOPP_Real_32_Renamed_gfx11 op, SOPP_Pseudo backing_pseudo, string real_name> { def _gfx11 : SOPP_Real_32, Select_gfx11, - MnemonicAlias, Requires<[isGFX11Plus]>; + MnemonicAlias, Requires<[isGFX11Only]>; +} + +multiclass SOPP_Real_32_gfx11_gfx12 op> : + SOPP_Real_32_gfx11, SOPP_Real_32_gfx12; + +multiclass SOPP_Real_64_gfx11_gfx12 op> : + SOPP_Real_64_gfx11, SOPP_Real_64_gfx12; + +multiclass SOPP_Real_32_Renamed_gfx11_gfx12 op, SOPP_Pseudo backing_pseudo, string real_name> : + SOPP_Real_32_Renamed_gfx11, + SOPP_Real_32_Renamed_gfx12; + +multiclass SOPP_Real_With_Relaxation_gfx12 op> { + defm "" : SOPP_Real_32_gfx12; + defm _pad_s_nop : SOPP_Real_64_gfx12; } multiclass SOPP_Real_With_Relaxation_gfx11 op> { @@ -2245,48 +2415,51 @@ multiclass SOPP_Real_With_Relaxation_gfx11 op> { defm _pad_s_nop : SOPP_Real_64_gfx11; } -defm S_SETKILL : SOPP_Real_32_gfx11<0x001>; -defm S_SETHALT : SOPP_Real_32_gfx11<0x002>; -defm S_SLEEP : SOPP_Real_32_gfx11<0x003>; -defm S_SET_INST_PREFETCH_DISTANCE : SOPP_Real_32_Renamed_gfx11<0x004, S_INST_PREFETCH, "s_set_inst_prefetch_distance">; -defm S_CLAUSE : SOPP_Real_32_gfx11<0x005>; -defm S_DELAY_ALU : SOPP_Real_32_gfx11<0x007>; +multiclass SOPP_Real_With_Relaxation_gfx11_gfx12op> : + SOPP_Real_With_Relaxation_gfx11, SOPP_Real_With_Relaxation_gfx12; + +defm S_SETKILL : SOPP_Real_32_gfx11_gfx12<0x001>; +defm S_SETHALT : SOPP_Real_32_gfx11_gfx12<0x002>; +defm S_SLEEP : SOPP_Real_32_gfx11_gfx12<0x003>; +defm S_SET_INST_PREFETCH_DISTANCE : SOPP_Real_32_Renamed_gfx11_gfx12<0x004, S_INST_PREFETCH, "s_set_inst_prefetch_distance">; +defm S_CLAUSE : SOPP_Real_32_gfx11_gfx12<0x005>; +defm S_DELAY_ALU : SOPP_Real_32_gfx11_gfx12<0x007>; defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11<0x008>; -defm S_WAITCNT : SOPP_Real_32_gfx11<0x009>; -defm S_WAIT_IDLE : SOPP_Real_32_gfx11<0x00a>; -defm S_WAIT_EVENT : SOPP_Real_32_gfx11<0x00b>; -defm S_TRAP : SOPP_Real_32_gfx11<0x010>; -defm S_ROUND_MODE : SOPP_Real_32_gfx11<0x011>; -defm S_DENORM_MODE : SOPP_Real_32_gfx11<0x012>; -defm S_BRANCH : SOPP_Real_With_Relaxation_gfx11<0x020>; -defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx11<0x021>; -defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx11<0x022>; -defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx11<0x023>; -defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx11<0x024>; -defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx11<0x025>; -defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx11<0x026>; +defm S_WAITCNT : SOPP_Real_32_gfx11_gfx12<0x009>; +defm S_WAIT_IDLE : SOPP_Real_32_gfx11_gfx12<0x00a>; +defm S_WAIT_EVENT : SOPP_Real_32_gfx11_gfx12<0x00b>; +defm S_TRAP : SOPP_Real_32_gfx11_gfx12<0x010>; +defm S_ROUND_MODE : SOPP_Real_32_gfx11_gfx12<0x011>; +defm S_DENORM_MODE : SOPP_Real_32_gfx11_gfx12<0x012>; +defm S_BRANCH : SOPP_Real_With_Relaxation_gfx11_gfx12<0x020>; +defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x021>; +defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x022>; +defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x023>; +defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x024>; +defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x025>; +defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x026>; defm S_CBRANCH_CDBGSYS : SOPP_Real_With_Relaxation_gfx11<0x027>; defm S_CBRANCH_CDBGUSER : SOPP_Real_With_Relaxation_gfx11<0x028>; defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx11<0x029>; defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx11<0x02a>; -defm S_ENDPGM : SOPP_Real_32_gfx11<0x030>; -defm S_ENDPGM_SAVED : SOPP_Real_32_gfx11<0x031>; -defm S_WAKEUP : SOPP_Real_32_gfx11<0x034>; -defm S_SETPRIO : SOPP_Real_32_gfx11<0x035>; -defm S_SENDMSG : SOPP_Real_32_gfx11<0x036>; -defm S_SENDMSGHALT : SOPP_Real_32_gfx11<0x037>; -defm S_INCPERFLEVEL : SOPP_Real_32_gfx11<0x038>; -defm S_DECPERFLEVEL : SOPP_Real_32_gfx11<0x039>; -defm S_TTRACEDATA : SOPP_Real_32_gfx11<0x03a>; -defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx11<0x03b>; -defm S_ICACHE_INV : SOPP_Real_32_gfx11<0x03c>; -defm S_BARRIER : SOPP_Real_32_gfx11<0x03d>; +defm S_ENDPGM : SOPP_Real_32_gfx11_gfx12<0x030>; +defm S_ENDPGM_SAVED : SOPP_Real_32_gfx11_gfx12<0x031>; +defm S_WAKEUP : SOPP_Real_32_gfx11_gfx12<0x034>; +defm S_SETPRIO : SOPP_Real_32_gfx11_gfx12<0x035>; +defm S_SENDMSG : SOPP_Real_32_gfx11_gfx12<0x036>; +defm S_SENDMSGHALT : SOPP_Real_32_gfx11_gfx12<0x037>; +defm S_INCPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x038>; +defm S_DECPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x039>; +defm S_TTRACEDATA : SOPP_Real_32_gfx11_gfx12<0x03a>; +defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx11_gfx12<0x03b>; +defm S_ICACHE_INV : SOPP_Real_32_gfx11_gfx12<0x03c>; +defm S_BARRIER : SOPP_Real_32_gfx11_gfx12<0x03d>; //===----------------------------------------------------------------------===// -// SOPP - GFX1150 +// SOPP - GFX1150, GFX12. //===----------------------------------------------------------------------===// -defm S_SINGLEUSE_VDST : SOPP_Real_32_gfx11<0x013>; +defm S_SINGLEUSE_VDST : SOPP_Real_32_gfx11_gfx12<0x013>; //===----------------------------------------------------------------------===// // SOPP - GFX6, GFX7, GFX8, GFX9, GFX10 @@ -2322,11 +2495,11 @@ multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9 op> : multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10 op> : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9, SOPP_Real_32_gfx10; -multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11 op> : - SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10, SOPP_Real_32_gfx11; +multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12 op> : + SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10, SOPP_Real_32_gfx11_gfx12; -multiclass SOPP_Real_32_gfx10_gfx11 op> : - SOPP_Real_32_gfx10, SOPP_Real_32_gfx11; +multiclass SOPP_Real_32_gfx10_gfx11_gfx12 op> : + SOPP_Real_32_gfx10, SOPP_Real_32_gfx11_gfx12; //64 bit encodings, for Relaxation multiclass SOPP_Real_64_gfx6_gfx7 op> { @@ -2359,8 +2532,8 @@ multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9 op> : multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10 op> : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9, SOPP_Real_64_gfx10; -multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11 op> : - SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10, SOPP_Real_64_gfx11; +multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12 op> : + SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10, SOPP_Real_64_gfx11_gfx12; //relaxation for insts with no operands not implemented multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10 op> { @@ -2368,7 +2541,7 @@ multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10 op> { defm _pad_s_nop : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10; } -defm S_NOP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11<0x000>; +defm S_NOP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x000>; defm S_ENDPGM : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x001>; defm S_WAKEUP : SOPP_Real_32_gfx8_gfx9_gfx10<0x003>; defm S_BARRIER : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00a>; @@ -2388,7 +2561,7 @@ defm S_ENDPGM_SAVED : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x01B>; defm S_SET_GPR_IDX_OFF : SOPP_Real_32_gfx8_gfx9<0x01c>; defm S_SET_GPR_IDX_MODE : SOPP_Real_32_gfx8_gfx9<0x01d>; defm S_ENDPGM_ORDERED_PS_DONE : SOPP_Real_32_gfx8_gfx9_gfx10<0x01e>; -defm S_CODE_END : SOPP_Real_32_gfx10_gfx11<0x01f>; +defm S_CODE_END : SOPP_Real_32_gfx10_gfx11_gfx12<0x01f>; defm S_INST_PREFETCH : SOPP_Real_32_gfx10<0x020>; defm S_CLAUSE : SOPP_Real_32_gfx10<0x021>; defm S_WAIT_IDLE : SOPP_Real_32_gfx10<0x022>; @@ -2412,66 +2585,74 @@ defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_ } //===----------------------------------------------------------------------===// -// SOPC - GFX11 +// SOPC - GFX11, GFX12. //===----------------------------------------------------------------------===// +multiclass SOPC_Real_gfx12 op> { + def _gfx12 : SOPC_Real(NAME)>, + Select_gfx12(NAME).Mnemonic>; +} + multiclass SOPC_Real_gfx11 op> { def _gfx11 : SOPC_Real(NAME)>, Select_gfx11(NAME).Mnemonic>; } -defm S_CMP_EQ_I32 : SOPC_Real_gfx11<0x00>; -defm S_CMP_LG_I32 : SOPC_Real_gfx11<0x01>; -defm S_CMP_GT_I32 : SOPC_Real_gfx11<0x02>; -defm S_CMP_GE_I32 : SOPC_Real_gfx11<0x03>; -defm S_CMP_LT_I32 : SOPC_Real_gfx11<0x04>; -defm S_CMP_LE_I32 : SOPC_Real_gfx11<0x05>; -defm S_CMP_EQ_U32 : SOPC_Real_gfx11<0x06>; -defm S_CMP_LG_U32 : SOPC_Real_gfx11<0x07>; -defm S_CMP_GT_U32 : SOPC_Real_gfx11<0x08>; -defm S_CMP_GE_U32 : SOPC_Real_gfx11<0x09>; -defm S_CMP_LT_U32 : SOPC_Real_gfx11<0x0a>; -defm S_CMP_LE_U32 : SOPC_Real_gfx11<0x0b>; -defm S_BITCMP0_B32 : SOPC_Real_gfx11<0x0c>; -defm S_BITCMP1_B32 : SOPC_Real_gfx11<0x0d>; -defm S_BITCMP0_B64 : SOPC_Real_gfx11<0x0e>; -defm S_BITCMP1_B64 : SOPC_Real_gfx11<0x0f>; -defm S_CMP_EQ_U64 : SOPC_Real_gfx11<0x10>; -defm S_CMP_LG_U64 : SOPC_Real_gfx11<0x11>; +multiclass SOPC_Real_gfx11_gfx12 op> : + SOPC_Real_gfx11, SOPC_Real_gfx12; + +defm S_CMP_EQ_I32 : SOPC_Real_gfx11_gfx12<0x00>; +defm S_CMP_LG_I32 : SOPC_Real_gfx11_gfx12<0x01>; +defm S_CMP_GT_I32 : SOPC_Real_gfx11_gfx12<0x02>; +defm S_CMP_GE_I32 : SOPC_Real_gfx11_gfx12<0x03>; +defm S_CMP_LT_I32 : SOPC_Real_gfx11_gfx12<0x04>; +defm S_CMP_LE_I32 : SOPC_Real_gfx11_gfx12<0x05>; +defm S_CMP_EQ_U32 : SOPC_Real_gfx11_gfx12<0x06>; +defm S_CMP_LG_U32 : SOPC_Real_gfx11_gfx12<0x07>; +defm S_CMP_GT_U32 : SOPC_Real_gfx11_gfx12<0x08>; +defm S_CMP_GE_U32 : SOPC_Real_gfx11_gfx12<0x09>; +defm S_CMP_LT_U32 : SOPC_Real_gfx11_gfx12<0x0a>; +defm S_CMP_LE_U32 : SOPC_Real_gfx11_gfx12<0x0b>; +defm S_BITCMP0_B32 : SOPC_Real_gfx11_gfx12<0x0c>; +defm S_BITCMP1_B32 : SOPC_Real_gfx11_gfx12<0x0d>; +defm S_BITCMP0_B64 : SOPC_Real_gfx11_gfx12<0x0e>; +defm S_BITCMP1_B64 : SOPC_Real_gfx11_gfx12<0x0f>; +defm S_CMP_EQ_U64 : SOPC_Real_gfx11_gfx12<0x10>; +defm S_CMP_LG_U64 : SOPC_Real_gfx11_gfx12<0x11>; //===----------------------------------------------------------------------===// -// SOPC - GFX1150 +// SOPC - GFX1150, GFX12 //===----------------------------------------------------------------------===// -defm S_CMP_LT_F32 : SOPC_Real_gfx11<0x41>; -defm S_CMP_EQ_F32 : SOPC_Real_gfx11<0x42>; -defm S_CMP_LE_F32 : SOPC_Real_gfx11<0x43>; -defm S_CMP_GT_F32 : SOPC_Real_gfx11<0x44>; -defm S_CMP_LG_F32 : SOPC_Real_gfx11<0x45>; -defm S_CMP_GE_F32 : SOPC_Real_gfx11<0x46>; -defm S_CMP_O_F32 : SOPC_Real_gfx11<0x47>; -defm S_CMP_U_F32 : SOPC_Real_gfx11<0x48>; -defm S_CMP_NGE_F32 : SOPC_Real_gfx11<0x49>; -defm S_CMP_NLG_F32 : SOPC_Real_gfx11<0x4a>; -defm S_CMP_NGT_F32 : SOPC_Real_gfx11<0x4b>; -defm S_CMP_NLE_F32 : SOPC_Real_gfx11<0x4c>; -defm S_CMP_NEQ_F32 : SOPC_Real_gfx11<0x4d>; -defm S_CMP_NLT_F32 : SOPC_Real_gfx11<0x4e>; - -defm S_CMP_LT_F16 : SOPC_Real_gfx11<0x51>; -defm S_CMP_EQ_F16 : SOPC_Real_gfx11<0x52>; -defm S_CMP_LE_F16 : SOPC_Real_gfx11<0x53>; -defm S_CMP_GT_F16 : SOPC_Real_gfx11<0x54>; -defm S_CMP_LG_F16 : SOPC_Real_gfx11<0x55>; -defm S_CMP_GE_F16 : SOPC_Real_gfx11<0x56>; -defm S_CMP_O_F16 : SOPC_Real_gfx11<0x57>; -defm S_CMP_U_F16 : SOPC_Real_gfx11<0x58>; -defm S_CMP_NGE_F16 : SOPC_Real_gfx11<0x59>; -defm S_CMP_NLG_F16 : SOPC_Real_gfx11<0x5a>; -defm S_CMP_NGT_F16 : SOPC_Real_gfx11<0x5b>; -defm S_CMP_NLE_F16 : SOPC_Real_gfx11<0x5c>; -defm S_CMP_NEQ_F16 : SOPC_Real_gfx11<0x5d>; -defm S_CMP_NLT_F16 : SOPC_Real_gfx11<0x5e>; +defm S_CMP_LT_F32 : SOPC_Real_gfx11_gfx12<0x41>; +defm S_CMP_EQ_F32 : SOPC_Real_gfx11_gfx12<0x42>; +defm S_CMP_LE_F32 : SOPC_Real_gfx11_gfx12<0x43>; +defm S_CMP_GT_F32 : SOPC_Real_gfx11_gfx12<0x44>; +defm S_CMP_LG_F32 : SOPC_Real_gfx11_gfx12<0x45>; +defm S_CMP_GE_F32 : SOPC_Real_gfx11_gfx12<0x46>; +defm S_CMP_O_F32 : SOPC_Real_gfx11_gfx12<0x47>; +defm S_CMP_U_F32 : SOPC_Real_gfx11_gfx12<0x48>; +defm S_CMP_NGE_F32 : SOPC_Real_gfx11_gfx12<0x49>; +defm S_CMP_NLG_F32 : SOPC_Real_gfx11_gfx12<0x4a>; +defm S_CMP_NGT_F32 : SOPC_Real_gfx11_gfx12<0x4b>; +defm S_CMP_NLE_F32 : SOPC_Real_gfx11_gfx12<0x4c>; +defm S_CMP_NEQ_F32 : SOPC_Real_gfx11_gfx12<0x4d>; +defm S_CMP_NLT_F32 : SOPC_Real_gfx11_gfx12<0x4e>; + +defm S_CMP_LT_F16 : SOPC_Real_gfx11_gfx12<0x51>; +defm S_CMP_EQ_F16 : SOPC_Real_gfx11_gfx12<0x52>; +defm S_CMP_LE_F16 : SOPC_Real_gfx11_gfx12<0x53>; +defm S_CMP_GT_F16 : SOPC_Real_gfx11_gfx12<0x54>; +defm S_CMP_LG_F16 : SOPC_Real_gfx11_gfx12<0x55>; +defm S_CMP_GE_F16 : SOPC_Real_gfx11_gfx12<0x56>; +defm S_CMP_O_F16 : SOPC_Real_gfx11_gfx12<0x57>; +defm S_CMP_U_F16 : SOPC_Real_gfx11_gfx12<0x58>; +defm S_CMP_NGE_F16 : SOPC_Real_gfx11_gfx12<0x59>; +defm S_CMP_NLG_F16 : SOPC_Real_gfx11_gfx12<0x5a>; +defm S_CMP_NGT_F16 : SOPC_Real_gfx11_gfx12<0x5b>; +defm S_CMP_NLE_F16 : SOPC_Real_gfx11_gfx12<0x5c>; +defm S_CMP_NEQ_F16 : SOPC_Real_gfx11_gfx12<0x5d>; +defm S_CMP_NLT_F16 : SOPC_Real_gfx11_gfx12<0x5e>; //===----------------------------------------------------------------------===// // SOPC - GFX6, GFX7, GFX8, GFX9, GFX10 diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp index ce40d82021cf..403efd6ffed3 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp @@ -87,41 +87,56 @@ namespace Hwreg { // Disable lint checking for this block since it makes the table unreadable. // NOLINTBEGIN +// clang-format off const CustomOperand Opr[] = { {{""}}, {{"HW_REG_MODE"}, ID_MODE}, {{"HW_REG_STATUS"}, ID_STATUS}, - {{"HW_REG_TRAPSTS"}, ID_TRAPSTS}, + {{"HW_REG_TRAPSTS"}, ID_TRAPSTS, isNotGFX12Plus}, {{"HW_REG_HW_ID"}, ID_HW_ID, isNotGFX10Plus}, {{"HW_REG_GPR_ALLOC"}, ID_GPR_ALLOC}, {{"HW_REG_LDS_ALLOC"}, ID_LDS_ALLOC}, {{"HW_REG_IB_STS"}, ID_IB_STS}, {{""}}, {{""}}, + {{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx12, isGFX12Plus}, + {{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO_gfx12, isGFX12Plus}, + {{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI_gfx12, isGFX12Plus}, {{""}}, {{""}}, - {{""}}, - {{""}}, - {{""}}, - {{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9Plus}, + {{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9_GFX10_GFX11}, {{"HW_REG_TBA_LO"}, ID_TBA_LO, isGFX9_GFX10}, {{"HW_REG_TBA_HI"}, ID_TBA_HI, isGFX9_GFX10}, {{"HW_REG_TMA_LO"}, ID_TMA_LO, isGFX9_GFX10}, {{"HW_REG_TMA_HI"}, ID_TMA_HI, isGFX9_GFX10}, - {{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10Plus}, - {{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10Plus}, + {{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10_GFX11}, + {{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10_GFX11}, {{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK, isGFX10Before1030}, {{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus}, {{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus}, {{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10}, {{""}}, - {{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA, isGFX11Plus}, + {{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx11, isGFX11}, {{""}}, - {{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_BEncoding}, - - // Register numbers reused in GFX11+ - {{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO, isGFX11Plus}, - {{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI, isGFX11Plus}, + {{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_3_GFX11}, + {{"HW_REG_SHADER_CYCLES_HI"}, ID_SHADER_CYCLES_HI, isGFX12Plus}, + {{"HW_REG_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus}, + {{"HW_REG_DVGPR_ALLOC_HI"}, ID_DVGPR_ALLOC_HI, isGFX12Plus}, + + // Register numbers reused in GFX11 + {{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO_gfx11, isGFX11}, + {{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI_gfx11, isGFX11}, + + // Register numbers reused in GFX12+ + {{"HW_REG_STATE_PRIV"}, ID_STATE_PRIV, isGFX12Plus}, + {{"HW_REG_PERF_SNAPSHOT_DATA1"}, ID_PERF_SNAPSHOT_DATA1, isGFX12Plus}, + {{"HW_REG_PERF_SNAPSHOT_DATA2"}, ID_PERF_SNAPSHOT_DATA2, isGFX12Plus}, + {{"HW_REG_EXCP_FLAG_PRIV"}, ID_EXCP_FLAG_PRIV, isGFX12Plus}, + {{"HW_REG_EXCP_FLAG_USER"}, ID_EXCP_FLAG_USER, isGFX12Plus}, + {{"HW_REG_TRAP_CTRL"}, ID_TRAP_CTRL, isGFX12Plus}, + {{"HW_REG_SCRATCH_BASE_LO"}, ID_FLAT_SCR_LO, isGFX12Plus}, + {{"HW_REG_SCRATCH_BASE_HI"}, ID_FLAT_SCR_HI, isGFX12Plus}, + {{"HW_REG_SHADER_CYCLES_LO"}, ID_SHADER_CYCLES, isGFX12Plus}, // GFX940 specific registers {{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940}, @@ -133,6 +148,7 @@ const CustomOperand Opr[] = { // Aliases {{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10}, }; +// clang-format on // NOLINTEND const int OPR_SIZE = static_cast( diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 3aacde50523f..68d561a0d9f7 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -2604,6 +2604,9 @@ static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST) { bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset) { + if (isGFX12Plus(ST)) + return isUInt<23>(EncodedOffset); + return hasSMEMByteOffset(ST) ? isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset); } @@ -2611,6 +2614,9 @@ bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer) { + if (isGFX12Plus(ST)) + return isInt<24>(EncodedOffset); + return !IsBuffer && hasSMRDSignedImmOffset(ST) && isInt<21>(EncodedOffset); @@ -2631,6 +2637,10 @@ uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, std::optional getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer) { + if (isGFX12Plus(ST)) // 24 bit signed offsets + return isInt<24>(ByteOffset) ? std::optional(ByteOffset) + : std::nullopt; + // The signed version is always a byte offset. if (!IsBuffer && hasSMRDSignedImmOffset(ST)) { assert(hasSMEMByteOffset(ST)); diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 476a9bb15edb..b85107ec4719 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -4836,7 +4836,7 @@ bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, unsigned DefClass = DefMI.getDesc().getSchedClass(); std::optional DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); - return DefCycle <= 2U; + return DefCycle && DefCycle <= 2U; } return false; } diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 36e3d1fbf856..db63facca870 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -10402,10 +10402,7 @@ static void ReplaceREADCYCLECOUNTER(SDNode *N, static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V) { SDLoc dl(V.getNode()); - SDValue VLo = DAG.getAnyExtOrTrunc(V, dl, MVT::i32); - SDValue VHi = DAG.getAnyExtOrTrunc( - DAG.getNode(ISD::SRL, dl, MVT::i64, V, DAG.getConstant(32, dl, MVT::i32)), - dl, MVT::i32); + auto [VLo, VHi] = DAG.SplitScalar(V, dl, MVT::i32, MVT::i32); bool isBigEndian = DAG.getDataLayout().isBigEndian(); if (isBigEndian) std::swap (VLo, VHi); diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp index 401398bdd4b1..0f4ece64bff5 100644 --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -40,7 +40,6 @@ #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" -#include #include #include #include diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h index 1f539d3270b7..436cd62c2581 100644 --- a/llvm/lib/Target/BPF/BPF.h +++ b/llvm/lib/Target/BPF/BPF.h @@ -10,6 +10,7 @@ #define LLVM_LIB_TARGET_BPF_BPF_H #include "MCTargetDesc/BPFMCTargetDesc.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include "llvm/Target/TargetMachine.h" @@ -62,6 +63,24 @@ class BPFAdjustOptPass : public PassInfoMixin { public: PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); }; + +class BPFPreserveStaticOffsetPass + : public PassInfoMixin { + bool AllowPartial; + +public: + BPFPreserveStaticOffsetPass(bool AllowPartial) : AllowPartial(AllowPartial) {} + PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + + static bool isRequired() { return true; } + + static std::pair + reconstructLoad(CallInst *Call); + + static std::pair + reconstructStore(CallInst *Call); +}; + } // namespace llvm #endif diff --git a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp index 1895d15c1f55..9634c16a30dc 100644 --- a/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp +++ b/llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp @@ -172,8 +172,6 @@ private: bool IsValidAIChain(const MDNode *ParentMeta, uint32_t ParentAI, const MDNode *ChildMeta); bool removePreserveAccessIndexIntrinsic(Function &F); - void replaceWithGEP(std::vector &CallList, - uint32_t NumOfZerosIndex, uint32_t DIIndex); bool HasPreserveFieldInfoCall(CallInfoStack &CallStack); void GetStorageBitRange(DIDerivedType *MemberTy, Align RecordAlignment, uint32_t &StartBitOffset, uint32_t &EndBitOffset); @@ -185,7 +183,6 @@ private: std::string &AccessKey, MDNode *&BaseMeta); MDNode *computeAccessKey(CallInst *Call, CallInfo &CInfo, std::string &AccessKey, bool &IsInt32Ret); - uint64_t getConstant(const Value *IndexValue); bool transformGEPChain(CallInst *Call, CallInfo &CInfo); }; @@ -326,6 +323,12 @@ static Type *getBaseElementType(const CallInst *Call) { return Call->getParamElementType(0); } +static uint64_t getConstant(const Value *IndexValue) { + const ConstantInt *CV = dyn_cast(IndexValue); + assert(CV); + return CV->getValue().getZExtValue(); +} + /// Check whether a call is a preserve_*_access_index intrinsic call or not. bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call, CallInfo &CInfo) { @@ -410,26 +413,36 @@ bool BPFAbstractMemberAccess::IsPreserveDIAccessIndexCall(const CallInst *Call, return false; } -void BPFAbstractMemberAccess::replaceWithGEP(std::vector &CallList, - uint32_t DimensionIndex, - uint32_t GEPIndex) { - for (auto *Call : CallList) { - uint32_t Dimension = 1; - if (DimensionIndex > 0) - Dimension = getConstant(Call->getArgOperand(DimensionIndex)); - - Constant *Zero = - ConstantInt::get(Type::getInt32Ty(Call->getParent()->getContext()), 0); - SmallVector IdxList; - for (unsigned I = 0; I < Dimension; ++I) - IdxList.push_back(Zero); - IdxList.push_back(Call->getArgOperand(GEPIndex)); - - auto *GEP = GetElementPtrInst::CreateInBounds( - getBaseElementType(Call), Call->getArgOperand(0), IdxList, "", Call); - Call->replaceAllUsesWith(GEP); - Call->eraseFromParent(); - } +static void replaceWithGEP(CallInst *Call, uint32_t DimensionIndex, + uint32_t GEPIndex) { + uint32_t Dimension = 1; + if (DimensionIndex > 0) + Dimension = getConstant(Call->getArgOperand(DimensionIndex)); + + Constant *Zero = + ConstantInt::get(Type::getInt32Ty(Call->getParent()->getContext()), 0); + SmallVector IdxList; + for (unsigned I = 0; I < Dimension; ++I) + IdxList.push_back(Zero); + IdxList.push_back(Call->getArgOperand(GEPIndex)); + + auto *GEP = GetElementPtrInst::CreateInBounds( + getBaseElementType(Call), Call->getArgOperand(0), IdxList, "", Call); + Call->replaceAllUsesWith(GEP); + Call->eraseFromParent(); +} + +void BPFCoreSharedInfo::removeArrayAccessCall(CallInst *Call) { + replaceWithGEP(Call, 1, 2); +} + +void BPFCoreSharedInfo::removeStructAccessCall(CallInst *Call) { + replaceWithGEP(Call, 0, 1); +} + +void BPFCoreSharedInfo::removeUnionAccessCall(CallInst *Call) { + Call->replaceAllUsesWith(Call->getArgOperand(0)); + Call->eraseFromParent(); } bool BPFAbstractMemberAccess::removePreserveAccessIndexIntrinsic(Function &F) { @@ -464,12 +477,12 @@ bool BPFAbstractMemberAccess::removePreserveAccessIndexIntrinsic(Function &F) { // . addr = preserve_struct_access_index(base, gep_index, di_index) // is transformed to // addr = GEP(base, 0, gep_index) - replaceWithGEP(PreserveArrayIndexCalls, 1, 2); - replaceWithGEP(PreserveStructIndexCalls, 0, 1); - for (auto *Call : PreserveUnionIndexCalls) { - Call->replaceAllUsesWith(Call->getArgOperand(0)); - Call->eraseFromParent(); - } + for (CallInst *Call : PreserveArrayIndexCalls) + BPFCoreSharedInfo::removeArrayAccessCall(Call); + for (CallInst *Call : PreserveStructIndexCalls) + BPFCoreSharedInfo::removeStructAccessCall(Call); + for (CallInst *Call : PreserveUnionIndexCalls) + BPFCoreSharedInfo::removeUnionAccessCall(Call); return Found; } @@ -634,12 +647,6 @@ void BPFAbstractMemberAccess::collectAICallChains(Function &F) { } } -uint64_t BPFAbstractMemberAccess::getConstant(const Value *IndexValue) { - const ConstantInt *CV = dyn_cast(IndexValue); - assert(CV); - return CV->getValue().getZExtValue(); -} - /// Get the start and the end of storage offset for \p MemberTy. void BPFAbstractMemberAccess::GetStorageBitRange(DIDerivedType *MemberTy, Align RecordAlignment, diff --git a/llvm/lib/Target/BPF/BPFCORE.h b/llvm/lib/Target/BPF/BPFCORE.h index 9a547a775c96..f46a8ef62a7f 100644 --- a/llvm/lib/Target/BPF/BPFCORE.h +++ b/llvm/lib/Target/BPF/BPFCORE.h @@ -10,6 +10,7 @@ #define LLVM_LIB_TARGET_BPF_BPFCORE_H #include "llvm/ADT/StringRef.h" +#include "llvm/IR/Instructions.h" namespace llvm { @@ -53,6 +54,9 @@ public: static Instruction *insertPassThrough(Module *M, BasicBlock *BB, Instruction *Input, Instruction *Before); + static void removeArrayAccessCall(CallInst *Call); + static void removeStructAccessCall(CallInst *Call); + static void removeUnionAccessCall(CallInst *Call); }; } // namespace llvm diff --git a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp index a3616ae7ebab..56c89f61b319 100644 --- a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp +++ b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp @@ -12,6 +12,8 @@ // The following are done for IR adjustment: // - remove __builtin_bpf_passthrough builtins. Target independent IR // optimizations are done and those builtins can be removed. +// - remove llvm.bpf.getelementptr.and.load builtins. +// - remove llvm.bpf.getelementptr.and.store builtins. // //===----------------------------------------------------------------------===// @@ -24,6 +26,7 @@ #include "llvm/IR/IRBuilder.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicsBPF.h" #include "llvm/IR/Module.h" #include "llvm/IR/Type.h" #include "llvm/IR/User.h" @@ -51,6 +54,7 @@ private: bool removePassThroughBuiltin(Module &M); bool removeCompareBuiltin(Module &M); bool sinkMinMax(Module &M); + bool removeGEPBuiltins(Module &M); }; } // End anonymous namespace @@ -361,10 +365,62 @@ void BPFCheckAndAdjustIR::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); } +static void unrollGEPLoad(CallInst *Call) { + auto [GEP, Load] = BPFPreserveStaticOffsetPass::reconstructLoad(Call); + GEP->insertBefore(Call); + Load->insertBefore(Call); + Call->replaceAllUsesWith(Load); + Call->eraseFromParent(); +} + +static void unrollGEPStore(CallInst *Call) { + auto [GEP, Store] = BPFPreserveStaticOffsetPass::reconstructStore(Call); + GEP->insertBefore(Call); + Store->insertBefore(Call); + Call->eraseFromParent(); +} + +static bool removeGEPBuiltinsInFunc(Function &F) { + SmallVector GEPLoads; + SmallVector GEPStores; + for (auto &BB : F) + for (auto &Insn : BB) + if (auto *Call = dyn_cast(&Insn)) + if (auto *Called = Call->getCalledFunction()) + switch (Called->getIntrinsicID()) { + case Intrinsic::bpf_getelementptr_and_load: + GEPLoads.push_back(Call); + break; + case Intrinsic::bpf_getelementptr_and_store: + GEPStores.push_back(Call); + break; + } + + if (GEPLoads.empty() && GEPStores.empty()) + return false; + + for_each(GEPLoads, unrollGEPLoad); + for_each(GEPStores, unrollGEPStore); + + return true; +} + +// Rewrites the following builtins: +// - llvm.bpf.getelementptr.and.load +// - llvm.bpf.getelementptr.and.store +// As (load (getelementptr ...)) or (store (getelementptr ...)). +bool BPFCheckAndAdjustIR::removeGEPBuiltins(Module &M) { + bool Changed = false; + for (auto &F : M) + Changed = removeGEPBuiltinsInFunc(F) || Changed; + return Changed; +} + bool BPFCheckAndAdjustIR::adjustIR(Module &M) { bool Changed = removePassThroughBuiltin(M); Changed = removeCompareBuiltin(M) || Changed; Changed = sinkMinMax(M) || Changed; + Changed = removeGEPBuiltins(M) || Changed; return Changed; } diff --git a/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp b/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp new file mode 100644 index 000000000000..c64fe00beaef --- /dev/null +++ b/llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp @@ -0,0 +1,680 @@ +//===------ BPFPreserveStaticOffset.cpp -----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// TLDR: replaces llvm.preserve.static.offset + GEP + load / store +// with llvm.bpf.getelementptr.and.load / store +// +// This file implements BPFPreserveStaticOffsetPass transformation. +// This transformation address two BPF verifier specific issues: +// +// (a) Access to the fields of some structural types is allowed only +// using load and store instructions with static immediate offsets. +// +// Examples of such types are `struct __sk_buff` and `struct +// bpf_sock_ops`. This is so because offsets of the fields of +// these structures do not match real offsets in the running +// kernel. During BPF program load LDX and STX instructions +// referring to the fields of these types are rewritten so that +// offsets match real offsets. For this rewrite to happen field +// offsets have to be encoded as immediate operands of the +// instructions. +// +// See kernel/bpf/verifier.c:convert_ctx_access function in the +// Linux kernel source tree for details. +// +// (b) Pointers to context parameters of BPF programs must not be +// modified before access. +// +// During BPF program verification a tag PTR_TO_CTX is tracked for +// register values. In case if register with such tag is modified +// BPF program is not allowed to read or write memory using this +// register. See kernel/bpf/verifier.c:check_mem_access function +// in the Linux kernel source tree for details. +// +// The following sequence of the IR instructions: +// +// %x = getelementptr %ptr, %constant_offset +// %y = load %x +// +// Is translated as a single machine instruction: +// +// LDW %ptr, %constant_offset +// +// In order for cases (a) and (b) to work the sequence %x-%y above has +// to be preserved by the IR passes. +// +// However, several optimization passes might sink `load` instruction +// or hoist `getelementptr` instruction so that the instructions are +// no longer in sequence. Examples of such passes are: +// SimplifyCFGPass, InstCombinePass, GVNPass. +// After such modification the verifier would reject the BPF program. +// +// To avoid this issue the patterns like (load/store (getelementptr ...)) +// are replaced by calls to BPF specific intrinsic functions: +// - llvm.bpf.getelementptr.and.load +// - llvm.bpf.getelementptr.and.store +// +// These calls are lowered back to (load/store (getelementptr ...)) +// by BPFCheckAndAdjustIR pass right before the translation from IR to +// machine instructions. +// +// The transformation is split into the following steps: +// - When IR is generated from AST the calls to intrinsic function +// llvm.preserve.static.offset are inserted. +// - BPFPreserveStaticOffsetPass is executed as early as possible +// with AllowPatial set to true, this handles marked GEP chains +// with constant offsets. +// - BPFPreserveStaticOffsetPass is executed at ScalarOptimizerLateEPCallback +// with AllowPatial set to false, this handles marked GEP chains +// with offsets that became constant after loop unrolling, e.g. +// to handle the following code: +// +// struct context { int x[4]; } __attribute__((preserve_static_offset)); +// +// struct context *ctx = ...; +// #pragma clang loop unroll(full) +// for (int i = 0; i < 4; ++i) +// foo(ctx->x[i]); +// +// The early BPFPreserveStaticOffsetPass run is necessary to allow +// additional GVN / CSE opportunities after functions inlining. +// The relative order of optimization applied to function: +// - early stage (1) +// - ... +// - function inlining (2) +// - ... +// - loop unrolling +// - ... +// - ScalarOptimizerLateEPCallback (3) +// +// When function A is inlined into function B all optimizations for A +// are already done, while some passes remain for B. In case if +// BPFPreserveStaticOffsetPass is done at (3) but not done at (1) +// the code after (2) would contain a mix of +// (load (gep %p)) and (get.and.load %p) usages: +// - the (load (gep %p)) would come from the calling function; +// - the (get.and.load %p) would come from the callee function. +// Thus clobbering CSE / GVN passes done after inlining. + +#include "BPF.h" +#include "BPFCORE.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/IR/Argument.h" +#include "llvm/IR/Attributes.h" +#include "llvm/IR/BasicBlock.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DebugInfoMetadata.h" +#include "llvm/IR/DiagnosticInfo.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/InstIterator.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/Intrinsics.h" +#include "llvm/IR/IntrinsicsBPF.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" + +#define DEBUG_TYPE "bpf-preserve-static-offset" + +using namespace llvm; + +static const unsigned GepAndLoadFirstIdxArg = 6; +static const unsigned GepAndStoreFirstIdxArg = 7; + +static bool isIntrinsicCall(Value *I, Intrinsic::ID Id) { + if (auto *Call = dyn_cast(I)) + if (Function *Func = Call->getCalledFunction()) + return Func->getIntrinsicID() == Id; + return false; +} + +static bool isPreserveStaticOffsetCall(Value *I) { + return isIntrinsicCall(I, Intrinsic::preserve_static_offset); +} + +static CallInst *isGEPAndLoad(Value *I) { + if (isIntrinsicCall(I, Intrinsic::bpf_getelementptr_and_load)) + return cast(I); + return nullptr; +} + +static CallInst *isGEPAndStore(Value *I) { + if (isIntrinsicCall(I, Intrinsic::bpf_getelementptr_and_store)) + return cast(I); + return nullptr; +} + +template +static DILocation *mergeDILocations(SmallVector &Insns) { + DILocation *Merged = (*Insns.begin())->getDebugLoc(); + for (T *I : Insns) + Merged = DILocation::getMergedLocation(Merged, I->getDebugLoc()); + return Merged; +} + +static CallInst *makeIntrinsicCall(Module *M, + Intrinsic::BPFIntrinsics Intrinsic, + ArrayRef Types, + ArrayRef Args) { + + Function *Fn = Intrinsic::getDeclaration(M, Intrinsic, Types); + return CallInst::Create(Fn, Args); +} + +static void setParamElementType(CallInst *Call, unsigned ArgNo, Type *Type) { + LLVMContext &C = Call->getContext(); + Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::ElementType, Type)); +} + +static void setParamReadNone(CallInst *Call, unsigned ArgNo) { + LLVMContext &C = Call->getContext(); + Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::ReadNone)); +} + +static void setParamReadOnly(CallInst *Call, unsigned ArgNo) { + LLVMContext &C = Call->getContext(); + Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::ReadOnly)); +} + +static void setParamWriteOnly(CallInst *Call, unsigned ArgNo) { + LLVMContext &C = Call->getContext(); + Call->addParamAttr(ArgNo, Attribute::get(C, Attribute::WriteOnly)); +} + +namespace { +struct GEPChainInfo { + bool InBounds; + Type *SourceElementType; + SmallVector Indices; + SmallVector Members; + + GEPChainInfo() { reset(); } + + void reset() { + InBounds = true; + SourceElementType = nullptr; + Indices.clear(); + Members.clear(); + } +}; +} // Anonymous namespace + +template > +static void fillCommonArgs(LLVMContext &C, SmallVector &Args, + GEPChainInfo &GEP, T *Insn) { + Type *Int8Ty = Type::getInt8Ty(C); + Type *Int1Ty = Type::getInt1Ty(C); + // Implementation of Align guarantees that ShiftValue < 64 + unsigned AlignShiftValue = Log2_64(Insn->getAlign().value()); + Args.push_back(GEP.Members[0]->getPointerOperand()); + Args.push_back(ConstantInt::get(Int1Ty, Insn->isVolatile())); + Args.push_back(ConstantInt::get(Int8Ty, (unsigned)Insn->getOrdering())); + Args.push_back(ConstantInt::get(Int8Ty, (unsigned)Insn->getSyncScopeID())); + Args.push_back(ConstantInt::get(Int8Ty, AlignShiftValue)); + Args.push_back(ConstantInt::get(Int1Ty, GEP.InBounds)); + Args.append(GEP.Indices.begin(), GEP.Indices.end()); +} + +static Instruction *makeGEPAndLoad(Module *M, GEPChainInfo &GEP, + LoadInst *Load) { + SmallVector Args; + fillCommonArgs(M->getContext(), Args, GEP, Load); + CallInst *Call = makeIntrinsicCall(M, Intrinsic::bpf_getelementptr_and_load, + {Load->getType()}, Args); + setParamElementType(Call, 0, GEP.SourceElementType); + Call->applyMergedLocation(mergeDILocations(GEP.Members), Load->getDebugLoc()); + Call->setName((*GEP.Members.rbegin())->getName()); + if (Load->isUnordered()) { + Call->setOnlyReadsMemory(); + Call->setOnlyAccessesArgMemory(); + setParamReadOnly(Call, 0); + } + for (unsigned I = GepAndLoadFirstIdxArg; I < Args.size(); ++I) + Call->addParamAttr(I, Attribute::ImmArg); + Call->setAAMetadata(Load->getAAMetadata()); + return Call; +} + +static Instruction *makeGEPAndStore(Module *M, GEPChainInfo &GEP, + StoreInst *Store) { + SmallVector Args; + Args.push_back(Store->getValueOperand()); + fillCommonArgs(M->getContext(), Args, GEP, Store); + CallInst *Call = + makeIntrinsicCall(M, Intrinsic::bpf_getelementptr_and_store, + {Store->getValueOperand()->getType()}, Args); + setParamElementType(Call, 1, GEP.SourceElementType); + if (Store->getValueOperand()->getType()->isPointerTy()) + setParamReadNone(Call, 0); + Call->applyMergedLocation(mergeDILocations(GEP.Members), + Store->getDebugLoc()); + if (Store->isUnordered()) { + Call->setOnlyWritesMemory(); + Call->setOnlyAccessesArgMemory(); + setParamWriteOnly(Call, 1); + } + for (unsigned I = GepAndStoreFirstIdxArg; I < Args.size(); ++I) + Call->addParamAttr(I, Attribute::ImmArg); + Call->setAAMetadata(Store->getAAMetadata()); + return Call; +} + +static unsigned getOperandAsUnsigned(CallInst *Call, unsigned ArgNo) { + if (auto *Int = dyn_cast(Call->getOperand(ArgNo))) + return Int->getValue().getZExtValue(); + std::string Report; + raw_string_ostream ReportS(Report); + ReportS << "Expecting ConstantInt as argument #" << ArgNo << " of " << *Call + << "\n"; + report_fatal_error(StringRef(Report)); +} + +static GetElementPtrInst *reconstructGEP(CallInst *Call, int Delta) { + SmallVector Indices; + Indices.append(Call->data_operands_begin() + 6 + Delta, + Call->data_operands_end()); + Type *GEPPointeeType = Call->getParamElementType(Delta); + auto *GEP = + GetElementPtrInst::Create(GEPPointeeType, Call->getOperand(Delta), + ArrayRef(Indices), Call->getName()); + GEP->setIsInBounds(getOperandAsUnsigned(Call, 5 + Delta)); + return GEP; +} + +template > +static void reconstructCommon(CallInst *Call, GetElementPtrInst *GEP, T *Insn, + int Delta) { + Insn->setVolatile(getOperandAsUnsigned(Call, 1 + Delta)); + Insn->setOrdering((AtomicOrdering)getOperandAsUnsigned(Call, 2 + Delta)); + Insn->setSyncScopeID(getOperandAsUnsigned(Call, 3 + Delta)); + unsigned AlignShiftValue = getOperandAsUnsigned(Call, 4 + Delta); + Insn->setAlignment(Align(1ULL << AlignShiftValue)); + GEP->setDebugLoc(Call->getDebugLoc()); + Insn->setDebugLoc(Call->getDebugLoc()); + Insn->setAAMetadata(Call->getAAMetadata()); +} + +std::pair +BPFPreserveStaticOffsetPass::reconstructLoad(CallInst *Call) { + GetElementPtrInst *GEP = reconstructGEP(Call, 0); + Type *ReturnType = Call->getFunctionType()->getReturnType(); + auto *Load = new LoadInst(ReturnType, GEP, "", + /* These would be set in reconstructCommon */ + false, Align(1)); + reconstructCommon(Call, GEP, Load, 0); + return std::pair{GEP, Load}; +} + +std::pair +BPFPreserveStaticOffsetPass::reconstructStore(CallInst *Call) { + GetElementPtrInst *GEP = reconstructGEP(Call, 1); + auto *Store = new StoreInst(Call->getOperand(0), GEP, + /* These would be set in reconstructCommon */ + false, Align(1)); + reconstructCommon(Call, GEP, Store, 1); + return std::pair{GEP, Store}; +} + +static bool isZero(Value *V) { + auto *CI = dyn_cast(V); + return CI && CI->isZero(); +} + +// Given a chain of GEP instructions collect information necessary to +// merge this chain as a single GEP instruction of form: +// getelementptr %, ptr %p, i32 0, , , ... +static bool foldGEPChainAsStructAccess(SmallVector &GEPs, + GEPChainInfo &Info) { + if (GEPs.empty()) + return false; + + if (!all_of(GEPs, [=](GetElementPtrInst *GEP) { + return GEP->hasAllConstantIndices(); + })) + return false; + + GetElementPtrInst *First = GEPs[0]; + Info.InBounds = First->isInBounds(); + Info.SourceElementType = First->getSourceElementType(); + Type *ResultElementType = First->getResultElementType(); + Info.Indices.append(First->idx_begin(), First->idx_end()); + Info.Members.push_back(First); + + for (auto *Iter = GEPs.begin() + 1; Iter != GEPs.end(); ++Iter) { + GetElementPtrInst *GEP = *Iter; + if (!isZero(*GEP->idx_begin())) { + Info.reset(); + return false; + } + if (!GEP->getSourceElementType() || + GEP->getSourceElementType() != ResultElementType) { + Info.reset(); + return false; + } + Info.InBounds &= GEP->isInBounds(); + Info.Indices.append(GEP->idx_begin() + 1, GEP->idx_end()); + Info.Members.push_back(GEP); + ResultElementType = GEP->getResultElementType(); + } + + return true; +} + +// Given a chain of GEP instructions collect information necessary to +// merge this chain as a single GEP instruction of form: +// getelementptr i8, ptr %p, i64 %offset +static bool foldGEPChainAsU8Access(SmallVector &GEPs, + GEPChainInfo &Info) { + if (GEPs.empty()) + return false; + + GetElementPtrInst *First = GEPs[0]; + const DataLayout &DL = First->getModule()->getDataLayout(); + LLVMContext &C = First->getContext(); + Type *PtrTy = First->getType()->getScalarType(); + APInt Offset(DL.getIndexTypeSizeInBits(PtrTy), 0); + for (GetElementPtrInst *GEP : GEPs) { + if (!GEP->accumulateConstantOffset(DL, Offset)) { + Info.reset(); + return false; + } + Info.InBounds &= GEP->isInBounds(); + Info.Members.push_back(GEP); + } + Info.SourceElementType = Type::getInt8Ty(C); + Info.Indices.push_back(ConstantInt::get(C, Offset)); + + return true; +} + +static void reportNonStaticGEPChain(Instruction *Insn) { + auto Msg = DiagnosticInfoUnsupported( + *Insn->getFunction(), + Twine("Non-constant offset in access to a field of a type marked " + "with preserve_static_offset might be rejected by BPF verifier") + .concat(Insn->getDebugLoc() + ? "" + : " (pass -g option to get exact location)"), + Insn->getDebugLoc(), DS_Warning); + Insn->getContext().diagnose(Msg); +} + +static bool allZeroIndices(SmallVector &GEPs) { + return GEPs.empty() || all_of(GEPs, [=](GetElementPtrInst *GEP) { + return GEP->hasAllZeroIndices(); + }); +} + +static bool tryToReplaceWithGEPBuiltin(Instruction *LoadOrStoreTemplate, + SmallVector &GEPs, + Instruction *InsnToReplace) { + GEPChainInfo GEPChain; + if (!foldGEPChainAsStructAccess(GEPs, GEPChain) && + !foldGEPChainAsU8Access(GEPs, GEPChain)) { + return false; + } + Module *M = InsnToReplace->getModule(); + if (auto *Load = dyn_cast(LoadOrStoreTemplate)) { + Instruction *Replacement = makeGEPAndLoad(M, GEPChain, Load); + Replacement->insertBefore(InsnToReplace); + InsnToReplace->replaceAllUsesWith(Replacement); + } + if (auto *Store = dyn_cast(LoadOrStoreTemplate)) { + Instruction *Replacement = makeGEPAndStore(M, GEPChain, Store); + Replacement->insertBefore(InsnToReplace); + } + return true; +} + +// Check if U->getPointerOperand() == I +static bool isPointerOperand(Value *I, User *U) { + if (auto *L = dyn_cast(U)) + return L->getPointerOperand() == I; + if (auto *S = dyn_cast(U)) + return S->getPointerOperand() == I; + if (auto *GEP = dyn_cast(U)) + return GEP->getPointerOperand() == I; + if (auto *Call = isGEPAndLoad(U)) + return Call->getArgOperand(0) == I; + if (auto *Call = isGEPAndStore(U)) + return Call->getArgOperand(1) == I; + return false; +} + +static bool isInlineableCall(User *U) { + if (auto *Call = dyn_cast(U)) + return Call->hasFnAttr(Attribute::InlineHint); + return false; +} + +static void rewriteAccessChain(Instruction *Insn, + SmallVector &GEPs, + SmallVector &Visited, + bool AllowPatial, bool &StillUsed); + +static void rewriteUses(Instruction *Insn, + SmallVector &GEPs, + SmallVector &Visited, bool AllowPatial, + bool &StillUsed) { + for (User *U : Insn->users()) { + auto *UI = dyn_cast(U); + if (UI && (isPointerOperand(Insn, UI) || isPreserveStaticOffsetCall(UI) || + isInlineableCall(UI))) + rewriteAccessChain(UI, GEPs, Visited, AllowPatial, StillUsed); + else + LLVM_DEBUG({ + llvm::dbgs() << "unsupported usage in BPFPreserveStaticOffsetPass:\n"; + llvm::dbgs() << " Insn: " << *Insn << "\n"; + llvm::dbgs() << " User: " << *U << "\n"; + }); + } +} + +// A DFS traversal of GEP chain trees starting from Root. +// +// Recursion descends through GEP instructions and +// llvm.preserve.static.offset calls. Recursion stops at any other +// instruction. If load or store instruction is reached it is replaced +// by a call to `llvm.bpf.getelementptr.and.load` or +// `llvm.bpf.getelementptr.and.store` intrinsic. +// If `llvm.bpf.getelementptr.and.load/store` is reached the accumulated +// GEPs are merged into the intrinsic call. +// If nested calls to `llvm.preserve.static.offset` are encountered these +// calls are marked for deletion. +// +// Parameters description: +// - Insn - current position in the tree +// - GEPs - GEP instructions for the current branch +// - Visited - a list of visited instructions in DFS order, +// order is important for unused instruction deletion. +// - AllowPartial - when true GEP chains that can't be folded are +// not reported, otherwise diagnostic message is show for such chains. +// - StillUsed - set to true if one of the GEP chains could not be +// folded, makes sense when AllowPartial is false, means that root +// preserve.static.offset call is still in use and should remain +// until the next run of this pass. +static void rewriteAccessChain(Instruction *Insn, + SmallVector &GEPs, + SmallVector &Visited, + bool AllowPatial, bool &StillUsed) { + auto MarkAndTraverseUses = [&]() { + Visited.push_back(Insn); + rewriteUses(Insn, GEPs, Visited, AllowPatial, StillUsed); + }; + auto TryToReplace = [&](Instruction *LoadOrStore) { + // Do nothing for (preserve.static.offset (load/store ..)) or for + // GEPs with zero indices. Such constructs lead to zero offset and + // are simplified by other passes. + if (allZeroIndices(GEPs)) + return; + if (tryToReplaceWithGEPBuiltin(LoadOrStore, GEPs, Insn)) { + Visited.push_back(Insn); + return; + } + if (!AllowPatial) + reportNonStaticGEPChain(Insn); + StillUsed = true; + }; + if (isa(Insn) || isa(Insn)) { + TryToReplace(Insn); + } else if (isGEPAndLoad(Insn)) { + auto [GEP, Load] = + BPFPreserveStaticOffsetPass::reconstructLoad(cast(Insn)); + GEPs.push_back(GEP); + TryToReplace(Load); + GEPs.pop_back(); + delete Load; + delete GEP; + } else if (isGEPAndStore(Insn)) { + // This case can't be merged with the above because + // `delete Load` / `delete Store` wants a concrete type, + // destructor of Instruction is protected. + auto [GEP, Store] = + BPFPreserveStaticOffsetPass::reconstructStore(cast(Insn)); + GEPs.push_back(GEP); + TryToReplace(Store); + GEPs.pop_back(); + delete Store; + delete GEP; + } else if (auto *GEP = dyn_cast(Insn)) { + GEPs.push_back(GEP); + MarkAndTraverseUses(); + GEPs.pop_back(); + } else if (isPreserveStaticOffsetCall(Insn)) { + MarkAndTraverseUses(); + } else if (isInlineableCall(Insn)) { + // Preserve preserve.static.offset call for parameters of + // functions that might be inlined. These would be removed on a + // second pass after inlining. + // Might happen when a pointer to a preserve_static_offset + // structure is passed as parameter of a function that would be + // inlined inside a loop that would be unrolled. + if (AllowPatial) + StillUsed = true; + } else { + SmallString<128> Buf; + raw_svector_ostream BufStream(Buf); + BufStream << *Insn; + report_fatal_error( + Twine("Unexpected rewriteAccessChain Insn = ").concat(Buf)); + } +} + +static void removeMarkerCall(Instruction *Marker) { + Marker->replaceAllUsesWith(Marker->getOperand(0)); + Marker->eraseFromParent(); +} + +static bool rewriteAccessChain(Instruction *Marker, bool AllowPatial, + SmallPtrSetImpl &RemovedMarkers) { + SmallVector GEPs; + SmallVector Visited; + bool StillUsed = false; + rewriteUses(Marker, GEPs, Visited, AllowPatial, StillUsed); + // Check if Visited instructions could be removed, iterate in + // reverse to unblock instructions higher in the chain. + for (auto V = Visited.rbegin(); V != Visited.rend(); ++V) { + if (isPreserveStaticOffsetCall(*V)) { + removeMarkerCall(*V); + RemovedMarkers.insert(*V); + } else if ((*V)->use_empty()) { + (*V)->eraseFromParent(); + } + } + return StillUsed; +} + +static std::vector +collectPreserveStaticOffsetCalls(Function &F) { + std::vector Calls; + for (Instruction &Insn : instructions(F)) + if (isPreserveStaticOffsetCall(&Insn)) + Calls.push_back(&Insn); + return Calls; +} + +bool isPreserveArrayIndex(Value *V) { + return isIntrinsicCall(V, Intrinsic::preserve_array_access_index); +} + +bool isPreserveStructIndex(Value *V) { + return isIntrinsicCall(V, Intrinsic::preserve_struct_access_index); +} + +bool isPreserveUnionIndex(Value *V) { + return isIntrinsicCall(V, Intrinsic::preserve_union_access_index); +} + +static void removePAICalls(Instruction *Marker) { + auto IsPointerOperand = [](Value *Op, User *U) { + if (auto *GEP = dyn_cast(U)) + return GEP->getPointerOperand() == Op; + if (isPreserveStaticOffsetCall(U) || isPreserveArrayIndex(U) || + isPreserveStructIndex(U) || isPreserveUnionIndex(U)) + return cast(U)->getArgOperand(0) == Op; + return false; + }; + + SmallVector WorkList; + WorkList.push_back(Marker); + do { + Value *V = WorkList.pop_back_val(); + for (User *U : V->users()) + if (IsPointerOperand(V, U)) + WorkList.push_back(U); + auto *Call = dyn_cast(V); + if (!Call) + continue; + if (isPreserveArrayIndex(V)) + BPFCoreSharedInfo::removeArrayAccessCall(Call); + else if (isPreserveStructIndex(V)) + BPFCoreSharedInfo::removeStructAccessCall(Call); + else if (isPreserveUnionIndex(V)) + BPFCoreSharedInfo::removeUnionAccessCall(Call); + } while (!WorkList.empty()); +} + +// Look for sequences: +// - llvm.preserve.static.offset -> getelementptr... -> load +// - llvm.preserve.static.offset -> getelementptr... -> store +// And replace those with calls to intrinsics: +// - llvm.bpf.getelementptr.and.load +// - llvm.bpf.getelementptr.and.store +static bool rewriteFunction(Function &F, bool AllowPartial) { + LLVM_DEBUG(dbgs() << "********** BPFPreserveStaticOffsetPass (AllowPartial=" + << AllowPartial << ") ************\n"); + + auto MarkerCalls = collectPreserveStaticOffsetCalls(F); + SmallPtrSet RemovedMarkers; + + LLVM_DEBUG(dbgs() << "There are " << MarkerCalls.size() + << " preserve.static.offset calls\n"); + + if (MarkerCalls.empty()) + return false; + + for (auto *Call : MarkerCalls) + removePAICalls(Call); + + for (auto *Call : MarkerCalls) { + if (RemovedMarkers.contains(Call)) + continue; + bool StillUsed = rewriteAccessChain(Call, AllowPartial, RemovedMarkers); + if (!StillUsed || !AllowPartial) + removeMarkerCall(Call); + } + + return true; +} + +PreservedAnalyses +llvm::BPFPreserveStaticOffsetPass::run(Function &F, + FunctionAnalysisManager &AM) { + return rewriteFunction(F, AllowPartial) ? PreservedAnalyses::none() + : PreservedAnalyses::all(); +} diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 983a4ff6aa5c..65286c822c4b 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -105,11 +105,16 @@ void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { FPM.addPass(BPFIRPeepholePass()); return true; } + if (PassName == "bpf-preserve-static-offset") { + FPM.addPass(BPFPreserveStaticOffsetPass(false)); + return true; + } return false; }); PB.registerPipelineStartEPCallback( [=](ModulePassManager &MPM, OptimizationLevel) { FunctionPassManager FPM; + FPM.addPass(BPFPreserveStaticOffsetPass(true)); FPM.addPass(BPFAbstractMemberAccessPass(this)); FPM.addPass(BPFPreserveDITypePass()); FPM.addPass(BPFIRPeepholePass()); @@ -119,6 +124,12 @@ void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { OptimizationLevel Level) { FPM.addPass(SimplifyCFGPass(SimplifyCFGOptions().hoistCommonInsts(true))); }); + PB.registerScalarOptimizerLateEPCallback( + [=](FunctionPassManager &FPM, OptimizationLevel Level) { + // Run this after loop unrolling but before + // SimplifyCFGPass(... .sinkCommonInsts(true)) + FPM.addPass(BPFPreserveStaticOffsetPass(false)); + }); PB.registerPipelineEarlySimplificationEPCallback( [=](ModulePassManager &MPM, OptimizationLevel) { MPM.addPass(BPFAdjustOptPass()); diff --git a/llvm/lib/Target/BPF/CMakeLists.txt b/llvm/lib/Target/BPF/CMakeLists.txt index f4a8fa3674cd..6a96394a6aee 100644 --- a/llvm/lib/Target/BPF/CMakeLists.txt +++ b/llvm/lib/Target/BPF/CMakeLists.txt @@ -26,6 +26,7 @@ add_llvm_target(BPFCodeGen BPFISelLowering.cpp BPFMCInstLower.cpp BPFPreserveDIType.cpp + BPFPreserveStaticOffset.cpp BPFRegisterInfo.cpp BPFSelectionDAGInfo.cpp BPFSubtarget.cpp diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index d297d115d59c..400327373ad1 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -246,6 +246,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); setOperationAction(ISD::BUILD_VECTOR, VT, Custom); + + setOperationAction(ISD::VSELECT, VT, Legal); } for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) { setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); @@ -277,6 +279,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); setOperationAction(ISD::BUILD_VECTOR, VT, Custom); + + setOperationAction(ISD::VSELECT, VT, Legal); } for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) { setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); @@ -314,6 +318,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, setStackPointerRegisterToSaveRestore(LoongArch::R3); setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); setMaxAtomicSizeInBitsSupported(Subtarget.getGRLen()); diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index 240f28b0dc5a..0bd8db1bfdf0 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -1480,6 +1480,14 @@ def : Pat<(f32 (vector_extract v8f32:$xj, i64:$rk)), def : Pat<(f64 (vector_extract v4f64:$xj, i64:$rk)), (f64 (EXTRACT_SUBREG (XVREPLVE_D v4f64:$xj, i64:$rk), sub_64))>; +// vselect +def : Pat<(v32i8 (vselect LASX256:$xj, LASX256:$xd, + (v32i8 (SplatPat_uimm8 uimm8:$imm)))), + (XVBITSELI_B LASX256:$xd, LASX256:$xj, uimm8:$imm)>; +foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in + def : Pat<(vt (vselect LASX256:$xa, LASX256:$xk, LASX256:$xj)), + (XVBITSEL_V LASX256:$xj, LASX256:$xk, LASX256:$xa)>; + } // Predicates = [HasExtLASX] /// Intrinsic pattern diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index fb4726c530b5..5800ff6f6266 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -1564,6 +1564,14 @@ def : Pat<(f32 (vector_extract v4f32:$vj, i64:$rk)), def : Pat<(f64 (vector_extract v2f64:$vj, i64:$rk)), (f64 (EXTRACT_SUBREG (VREPLVE_D v2f64:$vj, i64:$rk), sub_64))>; +// vselect +def : Pat<(v16i8 (vselect LSX128:$vj, LSX128:$vd, + (v16i8 (SplatPat_uimm8 uimm8:$imm)))), + (VBITSELI_B LSX128:$vd, LSX128:$vj, uimm8:$imm)>; +foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in + def : Pat<(vt (vselect LSX128:$va, LSX128:$vk, LSX128:$vj)), + (VBITSEL_V LSX128:$vj, LSX128:$vk, LSX128:$va)>; + } // Predicates = [HasExtLSX] /// Intrinsic pattern diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index b975825dae4b..61285c6ba98d 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -508,7 +508,6 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM, setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Expand); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i16, Expand); - // Conversion to/from i8/i8x4 is always legal. setOperationAction(ISD::BUILD_VECTOR, MVT::v4i8, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom); @@ -718,8 +717,8 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM, // We have some custom DAG combine patterns for these nodes setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::EXTRACT_VECTOR_ELT, ISD::FADD, - ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::STORE, - ISD::UREM, ISD::VSELECT}); + ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM, + ISD::VSELECT}); // setcc for f16x2 and bf16x2 needs special handling to prevent // legalizer's attempt to scalarize it due to v2i1 not being legal. @@ -2917,6 +2916,7 @@ NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const { DAG.getMemIntrinsicNode(Opcode, DL, DAG.getVTList(MVT::Other), Ops, MemSD->getMemoryVT(), MemSD->getMemOperand()); + // return DCI.CombineTo(N, NewSt, true); return NewSt; } @@ -5557,51 +5557,6 @@ static SDValue PerformLOADCombine(SDNode *N, DL); } -// Lower a v16i8 (or a v8i8) store into a StoreV4 (or StoreV2) operation with -// i32 results instead of letting ReplaceLoadVector split it into smaller stores -// during legalization. This is done at dag-combine1 time, so that vector -// operations with i8 elements can be optimised away instead of being needlessly -// split during legalization, which involves storing to the stack and loading it -// back. -static SDValue PerformSTORECombine(SDNode *N, - TargetLowering::DAGCombinerInfo &DCI) { - SelectionDAG &DAG = DCI.DAG; - StoreSDNode *ST = cast(N); - EVT VT = ST->getValue().getValueType(); - if (VT != MVT::v16i8 && VT != MVT::v8i8) - return SDValue(); - - // Create a v4i32 vector store operation, effectively <4 x v4i8>. - unsigned Opc = VT == MVT::v16i8 ? NVPTXISD::StoreV4 : NVPTXISD::StoreV2; - EVT NewVT = VT == MVT::v16i8 ? MVT::v4i32 : MVT::v2i32; - unsigned NumElts = NewVT.getVectorNumElements(); - - // Create a vector of the type required by the new store: v16i8 -> v4i32. - SDValue NewStoreValue = DCI.DAG.getBitcast(NewVT, ST->getValue()); - - // Operands for the store. - SmallVector Ops; - Ops.reserve(N->getNumOperands() + NumElts - 1); - // Chain value. - Ops.push_back(N->ops().front()); - - SDLoc DL(N); - SmallVector Elts(NumElts); - // Break v4i32 (or v2i32) into four (or two) elements. - for (unsigned I = 0; I < NumElts; ++I) - Elts[I] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, - NewStoreValue.getValueType().getVectorElementType(), - NewStoreValue, DAG.getIntPtrConstant(I, DL)); - Ops.append(Elts.begin(), Elts.end()); - // Any remaining operands. - Ops.append(N->op_begin() + 2, N->op_end()); - - SDValue NewStore = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), - Ops, NewVT, ST->getMemOperand()); - // Return the new chain. - return NewStore.getValue(0); -} - SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { CodeGenOptLevel OptLevel = getTargetMachine().getOptLevel(); @@ -5623,8 +5578,6 @@ SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N, return PerformSETCCCombine(N, DCI, STI.getSmVersion()); case ISD::LOAD: return PerformLOADCombine(N, DCI); - case ISD::STORE: - return PerformSTORECombine(N, DCI); case NVPTXISD::StoreRetval: case NVPTXISD::StoreRetvalV2: case NVPTXISD::StoreRetvalV4: diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 49d003db8ffc..21cd27d62711 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2877,8 +2877,9 @@ static bool isClusterableLdStOpcPair(unsigned FirstOpc, unsigned SecondOpc, } bool PPCInstrInfo::shouldClusterMemOps( - ArrayRef BaseOps1, - ArrayRef BaseOps2, unsigned ClusterSize, + ArrayRef BaseOps1, int64_t OpOffset1, + bool OffsetIsScalable1, ArrayRef BaseOps2, + int64_t OpOffset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const { assert(BaseOps1.size() == 1 && BaseOps2.size() == 1); diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index a8dc7d6d0e37..2f0b9498411a 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -532,7 +532,9 @@ public: /// Returns true if the two given memory operations should be scheduled /// adjacent. bool shouldClusterMemOps(ArrayRef BaseOps1, + int64_t Offset1, bool OffsetIsScalable1, ArrayRef BaseOps2, + int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override; diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp index 9e96fba069c4..50ed85acdec0 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp @@ -423,10 +423,6 @@ bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, return true; } -static const MCPhysReg ArgGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12, - RISCV::X13, RISCV::X14, RISCV::X15, - RISCV::X16, RISCV::X17}; - /// If there are varargs that were passed in a0-a7, the data in those registers /// must be copied to the varargs save area on the stack. void RISCVCallLowering::saveVarArgRegisters( @@ -435,61 +431,64 @@ void RISCVCallLowering::saveVarArgRegisters( MachineFunction &MF = MIRBuilder.getMF(); const RISCVSubtarget &Subtarget = MF.getSubtarget(); unsigned XLenInBytes = Subtarget.getXLen() / 8; - ArrayRef ArgRegs(ArgGPRs); + ArrayRef ArgRegs = RISCV::getArgGPRs(); + MachineRegisterInfo &MRI = MF.getRegInfo(); unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); + MachineFrameInfo &MFI = MF.getFrameInfo(); + RISCVMachineFunctionInfo *RVFI = MF.getInfo(); - // Offset of the first variable argument from stack pointer, and size of - // the vararg save area. For now, the varargs save area is either zero or - // large enough to hold a0-a7. - int VaArgOffset; + // Size of the vararg save area. For now, the varargs save area is either + // zero or large enough to hold a0-a7. int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); + int FI; // If all registers are allocated, then all varargs must be passed on the // stack and we don't need to save any argregs. if (VarArgsSaveSize == 0) { - VaArgOffset = Assigner.StackSize; + int VaArgOffset = Assigner.StackSize; + FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); } else { - VaArgOffset = -VarArgsSaveSize; + int VaArgOffset = -VarArgsSaveSize; + FI = MFI.CreateFixedObject(VarArgsSaveSize, VaArgOffset, true); + + // If saving an odd number of registers then create an extra stack slot to + // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures + // offsets to even-numbered registered remain 2*XLEN-aligned. + if (Idx % 2) { + MFI.CreateFixedObject(XLenInBytes, + VaArgOffset - static_cast(XLenInBytes), true); + VarArgsSaveSize += XLenInBytes; + } + + const LLT p0 = LLT::pointer(MF.getDataLayout().getAllocaAddrSpace(), + Subtarget.getXLen()); + const LLT sXLen = LLT::scalar(Subtarget.getXLen()); + + auto FIN = MIRBuilder.buildFrameIndex(p0, FI); + auto Offset = MIRBuilder.buildConstant( + MRI.createGenericVirtualRegister(sXLen), XLenInBytes); + + // Copy the integer registers that may have been used for passing varargs + // to the vararg save area. + const MVT XLenVT = Subtarget.getXLenVT(); + for (unsigned I = Idx; I < ArgRegs.size(); ++I) { + const Register VReg = MRI.createGenericVirtualRegister(sXLen); + Handler.assignValueToReg( + VReg, ArgRegs[I], + CCValAssign::getReg(I + MF.getFunction().getNumOperands(), XLenVT, + ArgRegs[I], XLenVT, CCValAssign::Full)); + auto MPO = + MachinePointerInfo::getFixedStack(MF, FI, (I - Idx) * XLenInBytes); + MIRBuilder.buildStore(VReg, FIN, MPO, inferAlignFromPtrInfo(MF, MPO)); + FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0), + FIN.getReg(0), Offset); + } } // Record the frame index of the first variable argument which is a value // necessary to G_VASTART. - MachineFrameInfo &MFI = MF.getFrameInfo(); - int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); - RISCVMachineFunctionInfo *RVFI = MF.getInfo(); RVFI->setVarArgsFrameIndex(FI); - - // If saving an odd number of registers then create an extra stack slot to - // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures - // offsets to even-numbered registered remain 2*XLEN-aligned. - if (Idx % 2) { - MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes, true); - VarArgsSaveSize += XLenInBytes; - } RVFI->setVarArgsSaveSize(VarArgsSaveSize); - - // Copy the integer registers that may have been used for passing varargs - // to the vararg save area. - const LLT p0 = LLT::pointer(MF.getDataLayout().getAllocaAddrSpace(), - Subtarget.getXLen()); - const LLT sXLen = LLT::scalar(Subtarget.getXLen()); - const MVT XLenVT = Subtarget.getXLenVT(); - MachineRegisterInfo &MRI = MF.getRegInfo(); - for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += XLenInBytes) { - const Register VReg = MRI.createGenericVirtualRegister(sXLen); - Handler.assignValueToReg( - VReg, ArgRegs[I], - CCValAssign::getReg(I + MF.getFunction().getNumOperands(), XLenVT, - ArgRegs[I], XLenVT, CCValAssign::Full)); - FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); - auto FIN = MIRBuilder.buildFrameIndex(p0, FI); - auto MPO = MachinePointerInfo::getFixedStack(MF, FI); - auto Store = - MIRBuilder.buildStore(VReg, FIN, MPO, inferAlignFromPtrInfo(MF, MPO)); - // This was taken from SelectionDAG, but we are not sure why it exists. - // It is being investigated in github.com/llvm/llvm-project/issues/73735. - Store->memoperands()[0]->setValue((Value *)nullptr); - } } bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index 140dd58fdc5b..61bdbfc47d94 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -104,6 +104,10 @@ private: // Custom renderers for tablegen void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; + void renderImmSubFromXLen(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const; + void renderImmSubFrom32(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const; void renderImmPlus1(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; void renderImm(MachineInstrBuilder &MIB, const MachineInstr &MI, @@ -721,6 +725,24 @@ void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB, MIB.addImm(-CstVal); } +void RISCVInstructionSelector::renderImmSubFromXLen(MachineInstrBuilder &MIB, + const MachineInstr &MI, + int OpIdx) const { + assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && + "Expected G_CONSTANT"); + uint64_t CstVal = MI.getOperand(1).getCImm()->getZExtValue(); + MIB.addImm(STI.getXLen() - CstVal); +} + +void RISCVInstructionSelector::renderImmSubFrom32(MachineInstrBuilder &MIB, + const MachineInstr &MI, + int OpIdx) const { + assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && + "Expected G_CONSTANT"); + uint64_t CstVal = MI.getOperand(1).getCImm()->getZExtValue(); + MIB.addImm(32 - CstVal); +} + void RISCVInstructionSelector::renderImmPlus1(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const { diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp index d68c44322fba..570b9802a2f5 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp @@ -23,6 +23,7 @@ using namespace llvm; using namespace LegalityPredicates; +using namespace LegalizeMutations; // Is this type supported by scalar FP arithmetic operations given the current // subtarget. @@ -99,7 +100,15 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower(); - getActionDefinitionsBuilder({G_ROTL, G_ROTR}).lower(); + auto &RotateActions = getActionDefinitionsBuilder({G_ROTL, G_ROTR}); + if (ST.hasStdExtZbb()) { + RotateActions.legalFor({{s32, sXLen}, {sXLen, sXLen}}); + // Widen s32 rotate amount to s64 so SDAG patterns will match. + if (ST.is64Bit()) + RotateActions.widenScalarIf(all(typeIs(0, s32), typeIs(1, s32)), + changeTo(1, sXLen)); + } + RotateActions.lower(); getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower(); diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td index b675446380e4..5f16ffb0a024 100644 --- a/llvm/lib/Target/RISCV/RISCVGISel.td +++ b/llvm/lib/Target/RISCV/RISCVGISel.td @@ -37,6 +37,11 @@ def ImmPlus1 : SDNodeXForm, GISDNodeXFormEquiv; +def GIImmSubFromXLen : GICustomOperandRenderer<"renderImmSubFromXLen">, + GISDNodeXFormEquiv; +def GIImmSubFrom32 : GICustomOperandRenderer<"renderImmSubFrom32">, + GISDNodeXFormEquiv; + def GIImmPlus1 : GICustomOperandRenderer<"renderImmPlus1">, GISDNodeXFormEquiv; @@ -56,9 +61,12 @@ def gi_trailing_zero : GICustomOperandRenderer<"renderTrailingZeros">, // parameter appears to be ignored so this pattern works for both, however we // should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead // here. -def ShiftMaskGI : +def GIShiftMaskXLen : GIComplexOperandMatcher, GIComplexPatternEquiv; +def GIShiftMask32 : + GIComplexOperandMatcher, + GIComplexPatternEquiv; def gi_sh1add_op : GIComplexOperandMatcher">, GIComplexPatternEquiv; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index cf1b11c14b6d..f2ec422b54a9 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -15948,7 +15948,7 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, break; case Intrinsic::riscv_vsetvli: case Intrinsic::riscv_vsetvlimax: - // Assume that VL output is >= 65536. + // Assume that VL output is <= 65536. // TODO: Take SEW and LMUL into account. if (BitWidth > 17) Known.Zero.setBitsFrom(17); @@ -16844,10 +16844,6 @@ void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, // register-size fields in the same situations they would be for fixed // arguments. -static const MCPhysReg ArgGPRs[] = { - RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, - RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17 -}; static const MCPhysReg ArgFPR16s[] = { RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H, RISCV::F14_H, RISCV::F15_H, RISCV::F16_H, RISCV::F17_H @@ -16872,6 +16868,14 @@ static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4}; static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}; +ArrayRef RISCV::getArgGPRs() { + static const MCPhysReg ArgGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12, + RISCV::X13, RISCV::X14, RISCV::X15, + RISCV::X16, RISCV::X17}; + + return ArrayRef(ArgGPRs); +} + // Pass a 2*XLEN argument that has been split into two XLEN values through // registers or the stack as necessary. static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, @@ -16879,6 +16883,7 @@ static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2) { unsigned XLenInBytes = XLen / 8; + ArrayRef ArgGPRs = RISCV::getArgGPRs(); if (Register Reg = State.AllocateReg(ArgGPRs)) { // At least one half can be passed via register. State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, @@ -16999,6 +17004,8 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, LocInfo = CCValAssign::BCvt; } + ArrayRef ArgGPRs = RISCV::getArgGPRs(); + // If this is a variadic argument, the RISC-V calling convention requires // that it is assigned an 'even' or 'aligned' register if it has 8-byte // alignment (RV32) or 16-byte alignment (RV64). An aligned register should @@ -17684,56 +17691,56 @@ SDValue RISCVTargetLowering::LowerFormalArguments( MF.getInfo()->setIsVectorCall(); if (IsVarArg) { - ArrayRef ArgRegs = ArrayRef(ArgGPRs); + ArrayRef ArgRegs = RISCV::getArgGPRs(); unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); const TargetRegisterClass *RC = &RISCV::GPRRegClass; MachineFrameInfo &MFI = MF.getFrameInfo(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); RISCVMachineFunctionInfo *RVFI = MF.getInfo(); - // Offset of the first variable argument from stack pointer, and size of - // the vararg save area. For now, the varargs save area is either zero or - // large enough to hold a0-a7. - int VaArgOffset; + // Size of the vararg save area. For now, the varargs save area is either + // zero or large enough to hold a0-a7. int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); + int FI; // If all registers are allocated, then all varargs must be passed on the // stack and we don't need to save any argregs. if (VarArgsSaveSize == 0) { - VaArgOffset = CCInfo.getStackSize(); + int VaArgOffset = CCInfo.getStackSize(); + FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); } else { - VaArgOffset = -VarArgsSaveSize; + int VaArgOffset = -VarArgsSaveSize; + FI = MFI.CreateFixedObject(VarArgsSaveSize, VaArgOffset, true); + + // If saving an odd number of registers then create an extra stack slot to + // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures + // offsets to even-numbered registered remain 2*XLEN-aligned. + if (Idx % 2) { + MFI.CreateFixedObject( + XLenInBytes, VaArgOffset - static_cast(XLenInBytes), true); + VarArgsSaveSize += XLenInBytes; + } + + SDValue FIN = DAG.getFrameIndex(FI, PtrVT); + + // Copy the integer registers that may have been used for passing varargs + // to the vararg save area. + for (unsigned I = Idx; I < ArgRegs.size(); ++I) { + const Register Reg = RegInfo.createVirtualRegister(RC); + RegInfo.addLiveIn(ArgRegs[I], Reg); + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT); + SDValue Store = DAG.getStore( + Chain, DL, ArgValue, FIN, + MachinePointerInfo::getFixedStack(MF, FI, (I - Idx) * XLenInBytes)); + OutChains.push_back(Store); + FIN = + DAG.getMemBasePlusOffset(FIN, TypeSize::getFixed(XLenInBytes), DL); + } } // Record the frame index of the first variable argument // which is a value necessary to VASTART. - int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); RVFI->setVarArgsFrameIndex(FI); - - // If saving an odd number of registers then create an extra stack slot to - // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures - // offsets to even-numbered registered remain 2*XLEN-aligned. - if (Idx % 2) { - MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes, true); - VarArgsSaveSize += XLenInBytes; - } - - // Copy the integer registers that may have been used for passing varargs - // to the vararg save area. - for (unsigned I = Idx; I < ArgRegs.size(); - ++I, VaArgOffset += XLenInBytes) { - const Register Reg = RegInfo.createVirtualRegister(RC); - RegInfo.addLiveIn(ArgRegs[I], Reg); - SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT); - FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); - SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); - SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, - MachinePointerInfo::getFixedStack(MF, FI)); - cast(Store.getNode()) - ->getMemOperand() - ->setValue((Value *)nullptr); - OutChains.push_back(Store); - } RVFI->setVarArgsSaveSize(VarArgsSaveSize); } diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 486efeb8339a..ae798cc47bf8 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -986,6 +986,9 @@ bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); + +ArrayRef getArgGPRs(); + } // end namespace RISCV namespace RISCVVIntrinsicsTable { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 2918e5654db4..1dcff7eb563e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2266,8 +2266,9 @@ static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, } bool RISCVInstrInfo::shouldClusterMemOps( - ArrayRef BaseOps1, - ArrayRef BaseOps2, unsigned ClusterSize, + ArrayRef BaseOps1, int64_t Offset1, + bool OffsetIsScalable1, ArrayRef BaseOps2, + int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const { // If the mem ops (to be clustered) do not have the same base ptr, then they // should not be clustered @@ -2304,7 +2305,8 @@ bool RISCVInstrInfo::getMemOperandWithOffsetWidth( // load/store instructions. if (LdSt.getNumExplicitOperands() != 3) return false; - if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) + if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) || + !LdSt.getOperand(2).isImm()) return false; if (!LdSt.hasOneMemOperand()) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 0954286a419b..7e1d3f311806 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -158,7 +158,9 @@ public: const TargetRegisterInfo *TRI) const override; bool shouldClusterMemOps(ArrayRef BaseOps1, + int64_t Offset1, bool OffsetIsScalable1, ArrayRef BaseOps2, + int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 235cfd3f604b..fa618b437ce7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -397,25 +397,25 @@ let Predicates = [HasVendorXSfvcp] in { } } -let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod" in { +let Predicates = [HasVendorXSfvqmaccdod] in { defm VQMACCU_2x8x2 : VPseudoSiFiveVQMACC; defm VQMACC_2x8x2 : VPseudoSiFiveVQMACC; defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACC; defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACC; } -let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq" in { +let Predicates = [HasVendorXSfvqmaccqoq] in { defm VQMACCU_4x8x4 : VPseudoSiFiveVQMACC; defm VQMACC_4x8x4 : VPseudoSiFiveVQMACC; defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACC; defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACC; } -let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq" in { +let Predicates = [HasVendorXSfvfwmaccqqq] in { defm VFWMACC_4x4x4 : VPseudoSiFiveVFWMACC; } -let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf" in { +let Predicates = [HasVendorXSfvfnrclipxfqf] in { defm VFNRCLIP_XU_F_QF : VPseudoSiFiveVFNRCLIP; defm VFNRCLIP_X_F_QF : VPseudoSiFiveVFNRCLIP; } diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 475ccc01df1f..a3c19115bd31 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -299,12 +299,20 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const { "Unexpected subreg numbering"); Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); - BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL); - uint32_t ShiftAmount = Log2_32(LMUL); - if (ShiftAmount != 0) - BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) - .addReg(VL) - .addImm(ShiftAmount); + // Optimize for constant VLEN. + const RISCVSubtarget &STI = MF.getSubtarget(); + if (STI.getRealMinVLen() == STI.getRealMaxVLen()) { + const int64_t VLENB = STI.getRealMinVLen() / 8; + int64_t Offset = VLENB * LMUL; + STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset); + } else { + BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL); + uint32_t ShiftAmount = Log2_32(LMUL); + if (ShiftAmount != 0) + BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) + .addReg(VL) + .addImm(ShiftAmount); + } Register SrcReg = II->getOperand(0).getReg(); Register Base = II->getOperand(1).getReg(); @@ -368,12 +376,20 @@ void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const { "Unexpected subreg numbering"); Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); - BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL); - uint32_t ShiftAmount = Log2_32(LMUL); - if (ShiftAmount != 0) - BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) - .addReg(VL) - .addImm(ShiftAmount); + // Optimize for constant VLEN. + const RISCVSubtarget &STI = MF.getSubtarget(); + if (STI.getRealMinVLen() == STI.getRealMaxVLen()) { + const int64_t VLENB = STI.getRealMinVLen() / 8; + int64_t Offset = VLENB * LMUL; + STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset); + } else { + BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL); + uint32_t ShiftAmount = Log2_32(LMUL); + if (ShiftAmount != 0) + BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) + .addReg(VL) + .addImm(ShiftAmount); + } Register DestReg = II->getOperand(0).getReg(); Register Base = II->getOperand(1).getReg(); diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index 53ef9d1baf7b..45783d482f3b 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -208,20 +208,26 @@ def SiFive7Model : SchedMachineModel { // Pipe A can handle memory, integer alu and vector operations. // Pipe B can handle integer alu, control flow, integer multiply and divide, // and floating point computation. -// Pipe V can handle the V extension. +// The V pipeline is modeled by the VCQ, VA, VL, and VS resources. let SchedModel = SiFive7Model in { let BufferSize = 0 in { def SiFive7PipeA : ProcResource<1>; def SiFive7PipeB : ProcResource<1>; -def SiFive7PipeV : ProcResource<1>; -} - -let BufferSize = 1 in { -def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division -def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt -def SiFive7VA : ProcResource<1> { let Super = SiFive7PipeV; } // Arithmetic sequencer -def SiFive7VL : ProcResource<1> { let Super = SiFive7PipeV; } // Load sequencer -def SiFive7VS : ProcResource<1> { let Super = SiFive7PipeV; } // Store sequencer +def SiFive7IDiv : ProcResource<1>; // Int Division +def SiFive7FDiv : ProcResource<1>; // FP Division/Sqrt +def SiFive7VA : ProcResource<1>; // Arithmetic sequencer +def SiFive7VL : ProcResource<1>; // Load sequencer +def SiFive7VS : ProcResource<1>; // Store sequencer +// The VCQ accepts instructions from the the A Pipe and holds them until the +// vector unit is ready to dequeue them. The unit dequeues up to one instruction +// per cycle, in order, as soon as the sequencer for that type of instruction is +// avaliable. This resource is meant to be used for 1 cycle by all vector +// instructions, to model that only one vector instruction may be dequed at a +// time. The actual dequeueing into the sequencer is modeled by the VA, VL, and +// VS sequencer resources below. Each of them will only accept a single +// instruction at a time and remain busy for the number of cycles associated +// with that instruction. +def SiFive7VCQ : ProcResource<1>; // Vector Command Queue } def SiFive7PipeAB : ProcResGroup<[SiFive7PipeA, SiFive7PipeB]>; @@ -433,21 +439,21 @@ def : WriteRes; foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 4, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVLDE", [SiFive7VL], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDFF", [SiFive7VL], mx, IsWorstCase>; + let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVLDE", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDFF", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; } - let Latency = 1, ReleaseAtCycles = [Cycles] in - defm "" : LMULWriteResMX<"WriteVSTE", [SiFive7VS], mx, IsWorstCase>; + let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in + defm "" : LMULWriteResMX<"WriteVSTE", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; } foreach mx = SchedMxList in { defvar Cycles = SiFive7GetMaskLoadStoreCycles.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 4, ReleaseAtCycles = [Cycles] in - defm "" : LMULWriteResMX<"WriteVLDM", [SiFive7VL], mx, IsWorstCase>; - let Latency = 1, ReleaseAtCycles = [Cycles] in - defm "" : LMULWriteResMX<"WriteVSTM", [SiFive7VS], mx, IsWorstCase>; + let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in + defm "" : LMULWriteResMX<"WriteVLDM", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in + defm "" : LMULWriteResMX<"WriteVSTM", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; } // Strided loads and stores operate at one element per cycle and should be @@ -466,17 +472,17 @@ foreach mx = SchedMxList in { defvar VLDSX0Cycles = SiFive7GetCyclesDefault.c; defvar Cycles = SiFive7GetCyclesOnePerElement.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred, [SiFive7VL], - 4, [VLDSX0Cycles], !add(3, Cycles), - [Cycles], mx, IsWorstCase>; - let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFive7VL], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFive7VL], mx, IsWorstCase>; + defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred, [SiFive7VCQ, SiFive7VL], + 4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles), + [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>; + let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; } - let Latency = 1, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVSTS8", [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFive7VS], mx, IsWorstCase>; + let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVSTS8", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; } } // TODO: The MxLists need to be filtered by EEW. We only need to support @@ -486,72 +492,72 @@ foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in { defvar VLDSX0Cycles = SiFive7GetCyclesDefault.c; defvar Cycles = SiFive7GetCyclesOnePerElement.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred, [SiFive7VL], - 4, [VLDSX0Cycles], !add(3, Cycles), - [Cycles], mx, IsWorstCase>; - let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFive7VL], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFive7VL], mx, IsWorstCase>; + defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred, [SiFive7VCQ, SiFive7VL], + 4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles), + [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>; + let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; } - let Latency = 1, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVSTS16", [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFive7VS], mx, IsWorstCase>; + let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVSTS16", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; } } foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in { defvar VLDSX0Cycles = SiFive7GetCyclesDefault.c; defvar Cycles = SiFive7GetCyclesOnePerElement.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred, [SiFive7VL], - 4, [VLDSX0Cycles], !add(3, Cycles), - [Cycles], mx, IsWorstCase>; - let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFive7VL], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFive7VL], mx, IsWorstCase>; + defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred, [SiFive7VCQ, SiFive7VL], + 4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles), + [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>; + let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; } - let Latency = 1, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVSTS32", [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFive7VS], mx, IsWorstCase>; + let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVSTS32", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; } } foreach mx = ["M1", "M2", "M4", "M8"] in { defvar VLDSX0Cycles = SiFive7GetCyclesDefault.c; defvar Cycles = SiFive7GetCyclesOnePerElement.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS64", VLDSX0Pred, [SiFive7VL], - 4, [VLDSX0Cycles], !add(3, Cycles), - [Cycles], mx, IsWorstCase>; - let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFive7VL], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFive7VL], mx, IsWorstCase>; + defm SiFive7 : LMULWriteResMXVariant<"WriteVLDS64", VLDSX0Pred, [SiFive7VCQ, SiFive7VL], + 4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles), + [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>; + let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; } - let Latency = 1, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVSTS64", [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFive7VS], mx, IsWorstCase>; + let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVSTS64", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; } } // VLD*R is LMUL aware -let Latency = 4, ReleaseAtCycles = [2] in - def : WriteRes; -let Latency = 4, ReleaseAtCycles = [4] in - def : WriteRes; -let Latency = 4, ReleaseAtCycles = [8] in - def : WriteRes; -let Latency = 4, ReleaseAtCycles = [16] in - def : WriteRes; +let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 2)] in + def : WriteRes; +let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 4)] in + def : WriteRes; +let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 8)] in + def : WriteRes; +let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 16)] in + def : WriteRes; // VST*R is LMUL aware -let Latency = 1, ReleaseAtCycles = [2] in - def : WriteRes; -let Latency = 1, ReleaseAtCycles = [4] in - def : WriteRes; -let Latency = 1, ReleaseAtCycles = [8] in - def : WriteRes; -let Latency = 1, ReleaseAtCycles = [16] in - def : WriteRes; +let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 2)] in + def : WriteRes; +let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 4)] in + def : WriteRes; +let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 8)] in + def : WriteRes; +let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 16)] in + def : WriteRes; // Segmented Loads and Stores // Unit-stride segmented loads and stores are effectively converted into strided @@ -564,22 +570,22 @@ foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesSegmentedSeg2.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; // Does not chain so set latency high - let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVLSEG2e" # eew, [SiFive7VL], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLSEGFF2e" # eew, [SiFive7VL], mx, IsWorstCase>; + let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVLSEG2e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLSEGFF2e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; } - let Latency = 1, ReleaseAtCycles = [Cycles] in - defm "" : LMULWriteResMX<"WriteVSSEG2e" # eew, [SiFive7VS], mx, IsWorstCase>; + let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in + defm "" : LMULWriteResMX<"WriteVSSEG2e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; foreach nf=3-8 in { defvar Cycles = SiFive7GetCyclesSegmented.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; // Does not chain so set latency high - let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>; + let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; } - let Latency = 1, ReleaseAtCycles = [Cycles] in - defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>; + let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in + defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; } } } @@ -589,15 +595,15 @@ foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesSegmented.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; // Does not chain so set latency high - let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>; + let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>; } - let Latency = 1, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>; + let Latency = 1, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>; } } } @@ -607,41 +613,41 @@ foreach mx = SchedMxList in { foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 4, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVIALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIALUX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIALUI", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICALUX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICALUI", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVShiftV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVShiftX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVShiftI", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMulV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMulX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMovV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMovX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMovI", [SiFive7VA], mx, IsWorstCase>; + let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVIALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVShiftV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVShiftX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVShiftI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMulX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMovV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMovX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMovI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } // Mask results can't chain. - let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVICmpV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICmpX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICmpI", [SiFive7VA], mx, IsWorstCase>; + let Latency = !add(Cycles, 3), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVICmpV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICmpX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICmpI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 4, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVExtV", [SiFive7VA], mx, IsWorstCase>; + let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVExtV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } foreach mx = SchedMxList in { @@ -649,9 +655,9 @@ foreach mx = SchedMxList in { defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor.c, !div(SiFive7GetCyclesOnePerElement.c, 4)); defvar IsWorstCase = SiFive7IsWorstCaseMXSEW.c; - let Latency = Cycles, ReleaseAtCycles = [Cycles] in { - defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFive7VA], mx, sew, IsWorstCase>; - defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFive7VA], mx, sew, IsWorstCase>; + let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; } } } @@ -660,24 +666,24 @@ foreach mx = SchedMxList in { foreach mx = SchedMxListW in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWMulV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWMulX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWMulX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } // Narrowing foreach mx = SchedMxListW in { defvar Cycles = SiFive7GetCyclesNarrowing.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } @@ -685,27 +691,27 @@ foreach mx = SchedMxListW in { foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVSALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSALUX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSALUI", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVAALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVAALUX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSMulV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSMulX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVSALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSMulX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } // Narrowing foreach mx = SchedMxListW in { defvar Cycles = SiFive7GetCyclesNarrowing.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVNClipV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVNClipX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVNClipI", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVNClipV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNClipX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNClipI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } @@ -713,30 +719,30 @@ foreach mx = SchedMxListW in { foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVFALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFALUF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMulV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMulF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMulAddV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMulAddF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFRecpV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVFALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFALUF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMulF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMulAddV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMulAddF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFRecpV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } - let Latency = 4, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVFSgnjV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFSgnjF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMinMaxV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMinMaxF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFClassV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFMovV", [SiFive7VA], mx, IsWorstCase>; + let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVFSgnjV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFSgnjF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMinMaxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMinMaxF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFClassV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMovV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } // Mask results can't chain. - let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFive7VA], mx, IsWorstCase>; + let Latency = !add(Cycles, 3), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } foreach mx = SchedMxListF in { @@ -744,10 +750,10 @@ foreach mx = SchedMxListF in { defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor.c, !div(SiFive7GetCyclesOnePerElement.c, 4)); defvar IsWorstCase = SiFive7IsWorstCaseMXSEW.c; - let Latency = Cycles, ReleaseAtCycles = [Cycles] in { - defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFive7VA], mx, sew, IsWorstCase>; - defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFive7VA], mx, sew, IsWorstCase>; - defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFive7VA], mx, sew, IsWorstCase>; + let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; } } } @@ -756,38 +762,38 @@ foreach mx = SchedMxListF in { foreach mx = SchedMxListW in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVFWCvtIToFV", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVFWCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } foreach mx = SchedMxListFW in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVFWALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWMulV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWMulAddV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWCvtFToFV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWMulAddF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWMulF", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFWALUF", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVFWALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFWMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFWMulAddV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFWCvtFToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFWMulAddF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFWMulF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFWALUF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } // Narrowing foreach mx = SchedMxListW in { defvar Cycles = SiFive7GetCyclesNarrowing.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } foreach mx = SchedMxListFW in { defvar Cycles = SiFive7GetCyclesNarrowing.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVFNCvtIToFV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFNCvtFToFV", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVFNCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFNCvtFToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } @@ -796,10 +802,10 @@ foreach mx = SchedMxList in { foreach sew = SchedSEWSet.val in { defvar Cycles = SiFive7GetReductionCycles.c; defvar IsWorstCase = SiFive7IsWorstCaseMXSEW.c; - let Latency = Cycles, ReleaseAtCycles = [Cycles] in { - defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA], + let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; - defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA], + defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; } } @@ -809,8 +815,8 @@ foreach mx = SchedMxListWRed in { foreach sew = SchedSEWSet.val in { defvar Cycles = SiFive7GetReductionCycles.c; defvar IsWorstCase = SiFive7IsWorstCaseMXSEW.c; - let Latency = Cycles, ReleaseAtCycles = [Cycles] in - defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFive7VA], + let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in + defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; } } @@ -819,15 +825,15 @@ foreach mx = SchedMxListF in { foreach sew = SchedSEWSet.val in { defvar RedCycles = SiFive7GetReductionCycles.c; defvar IsWorstCase = SiFive7IsWorstCaseMXSEW.c; - let Latency = RedCycles, ReleaseAtCycles = [RedCycles] in { - defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFive7VA], + let Latency = RedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, RedCycles)] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; - defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [SiFive7VA], + defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; } defvar OrdRedCycles = SiFive7GetOrderedReductionCycles.c; - let Latency = OrdRedCycles, ReleaseAtCycles = [OrdRedCycles] in - defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFive7VA], + let Latency = OrdRedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, OrdRedCycles)] in + defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; } } @@ -836,12 +842,12 @@ foreach mx = SchedMxListFWRed in { foreach sew = SchedSEWSet.val in { defvar RedCycles = SiFive7GetReductionCycles.c; defvar IsWorstCase = SiFive7IsWorstCaseMXSEW.c; - let Latency = RedCycles, ReleaseAtCycles = [RedCycles] in - defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFive7VA], + let Latency = RedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, RedCycles)] in + defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; defvar OrdRedCycles = SiFive7GetOrderedReductionCycles.c; - let Latency = OrdRedCycles, ReleaseAtCycles = [OrdRedCycles] in - defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFive7VA], + let Latency = OrdRedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, OrdRedCycles)] in + defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; } } @@ -850,35 +856,35 @@ foreach mx = SchedMxListFWRed in { foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesVMask.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 4, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVMALUV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVMPopV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFive7VA], mx, IsWorstCase>; + let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVMALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVMPopV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 4, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VA], mx, IsWorstCase>; + let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } // 16. Vector Permutation Instructions -let Latency = 4, ReleaseAtCycles = [1] in { - def : WriteRes; - def : WriteRes; - def : WriteRes; - def : WriteRes; +let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 1)] in { + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; } foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 8, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFive7VA], mx, IsWorstCase>; + let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } @@ -886,9 +892,9 @@ foreach mx = SchedMxList in { foreach sew = SchedSEWSet.val in { defvar Cycles = SiFive7GetCyclesOnePerElement.c; defvar IsWorstCase = SiFive7IsWorstCaseMXSEW.c; - let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in { - defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFive7VA], mx, sew, IsWorstCase>; - defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFive7VA], mx, sew, IsWorstCase>; + let Latency = !add(Cycles, 3), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>; } } } @@ -896,23 +902,23 @@ foreach mx = SchedMxList in { foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; - let Latency = 4, ReleaseAtCycles = [Cycles] in { - defm "" : LMULWriteResMX<"WriteVISlideX", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVISlideI", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFive7VA], mx, IsWorstCase>; + let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { + defm "" : LMULWriteResMX<"WriteVISlideX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVISlideI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } // VMov*V is LMUL Aware -let Latency = 4, ReleaseAtCycles = [2] in - def : WriteRes; -let Latency = 4, ReleaseAtCycles = [4] in - def : WriteRes; -let Latency = 4, ReleaseAtCycles = [8] in - def : WriteRes; -let Latency = 4, ReleaseAtCycles = [16] in - def : WriteRes; +let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 2)] in + def : WriteRes; +let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 4)] in + def : WriteRes; +let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 8)] in + def : WriteRes; +let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 16)] in + def : WriteRes; // Others def : WriteRes; diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td index b5ddb8197993..29f2ceec25fa 100644 --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -69,19 +69,23 @@ multiclass LMULSEWWriteResMXSEW resources, // is created similiarly if IsWorstCase is true. multiclass LMULWriteResMXVariant resources, - int predLat, list predCycles, - int noPredLat, list noPredCycles, + int predLat, list predAcquireCycles, + list predReleaseCycles, int noPredLat, + list noPredAcquireCycles, + list noPredReleaseCycles, string mx, bit IsWorstCase> { defvar nameMX = name # "_" # mx; // Define the different behaviors - def NAME # nameMX # "_Pred" : SchedWriteRes { + def nameMX # "_Pred" : SchedWriteRes{ let Latency = predLat; - let ReleaseAtCycles = predCycles; + let AcquireAtCycles = predAcquireCycles; + let ReleaseAtCycles = predReleaseCycles; } - def NAME # nameMX # "_NoPred" : SchedWriteRes { + def nameMX # "_NoPred" : SchedWriteRes { let Latency = noPredLat; - let ReleaseAtCycles = noPredCycles; + let AcquireAtCycles = noPredAcquireCycles; + let ReleaseAtCycles = noPredReleaseCycles; } // Tie behavior to predicate diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp index 610d9a033aee..000d68d4a79f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp @@ -506,8 +506,7 @@ bool SPIRVEmitIntrinsics::runOnFunction(Function &Func) { continue; Type *ElTy = SI->getValueOperand()->getType(); PointerType *PTy = cast(SI->getOperand(1)->getType()); - if (ElTy->isAggregateType() || ElTy->isVectorTy() || - !PTy->isOpaqueOrPointeeTypeMatches(ElTy)) + if (ElTy->isAggregateType() || ElTy->isVectorTy()) AggrStores.insert(&I); } diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index d0eb0255f7d9..873994c2e333 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -129,6 +129,8 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, setBooleanContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); + setMaxAtomicSizeInBitsSupported(128); + // Instructions are strings of 2-byte aligned 2-byte values. setMinFunctionAlignment(Align(2)); // For performance reasons we prefer 16-byte alignment. @@ -870,9 +872,11 @@ bool SystemZTargetLowering::hasInlineStackProbe(const MachineFunction &MF) const TargetLowering::AtomicExpansionKind SystemZTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const { + // TODO: expand them all here instead of in backend. return (RMW->isFloatingPointOperation() || RMW->getOperation() == AtomicRMWInst::UIncWrap || - RMW->getOperation() == AtomicRMWInst::UDecWrap) + RMW->getOperation() == AtomicRMWInst::UDecWrap || + RMW->getType()->isIntegerTy(128)) ? AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None; } diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index f7096b708b39..ff496d29b391 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -43,9 +43,6 @@ bool TargetMachine::isLargeGlobalObject(const GlobalObject *GO) const { if (getTargetTriple().getArch() != Triple::x86_64) return false; - if (getCodeModel() != CodeModel::Medium && getCodeModel() != CodeModel::Large) - return false; - if (isa(GO)) return getCodeModel() == CodeModel::Large; @@ -54,22 +51,39 @@ bool TargetMachine::isLargeGlobalObject(const GlobalObject *GO) const { if (GV->isThreadLocal()) return false; - // Allowing large metadata sections in the presence of an explicit section is - // useful, even if GCC does not allow them. However, we should not mark - // certain well-known prefixes as large, because it would make the whole - // output section large and cause the linker to move it, which is almost - // always undesired. + // We should properly mark well-known section name prefixes as small/large, + // because otherwise the output section may have the wrong section flags and + // the linker will lay it out in an unexpected way. StringRef Name = GV->getSection(); - auto IsPrefix = [&](StringRef Prefix) { - StringRef S = Name; - return S.consume_front(Prefix) && (S.empty() || S[0] == '.'); - }; - if (IsPrefix(".bss") || IsPrefix(".data") || IsPrefix(".rodata")) - return false; + if (!Name.empty()) { + auto IsPrefix = [&](StringRef Prefix) { + StringRef S = Name; + return S.consume_front(Prefix) && (S.empty() || S[0] == '.'); + }; + if (IsPrefix(".bss") || IsPrefix(".data") || IsPrefix(".rodata")) + return false; + if (IsPrefix(".lbss") || IsPrefix(".ldata") || IsPrefix(".lrodata")) + return true; + } - const DataLayout &DL = GV->getParent()->getDataLayout(); - uint64_t Size = DL.getTypeSizeInBits(GV->getValueType()) / 8; - return Size == 0 || Size > LargeDataThreshold; + // For x86-64, we treat an explicit GlobalVariable small code model to mean + // that the global should be placed in a small section, and ditto for large. + // Well-known section names above take precedence for correctness. + if (auto CM = GV->getCodeModel()) { + if (*CM == CodeModel::Small) + return false; + if (*CM == CodeModel::Large) + return true; + } + + if (getCodeModel() == CodeModel::Medium || + getCodeModel() == CodeModel::Large) { + const DataLayout &DL = GV->getParent()->getDataLayout(); + uint64_t Size = DL.getTypeSizeInBits(GV->getValueType()) / 8; + return Size == 0 || Size > LargeDataThreshold; + } + + return false; } bool TargetMachine::isPositionIndependent() const { diff --git a/llvm/lib/Target/X86/X86CallingConv.td b/llvm/lib/Target/X86/X86CallingConv.td index 27e4fe0cb7a0..16014d6a2f60 100644 --- a/llvm/lib/Target/X86/X86CallingConv.td +++ b/llvm/lib/Target/X86/X86CallingConv.td @@ -1151,6 +1151,9 @@ def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP) def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, R8, R9, R10)>; +def CSR_Win64_RT_MostRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, + (sequence "XMM%u", 6, 15))>; + // All registers - except r11 and return registers. def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, (sequence "XMM%u", 0, 15))>; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6167be7bdf84..4fca5afb46dd 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -83,13 +83,6 @@ static cl::opt MulConstantOptimization( "SHIFT, LEA, etc."), cl::Hidden); -static cl::opt ExperimentalUnorderedISEL( - "x86-experimental-unordered-atomic-isel", cl::init(false), - cl::desc("Use LoadSDNode and StoreSDNode instead of " - "AtomicSDNode for unordered atomic loads and " - "stores respectively."), - cl::Hidden); - X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI) : TargetLowering(TM), Subtarget(STI) { @@ -30598,18 +30591,6 @@ X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const { return Loaded; } -bool X86TargetLowering::lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const { - if (!SI.isUnordered()) - return false; - return ExperimentalUnorderedISEL; -} -bool X86TargetLowering::lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const { - if (!LI.isUnordered()) - return false; - return ExperimentalUnorderedISEL; -} - - /// Emit a locked operation on a stack location which does not change any /// memory location, but does involve a lock prefix. Location is chosen to be /// a) very likely accessed only by a single thread to minimize cache traffic, @@ -50491,11 +50472,14 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG, bool NoImplicitFloatOps = F.hasFnAttribute(Attribute::NoImplicitFloat); bool F64IsLegal = !Subtarget.useSoftFloat() && !NoImplicitFloatOps && Subtarget.hasSSE2(); - if ((VT == MVT::i64 && F64IsLegal && !Subtarget.is64Bit()) && - isa(St->getValue()) && + + if (!F64IsLegal || Subtarget.is64Bit()) + return SDValue(); + + if (VT == MVT::i64 && isa(St->getValue()) && cast(St->getValue())->isSimple() && St->getChain().hasOneUse() && St->isSimple()) { - LoadSDNode *Ld = cast(St->getValue().getNode()); + auto *Ld = cast(St->getValue()); if (!ISD::isNormalLoad(Ld)) return SDValue(); @@ -50522,7 +50506,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG, // to get past legalization. The execution dependencies fixup pass will // choose the optimal machine instruction for the store if this really is // an integer or v2f32 rather than an f64. - if (VT == MVT::i64 && F64IsLegal && !Subtarget.is64Bit() && + if (VT == MVT::i64 && St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) { SDValue OldExtract = St->getOperand(1); SDValue ExtOp0 = OldExtract.getOperand(0); diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 3b1b2603fd8f..9bd1622cb0d3 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1753,9 +1753,6 @@ namespace llvm { LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override; - bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const override; - bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const override; - bool needsCmpXchgNb(Type *MemType) const; void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, diff --git a/llvm/lib/Target/X86/X86Instr3DNow.td b/llvm/lib/Target/X86/X86Instr3DNow.td index d5651b677695..3be03ab0f433 100644 --- a/llvm/lib/Target/X86/X86Instr3DNow.td +++ b/llvm/lib/Target/X86/X86Instr3DNow.td @@ -79,16 +79,6 @@ let SchedRW = [WriteEMMS], def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>, TB; -// PREFETCHWT1 is supported we want to use it for everything but T0. -def PrefetchWLevel : PatFrag<(ops), (i32 timm), [{ - return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1(); -}]>; - -// Use PREFETCHWT1 for NTA, T2, T1. -def PrefetchWT1Level : TImmLeaf; - let SchedRW = [WriteLoad] in { let Predicates = [Has3DNow, NoSSEPrefetch] in def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr), diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 77b359e84fbd..5eb893a82fcc 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -12,194 +12,6 @@ // //===----------------------------------------------------------------------===// -// Group template arguments that can be derived from the vector type (EltNum x -// EltVT). These are things like the register class for the writemask, etc. -// The idea is to pass one of these as the template argument rather than the -// individual arguments. -// The template is also used for scalar types, in this case numelts is 1. -class X86VectorVTInfo { - RegisterClass RC = rc; - ValueType EltVT = eltvt; - int NumElts = numelts; - - // Corresponding mask register class. - RegisterClass KRC = !cast("VK" # NumElts); - - // Corresponding mask register pair class. - RegisterOperand KRPC = !if (!gt(NumElts, 16), ?, - !cast("VK" # NumElts # "Pair")); - - // Corresponding write-mask register class. - RegisterClass KRCWM = !cast("VK" # NumElts # "WM"); - - // The mask VT. - ValueType KVT = !cast("v" # NumElts # "i1"); - - // Suffix used in the instruction mnemonic. - string Suffix = suffix; - - // VTName is a string name for vector VT. For vector types it will be - // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32 - // It is a little bit complex for scalar types, where NumElts = 1. - // In this case we build v4f32 or v2f64 - string VTName = "v" # !if (!eq (NumElts, 1), - !if (!eq (EltVT.Size, 16), 8, - !if (!eq (EltVT.Size, 32), 4, - !if (!eq (EltVT.Size, 64), 2, NumElts))), NumElts) # EltVT; - - // The vector VT. - ValueType VT = !cast(VTName); - - string EltTypeName = !cast(EltVT); - // Size of the element type in bits, e.g. 32 for v16i32. - string EltSizeName = !subst("i", "", !subst("f", "", !subst("b", "", EltTypeName))); - int EltSize = EltVT.Size; - - // "i" for integer types and "f" for floating-point types - string TypeVariantName = !subst("b", "", !subst(EltSizeName, "", EltTypeName)); - - // Size of RC in bits, e.g. 512 for VR512. - int Size = VT.Size; - - // The corresponding memory operand, e.g. i512mem for VR512. - X86MemOperand MemOp = !cast(TypeVariantName # Size # "mem"); - X86MemOperand ScalarMemOp = !cast(!subst("b", "", EltTypeName) # "mem"); - // FP scalar memory operand for intrinsics - ssmem/sdmem. - Operand IntScalarMemOp = !if (!eq (EltTypeName, "f16"), !cast("shmem"), - !if (!eq (EltTypeName, "bf16"), !cast("shmem"), - !if (!eq (EltTypeName, "f32"), !cast("ssmem"), - !if (!eq (EltTypeName, "f64"), !cast("sdmem"), ?)))); - - // Load patterns - PatFrag LdFrag = !cast("load" # VTName); - - PatFrag AlignedLdFrag = !cast("alignedload" # VTName); - - PatFrag ScalarLdFrag = !cast("load" # !subst("b", "", EltTypeName)); - PatFrag BroadcastLdFrag = !cast("X86VBroadcastld" # EltSizeName); - - PatFrags ScalarIntMemFrags = !if (!eq (EltTypeName, "f16"), !cast("sse_load_f16"), - !if (!eq (EltTypeName, "bf16"), !cast("sse_load_f16"), - !if (!eq (EltTypeName, "f32"), !cast("sse_load_f32"), - !if (!eq (EltTypeName, "f64"), !cast("sse_load_f64"), ?)))); - - // The string to specify embedded broadcast in assembly. - string BroadcastStr = "{1to" # NumElts # "}"; - - // 8-bit compressed displacement tuple/subvector format. This is only - // defined for NumElts <= 8. - CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0), - !cast("CD8VT" # NumElts), ?); - - SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm, - !if (!eq (Size, 256), sub_ymm, ?)); - - Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle, - !if (!eq (EltTypeName, "f64"), SSEPackedDouble, - !if (!eq (EltTypeName, "f16"), SSEPackedSingle, // FIXME? - !if (!eq (EltTypeName, "bf16"), SSEPackedSingle, // FIXME? - SSEPackedInt)))); - - RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, - !if (!eq (EltTypeName, "f16"), FR16X, - !if (!eq (EltTypeName, "bf16"), FR16X, - FR64X))); - - dag ImmAllZerosV = (VT immAllZerosV); - - string ZSuffix = !if (!eq (Size, 128), "Z128", - !if (!eq (Size, 256), "Z256", "Z")); -} - -def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">; -def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">; -def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">; -def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">; -def v32f16_info : X86VectorVTInfo<32, f16, VR512, "ph">; -def v32bf16_info: X86VectorVTInfo<32, bf16, VR512, "pbf">; -def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">; -def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">; - -// "x" in v32i8x_info means RC = VR256X -def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">; -def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">; -def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">; -def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">; -def v16f16x_info : X86VectorVTInfo<16, f16, VR256X, "ph">; -def v16bf16x_info: X86VectorVTInfo<16, bf16, VR256X, "pbf">; -def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">; -def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">; - -def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">; -def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">; -def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">; -def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">; -def v8f16x_info : X86VectorVTInfo<8, f16, VR128X, "ph">; -def v8bf16x_info : X86VectorVTInfo<8, bf16, VR128X, "pbf">; -def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">; -def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">; - -// We map scalar types to the smallest (128-bit) vector type -// with the appropriate element type. This allows to use the same masking logic. -def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">; -def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">; -def f16x_info : X86VectorVTInfo<1, f16, VR128X, "sh">; -def bf16x_info : X86VectorVTInfo<1, bf16, VR128X, "sbf">; -def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">; -def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">; - -class AVX512VLVectorVTInfo { - X86VectorVTInfo info512 = i512; - X86VectorVTInfo info256 = i256; - X86VectorVTInfo info128 = i128; -} - -def avx512vl_i8_info : AVX512VLVectorVTInfo; -def avx512vl_i16_info : AVX512VLVectorVTInfo; -def avx512vl_i32_info : AVX512VLVectorVTInfo; -def avx512vl_i64_info : AVX512VLVectorVTInfo; -def avx512vl_f16_info : AVX512VLVectorVTInfo; -def avx512vl_bf16_info : AVX512VLVectorVTInfo; -def avx512vl_f32_info : AVX512VLVectorVTInfo; -def avx512vl_f64_info : AVX512VLVectorVTInfo; - -class X86KVectorVTInfo { - RegisterClass KRC = _krc; - RegisterClass KRCWM = _krcwm; - ValueType KVT = _vt; -} - -def v1i1_info : X86KVectorVTInfo; -def v2i1_info : X86KVectorVTInfo; -def v4i1_info : X86KVectorVTInfo; -def v8i1_info : X86KVectorVTInfo; -def v16i1_info : X86KVectorVTInfo; -def v32i1_info : X86KVectorVTInfo; -def v64i1_info : X86KVectorVTInfo; - -// Used for matching masked operations. Ensures the operation part only has a -// single use. -def vselect_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2), - (vselect node:$mask, node:$src1, node:$src2), [{ - return isProfitableToFormMaskedOp(N); -}]>; - -def X86selects_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2), - (X86selects node:$mask, node:$src1, node:$src2), [{ - return isProfitableToFormMaskedOp(N); -}]>; - // This multiclass generates the masking variants from the non-masking // variant. It only provides the assembly pieces for the masking variants. // It assumes custom ISel patterns for masking which can be provided as @@ -2157,15 +1969,6 @@ multiclass avx512_cmp_scalarhasOneUse(); -}]>; -def X86cmpmsSAE_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), - (X86cmpmsSAE node:$src1, node:$src2, node:$cc), [{ - return N->hasOneUse(); -}]>; - let Predicates = [HasAVX512] in { let ExeDomain = SSEPackedSingle in defm VCMPSSZ : avx512_cmp_scalar opc, string OpcodeStr, } } -// This fragment treats X86cmpm as commutable to help match loads in both -// operands for PCMPEQ. -def X86setcc_commute : SDNode<"ISD::SETCC", SDTSetCC, [SDNPCommutative]>; -def X86pcmpgtm : PatFrag<(ops node:$src1, node:$src2), - (setcc node:$src1, node:$src2, SETGT)>; - // AddedComplexity is needed because the explicit SETEQ/SETGT CondCode doesn't // increase the pattern complexity the way an immediate would. let AddedComplexity = 2 in { @@ -2304,20 +2101,6 @@ defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", T8PD, REX_W, EVEX_CD8<64, CD8VF>; } -def X86pcmpm_imm : SDNodeXForm(N->getOperand(2))->get(); - uint8_t SSECC = X86::getVPCMPImmForCond(CC); - return getI8Imm(SSECC, SDLoc(N)); -}]>; - -// Swapped operand version of the above. -def X86pcmpm_imm_commute : SDNodeXForm(N->getOperand(2))->get(); - uint8_t SSECC = X86::getVPCMPImmForCond(CC); - SSECC = X86::getSwappedVPCMPImm(SSECC); - return getI8Imm(SSECC, SDLoc(N)); -}]>; - multiclass avx512_icmp_cc opc, string Suffix, PatFrag Frag, PatFrag Frag_su, X86FoldableSchedWrite sched, @@ -2451,30 +2234,6 @@ multiclass avx512_icmp_cc_rmb_vl opc, string Suffix, PatFrag Frag, } } -def X86pcmpm : PatFrag<(ops node:$src1, node:$src2, node:$cc), - (setcc node:$src1, node:$src2, node:$cc), [{ - ISD::CondCode CC = cast(N->getOperand(2))->get(); - return !ISD::isUnsignedIntSetCC(CC); -}], X86pcmpm_imm>; - -def X86pcmpm_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), - (setcc node:$src1, node:$src2, node:$cc), [{ - ISD::CondCode CC = cast(N->getOperand(2))->get(); - return N->hasOneUse() && !ISD::isUnsignedIntSetCC(CC); -}], X86pcmpm_imm>; - -def X86pcmpum : PatFrag<(ops node:$src1, node:$src2, node:$cc), - (setcc node:$src1, node:$src2, node:$cc), [{ - ISD::CondCode CC = cast(N->getOperand(2))->get(); - return ISD::isUnsignedIntSetCC(CC); -}], X86pcmpm_imm>; - -def X86pcmpum_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), - (setcc node:$src1, node:$src2, node:$cc), [{ - ISD::CondCode CC = cast(N->getOperand(2))->get(); - return N->hasOneUse() && ISD::isUnsignedIntSetCC(CC); -}], X86pcmpm_imm>; - // FIXME: Is there a better scheduler class for VPCMP/VPCMPU? defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86pcmpm, X86pcmpm_su, SchedWriteVecALU, avx512vl_i8_info, HasBWI>, @@ -2504,16 +2263,6 @@ defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86pcmpum, X86pcmpum_su, SchedWriteVecALU, avx512vl_i64_info, HasAVX512>, REX_W, EVEX_CD8<64, CD8VF>; -def X86cmpm_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), - (X86cmpm node:$src1, node:$src2, node:$cc), [{ - return N->hasOneUse(); -}]>; - -def X86cmpm_imm_commute : SDNodeXFormgetZExtValue() & 0x1f); - return getI8Imm(Imm, SDLoc(N)); -}]>; - multiclass avx512_vcmp_common { let Uses = [MXCSR], mayRaiseFPException = 1 in { @@ -2679,16 +2428,6 @@ let Predicates = [HasFP16] in { // ---------------------------------------------------------------- // FPClass -def X86Vfpclasss_su : PatFrag<(ops node:$src1, node:$src2), - (X86Vfpclasss node:$src1, node:$src2), [{ - return N->hasOneUse(); -}]>; - -def X86Vfpclass_su : PatFrag<(ops node:$src1, node:$src2), - (X86Vfpclass node:$src1, node:$src2), [{ - return N->hasOneUse(); -}]>; - //handle fpclass instruction mask = op(reg_scalar,imm) // op(mem_scalar,imm) multiclass avx512_scalar_fpclass opc, string OpcodeStr, @@ -3082,10 +2821,6 @@ multiclass avx512_mask_binop_all opc, string OpcodeStr, sched, HasBWI, IsCommutable>, VEX_4V, VEX_L, REX_W, PS; } -// These nodes use 'vnot' instead of 'not' to support vectors. -def vandn : PatFrag<(ops node:$i0, node:$i1), (and (vnot node:$i0), node:$i1)>; -def vxnor : PatFrag<(ops node:$i0, node:$i1), (vnot (xor node:$i0, node:$i1))>; - // TODO - do we need a X86SchedWriteWidths::KMASK type? defm KAND : avx512_mask_binop_all<0x41, "kand", and, SchedWriteVecLogic.XMM, 1>; defm KOR : avx512_mask_binop_all<0x45, "kor", or, SchedWriteVecLogic.XMM, 1>; @@ -9880,19 +9615,6 @@ defm : avx512_masked_scalar; -def select_truncs : PatFrag<(ops node:$src, node:$src0, node:$mask), - (vselect_mask node:$mask, - (X86vtruncs node:$src), node:$src0)>; -def select_truncus : PatFrag<(ops node:$src, node:$src0, node:$mask), - (vselect_mask node:$mask, - (X86vtruncus node:$src), node:$src0)>; - multiclass avx512_trunc_common opc, string OpcodeStr, SDNode OpNode, SDPatternOperator MaskNode, X86FoldableSchedWrite sched, X86VectorVTInfo SrcInfo, @@ -12676,11 +12398,6 @@ defm VPOPCNTW : avx512_unary_rm_vl<0x54, "vpopcntw", ctpop, SchedWriteVecALU, defm : avx512_unary_lowering<"VPOPCNTB", ctpop, avx512vl_i8_info, HasBITALG>; defm : avx512_unary_lowering<"VPOPCNTW", ctpop, avx512vl_i16_info, HasBITALG>; -def X86Vpshufbitqmb_su : PatFrag<(ops node:$src1, node:$src2), - (X86Vpshufbitqmb node:$src1, node:$src2), [{ - return N->hasOneUse(); -}]>; - multiclass VPSHUFBITQMB_rm { defm rr : AVX512_maskable_cmp<0x8F, MRMSrcReg, VTI, (outs VTI.KRC:$dst), (ins VTI.RC:$src1, VTI.RC:$src2), diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 56cbc13eaaec..8c355e84a065 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -48,16 +48,6 @@ def PLEA64r : PseudoI<(outs GR64:$dst), (ins anymem:$src), []>; // Fixed-Register Multiplication and Division Instructions. // -// SchedModel info for instruction that loads one value and gets the second -// (and possibly third) value from a register. -// This is used for instructions that put the memory operands before other -// uses. -class SchedLoadReg : Sched<[Sched.Folded, - // Memory operand. - ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, - // Register reads (implicit or explicit). - Sched.ReadAfterFold, Sched.ReadAfterFold]>; - // BinOpRR - Binary instructions with inputs "reg, reg". class BinOpRR opcode, string mnemonic, X86TypeInfo typeinfo, dag outlist, X86FoldableSchedWrite sched, list pattern> @@ -506,17 +496,6 @@ class IMulOpRMI opcode, string mnemonic, X86TypeInfo info, let ImmT = info.ImmEncoding; } -def X86add_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), - (X86add_flag node:$lhs, node:$rhs), [{ - return hasNoCarryFlagUses(SDValue(N, 1)); -}]>; - -def X86sub_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), - (X86sub_flag node:$lhs, node:$rhs), [{ - // Only use DEC if the result is used. - return !SDValue(N, 0).use_empty() && hasNoCarryFlagUses(SDValue(N, 1)); -}]>; - let Defs = [EFLAGS] in { let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { // Short forms only valid in 32-bit mode. Selected during MCInst lowering. @@ -1221,9 +1200,6 @@ def : Pat<(store (X86adc_flag i64relocImmSExt32_su:$src, (load addr:$dst), EFLAG // generate a result. From an encoding perspective, they are very different: // they don't have all the usual imm8 and REV forms, and are encoded into a // different space. -def X86testpat : PatFrag<(ops node:$lhs, node:$rhs), - (X86cmp (and_su node:$lhs, node:$rhs), 0)>; - let isCompare = 1 in { let Defs = [EFLAGS] in { let isCommutable = 1 in { diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index 9e99dbd6fe85..457833f8cc33 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -786,16 +786,6 @@ defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; -def X86lock_add_nocf : PatFrag<(ops node:$lhs, node:$rhs), - (X86lock_add node:$lhs, node:$rhs), [{ - return hasNoCarryFlagUses(SDValue(N, 0)); -}]>; - -def X86lock_sub_nocf : PatFrag<(ops node:$lhs, node:$rhs), - (X86lock_sub node:$lhs, node:$rhs), [{ - return hasNoCarryFlagUses(SDValue(N, 0)); -}]>; - let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, SchedRW = [WriteALURMW] in { let Predicates = [UseIncDec] in { @@ -1304,31 +1294,6 @@ def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 tglobaladdr:$dst)), // %r11. This happens when calling a vararg function with 6 arguments. // // Match an X86tcret that uses less than 7 volatile registers. -def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), - (X86tcret node:$ptr, node:$off), [{ - // X86tcret args: (*chain, ptr, imm, regs..., glue) - unsigned NumRegs = 0; - for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) - if (isa(N->getOperand(i)) && ++NumRegs > 6) - return false; - return true; -}]>; - -def X86tcret_1reg : PatFrag<(ops node:$ptr, node:$off), - (X86tcret node:$ptr, node:$off), [{ - // X86tcret args: (*chain, ptr, imm, regs..., glue) - unsigned NumRegs = 1; - const SDValue& BasePtr = cast(N->getOperand(1))->getBasePtr(); - if (isa(BasePtr)) - NumRegs = 3; - else if (BasePtr->getNumOperands() && isa(BasePtr->getOperand(0))) - NumRegs = 3; - for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) - if (isa(N->getOperand(i)) && ( NumRegs-- == 0)) - return false; - return true; -}]>; - def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), (TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>, Requires<[Not64BitMode, NotUseIndirectThunkCalls]>; @@ -1449,32 +1414,8 @@ def : Pat<(i64 (anyext GR16:$src)), def : Pat<(i64 (anyext GR32:$src)), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; -// If this is an anyext of the remainder of an 8-bit sdivrem, use a MOVSX -// instead of a MOVZX. The sdivrem lowering will emit emit a MOVSX to move -// %ah to the lower byte of a register. By using a MOVSX here we allow a -// post-isel peephole to merge the two MOVSX instructions into one. -def anyext_sdiv : PatFrag<(ops node:$lhs), (anyext node:$lhs),[{ - return (N->getOperand(0).getOpcode() == ISD::SDIVREM && - N->getOperand(0).getResNo() == 1); -}]>; def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>; -// Any instruction that defines a 32-bit result leaves the high half of the -// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may -// be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying -// anything about the upper 32 bits, they're probably just qualifying a -// CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit -// operation will zero-extend up to 64 bits. -def def32 : PatLeaf<(i32 GR32:$src), [{ - return N->getOpcode() != ISD::TRUNCATE && - N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && - N->getOpcode() != ISD::CopyFromReg && - N->getOpcode() != ISD::AssertSext && - N->getOpcode() != ISD::AssertZext && - N->getOpcode() != ISD::AssertAlign && - N->getOpcode() != ISD::FREEZE; -}]>; - // In the case of a 32-bit def that is known to implicitly zero-extend, // we can use a SUBREG_TO_REG. def : Pat<(i64 (zext def32:$src)), @@ -1492,17 +1433,6 @@ def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)), // generator to make the generated code easier to read. To do this, we select // into "disjoint bits" pseudo ops. -// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. -def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ - if (ConstantSDNode *CN = dyn_cast(N->getOperand(1))) - return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); - - KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0); - KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0); - return (~Known0.Zero & ~Known1.Zero) == 0; -}]>; - - // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. // Try this before the selecting to OR. let SchedRW = [WriteALU] in { @@ -1820,23 +1750,6 @@ def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; -def shiftMask8 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ - return isUnneededShiftMask(N, 3); -}]>; - -def shiftMask16 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ - return isUnneededShiftMask(N, 4); -}]>; - -def shiftMask32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ - return isUnneededShiftMask(N, 5); -}]>; - -def shiftMask64 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ - return isUnneededShiftMask(N, 6); -}]>; - - // Shift amount is implicitly masked. multiclass MaskedShiftAmountPats { // (shift x (and y, 31)) ==> (shift x, y) diff --git a/llvm/lib/Target/X86/X86InstrFPStack.td b/llvm/lib/Target/X86/X86InstrFPStack.td index 66a2d27abf86..09655d939121 100644 --- a/llvm/lib/Target/X86/X86InstrFPStack.td +++ b/llvm/lib/Target/X86/X86InstrFPStack.td @@ -12,127 +12,6 @@ // //===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// FPStack specific DAG Nodes. -//===----------------------------------------------------------------------===// - -def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, - SDTCisPtrTy<1>]>; -def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, - SDTCisPtrTy<1>]>; -def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; -def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; - -def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; -def SDTX86CwdLoad : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; -def SDTX86FPEnv : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; - -def X86fp80_add : SDNode<"X86ISD::FP80_ADD", SDTFPBinOp, [SDNPCommutative]>; -def X86strict_fp80_add : SDNode<"X86ISD::STRICT_FP80_ADD", SDTFPBinOp, - [SDNPHasChain,SDNPCommutative]>; -def any_X86fp80_add : PatFrags<(ops node:$lhs, node:$rhs), - [(X86strict_fp80_add node:$lhs, node:$rhs), - (X86fp80_add node:$lhs, node:$rhs)]>; - -def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, - [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; -def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, - [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; -def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, - [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; -def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, - [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; -def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, - [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; -def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, - [SDNPHasChain, SDNPMayStore, SDNPSideEffect, - SDNPMemOperand]>; -def X86fp_cwd_set16 : SDNode<"X86ISD::FLDCW16m", SDTX86CwdLoad, - [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, - SDNPMemOperand]>; -def X86fpenv_get : SDNode<"X86ISD::FNSTENVm", SDTX86FPEnv, - [SDNPHasChain, SDNPMayStore, SDNPSideEffect, - SDNPMemOperand]>; -def X86fpenv_set : SDNode<"X86ISD::FLDENVm", SDTX86FPEnv, - [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, - SDNPMemOperand]>; - -def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), - (X86fst node:$val, node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::f32; -}]>; -def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), - (X86fst node:$val, node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::f64; -}]>; -def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), - (X86fst node:$val, node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::f80; -}]>; - -def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::f32; -}]>; -def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::f64; -}]>; -def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::f80; -}]>; - -def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::i16; -}]>; -def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::i32; -}]>; -def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::i64; -}]>; - -def X86fist32 : PatFrag<(ops node:$val, node:$ptr), - (X86fist node:$val, node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::i32; -}]>; - -def X86fist64 : PatFrag<(ops node:$val, node:$ptr), - (X86fist node:$val, node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::i64; -}]>; - -def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), - (X86fp_to_mem node:$val, node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::i16; -}]>; -def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), - (X86fp_to_mem node:$val, node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::i32; -}]>; -def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), - (X86fp_to_mem node:$val, node:$ptr), [{ - return cast(N)->getMemoryVT() == MVT::i64; -}]>; - -//===----------------------------------------------------------------------===// -// FPStack pattern fragments -//===----------------------------------------------------------------------===// - -def fpimm0 : FPImmLeaf; - -def fpimmneg0 : FPImmLeaf; - -def fpimm1 : FPImmLeaf; - -def fpimmneg1 : FPImmLeaf; - // Some 'special' instructions - expanded after instruction selection. // Clobbers EFLAGS due to OR instruction used internally. // FIXME: Can we model this in SelectionDAG? @@ -645,7 +524,7 @@ def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; } // Floating point constant loads. -let SchedRW = [WriteZero], Uses = [FPCW] in { +let SchedRW = [WriteZero], Uses = [FPCW], isReMaterializable = 1 in { def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, [(set RFP32:$dst, fpimm0)]>; def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td index 68a9bb7053a1..df05a5788a50 100644 --- a/llvm/lib/Target/X86/X86InstrFormats.td +++ b/llvm/lib/Target/X86/X86InstrFormats.td @@ -192,91 +192,6 @@ def AdSize16 : AddressSize<1>; // Encodes a 16-bit address. def AdSize32 : AddressSize<2>; // Encodes a 32-bit address. def AdSize64 : AddressSize<3>; // Encodes a 64-bit address. -// Prefix byte classes which are used to indicate to the ad-hoc machine code -// emitter that various prefix bytes are required. -class OpSize16 { OperandSize OpSize = OpSize16; } -class OpSize32 { OperandSize OpSize = OpSize32; } -class AdSize16 { AddressSize AdSize = AdSize16; } -class AdSize32 { AddressSize AdSize = AdSize32; } -class AdSize64 { AddressSize AdSize = AdSize64; } -class REX_W { bit hasREX_W = 1; } -class LOCK { bit hasLockPrefix = 1; } -class REP { bit hasREPPrefix = 1; } -class TB { Map OpMap = TB; } -class T8 { Map OpMap = T8; } -class TA { Map OpMap = TA; } -class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } -class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; } -class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; } -class ThreeDNow { Map OpMap = ThreeDNow; } -class T_MAP4 { Map OpMap = T_MAP4; } -class T_MAP4PS : T_MAP4 { Prefix OpPrefix = PS; } // none -class T_MAP4PD : T_MAP4 { Prefix OpPrefix = PD; } // 0x66 -class T_MAP4XS : T_MAP4 { Prefix OpPrefix = XS; } // 0xF3 -class T_MAP4XD : T_MAP4 { Prefix OpPrefix = XD; } // 0xF2 -class T_MAP5 { Map OpMap = T_MAP5; } -class T_MAP5PS : T_MAP5 { Prefix OpPrefix = PS; } // none -class T_MAP5PD : T_MAP5 { Prefix OpPrefix = PD; } // 0x66 -class T_MAP5XS : T_MAP5 { Prefix OpPrefix = XS; } // 0xF3 -class T_MAP5XD : T_MAP5 { Prefix OpPrefix = XD; } // 0xF2 -class T_MAP6 { Map OpMap = T_MAP6; } -class T_MAP6PS : T_MAP6 { Prefix OpPrefix = PS; } -class T_MAP6PD : T_MAP6 { Prefix OpPrefix = PD; } -class T_MAP6XS : T_MAP6 { Prefix OpPrefix = XS; } -class T_MAP6XD : T_MAP6 { Prefix OpPrefix = XD; } -class T_MAP7 { Map OpMap = T_MAP7; } -class T_MAP7XS : T_MAP7 { Prefix OpPrefix = XS; } // 0xF3 -class T_MAP7XD : T_MAP7 { Prefix OpPrefix = XD; } // 0xF2 -class OBXS { Prefix OpPrefix = XS; } -class PS : TB { Prefix OpPrefix = PS; } -class PD : TB { Prefix OpPrefix = PD; } -class XD : TB { Prefix OpPrefix = XD; } -class XS : TB { Prefix OpPrefix = XS; } -class T8PS : T8 { Prefix OpPrefix = PS; } -class T8PD : T8 { Prefix OpPrefix = PD; } -class T8XD : T8 { Prefix OpPrefix = XD; } -class T8XS : T8 { Prefix OpPrefix = XS; } -class TAPS : TA { Prefix OpPrefix = PS; } -class TAPD : TA { Prefix OpPrefix = PD; } -class TAXD : TA { Prefix OpPrefix = XD; } -class TAXS : TA { Prefix OpPrefix = XS; } -class VEX { Encoding OpEnc = EncVEX; } -class WIG { bit IgnoresW = 1; } -// Special version of REX_W that can be changed to VEX.W==0 for EVEX2VEX. -class VEX_W1X { bit hasREX_W = 1; bit EVEX_W1_VEX_W0 = 1; } -class VEX_4V : VEX { bit hasVEX_4V = 1; } -class VEX_L { bit hasVEX_L = 1; } -class VEX_LIG { bit ignoresVEX_L = 1; } -class EVEX { Encoding OpEnc = EncEVEX; } -class EVEX_4V : EVEX { bit hasVEX_4V = 1; } -class EVEX_K { bit hasEVEX_K = 1; } -class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } -class EVEX_B { bit hasEVEX_B = 1; } -class EVEX_RC { bit hasEVEX_RC = 1; } -class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } -class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; } -class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; } -class NOTRACK { bit hasNoTrackPrefix = 1; } -class SIMD_EXC { list Uses = [MXCSR]; bit mayRaiseFPException = 1; } - -// Specify AVX512 8-bit compressed displacement encoding based on the vector -// element size in bits (8, 16, 32, 64) and the CDisp8 form. -class EVEX_CD8 { - int CD8_EltSize = !srl(esize, 3); - bits<3> CD8_Form = form.Value; -} - -class XOP { Encoding OpEnc = EncXOP; } -class XOP_4V : XOP { bit hasVEX_4V = 1; } - -// Provide a specific instruction to be used by the EVEX2VEX conversion. -class EVEX2VEXOverride { - string EVEX2VEXOverride = VEXInstrName; -} - -// Prevent EVEX->VEX conversion from considering this instruction. -class NotEVEX2VEXConvertible { bit notEVEX2VEXConvertible = 1; } - // Force the instruction to use REX2/VEX/EVEX encoding. class ExplicitOpPrefix val> { bits<2> Value = val; @@ -285,9 +200,6 @@ def NoExplicitOpPrefix : ExplicitOpPrefix<0>; def ExplicitREX2 : ExplicitOpPrefix<1>; def ExplicitVEX : ExplicitOpPrefix<2>; def ExplicitEVEX : ExplicitOpPrefix<3>; -class ExplicitREX2Prefix { ExplicitOpPrefix explicitOpPrefix = ExplicitREX2; } -class ExplicitVEXPrefix { ExplicitOpPrefix explicitOpPrefix = ExplicitVEX; } -class ExplicitEVEXPrefix { ExplicitOpPrefix explicitOpPrefix = ExplicitEVEX; } class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, string AsmStr, Domain d = GenericDomain> @@ -397,621 +309,3 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, let TSFlags{49} = hasNoTrackPrefix; let TSFlags{51-50} = explicitOpPrefixBits; } - -class PseudoI pattern> - : X86Inst<0, Pseudo, NoImm, oops, iops, ""> { - let Pattern = pattern; -} - -class I o, Format f, dag outs, dag ins, string asm, - list pattern, Domain d = GenericDomain> - : X86Inst { - let Pattern = pattern; -} -class Ii8 o, Format f, dag outs, dag ins, string asm, - list pattern, Domain d = GenericDomain> - : X86Inst { - let Pattern = pattern; -} -class Ii8Reg o, Format f, dag outs, dag ins, string asm, - list pattern, Domain d = GenericDomain> - : X86Inst { - let Pattern = pattern; -} -class Ii8PCRel o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { - let Pattern = pattern; -} -class Ii16 o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { - let Pattern = pattern; -} -class Ii32 o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { - let Pattern = pattern; -} -class Ii32S o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { - let Pattern = pattern; -} - -class Ii64 o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { - let Pattern = pattern; -} - -class Ii16PCRel o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { - let Pattern = pattern; -} - -class Ii32PCRel o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { - let Pattern = pattern; -} - -// FPStack Instruction Templates: -// FPI - Floating Point Instruction template. -class FPI o, Format F, dag outs, dag ins, string asm> - : I { - let Defs = [FPSW]; - let Predicates = [HasX87]; -} - -// FpI_ - Floating Point Pseudo Instruction template. -class FpI_ pattern> - : PseudoI { - let FPForm = fp; - let Defs = [FPSW]; - let Predicates = [HasX87]; -} - -// Templates for instructions that use a 16- or 32-bit segmented address as -// their only operand: lcall (FAR CALL) and ljmp (FAR JMP) -// -// Iseg16 - 16-bit segment selector, 16-bit offset -// Iseg32 - 16-bit segment selector, 32-bit offset - -class Iseg16 o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { - let Pattern = pattern; -} - -class Iseg32 o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { - let Pattern = pattern; -} - -// SI - SSE 1 & 2 scalar instructions -class SI o, Format F, dag outs, dag ins, string asm, - list pattern, Domain d = GenericDomain> - : I { - let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], - !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], - !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], - !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], - !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], - [UseSSE1]))))); - - // AVX instructions have a 'v' prefix in the mnemonic - let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), - !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), - asm)); -} - -// SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512 -class SI_Int o, Format F, dag outs, dag ins, string asm, - list pattern, Domain d = GenericDomain> - : I { - let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], - !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], - !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], - !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], - !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], - [UseSSE1]))))); - - // AVX instructions have a 'v' prefix in the mnemonic - let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), - !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), - asm)); -} -// SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512 -class SIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8 { - let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], - !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], - !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], - [UseSSE2]))); - - // AVX instructions have a 'v' prefix in the mnemonic - let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), - !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), - asm)); -} - -// PI - SSE 1 & 2 packed instructions -class PI o, Format F, dag outs, dag ins, string asm, list pattern, - Domain d> - : I { - let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], - !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], - !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], - [UseSSE1]))); - - // AVX instructions have a 'v' prefix in the mnemonic - let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), - !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), - asm)); -} - -// MMXPI - SSE 1 & 2 packed instructions with MMX operands -class MMXPI o, Format F, dag outs, dag ins, string asm, list pattern, - Domain d> - : I { - let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasMMX, HasSSE2], - [HasMMX, HasSSE1]); -} - -// PIi8 - SSE 1 & 2 packed instructions with immediate -class PIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, Domain d> - : Ii8 { - let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], - !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], - !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], - [UseSSE1]))); - - // AVX instructions have a 'v' prefix in the mnemonic - let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), - !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), - asm)); -} - -// SSE1 Instruction Templates: -// -// SSI - SSE1 instructions with XS prefix. -// PSI - SSE1 instructions with PS prefix. -// PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. -// VSSI - SSE1 instructions with XS prefix in AVX form. -// VPSI - SSE1 instructions with PS prefix in AVX form, packed single. - -class SSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XS, Requires<[UseSSE1]>; -class SSIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XS, Requires<[UseSSE1]>; -class PSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PS, - Requires<[UseSSE1]>; -class PSIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, PS, - Requires<[UseSSE1]>; -class VSSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XS, - Requires<[HasAVX]>; -class VPSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PS, - Requires<[HasAVX]>; - -// SSE2 Instruction Templates: -// -// SDI - SSE2 instructions with XD prefix. -// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. -// S2SI - SSE2 instructions with XS prefix. -// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. -// PDI - SSE2 instructions with PD prefix, packed double domain. -// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. -// VSDI - SSE2 scalar instructions with XD prefix in AVX form. -// VPDI - SSE2 vector instructions with PD prefix in AVX form, -// packed double domain. -// VS2I - SSE2 scalar instructions with PD prefix in AVX form. -// S2I - SSE2 scalar instructions with PD prefix. -// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as -// MMX operands. -// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as -// MMX operands. - -class SDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XD, Requires<[UseSSE2]>; -class SDIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XD, Requires<[UseSSE2]>; -class S2SI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XS, Requires<[UseSSE2]>; -class S2SIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XS, Requires<[UseSSE2]>; -class PDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PD, - Requires<[UseSSE2]>; -class PDIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, PD, - Requires<[UseSSE2]>; -class VSDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XD, - Requires<[UseAVX]>; -class VS2SI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XS, - Requires<[HasAVX]>; -class VPDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, - PD, Requires<[HasAVX]>; -class VS2I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PD, - Requires<[UseAVX]>; -class S2I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PD, Requires<[UseSSE2]>; -class MMXSDIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XD, Requires<[HasMMX, HasSSE2]>; -class MMXS2SIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XS, Requires<[HasMMX, HasSSE2]>; - -// SSE3 Instruction Templates: -// -// S3I - SSE3 instructions with PD prefixes. -// S3SI - SSE3 instructions with XS prefix. -// S3DI - SSE3 instructions with XD prefix. - -class S3SI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XS, - Requires<[UseSSE3]>; -class S3DI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XD, - Requires<[UseSSE3]>; -class S3I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PD, - Requires<[UseSSE3]>; - - -// SSSE3 Instruction Templates: -// -// SS38I - SSSE3 instructions with T8 prefix. -// SS3AI - SSSE3 instructions with TA prefix. -// MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. -// MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. -// -// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version -// uses the MMX registers. The 64-bit versions are grouped with the MMX -// classes. They need to be enabled even if AVX is enabled. - -class SS38I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8PD, - Requires<[UseSSSE3]>; -class SS3AI o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TAPD, - Requires<[UseSSSE3]>; -class MMXSS38I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8PS, - Requires<[HasMMX, HasSSSE3]>; -class MMXSS3AI o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TAPS, - Requires<[HasMMX, HasSSSE3]>; - -// SSE4.1 Instruction Templates: -// -// SS48I - SSE 4.1 instructions with T8 prefix. -// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. -// -class SS48I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8PD, - Requires<[UseSSE41]>; -class SS4AIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TAPD, - Requires<[UseSSE41]>; - -// SSE4.2 Instruction Templates: -// -// SS428I - SSE 4.2 instructions with T8 prefix. -class SS428I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8PD, - Requires<[UseSSE42]>; - -// SS42AI = SSE 4.2 instructions with TA prefix -class SS42AI o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TAPD, - Requires<[UseSSE42]>; - -// CRC32I - SSE 4.2 CRC32 instructions. -// NOTE: 'HasCRC32' is used as CRC32 instructions are GPR only and not directly -// controlled by the SSE42 flag. -class CRC32I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8XD, Requires<[HasCRC32]>; - -// AVX Instruction Templates: -// Instructions introduced in AVX (no SSE equivalent forms) -// -// AVX8I - AVX instructions with T8PD prefix. -// AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. -class AVX8I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8PD, - Requires<[HasAVX]>; -class AVXAIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TAPD, - Requires<[HasAVX]>; - -// AVX2 Instruction Templates: -// Instructions introduced in AVX2 (no SSE equivalent forms) -// -// AVX28I - AVX2 instructions with T8PD prefix. -// AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. -class AVX28I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8PD, - Requires<[HasAVX2]>; -class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TAPD, - Requires<[HasAVX2]>; - - -// AVX-512 Instruction Templates: -// Instructions introduced in AVX-512 (no SSE equivalent forms) -// -// AVX5128I - AVX-512 instructions with T8PD prefix. -// AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. -// AVX512PDI - AVX-512 instructions with PD, double packed. -// AVX512PSI - AVX-512 instructions with PS, single packed. -// AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. -// AVX512XSI - AVX-512 instructions with XS prefix, generic domain. -// AVX512BI - AVX-512 instructions with PD, int packed domain. -// AVX512SI - AVX-512 scalar instructions with PD prefix. - -class AVX5128I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8PD, - Requires<[HasAVX512]>; -class AVX5128IBase : T8PD { - Domain ExeDomain = SSEPackedInt; -} -class AVX512XS8I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8XS, - Requires<[HasAVX512]>; -class AVX512XSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XS, - Requires<[HasAVX512]>; -class AVX512XDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XD, - Requires<[HasAVX512]>; -class AVX512BI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PD, - Requires<[HasAVX512]>; -class AVX512BIBase : PD { - Domain ExeDomain = SSEPackedInt; -} -class AVX512BIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, PD, - Requires<[HasAVX512]>; -class AVX512BIi8Base : PD { - Domain ExeDomain = SSEPackedInt; - ImmType ImmT = Imm8; -} -class AVX512XSIi8Base : XS { - Domain ExeDomain = SSEPackedInt; - ImmType ImmT = Imm8; -} -class AVX512XDIi8Base : XD { - Domain ExeDomain = SSEPackedInt; - ImmType ImmT = Imm8; -} -class AVX512PSIi8Base : PS { - Domain ExeDomain = SSEPackedSingle; - ImmType ImmT = Imm8; -} -class AVX512PDIi8Base : PD { - Domain ExeDomain = SSEPackedDouble; - ImmType ImmT = Imm8; -} -class AVX512AIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TAPD, - Requires<[HasAVX512]>; -class AVX512AIi8Base : TAPD { - ImmType ImmT = Imm8; -} -class AVX512Ii8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, - Requires<[HasAVX512]>; -class AVX512PDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PD, - Requires<[HasAVX512]>; -class AVX512PSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PS, - Requires<[HasAVX512]>; -class AVX512PIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, Domain d> - : Ii8, Requires<[HasAVX512]>; -class AVX512PI o, Format F, dag outs, dag ins, string asm, - list pattern, Domain d> - : I, Requires<[HasAVX512]>; -class AVX512FMA3S o, Format F, dag outs, dag ins, string asm, - listpattern> - : I, T8PD, - EVEX_4V, Requires<[HasAVX512]>; - -class AVX512 o, Format F, dag outs, dag ins, string asm, - listpattern> - : I, Requires<[HasAVX512]>; - -// AES Instruction Templates: -// -// AES8I -// These use the same encoding as the SSE4.2 T8 and TA encodings. -class AES8I o, Format F, dag outs, dag ins, string asm, - listpattern> - : I, T8PD, - Requires<[NoAVX, HasAES]>; - -class AESAI o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TAPD, - Requires<[NoAVX, HasAES]>; - -// PCLMUL Instruction Templates -class PCLMULIi8 o, Format F, dag outs, dag ins, string asm, - listpattern> - : Ii8, TAPD; - -// FMA3 Instruction Templates -class FMA3 o, Format F, dag outs, dag ins, string asm, - listpattern> - : I, T8PD, - VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>; -class FMA3S o, Format F, dag outs, dag ins, string asm, - listpattern> - : I, T8PD, - VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>; -class FMA3S_Int o, Format F, dag outs, dag ins, string asm, - listpattern> - : I, T8PD, - VEX_4V, FMASC, Requires<[HasFMA, NoAVX512]>; - -// FMA4 Instruction Templates -class FMA4 o, Format F, dag outs, dag ins, string asm, - listpattern> - : Ii8Reg, TAPD, - VEX_4V, FMASC, Requires<[HasFMA4, NoVLX]>; -class FMA4S o, Format F, dag outs, dag ins, string asm, - listpattern> - : Ii8Reg, TAPD, - VEX_4V, FMASC, Requires<[HasFMA4, NoAVX512]>; -class FMA4S_Int o, Format F, dag outs, dag ins, string asm, - listpattern> - : Ii8Reg, TAPD, - VEX_4V, FMASC, Requires<[HasFMA4]>; - -// XOP 2, 3 and 4 Operand Instruction Template -class IXOP o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, - XOP9, Requires<[HasXOP]>; - -// XOP 2 and 3 Operand Instruction Templates with imm byte -class IXOPi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, - XOP8, Requires<[HasXOP]>; -// XOP 4 Operand Instruction Templates with imm byte -class IXOPi8Reg o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8Reg, - XOP8, Requires<[HasXOP]>; - -// XOP 5 operand instruction (VEX encoding!) -class IXOP5 o, Format F, dag outs, dag ins, string asm, - listpattern> - : Ii8Reg, TAPD, - VEX_4V, Requires<[HasXOP]>; - -// X86-64 Instruction templates... -// - -class RI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, REX_W; -class RIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, REX_W; -class RIi16 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii16, REX_W; -class RIi32 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii32, REX_W; -class RIi32S o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii32S, REX_W; -class RIi64 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii64, REX_W; - -class RS2I o, Format F, dag outs, dag ins, string asm, - list pattern> - : S2I, REX_W; -class VRS2I o, Format F, dag outs, dag ins, string asm, - list pattern> - : VS2I, REX_W; - -// MMX Instruction templates -// - -// MMXI - MMX instructions with TB prefix. -// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. -// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. -// MMX2I - MMX / SSE2 instructions with PD prefix. -// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. -// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. -// MMXID - MMX instructions with XD prefix. -// MMXIS - MMX instructions with XS prefix. -class MMXI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PS, Requires<[HasMMX]>; -class MMXI32 o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PS, Requires<[HasMMX,Not64BitMode]>; -class MMXI64 o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PS, Requires<[HasMMX,In64BitMode]>; -class MMXRI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PS, REX_W, - Requires<[HasMMX,In64BitMode]>; -class MMX2I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, PD, Requires<[HasMMX]>; -class MMXIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, PS, Requires<[HasMMX]>; -class MMXID o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XD, Requires<[HasMMX]>; -class MMXIS o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XS, Requires<[HasMMX]>; diff --git a/llvm/lib/Target/X86/X86InstrFragments.td b/llvm/lib/Target/X86/X86InstrFragments.td new file mode 100644 index 000000000000..adf527d72f5b --- /dev/null +++ b/llvm/lib/Target/X86/X86InstrFragments.td @@ -0,0 +1,841 @@ +//===----------X86InstrFragments - X86 Pattern fragments. --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// X86-specific DAG node. +def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisSameAs<1, 2>]>; +def SDTX86FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisFP<1>, + SDTCisSameAs<1, 2>]>; + +def SDTX86Cmov : SDTypeProfile<1, 4, + [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; + +// Unary and binary operator instructions that set EFLAGS as a side-effect. +def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, + [SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; + +// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS +def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, + [SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, + SDTCisVT<1, i32>, + SDTCisVT<4, i32>]>; +// RES1, RES2, FLAGS = op LHS, RHS +def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, + [SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; +def SDTX86BrCond : SDTypeProfile<0, 3, + [SDTCisVT<0, OtherVT>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86SetCC : SDTypeProfile<1, 2, + [SDTCisVT<0, i8>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; +def SDTX86SetCC_C : SDTypeProfile<1, 2, + [SDTCisInt<0>, + SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; + +def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; + +def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; + +def SDTX86rdpkru : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDTX86wrpkru : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, + SDTCisVT<2, i32>]>; + +def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, + SDTCisVT<2, i8>]>; +def SDTX86cas8pair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; +def SDTX86cas16pair : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i64>]>; + +def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>, + SDTCisInt<2>]>; + +def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>]>; + +def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; + +def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; +def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; + +def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, + SDTCisPtrTy<1>]>; + +def SDT_X86VAARG : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, + SDTCisPtrTy<1>, + SDTCisVT<2, i32>, + SDTCisVT<3, i8>, + SDTCisVT<4, i32>]>; + +def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; + +def SDTX86Void : SDTypeProfile<0, 0, []>; + +def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; + +def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86DYN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; + +def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; + +def SDT_X86PROBED_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; + +def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + +def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; + +def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, + SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>; + +def SDT_X86AESENCDECKL : SDTypeProfile<2, 2, [SDTCisVT<0, v2i64>, + SDTCisVT<1, i32>, + SDTCisVT<2, v2i64>, + SDTCisPtrTy<3>]>; + +def SDTX86Cmpccxadd : SDTypeProfile<1, 4, [SDTCisSameAs<0, 2>, + SDTCisPtrTy<1>, SDTCisSameAs<2, 3>, + SDTCisVT<4, i8>]>; + +def X86MFence : SDNode<"X86ISD::MFENCE", SDTNone, [SDNPHasChain]>; + + +def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; +def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; +def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>; +def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>; + +def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; +def X86fcmp : SDNode<"X86ISD::FCMP", SDTX86FCmp>; +def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86FCmp, [SDNPHasChain]>; +def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86FCmp, [SDNPHasChain]>; +def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; + +def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; +def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, + [SDNPHasChain]>; +def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; +def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; + +def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, + [SDNPHasChain, SDNPSideEffect]>; + +def X86rdpkru : SDNode<"X86ISD::RDPKRU", SDTX86rdpkru, + [SDNPHasChain, SDNPSideEffect]>; +def X86wrpkru : SDNode<"X86ISD::WRPKRU", SDTX86wrpkru, + [SDNPHasChain, SDNPSideEffect]>; + +def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8pair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; +def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86cas16pair, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad, SDNPMemOperand]>; + +def X86retglue : SDNode<"X86ISD::RET_GLUE", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; +def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, + [SDNPHasChain, SDNPOptInGlue]>; + +def X86vastart_save_xmm_regs : + SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", + SDT_X86VASTART_SAVE_XMM_REGS, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPVariadic]>; +def X86vaarg64 : + SDNode<"X86ISD::VAARG_64", SDT_X86VAARG, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, + SDNPMemOperand]>; +def X86vaargx32 : + SDNode<"X86ISD::VAARG_X32", SDT_X86VAARG, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, + SDNPMemOperand]>; +def X86callseq_start : + SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, + [SDNPHasChain, SDNPOutGlue]>; +def X86callseq_end : + SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; + +def X86call_rvmarker : SDNode<"X86ISD::CALL_RVMARKER", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; + + +def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, + SDNPVariadic]>; +def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, + [SDNPHasChain]>; + +def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; +def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, + [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, + SDNPMayLoad]>; + +def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; +def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; + +def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", + SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, + SDTCisInt<1>]>>; + +def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, + [SDNPHasChain]>; + +def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", + SDTypeProfile<1, 1, [SDTCisInt<0>, + SDTCisPtrTy<1>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", + SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, + [SDNPHasChain, SDNPSideEffect]>; +def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", + SDTypeProfile<0, 0, []>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + +def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; +def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, + [SDNPCommutative]>; +def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; +def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; + +def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, + [SDNPCommutative]>; +def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, + [SDNPCommutative]>; + +def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; +def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, + SDNPMemOperand]>; + +def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; +def X86bextri : SDNode<"X86ISD::BEXTRI", SDTIntBinOp>; + +def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntBinOp>; + +def X86pdep : SDNode<"X86ISD::PDEP", SDTIntBinOp>; +def X86pext : SDNode<"X86ISD::PEXT", SDTIntBinOp>; + +def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; + +def X86DynAlloca : SDNode<"X86ISD::DYN_ALLOCA", SDT_X86DYN_ALLOCA, + [SDNPHasChain, SDNPOutGlue]>; + +def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, + [SDNPHasChain]>; + +def X86ProbedAlloca : SDNode<"X86ISD::PROBED_ALLOCA", SDT_X86PROBED_ALLOCA, + [SDNPHasChain]>; + +def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def X86lwpins : SDNode<"X86ISD::LWPINS", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; + +def X86umwait : SDNode<"X86ISD::UMWAIT", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86tpause : SDNode<"X86ISD::TPAUSE", + SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86enqcmd : SDNode<"X86ISD::ENQCMD", SDT_X86ENQCMD, + [SDNPHasChain, SDNPSideEffect]>; +def X86enqcmds : SDNode<"X86ISD::ENQCMDS", SDT_X86ENQCMD, + [SDNPHasChain, SDNPSideEffect]>; +def X86testui : SDNode<"X86ISD::TESTUI", + SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, + [SDNPHasChain, SDNPSideEffect]>; + +def X86aesenc128kl : SDNode<"X86ISD::AESENC128KL", SDT_X86AESENCDECKL, + [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, + SDNPMemOperand]>; +def X86aesdec128kl : SDNode<"X86ISD::AESDEC128KL", SDT_X86AESENCDECKL, + [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, + SDNPMemOperand]>; +def X86aesenc256kl : SDNode<"X86ISD::AESENC256KL", SDT_X86AESENCDECKL, + [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, + SDNPMemOperand]>; +def X86aesdec256kl : SDNode<"X86ISD::AESDEC256KL", SDT_X86AESENCDECKL, + [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, + SDNPMemOperand]>; + +def X86cmpccxadd : SDNode<"X86ISD::CMPCCXADD", SDTX86Cmpccxadd, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, + SDNPMemOperand]>; + +// Define X86-specific addressing mode. +def addr : ComplexPattern; +def lea32addr : ComplexPattern; +// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. +def lea64_32addr : ComplexPattern; + +def tls32addr : ComplexPattern; + +def tls32baseaddr : ComplexPattern; + +def lea64addr : ComplexPattern; + +def tls64addr : ComplexPattern; + +def tls64baseaddr : ComplexPattern; + +def vectoraddr : ComplexPattern; + +// A relocatable immediate is an operand that can be relocated by the linker to +// an immediate, such as a regular symbol in non-PIC code. +def relocImm : ComplexPattern; + +// X86 specific condition code. These correspond to CondCode in +// X86InstrInfo.h. They must be kept in synch. +def X86_COND_O : PatLeaf<(i8 0)>; +def X86_COND_NO : PatLeaf<(i8 1)>; +def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C +def X86_COND_AE : PatLeaf<(i8 3)>; // alt. COND_NC +def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z +def X86_COND_NE : PatLeaf<(i8 5)>; // alt. COND_NZ +def X86_COND_BE : PatLeaf<(i8 6)>; // alt. COND_NA +def X86_COND_A : PatLeaf<(i8 7)>; // alt. COND_NBE +def X86_COND_S : PatLeaf<(i8 8)>; +def X86_COND_NS : PatLeaf<(i8 9)>; +def X86_COND_P : PatLeaf<(i8 10)>; // alt. COND_PE +def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO +def X86_COND_L : PatLeaf<(i8 12)>; // alt. COND_NGE +def X86_COND_GE : PatLeaf<(i8 13)>; // alt. COND_NL +def X86_COND_LE : PatLeaf<(i8 14)>; // alt. COND_NG +def X86_COND_G : PatLeaf<(i8 15)>; // alt. COND_NLE + +def i16immSExt8 : ImmLeaf(Imm); }]>; +def i32immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt8 : ImmLeaf(Imm); }]>; +def i64immSExt32 : ImmLeaf(Imm); }]>; +def i64timmSExt32 : TImmLeaf(Imm); }]>; + +def i16relocImmSExt8 : PatLeaf<(i16 relocImm), [{ + return isSExtAbsoluteSymbolRef(8, N); +}]>; +def i32relocImmSExt8 : PatLeaf<(i32 relocImm), [{ + return isSExtAbsoluteSymbolRef(8, N); +}]>; +def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ + return isSExtAbsoluteSymbolRef(8, N); +}]>; +def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ + return isSExtAbsoluteSymbolRef(32, N); +}]>; + +// If we have multiple users of an immediate, it's much smaller to reuse +// the register, rather than encode the immediate in every instruction. +// This has the risk of increasing register pressure from stretched live +// ranges, however, the immediates should be trivial to rematerialize by +// the RA in the event of high register pressure. +// TODO : This is currently enabled for stores and binary ops. There are more +// cases for which this can be enabled, though this catches the bulk of the +// issues. +// TODO2 : This should really also be enabled under O2, but there's currently +// an issue with RA where we don't pull the constants into their users +// when we rematerialize them. I'll follow-up on enabling O2 after we fix that +// issue. +// TODO3 : This is currently limited to single basic blocks (DAG creation +// pulls block immediates to the top and merges them if necessary). +// Eventually, it would be nice to allow ConstantHoisting to merge constants +// globally for potentially added savings. +// +def imm_su : PatLeaf<(imm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def relocImm8_su : PatLeaf<(i8 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def relocImm16_su : PatLeaf<(i16 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def relocImm32_su : PatLeaf<(i32 relocImm), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i16relocImmSExt8_su : PatLeaf<(i16relocImmSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i32relocImmSExt8_su : PatLeaf<(i32relocImmSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; +def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ + return !shouldAvoidImmediateInstFormsForSize(N); +}]>; + +// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit +// unsigned field. +def i64immZExt32 : ImmLeaf(Imm); }]>; + +def i64immZExt32SExt8 : ImmLeaf(Imm) && isInt<8>(static_cast(Imm)); +}]>; + +// Helper fragments for loads. + +// It's safe to fold a zextload/extload from i1 as a regular i8 load. The +// upper bits are guaranteed to be zero and we were going to emit a MOV8rm +// which might get folded during peephole anyway. +def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || + ExtType == ISD::ZEXTLOAD; +}]>; + +// It's always safe to treat a anyext i16 load as a i32 load if the i16 is +// known to be 32-bit aligned or better. Ditto for i8 to i16. +def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) + return LD->getAlign() >= 2 && LD->isSimple(); + return false; +}]>; + +def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType == ISD::NON_EXTLOAD) + return true; + if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) + return LD->getAlign() >= 4 && LD->isSimple(); + return false; +}]>; + +def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; +def loadf16 : PatFrag<(ops node:$ptr), (f16 (load node:$ptr))>; +def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; +def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; +def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; +def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; +def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Ld->getAlign() >= Ld->getMemoryVT().getStoreSize(); +}]>; +def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ + LoadSDNode *Ld = cast(N); + return Subtarget->hasSSEUnalignedMem() || + Ld->getAlign() >= Ld->getMemoryVT().getStoreSize(); +}]>; + +def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; +def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; +def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; +def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; +def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; +def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; + +def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; +def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; +def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; +def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; +def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; +def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; +def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; +def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; +def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; +def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; + +def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; +def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; +def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; +def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; +def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; +def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; +def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; +def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; +def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; + +// We can treat an i8/i16 extending load to i64 as a 32 bit load if its known +// to be 4 byte aligned or better. +def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (unindexedload node:$ptr)), [{ + LoadSDNode *LD = cast(N); + ISD::LoadExtType ExtType = LD->getExtensionType(); + if (ExtType != ISD::EXTLOAD) + return false; + if (LD->getMemoryVT() == MVT::i32) + return true; + + return LD->getAlign() >= 4 && LD->isSimple(); +}]>; + +// binary op with only one user +class binop_oneuse + : PatFrag<(ops node:$A, node:$B), + (operator node:$A, node:$B), [{ + return N->hasOneUse(); +}]>; + +def add_su : binop_oneuse; +def and_su : binop_oneuse; +def srl_su : binop_oneuse; + +// unary op with only one user +class unop_oneuse + : PatFrag<(ops node:$A), + (operator node:$A), [{ + return N->hasOneUse(); +}]>; + + +def ineg_su : unop_oneuse; +def trunc_su : unop_oneuse; + +def X86add_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), + (X86add_flag node:$lhs, node:$rhs), [{ + return hasNoCarryFlagUses(SDValue(N, 1)); +}]>; + +def X86sub_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), + (X86sub_flag node:$lhs, node:$rhs), [{ + // Only use DEC if the result is used. + return !SDValue(N, 0).use_empty() && hasNoCarryFlagUses(SDValue(N, 1)); +}]>; + +def X86testpat : PatFrag<(ops node:$lhs, node:$rhs), + (X86cmp (and_su node:$lhs, node:$rhs), 0)>; + + +def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs), + [(X86strict_fcmp node:$lhs, node:$rhs), + (X86fcmp node:$lhs, node:$rhs)]>; + +// PREFETCHWT1 is supported we want to use it for everything but T0. +def PrefetchWLevel : PatFrag<(ops), (i32 timm), [{ + return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1(); +}]>; + +// Use PREFETCHWT1 for NTA, T2, T1. +def PrefetchWT1Level : TImmLeaf; + +def X86lock_add_nocf : PatFrag<(ops node:$lhs, node:$rhs), + (X86lock_add node:$lhs, node:$rhs), [{ + return hasNoCarryFlagUses(SDValue(N, 0)); +}]>; + +def X86lock_sub_nocf : PatFrag<(ops node:$lhs, node:$rhs), + (X86lock_sub node:$lhs, node:$rhs), [{ + return hasNoCarryFlagUses(SDValue(N, 0)); +}]>; + +def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), + (X86tcret node:$ptr, node:$off), [{ + // X86tcret args: (*chain, ptr, imm, regs..., glue) + unsigned NumRegs = 0; + for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) + if (isa(N->getOperand(i)) && ++NumRegs > 6) + return false; + return true; +}]>; + +def X86tcret_1reg : PatFrag<(ops node:$ptr, node:$off), + (X86tcret node:$ptr, node:$off), [{ + // X86tcret args: (*chain, ptr, imm, regs..., glue) + unsigned NumRegs = 1; + const SDValue& BasePtr = cast(N->getOperand(1))->getBasePtr(); + if (isa(BasePtr)) + NumRegs = 3; + else if (BasePtr->getNumOperands() && isa(BasePtr->getOperand(0))) + NumRegs = 3; + for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) + if (isa(N->getOperand(i)) && ( NumRegs-- == 0)) + return false; + return true; +}]>; + +// If this is an anyext of the remainder of an 8-bit sdivrem, use a MOVSX +// instead of a MOVZX. The sdivrem lowering will emit emit a MOVSX to move +// %ah to the lower byte of a register. By using a MOVSX here we allow a +// post-isel peephole to merge the two MOVSX instructions into one. +def anyext_sdiv : PatFrag<(ops node:$lhs), (anyext node:$lhs),[{ + return (N->getOperand(0).getOpcode() == ISD::SDIVREM && + N->getOperand(0).getResNo() == 1); +}]>; + +// Any instruction that defines a 32-bit result leaves the high half of the +// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may +// be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying +// anything about the upper 32 bits, they're probably just qualifying a +// CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit +// operation will zero-extend up to 64 bits. +def def32 : PatLeaf<(i32 GR32:$src), [{ + return N->getOpcode() != ISD::TRUNCATE && + N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && + N->getOpcode() != ISD::CopyFromReg && + N->getOpcode() != ISD::AssertSext && + N->getOpcode() != ISD::AssertZext && + N->getOpcode() != ISD::AssertAlign && + N->getOpcode() != ISD::FREEZE; +}]>; + +// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. +def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ + if (ConstantSDNode *CN = dyn_cast(N->getOperand(1))) + return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); + + KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0); + KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0); + return (~Known0.Zero & ~Known1.Zero) == 0; +}]>; + +def shiftMask8 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ + return isUnneededShiftMask(N, 3); +}]>; + +def shiftMask16 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ + return isUnneededShiftMask(N, 4); +}]>; + +def shiftMask32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ + return isUnneededShiftMask(N, 5); +}]>; + +def shiftMask64 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ + return isUnneededShiftMask(N, 6); +}]>; + +//===----------------------------------------------------------------------===// +// Pattern fragments to auto generate BMI instructions. +//===----------------------------------------------------------------------===// + +def or_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), + (X86or_flag node:$lhs, node:$rhs), [{ + return hasNoCarryFlagUses(SDValue(N, 1)); +}]>; + +def xor_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), + (X86xor_flag node:$lhs, node:$rhs), [{ + return hasNoCarryFlagUses(SDValue(N, 1)); +}]>; + +def and_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), + (X86and_flag node:$lhs, node:$rhs), [{ + return hasNoCarryFlagUses(SDValue(N, 1)); +}]>; + +//===----------------------------------------------------------------------===// +// FPStack specific DAG Nodes. +//===----------------------------------------------------------------------===// + +def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, + SDTCisPtrTy<1>]>; +def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, + SDTCisPtrTy<1>]>; +def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; +def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; + +def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; +def SDTX86CwdLoad : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; +def SDTX86FPEnv : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; + +def X86fp80_add : SDNode<"X86ISD::FP80_ADD", SDTFPBinOp, [SDNPCommutative]>; +def X86strict_fp80_add : SDNode<"X86ISD::STRICT_FP80_ADD", SDTFPBinOp, + [SDNPHasChain,SDNPCommutative]>; +def any_X86fp80_add : PatFrags<(ops node:$lhs, node:$rhs), + [(X86strict_fp80_add node:$lhs, node:$rhs), + (X86fp80_add node:$lhs, node:$rhs)]>; + +def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; +def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; +def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, + [SDNPHasChain, SDNPMayStore, SDNPSideEffect, + SDNPMemOperand]>; +def X86fp_cwd_set16 : SDNode<"X86ISD::FLDCW16m", SDTX86CwdLoad, + [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, + SDNPMemOperand]>; +def X86fpenv_get : SDNode<"X86ISD::FNSTENVm", SDTX86FPEnv, + [SDNPHasChain, SDNPMayStore, SDNPSideEffect, + SDNPMemOperand]>; +def X86fpenv_set : SDNode<"X86ISD::FLDENVm", SDTX86FPEnv, + [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, + SDNPMemOperand]>; + +def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), + (X86fst node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f32; +}]>; +def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), + (X86fst node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f64; +}]>; +def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), + (X86fst node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f80; +}]>; + +def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f32; +}]>; +def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f64; +}]>; +def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f80; +}]>; + +def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i16; +}]>; +def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i32; +}]>; +def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i64; +}]>; + +def X86fist32 : PatFrag<(ops node:$val, node:$ptr), + (X86fist node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i32; +}]>; + +def X86fist64 : PatFrag<(ops node:$val, node:$ptr), + (X86fist node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i64; +}]>; + +def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), + (X86fp_to_mem node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i16; +}]>; +def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), + (X86fp_to_mem node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i32; +}]>; +def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), + (X86fp_to_mem node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i64; +}]>; + +//===----------------------------------------------------------------------===// +// FPStack pattern fragments +//===----------------------------------------------------------------------===// + +def fpimm0 : FPImmLeaf; + +def fpimmneg0 : FPImmLeaf; + +def fpimm1 : FPImmLeaf; + +def fpimmneg1 : FPImmLeaf; diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td index 9c1f33e6f975..f86e15b3ed5d 100644 --- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -1045,10 +1045,6 @@ def sse_load_f64 : PatFrags<(ops node:$ptr), (v2f64 (X86vzload64 node:$ptr)), (v2f64 (scalar_to_vector (loadf64 node:$ptr)))]>; -def shmem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>; -def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; -def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; - def fp16imm0 : PatLeaf<(f16 fpimm), [{ return N->isExactlyValue(+0.0); }]>; @@ -1263,3 +1259,116 @@ def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3) (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ return cast(N)->getMemoryVT().getScalarType() == MVT::i32; }]>; + +def X86Vfpclasss_su : PatFrag<(ops node:$src1, node:$src2), + (X86Vfpclasss node:$src1, node:$src2), [{ + return N->hasOneUse(); +}]>; + +def X86Vfpclass_su : PatFrag<(ops node:$src1, node:$src2), + (X86Vfpclass node:$src1, node:$src2), [{ + return N->hasOneUse(); +}]>; + +// These nodes use 'vnot' instead of 'not' to support vectors. +def vandn : PatFrag<(ops node:$i0, node:$i1), (and (vnot node:$i0), node:$i1)>; +def vxnor : PatFrag<(ops node:$i0, node:$i1), (vnot (xor node:$i0, node:$i1))>; + +// Used for matching masked operations. Ensures the operation part only has a +// single use. +def vselect_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2), + (vselect node:$mask, node:$src1, node:$src2), [{ + return isProfitableToFormMaskedOp(N); +}]>; + +def X86selects_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2), + (X86selects node:$mask, node:$src1, node:$src2), [{ + return isProfitableToFormMaskedOp(N); +}]>; + +def X86cmpms_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (X86cmpms node:$src1, node:$src2, node:$cc), [{ + return N->hasOneUse(); +}]>; +def X86cmpmsSAE_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (X86cmpmsSAE node:$src1, node:$src2, node:$cc), [{ + return N->hasOneUse(); +}]>; + +// PatFrags that contain a select and a truncate op. The take operands in the +// same order as X86vmtrunc, X86vmtruncs, X86vmtruncus. This allows us to pass +// either to the multiclasses. +def select_trunc : PatFrag<(ops node:$src, node:$src0, node:$mask), + (vselect_mask node:$mask, + (trunc node:$src), node:$src0)>; +def select_truncs : PatFrag<(ops node:$src, node:$src0, node:$mask), + (vselect_mask node:$mask, + (X86vtruncs node:$src), node:$src0)>; +def select_truncus : PatFrag<(ops node:$src, node:$src0, node:$mask), + (vselect_mask node:$mask, + (X86vtruncus node:$src), node:$src0)>; + +def X86Vpshufbitqmb_su : PatFrag<(ops node:$src1, node:$src2), + (X86Vpshufbitqmb node:$src1, node:$src2), [{ + return N->hasOneUse(); +}]>; + +// This fragment treats X86cmpm as commutable to help match loads in both +// operands for PCMPEQ. +def X86setcc_commute : SDNode<"ISD::SETCC", SDTSetCC, [SDNPCommutative]>; +def X86pcmpgtm : PatFrag<(ops node:$src1, node:$src2), + (setcc node:$src1, node:$src2, SETGT)>; + +def X86pcmpm_imm : SDNodeXForm(N->getOperand(2))->get(); + uint8_t SSECC = X86::getVPCMPImmForCond(CC); + return getI8Imm(SSECC, SDLoc(N)); +}]>; + +// Swapped operand version of the above. +def X86pcmpm_imm_commute : SDNodeXForm(N->getOperand(2))->get(); + uint8_t SSECC = X86::getVPCMPImmForCond(CC); + SSECC = X86::getSwappedVPCMPImm(SSECC); + return getI8Imm(SSECC, SDLoc(N)); +}]>; + +def X86pcmpm : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return !ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm>; + +def X86pcmpm_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return N->hasOneUse() && !ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm>; + +def X86pcmpum : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm>; + +def X86pcmpum_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (setcc node:$src1, node:$src2, node:$cc), [{ + ISD::CondCode CC = cast(N->getOperand(2))->get(); + return N->hasOneUse() && ISD::isUnsignedIntSetCC(CC); +}], X86pcmpm_imm>; + +def X86cmpm_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), + (X86cmpm node:$src1, node:$src2, node:$cc), [{ + return N->hasOneUse(); +}]>; + +def X86cmpm_imm_commute : SDNodeXFormgetZExtValue() & 0x1f); + return getI8Imm(Imm, SDLoc(N)); +}]>; + +def X86vpmaddwd_su : PatFrag<(ops node:$lhs, node:$rhs), + (X86vpmaddwd node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; + diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index ea3bf1f101c1..a69ce40982ad 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -780,8 +780,16 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable( // flag set. llvm_unreachable("Unknown rematerializable operation!"); break; - + case X86::IMPLICIT_DEF: + // Defer to generic logic. + break; case X86::LOAD_STACK_GUARD: + case X86::LD_Fp032: + case X86::LD_Fp064: + case X86::LD_Fp080: + case X86::LD_Fp132: + case X86::LD_Fp164: + case X86::LD_Fp180: case X86::AVX1_SETALLONES: case X86::AVX2_SETALLONES: case X86::AVX512_128_SET0: diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 9ec09ac3d28e..ee54796323b8 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -6,1413 +6,36 @@ // //===----------------------------------------------------------------------===// // -// This file describes the X86 properties of the instructions which are needed +// This file describes the X86 properties of the instructions which are needed // for code generation, machine code emission, and analysis. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// X86 specific DAG Nodes. +// X86 Pattern fragments. // - -def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, - SDTCisSameAs<1, 2>]>; -def SDTX86FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisFP<1>, - SDTCisSameAs<1, 2>]>; - -def SDTX86Cmov : SDTypeProfile<1, 4, - [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, - SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; - -// Unary and binary operator instructions that set EFLAGS as a side-effect. -def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, - [SDTCisSameAs<0, 2>, - SDTCisInt<0>, SDTCisVT<1, i32>]>; - -def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, - [SDTCisSameAs<0, 2>, - SDTCisSameAs<0, 3>, - SDTCisInt<0>, SDTCisVT<1, i32>]>; - -// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS -def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, - [SDTCisSameAs<0, 2>, - SDTCisSameAs<0, 3>, - SDTCisInt<0>, - SDTCisVT<1, i32>, - SDTCisVT<4, i32>]>; -// RES1, RES2, FLAGS = op LHS, RHS -def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, - [SDTCisSameAs<0, 1>, - SDTCisSameAs<0, 2>, - SDTCisSameAs<0, 3>, - SDTCisInt<0>, SDTCisVT<1, i32>]>; -def SDTX86BrCond : SDTypeProfile<0, 3, - [SDTCisVT<0, OtherVT>, - SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; - -def SDTX86SetCC : SDTypeProfile<1, 2, - [SDTCisVT<0, i8>, - SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; -def SDTX86SetCC_C : SDTypeProfile<1, 2, - [SDTCisInt<0>, - SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; - -def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; - -def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; - -def SDTX86rdpkru : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; -def SDTX86wrpkru : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, - SDTCisVT<2, i32>]>; - -def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, - SDTCisVT<2, i8>]>; -def SDTX86cas8pair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; -def SDTX86cas16pair : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i64>]>; - -def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, - SDTCisPtrTy<1>, - SDTCisInt<2>]>; - -def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, - SDTCisPtrTy<1>]>; - -def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; - -def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, - SDTCisVT<1, i32>]>; -def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, - SDTCisVT<1, i32>]>; - -def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; - -def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; - -def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, - SDTCisPtrTy<1>]>; - -def SDT_X86VAARG : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, - SDTCisPtrTy<1>, - SDTCisVT<2, i32>, - SDTCisVT<3, i8>, - SDTCisVT<4, i32>]>; - -def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; - -def SDTX86Void : SDTypeProfile<0, 0, []>; - -def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; - -def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; - -def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; - -def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; - -def SDT_X86DYN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; - -def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; - -def SDT_X86PROBED_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; - -def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; - -def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; - -def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, - SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>; - -def SDT_X86AESENCDECKL : SDTypeProfile<2, 2, [SDTCisVT<0, v2i64>, - SDTCisVT<1, i32>, - SDTCisVT<2, v2i64>, - SDTCisPtrTy<3>]>; - -def SDTX86Cmpccxadd : SDTypeProfile<1, 4, [SDTCisSameAs<0, 2>, - SDTCisPtrTy<1>, SDTCisSameAs<2, 3>, - SDTCisVT<4, i8>]>; - -def X86MFence : SDNode<"X86ISD::MFENCE", SDTNone, [SDNPHasChain]>; - - -def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; -def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; -def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>; -def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>; - -def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; -def X86fcmp : SDNode<"X86ISD::FCMP", SDTX86FCmp>; -def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86FCmp, [SDNPHasChain]>; -def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86FCmp, [SDNPHasChain]>; -def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; - -def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; -def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, - [SDNPHasChain]>; -def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; -def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; - -def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, - [SDNPHasChain, SDNPSideEffect]>; - -def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, - [SDNPHasChain, SDNPSideEffect]>; - -def X86rdpkru : SDNode<"X86ISD::RDPKRU", SDTX86rdpkru, - [SDNPHasChain, SDNPSideEffect]>; -def X86wrpkru : SDNode<"X86ISD::WRPKRU", SDTX86wrpkru, - [SDNPHasChain, SDNPSideEffect]>; - -def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, - [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; -def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8pair, - [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; -def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86cas16pair, - [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, - SDNPMayLoad, SDNPMemOperand]>; - -def X86retglue : SDNode<"X86ISD::RET_GLUE", SDTX86Ret, - [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; -def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, - [SDNPHasChain, SDNPOptInGlue]>; - -def X86vastart_save_xmm_regs : - SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", - SDT_X86VASTART_SAVE_XMM_REGS, - [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPVariadic]>; -def X86vaarg64 : - SDNode<"X86ISD::VAARG_64", SDT_X86VAARG, - [SDNPHasChain, SDNPMayLoad, SDNPMayStore, - SDNPMemOperand]>; -def X86vaargx32 : - SDNode<"X86ISD::VAARG_X32", SDT_X86VAARG, - [SDNPHasChain, SDNPMayLoad, SDNPMayStore, - SDNPMemOperand]>; -def X86callseq_start : - SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, - [SDNPHasChain, SDNPOutGlue]>; -def X86callseq_end : - SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, - [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; - -def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, - [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, - SDNPVariadic]>; - -def X86call_rvmarker : SDNode<"X86ISD::CALL_RVMARKER", SDT_X86Call, - [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, - SDNPVariadic]>; - - -def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, - [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, - SDNPVariadic]>; -def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, - [SDNPHasChain]>; - -def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, - [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; -def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, - [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, - SDNPMayLoad]>; - -def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; -def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; - -def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", - SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, - SDTCisInt<1>]>>; - -def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, - [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; - -def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, - [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; - -def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, - [SDNPHasChain]>; - -def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", - SDTypeProfile<1, 1, [SDTCisInt<0>, - SDTCisPtrTy<1>]>, - [SDNPHasChain, SDNPSideEffect]>; -def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", - SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, - [SDNPHasChain, SDNPSideEffect]>; -def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", - SDTypeProfile<0, 0, []>, - [SDNPHasChain, SDNPSideEffect]>; - -def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, - [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; - -def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, - [SDNPCommutative]>; -def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; -def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, - [SDNPCommutative]>; -def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, - [SDNPCommutative]>; -def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; -def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; - -def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, - [SDNPCommutative]>; -def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, - [SDNPCommutative]>; -def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, - [SDNPCommutative]>; - -def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, - [SDNPHasChain, SDNPMayStore, SDNPMayLoad, - SDNPMemOperand]>; -def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, - [SDNPHasChain, SDNPMayStore, SDNPMayLoad, - SDNPMemOperand]>; -def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, - [SDNPHasChain, SDNPMayStore, SDNPMayLoad, - SDNPMemOperand]>; -def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, - [SDNPHasChain, SDNPMayStore, SDNPMayLoad, - SDNPMemOperand]>; -def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, - [SDNPHasChain, SDNPMayStore, SDNPMayLoad, - SDNPMemOperand]>; - -def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; -def X86bextri : SDNode<"X86ISD::BEXTRI", SDTIntBinOp>; - -def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntBinOp>; - -def X86pdep : SDNode<"X86ISD::PDEP", SDTIntBinOp>; -def X86pext : SDNode<"X86ISD::PEXT", SDTIntBinOp>; - -def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; - -def X86DynAlloca : SDNode<"X86ISD::DYN_ALLOCA", SDT_X86DYN_ALLOCA, - [SDNPHasChain, SDNPOutGlue]>; - -def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, - [SDNPHasChain]>; - -def X86ProbedAlloca : SDNode<"X86ISD::PROBED_ALLOCA", SDT_X86PROBED_ALLOCA, - [SDNPHasChain]>; - -def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, - [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; - -def X86lwpins : SDNode<"X86ISD::LWPINS", - SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, - SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, - [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; - -def X86umwait : SDNode<"X86ISD::UMWAIT", - SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, - SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, - [SDNPHasChain, SDNPSideEffect]>; - -def X86tpause : SDNode<"X86ISD::TPAUSE", - SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, - SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, - [SDNPHasChain, SDNPSideEffect]>; - -def X86enqcmd : SDNode<"X86ISD::ENQCMD", SDT_X86ENQCMD, - [SDNPHasChain, SDNPSideEffect]>; -def X86enqcmds : SDNode<"X86ISD::ENQCMDS", SDT_X86ENQCMD, - [SDNPHasChain, SDNPSideEffect]>; -def X86testui : SDNode<"X86ISD::TESTUI", - SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, - [SDNPHasChain, SDNPSideEffect]>; - -def X86aesenc128kl : SDNode<"X86ISD::AESENC128KL", SDT_X86AESENCDECKL, - [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, - SDNPMemOperand]>; -def X86aesdec128kl : SDNode<"X86ISD::AESDEC128KL", SDT_X86AESENCDECKL, - [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, - SDNPMemOperand]>; -def X86aesenc256kl : SDNode<"X86ISD::AESENC256KL", SDT_X86AESENCDECKL, - [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, - SDNPMemOperand]>; -def X86aesdec256kl : SDNode<"X86ISD::AESDEC256KL", SDT_X86AESENCDECKL, - [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, - SDNPMemOperand]>; - -def X86cmpccxadd : SDNode<"X86ISD::CMPCCXADD", SDTX86Cmpccxadd, - [SDNPHasChain, SDNPMayLoad, SDNPMayStore, - SDNPMemOperand]>; +include "X86InstrFragments.td" +include "X86InstrFragmentsSIMD.td" //===----------------------------------------------------------------------===// // X86 Operand Definitions. // - -// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for -// the index operand of an address, to conform to x86 encoding restrictions. -def ptr_rc_nosp : PointerLikeRegClass<1>; - -// *mem - Operand definitions for the funky X86 addressing mode operands. -// -def X86MemAsmOperand : AsmOperandClass { - let Name = "Mem"; -} -let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { - def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } - def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } - def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } - def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } - def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } - def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } - def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } - def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } - // Gather mem operands - def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } - def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } - def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } - def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } - def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } - - def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } - def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } - def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } - def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } - def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } - def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } - def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } - def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } - def X86Mem512_GR16Operand : AsmOperandClass { let Name = "Mem512_GR16"; } - def X86Mem512_GR32Operand : AsmOperandClass { let Name = "Mem512_GR32"; } - def X86Mem512_GR64Operand : AsmOperandClass { let Name = "Mem512_GR64"; } - - def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; } -} - -def X86AbsMemAsmOperand : AsmOperandClass { - let Name = "AbsMem"; - let SuperClasses = [X86MemAsmOperand]; -} - -class X86MemOperand : Operand { - let PrintMethod = printMethod; - let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); - let ParserMatchClass = parserMatchClass; - let OperandType = "OPERAND_MEMORY"; - int Size = size; -} - -// Gather mem operands -class X86VMemOperand - : X86MemOperand { - let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); -} - -def anymem : X86MemOperand<"printMemReference">; -def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs), - [(X86strict_fcmp node:$lhs, node:$rhs), - (X86fcmp node:$lhs, node:$rhs)]>; - -// FIXME: Right now we allow any size during parsing, but we might want to -// restrict to only unsized memory. -def opaquemem : X86MemOperand<"printMemReference">; - -def sibmem: X86MemOperand<"printMemReference", X86SibMemOperand>; - -def i8mem : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8>; -def i16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; -def i32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; -def i64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; -def i128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; -def i256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; -def i512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; -def f16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; -def f32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; -def f64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; -def f80mem : X86MemOperand<"printtbytemem", X86Mem80AsmOperand, 80>; -def f128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; -def f256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; -def f512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; - -// 32/64 mode specific mem operands -def i512mem_GR16 : X86MemOperand<"printzmmwordmem", X86Mem512_GR16Operand, 512>; -def i512mem_GR32 : X86MemOperand<"printzmmwordmem", X86Mem512_GR32Operand, 512>; -def i512mem_GR64 : X86MemOperand<"printzmmwordmem", X86Mem512_GR64Operand, 512>; - -// Gather mem operands -def vx64mem : X86VMemOperand; -def vx128mem : X86VMemOperand; -def vx256mem : X86VMemOperand; -def vy128mem : X86VMemOperand; -def vy256mem : X86VMemOperand; - -def vx64xmem : X86VMemOperand; -def vx128xmem : X86VMemOperand; -def vx256xmem : X86VMemOperand; -def vy128xmem : X86VMemOperand; -def vy256xmem : X86VMemOperand; -def vy512xmem : X86VMemOperand; -def vz256mem : X86VMemOperand; -def vz512mem : X86VMemOperand; - -// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead -// of a plain GPR, so that it doesn't potentially require a REX prefix. -def ptr_rc_norex : PointerLikeRegClass<2>; -def ptr_rc_norex_nosp : PointerLikeRegClass<3>; - -def i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> { - let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, - SEGMENT_REG); -} - -// GPRs available for tailcall. -// It represents GR32_TC, GR64_TC or GR64_TCW64. -def ptr_rc_tailcall : PointerLikeRegClass<4>; - -// Special i32mem for addresses of load folding tail calls. These are not -// allowed to use callee-saved registers since they must be scheduled -// after callee-saved register are popped. -def i32mem_TC : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32> { - let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, - i32imm, SEGMENT_REG); -} - -// Special i64mem for addresses of load folding tail calls. These are not -// allowed to use callee-saved registers since they must be scheduled -// after callee-saved register are popped. -def i64mem_TC : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64> { - let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, - ptr_rc_tailcall, i32imm, SEGMENT_REG); -} - -// Special parser to detect 16-bit mode to select 16-bit displacement. -def X86AbsMem16AsmOperand : AsmOperandClass { - let Name = "AbsMem16"; - let RenderMethod = "addAbsMemOperands"; - let SuperClasses = [X86AbsMemAsmOperand]; -} - -// Branch targets print as pc-relative values. -class BranchTargetOperand : Operand { - let OperandType = "OPERAND_PCREL"; - let PrintMethod = "printPCRelImm"; - let ParserMatchClass = X86AbsMemAsmOperand; -} - -def i32imm_brtarget : BranchTargetOperand; -def i16imm_brtarget : BranchTargetOperand; - -// 64-bits but only 32 bits are significant, and those bits are treated as being -// pc relative. -def i64i32imm_brtarget : BranchTargetOperand; - -def brtarget : BranchTargetOperand; -def brtarget8 : BranchTargetOperand; -def brtarget16 : BranchTargetOperand { - let ParserMatchClass = X86AbsMem16AsmOperand; -} -def brtarget32 : BranchTargetOperand; - -let RenderMethod = "addSrcIdxOperands" in { - def X86SrcIdx8Operand : AsmOperandClass { - let Name = "SrcIdx8"; - let SuperClasses = [X86Mem8AsmOperand]; - } - def X86SrcIdx16Operand : AsmOperandClass { - let Name = "SrcIdx16"; - let SuperClasses = [X86Mem16AsmOperand]; - } - def X86SrcIdx32Operand : AsmOperandClass { - let Name = "SrcIdx32"; - let SuperClasses = [X86Mem32AsmOperand]; - } - def X86SrcIdx64Operand : AsmOperandClass { - let Name = "SrcIdx64"; - let SuperClasses = [X86Mem64AsmOperand]; - } -} // RenderMethod = "addSrcIdxOperands" - -let RenderMethod = "addDstIdxOperands" in { - def X86DstIdx8Operand : AsmOperandClass { - let Name = "DstIdx8"; - let SuperClasses = [X86Mem8AsmOperand]; - } - def X86DstIdx16Operand : AsmOperandClass { - let Name = "DstIdx16"; - let SuperClasses = [X86Mem16AsmOperand]; - } - def X86DstIdx32Operand : AsmOperandClass { - let Name = "DstIdx32"; - let SuperClasses = [X86Mem32AsmOperand]; - } - def X86DstIdx64Operand : AsmOperandClass { - let Name = "DstIdx64"; - let SuperClasses = [X86Mem64AsmOperand]; - } -} // RenderMethod = "addDstIdxOperands" - -let RenderMethod = "addMemOffsOperands" in { - def X86MemOffs16_8AsmOperand : AsmOperandClass { - let Name = "MemOffs16_8"; - let SuperClasses = [X86Mem8AsmOperand]; - } - def X86MemOffs16_16AsmOperand : AsmOperandClass { - let Name = "MemOffs16_16"; - let SuperClasses = [X86Mem16AsmOperand]; - } - def X86MemOffs16_32AsmOperand : AsmOperandClass { - let Name = "MemOffs16_32"; - let SuperClasses = [X86Mem32AsmOperand]; - } - def X86MemOffs32_8AsmOperand : AsmOperandClass { - let Name = "MemOffs32_8"; - let SuperClasses = [X86Mem8AsmOperand]; - } - def X86MemOffs32_16AsmOperand : AsmOperandClass { - let Name = "MemOffs32_16"; - let SuperClasses = [X86Mem16AsmOperand]; - } - def X86MemOffs32_32AsmOperand : AsmOperandClass { - let Name = "MemOffs32_32"; - let SuperClasses = [X86Mem32AsmOperand]; - } - def X86MemOffs32_64AsmOperand : AsmOperandClass { - let Name = "MemOffs32_64"; - let SuperClasses = [X86Mem64AsmOperand]; - } - def X86MemOffs64_8AsmOperand : AsmOperandClass { - let Name = "MemOffs64_8"; - let SuperClasses = [X86Mem8AsmOperand]; - } - def X86MemOffs64_16AsmOperand : AsmOperandClass { - let Name = "MemOffs64_16"; - let SuperClasses = [X86Mem16AsmOperand]; - } - def X86MemOffs64_32AsmOperand : AsmOperandClass { - let Name = "MemOffs64_32"; - let SuperClasses = [X86Mem32AsmOperand]; - } - def X86MemOffs64_64AsmOperand : AsmOperandClass { - let Name = "MemOffs64_64"; - let SuperClasses = [X86Mem64AsmOperand]; - } -} // RenderMethod = "addMemOffsOperands" - -class X86SrcIdxOperand - : X86MemOperand { - let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); -} - -class X86DstIdxOperand - : X86MemOperand { - let MIOperandInfo = (ops ptr_rc); -} - -def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; -def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; -def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; -def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; -def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; -def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; -def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; -def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; - -class X86MemOffsOperand - : X86MemOperand { - let MIOperandInfo = (ops immOperand, SEGMENT_REG); -} - -def offset16_8 : X86MemOffsOperand; -def offset16_16 : X86MemOffsOperand; -def offset16_32 : X86MemOffsOperand; -def offset32_8 : X86MemOffsOperand; -def offset32_16 : X86MemOffsOperand; -def offset32_32 : X86MemOffsOperand; -def offset32_64 : X86MemOffsOperand; -def offset64_8 : X86MemOffsOperand; -def offset64_16 : X86MemOffsOperand; -def offset64_32 : X86MemOffsOperand; -def offset64_64 : X86MemOffsOperand; - -def ccode : Operand { - let PrintMethod = "printCondCode"; - let OperandNamespace = "X86"; - let OperandType = "OPERAND_COND_CODE"; -} - -class ImmSExtAsmOperandClass : AsmOperandClass { - let SuperClasses = [ImmAsmOperand]; - let RenderMethod = "addImmOperands"; -} - -def X86GR32orGR64AsmOperand : AsmOperandClass { - let Name = "GR32orGR64"; -} -def GR32orGR64 : RegisterOperand { - let ParserMatchClass = X86GR32orGR64AsmOperand; -} - -def X86GR16orGR32orGR64AsmOperand : AsmOperandClass { - let Name = "GR16orGR32orGR64"; -} -def GR16orGR32orGR64 : RegisterOperand { - let ParserMatchClass = X86GR16orGR32orGR64AsmOperand; -} - -def AVX512RCOperand : AsmOperandClass { - let Name = "AVX512RC"; -} -def AVX512RC : Operand { - let PrintMethod = "printRoundingControl"; - let OperandNamespace = "X86"; - let OperandType = "OPERAND_ROUNDING_CONTROL"; - let ParserMatchClass = AVX512RCOperand; -} - -// Sign-extended immediate classes. We don't need to define the full lattice -// here because there is no instruction with an ambiguity between ImmSExti64i32 -// and ImmSExti32i8. -// -// The strange ranges come from the fact that the assembler always works with -// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" -// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). - -// [0, 0x7FFFFFFF] | -// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] -def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { - let Name = "ImmSExti64i32"; -} - -// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | -// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] -def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { - let Name = "ImmSExti16i8"; - let SuperClasses = [ImmSExti64i32AsmOperand]; -} - -// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | -// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] -def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { - let Name = "ImmSExti32i8"; -} - -// [0, 0x0000007F] | -// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] -def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { - let Name = "ImmSExti64i8"; - let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, - ImmSExti64i32AsmOperand]; -} - -// 4-bit immediate used by some XOP instructions -// [0, 0xF] -def ImmUnsignedi4AsmOperand : AsmOperandClass { - let Name = "ImmUnsignedi4"; - let RenderMethod = "addImmOperands"; - let DiagnosticType = "InvalidImmUnsignedi4"; -} - -// Unsigned immediate used by SSE/AVX instructions -// [0, 0xFF] -// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] -def ImmUnsignedi8AsmOperand : AsmOperandClass { - let Name = "ImmUnsignedi8"; - let RenderMethod = "addImmOperands"; -} - -// A couple of more descriptive operand definitions. -// 16-bits but only 8 bits are significant. -def i16i8imm : Operand { - let ParserMatchClass = ImmSExti16i8AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} -// 32-bits but only 8 bits are significant. -def i32i8imm : Operand { - let ParserMatchClass = ImmSExti32i8AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} - -// 64-bits but only 32 bits are significant. -def i64i32imm : Operand { - let ParserMatchClass = ImmSExti64i32AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} - -// 64-bits but only 8 bits are significant. -def i64i8imm : Operand { - let ParserMatchClass = ImmSExti64i8AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} - -// Unsigned 4-bit immediate used by some XOP instructions. -def u4imm : Operand { - let PrintMethod = "printU8Imm"; - let ParserMatchClass = ImmUnsignedi4AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} - -// Unsigned 8-bit immediate used by SSE/AVX instructions. -def u8imm : Operand { - let PrintMethod = "printU8Imm"; - let ParserMatchClass = ImmUnsignedi8AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} - -// 16-bit immediate but only 8-bits are significant and they are unsigned. -// Used by BT instructions. -def i16u8imm : Operand { - let PrintMethod = "printU8Imm"; - let ParserMatchClass = ImmUnsignedi8AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} - -// 32-bit immediate but only 8-bits are significant and they are unsigned. -// Used by some SSE/AVX instructions that use intrinsics. -def i32u8imm : Operand { - let PrintMethod = "printU8Imm"; - let ParserMatchClass = ImmUnsignedi8AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} - -// 64-bit immediate but only 8-bits are significant and they are unsigned. -// Used by BT instructions. -def i64u8imm : Operand { - let PrintMethod = "printU8Imm"; - let ParserMatchClass = ImmUnsignedi8AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} - -def lea64_32mem : Operand { - let PrintMethod = "printMemReference"; - let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); - let ParserMatchClass = X86MemAsmOperand; -} - -// Memory operands that use 64-bit pointers in both ILP32 and LP64. -def lea64mem : Operand { - let PrintMethod = "printMemReference"; - let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); - let ParserMatchClass = X86MemAsmOperand; -} - -let RenderMethod = "addMaskPairOperands" in { - def VK1PairAsmOperand : AsmOperandClass { let Name = "VK1Pair"; } - def VK2PairAsmOperand : AsmOperandClass { let Name = "VK2Pair"; } - def VK4PairAsmOperand : AsmOperandClass { let Name = "VK4Pair"; } - def VK8PairAsmOperand : AsmOperandClass { let Name = "VK8Pair"; } - def VK16PairAsmOperand : AsmOperandClass { let Name = "VK16Pair"; } -} - -def VK1Pair : RegisterOperand { - let ParserMatchClass = VK1PairAsmOperand; -} - -def VK2Pair : RegisterOperand { - let ParserMatchClass = VK2PairAsmOperand; -} - -def VK4Pair : RegisterOperand { - let ParserMatchClass = VK4PairAsmOperand; -} - -def VK8Pair : RegisterOperand { - let ParserMatchClass = VK8PairAsmOperand; -} - -def VK16Pair : RegisterOperand { - let ParserMatchClass = VK16PairAsmOperand; -} +include "X86InstrOperands.td" //===----------------------------------------------------------------------===// -// X86 Complex Pattern Definitions. +// X86 Predicate Definitions. // - -// Define X86-specific addressing mode. -def addr : ComplexPattern; -def lea32addr : ComplexPattern; -// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. -def lea64_32addr : ComplexPattern; - -def tls32addr : ComplexPattern; - -def tls32baseaddr : ComplexPattern; - -def lea64addr : ComplexPattern; - -def tls64addr : ComplexPattern; - -def tls64baseaddr : ComplexPattern; - -def vectoraddr : ComplexPattern; - -// A relocatable immediate is an operand that can be relocated by the linker to -// an immediate, such as a regular symbol in non-PIC code. -def relocImm : ComplexPattern; - -//===----------------------------------------------------------------------===// -// X86 Instruction Predicate Definitions. -def TruePredicate : Predicate<"true">; - -def HasEGPR : Predicate<"Subtarget->hasEGPR()">; -def NoEGPR : Predicate<"!Subtarget->hasEGPR()">; -def HasCMOV : Predicate<"Subtarget->canUseCMOV()">; -def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">; -def HasNOPL : Predicate<"Subtarget->hasNOPL()">; -def HasMMX : Predicate<"Subtarget->hasMMX()">; -def Has3DNow : Predicate<"Subtarget->hasThreeDNow()">; -def Has3DNowA : Predicate<"Subtarget->hasThreeDNowA()">; -def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; -def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; -def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; -def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; -def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; -def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; -def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; -def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; -def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; -def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; -def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; -def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; -def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; -def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; -def NoAVX : Predicate<"!Subtarget->hasAVX()">; -def HasAVX : Predicate<"Subtarget->hasAVX()">; -def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; -def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; -def HasEVEX512 : Predicate<"Subtarget->hasEVEX512()">; -def HasAVX10_1 : Predicate<"Subtarget->hasAVX10_1()">; -def HasAVX10_1_512 : Predicate<"Subtarget->hasAVX10_1_512()">; -def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; -def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; -def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; -def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; -def HasCDI : Predicate<"Subtarget->hasCDI()">; -def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; -def HasPFI : Predicate<"Subtarget->hasPFI()">; -def HasERI : Predicate<"Subtarget->hasERI()">; -def HasDQI : Predicate<"Subtarget->hasDQI()">; -def NoDQI : Predicate<"!Subtarget->hasDQI()">; -def HasBWI : Predicate<"Subtarget->hasBWI()">; -def NoBWI : Predicate<"!Subtarget->hasBWI()">; -def HasVLX : Predicate<"Subtarget->hasVLX()">; -def NoVLX : Predicate<"!Subtarget->hasVLX()">; -def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; -def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; -def HasPKU : Predicate<"Subtarget->hasPKU()">; -def HasVNNI : Predicate<"Subtarget->hasVNNI()">; -def HasVP2INTERSECT : Predicate<"Subtarget->hasVP2INTERSECT()">; -def HasBF16 : Predicate<"Subtarget->hasBF16()">; -def HasFP16 : Predicate<"Subtarget->hasFP16()">; -def HasAVXVNNIINT16 : Predicate<"Subtarget->hasAVXVNNIINT16()">; -def HasAVXVNNIINT8 : Predicate<"Subtarget->hasAVXVNNIINT8()">; -def HasAVXVNNI : Predicate <"Subtarget->hasAVXVNNI()">; -def NoVLX_Or_NoVNNI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVNNI()">; - -def HasBITALG : Predicate<"Subtarget->hasBITALG()">; -def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; -def HasAES : Predicate<"Subtarget->hasAES()">; -def HasVAES : Predicate<"Subtarget->hasVAES()">; -def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; -def HasFXSR : Predicate<"Subtarget->hasFXSR()">; -def HasX87 : Predicate<"Subtarget->hasX87()">; -def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; -def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; -def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; -def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; -def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; -def NoVLX_Or_NoVPCLMULQDQ : - Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; -def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; -def HasGFNI : Predicate<"Subtarget->hasGFNI()">; -def HasFMA : Predicate<"Subtarget->hasFMA()">; -def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; -def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; -def HasXOP : Predicate<"Subtarget->hasXOP()">; -def HasTBM : Predicate<"Subtarget->hasTBM()">; -def NoTBM : Predicate<"!Subtarget->hasTBM()">; -def HasLWP : Predicate<"Subtarget->hasLWP()">; -def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; -def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; -def HasF16C : Predicate<"Subtarget->hasF16C()">; -def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; -def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; -def HasBMI : Predicate<"Subtarget->hasBMI()">; -def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; -def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; -def HasVBMI : Predicate<"Subtarget->hasVBMI()">; -def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; -def HasIFMA : Predicate<"Subtarget->hasIFMA()">; -def HasAVXIFMA : Predicate<"Subtarget->hasAVXIFMA()">; -def NoVLX_Or_NoIFMA : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasIFMA()">; -def HasRTM : Predicate<"Subtarget->hasRTM()">; -def HasADX : Predicate<"Subtarget->hasADX()">; -def HasSHA : Predicate<"Subtarget->hasSHA()">; -def HasSHA512 : Predicate<"Subtarget->hasSHA512()">; -def HasSGX : Predicate<"Subtarget->hasSGX()">; -def HasSM3 : Predicate<"Subtarget->hasSM3()">; -def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; -def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; -def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; -def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; -def HasPREFETCHI : Predicate<"Subtarget->hasPREFETCHI()">; -def HasPrefetchW : Predicate<"Subtarget->hasPrefetchW()">; -def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; -def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; -def HasLAHFSAHF64 : Predicate<"Subtarget->hasLAHFSAHF64()">; -def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; -def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; -def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; -def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; -def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; -def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; -def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; -def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; -def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; -def HasSM4 : Predicate<"Subtarget->hasSM4()">; -def HasCLFLUSH : Predicate<"Subtarget->hasCLFLUSH()">; -def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; -def HasCLWB : Predicate<"Subtarget->hasCLWB()">; -def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; -def HasRDPID : Predicate<"Subtarget->hasRDPID()">; -def HasRDPRU : Predicate<"Subtarget->hasRDPRU()">; -def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; -def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; -def HasCX8 : Predicate<"Subtarget->hasCX8()">; -def HasCX16 : Predicate<"Subtarget->hasCX16()">; -def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; -def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">; -def HasAMXFP16 : Predicate<"Subtarget->hasAMXFP16()">; -def HasCMPCCXADD : Predicate<"Subtarget->hasCMPCCXADD()">; -def HasAVXNECONVERT : Predicate<"Subtarget->hasAVXNECONVERT()">; -def HasKL : Predicate<"Subtarget->hasKL()">; -def HasRAOINT : Predicate<"Subtarget->hasRAOINT()">; -def HasWIDEKL : Predicate<"Subtarget->hasWIDEKL()">; -def HasHRESET : Predicate<"Subtarget->hasHRESET()">; -def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">; -def HasTSXLDTRK : Predicate<"Subtarget->hasTSXLDTRK()">; -def HasAMXTILE : Predicate<"Subtarget->hasAMXTILE()">; -def HasAMXBF16 : Predicate<"Subtarget->hasAMXBF16()">; -def HasAMXINT8 : Predicate<"Subtarget->hasAMXINT8()">; -def HasAMXCOMPLEX : Predicate<"Subtarget->hasAMXCOMPLEX()">; -def HasUINTR : Predicate<"Subtarget->hasUINTR()">; -def HasUSERMSR : Predicate<"Subtarget->hasUSERMSR()">; -def HasCRC32 : Predicate<"Subtarget->hasCRC32()">; - -def HasX86_64 : Predicate<"Subtarget->hasX86_64()">; -def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, - AssemblerPredicate<(all_of (not Is64Bit)), "Not 64-bit mode">; -def In64BitMode : Predicate<"Subtarget->is64Bit()">, - AssemblerPredicate<(all_of Is64Bit), "64-bit mode">; -def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; -def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; -def In16BitMode : Predicate<"Subtarget->is16Bit()">, - AssemblerPredicate<(all_of Is16Bit), "16-bit mode">; -def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, - AssemblerPredicate<(all_of (not Is16Bit)), "Not 16-bit mode">; -def In32BitMode : Predicate<"Subtarget->is32Bit()">, - AssemblerPredicate<(all_of Is32Bit), "32-bit mode">; -def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; -def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; -def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" - "Subtarget->getFrameLowering()->hasFP(*MF)"> { - let RecomputePerFunction = 1; -} -def IsPS : Predicate<"Subtarget->isTargetPS()">; -def NotPS : Predicate<"!Subtarget->isTargetPS()">; -def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; -def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; -def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; -def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; -def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" - "TM.getCodeModel() == CodeModel::Kernel">; -def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; - -// We could compute these on a per-module basis but doing so requires accessing -// the Function object through the Subtarget and objections were raised -// to that (see post-commit review comments for r301750). -let RecomputePerFunction = 1 in { - def OptForSize : Predicate<"shouldOptForSize(MF)">; - def OptForMinSize : Predicate<"MF->getFunction().hasMinSize()">; - def OptForSpeed : Predicate<"!shouldOptForSize(MF)">; - def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " - "shouldOptForSize(MF)">; - def NoSSE41_Or_OptForSize : Predicate<"shouldOptForSize(MF) || " - "!Subtarget->hasSSE41()">; -} - -def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; -def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; -def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; -def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; -def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; -def HasERMSB : Predicate<"Subtarget->hasERMSB()">; -def HasFSRM : Predicate<"Subtarget->hasFSRM()">; -def HasMFence : Predicate<"Subtarget->hasMFence()">; -def UseIndirectThunkCalls : Predicate<"Subtarget->useIndirectThunkCalls()">; -def NotUseIndirectThunkCalls : Predicate<"!Subtarget->useIndirectThunkCalls()">; +include "X86InstrPredicates.td" //===----------------------------------------------------------------------===// // X86 Instruction Format Definitions. // - include "X86InstrFormats.td" //===----------------------------------------------------------------------===// -// Pattern fragments. +// X86 Instruction utilities. // - -// X86 specific condition code. These correspond to CondCode in -// X86InstrInfo.h. They must be kept in synch. -def X86_COND_O : PatLeaf<(i8 0)>; -def X86_COND_NO : PatLeaf<(i8 1)>; -def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C -def X86_COND_AE : PatLeaf<(i8 3)>; // alt. COND_NC -def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z -def X86_COND_NE : PatLeaf<(i8 5)>; // alt. COND_NZ -def X86_COND_BE : PatLeaf<(i8 6)>; // alt. COND_NA -def X86_COND_A : PatLeaf<(i8 7)>; // alt. COND_NBE -def X86_COND_S : PatLeaf<(i8 8)>; -def X86_COND_NS : PatLeaf<(i8 9)>; -def X86_COND_P : PatLeaf<(i8 10)>; // alt. COND_PE -def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO -def X86_COND_L : PatLeaf<(i8 12)>; // alt. COND_NGE -def X86_COND_GE : PatLeaf<(i8 13)>; // alt. COND_NL -def X86_COND_LE : PatLeaf<(i8 14)>; // alt. COND_NG -def X86_COND_G : PatLeaf<(i8 15)>; // alt. COND_NLE - -def i16immSExt8 : ImmLeaf(Imm); }]>; -def i32immSExt8 : ImmLeaf(Imm); }]>; -def i64immSExt8 : ImmLeaf(Imm); }]>; -def i64immSExt32 : ImmLeaf(Imm); }]>; -def i64timmSExt32 : TImmLeaf(Imm); }]>; - -def i16relocImmSExt8 : PatLeaf<(i16 relocImm), [{ - return isSExtAbsoluteSymbolRef(8, N); -}]>; -def i32relocImmSExt8 : PatLeaf<(i32 relocImm), [{ - return isSExtAbsoluteSymbolRef(8, N); -}]>; -def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ - return isSExtAbsoluteSymbolRef(8, N); -}]>; -def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ - return isSExtAbsoluteSymbolRef(32, N); -}]>; - -// If we have multiple users of an immediate, it's much smaller to reuse -// the register, rather than encode the immediate in every instruction. -// This has the risk of increasing register pressure from stretched live -// ranges, however, the immediates should be trivial to rematerialize by -// the RA in the event of high register pressure. -// TODO : This is currently enabled for stores and binary ops. There are more -// cases for which this can be enabled, though this catches the bulk of the -// issues. -// TODO2 : This should really also be enabled under O2, but there's currently -// an issue with RA where we don't pull the constants into their users -// when we rematerialize them. I'll follow-up on enabling O2 after we fix that -// issue. -// TODO3 : This is currently limited to single basic blocks (DAG creation -// pulls block immediates to the top and merges them if necessary). -// Eventually, it would be nice to allow ConstantHoisting to merge constants -// globally for potentially added savings. -// -def imm_su : PatLeaf<(imm), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; -def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; - -def relocImm8_su : PatLeaf<(i8 relocImm), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; -def relocImm16_su : PatLeaf<(i16 relocImm), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; -def relocImm32_su : PatLeaf<(i32 relocImm), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; - -def i16relocImmSExt8_su : PatLeaf<(i16relocImmSExt8), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; -def i32relocImmSExt8_su : PatLeaf<(i32relocImmSExt8), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; -def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; -def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; - -def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; -def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; -def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ - return !shouldAvoidImmediateInstFormsForSize(N); -}]>; - -// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit -// unsigned field. -def i64immZExt32 : ImmLeaf(Imm); }]>; - -def i64immZExt32SExt8 : ImmLeaf(Imm) && isInt<8>(static_cast(Imm)); -}]>; - -// Helper fragments for loads. - -// It's safe to fold a zextload/extload from i1 as a regular i8 load. The -// upper bits are guaranteed to be zero and we were going to emit a MOV8rm -// which might get folded during peephole anyway. -def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ - LoadSDNode *LD = cast(N); - ISD::LoadExtType ExtType = LD->getExtensionType(); - return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || - ExtType == ISD::ZEXTLOAD; -}]>; - -// It's always safe to treat a anyext i16 load as a i32 load if the i16 is -// known to be 32-bit aligned or better. Ditto for i8 to i16. -def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ - LoadSDNode *LD = cast(N); - ISD::LoadExtType ExtType = LD->getExtensionType(); - if (ExtType == ISD::NON_EXTLOAD) - return true; - if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) - return LD->getAlign() >= 2 && LD->isSimple(); - return false; -}]>; - -def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ - LoadSDNode *LD = cast(N); - ISD::LoadExtType ExtType = LD->getExtensionType(); - if (ExtType == ISD::NON_EXTLOAD) - return true; - if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) - return LD->getAlign() >= 4 && LD->isSimple(); - return false; -}]>; - -def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; -def loadf16 : PatFrag<(ops node:$ptr), (f16 (load node:$ptr))>; -def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; -def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; -def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; -def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; -def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ - LoadSDNode *Ld = cast(N); - return Ld->getAlign() >= Ld->getMemoryVT().getStoreSize(); -}]>; -def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ - LoadSDNode *Ld = cast(N); - return Subtarget->hasSSEUnalignedMem() || - Ld->getAlign() >= Ld->getMemoryVT().getStoreSize(); -}]>; - -def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; -def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; -def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; -def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; -def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; -def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; - -def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; -def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; -def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; -def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; -def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; -def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; -def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; -def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; -def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; -def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; - -def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; -def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; -def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; -def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; -def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; -def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; -def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; -def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; -def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; - -// We can treat an i8/i16 extending load to i64 as a 32 bit load if its known -// to be 4 byte aligned or better. -def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (unindexedload node:$ptr)), [{ - LoadSDNode *LD = cast(N); - ISD::LoadExtType ExtType = LD->getExtensionType(); - if (ExtType != ISD::EXTLOAD) - return false; - if (LD->getMemoryVT() == MVT::i32) - return true; - - return LD->getAlign() >= 4 && LD->isSimple(); -}]>; - -// binary op with only one user -class binop_oneuse - : PatFrag<(ops node:$A, node:$B), - (operator node:$A, node:$B), [{ - return N->hasOneUse(); -}]>; - -def add_su : binop_oneuse; -def and_su : binop_oneuse; -def srl_su : binop_oneuse; - -// unary op with only one user -class unop_oneuse - : PatFrag<(ops node:$A), - (operator node:$A), [{ - return N->hasOneUse(); -}]>; - - -def ineg_su : unop_oneuse; -def trunc_su : unop_oneuse; - -//===----------------------------------------------------------------------===// -// X86 Type infomation definitions -//===----------------------------------------------------------------------===// - -/// X86TypeInfo - This is a bunch of information that describes relevant X86 -/// information about value types. For example, it can tell you what the -/// register class and preferred load to use. -class X86TypeInfo { - /// VT - This is the value type itself. - ValueType VT = vt; - - /// InstrSuffix - This is the suffix used on instructions with this type. For - /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q". - string InstrSuffix = instrsuffix; - - /// RegClass - This is the register class associated with this type. For - /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64. - RegisterClass RegClass = regclass; - - /// LoadNode - This is the load node associated with this type. For - /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64. - PatFrag LoadNode = loadnode; - - /// MemOperand - This is the memory operand associated with this type. For - /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem. - X86MemOperand MemOperand = memoperand; - - /// ImmEncoding - This is the encoding of an immediate of this type. For - /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32 - /// since the immediate fields of i64 instructions is a 32-bit sign extended - /// value. - ImmType ImmEncoding = immkind; - - /// ImmOperand - This is the operand kind of an immediate of this type. For - /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 -> - /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign - /// extended value. - Operand ImmOperand = immoperand; - - /// ImmOperator - This is the operator that should be used to match an - /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32). - SDPatternOperator ImmOperator = immoperator; - - SDPatternOperator ImmNoSuOperator = immnosuoperator; - - /// Imm8Operand - This is the operand kind to use for an imm8 of this type. - /// For example, i8 -> , i16 -> i16i8imm, i32 -> i32i8imm. This is - /// only used for instructions that have a sign-extended imm8 field form. - Operand Imm8Operand = imm8operand; - - /// Imm8Operator - This is the operator that should be used to match an 8-bit - /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8). - SDPatternOperator Imm8Operator = imm8operator; - - SDPatternOperator Imm8NoSuOperator = imm8nosuoperator; - - /// HasOddOpcode - This bit is true if the instruction should have an odd (as - /// opposed to even) opcode. Operations on i8 are usually even, operations on - /// other datatypes are odd. - bit HasOddOpcode = hasOddOpcode; - - /// OpSize - Selects whether the instruction needs a 0x66 prefix based on - /// 16-bit vs 32-bit mode. i8/i64 set this to OpSizeFixed. i16 sets this - /// to Opsize16. i32 sets this to OpSize32. - OperandSize OpSize = opSize; - - /// HasREX_W - This bit is set to true if the instruction should have - /// the 0x40 REX prefix. This is set for i64 types. - bit HasREX_W = hasREX_W; -} - -def invalid_node : SDNode<"<>", SDTIntLeaf,[],"<>">; - -def Xi8 : X86TypeInfo; -def Xi16 : X86TypeInfo; -def Xi32 : X86TypeInfo; -def Xi64 : X86TypeInfo; - -/// ITy - This instruction base class takes the type info for the instruction. -/// Using this, it: -/// 1. Concatenates together the instruction mnemonic with the appropriate -/// suffix letter, a tab, and the arguments. -/// 2. Infers whether the instruction should have a 0x66 prefix byte. -/// 3. Infers whether the instruction should have a 0x40 REX_W prefix. -/// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations) -/// or 1 (for i16,i32,i64 operations). -class ITy opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins, - string mnemonic, string args, list pattern> - : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4}, - opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode }, - f, outs, ins, - !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> { - - // Infer instruction prefixes from type info. - let OpSize = typeinfo.OpSize; - let hasREX_W = typeinfo.HasREX_W; -} +include "X86InstrUtils.td" //===----------------------------------------------------------------------===// // Subsystems. @@ -1429,8 +52,6 @@ include "X86InstrShiftRotate.td" // X87 Floating Point Stack. include "X86InstrFPStack.td" -// SIMD support (SSE, MMX and AVX) -include "X86InstrFragmentsSIMD.td" // FMA - Fused Multiply-Add support (requires FMA) include "X86InstrFMA.td" @@ -1447,10 +68,8 @@ include "X86Instr3DNow.td" include "X86InstrVMX.td" include "X86InstrSVM.td" include "X86InstrSNP.td" - include "X86InstrTSX.td" include "X86InstrSGX.td" - include "X86InstrTDX.td" // Key Locker instructions @@ -1471,4 +90,3 @@ include "X86InstrVecCompiler.td" // Assembler mnemonic/instruction aliases include "X86InstrAsmAlias.td" - diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 764d4bd6da2a..82c079fe2ea8 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1244,26 +1244,6 @@ let Predicates = [HasBMI, HasEGPR], Defs = [EFLAGS] in { defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS, "_EVEX">, REX_W, EVEX; } -//===----------------------------------------------------------------------===// -// Pattern fragments to auto generate BMI instructions. -//===----------------------------------------------------------------------===// - -def or_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), - (X86or_flag node:$lhs, node:$rhs), [{ - return hasNoCarryFlagUses(SDValue(N, 1)); -}]>; - -def xor_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), - (X86xor_flag node:$lhs, node:$rhs), [{ - return hasNoCarryFlagUses(SDValue(N, 1)); -}]>; - -def and_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), - (X86and_flag node:$lhs, node:$rhs), [{ - return hasNoCarryFlagUses(SDValue(N, 1)); -}]>; - - let Predicates = [HasBMI] in { // FIXME(1): patterns for the load versions are not implemented // FIXME(2): By only matching `add_su` and `ineg_su` we may emit diff --git a/llvm/lib/Target/X86/X86InstrOperands.td b/llvm/lib/Target/X86/X86InstrOperands.td new file mode 100644 index 000000000000..761458f9cffc --- /dev/null +++ b/llvm/lib/Target/X86/X86InstrOperands.td @@ -0,0 +1,497 @@ +//===------- X86InstrOperands.td - X86 Operand Definitions --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for +// the index operand of an address, to conform to x86 encoding restrictions. +def ptr_rc_nosp : PointerLikeRegClass<1>; + +// *mem - Operand definitions for the funky X86 addressing mode operands. +// +def X86MemAsmOperand : AsmOperandClass { + let Name = "Mem"; +} +let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { + def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } + def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } + def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } + def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } + def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } + def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } + def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } + def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } + // Gather mem operands + def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } + def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } + def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } + def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } + def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } + + def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } + def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } + def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } + def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } + def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } + def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } + def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } + def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } + def X86Mem512_GR16Operand : AsmOperandClass { let Name = "Mem512_GR16"; } + def X86Mem512_GR32Operand : AsmOperandClass { let Name = "Mem512_GR32"; } + def X86Mem512_GR64Operand : AsmOperandClass { let Name = "Mem512_GR64"; } + + def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; } +} + +def X86AbsMemAsmOperand : AsmOperandClass { + let Name = "AbsMem"; + let SuperClasses = [X86MemAsmOperand]; +} + +class X86MemOperand : Operand { + let PrintMethod = printMethod; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); + let ParserMatchClass = parserMatchClass; + let OperandType = "OPERAND_MEMORY"; + int Size = size; +} + +// Gather mem operands +class X86VMemOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); +} + +def anymem : X86MemOperand<"printMemReference">; + +// FIXME: Right now we allow any size during parsing, but we might want to +// restrict to only unsized memory. +def opaquemem : X86MemOperand<"printMemReference">; + +def sibmem: X86MemOperand<"printMemReference", X86SibMemOperand>; + +def i8mem : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8>; +def i16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; +def i32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; +def i64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; +def i128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; +def i256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; +def i512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; +def f16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; +def f32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; +def f64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; +def f80mem : X86MemOperand<"printtbytemem", X86Mem80AsmOperand, 80>; +def f128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; +def f256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; +def f512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; + +// 32/64 mode specific mem operands +def i512mem_GR16 : X86MemOperand<"printzmmwordmem", X86Mem512_GR16Operand, 512>; +def i512mem_GR32 : X86MemOperand<"printzmmwordmem", X86Mem512_GR32Operand, 512>; +def i512mem_GR64 : X86MemOperand<"printzmmwordmem", X86Mem512_GR64Operand, 512>; + +// Gather mem operands +def vx64mem : X86VMemOperand; +def vx128mem : X86VMemOperand; +def vx256mem : X86VMemOperand; +def vy128mem : X86VMemOperand; +def vy256mem : X86VMemOperand; + +def vx64xmem : X86VMemOperand; +def vx128xmem : X86VMemOperand; +def vx256xmem : X86VMemOperand; +def vy128xmem : X86VMemOperand; +def vy256xmem : X86VMemOperand; +def vy512xmem : X86VMemOperand; +def vz256mem : X86VMemOperand; +def vz512mem : X86VMemOperand; + +def shmem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>; +def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; +def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; + +// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead +// of a plain GPR, so that it doesn't potentially require a REX prefix. +def ptr_rc_norex : PointerLikeRegClass<2>; +def ptr_rc_norex_nosp : PointerLikeRegClass<3>; + +def i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> { + let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, + SEGMENT_REG); +} + +// GPRs available for tailcall. +// It represents GR32_TC, GR64_TC or GR64_TCW64. +def ptr_rc_tailcall : PointerLikeRegClass<4>; + +// Special i32mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i32mem_TC : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32> { + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, + i32imm, SEGMENT_REG); +} + +// Special i64mem for addresses of load folding tail calls. These are not +// allowed to use callee-saved registers since they must be scheduled +// after callee-saved register are popped. +def i64mem_TC : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64> { + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, + ptr_rc_tailcall, i32imm, SEGMENT_REG); +} + +// Special parser to detect 16-bit mode to select 16-bit displacement. +def X86AbsMem16AsmOperand : AsmOperandClass { + let Name = "AbsMem16"; + let RenderMethod = "addAbsMemOperands"; + let SuperClasses = [X86AbsMemAsmOperand]; +} + +// Branch targets print as pc-relative values. +class BranchTargetOperand : Operand { + let OperandType = "OPERAND_PCREL"; + let PrintMethod = "printPCRelImm"; + let ParserMatchClass = X86AbsMemAsmOperand; +} + +def i32imm_brtarget : BranchTargetOperand; +def i16imm_brtarget : BranchTargetOperand; + +// 64-bits but only 32 bits are significant, and those bits are treated as being +// pc relative. +def i64i32imm_brtarget : BranchTargetOperand; + +def brtarget : BranchTargetOperand; +def brtarget8 : BranchTargetOperand; +def brtarget16 : BranchTargetOperand { + let ParserMatchClass = X86AbsMem16AsmOperand; +} +def brtarget32 : BranchTargetOperand; + +let RenderMethod = "addSrcIdxOperands" in { + def X86SrcIdx8Operand : AsmOperandClass { + let Name = "SrcIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86SrcIdx16Operand : AsmOperandClass { + let Name = "SrcIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86SrcIdx32Operand : AsmOperandClass { + let Name = "SrcIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86SrcIdx64Operand : AsmOperandClass { + let Name = "SrcIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addSrcIdxOperands" + +let RenderMethod = "addDstIdxOperands" in { + def X86DstIdx8Operand : AsmOperandClass { + let Name = "DstIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86DstIdx16Operand : AsmOperandClass { + let Name = "DstIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86DstIdx32Operand : AsmOperandClass { + let Name = "DstIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86DstIdx64Operand : AsmOperandClass { + let Name = "DstIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addDstIdxOperands" + +let RenderMethod = "addMemOffsOperands" in { + def X86MemOffs16_8AsmOperand : AsmOperandClass { + let Name = "MemOffs16_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs16_16AsmOperand : AsmOperandClass { + let Name = "MemOffs16_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs16_32AsmOperand : AsmOperandClass { + let Name = "MemOffs16_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_8AsmOperand : AsmOperandClass { + let Name = "MemOffs32_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs32_16AsmOperand : AsmOperandClass { + let Name = "MemOffs32_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs32_32AsmOperand : AsmOperandClass { + let Name = "MemOffs32_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_64AsmOperand : AsmOperandClass { + let Name = "MemOffs32_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } + def X86MemOffs64_8AsmOperand : AsmOperandClass { + let Name = "MemOffs64_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs64_16AsmOperand : AsmOperandClass { + let Name = "MemOffs64_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs64_32AsmOperand : AsmOperandClass { + let Name = "MemOffs64_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs64_64AsmOperand : AsmOperandClass { + let Name = "MemOffs64_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addMemOffsOperands" + +class X86SrcIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); +} + +class X86DstIdxOperand + : X86MemOperand { + let MIOperandInfo = (ops ptr_rc); +} + +def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; +def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; +def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; +def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; +def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; +def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; +def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; +def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; + +class X86MemOffsOperand + : X86MemOperand { + let MIOperandInfo = (ops immOperand, SEGMENT_REG); +} + +def offset16_8 : X86MemOffsOperand; +def offset16_16 : X86MemOffsOperand; +def offset16_32 : X86MemOffsOperand; +def offset32_8 : X86MemOffsOperand; +def offset32_16 : X86MemOffsOperand; +def offset32_32 : X86MemOffsOperand; +def offset32_64 : X86MemOffsOperand; +def offset64_8 : X86MemOffsOperand; +def offset64_16 : X86MemOffsOperand; +def offset64_32 : X86MemOffsOperand; +def offset64_64 : X86MemOffsOperand; + +def ccode : Operand { + let PrintMethod = "printCondCode"; + let OperandNamespace = "X86"; + let OperandType = "OPERAND_COND_CODE"; +} + +class ImmSExtAsmOperandClass : AsmOperandClass { + let SuperClasses = [ImmAsmOperand]; + let RenderMethod = "addImmOperands"; +} + +def X86GR32orGR64AsmOperand : AsmOperandClass { + let Name = "GR32orGR64"; +} +def GR32orGR64 : RegisterOperand { + let ParserMatchClass = X86GR32orGR64AsmOperand; +} + +def X86GR16orGR32orGR64AsmOperand : AsmOperandClass { + let Name = "GR16orGR32orGR64"; +} +def GR16orGR32orGR64 : RegisterOperand { + let ParserMatchClass = X86GR16orGR32orGR64AsmOperand; +} + +def AVX512RCOperand : AsmOperandClass { + let Name = "AVX512RC"; +} +def AVX512RC : Operand { + let PrintMethod = "printRoundingControl"; + let OperandNamespace = "X86"; + let OperandType = "OPERAND_ROUNDING_CONTROL"; + let ParserMatchClass = AVX512RCOperand; +} + +// Sign-extended immediate classes. We don't need to define the full lattice +// here because there is no instruction with an ambiguity between ImmSExti64i32 +// and ImmSExti32i8. +// +// The strange ranges come from the fact that the assembler always works with +// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" +// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). + +// [0, 0x7FFFFFFF] | +// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i32"; +} + +// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti16i8"; + let SuperClasses = [ImmSExti64i32AsmOperand]; +} + +// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti32i8"; +} + +// [0, 0x0000007F] | +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { + let Name = "ImmSExti64i8"; + let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, + ImmSExti64i32AsmOperand]; +} + +// 4-bit immediate used by some XOP instructions +// [0, 0xF] +def ImmUnsignedi4AsmOperand : AsmOperandClass { + let Name = "ImmUnsignedi4"; + let RenderMethod = "addImmOperands"; + let DiagnosticType = "InvalidImmUnsignedi4"; +} + +// Unsigned immediate used by SSE/AVX instructions +// [0, 0xFF] +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmUnsignedi8AsmOperand : AsmOperandClass { + let Name = "ImmUnsignedi8"; + let RenderMethod = "addImmOperands"; +} + +// A couple of more descriptive operand definitions. +// 16-bits but only 8 bits are significant. +def i16i8imm : Operand { + let ParserMatchClass = ImmSExti16i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} +// 32-bits but only 8 bits are significant. +def i32i8imm : Operand { + let ParserMatchClass = ImmSExti32i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 32 bits are significant. +def i64i32imm : Operand { + let ParserMatchClass = ImmSExti64i32AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bits but only 8 bits are significant. +def i64i8imm : Operand { + let ParserMatchClass = ImmSExti64i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// Unsigned 4-bit immediate used by some XOP instructions. +def u4imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi4AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// Unsigned 8-bit immediate used by SSE/AVX instructions. +def u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 16-bit immediate but only 8-bits are significant and they are unsigned. +// Used by BT instructions. +def i16u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 32-bit immediate but only 8-bits are significant and they are unsigned. +// Used by some SSE/AVX instructions that use intrinsics. +def i32u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 64-bit immediate but only 8-bits are significant and they are unsigned. +// Used by BT instructions. +def i64u8imm : Operand { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def lea64_32mem : Operand { + let PrintMethod = "printMemReference"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + +// Memory operands that use 64-bit pointers in both ILP32 and LP64. +def lea64mem : Operand { + let PrintMethod = "printMemReference"; + let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); + let ParserMatchClass = X86MemAsmOperand; +} + +let RenderMethod = "addMaskPairOperands" in { + def VK1PairAsmOperand : AsmOperandClass { let Name = "VK1Pair"; } + def VK2PairAsmOperand : AsmOperandClass { let Name = "VK2Pair"; } + def VK4PairAsmOperand : AsmOperandClass { let Name = "VK4Pair"; } + def VK8PairAsmOperand : AsmOperandClass { let Name = "VK8Pair"; } + def VK16PairAsmOperand : AsmOperandClass { let Name = "VK16Pair"; } +} + +def VK1Pair : RegisterOperand { + let ParserMatchClass = VK1PairAsmOperand; +} + +def VK2Pair : RegisterOperand { + let ParserMatchClass = VK2PairAsmOperand; +} + +def VK4Pair : RegisterOperand { + let ParserMatchClass = VK4PairAsmOperand; +} + +def VK8Pair : RegisterOperand { + let ParserMatchClass = VK8PairAsmOperand; +} + +def VK16Pair : RegisterOperand { + let ParserMatchClass = VK16PairAsmOperand; +} diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td new file mode 100644 index 000000000000..8653f15d8602 --- /dev/null +++ b/llvm/lib/Target/X86/X86InstrPredicates.td @@ -0,0 +1,207 @@ +//===---X86InstrPredicates.td - X86 Predicate Definitions --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +def TruePredicate : Predicate<"true">; + +def HasEGPR : Predicate<"Subtarget->hasEGPR()">; +def NoEGPR : Predicate<"!Subtarget->hasEGPR()">; +def HasCMOV : Predicate<"Subtarget->canUseCMOV()">; +def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">; +def HasNOPL : Predicate<"Subtarget->hasNOPL()">; +def HasMMX : Predicate<"Subtarget->hasMMX()">; +def Has3DNow : Predicate<"Subtarget->hasThreeDNow()">; +def Has3DNowA : Predicate<"Subtarget->hasThreeDNowA()">; +def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; +def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; +def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; +def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; +def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; +def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; +def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; +def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; +def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; +def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; +def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; +def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; +def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; +def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; +def NoAVX : Predicate<"!Subtarget->hasAVX()">; +def HasAVX : Predicate<"Subtarget->hasAVX()">; +def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; +def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; +def HasEVEX512 : Predicate<"Subtarget->hasEVEX512()">; +def HasAVX10_1 : Predicate<"Subtarget->hasAVX10_1()">; +def HasAVX10_1_512 : Predicate<"Subtarget->hasAVX10_1_512()">; +def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; +def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; +def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; +def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; +def HasCDI : Predicate<"Subtarget->hasCDI()">; +def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; +def HasPFI : Predicate<"Subtarget->hasPFI()">; +def HasERI : Predicate<"Subtarget->hasERI()">; +def HasDQI : Predicate<"Subtarget->hasDQI()">; +def NoDQI : Predicate<"!Subtarget->hasDQI()">; +def HasBWI : Predicate<"Subtarget->hasBWI()">; +def NoBWI : Predicate<"!Subtarget->hasBWI()">; +def HasVLX : Predicate<"Subtarget->hasVLX()">; +def NoVLX : Predicate<"!Subtarget->hasVLX()">; +def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; +def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; +def HasPKU : Predicate<"Subtarget->hasPKU()">; +def HasVNNI : Predicate<"Subtarget->hasVNNI()">; +def HasVP2INTERSECT : Predicate<"Subtarget->hasVP2INTERSECT()">; +def HasBF16 : Predicate<"Subtarget->hasBF16()">; +def HasFP16 : Predicate<"Subtarget->hasFP16()">; +def HasAVXVNNIINT16 : Predicate<"Subtarget->hasAVXVNNIINT16()">; +def HasAVXVNNIINT8 : Predicate<"Subtarget->hasAVXVNNIINT8()">; +def HasAVXVNNI : Predicate <"Subtarget->hasAVXVNNI()">; +def NoVLX_Or_NoVNNI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVNNI()">; + +def HasBITALG : Predicate<"Subtarget->hasBITALG()">; +def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; +def HasAES : Predicate<"Subtarget->hasAES()">; +def HasVAES : Predicate<"Subtarget->hasVAES()">; +def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; +def HasFXSR : Predicate<"Subtarget->hasFXSR()">; +def HasX87 : Predicate<"Subtarget->hasX87()">; +def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; +def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; +def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; +def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; +def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; +def NoVLX_Or_NoVPCLMULQDQ : + Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; +def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; +def HasGFNI : Predicate<"Subtarget->hasGFNI()">; +def HasFMA : Predicate<"Subtarget->hasFMA()">; +def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; +def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; +def HasXOP : Predicate<"Subtarget->hasXOP()">; +def HasTBM : Predicate<"Subtarget->hasTBM()">; +def NoTBM : Predicate<"!Subtarget->hasTBM()">; +def HasLWP : Predicate<"Subtarget->hasLWP()">; +def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; +def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; +def HasF16C : Predicate<"Subtarget->hasF16C()">; +def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; +def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; +def HasBMI : Predicate<"Subtarget->hasBMI()">; +def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; +def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; +def HasVBMI : Predicate<"Subtarget->hasVBMI()">; +def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; +def HasIFMA : Predicate<"Subtarget->hasIFMA()">; +def HasAVXIFMA : Predicate<"Subtarget->hasAVXIFMA()">; +def NoVLX_Or_NoIFMA : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasIFMA()">; +def HasRTM : Predicate<"Subtarget->hasRTM()">; +def HasADX : Predicate<"Subtarget->hasADX()">; +def HasSHA : Predicate<"Subtarget->hasSHA()">; +def HasSHA512 : Predicate<"Subtarget->hasSHA512()">; +def HasSGX : Predicate<"Subtarget->hasSGX()">; +def HasSM3 : Predicate<"Subtarget->hasSM3()">; +def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; +def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; +def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; +def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; +def HasPREFETCHI : Predicate<"Subtarget->hasPREFETCHI()">; +def HasPrefetchW : Predicate<"Subtarget->hasPrefetchW()">; +def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; +def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; +def HasLAHFSAHF64 : Predicate<"Subtarget->hasLAHFSAHF64()">; +def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; +def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; +def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; +def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; +def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; +def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; +def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; +def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; +def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; +def HasSM4 : Predicate<"Subtarget->hasSM4()">; +def HasCLFLUSH : Predicate<"Subtarget->hasCLFLUSH()">; +def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; +def HasCLWB : Predicate<"Subtarget->hasCLWB()">; +def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; +def HasRDPID : Predicate<"Subtarget->hasRDPID()">; +def HasRDPRU : Predicate<"Subtarget->hasRDPRU()">; +def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; +def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; +def HasCX8 : Predicate<"Subtarget->hasCX8()">; +def HasCX16 : Predicate<"Subtarget->hasCX16()">; +def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; +def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">; +def HasAMXFP16 : Predicate<"Subtarget->hasAMXFP16()">; +def HasCMPCCXADD : Predicate<"Subtarget->hasCMPCCXADD()">; +def HasAVXNECONVERT : Predicate<"Subtarget->hasAVXNECONVERT()">; +def HasKL : Predicate<"Subtarget->hasKL()">; +def HasRAOINT : Predicate<"Subtarget->hasRAOINT()">; +def HasWIDEKL : Predicate<"Subtarget->hasWIDEKL()">; +def HasHRESET : Predicate<"Subtarget->hasHRESET()">; +def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">; +def HasTSXLDTRK : Predicate<"Subtarget->hasTSXLDTRK()">; +def HasAMXTILE : Predicate<"Subtarget->hasAMXTILE()">; +def HasAMXBF16 : Predicate<"Subtarget->hasAMXBF16()">; +def HasAMXINT8 : Predicate<"Subtarget->hasAMXINT8()">; +def HasAMXCOMPLEX : Predicate<"Subtarget->hasAMXCOMPLEX()">; +def HasUINTR : Predicate<"Subtarget->hasUINTR()">; +def HasUSERMSR : Predicate<"Subtarget->hasUSERMSR()">; +def HasCRC32 : Predicate<"Subtarget->hasCRC32()">; + +def HasX86_64 : Predicate<"Subtarget->hasX86_64()">; +def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, + AssemblerPredicate<(all_of (not Is64Bit)), "Not 64-bit mode">; +def In64BitMode : Predicate<"Subtarget->is64Bit()">, + AssemblerPredicate<(all_of Is64Bit), "64-bit mode">; +def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; +def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; +def In16BitMode : Predicate<"Subtarget->is16Bit()">, + AssemblerPredicate<(all_of Is16Bit), "16-bit mode">; +def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, + AssemblerPredicate<(all_of (not Is16Bit)), "Not 16-bit mode">; +def In32BitMode : Predicate<"Subtarget->is32Bit()">, + AssemblerPredicate<(all_of Is32Bit), "32-bit mode">; +def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; +def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; +def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" + "Subtarget->getFrameLowering()->hasFP(*MF)"> { + let RecomputePerFunction = 1; +} +def IsPS : Predicate<"Subtarget->isTargetPS()">; +def NotPS : Predicate<"!Subtarget->isTargetPS()">; +def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; +def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; +def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; +def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; +def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" + "TM.getCodeModel() == CodeModel::Kernel">; +def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; + +// We could compute these on a per-module basis but doing so requires accessing +// the Function object through the Subtarget and objections were raised +// to that (see post-commit review comments for r301750). +let RecomputePerFunction = 1 in { + def OptForSize : Predicate<"shouldOptForSize(MF)">; + def OptForMinSize : Predicate<"MF->getFunction().hasMinSize()">; + def OptForSpeed : Predicate<"!shouldOptForSize(MF)">; + def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " + "shouldOptForSize(MF)">; + def NoSSE41_Or_OptForSize : Predicate<"shouldOptForSize(MF) || " + "!Subtarget->hasSSE41()">; +} + +def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; +def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; +def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; +def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; +def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; +def HasERMSB : Predicate<"Subtarget->hasERMSB()">; +def HasFSRM : Predicate<"Subtarget->hasFSRM()">; +def HasMFence : Predicate<"Subtarget->hasMFence()">; +def UseIndirectThunkCalls : Predicate<"Subtarget->useIndirectThunkCalls()">; +def NotUseIndirectThunkCalls : Predicate<"!Subtarget->useIndirectThunkCalls()">; diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index ef6db2d45d66..34eb17af1033 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -7359,11 +7359,6 @@ defm VPDPBUSDS : avx_vnni_rm<0x51, "vpdpbusds", X86Vpdpbusds, 0>; defm VPDPWSSD : avx_vnni_rm<0x52, "vpdpwssd", X86Vpdpwssd, 1>; defm VPDPWSSDS : avx_vnni_rm<0x53, "vpdpwssds", X86Vpdpwssds, 1>; -def X86vpmaddwd_su : PatFrag<(ops node:$lhs, node:$rhs), - (X86vpmaddwd node:$lhs, node:$rhs), [{ - return N->hasOneUse(); -}]>; - let Predicates = [HasAVXVNNI, NoVLX_Or_NoVNNI] in { def : Pat<(v8i32 (add VR256:$src1, (X86vpmaddwd_su VR256:$src2, VR256:$src3))), diff --git a/llvm/lib/Target/X86/X86InstrUtils.td b/llvm/lib/Target/X86/X86InstrUtils.td new file mode 100644 index 000000000000..071c41da6722 --- /dev/null +++ b/llvm/lib/Target/X86/X86InstrUtils.td @@ -0,0 +1,1014 @@ +//===-- X86InstrUtils.td - X86 Instruction Utilities --------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file provides utilities for simplifying the instruction definitions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Classes for setting the fields of X86Inst +//===----------------------------------------------------------------------===// + +// Prefix byte classes which are used to indicate to the ad-hoc machine code +// emitter that various prefix bytes are required. +class OpSize16 { OperandSize OpSize = OpSize16; } +class OpSize32 { OperandSize OpSize = OpSize32; } +class AdSize16 { AddressSize AdSize = AdSize16; } +class AdSize32 { AddressSize AdSize = AdSize32; } +class AdSize64 { AddressSize AdSize = AdSize64; } +class REX_W { bit hasREX_W = 1; } +class LOCK { bit hasLockPrefix = 1; } +class REP { bit hasREPPrefix = 1; } +class TB { Map OpMap = TB; } +class T8 { Map OpMap = T8; } +class TA { Map OpMap = TA; } +class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } +class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; } +class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; } +class ThreeDNow { Map OpMap = ThreeDNow; } +class T_MAP4 { Map OpMap = T_MAP4; } +class T_MAP4PS : T_MAP4 { Prefix OpPrefix = PS; } // none +class T_MAP4PD : T_MAP4 { Prefix OpPrefix = PD; } // 0x66 +class T_MAP4XS : T_MAP4 { Prefix OpPrefix = XS; } // 0xF3 +class T_MAP4XD : T_MAP4 { Prefix OpPrefix = XD; } // 0xF2 +class T_MAP5 { Map OpMap = T_MAP5; } +class T_MAP5PS : T_MAP5 { Prefix OpPrefix = PS; } // none +class T_MAP5PD : T_MAP5 { Prefix OpPrefix = PD; } // 0x66 +class T_MAP5XS : T_MAP5 { Prefix OpPrefix = XS; } // 0xF3 +class T_MAP5XD : T_MAP5 { Prefix OpPrefix = XD; } // 0xF2 +class T_MAP6 { Map OpMap = T_MAP6; } +class T_MAP6PS : T_MAP6 { Prefix OpPrefix = PS; } +class T_MAP6PD : T_MAP6 { Prefix OpPrefix = PD; } +class T_MAP6XS : T_MAP6 { Prefix OpPrefix = XS; } +class T_MAP6XD : T_MAP6 { Prefix OpPrefix = XD; } +class T_MAP7 { Map OpMap = T_MAP7; } +class T_MAP7XS : T_MAP7 { Prefix OpPrefix = XS; } // 0xF3 +class T_MAP7XD : T_MAP7 { Prefix OpPrefix = XD; } // 0xF2 +class OBXS { Prefix OpPrefix = XS; } +class PS : TB { Prefix OpPrefix = PS; } +class PD : TB { Prefix OpPrefix = PD; } +class XD : TB { Prefix OpPrefix = XD; } +class XS : TB { Prefix OpPrefix = XS; } +class T8PS : T8 { Prefix OpPrefix = PS; } +class T8PD : T8 { Prefix OpPrefix = PD; } +class T8XD : T8 { Prefix OpPrefix = XD; } +class T8XS : T8 { Prefix OpPrefix = XS; } +class TAPS : TA { Prefix OpPrefix = PS; } +class TAPD : TA { Prefix OpPrefix = PD; } +class TAXD : TA { Prefix OpPrefix = XD; } +class TAXS : TA { Prefix OpPrefix = XS; } +class VEX { Encoding OpEnc = EncVEX; } +class WIG { bit IgnoresW = 1; } +// Special version of REX_W that can be changed to VEX.W==0 for EVEX2VEX. +class VEX_W1X { bit hasREX_W = 1; bit EVEX_W1_VEX_W0 = 1; } +class VEX_4V : VEX { bit hasVEX_4V = 1; } +class VEX_L { bit hasVEX_L = 1; } +class VEX_LIG { bit ignoresVEX_L = 1; } +class EVEX { Encoding OpEnc = EncEVEX; } +class EVEX_4V : EVEX { bit hasVEX_4V = 1; } +class EVEX_K { bit hasEVEX_K = 1; } +class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } +class EVEX_B { bit hasEVEX_B = 1; } +class EVEX_RC { bit hasEVEX_RC = 1; } +class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } +class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; } +class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; } +class NOTRACK { bit hasNoTrackPrefix = 1; } +class SIMD_EXC { list Uses = [MXCSR]; bit mayRaiseFPException = 1; } +// Specify AVX512 8-bit compressed displacement encoding based on the vector +// element size in bits (8, 16, 32, 64) and the CDisp8 form. +class EVEX_CD8 { + int CD8_EltSize = !srl(esize, 3); + bits<3> CD8_Form = form.Value; +} +class XOP { Encoding OpEnc = EncXOP; } +class XOP_4V : XOP { bit hasVEX_4V = 1; } +class EVEX2VEXOverride { + string EVEX2VEXOverride = VEXInstrName; +} +class AVX512BIi8Base : PD { + Domain ExeDomain = SSEPackedInt; + ImmType ImmT = Imm8; +} +class AVX512XSIi8Base : XS { + Domain ExeDomain = SSEPackedInt; + ImmType ImmT = Imm8; +} +class AVX512XDIi8Base : XD { + Domain ExeDomain = SSEPackedInt; + ImmType ImmT = Imm8; +} +class AVX512PSIi8Base : PS { + Domain ExeDomain = SSEPackedSingle; + ImmType ImmT = Imm8; +} +class AVX512PDIi8Base : PD { + Domain ExeDomain = SSEPackedDouble; + ImmType ImmT = Imm8; +} +class NotEVEX2VEXConvertible { bit notEVEX2VEXConvertible = 1; } +class ExplicitREX2Prefix { ExplicitOpPrefix explicitOpPrefix = ExplicitREX2; } +class ExplicitVEXPrefix { ExplicitOpPrefix explicitOpPrefix = ExplicitVEX; } +class ExplicitEVEXPrefix { ExplicitOpPrefix explicitOpPrefix = ExplicitEVEX; } + +// SchedModel info for instruction that loads one value and gets the second +// (and possibly third) value from a register. +// This is used for instructions that put the memory operands before other +// uses. +class SchedLoadReg : Sched<[Sched.Folded, + // Memory operand. + ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, + // Register reads (implicit or explicit). + Sched.ReadAfterFold, Sched.ReadAfterFold]>; + +//===----------------------------------------------------------------------===// +// X86 Type infomation definitions +//===----------------------------------------------------------------------===// + +/// X86TypeInfo - This is a bunch of information that describes relevant X86 +/// information about value types. For example, it can tell you what the +/// register class and preferred load to use. +class X86TypeInfo { + /// VT - This is the value type itself. + ValueType VT = vt; + + /// InstrSuffix - This is the suffix used on instructions with this type. For + /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q". + string InstrSuffix = instrsuffix; + + /// RegClass - This is the register class associated with this type. For + /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64. + RegisterClass RegClass = regclass; + + /// LoadNode - This is the load node associated with this type. For + /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64. + PatFrag LoadNode = loadnode; + + /// MemOperand - This is the memory operand associated with this type. For + /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem. + X86MemOperand MemOperand = memoperand; + + /// ImmEncoding - This is the encoding of an immediate of this type. For + /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32 + /// since the immediate fields of i64 instructions is a 32-bit sign extended + /// value. + ImmType ImmEncoding = immkind; + + /// ImmOperand - This is the operand kind of an immediate of this type. For + /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 -> + /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign + /// extended value. + Operand ImmOperand = immoperand; + + /// ImmOperator - This is the operator that should be used to match an + /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32). + SDPatternOperator ImmOperator = immoperator; + + SDPatternOperator ImmNoSuOperator = immnosuoperator; + + /// Imm8Operand - This is the operand kind to use for an imm8 of this type. + /// For example, i8 -> , i16 -> i16i8imm, i32 -> i32i8imm. This is + /// only used for instructions that have a sign-extended imm8 field form. + Operand Imm8Operand = imm8operand; + + /// Imm8Operator - This is the operator that should be used to match an 8-bit + /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8). + SDPatternOperator Imm8Operator = imm8operator; + + SDPatternOperator Imm8NoSuOperator = imm8nosuoperator; + + /// HasOddOpcode - This bit is true if the instruction should have an odd (as + /// opposed to even) opcode. Operations on i8 are usually even, operations on + /// other datatypes are odd. + bit HasOddOpcode = hasOddOpcode; + + /// OpSize - Selects whether the instruction needs a 0x66 prefix based on + /// 16-bit vs 32-bit mode. i8/i64 set this to OpSizeFixed. i16 sets this + /// to Opsize16. i32 sets this to OpSize32. + OperandSize OpSize = opSize; + + /// HasREX_W - This bit is set to true if the instruction should have + /// the 0x40 REX prefix. This is set for i64 types. + bit HasREX_W = hasREX_W; +} + +def invalid_node : SDNode<"<>", SDTIntLeaf,[],"<>">; + +def Xi8 : X86TypeInfo; +def Xi16 : X86TypeInfo; +def Xi32 : X86TypeInfo; +def Xi64 : X86TypeInfo; + +// Group template arguments that can be derived from the vector type (EltNum x +// EltVT). These are things like the register class for the writemask, etc. +// The idea is to pass one of these as the template argument rather than the +// individual arguments. +// The template is also used for scalar types, in this case numelts is 1. +class X86VectorVTInfo { + RegisterClass RC = rc; + ValueType EltVT = eltvt; + int NumElts = numelts; + + // Corresponding mask register class. + RegisterClass KRC = !cast("VK" # NumElts); + + // Corresponding mask register pair class. + RegisterOperand KRPC = !if (!gt(NumElts, 16), ?, + !cast("VK" # NumElts # "Pair")); + + // Corresponding write-mask register class. + RegisterClass KRCWM = !cast("VK" # NumElts # "WM"); + + // The mask VT. + ValueType KVT = !cast("v" # NumElts # "i1"); + + // Suffix used in the instruction mnemonic. + string Suffix = suffix; + + // VTName is a string name for vector VT. For vector types it will be + // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32 + // It is a little bit complex for scalar types, where NumElts = 1. + // In this case we build v4f32 or v2f64 + string VTName = "v" # !if (!eq (NumElts, 1), + !if (!eq (EltVT.Size, 16), 8, + !if (!eq (EltVT.Size, 32), 4, + !if (!eq (EltVT.Size, 64), 2, NumElts))), NumElts) # EltVT; + + // The vector VT. + ValueType VT = !cast(VTName); + + string EltTypeName = !cast(EltVT); + // Size of the element type in bits, e.g. 32 for v16i32. + string EltSizeName = !subst("i", "", !subst("f", "", !subst("b", "", EltTypeName))); + int EltSize = EltVT.Size; + + // "i" for integer types and "f" for floating-point types + string TypeVariantName = !subst("b", "", !subst(EltSizeName, "", EltTypeName)); + + // Size of RC in bits, e.g. 512 for VR512. + int Size = VT.Size; + + // The corresponding memory operand, e.g. i512mem for VR512. + X86MemOperand MemOp = !cast(TypeVariantName # Size # "mem"); + X86MemOperand ScalarMemOp = !cast(!subst("b", "", EltTypeName) # "mem"); + // FP scalar memory operand for intrinsics - ssmem/sdmem. + Operand IntScalarMemOp = !if (!eq (EltTypeName, "f16"), !cast("shmem"), + !if (!eq (EltTypeName, "bf16"), !cast("shmem"), + !if (!eq (EltTypeName, "f32"), !cast("ssmem"), + !if (!eq (EltTypeName, "f64"), !cast("sdmem"), ?)))); + + // Load patterns + PatFrag LdFrag = !cast("load" # VTName); + + PatFrag AlignedLdFrag = !cast("alignedload" # VTName); + + PatFrag ScalarLdFrag = !cast("load" # !subst("b", "", EltTypeName)); + PatFrag BroadcastLdFrag = !cast("X86VBroadcastld" # EltSizeName); + + PatFrags ScalarIntMemFrags = !if (!eq (EltTypeName, "f16"), !cast("sse_load_f16"), + !if (!eq (EltTypeName, "bf16"), !cast("sse_load_f16"), + !if (!eq (EltTypeName, "f32"), !cast("sse_load_f32"), + !if (!eq (EltTypeName, "f64"), !cast("sse_load_f64"), ?)))); + + // The string to specify embedded broadcast in assembly. + string BroadcastStr = "{1to" # NumElts # "}"; + + // 8-bit compressed displacement tuple/subvector format. This is only + // defined for NumElts <= 8. + CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0), + !cast("CD8VT" # NumElts), ?); + + SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm, + !if (!eq (Size, 256), sub_ymm, ?)); + + Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle, + !if (!eq (EltTypeName, "f64"), SSEPackedDouble, + !if (!eq (EltTypeName, "f16"), SSEPackedSingle, // FIXME? + !if (!eq (EltTypeName, "bf16"), SSEPackedSingle, // FIXME? + SSEPackedInt)))); + + RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, + !if (!eq (EltTypeName, "f16"), FR16X, + !if (!eq (EltTypeName, "bf16"), FR16X, + FR64X))); + + dag ImmAllZerosV = (VT immAllZerosV); + + string ZSuffix = !if (!eq (Size, 128), "Z128", + !if (!eq (Size, 256), "Z256", "Z")); +} + +def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">; +def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">; +def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">; +def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">; +def v32f16_info : X86VectorVTInfo<32, f16, VR512, "ph">; +def v32bf16_info: X86VectorVTInfo<32, bf16, VR512, "pbf">; +def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">; +def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">; + +// "x" in v32i8x_info means RC = VR256X +def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">; +def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">; +def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">; +def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">; +def v16f16x_info : X86VectorVTInfo<16, f16, VR256X, "ph">; +def v16bf16x_info: X86VectorVTInfo<16, bf16, VR256X, "pbf">; +def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">; +def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">; + +def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">; +def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">; +def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">; +def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">; +def v8f16x_info : X86VectorVTInfo<8, f16, VR128X, "ph">; +def v8bf16x_info : X86VectorVTInfo<8, bf16, VR128X, "pbf">; +def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">; +def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">; + +// We map scalar types to the smallest (128-bit) vector type +// with the appropriate element type. This allows to use the same masking logic. +def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">; +def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">; +def f16x_info : X86VectorVTInfo<1, f16, VR128X, "sh">; +def bf16x_info : X86VectorVTInfo<1, bf16, VR128X, "sbf">; +def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">; +def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">; + +class AVX512VLVectorVTInfo { + X86VectorVTInfo info512 = i512; + X86VectorVTInfo info256 = i256; + X86VectorVTInfo info128 = i128; +} + +def avx512vl_i8_info : AVX512VLVectorVTInfo; +def avx512vl_i16_info : AVX512VLVectorVTInfo; +def avx512vl_i32_info : AVX512VLVectorVTInfo; +def avx512vl_i64_info : AVX512VLVectorVTInfo; +def avx512vl_f16_info : AVX512VLVectorVTInfo; +def avx512vl_bf16_info : AVX512VLVectorVTInfo; +def avx512vl_f32_info : AVX512VLVectorVTInfo; +def avx512vl_f64_info : AVX512VLVectorVTInfo; + +class X86KVectorVTInfo { + RegisterClass KRC = _krc; + RegisterClass KRCWM = _krcwm; + ValueType KVT = _vt; +} + +def v1i1_info : X86KVectorVTInfo; +def v2i1_info : X86KVectorVTInfo; +def v4i1_info : X86KVectorVTInfo; +def v8i1_info : X86KVectorVTInfo; +def v16i1_info : X86KVectorVTInfo; +def v32i1_info : X86KVectorVTInfo; +def v64i1_info : X86KVectorVTInfo; + +// Subclasses of X86Inst +class PseudoI pattern> + : X86Inst<0, Pseudo, NoImm, oops, iops, ""> { + let Pattern = pattern; +} + +class I o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { + let Pattern = pattern; +} +class Ii8 o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { + let Pattern = pattern; +} +class Ii8Reg o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { + let Pattern = pattern; +} +class Ii8PCRel o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; +} +class Ii16 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; +} +class Ii32 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; +} +class Ii32S o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; +} + +class Ii64 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; +} + +class Ii16PCRel o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; +} + +class Ii32PCRel o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; +} + +// FPStack Instruction Templates: +// FPI - Floating Point Instruction template. +class FPI o, Format F, dag outs, dag ins, string asm> + : I { + let Defs = [FPSW]; + let Predicates = [HasX87]; +} + +// FpI_ - Floating Point Pseudo Instruction template. +class FpI_ pattern> + : PseudoI { + let FPForm = fp; + let Defs = [FPSW]; + let Predicates = [HasX87]; +} + +// Templates for instructions that use a 16- or 32-bit segmented address as +// their only operand: lcall (FAR CALL) and ljmp (FAR JMP) +// +// Iseg16 - 16-bit segment selector, 16-bit offset +// Iseg32 - 16-bit segment selector, 32-bit offset + +class Iseg16 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; +} + +class Iseg32 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst { + let Pattern = pattern; +} + +// SI - SSE 1 & 2 scalar instructions +class SI o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : I { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], + !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], + !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512 +class SI_Int o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : I { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], + !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], + !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} +// SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512 +class SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8 { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], + !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], + [UseSSE2]))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// PI - SSE 1 & 2 packed instructions +class PI o, Format F, dag outs, dag ins, string asm, list pattern, + Domain d> + : I { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// MMXPI - SSE 1 & 2 packed instructions with MMX operands +class MMXPI o, Format F, dag outs, dag ins, string asm, list pattern, + Domain d> + : I { + let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasMMX, HasSSE2], + [HasMMX, HasSSE1]); +} + +// PIi8 - SSE 1 & 2 packed instructions with immediate +class PIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d> + : Ii8 { + let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], + !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], + !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], + [UseSSE1]))); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), + !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), + asm)); +} + +// SSE1 Instruction Templates: +// +// SSI - SSE1 instructions with XS prefix. +// PSI - SSE1 instructions with PS prefix. +// PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. +// VSSI - SSE1 instructions with XS prefix in AVX form. +// VPSI - SSE1 instructions with PS prefix in AVX form, packed single. + +class SSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, Requires<[UseSSE1]>; +class SSIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[UseSSE1]>; +class PSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, + Requires<[UseSSE1]>; +class PSIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PS, + Requires<[UseSSE1]>; +class VSSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[HasAVX]>; +class VPSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, + Requires<[HasAVX]>; + +// SSE2 Instruction Templates: +// +// SDI - SSE2 instructions with XD prefix. +// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. +// S2SI - SSE2 instructions with XS prefix. +// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. +// PDI - SSE2 instructions with PD prefix, packed double domain. +// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. +// VSDI - SSE2 scalar instructions with XD prefix in AVX form. +// VPDI - SSE2 vector instructions with PD prefix in AVX form, +// packed double domain. +// VS2I - SSE2 scalar instructions with PD prefix in AVX form. +// S2I - SSE2 scalar instructions with PD prefix. +// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as +// MMX operands. +// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as +// MMX operands. + +class SDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, Requires<[UseSSE2]>; +class SDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[UseSSE2]>; +class S2SI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, Requires<[UseSSE2]>; +class S2SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[UseSSE2]>; +class PDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[UseSSE2]>; +class PDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PD, + Requires<[UseSSE2]>; +class VSDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, + Requires<[UseAVX]>; +class VS2SI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[HasAVX]>; +class VPDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, + PD, Requires<[HasAVX]>; +class VS2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[UseAVX]>; +class S2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, Requires<[UseSSE2]>; +class MMXSDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[HasMMX, HasSSE2]>; +class MMXS2SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[HasMMX, HasSSE2]>; + +// SSE3 Instruction Templates: +// +// S3I - SSE3 instructions with PD prefixes. +// S3SI - SSE3 instructions with XS prefix. +// S3DI - SSE3 instructions with XD prefix. + +class S3SI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[UseSSE3]>; +class S3DI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, + Requires<[UseSSE3]>; +class S3I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[UseSSE3]>; + + +// SSSE3 Instruction Templates: +// +// SS38I - SSSE3 instructions with T8 prefix. +// SS3AI - SSSE3 instructions with TA prefix. +// MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. +// MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. +// +// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version +// uses the MMX registers. The 64-bit versions are grouped with the MMX +// classes. They need to be enabled even if AVX is enabled. + +class SS38I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[UseSSSE3]>; +class SS3AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[UseSSSE3]>; +class MMXSS38I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PS, + Requires<[HasMMX, HasSSSE3]>; +class MMXSS3AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPS, + Requires<[HasMMX, HasSSSE3]>; + +// SSE4.1 Instruction Templates: +// +// SS48I - SSE 4.1 instructions with T8 prefix. +// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. +// +class SS48I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[UseSSE41]>; +class SS4AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[UseSSE41]>; + +// SSE4.2 Instruction Templates: +// +// SS428I - SSE 4.2 instructions with T8 prefix. +class SS428I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[UseSSE42]>; + +// SS42AI = SSE 4.2 instructions with TA prefix +class SS42AI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[UseSSE42]>; + +// CRC32I - SSE 4.2 CRC32 instructions. +// NOTE: 'HasCRC32' is used as CRC32 instructions are GPR only and not directly +// controlled by the SSE42 flag. +class CRC32I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8XD, Requires<[HasCRC32]>; + +// AVX Instruction Templates: +// Instructions introduced in AVX (no SSE equivalent forms) +// +// AVX8I - AVX instructions with T8PD prefix. +// AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. +class AVX8I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[HasAVX]>; +class AVXAIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[HasAVX]>; + +// AVX2 Instruction Templates: +// Instructions introduced in AVX2 (no SSE equivalent forms) +// +// AVX28I - AVX2 instructions with T8PD prefix. +// AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. +class AVX28I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[HasAVX2]>; +class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[HasAVX2]>; + + +// AVX-512 Instruction Templates: +// Instructions introduced in AVX-512 (no SSE equivalent forms) +// +// AVX5128I - AVX-512 instructions with T8PD prefix. +// AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. +// AVX512PDI - AVX-512 instructions with PD, double packed. +// AVX512PSI - AVX-512 instructions with PS, single packed. +// AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. +// AVX512XSI - AVX-512 instructions with XS prefix, generic domain. +// AVX512BI - AVX-512 instructions with PD, int packed domain. +// AVX512SI - AVX-512 scalar instructions with PD prefix. + +class AVX5128I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8PD, + Requires<[HasAVX512]>; +class AVX5128IBase : T8PD { + Domain ExeDomain = SSEPackedInt; +} +class AVX512XS8I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, T8XS, + Requires<[HasAVX512]>; +class AVX512XSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XS, + Requires<[HasAVX512]>; +class AVX512XDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, XD, + Requires<[HasAVX512]>; +class AVX512BI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[HasAVX512]>; +class AVX512BIBase : PD { + Domain ExeDomain = SSEPackedInt; +} +class AVX512BIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PD, + Requires<[HasAVX512]>; +class AVX512AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[HasAVX512]>; +class AVX512AIi8Base : TAPD { + ImmType ImmT = Imm8; +} +class AVX512Ii8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, + Requires<[HasAVX512]>; +class AVX512PDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, + Requires<[HasAVX512]>; +class AVX512PSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, + Requires<[HasAVX512]>; +class AVX512PIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d> + : Ii8, Requires<[HasAVX512]>; +class AVX512PI o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d> + : I, Requires<[HasAVX512]>; +class AVX512FMA3S o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + EVEX_4V, Requires<[HasAVX512]>; + +class AVX512 o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, Requires<[HasAVX512]>; + +// AES Instruction Templates: +// +// AES8I +// These use the same encoding as the SSE4.2 T8 and TA encodings. +class AES8I o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + Requires<[NoAVX, HasAES]>; + +class AESAI o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TAPD, + Requires<[NoAVX, HasAES]>; + +// PCLMUL Instruction Templates +class PCLMULIi8 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8, TAPD; + +// FMA3 Instruction Templates +class FMA3 o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>; +class FMA3S o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>; +class FMA3S_Int o, Format F, dag outs, dag ins, string asm, + listpattern> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA, NoAVX512]>; + +// FMA4 Instruction Templates +class FMA4 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, FMASC, Requires<[HasFMA4, NoVLX]>; +class FMA4S o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, FMASC, Requires<[HasFMA4, NoAVX512]>; +class FMA4S_Int o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, FMASC, Requires<[HasFMA4]>; + +// XOP 2, 3 and 4 Operand Instruction Template +class IXOP o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, + XOP9, Requires<[HasXOP]>; + +// XOP 2 and 3 Operand Instruction Templates with imm byte +class IXOPi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, + XOP8, Requires<[HasXOP]>; +// XOP 4 Operand Instruction Templates with imm byte +class IXOPi8Reg o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8Reg, + XOP8, Requires<[HasXOP]>; + +// XOP 5 operand instruction (VEX encoding!) +class IXOP5 o, Format F, dag outs, dag ins, string asm, + listpattern> + : Ii8Reg, TAPD, + VEX_4V, Requires<[HasXOP]>; + +// X86-64 Instruction templates... +// + +class RI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, REX_W; +class RIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, REX_W; +class RIi16 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii16, REX_W; +class RIi32 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii32, REX_W; +class RIi32S o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii32S, REX_W; +class RIi64 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii64, REX_W; + +class RS2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : S2I, REX_W; +class VRS2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : VS2I, REX_W; + +// MMX Instruction templates +// + +// MMXI - MMX instructions with TB prefix. +// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. +// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. +// MMX2I - MMX / SSE2 instructions with PD prefix. +// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. +// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. +// MMXID - MMX instructions with XD prefix. +// MMXIS - MMX instructions with XS prefix. +class MMXI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, Requires<[HasMMX]>; +class MMXI32 o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, Requires<[HasMMX,Not64BitMode]>; +class MMXI64 o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, Requires<[HasMMX,In64BitMode]>; +class MMXRI o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PS, REX_W, + Requires<[HasMMX,In64BitMode]>; +class MMX2I o, Format F, dag outs, dag ins, string asm, + list pattern> + : I, PD, Requires<[HasMMX]>; +class MMXIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, PS, Requires<[HasMMX]>; +class MMXID o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XD, Requires<[HasMMX]>; +class MMXIS o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, XS, Requires<[HasMMX]>; + +/// ITy - This instruction base class takes the type info for the instruction. +/// Using this, it: +/// 1. Concatenates together the instruction mnemonic with the appropriate +/// suffix letter, a tab, and the arguments. +/// 2. Infers whether the instruction should have a 0x66 prefix byte. +/// 3. Infers whether the instruction should have a 0x40 REX_W prefix. +/// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations) +/// or 1 (for i16,i32,i64 operations). +class ITy opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins, + string mnemonic, string args, list pattern> + : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4}, + opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode }, + f, outs, ins, + !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> { + + // Infer instruction prefixes from type info. + let OpSize = typeinfo.OpSize; + let hasREX_W = typeinfo.HasREX_W; +} diff --git a/llvm/lib/Target/X86/X86InstrVMX.td b/llvm/lib/Target/X86/X86InstrVMX.td index cfeddbccccac..c601b1a97932 100644 --- a/llvm/lib/Target/X86/X86InstrVMX.td +++ b/llvm/lib/Target/X86/X86InstrVMX.td @@ -23,6 +23,11 @@ def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD, Requires<[In64BitMode]>; +let CD8_Scale = 0 in +def INVEPT64_EVEX : I<0xF0, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), + "invept\t{$src2, $src1|$src1, $src2}", []>, + EVEX, T_MAP4XS, Requires<[In64BitMode]>; + // 66 0F 38 81 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD, @@ -31,6 +36,11 @@ def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD, Requires<[In64BitMode]>; +let CD8_Scale = 0 in +def INVVPID64_EVEX : I<0xF1, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), + "invvpid\t{$src2, $src1|$src1, $src2}", []>, + EVEX, T_MAP4XS, Requires<[In64BitMode]>; + // 0F 01 C1 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB; def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), diff --git a/llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp b/llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp index e562748c98fe..3b370d8c3eb1 100644 --- a/llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp +++ b/llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp @@ -27,7 +27,6 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/IR/Function.h" #include "llvm/Support/Debug.h" -#include using namespace llvm; diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index 379a9d448a96..5c32519dab37 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -310,7 +310,8 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { return CSR_64_AllRegs_AVX_SaveList; return CSR_64_AllRegs_SaveList; case CallingConv::PreserveMost: - return CSR_64_RT_MostRegs_SaveList; + return IsWin64 ? CSR_Win64_RT_MostRegs_SaveList + : CSR_64_RT_MostRegs_SaveList; case CallingConv::PreserveAll: if (HasAVX) return CSR_64_RT_AllRegs_AVX_SaveList; @@ -431,7 +432,7 @@ X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF, return CSR_64_AllRegs_AVX_RegMask; return CSR_64_AllRegs_RegMask; case CallingConv::PreserveMost: - return CSR_64_RT_MostRegs_RegMask; + return IsWin64 ? CSR_Win64_RT_MostRegs_RegMask : CSR_64_RT_MostRegs_RegMask; case CallingConv::PreserveAll: if (HasAVX) return CSR_64_RT_AllRegs_AVX_RegMask; diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index b3dd4de2a769..80edad58985b 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -147,12 +147,7 @@ XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM, setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); - // Atomic operations - // We request a fence for ATOMIC_* instructions, to reduce them to Monotonic. - // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP. setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); - setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); - setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); // TRAMPOLINE is custom lowered. setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); @@ -171,6 +166,9 @@ XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM, setMinFunctionAlignment(Align(2)); setPrefFunctionAlignment(Align(4)); + + // This target doesn't implement native atomics. + setMaxAtomicSizeInBitsSupported(0); } bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { @@ -215,9 +213,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); - case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); - case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG); - case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op, DAG); + case ISD::ATOMIC_FENCE: + return LowerATOMIC_FENCE(Op, DAG); default: llvm_unreachable("unimplemented operand"); } @@ -928,88 +925,6 @@ LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { return DAG.getNode(ISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0)); } -SDValue XCoreTargetLowering:: -LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const { - AtomicSDNode *N = cast(Op); - assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP"); - assert((N->getSuccessOrdering() == AtomicOrdering::Unordered || - N->getSuccessOrdering() == AtomicOrdering::Monotonic) && - "shouldInsertFencesForAtomic(true) expects unordered / monotonic"); - if (N->getMemoryVT() == MVT::i32) { - if (N->getAlign() < Align(4)) - report_fatal_error("atomic load must be aligned"); - return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op), - N->getChain(), N->getBasePtr(), N->getPointerInfo(), - N->getAlign(), N->getMemOperand()->getFlags(), - N->getAAInfo(), N->getRanges()); - } - if (N->getMemoryVT() == MVT::i16) { - if (N->getAlign() < Align(2)) - report_fatal_error("atomic load must be aligned"); - return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), - N->getBasePtr(), N->getPointerInfo(), MVT::i16, - N->getAlign(), N->getMemOperand()->getFlags(), - N->getAAInfo()); - } - if (N->getMemoryVT() == MVT::i8) - return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), - N->getBasePtr(), N->getPointerInfo(), MVT::i8, - N->getAlign(), N->getMemOperand()->getFlags(), - N->getAAInfo()); - return SDValue(); -} - -SDValue XCoreTargetLowering:: -LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const { - AtomicSDNode *N = cast(Op); - assert(N->getOpcode() == ISD::ATOMIC_STORE && "Bad Atomic OP"); - assert((N->getSuccessOrdering() == AtomicOrdering::Unordered || - N->getSuccessOrdering() == AtomicOrdering::Monotonic) && - "shouldInsertFencesForAtomic(true) expects unordered / monotonic"); - if (N->getMemoryVT() == MVT::i32) { - if (N->getAlign() < Align(4)) - report_fatal_error("atomic store must be aligned"); - return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(), N->getBasePtr(), - N->getPointerInfo(), N->getAlign(), - N->getMemOperand()->getFlags(), N->getAAInfo()); - } - if (N->getMemoryVT() == MVT::i16) { - if (N->getAlign() < Align(2)) - report_fatal_error("atomic store must be aligned"); - return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(), - N->getBasePtr(), N->getPointerInfo(), MVT::i16, - N->getAlign(), N->getMemOperand()->getFlags(), - N->getAAInfo()); - } - if (N->getMemoryVT() == MVT::i8) - return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(), - N->getBasePtr(), N->getPointerInfo(), MVT::i8, - N->getAlign(), N->getMemOperand()->getFlags(), - N->getAAInfo()); - return SDValue(); -} - -MachineMemOperand::Flags -XCoreTargetLowering::getTargetMMOFlags(const Instruction &I) const { - // Because of how we convert atomic_load and atomic_store to normal loads and - // stores in the DAG, we need to ensure that the MMOs are marked volatile - // since DAGCombine hasn't been updated to account for atomic, but non - // volatile loads. (See D57601) - if (auto *SI = dyn_cast(&I)) - if (SI->isAtomic()) - return MachineMemOperand::MOVolatile; - if (auto *LI = dyn_cast(&I)) - if (LI->isAtomic()) - return MachineMemOperand::MOVolatile; - if (auto *AI = dyn_cast(&I)) - if (AI->isAtomic()) - return MachineMemOperand::MOVolatile; - if (auto *AI = dyn_cast(&I)) - if (AI->isAtomic()) - return MachineMemOperand::MOVolatile; - return MachineMemOperand::MONone; -} - //===----------------------------------------------------------------------===// // Calling Convention Implementation //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.h b/llvm/lib/Target/XCore/XCoreISelLowering.h index cfd0619cba8f..eaa36d40cba9 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.h +++ b/llvm/lib/Target/XCore/XCoreISelLowering.h @@ -181,11 +181,6 @@ namespace llvm { SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; - - MachineMemOperand::Flags getTargetMMOFlags( - const Instruction &I) const override; // Inline asm support std::pair @@ -219,14 +214,10 @@ namespace llvm { const SmallVectorImpl &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override; - bool - CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, - bool isVarArg, - const SmallVectorImpl &ArgsFlags, - LLVMContext &Context) const override; - bool shouldInsertFencesForAtomic(const Instruction *I) const override { - return true; - } + bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, + bool isVarArg, + const SmallVectorImpl &ArgsFlags, + LLVMContext &Context) const override; }; } diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp index 5fcb518cf37c..733f290b1bc9 100644 --- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp +++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp @@ -1467,9 +1467,19 @@ void LowerTypeTestsModule::createJumpTable( SmallVector AsmArgs; AsmArgs.reserve(Functions.size() * 2); - for (GlobalTypeMember *GTM : Functions) + // Check if all entries have the NoUnwind attribute. + // If all entries have it, we can safely mark the + // cfi.jumptable as NoUnwind, otherwise, direct calls + // to the jump table will not handle exceptions properly + bool areAllEntriesNounwind = true; + for (GlobalTypeMember *GTM : Functions) { + if (!llvm::cast(GTM->getGlobal()) + ->hasFnAttribute(llvm::Attribute::NoUnwind)) { + areAllEntriesNounwind = false; + } createJumpTableEntry(AsmOS, ConstraintOS, JumpTableArch, AsmArgs, cast(GTM->getGlobal())); + } // Align the whole table by entry size. F->setAlignment(Align(getJumpTableEntrySize())); @@ -1512,8 +1522,13 @@ void LowerTypeTestsModule::createJumpTable( // -fcf-protection=. if (JumpTableArch == Triple::x86 || JumpTableArch == Triple::x86_64) F->addFnAttr(Attribute::NoCfCheck); - // Make sure we don't emit .eh_frame for this function. - F->addFnAttr(Attribute::NoUnwind); + + // Make sure we don't emit .eh_frame for this function if it isn't needed. + if (areAllEntriesNounwind) + F->addFnAttr(Attribute::NoUnwind); + + // Make sure we do not inline any calls to the cfi.jumptable. + F->addFnAttr(Attribute::NoInline); BasicBlock *BB = BasicBlock::Create(M.getContext(), "entry", F); IRBuilder<> IRB(BB); diff --git a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp index 5ded0e69927c..85afc020dbf8 100644 --- a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp +++ b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp @@ -1264,7 +1264,8 @@ static bool AddCalls(VTableSlotInfo &SlotInfo, const ValueInfo &Callee) { // to better ensure we have the opportunity to inline them. bool IsExported = false; auto &S = Callee.getSummaryList()[0]; - CalleeInfo CI(CalleeInfo::HotnessType::Hot, /* RelBF = */ 0); + CalleeInfo CI(CalleeInfo::HotnessType::Hot, /* HasTailCall = */ false, + /* RelBF = */ 0); auto AddCalls = [&](CallSiteInfo &CSInfo) { for (auto *FS : CSInfo.SummaryTypeCheckedLoadUsers) { FS->addCall({Callee, CI}); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index 427558f30905..719a2678fc18 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -903,8 +903,7 @@ Instruction *InstCombinerImpl::foldAddWithConstant(BinaryOperator &Add) { // (X | Op01C) + Op1C --> X + (Op01C + Op1C) iff the `or` is actually an `add` Constant *Op01C; - if (match(Op0, m_Or(m_Value(X), m_ImmConstant(Op01C))) && - haveNoCommonBitsSet(X, Op01C, SQ.getWithInstruction(&Add))) + if (match(Op0, m_DisjointOr(m_Value(X), m_ImmConstant(Op01C)))) return BinaryOperator::CreateAdd(X, ConstantExpr::getAdd(Op01C, Op1C)); // (X | C2) + C --> (X | C2) ^ C2 iff (C2 == -C) @@ -1583,11 +1582,8 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) { // A+B --> A|B iff A and B have no bits set in common. WithCache LHSCache(LHS), RHSCache(RHS); - if (haveNoCommonBitsSet(LHSCache, RHSCache, SQ.getWithInstruction(&I))) { - auto *Or = BinaryOperator::CreateOr(LHS, RHS); - cast(Or)->setIsDisjoint(true); - return Or; - } + if (haveNoCommonBitsSet(LHSCache, RHSCache, SQ.getWithInstruction(&I))) + return BinaryOperator::CreateDisjointOr(LHS, RHS); if (Instruction *Ext = narrowMathIfNoOverflow(I)) return Ext; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 481fcdf18194..39466a9e3751 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -3393,9 +3393,8 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { // If the operands have no common bits set: // or (mul X, Y), X --> add (mul X, Y), X --> mul X, (Y + 1) - if (match(&I, - m_c_Or(m_OneUse(m_Mul(m_Value(X), m_Value(Y))), m_Deferred(X))) && - cast(I).isDisjoint()) { + if (match(&I, m_c_DisjointOr(m_OneUse(m_Mul(m_Value(X), m_Value(Y))), + m_Deferred(X)))) { Value *IncrementY = Builder.CreateAdd(Y, ConstantInt::get(Ty, 1)); return BinaryOperator::CreateMul(X, IncrementY); } @@ -4463,7 +4462,7 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) { Value *M; if (match(&I, m_c_Xor(m_c_And(m_Not(m_Value(M)), m_Value()), m_c_And(m_Deferred(M), m_Value())))) - return BinaryOperator::CreateOr(Op0, Op1); + return BinaryOperator::CreateDisjointOr(Op0, Op1); if (Instruction *Xor = visitMaskedMerge(I, Builder)) return Xor; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 1d09d9b44a9e..4295c7692e6d 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -12,6 +12,7 @@ #include "InstCombineInternal.h" #include "llvm/ADT/APSInt.h" +#include "llvm/ADT/ScopeExit.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/CaptureTracking.h" @@ -6113,13 +6114,19 @@ Instruction *InstCombinerImpl::foldICmpUsingKnownBits(ICmpInst &I) { KnownBits Op0Known(BitWidth); KnownBits Op1Known(BitWidth); - if (SimplifyDemandedBits(&I, 0, - getDemandedBitsLHSMask(I, BitWidth), - Op0Known, 0)) - return &I; + { + // Don't use dominating conditions when folding icmp using known bits. This + // may convert signed into unsigned predicates in ways that other passes + // (especially IndVarSimplify) may not be able to reliably undo. + SQ.DC = nullptr; + auto _ = make_scope_exit([&]() { SQ.DC = &DC; }); + if (SimplifyDemandedBits(&I, 0, getDemandedBitsLHSMask(I, BitWidth), + Op0Known, 0)) + return &I; - if (SimplifyDemandedBits(&I, 1, APInt::getAllOnes(BitWidth), Op1Known, 0)) - return &I; + if (SimplifyDemandedBits(&I, 1, APInt::getAllOnes(BitWidth), Op1Known, 0)) + return &I; + } // Given the known and unknown bits, compute a range that the LHS could be // in. Compute the Min, Max and RHS values based on the known bits. For the diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h index 0bbb22be7156..bb620ad8d41c 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h +++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h @@ -459,6 +459,7 @@ public: // use counts. SmallVector Ops(I.operands()); Worklist.remove(&I); + DC.removeValue(&I); I.eraseFromParent(); for (Value *Op : Ops) Worklist.handleUseCountDecrement(Op); @@ -739,13 +740,11 @@ class Negator final { using BuilderTy = IRBuilder; BuilderTy Builder; - const SimplifyQuery &SQ; - const bool IsTrulyNegation; SmallDenseMap NegationsCache; - Negator(LLVMContext &C, const SimplifyQuery &SQ, bool IsTrulyNegation); + Negator(LLVMContext &C, const DataLayout &DL, bool IsTrulyNegation); #if LLVM_ENABLE_STATS unsigned NumValuesVisitedInThisNegator = 0; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index 3b45138a8beb..588bb00462d2 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -300,9 +300,8 @@ Instruction *InstCombinerImpl::visitMul(BinaryOperator &I) { // Canonicalize (X|C1)*MulC -> X*MulC+C1*MulC. Value *X; Constant *C1; - if ((match(Op0, m_OneUse(m_Add(m_Value(X), m_ImmConstant(C1))))) || - (match(Op0, m_OneUse(m_Or(m_Value(X), m_ImmConstant(C1)))) && - haveNoCommonBitsSet(X, C1, SQ.getWithInstruction(&I)))) { + if (match(Op0, m_OneUse(m_Add(m_Value(X), m_ImmConstant(C1)))) || + match(Op0, m_OneUse(m_DisjointOr(m_Value(X), m_ImmConstant(C1))))) { // C1*MulC simplifies to a tidier constant. Value *NewC = Builder.CreateMul(C1, MulC); auto *BOp0 = cast(Op0); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp index 6e0b44c11f22..513b185c83a4 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp @@ -97,13 +97,13 @@ static cl::opt cl::desc("What is the maximal lookup depth when trying to " "check for viability of negation sinking.")); -Negator::Negator(LLVMContext &C, const SimplifyQuery &SQ, bool IsTrulyNegation_) - : Builder(C, TargetFolder(SQ.DL), +Negator::Negator(LLVMContext &C, const DataLayout &DL, bool IsTrulyNegation_) + : Builder(C, TargetFolder(DL), IRBuilderCallbackInserter([&](Instruction *I) { ++NegatorNumInstructionsCreatedTotal; NewInstructions.push_back(I); })), - SQ(SQ), IsTrulyNegation(IsTrulyNegation_) {} + IsTrulyNegation(IsTrulyNegation_) {} #if LLVM_ENABLE_STATS Negator::~Negator() { @@ -402,8 +402,7 @@ std::array Negator::getSortedOperandsOfBinOp(Instruction *I) { I->getName() + ".neg", /* HasNUW */ false, IsNSW); } case Instruction::Or: { - if (!haveNoCommonBitsSet(I->getOperand(0), I->getOperand(1), - SQ.getWithInstruction(I))) + if (!cast(I)->isDisjoint()) return nullptr; // Don't know how to handle `or` in general. std::array Ops = getSortedOperandsOfBinOp(I); // `or`/`add` are interchangeable when operands have no common bits set. @@ -539,7 +538,7 @@ std::array Negator::getSortedOperandsOfBinOp(Instruction *I) { if (!NegatorEnabled || !DebugCounter::shouldExecute(NegatorCounter)) return nullptr; - Negator N(Root->getContext(), IC.getSimplifyQuery(), LHSIsZero); + Negator N(Root->getContext(), IC.getDataLayout(), LHSIsZero); std::optional Res = N.run(Root, IsNSW); if (!Res) { // Negation failed. LLVM_DEBUG(dbgs() << "Negator: failed to sink negation into " << *Root diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index 732a3a13dacc..046ce9d1207e 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -315,6 +315,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.Zero)) { Instruction *Or = BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1)); + if (DemandedMask.isAllOnes()) + cast(Or)->setIsDisjoint(true); Or->takeName(I); return InsertNewInstWith(Or, I->getIterator()); } diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index 0f033a9adad7..30e058000d2b 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -3106,6 +3106,7 @@ Instruction *InstCombinerImpl::visitBranchInst(BranchInst &BI) { return nullptr; } + DC.registerBranch(&BI); return nullptr; } diff --git a/llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp b/llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp index 47af299dbd47..47f663fa0cf0 100644 --- a/llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp +++ b/llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp @@ -372,10 +372,10 @@ static void splitCallSite(CallBase &CB, return; } - auto *OriginalBegin = &*TailBB->begin(); + BasicBlock::iterator OriginalBegin = TailBB->begin(); // Replace users of the original call with a PHI mering call-sites split. if (CallPN) { - CallPN->insertBefore(OriginalBegin); + CallPN->insertBefore(*TailBB, OriginalBegin); CB.replaceAllUsesWith(CallPN); } @@ -387,6 +387,7 @@ static void splitCallSite(CallBase &CB, // do not introduce unnecessary PHI nodes for def-use chains from the call // instruction to the beginning of the block. auto I = CB.getReverseIterator(); + Instruction *OriginalBeginInst = &*OriginalBegin; while (I != TailBB->rend()) { Instruction *CurrentI = &*I++; if (!CurrentI->use_empty()) { @@ -399,13 +400,13 @@ static void splitCallSite(CallBase &CB, for (auto &Mapping : ValueToValueMaps) NewPN->addIncoming(Mapping[CurrentI], cast(Mapping[CurrentI])->getParent()); - NewPN->insertBefore(&*TailBB->begin()); + NewPN->insertBefore(*TailBB, TailBB->begin()); CurrentI->replaceAllUsesWith(NewPN); } CurrentI->dropDbgValues(); CurrentI->eraseFromParent(); // We are done once we handled the first original instruction in TailBB. - if (CurrentI == OriginalBegin) + if (CurrentI == OriginalBeginInst) break; } } diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp index 898f29f4b9ec..a6fbddca5cba 100644 --- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp +++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp @@ -544,10 +544,8 @@ static Decomposition decompose(Value *V, } // Decompose or as an add if there are no common bits between the operands. - if (match(V, m_Or(m_Value(Op0), m_ConstantInt(CI))) && - haveNoCommonBitsSet(Op0, CI, DL)) { + if (match(V, m_DisjointOr(m_Value(Op0), m_ConstantInt(CI)))) return MergeResults(Op0, CI, IsSigned); - } if (match(V, m_NUWShl(m_Value(Op1), m_ConstantInt(CI))) && canUseSExt(CI)) { if (CI->getSExtValue() < 0 || CI->getSExtValue() >= 64) diff --git a/llvm/lib/Transforms/Scalar/Reassociate.cpp b/llvm/lib/Transforms/Scalar/Reassociate.cpp index 0d55c72e407e..42e979db24d2 100644 --- a/llvm/lib/Transforms/Scalar/Reassociate.cpp +++ b/llvm/lib/Transforms/Scalar/Reassociate.cpp @@ -2256,9 +2256,10 @@ void ReassociatePass::OptimizeInst(Instruction *I) { // with no common bits set, convert it to X+Y. if (I->getOpcode() == Instruction::Or && shouldConvertOrWithNoCommonBitsToAdd(I) && !isLoadCombineCandidate(I) && - haveNoCommonBitsSet(I->getOperand(0), I->getOperand(1), - SimplifyQuery(I->getModule()->getDataLayout(), - /*DT=*/nullptr, /*AC=*/nullptr, I))) { + (cast(I)->isDisjoint() || + haveNoCommonBitsSet(I->getOperand(0), I->getOperand(1), + SimplifyQuery(I->getModule()->getDataLayout(), + /*DT=*/nullptr, /*AC=*/nullptr, I)))) { Instruction *NI = convertOrWithNoCommonBitsToAdd(I); RedoInsts.insert(I); MadeChange = true; @@ -2554,7 +2555,7 @@ ReassociatePass::BuildPairMap(ReversePostOrderTraversal &RPOT) { // Make a "pairmap" of how often each operand pair occurs. for (BasicBlock *BI : RPOT) { for (Instruction &I : *BI) { - if (!I.isAssociative()) + if (!I.isAssociative() || !I.isBinaryOp()) continue; // Ignore nodes that aren't at the root of trees. diff --git a/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp b/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp index 7b850f05bec1..c6e8505d5ab4 100644 --- a/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp +++ b/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp @@ -369,8 +369,14 @@ static bool canTransformAccumulatorRecursion(Instruction *I, CallInst *CI) { if (!I->isAssociative() || !I->isCommutative()) return false; - assert(I->getNumOperands() == 2 && - "Associative/commutative operations should have 2 args!"); + assert(I->getNumOperands() >= 2 && + "Associative/commutative operations should have at least 2 args!"); + + if (IntrinsicInst *II = dyn_cast(I)) { + // Accumulators must have an identity. + if (!ConstantExpr::getIntrinsicIdentity(II->getIntrinsicID(), I->getType())) + return false; + } // Exactly one operand should be the result of the call instruction. if ((I->getOperand(0) == CI && I->getOperand(1) == CI) || @@ -569,8 +575,8 @@ void TailRecursionEliminator::insertAccumulator(Instruction *AccRecInstr) { for (pred_iterator PI = PB; PI != PE; ++PI) { BasicBlock *P = *PI; if (P == &F.getEntryBlock()) { - Constant *Identity = ConstantExpr::getBinOpIdentity( - AccRecInstr->getOpcode(), AccRecInstr->getType()); + Constant *Identity = + ConstantExpr::getIdentity(AccRecInstr, AccRecInstr->getType()); AccPN->addIncoming(Identity, P); } else { AccPN->addIncoming(AccPN, P); diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index e399329a5887..51f39e0ba0cc 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -1295,7 +1295,7 @@ bool llvm::TryToSimplifyUncondBranchFromEmptyBlock(BasicBlock *BB, // the same predecessors BB had. // Copy over any phi, debug or lifetime instruction. BB->getTerminator()->eraseFromParent(); - Succ->splice(Succ->getFirstNonPHI()->getIterator(), BB); + Succ->splice(Succ->getFirstNonPHIIt(), BB); } else { while (PHINode *PN = dyn_cast(&BB->front())) { // We explicitly check for such uses for merging phis. @@ -2587,14 +2587,7 @@ static bool rewriteDebugUsers( } // DPValue implementation of the above. - // RemoveDIs misery: The above loop of intrinsic-users are ordered by the - // use-list of the corresponding metadata-as-value: in reverse order of when - // they were added. Wheras DPUsers are ordered by when they were added to - // the replaceable-metadata map, i.e., in the order they were added. Thus to - // have matching orders between the two, we have to reverse here. For - // RemoveDIs we might in the long run need to consider whether this implicit - // ordering is relied upon by any other part of LLVM. - for (auto *DPV : llvm::reverse(DPUsers)) { + for (auto *DPV : DPUsers) { Instruction *MarkedInstr = DPV->getMarker()->MarkedInstr; Instruction *NextNonDebug = MarkedInstr; // The next instruction might still be a dbg.declare, skip over it. diff --git a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp index cbef27d1ecfa..76280ed492b3 100644 --- a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp @@ -541,31 +541,31 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { // duplication. using DbgIntrinsicHash = std::pair, DIExpression *>; - auto makeHash = [](DbgVariableIntrinsic *D) -> DbgIntrinsicHash { + auto makeHash = [](auto *D) -> DbgIntrinsicHash { auto VarLocOps = D->location_ops(); return {{hash_combine_range(VarLocOps.begin(), VarLocOps.end()), D->getVariable()}, D->getExpression()}; }; + SmallDenseSet DbgIntrinsics; for (Instruction &I : llvm::drop_begin(llvm::reverse(*OrigPreheader))) { - if (auto *DII = dyn_cast(&I)) + if (auto *DII = dyn_cast(&I)) { DbgIntrinsics.insert(makeHash(DII)); - else + // Until RemoveDIs supports dbg.declares in DPValue format, we'll need + // to collect DPValues attached to any other debug intrinsics. + for (const DPValue &DPV : DII->getDbgValueRange()) + DbgIntrinsics.insert(makeHash(&DPV)); + } else { break; + } } - // Duplicate implementation for DPValues, the non-instruction format of - // debug-info records in RemoveDIs. - auto makeHashDPV = [](const DPValue &D) -> DbgIntrinsicHash { - auto VarLocOps = D.location_ops(); - return {{hash_combine_range(VarLocOps.begin(), VarLocOps.end()), - D.getVariable()}, - D.getExpression()}; - }; - for (Instruction &I : llvm::drop_begin(llvm::reverse(*OrigPreheader))) - for (const DPValue &DPV : I.getDbgValueRange()) - DbgIntrinsics.insert(makeHashDPV(DPV)); + // Build DPValue hashes for DPValues attached to the terminator, which isn't + // considered in the loop above. + for (const DPValue &DPV : + OrigPreheader->getTerminator()->getDbgValueRange()) + DbgIntrinsics.insert(makeHash(&DPV)); // Remember the local noalias scope declarations in the header. After the // rotation, they must be duplicated and the scope must be cloned. This @@ -616,6 +616,10 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { LoopEntryBranch->cloneDebugInfoFrom(Inst, NextDbgInst); RemapDPValueRange(M, DbgValueRange, ValueMap, RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); + // Erase anything we've seen before. + for (DPValue &DPV : make_early_inc_range(DbgValueRange)) + if (DbgIntrinsics.count(makeHash(&DPV))) + DPV.eraseFromParent(); } NextDbgInst = I->getDbgValueRange().begin(); @@ -633,13 +637,13 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat) { auto Range = C->cloneDebugInfoFrom(Inst, NextDbgInst); - // Erase anything we've seen before. - for (DPValue &DPV : make_early_inc_range(Range)) - if (DbgIntrinsics.count(makeHashDPV(DPV))) - DPV.eraseFromParent(); RemapDPValueRange(M, Range, ValueMap, RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); NextDbgInst = std::nullopt; + // Erase anything we've seen before. + for (DPValue &DPV : make_early_inc_range(Range)) + if (DbgIntrinsics.count(makeHash(&DPV))) + DPV.eraseFromParent(); } // Eagerly remap the operands of the instruction. diff --git a/llvm/lib/Transforms/Utils/ModuleUtils.cpp b/llvm/lib/Transforms/Utils/ModuleUtils.cpp index fc42df75875e..7de0959ca57e 100644 --- a/llvm/lib/Transforms/Utils/ModuleUtils.cpp +++ b/llvm/lib/Transforms/Utils/ModuleUtils.cpp @@ -346,7 +346,8 @@ void VFABI::setVectorVariantNames(CallInst *CI, #ifndef NDEBUG for (const std::string &VariantMapping : VariantMappings) { LLVM_DEBUG(dbgs() << "VFABI: adding mapping '" << VariantMapping << "'\n"); - std::optional VI = VFABI::tryDemangleForVFABI(VariantMapping, *CI); + std::optional VI = + VFABI::tryDemangleForVFABI(VariantMapping, CI->getFunctionType()); assert(VI && "Cannot add an invalid VFABI name."); assert(M->getNamedValue(VI->VectorName) && "Cannot add variant to attribute: " diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index d7a0a29d6ed5..c07e9f043b7b 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -8578,8 +8578,8 @@ VPRecipeBuilder::tryToCreateWidenRecipe(Instruction *Instr, } if (auto *CI = dyn_cast(Instr)) { - return toVPRecipeResult( - new VPWidenCastRecipe(CI->getOpcode(), Operands[0], CI->getType(), CI)); + return toVPRecipeResult(new VPWidenCastRecipe(CI->getOpcode(), Operands[0], + CI->getType(), *CI)); } return toVPRecipeResult(tryToWiden(Instr, Operands, VPBB, Plan)); diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index be48465b8e0e..a1e3e76ac852 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -5466,7 +5466,8 @@ BoUpSLP::TreeEntry::EntryState BoUpSLP::getScalarsVectorizationState( Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); VFShape Shape = VFShape::get( - *CI, ElementCount::getFixed(static_cast(VL.size())), + CI->getFunctionType(), + ElementCount::getFixed(static_cast(VL.size())), false /*HasGlobalPred*/); Function *VecFunc = VFDatabase(*CI).getVectorizedFunction(Shape); @@ -6461,8 +6462,8 @@ getVectorCallCosts(CallInst *CI, FixedVectorType *VecTy, auto IntrinsicCost = TTI->getIntrinsicInstrCost(CostAttrs, TTI::TCK_RecipThroughput); - auto Shape = VFShape::get(*CI, ElementCount::getFixed(static_cast( - VecTy->getNumElements())), + auto Shape = VFShape::get(CI->getFunctionType(), + ElementCount::getFixed(VecTy->getNumElements()), false /*HasGlobalPred*/); Function *VecFunc = VFDatabase(*CI).getVectorizedFunction(Shape); auto LibCost = IntrinsicCost; @@ -9383,7 +9384,8 @@ BoUpSLP::isGatherShuffledSingleRegisterEntry( continue; // If the user instruction is used for some reason in different // vectorized nodes - make it depend on index. - if (TEUseEI.UserTE != UseEI.UserTE && TE->Idx < TEPtr->Idx) + if (TEUseEI.UserTE != UseEI.UserTE && + TEUseEI.UserTE->Idx < UseEI.UserTE->Idx) continue; } @@ -11643,8 +11645,9 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { Function *CF; if (!UseIntrinsic) { VFShape Shape = - VFShape::get(*CI, ElementCount::getFixed(static_cast( - VecTy->getNumElements())), + VFShape::get(CI->getFunctionType(), + ElementCount::getFixed( + static_cast(VecTy->getNumElements())), false /*HasGlobalPred*/); CF = VFDatabase(*CI).getVectorizedFunction(Shape); } else { diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index 639c2ac685a6..900245220448 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -826,9 +826,11 @@ class VPRecipeWithIRFlags : public VPRecipeBase { enum class OperationType : unsigned char { Cmp, OverflowingBinOp, + DisjointOp, PossiblyExactOp, GEPOp, FPMathOp, + NonNegOp, Other }; @@ -841,12 +843,18 @@ public: }; private: + struct DisjointFlagsTy { + char IsDisjoint : 1; + }; struct ExactFlagsTy { char IsExact : 1; }; struct GEPFlagsTy { char IsInBounds : 1; }; + struct NonNegFlagsTy { + char NonNeg : 1; + }; struct FastMathFlagsTy { char AllowReassoc : 1; char NoNaNs : 1; @@ -864,8 +872,10 @@ private: union { CmpInst::Predicate CmpPredicate; WrapFlagsTy WrapFlags; + DisjointFlagsTy DisjointFlags; ExactFlagsTy ExactFlags; GEPFlagsTy GEPFlags; + NonNegFlagsTy NonNegFlags; FastMathFlagsTy FMFs; unsigned AllFlags; }; @@ -884,6 +894,9 @@ public: if (auto *Op = dyn_cast(&I)) { OpType = OperationType::Cmp; CmpPredicate = Op->getPredicate(); + } else if (auto *Op = dyn_cast(&I)) { + OpType = OperationType::DisjointOp; + DisjointFlags.IsDisjoint = Op->isDisjoint(); } else if (auto *Op = dyn_cast(&I)) { OpType = OperationType::OverflowingBinOp; WrapFlags = {Op->hasNoUnsignedWrap(), Op->hasNoSignedWrap()}; @@ -893,6 +906,9 @@ public: } else if (auto *GEP = dyn_cast(&I)) { OpType = OperationType::GEPOp; GEPFlags.IsInBounds = GEP->isInBounds(); + } else if (auto *PNNI = dyn_cast(&I)) { + OpType = OperationType::NonNegOp; + NonNegFlags.NonNeg = PNNI->hasNonNeg(); } else if (auto *Op = dyn_cast(&I)) { OpType = OperationType::FPMathOp; FMFs = Op->getFastMathFlags(); @@ -921,6 +937,7 @@ public: return R->getVPDefID() == VPRecipeBase::VPInstructionSC || R->getVPDefID() == VPRecipeBase::VPWidenSC || R->getVPDefID() == VPRecipeBase::VPWidenGEPSC || + R->getVPDefID() == VPRecipeBase::VPWidenCastSC || R->getVPDefID() == VPRecipeBase::VPReplicateSC; } @@ -933,6 +950,9 @@ public: WrapFlags.HasNUW = false; WrapFlags.HasNSW = false; break; + case OperationType::DisjointOp: + DisjointFlags.IsDisjoint = false; + break; case OperationType::PossiblyExactOp: ExactFlags.IsExact = false; break; @@ -943,6 +963,9 @@ public: FMFs.NoNaNs = false; FMFs.NoInfs = false; break; + case OperationType::NonNegOp: + NonNegFlags.NonNeg = false; + break; case OperationType::Cmp: case OperationType::Other: break; @@ -956,6 +979,9 @@ public: I->setHasNoUnsignedWrap(WrapFlags.HasNUW); I->setHasNoSignedWrap(WrapFlags.HasNSW); break; + case OperationType::DisjointOp: + cast(I)->setIsDisjoint(DisjointFlags.IsDisjoint); + break; case OperationType::PossiblyExactOp: I->setIsExact(ExactFlags.IsExact); break; @@ -971,6 +997,9 @@ public: I->setHasAllowContract(FMFs.AllowContract); I->setHasApproxFunc(FMFs.ApproxFunc); break; + case OperationType::NonNegOp: + I->setNonNeg(NonNegFlags.NonNeg); + break; case OperationType::Cmp: case OperationType::Other: break; @@ -1177,7 +1206,7 @@ public: }; /// VPWidenCastRecipe is a recipe to create vector cast instructions. -class VPWidenCastRecipe : public VPRecipeBase, public VPValue { +class VPWidenCastRecipe : public VPRecipeWithIRFlags, public VPValue { /// Cast instruction opcode. Instruction::CastOps Opcode; @@ -1186,15 +1215,19 @@ class VPWidenCastRecipe : public VPRecipeBase, public VPValue { public: VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy, - CastInst *UI = nullptr) - : VPRecipeBase(VPDef::VPWidenCastSC, Op), VPValue(this, UI), + CastInst &UI) + : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, UI), VPValue(this, &UI), Opcode(Opcode), ResultTy(ResultTy) { - assert((!UI || UI->getOpcode() == Opcode) && + assert(UI.getOpcode() == Opcode && "opcode of underlying cast doesn't match"); - assert((!UI || UI->getType() == ResultTy) && + assert(UI.getType() == ResultTy && "result type of underlying cast doesn't match"); } + VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy) + : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op), VPValue(this, nullptr), + Opcode(Opcode), ResultTy(ResultTy) {} + ~VPWidenCastRecipe() override = default; VP_CLASSOF_IMPL(VPDef::VPWidenCastSC) diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index f73487ffb6a7..1891b211a356 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -635,6 +635,10 @@ void VPRecipeWithIRFlags::printFlags(raw_ostream &O) const { case OperationType::Cmp: O << " " << CmpInst::getPredicateName(getPredicate()); break; + case OperationType::DisjointOp: + if (DisjointFlags.IsDisjoint) + O << " disjoint"; + break; case OperationType::PossiblyExactOp: if (ExactFlags.IsExact) O << " exact"; @@ -652,6 +656,10 @@ void VPRecipeWithIRFlags::printFlags(raw_ostream &O) const { if (GEPFlags.IsInBounds) O << " inbounds"; break; + case OperationType::NonNegOp: + if (NonNegFlags.NonNeg) + O << " nneg"; + break; case OperationType::Other: break; } diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index 2baaf08cd054..ea90ed4a21b1 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -81,7 +81,7 @@ void VPlanTransforms::VPInstructionsToVPRecipes( NewRecipe = new VPWidenSelectRecipe(*SI, Ingredient.operands()); } else if (auto *CI = dyn_cast(Inst)) { NewRecipe = new VPWidenCastRecipe( - CI->getOpcode(), Ingredient.getOperand(0), CI->getType(), CI); + CI->getOpcode(), Ingredient.getOperand(0), CI->getType(), *CI); } else { NewRecipe = new VPWidenRecipe(*Inst, Ingredient.operands()); } diff --git a/llvm/lib/XRay/BlockVerifier.cpp b/llvm/lib/XRay/BlockVerifier.cpp index 9fb49fa9a860..99f255ea6688 100644 --- a/llvm/lib/XRay/BlockVerifier.cpp +++ b/llvm/lib/XRay/BlockVerifier.cpp @@ -8,6 +8,8 @@ #include "llvm/XRay/BlockVerifier.h" #include "llvm/Support/Error.h" +#include + namespace llvm { namespace xray { namespace { diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll index a0cbd740e473..457b00dea4bb 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll @@ -33,7 +33,7 @@ for.body: ; preds = %for.body.lr.ph, %fo %1 = load half, ptr %arrayidx2, align 4 %add3 = fadd fast half %1, %mul store half %add3, ptr %arrayidx2, align 4 - %add4 = or i32 %i.073, 1 + %add4 = or disjoint i32 %i.073, 1 %arrayidx5 = getelementptr inbounds [120 x half], ptr @src, i32 0, i32 %add4 %2 = load half, ptr %arrayidx5, align 4 %mul6 = fmul fast half %2, %k @@ -41,7 +41,7 @@ for.body: ; preds = %for.body.lr.ph, %fo %3 = load half, ptr %arrayidx8, align 4 %add9 = fadd fast half %3, %mul6 store half %add9, ptr %arrayidx8, align 4 - %add10 = or i32 %i.073, 2 + %add10 = or disjoint i32 %i.073, 2 %arrayidx11 = getelementptr inbounds [120 x half], ptr @src, i32 0, i32 %add10 %4 = load half, ptr %arrayidx11, align 4 %mul12 = fmul fast half %4, %k @@ -49,7 +49,7 @@ for.body: ; preds = %for.body.lr.ph, %fo %5 = load half, ptr %arrayidx14, align 4 %add15 = fadd fast half %5, %mul12 store half %add15, ptr %arrayidx14, align 4 - %add16 = or i32 %i.073, 3 + %add16 = or disjoint i32 %i.073, 3 %arrayidx17 = getelementptr inbounds [120 x half], ptr @src, i32 0, i32 %add16 %6 = load half, ptr %arrayidx17, align 4 %mul18 = fmul fast half %6, %k @@ -57,7 +57,7 @@ for.body: ; preds = %for.body.lr.ph, %fo %7 = load half, ptr %arrayidx20, align 4 %add21 = fadd fast half %7, %mul18 store half %add21, ptr %arrayidx20, align 4 - %add22 = or i32 %i.073, 4 + %add22 = or disjoint i32 %i.073, 4 %arrayidx23 = getelementptr inbounds [120 x half], ptr @src, i32 0, i32 %add22 %8 = load half, ptr %arrayidx23, align 4 %mul24 = fmul fast half %8, %k @@ -65,7 +65,7 @@ for.body: ; preds = %for.body.lr.ph, %fo %9 = load half, ptr %arrayidx26, align 4 %add27 = fadd fast half %9, %mul24 store half %add27, ptr %arrayidx26, align 4 - %add28 = or i32 %i.073, 5 + %add28 = or disjoint i32 %i.073, 5 %arrayidx29 = getelementptr inbounds [120 x half], ptr @src, i32 0, i32 %add28 %10 = load half, ptr %arrayidx29, align 4 %mul30 = fmul fast half %10, %k @@ -73,7 +73,7 @@ for.body: ; preds = %for.body.lr.ph, %fo %11 = load half, ptr %arrayidx32, align 4 %add33 = fadd fast half %11, %mul30 store half %add33, ptr %arrayidx32, align 4 - %add34 = or i32 %i.073, 6 + %add34 = or disjoint i32 %i.073, 6 %arrayidx35 = getelementptr inbounds [120 x half], ptr @src, i32 0, i32 %add34 %12 = load half, ptr %arrayidx35, align 4 %mul36 = fmul fast half %12, %k @@ -81,7 +81,7 @@ for.body: ; preds = %for.body.lr.ph, %fo %13 = load half, ptr %arrayidx38, align 4 %add39 = fadd fast half %13, %mul36 store half %add39, ptr %arrayidx38, align 4 - %add40 = or i32 %i.073, 7 + %add40 = or disjoint i32 %i.073, 7 %arrayidx41 = getelementptr inbounds [120 x half], ptr @src, i32 0, i32 %add40 %14 = load half, ptr %arrayidx41, align 4 %mul42 = fmul fast half %14, %k diff --git a/llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll b/llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll index d42e43173d25..e867e5f5bcfc 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll @@ -51,7 +51,7 @@ for.body: %i1 = shl nuw nsw i64 %indvars.iv, 2 %arrayidx2 = getelementptr inbounds i16, ptr %points, i64 %i1 %i2 = load i16, ptr %arrayidx2, align 2 - %i3 = or i64 %i1, 1 + %i3 = or disjoint i64 %i1, 1 %arrayidx7 = getelementptr inbounds i16, ptr %points, i64 %i3 %i4 = load i16, ptr %arrayidx7, align 2 %arrayidx = getelementptr inbounds i16, ptr %x, i64 %indvars.iv @@ -113,7 +113,7 @@ for.body: %i1 = shl nuw nsw i64 %indvars.iv, 2 %arrayidx2 = getelementptr inbounds i16, ptr %points, i64 %i1 %i2 = load i16, ptr %arrayidx2, align 2 - %i3 = or i64 %i1, 1 + %i3 = or disjoint i64 %i1, 1 %arrayidx7 = getelementptr inbounds i16, ptr %points, i64 %i3 %i4 = load i16, ptr %arrayidx7, align 2 %arrayidx = getelementptr inbounds i16, ptr %x, i64 %indvars.iv diff --git a/llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll b/llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll index 171b8d032e9c..741dd0746b74 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll @@ -55,7 +55,7 @@ for.body: store i16 %0, ptr %arrayidx2, align 2 %arrayidx4 = getelementptr inbounds i16, ptr %y, i64 %indvars.iv %2 = load i16, ptr %arrayidx4, align 2 - %3 = or i64 %1, 1 + %3 = or disjoint i64 %1, 1 %arrayidx7 = getelementptr inbounds i16, ptr %points, i64 %3 store i16 %2, ptr %arrayidx7, align 2 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 @@ -117,7 +117,7 @@ for.body: store i16 %0, ptr %arrayidx2, align 2 %arrayidx4 = getelementptr inbounds i16, ptr %y, i64 %indvars.iv %2 = load i16, ptr %arrayidx4, align 2 - %3 = or i64 %1, 1 + %3 = or disjoint i64 %1, 1 %arrayidx7 = getelementptr inbounds i16, ptr %points, i64 %3 store i16 %2, ptr %arrayidx7, align 2 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 diff --git a/llvm/test/Analysis/DependenceAnalysis/ExactRDIV.ll b/llvm/test/Analysis/DependenceAnalysis/ExactRDIV.ll index 1c7bcda1c7b1..4aa2458dcd8c 100644 --- a/llvm/test/Analysis/DependenceAnalysis/ExactRDIV.ll +++ b/llvm/test/Analysis/DependenceAnalysis/ExactRDIV.ll @@ -40,7 +40,7 @@ for.body4: ; preds = %for.body4.preheader %j.02 = phi i64 [ %inc9, %for.body4 ], [ 0, %for.body4.preheader ] %B.addr.01 = phi ptr [ %incdec.ptr, %for.body4 ], [ %B, %for.body4.preheader ] %mul5 = shl nsw i64 %j.02, 1 - %add64 = or i64 %mul5, 1 + %add64 = or disjoint i64 %mul5, 1 %arrayidx7 = getelementptr inbounds i32, ptr %A, i64 %add64 %0 = load i32, ptr %arrayidx7, align 4 %incdec.ptr = getelementptr inbounds i32, ptr %B.addr.01, i64 1 diff --git a/llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll b/llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll index 9a76154ce4e5..7822e61cf3aa 100644 --- a/llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll +++ b/llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll @@ -29,7 +29,7 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds i32, ptr %A, i64 %add store i32 %conv, ptr %arrayidx, align 4 %mul = shl i64 %i.02, 1 - %add13 = or i64 %mul, 1 + %add13 = or disjoint i64 %mul, 1 %arrayidx2 = getelementptr inbounds i32, ptr %A, i64 %add13 %0 = load i32, ptr %arrayidx2, align 4 %incdec.ptr = getelementptr inbounds i32, ptr %B.addr.01, i64 1 @@ -68,7 +68,7 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds i32, ptr %A, i64 %add store i32 %conv, ptr %arrayidx, align 4 %mul1 = shl i64 %i.02, 1 - %add23 = or i64 %mul1, 1 + %add23 = or disjoint i64 %mul1, 1 %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %add23 %0 = load i32, ptr %arrayidx3, align 4 %incdec.ptr = getelementptr inbounds i32, ptr %B.addr.01, i64 1 diff --git a/llvm/test/Analysis/DependenceAnalysis/GCD.ll b/llvm/test/Analysis/DependenceAnalysis/GCD.ll index 898158d983b2..f4890a269606 100644 --- a/llvm/test/Analysis/DependenceAnalysis/GCD.ll +++ b/llvm/test/Analysis/DependenceAnalysis/GCD.ll @@ -93,7 +93,7 @@ for.body3: ; preds = %for.cond1.preheader %mul5 = mul nsw i64 %i.03, 6 %mul6 = shl nsw i64 %j.02, 3 %add = add nsw i64 %mul5, %mul6 - %add7 = or i64 %add, 1 + %add7 = or disjoint i64 %add, 1 %arrayidx8 = getelementptr inbounds i32, ptr %A, i64 %add7 %0 = load i32, ptr %arrayidx8, align 4 %incdec.ptr = getelementptr inbounds i32, ptr %B.addr.11, i64 1 @@ -142,7 +142,7 @@ for.body3: ; preds = %for.cond1.preheader %mul = shl nsw i64 %i.03, 1 %mul4 = shl nsw i64 %j.02, 2 %sub = sub nsw i64 %mul, %mul4 - %add5 = or i64 %sub, 1 + %add5 = or disjoint i64 %sub, 1 %arrayidx = getelementptr inbounds i32, ptr %A, i64 %add5 store i32 %conv, ptr %arrayidx, align 4 %mul5 = mul nsw i64 %i.03, 6 @@ -384,7 +384,7 @@ for.body3: ; preds = %for.body3.preheader %arrayidx5 = getelementptr inbounds i32, ptr %A, i64 %arrayidx.sum store i32 %conv, ptr %arrayidx5, align 4 %mul6 = mul nsw i64 %j.03, 6 - %add7 = or i64 %mul6, 1 + %add7 = or disjoint i64 %mul6, 1 %mul7 = shl nsw i64 %i.06, 3 %1 = mul nsw i64 %mul7, %n %arrayidx8.sum = add i64 %1, %add7 @@ -464,7 +464,7 @@ for.body3: ; preds = %for.body3.preheader store i32 %7, ptr %arrayidx6, align 4 %8 = trunc i64 %indvars.iv to i32 %mul7 = mul nsw i32 %8, 6 - %add7 = or i32 %mul7, 1 + %add7 = or disjoint i32 %mul7, 1 %idxprom8 = sext i32 %add7 to i64 %9 = trunc i64 %indvars.iv8 to i32 %mul9 = shl nsw i32 %9, 3 @@ -548,7 +548,7 @@ for.body3: ; preds = %for.body3.preheader %4 = trunc i64 %indvars.iv to i32 %mul8 = mul nsw i32 %4, 6 %add9 = add nsw i32 %mul7, %mul8 - %add10 = or i32 %add9, 1 + %add10 = or disjoint i32 %add9, 1 %idxprom11 = sext i32 %add10 to i64 %arrayidx12 = getelementptr inbounds i32, ptr %A, i64 %idxprom11 %5 = load i32, ptr %arrayidx12, align 4 @@ -627,7 +627,7 @@ for.body3: ; preds = %for.body3.preheader store i32 %7, ptr %arrayidx6, align 4 %8 = trunc i64 %indvars.iv to i32 %mul7 = mul i32 %8, 6 - %add7 = or i32 %mul7, 1 + %add7 = or disjoint i32 %mul7, 1 %idxprom8 = zext i32 %add7 to i64 %9 = trunc i64 %indvars.iv8 to i32 %mul9 = shl i32 %9, 3 diff --git a/llvm/test/Analysis/LoopAccessAnalysis/forward-negative-step.ll b/llvm/test/Analysis/LoopAccessAnalysis/forward-negative-step.ll index 35e2109ab744..46e81cd74ab3 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/forward-negative-step.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/forward-negative-step.ll @@ -3,8 +3,6 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" -; FIXME: This should be vectorizable - ; void vectorizable_Read_Write(int *A) { ; for (unsigned i = 1022; i >= 0; i--) ; A[i+1] = A[i] + 1; @@ -13,10 +11,9 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" define void @vectorizable_Read_Write(ptr nocapture %A) { ; CHECK-LABEL: 'vectorizable_Read_Write' ; CHECK-NEXT: loop: -; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop -; CHECK-NEXT: Forward loop carried data dependence that prevents store-to-load forwarding. +; CHECK-NEXT: Memory dependences are safe ; CHECK-NEXT: Dependences: -; CHECK-NEXT: ForwardButPreventsForwarding: +; CHECK-NEXT: Forward: ; CHECK-NEXT: %l = load i32, ptr %gep.A, align 4 -> ; CHECK-NEXT: store i32 %add, ptr %gep.A.plus.1, align 4 ; CHECK-EMPTY: @@ -47,13 +44,13 @@ exit: ret void } -; FIXME: There's a forward dependency that prevents forwarding here. define void @neg_step_ForwardButPreventsForwarding(ptr nocapture %A, ptr noalias %B) { ; CHECK-LABEL: 'neg_step_ForwardButPreventsForwarding' ; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe +; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop +; CHECK-NEXT: Forward loop carried data dependence that prevents store-to-load forwarding. ; CHECK-NEXT: Dependences: -; CHECK-NEXT: Forward: +; CHECK-NEXT: ForwardButPreventsForwarding: ; CHECK-NEXT: store i32 0, ptr %gep.A, align 4 -> ; CHECK-NEXT: %l = load i32, ptr %gep.A.plus.1, align 4 ; CHECK-EMPTY: diff --git a/llvm/test/Analysis/LoopAccessAnalysis/print-order.ll b/llvm/test/Analysis/LoopAccessAnalysis/print-order.ll new file mode 100644 index 000000000000..65f94a7d8fdb --- /dev/null +++ b/llvm/test/Analysis/LoopAccessAnalysis/print-order.ll @@ -0,0 +1,65 @@ +; REQUIRES: asserts +; RUN: opt -passes='print' -debug-only=loop-accesses -disable-output < %s 2>&1 | FileCheck %s + +; void negative_step(int *A) { +; for (int i = 1022; i >= 0; i--) +; A[i+1] = A[i] + 1; +; } + +; CHECK: LAA: Found a loop in negative_step: loop +; CHECK: LAA: Checking memory dependencies +; CHECK-NEXT: LAA: Src Scev: {(4092 + %A),+,-4}<%loop>Sink Scev: {(4088 + %A),+,-4}<%loop>(Induction step: -1) +; CHECK-NEXT: LAA: Distance for store i32 %add, ptr %gep.A.plus.1, align 4 to %l = load i32, ptr %gep.A, align 4: -4 +; CHECK-NEXT: LAA: Dependence is negative + +define void @negative_step(ptr nocapture %A) { +entry: + %A.plus.1 = getelementptr i32, ptr %A, i64 1 + br label %loop + +loop: + %iv = phi i64 [ 1022, %entry ], [ %iv.next, %loop ] + %gep.A = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep.A, align 4 + %add = add nsw i32 %l, 1 + %gep.A.plus.1 = getelementptr i32, ptr %A.plus.1, i64 %iv + store i32 %add, ptr %gep.A.plus.1, align 4 + %iv.next = add nsw i64 %iv, -1 + %cmp.not = icmp eq i64 %iv, 0 + br i1 %cmp.not, label %exit, label %loop + +exit: + ret void +} + +; void positive_step(int *A) { +; for (int i = 1; i < 1024; i++) +; A[i-1] = A[i] + 1; +; } + +; CHECK: LAA: Found a loop in positive_step: loop +; CHECK: LAA: Checking memory dependencies +; CHECK-NEXT: LAA: Src Scev: {(4 + %A),+,4}<%loop>Sink Scev: {%A,+,4}<%loop>(Induction step: 1) +; CHECK-NEXT: LAA: Distance for %l = load i32, ptr %gep.A, align 4 to store i32 %add, ptr %gep.A.minus.1, align 4: -4 +; CHECK-NEXT: LAA: Dependence is negative + +define void @positive_step(ptr nocapture %A) { +entry: + %A.minus.1 = getelementptr i32, ptr %A, i64 -1 + br label %loop + +loop: + %iv = phi i64 [ 1, %entry ], [ %iv.next, %loop ] + %gep.A = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep.A, align 4 + %add = add nsw i32 %l, 1 + %gep.A.minus.1 = getelementptr i32, ptr %A.minus.1, i64 %iv + store i32 %add, ptr %gep.A.minus.1, align 4 + %iv.next = add nsw i64 %iv, 1 + %cmp.not = icmp eq i64 %iv, 1024 + br i1 %cmp.not, label %exit, label %loop + +exit: + ret void +} + diff --git a/llvm/test/Analysis/LoopAccessAnalysis/stride-access-dependence.ll b/llvm/test/Analysis/LoopAccessAnalysis/stride-access-dependence.ll index 145117a712ac..bfdd15f170d0 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/stride-access-dependence.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/stride-access-dependence.ll @@ -65,7 +65,7 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv %0 = trunc i64 %indvars.iv to i32 store i32 %0, ptr %arrayidx, align 4 - %1 = or i64 %indvars.iv, 3 + %1 = or disjoint i64 %indvars.iv, 3 %arrayidx2 = getelementptr inbounds i32, ptr %A, i64 %1 %2 = load i32, ptr %arrayidx2, align 4 %add3 = add nsw i32 %2, %sum.013 @@ -99,7 +99,7 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv %0 = trunc i64 %indvars.iv to i32 store i32 %0, ptr %arrayidx, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %1 %2 = trunc i64 %1 to i32 store i32 %2, ptr %arrayidx3, align 4 @@ -213,7 +213,7 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv %0 = trunc i64 %indvars.iv to i32 store i32 %0, ptr %arrayidx, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 2 %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv.next %2 = trunc i64 %1 to i32 @@ -328,7 +328,7 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv %0 = trunc i64 %indvars.iv to i32 store i32 %0, ptr %arrayidx, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds i32, ptr %add.ptr, i64 %indvars.iv %2 = trunc i64 %1 to i32 store i32 %2, ptr %arrayidx2, align 4 @@ -525,7 +525,7 @@ for.body: ; preds = %entry, %for.body %0 = trunc i64 %indvars.iv to i32 %arrayidx2 = getelementptr inbounds i32, ptr %incdec.ptr, i64 %indvars.iv store i32 %0, ptr %arrayidx2, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx5 = getelementptr inbounds i32, ptr %A, i64 %1 %2 = trunc i64 %1 to i32 store i32 %2, ptr %arrayidx5, align 4 diff --git a/llvm/test/Analysis/ScalarEvolution/add-like-or.ll b/llvm/test/Analysis/ScalarEvolution/add-like-or.ll index 38b6c44fdf35..86bb9058832b 100644 --- a/llvm/test/Analysis/ScalarEvolution/add-like-or.ll +++ b/llvm/test/Analysis/ScalarEvolution/add-like-or.ll @@ -6,15 +6,49 @@ define i8 @or-of-constant-with-no-common-bits-set(i8 %x, i8 %y) { ; CHECK-NEXT: Classifying expressions for: @or-of-constant-with-no-common-bits-set ; CHECK-NEXT: %t0 = shl i8 %x, 2 ; CHECK-NEXT: --> (4 * %x) U: [0,-3) S: [-128,125) -; CHECK-NEXT: %r = or i8 %t0, 3 +; CHECK-NEXT: %r = or disjoint i8 %t0, 3 ; CHECK-NEXT: --> (3 + (4 * %x)) U: [3,0) S: [-125,-128) ; CHECK-NEXT: Determining loop execution counts for: @or-of-constant-with-no-common-bits-set ; %t0 = shl i8 %x, 2 - %r = or i8 %t0, 3 + %r = or disjoint i8 %t0, 3 ret i8 %r } +define i8 @or-disjoint(i8 %x, i8 %y) { +; CHECK-LABEL: 'or-disjoint' +; CHECK-NEXT: Classifying expressions for: @or-disjoint +; CHECK-NEXT: %or = or disjoint i8 %x, %y +; CHECK-NEXT: --> (%x + %y) U: full-set S: full-set +; CHECK-NEXT: Determining loop execution counts for: @or-disjoint +; + %or = or disjoint i8 %x, %y + ret i8 %or +} + +define i8 @or-no-disjoint(i8 %x, i8 %y) { +; CHECK-LABEL: 'or-no-disjoint' +; CHECK-NEXT: Classifying expressions for: @or-no-disjoint +; CHECK-NEXT: %or = or i8 %x, %y +; CHECK-NEXT: --> %or U: full-set S: full-set +; CHECK-NEXT: Determining loop execution counts for: @or-no-disjoint +; + %or = or i8 %x, %y + ret i8 %or +} + +; FIXME: We could add nuw nsw flags here. +define noundef i8 @or-disjoint-transfer-flags(i8 %x, i8 %y) { +; CHECK-LABEL: 'or-disjoint-transfer-flags' +; CHECK-NEXT: Classifying expressions for: @or-disjoint-transfer-flags +; CHECK-NEXT: %or = or disjoint i8 %x, %y +; CHECK-NEXT: --> (%x + %y) U: full-set S: full-set +; CHECK-NEXT: Determining loop execution counts for: @or-disjoint-transfer-flags +; + %or = or disjoint i8 %x, %y + ret i8 %or +} + define void @mask-high(i64 %arg, ptr dereferenceable(4) %arg1) { ; CHECK-LABEL: 'mask-high' ; CHECK-NEXT: Classifying expressions for: @mask-high @@ -24,7 +58,7 @@ define void @mask-high(i64 %arg, ptr dereferenceable(4) %arg1) { ; CHECK-NEXT: --> (sext i32 %i to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648) ; CHECK-NEXT: %i3 = and i64 %arg, -16 ; CHECK-NEXT: --> (16 * (%arg /u 16)) U: [0,-15) S: [-9223372036854775808,9223372036854775793) -; CHECK-NEXT: %i4 = or i64 1, %i3 +; CHECK-NEXT: %i4 = or disjoint i64 1, %i3 ; CHECK-NEXT: --> (1 + (16 * (%arg /u 16))) U: [1,-14) S: [-9223372036854775807,9223372036854775794) ; CHECK-NEXT: %i7 = phi i64 [ %i4, %bb ], [ %i8, %bb6 ] ; CHECK-NEXT: --> {(1 + (16 * (%arg /u 16))),+,1}<%bb6> U: full-set S: full-set Exits: ((sext i32 %i to i64) smax (1 + (16 * (%arg /u 16)))) LoopDispositions: { %bb6: Computable } @@ -42,7 +76,7 @@ bb: %i = load i32, ptr %arg1, align 4 %i2 = sext i32 %i to i64 %i3 = and i64 %arg, -16 - %i4 = or i64 1, %i3 + %i4 = or disjoint i64 1, %i3 %i5 = icmp sgt i64 %i4, %i2 br i1 %i5, label %bb10, label %bb6 diff --git a/llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll b/llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll index bc308f258dd1..60809fcf31de 100644 --- a/llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll +++ b/llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll @@ -25,7 +25,7 @@ define void @foo(i32 %no, ptr nocapture %d, ptr nocapture %q) nounwind { ; CHECK-NEXT: --> {0,+,2}<%bb> U: [0,2147483645) S: [0,2147483645) Exits: (2 * ((1 + (zext i32 (-2 + (2 * (%no /u 2))) to i64)) /u 2)) LoopDispositions: { %bb: Computable } ; CHECK-NEXT: %5 = getelementptr inbounds double, ptr %q, i64 %4 ; CHECK-NEXT: --> {%q,+,16}<%bb> U: full-set S: full-set Exits: ((16 * ((1 + (zext i32 (-2 + (2 * (%no /u 2))) to i64)) /u 2)) + %q) LoopDispositions: { %bb: Computable } -; CHECK-NEXT: %7 = or i32 %i.01, 1 +; CHECK-NEXT: %7 = or disjoint i32 %i.01, 1 ; CHECK-NEXT: --> {1,+,2}<%bb> U: [1,2147483646) S: [1,2147483646) Exits: (1 + (2 * ((-1 + (2 * (%no /u 2))) /u 2))) LoopDispositions: { %bb: Computable } ; CHECK-NEXT: %8 = sext i32 %7 to i64 ; CHECK-NEXT: --> {1,+,2}<%bb> U: [1,2147483646) S: [1,2147483646) Exits: (1 + (2 * ((1 + (zext i32 (-2 + (2 * (%no /u 2))) to i64)) /u 2))) LoopDispositions: { %bb: Computable } @@ -71,7 +71,7 @@ bb: ; preds = %bb.nph, %bb1 %4 = sext i32 %i.01 to i64 ; [#uses=1] %5 = getelementptr inbounds double, ptr %q, i64 %4 ; [#uses=1] %6 = load double, ptr %5, align 8 ; [#uses=1] - %7 = or i32 %i.01, 1 ; [#uses=1] + %7 = or disjoint i32 %i.01, 1 ; [#uses=1] %8 = sext i32 %7 to i64 ; [#uses=1] diff --git a/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll b/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll index 51b8db676804..fab408ea372e 100644 --- a/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll +++ b/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll @@ -22,7 +22,7 @@ define void @foo(i32 %no, ptr nocapture %d, ptr nocapture %q) nounwind { ; CHECK-NEXT: --> {0,+,2}<%bb> U: [0,2147483645) S: [0,2147483645) Exits: (2 * ((1 + (zext i32 (-2 + (2 * (%no /u 2))) to i64)) /u 2)) LoopDispositions: { %bb: Computable } ; CHECK-NEXT: %5 = getelementptr inbounds double, ptr %q, i64 %4 ; CHECK-NEXT: --> {%q,+,16}<%bb> U: full-set S: full-set Exits: ((16 * ((1 + (zext i32 (-2 + (2 * (%no /u 2))) to i64)) /u 2)) + %q) LoopDispositions: { %bb: Computable } -; CHECK-NEXT: %7 = or i32 %i.01, 1 +; CHECK-NEXT: %7 = or disjoint i32 %i.01, 1 ; CHECK-NEXT: --> {1,+,2}<%bb> U: [1,2147483646) S: [1,2147483646) Exits: (1 + (2 * ((-1 + (2 * (%no /u 2))) /u 2))) LoopDispositions: { %bb: Computable } ; CHECK-NEXT: %8 = sext i32 %7 to i64 ; CHECK-NEXT: --> {1,+,2}<%bb> U: [1,2147483646) S: [1,2147483646) Exits: (1 + (2 * ((1 + (zext i32 (-2 + (2 * (%no /u 2))) to i64)) /u 2))) LoopDispositions: { %bb: Computable } @@ -67,7 +67,7 @@ bb: ; preds = %bb.nph, %bb1 %4 = sext i32 %i.01 to i64 ; [#uses=1] %5 = getelementptr inbounds double, ptr %q, i64 %4 ; [#uses=1] %6 = load double, ptr %5, align 8 ; [#uses=1] - %7 = or i32 %i.01, 1 ; [#uses=1] + %7 = or disjoint i32 %i.01, 1 ; [#uses=1] %8 = sext i32 %7 to i64 ; [#uses=1] diff --git a/llvm/test/Analysis/ScalarEvolution/sext-mul.ll b/llvm/test/Analysis/ScalarEvolution/sext-mul.ll index a31789c5ee3f..2340d5cb6fb6 100644 --- a/llvm/test/Analysis/ScalarEvolution/sext-mul.ll +++ b/llvm/test/Analysis/ScalarEvolution/sext-mul.ll @@ -18,7 +18,7 @@ define void @foo(ptr nocapture %arg, i32 %arg1, i32 %arg2) { ; CHECK-NEXT: --> %tmp12 U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } ; CHECK-NEXT: %tmp13 = sub nsw i32 %tmp12, %arg1 ; CHECK-NEXT: --> ((-1 * %arg1) + %tmp12) U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } -; CHECK-NEXT: %tmp14 = or i64 %tmp10, 1 +; CHECK-NEXT: %tmp14 = or disjoint i64 %tmp10, 1 ; CHECK-NEXT: --> (1 + (sext i32 {0,+,2}<%bb7> to i64)) U: [1,0) S: [-2147483647,2147483648) Exits: (1 + (sext i32 (-2 + (2 * %arg2)) to i64)) LoopDispositions: { %bb7: Computable } ; CHECK-NEXT: %tmp15 = getelementptr inbounds i32, ptr %arg, i64 %tmp14 ; CHECK-NEXT: --> (4 + (4 * (sext i32 {0,+,2}<%bb7> to i64)) + %arg) U: full-set S: full-set Exits: (4 + (4 * (sext i32 (-2 + (2 * %arg2)) to i64)) + %arg) LoopDispositions: { %bb7: Computable } @@ -58,7 +58,7 @@ bb7: ; preds = %bb7, %bb3 %tmp12 = load i32, ptr %tmp11, align 4 %tmp13 = sub nsw i32 %tmp12, %arg1 store i32 %tmp13, ptr %tmp11, align 4 - %tmp14 = or i64 %tmp10, 1 + %tmp14 = or disjoint i64 %tmp10, 1 %tmp15 = getelementptr inbounds i32, ptr %arg, i64 %tmp14 %tmp16 = load i32, ptr %tmp15, align 4 %tmp17 = mul nsw i32 %tmp16, %arg1 @@ -85,7 +85,7 @@ define void @goo(ptr nocapture %arg3, i32 %arg4, i32 %arg5) { ; CHECK-NEXT: --> %t12 U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } ; CHECK-NEXT: %t13 = sub nsw i32 %t12, %arg4 ; CHECK-NEXT: --> ((-1 * %arg4) + %t12) U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } -; CHECK-NEXT: %t14 = or i128 %t10, 1 +; CHECK-NEXT: %t14 = or disjoint i128 %t10, 1 ; CHECK-NEXT: --> (1 + (sext i127 {0,+,633825300114114700748351602688}<%bb7> to i128)) U: [1,-633825300114114700748351602686) S: [-85070591730234615865843651857942052863,85070591096409315751728951109590450178) Exits: (1 + (sext i127 (-633825300114114700748351602688 + (633825300114114700748351602688 * (zext i32 %arg5 to i127))) to i128)) LoopDispositions: { %bb7: Computable } ; CHECK-NEXT: %t15 = getelementptr inbounds i32, ptr %arg3, i128 %t14 ; CHECK-NEXT: --> (4 + %arg3) U: [4,0) S: [4,0) Exits: (4 + %arg3) LoopDispositions: { %bb7: Invariant } @@ -125,7 +125,7 @@ bb7: ; preds = %bb7, %bb3 %t12 = load i32, ptr %t11, align 4 %t13 = sub nsw i32 %t12, %arg4 store i32 %t13, ptr %t11, align 4 - %t14 = or i128 %t10, 1 + %t14 = or disjoint i128 %t10, 1 %t15 = getelementptr inbounds i32, ptr %arg3, i128 %t14 %t16 = load i32, ptr %t15, align 4 %t17 = mul nsw i32 %t16, %arg4 diff --git a/llvm/test/Analysis/StackSafetyAnalysis/ipa.ll b/llvm/test/Analysis/StackSafetyAnalysis/ipa.ll index dd6d714e8e5e..8de56adc2bbd 100644 --- a/llvm/test/Analysis/StackSafetyAnalysis/ipa.ll +++ b/llvm/test/Analysis/StackSafetyAnalysis/ipa.ll @@ -731,7 +731,7 @@ entry: ; INDEX-DAG: guid: [[Write1SameModule]], {{.*}}, params: ((param: 0, offset: [0, 0]))))) ; INDEX-DAG: guid: [[Write8]], {{.*}}, params: ((param: 0, offset: [0, 7]))))) ; INDEX-DAG: guid: [[Write4_2]], {{.*}}, params: ((param: 0, offset: [0, 3]), (param: 1, offset: [0, 3]))))) -; INDEX-DAG: guid: [[RecursiveWithOffset]], {{.*}}, calls: ((callee: ^{{[0-9]+}}))))) +; INDEX-DAG: guid: [[RecursiveWithOffset]], {{.*}}, calls: ((callee: ^{{[0-9]+}}, tail: 1))))) ; INDEX-DAG: guid: [[Weak]], {{.*}}, funcFlags: ({{.*}})))) ; INDEX-DAG: guid: [[Write1Private]], {{.*}}, params: ((param: 0, offset: [-1, -1]))))) ; INDEX-DAG: guid: [[InterposableWrite1]], {{.*}}, params: ((param: 0, offset: [0, 0]))))) diff --git a/llvm/test/Assembler/globalvariable-attributes.ll b/llvm/test/Assembler/globalvariable-attributes.ll index 544f9bdb270e..4882b447973c 100644 --- a/llvm/test/Assembler/globalvariable-attributes.ll +++ b/llvm/test/Assembler/globalvariable-attributes.ll @@ -9,6 +9,11 @@ @g7 = global i32 2, sanitize_address_dyninit, align 4 @g8 = global i32 2, sanitize_memtag, align 4 @g9 = global i32 2, no_sanitize_address, no_sanitize_hwaddress, sanitize_memtag, align 4 +@g10 = global i32 2, code_model "tiny" +@g11 = global i32 2, code_model "small" +@g12 = global i32 2, code_model "kernel" +@g13 = global i32 2, code_model "medium" +@g14 = global i32 2, code_model "large" attributes #0 = { "string" = "value" nobuiltin norecurse } @@ -21,6 +26,11 @@ attributes #0 = { "string" = "value" nobuiltin norecurse } ; CHECK: @g7 = global i32 2, sanitize_address_dyninit, align 4 ; CHECK: @g8 = global i32 2, sanitize_memtag, align 4 ; CHECK: @g9 = global i32 2, no_sanitize_address, no_sanitize_hwaddress, sanitize_memtag, align 4 +; CHECK: @g10 = global i32 2, code_model "tiny" +; CHECK: @g11 = global i32 2, code_model "small" +; CHECK: @g12 = global i32 2, code_model "kernel" +; CHECK: @g13 = global i32 2, code_model "medium" +; CHECK: @g14 = global i32 2, code_model "large" ; CHECK: attributes #0 = { "key"="value" "key2"="value2" } ; CHECK: attributes #1 = { "key3"="value3" } diff --git a/llvm/test/Assembler/index-value-order.ll b/llvm/test/Assembler/index-value-order.ll new file mode 100644 index 000000000000..9df6d4a46fef --- /dev/null +++ b/llvm/test/Assembler/index-value-order.ll @@ -0,0 +1,25 @@ +; Even if value ids come out of order summary assembly should be parsed correctly +; RUN: llvm-as %s -o - | llvm-dis -o - | FileCheck %s + +; CHECK-DAG: ^[[VTBL:[0-9]+]] = gv: {{.*}} "_ZTVN3FooE", {{.*}}virtFunc: ^[[VFN:[0-9]+]] +; CHECK-DAG: ^{{[0-9]+}} = typeidCompatibleVTable: {{.*}}name: "_ZTSN3FooE",{{.*}}(offset: 16, ^[[VTBL]]) +; CHECK-DAG: ^{{[0-9]+}} = gv: {{.*}}name: "_ZTSN3FooE" +; CHECK-DAG: ^[[VFN]] = gv: {{.*}} "_Z3barv" + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +$_ZTSN3FooE = comdat any + +@_ZTSN3FooE = linkonce_odr constant [7 x i8] c"N3FooE\00", comdat, align 1 +@"_ZTVN3FooE" = internal unnamed_addr constant { [2 x ptr] } { [2 x ptr] [ptr null, ptr @"_Z3barv"] }, align 8 + +define internal i32 @"_Z3barv"() { + ret i32 0 +} + +^0 = module: (path: "index-value-order.ll", hash: (0, 0, 0, 0, 0)) +^9 = gv: (name: "_ZTVN3FooE", summaries: (variable: (module: ^0, flags: (linkage: internal, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), varFlags: (readonly: 1, writeonly: 0, constant: 1, vcall_visibility: 0), vTableFuncs: ((virtFunc: ^3, offset: 16))))) +^4 = gv: (name: "_ZTSN3FooE", summaries: (variable: (module: ^0, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 1)))) +^3 = gv: (name: "_Z3barv", summaries: (function: (module: ^0, flags: (linkage: internal, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 1, funcFlags: (readNone: 1, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 1, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0)))) +^2 = typeidCompatibleVTable: (name: "_ZTSN3FooE", summary: ((offset: 16, ^9))) diff --git a/llvm/test/Assembler/thinlto-summary.ll b/llvm/test/Assembler/thinlto-summary.ll index beaf4528b92d..9eb3c6669780 100644 --- a/llvm/test/Assembler/thinlto-summary.ll +++ b/llvm/test/Assembler/thinlto-summary.ll @@ -9,11 +9,11 @@ ; Check a function that makes several calls with various profile hotness, and a ; reference (also tests forward references to function and variables in calls ; and refs). -^2 = gv: (guid: 1, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 10, calls: ((callee: ^15, hotness: hot), (callee: ^17, hotness: cold), (callee: ^16, hotness: none)), refs: (writeonly ^14, readonly ^13, ^11)))) +^2 = gv: (guid: 1, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 10, calls: ((callee: ^15, hotness: hot), (callee: ^17, hotness: cold), (callee: ^16, hotness: none, tail: 1)), refs: (writeonly ^14, readonly ^13, ^11)))) ; Function with a call that has relative block frequency instead of profile ; hotness. -^3 = gv: (guid: 2, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 10, calls: ((callee: ^15, relbf: 256))))) +^3 = gv: (guid: 2, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 10, calls: ((callee: ^15, relbf: 256, tail: 1))))) ; Summaries with different linkage types. ^4 = gv: (guid: 3, summaries: (function: (module: ^0, flags: (linkage: internal, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1), insts: 1))) @@ -69,8 +69,10 @@ ; Make sure we get back from llvm-dis essentially what we put in via llvm-as. ; CHECK: ^0 = module: (path: "thinlto-summary1.o", hash: (1369602428, 2747878711, 259090915, 2507395659, 1141468049)) ; CHECK: ^1 = module: (path: "thinlto-summary2.o", hash: (2998369023, 4283347029, 1195487472, 2757298015, 1852134156)) -; CHECK: ^2 = gv: (guid: 1, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 10, calls: ((callee: ^15, hotness: hot), (callee: ^17, hotness: cold), (callee: ^16, hotness: none)), refs: (^11, readonly ^13, writeonly ^14)))) -; CHECK: ^3 = gv: (guid: 2, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 10, calls: ((callee: ^15))))) +; CHECK: ^2 = gv: (guid: 1, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 10, calls: ((callee: ^15, hotness: hot), (callee: ^17, hotness: cold), (callee: ^16, hotness: none, tail: 1)), refs: (^11, readonly ^13, writeonly ^14)))) +;; relbf is not emitted since this is a combined summary, and that is only +;; emitted for per-module summaries. +; CHECK: ^3 = gv: (guid: 2, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 10, calls: ((callee: ^15, tail: 1))))) ; CHECK: ^4 = gv: (guid: 3, summaries: (function: (module: ^0, flags: (linkage: internal, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 1))) ; CHECK: ^5 = gv: (guid: 4, summaries: (alias: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), aliasee: ^14))) ; CHECK: ^6 = gv: (guid: 5, summaries: (function: (module: ^0, flags: (linkage: available_externally, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) diff --git a/llvm/test/Bindings/llvm-c/echo.ll b/llvm/test/Bindings/llvm-c/echo.ll index 72d5b455badc..0775cbb673e4 100644 --- a/llvm/test/Bindings/llvm-c/echo.ll +++ b/llvm/test/Bindings/llvm-c/echo.ll @@ -92,7 +92,8 @@ define i32 @iops(i32 %a, i32 %b) { %23 = ashr exact i32 %22, %14 %24 = zext i32 %23 to i64 %25 = zext nneg i32 %23 to i64 - ret i32 %23 + %26 = or disjoint i32 %23, %a + ret i32 %26 } define i32 @call() { diff --git a/llvm/test/Bitcode/thinlto-alias.ll b/llvm/test/Bitcode/thinlto-alias.ll index 373dc715de51..eb794f4e631d 100644 --- a/llvm/test/Bitcode/thinlto-alias.ll +++ b/llvm/test/Bitcode/thinlto-alias.ll @@ -21,7 +21,7 @@ ; CHECK-NEXT: +; CHECK-NEXT: ; CHECK: ; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; CHECK-NEXT: ; CHECK-NEXT: diff --git a/llvm/test/Bitcode/thinlto-asm-noimport.ll b/llvm/test/Bitcode/thinlto-asm-noimport.ll index 84d2e95cefbc..b937f95961a4 100644 --- a/llvm/test/Bitcode/thinlto-asm-noimport.ll +++ b/llvm/test/Bitcode/thinlto-asm-noimport.ll @@ -9,7 +9,7 @@ module asm "asm:" module asm "bx lr" ; NotEligibleToImport -; CHECK: +; CHECK-NEXT: -; CHECK-NEXT: +; CHECK-NEXT: ; CHECK-NEXT: diff --git a/llvm/test/Bitcode/thinlto-function-summary-callgraph-partial-sample-profile-summary.ll b/llvm/test/Bitcode/thinlto-function-summary-callgraph-partial-sample-profile-summary.ll index 1906229879f5..d44ee24694be 100644 --- a/llvm/test/Bitcode/thinlto-function-summary-callgraph-partial-sample-profile-summary.ll +++ b/llvm/test/Bitcode/thinlto-function-summary-callgraph-partial-sample-profile-summary.ll @@ -52,16 +52,16 @@ ; COMBINED-NEXT: -; COMBINED-NEXT: ; COMBINED-NEXT: diff --git a/llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll b/llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll index c8df387fca45..d7679b6f5af2 100644 --- a/llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll +++ b/llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll @@ -66,14 +66,14 @@ ; COMBINED-NEXT: -; COMBINED-NEXT: diff --git a/llvm/test/Bitcode/thinlto-function-summary-callgraph-sample-profile-summary.ll b/llvm/test/Bitcode/thinlto-function-summary-callgraph-sample-profile-summary.ll index e8e2b0de91b6..601bebd39267 100644 --- a/llvm/test/Bitcode/thinlto-function-summary-callgraph-sample-profile-summary.ll +++ b/llvm/test/Bitcode/thinlto-function-summary-callgraph-sample-profile-summary.ll @@ -51,16 +51,16 @@ ; COMBINED-NEXT: -; COMBINED-NEXT: diff --git a/llvm/test/Bitcode/thinlto-function-summary-callgraph.ll b/llvm/test/Bitcode/thinlto-function-summary-callgraph.ll index 765efcf7b822..542b400f8e33 100644 --- a/llvm/test/Bitcode/thinlto-function-summary-callgraph.ll +++ b/llvm/test/Bitcode/thinlto-function-summary-callgraph.ll @@ -19,7 +19,7 @@ ; CHECK-NEXT: ; CHECK: ; COMBINED-NEXT: +; COMBINED-NEXT: ; ModuleID = 'thinlto-function-summary-callgraph.ll' diff --git a/llvm/test/Bitcode/thinlto-function-summary-functionattrs.ll b/llvm/test/Bitcode/thinlto-function-summary-functionattrs.ll index 2ad49e3c8647..7fa15ebbde14 100644 --- a/llvm/test/Bitcode/thinlto-function-summary-functionattrs.ll +++ b/llvm/test/Bitcode/thinlto-function-summary-functionattrs.ll @@ -3,13 +3,13 @@ ; CHECK: ; COMBINED-NEXT: ; COMBINED-NEXT: -; COMBINED-DAG: ; COMBINED-DAG: diff --git a/llvm/test/Bitcode/thinlto-function-summary-paramaccess.ll b/llvm/test/Bitcode/thinlto-function-summary-paramaccess.ll index 96a783fdb3e2..f8e6476ea3e8 100644 --- a/llvm/test/Bitcode/thinlto-function-summary-paramaccess.ll +++ b/llvm/test/Bitcode/thinlto-function-summary-paramaccess.ll @@ -306,35 +306,35 @@ entry: ; COMBINED-NEXT: ; COMBINED-NEXT: ; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; COMBINED-NEXT: -; Function W contains a call to func3 as well as a reference to globalvar: +; CHECK-DAG: +; Function W contains a tail call to func3 as well as a reference to globalvar: ; op0=W op4=globalvar op5=func3 -; CHECK-DAG: +; CHECK-DAG: ; Function X contains call to foo, as well as address reference to foo ; which is in the same instruction as the call: ; op0=X op4=foo op5=foo -; CHECK-DAG: -; Function Y contains call to func2, and ensures we don't incorrectly add +; CHECK-DAG: +; Function Y contains tail call to func2, and ensures we don't incorrectly add ; a reference to it when reached while earlier analyzing the phi using its ; return value: ; op0=Y op4=func2 -; CHECK-DAG: -; Function Z contains call to func2, and ensures we don't incorrectly add +; CHECK-DAG: +; Function Z contains a tail call to func2, and ensures we don't incorrectly add ; a reference to it when reached while analyzing subsequent use of its return ; value: ; op0=Z op4=func2 -; CHECK-DAG: +; CHECK-DAG: ; Variable bar initialization contains address reference to func: ; op0=bar op2=func ; CHECK-DAG: @@ -148,9 +148,9 @@ entry: ; order, which depends on GUID, and the private function Y GUID will depend ; on the path to the test. ; DIS: ^0 = module: (path: "{{.*}}", hash: (0, 0, 0, 0, 0)) -; DIS-DAG: = gv: (name: "Z", summaries: (function: (module: ^0, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, calls: ((callee: ^{{.*}}))))) ; guid = 104084381700047393 +; DIS-DAG: = gv: (name: "Z", summaries: (function: (module: ^0, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, calls: ((callee: ^{{.*}}, tail: 1))))) ; guid = 104084381700047393 ; DIS-DAG: = gv: (name: "X", summaries: (function: (module: ^0, flags: (linkage: available_externally, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) ; guid = 1881667236089500162 -; DIS-DAG: = gv: (name: "W", summaries: (function: (module: ^0, flags: (linkage: weak_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) ; guid = 5790125716599269729 +; DIS-DAG: = gv: (name: "W", summaries: (function: (module: ^0, flags: (linkage: weak_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, calls: ((callee: ^{{.*}}, tail: 1)), refs: (^{{.*}})))) ; guid = 5790125716599269729 ; DIS-DAG: = gv: (name: "foo") ; guid = 6699318081062747564 ; DIS-DAG: = gv: (name: "func") ; guid = 7289175272376759421 ; DIS-DAG: = gv: (name: "func3") ; guid = 11517462787082255043 @@ -162,4 +162,4 @@ entry: ; DIS-DAG: = gv: (name: "bar", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), varFlags: (readonly: 1, writeonly: 1, constant: 0), refs: (^{{.*}})))) ; guid = 16434608426314478903 ; Don't try to match the exact GUID. Since it is private, the file path ; will get hashed, and that will be test dependent. -; DIS-DAG: = gv: (name: "Y", summaries: (function: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 14, calls: ((callee: ^{{.*}}))))) ; guid = +; DIS-DAG: = gv: (name: "Y", summaries: (function: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 14, calls: ((callee: ^{{.*}}, tail: 1))))) ; guid = diff --git a/llvm/test/Bitcode/thinlto-function-summary.ll b/llvm/test/Bitcode/thinlto-function-summary.ll index 6aee2636fa3b..799759ebcac1 100644 --- a/llvm/test/Bitcode/thinlto-function-summary.ll +++ b/llvm/test/Bitcode/thinlto-function-summary.ll @@ -19,10 +19,10 @@ ; BC: , ptr %array0, align 8 %array2 = getelementptr inbounds double, ptr %array0, i64 2 store <2 x double> , ptr %array2, align 8 - %index4 = or i64 %index, 4 + %index4 = or disjoint i64 %index, 4 %array4 = getelementptr inbounds double, ptr %array, i64 %index4 store <2 x double> , ptr %array4, align 8 %array6 = getelementptr inbounds double, ptr %array4, i64 2 store <2 x double> , ptr %array6, align 8 - %index8 = or i64 %index, 8 + %index8 = or disjoint i64 %index, 8 %array8 = getelementptr inbounds double, ptr %array, i64 %index8 store <2 x double> , ptr %array8, align 8 %array10 = getelementptr inbounds double, ptr %array8, i64 2 store <2 x double> , ptr %array10, align 8 - %index12 = or i64 %index, 12 + %index12 = or disjoint i64 %index, 12 %array12 = getelementptr inbounds double, ptr %array, i64 %index12 store <2 x double> , ptr %array12, align 8 %array14 = getelementptr inbounds double, ptr %array12, i64 2 diff --git a/llvm/test/CodeGen/AArch64/arm64-addrmode.ll b/llvm/test/CodeGen/AArch64/arm64-addrmode.ll index 69c558d9d559..3d4749a7b8e7 100644 --- a/llvm/test/CodeGen/AArch64/arm64-addrmode.ll +++ b/llvm/test/CodeGen/AArch64/arm64-addrmode.ll @@ -209,3 +209,89 @@ define void @t17(i64 %a) { %3 = load volatile i64, ptr %2, align 8 ret void } + +define i32 @LdOffset_i8(ptr %a) { +; CHECK-LABEL: LdOffset_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #56952 // =0xde78 +; CHECK-NEXT: movk w8, #15, lsl #16 +; CHECK-NEXT: ldrb w0, [x0, x8] +; CHECK-NEXT: ret + %arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992 + %val = load i8, ptr %arrayidx, align 1 + %conv = zext i8 %val to i32 + ret i32 %conv +} + +define i32 @LdOffset_i16(ptr %a) { +; CHECK-LABEL: LdOffset_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #48368 // =0xbcf0 +; CHECK-NEXT: movk w8, #31, lsl #16 +; CHECK-NEXT: ldrsh w0, [x0, x8] +; CHECK-NEXT: ret + %arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992 + %val = load i16, ptr %arrayidx, align 2 + %conv = sext i16 %val to i32 + ret i32 %conv +} + +define i32 @LdOffset_i32(ptr %a) { +; CHECK-LABEL: LdOffset_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #31200 // =0x79e0 +; CHECK-NEXT: movk w8, #63, lsl #16 +; CHECK-NEXT: ldr w0, [x0, x8] +; CHECK-NEXT: ret + %arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992 + %val = load i32, ptr %arrayidx, align 4 + ret i32 %val +} + +define i64 @LdOffset_i64_multi_offset(ptr %a) { +; CHECK-LABEL: LdOffset_i64_multi_offset: +; CHECK: // %bb.0: +; CHECK-NEXT: add x8, x0, #2031, lsl #12 // =8318976 +; CHECK-NEXT: ldr x9, [x8, #960] +; CHECK-NEXT: ldr x8, [x8, #3016] +; CHECK-NEXT: add x0, x8, x9 +; CHECK-NEXT: ret + %arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992 + %val0 = load i64, ptr %arrayidx, align 8 + %arrayidx1 = getelementptr inbounds i64, ptr %a, i64 1040249 + %val1 = load i64, ptr %arrayidx1, align 8 + %add = add nsw i64 %val1, %val0 + ret i64 %add +} + +define i64 @LdOffset_i64_multi_offset_with_commmon_base(ptr %a) { +; CHECK-LABEL: LdOffset_i64_multi_offset_with_commmon_base: +; CHECK: // %bb.0: +; CHECK-NEXT: add x8, x0, #507, lsl #12 // =2076672 +; CHECK-NEXT: ldr x9, [x8, #26464] +; CHECK-NEXT: ldr x8, [x8, #26496] +; CHECK-NEXT: add x0, x8, x9 +; CHECK-NEXT: ret + %b = getelementptr inbounds i16, ptr %a, i64 1038336 + %arrayidx = getelementptr inbounds i64, ptr %b, i64 3308 + %val0 = load i64, ptr %arrayidx, align 8 + %arrayidx1 = getelementptr inbounds i64, ptr %b, i64 3312 + %val1 = load i64, ptr %arrayidx1, align 8 + %add = add nsw i64 %val1, %val0 + ret i64 %add +} + +; Negative test: the offset is odd +define i32 @LdOffset_i16_odd_offset(ptr nocapture noundef readonly %a) { +; CHECK-LABEL: LdOffset_i16_odd_offset: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #56953 // =0xde79 +; CHECK-NEXT: movk w8, #15, lsl #16 +; CHECK-NEXT: ldrsh w0, [x0, x8] +; CHECK-NEXT: ret + %arrayidx = getelementptr inbounds i8, ptr %a, i64 1039993 + %val = load i16, ptr %arrayidx, align 2 + %conv = sext i16 %val to i32 + ret i32 %conv +} + diff --git a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll index 0d7620d1c883..7493afd672d4 100644 --- a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll +++ b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll @@ -14659,17 +14659,9 @@ define i8 @load_single_extract_variable_index_i8(ptr %A, i32 %idx) { ; ; CHECK-GISEL-LABEL: load_single_extract_variable_index_i8: ; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: sub sp, sp, #16 -; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16 -; CHECK-GISEL-NEXT: mov w9, w1 -; CHECK-GISEL-NEXT: ldr q0, [x0] -; CHECK-GISEL-NEXT: mov x8, sp -; CHECK-GISEL-NEXT: and x9, x9, #0xf -; CHECK-GISEL-NEXT: lsl x10, x9, #1 -; CHECK-GISEL-NEXT: str q0, [sp] -; CHECK-GISEL-NEXT: sub x9, x10, x9 -; CHECK-GISEL-NEXT: ldrb w0, [x8, x9] -; CHECK-GISEL-NEXT: add sp, sp, #16 +; CHECK-GISEL-NEXT: mov w8, w1 +; CHECK-GISEL-NEXT: and x8, x8, #0xf +; CHECK-GISEL-NEXT: ldrb w0, [x0, x8] ; CHECK-GISEL-NEXT: ret %lv = load <16 x i8>, ptr %A %e = extractelement <16 x i8> %lv, i32 %idx @@ -14692,15 +14684,9 @@ define i16 @load_single_extract_variable_index_i16(ptr %A, i32 %idx) { ; ; CHECK-GISEL-LABEL: load_single_extract_variable_index_i16: ; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: sub sp, sp, #16 -; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16 -; CHECK-GISEL-NEXT: ldr q0, [x0] -; CHECK-GISEL-NEXT: mov w9, w1 -; CHECK-GISEL-NEXT: mov x8, sp -; CHECK-GISEL-NEXT: and x9, x9, #0x7 -; CHECK-GISEL-NEXT: str q0, [sp] -; CHECK-GISEL-NEXT: ldrh w0, [x8, x9, lsl #1] -; CHECK-GISEL-NEXT: add sp, sp, #16 +; CHECK-GISEL-NEXT: mov w8, w1 +; CHECK-GISEL-NEXT: and x8, x8, #0x7 +; CHECK-GISEL-NEXT: ldrh w0, [x0, x8, lsl #1] ; CHECK-GISEL-NEXT: ret %lv = load <8 x i16>, ptr %A %e = extractelement <8 x i16> %lv, i32 %idx @@ -14717,15 +14703,9 @@ define i32 @load_single_extract_variable_index_i32(ptr %A, i32 %idx) { ; ; CHECK-GISEL-LABEL: load_single_extract_variable_index_i32: ; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: sub sp, sp, #16 -; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16 -; CHECK-GISEL-NEXT: ldr q0, [x0] -; CHECK-GISEL-NEXT: mov w9, w1 -; CHECK-GISEL-NEXT: mov x8, sp -; CHECK-GISEL-NEXT: and x9, x9, #0x3 -; CHECK-GISEL-NEXT: str q0, [sp] -; CHECK-GISEL-NEXT: ldr w0, [x8, x9, lsl #2] -; CHECK-GISEL-NEXT: add sp, sp, #16 +; CHECK-GISEL-NEXT: mov w8, w1 +; CHECK-GISEL-NEXT: and x8, x8, #0x3 +; CHECK-GISEL-NEXT: ldr w0, [x0, x8, lsl #2] ; CHECK-GISEL-NEXT: ret %lv = load <4 x i32>, ptr %A %e = extractelement <4 x i32> %lv, i32 %idx @@ -14779,14 +14759,8 @@ define i32 @load_single_extract_variable_index_masked_i32(ptr %A, i32 %idx) { ; ; CHECK-GISEL-LABEL: load_single_extract_variable_index_masked_i32: ; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: sub sp, sp, #16 -; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16 -; CHECK-GISEL-NEXT: ldr q0, [x0] -; CHECK-GISEL-NEXT: mov x8, sp -; CHECK-GISEL-NEXT: and w9, w1, #0x3 -; CHECK-GISEL-NEXT: str q0, [sp] -; CHECK-GISEL-NEXT: ldr w0, [x8, w9, uxtw #2] -; CHECK-GISEL-NEXT: add sp, sp, #16 +; CHECK-GISEL-NEXT: and w8, w1, #0x3 +; CHECK-GISEL-NEXT: ldr w0, [x0, w8, uxtw #2] ; CHECK-GISEL-NEXT: ret %idx.x = and i32 %idx, 3 %lv = load <4 x i32>, ptr %A @@ -14803,14 +14777,8 @@ define i32 @load_single_extract_variable_index_masked2_i32(ptr %A, i32 %idx) { ; ; CHECK-GISEL-LABEL: load_single_extract_variable_index_masked2_i32: ; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: sub sp, sp, #16 -; CHECK-GISEL-NEXT: .cfi_def_cfa_offset 16 -; CHECK-GISEL-NEXT: ldr q0, [x0] -; CHECK-GISEL-NEXT: mov x8, sp -; CHECK-GISEL-NEXT: and w9, w1, #0x1 -; CHECK-GISEL-NEXT: str q0, [sp] -; CHECK-GISEL-NEXT: ldr w0, [x8, w9, uxtw #2] -; CHECK-GISEL-NEXT: add sp, sp, #16 +; CHECK-GISEL-NEXT: and w8, w1, #0x1 +; CHECK-GISEL-NEXT: ldr w0, [x0, w8, uxtw #2] ; CHECK-GISEL-NEXT: ret %idx.x = and i32 %idx, 1 %lv = load <4 x i32>, ptr %A diff --git a/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.ll b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.ll new file mode 100644 index 000000000000..bc26eca6f27e --- /dev/null +++ b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.ll @@ -0,0 +1,125 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=arm64-apple-macosx10.13.0 -mcpu=apple-m1 < %s | FileCheck %s + +@.str = external constant [9 x i8] + +define void @_ZN38SanitizerCommonInterceptors_Scanf_Test8TestBodyEv(ptr %.str.40, ptr %.str.41, ptr %.str.42, ptr %.str.43, ptr %.str.44, ptr %.str.45, ptr nocapture writeonly %.str.47) nounwind { +; CHECK-LABEL: _ZN38SanitizerCommonInterceptors_Scanf_Test8TestBodyEv: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: sub sp, sp, #128 +; CHECK-NEXT: stp x28, x27, [sp, #32] ; 16-byte Folded Spill +; CHECK-NEXT: stp x26, x25, [sp, #48] ; 16-byte Folded Spill +; CHECK-NEXT: stp x24, x23, [sp, #64] ; 16-byte Folded Spill +; CHECK-NEXT: stp x22, x21, [sp, #80] ; 16-byte Folded Spill +; CHECK-NEXT: stp x20, x19, [sp, #96] ; 16-byte Folded Spill +; CHECK-NEXT: stp x29, x30, [sp, #112] ; 16-byte Folded Spill +; CHECK-NEXT: mov x24, x6 +; CHECK-NEXT: mov x19, x5 +; CHECK-NEXT: mov x20, x4 +; CHECK-NEXT: mov x21, x3 +; CHECK-NEXT: mov x22, x2 +; CHECK-NEXT: mov x23, x1 +; CHECK-NEXT: mov x25, x0 +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x0, #0 ; =0x0 +; CHECK-NEXT: mov w1, #1 ; =0x1 +; CHECK-NEXT: bl __ZL9testScanfPKcjz +; CHECK-NEXT: mov w28, #4 ; =0x4 +; CHECK-NEXT: stp x28, x28, [sp, #8] +; CHECK-NEXT: str x28, [sp] +; CHECK-NEXT: mov x0, #0 ; =0x0 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL9testScanfPKcjz +; CHECK-NEXT: stp x28, xzr, [sp] +; CHECK-NEXT: mov x0, #0 ; =0x0 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL9testScanfPKcjz +; CHECK-NEXT: mov w27, #8 ; =0x8 +; CHECK-NEXT: str x27, [sp] +; CHECK-NEXT: mov x0, #0 ; =0x0 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL9testScanfPKcjz +; CHECK-NEXT: mov w26, #1 ; =0x1 +; CHECK-NEXT: stp xzr, x26, [sp] +; CHECK-NEXT: mov x0, #0 ; =0x0 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL9testScanfPKcjz +; CHECK-NEXT: str x26, [sp] +; CHECK-NEXT: mov x0, #0 ; =0x0 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL9testScanfPKcjz +; CHECK-NEXT: str x28, [sp] +; CHECK-NEXT: Lloh0: +; CHECK-NEXT: adrp x26, _.str@GOTPAGE +; CHECK-NEXT: Lloh1: +; CHECK-NEXT: ldr x26, [x26, _.str@GOTPAGEOFF] +; CHECK-NEXT: mov x0, x26 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL9testScanfPKcjz +; CHECK-NEXT: str wzr, [x24] +; CHECK-NEXT: str x27, [sp] +; CHECK-NEXT: mov x0, x25 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz +; CHECK-NEXT: str x28, [sp] +; CHECK-NEXT: mov x0, x23 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz +; CHECK-NEXT: str x28, [sp] +; CHECK-NEXT: mov x0, x22 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz +; CHECK-NEXT: str x28, [sp] +; CHECK-NEXT: mov x0, x21 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz +; CHECK-NEXT: str x28, [sp] +; CHECK-NEXT: mov x0, x20 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x0, x19 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x0, x26 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz +; CHECK-NEXT: mov w8, #1 ; =0x1 +; CHECK-NEXT: stp x8, xzr, [sp, #8] +; CHECK-NEXT: str xzr, [sp] +; CHECK-NEXT: mov x0, #0 ; =0x0 +; CHECK-NEXT: mov w1, #0 ; =0x0 +; CHECK-NEXT: bl __ZL20testScanfNoGnuMallocPKcjz +; CHECK-NEXT: ldp x29, x30, [sp, #112] ; 16-byte Folded Reload +; CHECK-NEXT: ldp x20, x19, [sp, #96] ; 16-byte Folded Reload +; CHECK-NEXT: ldp x22, x21, [sp, #80] ; 16-byte Folded Reload +; CHECK-NEXT: ldp x24, x23, [sp, #64] ; 16-byte Folded Reload +; CHECK-NEXT: ldp x26, x25, [sp, #48] ; 16-byte Folded Reload +; CHECK-NEXT: ldp x28, x27, [sp, #32] ; 16-byte Folded Reload +; CHECK-NEXT: add sp, sp, #128 +; CHECK-NEXT: ret +; CHECK-NEXT: .loh AdrpLdrGot Lloh0, Lloh1 +entry: + tail call void (ptr, i32, ...) @_ZL9testScanfPKcjz(ptr null, i32 1, i32 0) + tail call void (ptr, i32, ...) @_ZL9testScanfPKcjz(ptr null, i32 0, i32 4, i32 4, i32 4) + tail call void (ptr, i32, ...) @_ZL9testScanfPKcjz(ptr null, i32 0, i32 4, i32 0) + tail call void (ptr, i32, ...) @_ZL9testScanfPKcjz(ptr null, i32 0, i32 8) + tail call void (ptr, i32, ...) @_ZL9testScanfPKcjz(ptr null, i32 0, i32 0, i32 1) + tail call void (ptr, i32, ...) @_ZL9testScanfPKcjz(ptr null, i32 0, i32 1) + tail call void (ptr, i32, ...) @_ZL9testScanfPKcjz(ptr nonnull @.str, i32 0, i32 4) + store i32 0, ptr %.str.47, align 4 + tail call void (ptr, i32, ...) @_ZL20testScanfNoGnuMallocPKcjz(ptr %.str.40, i32 0, i32 8) + tail call void (ptr, i32, ...) @_ZL20testScanfNoGnuMallocPKcjz(ptr %.str.41, i32 0, i32 4) + tail call void (ptr, i32, ...) @_ZL20testScanfNoGnuMallocPKcjz(ptr %.str.42, i32 0, i32 4) + tail call void (ptr, i32, ...) @_ZL20testScanfNoGnuMallocPKcjz(ptr %.str.43, i32 0, i32 4) + tail call void (ptr, i32, ...) @_ZL20testScanfNoGnuMallocPKcjz(ptr %.str.44, i32 0, i32 4) + tail call void (ptr, i32, ...) @_ZL20testScanfNoGnuMallocPKcjz(ptr %.str.45, i32 0, i32 0) + tail call void (ptr, i32, ...) @_ZL20testScanfNoGnuMallocPKcjz(ptr nonnull @.str, i32 0, i32 0) + tail call void (ptr, i32, ...) @_ZL20testScanfNoGnuMallocPKcjz(ptr null, i32 0, i32 0, i32 1, i32 0) + ret void +} + +declare void @_ZL9testScanfPKcjz(ptr, i32, ...) local_unnamed_addr + +declare void @_ZL20testScanfNoGnuMallocPKcjz(ptr, i32, ...) local_unnamed_addr diff --git a/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir new file mode 100644 index 000000000000..9040937d027d --- /dev/null +++ b/llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir @@ -0,0 +1,119 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=arm64-apple-macosx -mcpu=apple-m1 -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s +--- +name: func +tracksRegLiveness: true +body: | + bb.0: + liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6 + + ; CHECK-LABEL: name: func + ; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64sp = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:gpr32 = IMPLICIT_DEF + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64 = COPY $x4 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr64 = COPY $x5 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr64 = COPY $x6 + ; CHECK-NEXT: undef [[MOVi32imm:%[0-9]+]].sub_32:gpr64 = MOVi32imm 4, implicit-def [[MOVi32imm]] + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: BL 0, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKUP 24, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gpr64 = IMPLICIT_DEF + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: undef [[DEF3:%[0-9]+]].sub_32:gpr64 = IMPLICIT_DEF implicit-def [[DEF3]] + ; CHECK-NEXT: STRXui [[DEF3]], [[DEF]], 1 :: (store (s64) into stack + 8) + ; CHECK-NEXT: BL 0, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ; CHECK-NEXT: ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: STRXui [[MOVi32imm]], [[DEF]], 0 :: (store (s64) into stack) + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: STRWui undef [[MOVi32imm]].sub_32, [[COPY]], 0 :: (store (s32)) + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: STRXui [[DEF2]], undef [[DEF]], 0 :: (store (s64) into stack) + ; CHECK-NEXT: $x0 = COPY [[COPY6]] + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $x0 = COPY [[COPY5]] + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $x0 = COPY [[COPY4]] + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $x0 = COPY [[COPY3]] + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $x0 = COPY [[COPY2]] + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $x0 = COPY [[COPY1]] + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: ADJCALLSTACKDOWN 24, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: undef [[DEF4:%[0-9]+]].sub_32:gpr64 = IMPLICIT_DEF implicit-def [[DEF4]] + ; CHECK-NEXT: STRXui [[DEF4]], undef [[DEF]], 1 :: (store (s64) into stack + 8) + ; CHECK-NEXT: ADJCALLSTACKUP 24, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: RET_ReallyLR + %0:gpr64sp = IMPLICIT_DEF + undef %13.sub_32:gpr64 = IMPLICIT_DEF implicit-def %13 + dead %2:gpr32 = IMPLICIT_DEF + %3:gpr64common = COPY $x0 + %4:gpr64 = COPY $x1 + %5:gpr64 = COPY $x2 + %6:gpr64 = COPY $x3 + %7:gpr64 = COPY $x4 + %8:gpr64 = COPY $x5 + %9:gpr64 = COPY $x6 + undef %11.sub_32:gpr64 = MOVi32imm 4, implicit-def %11 + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + BL 0, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 24, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKUP 24, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + %12:gpr64 = IMPLICIT_DEF + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp + STRXui %13, %0, 1 :: (store (s64) into stack + 8) + BL 0, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + STRXui %11, %0, 0 :: (store (s64) into stack) + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + STRWui undef %11.sub_32, %3, 0 :: (store (s32)) + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + STRXui %12, undef %0, 0 :: (store (s64) into stack) + $x0 = COPY %9 + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + $x0 = COPY %8 + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + $x0 = COPY %7 + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + $x0 = COPY %6 + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + $x0 = COPY %5 + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + $x0 = COPY %4 + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ADJCALLSTACKDOWN 24, 0, implicit-def dead $sp, implicit $sp + STRXui %13, undef %0, 1 :: (store (s64) into stack + 8) + ADJCALLSTACKUP 24, 0, implicit-def dead $sp, implicit $sp + RET_ReallyLR + +... diff --git a/llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir b/llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir new file mode 100644 index 000000000000..aa94a03786f5 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=arm64-apple-macosx -mcpu=apple-m1 -stress-regalloc=4 -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s + +--- | + define void @inst_stores_to_dead_spill_implicit_def_impdef() { + ret void + } + + define void @inst_stores_to_dead_spill_movimm_impdef() { + ret void + } + + declare void @foo(ptr, i32, ...) + +... + +# The IMPLICIT_DEf has an implicit-def of a different virtual register +# than the main def, so it should not be unconditionally treated as +# rematerializable. + +--- +name: inst_stores_to_dead_spill_implicit_def_impdef +tracksRegLiveness: true +frameInfo: + hasCalls: true +body: | + bb.0: + liveins: $x0, $x1 + ; CHECK-LABEL: name: inst_stores_to_dead_spill_implicit_def_impdef + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: STRXui $x0, %stack.0, 0 :: (store (s64) into %stack.0) + ; CHECK-NEXT: dead undef [[COPY:%[0-9]+]].sub_32:gpr64 = COPY $x1 + ; CHECK-NEXT: dead undef [[DEF:%[0-9]+]].sub_32:gpr64 = IMPLICIT_DEF implicit-def %6 + ; CHECK-NEXT: STRXui %6, %stack.1, 0 :: (store (s64) into %stack.1) + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0, 0 :: (load (s64) from %stack.0) + ; CHECK-NEXT: [[LDRXui1:%[0-9]+]]:gpr64 = LDRXui %stack.1, 0 :: (load (s64) from %stack.1) + ; CHECK-NEXT: STRXui [[LDRXui1]], [[LDRXui]], 1 :: (store (s64) into stack + 8) + ; CHECK-NEXT: STRXui undef %8:gpr64, [[LDRXui]], 0 :: (store (s64) into stack) + ; CHECK-NEXT: RET_ReallyLR + %0:gpr64sp = COPY $x0 + undef %1.sub_32:gpr64 = COPY $x1 + undef %2.sub_32:gpr64 = IMPLICIT_DEF implicit-def %1 + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + BL @foo, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + STRXui %1, %0, 1 :: (store (s64) into stack + 8) + STRXui undef %1, %0, 0 :: (store (s64) into stack) + RET_ReallyLR + +... + +# Same function, except with a rematerializable mov imm instead of +# IMPLICIT_DEF +--- +name: inst_stores_to_dead_spill_movimm_impdef +tracksRegLiveness: true +frameInfo: + hasCalls: true +body: | + bb.0: + liveins: $x0, $x1 + ; CHECK-LABEL: name: inst_stores_to_dead_spill_movimm_impdef + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: STRXui $x0, %stack.0, 0 :: (store (s64) into %stack.0) + ; CHECK-NEXT: dead undef [[COPY:%[0-9]+]].sub_32:gpr64 = COPY $x1 + ; CHECK-NEXT: dead undef [[MOVi32imm:%[0-9]+]].sub_32:gpr64 = MOVi32imm 4, implicit-def %6 + ; CHECK-NEXT: STRXui %6, %stack.1, 0 :: (store (s64) into %stack.1) + ; CHECK-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0, 0 :: (load (s64) from %stack.0) + ; CHECK-NEXT: [[LDRXui1:%[0-9]+]]:gpr64 = LDRXui %stack.1, 0 :: (load (s64) from %stack.1) + ; CHECK-NEXT: STRXui [[LDRXui1]], [[LDRXui]], 1 :: (store (s64) into stack + 8) + ; CHECK-NEXT: STRXui undef %8:gpr64, [[LDRXui]], 0 :: (store (s64) into stack) + ; CHECK-NEXT: RET_ReallyLR + %0:gpr64sp = COPY $x0 + undef %1.sub_32:gpr64 = COPY $x1 + undef %2.sub_32:gpr64 = MOVi32imm 4, implicit-def %1 + ADJCALLSTACKDOWN 8, 0, implicit-def dead $sp, implicit $sp + BL @foo, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ADJCALLSTACKUP 8, 0, implicit-def dead $sp, implicit $sp + STRXui %1, %0, 1 :: (store (s64) into stack + 8) + STRXui undef %1, %0, 0 :: (store (s64) into stack) + RET_ReallyLR + +... + diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x2.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x2.ll new file mode 100644 index 000000000000..8f9993cf00c5 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x2.ll @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s + +; lookup table expand one register + +define {, } @luti2_i8( %x) { +; CHECK-LABEL: luti2_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.b, z1.b }, zt0, z0[7] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %x, i32 7) + ret {, } %res +} + +define {, } @luti2_i16( %x) { +; CHECK-LABEL: luti2_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.h, z1.h }, zt0, z0[7] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, %x, i32 7) + ret {, } %res +} + +define {, } @luti2_i32( %x) { +; CHECK-LABEL: luti2_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.s, z1.s }, zt0, z0[7] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %x, i32 7) + ret {, } %res +} + +define {, } @luti2_f16( %x) { +; CHECK-LABEL: luti2_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.h, z1.h }, zt0, z0[7] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, %x, i32 7) + ret {, } %res +} + +define {, } @luti2_bf16( %x) { +; CHECK-LABEL: luti2_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.h, z1.h }, zt0, z0[7] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, %x, i32 7) + ret {, } %res +} + +define {, } @luti2_f32( %x) { +; CHECK-LABEL: luti2_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.s, z1.s }, zt0, z0[7] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, %x, i32 7) + ret {, } %res +} + +declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32, , i32) +declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32, , i32) +declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32, , i32) diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x4.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x4.ll new file mode 100644 index 000000000000..b5d9ff8afdd4 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane-x4.ll @@ -0,0 +1,66 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s + +; lookup table expand one register + +define {, , , } @luti2_i8( %x) { +; CHECK-LABEL: luti2_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.b - z3.b }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %x, i32 3) + ret {, , , } %res +} + +define {, , , } @luti2_i16( %x) { +; CHECK-LABEL: luti2_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.h - z3.h }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, %x, i32 3) + ret {, , , } %res +} + +define {, , , } @luti2_i32( %x) { +; CHECK-LABEL: luti2_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.s - z3.s }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, %x, i32 3) + ret {, , , }%res +} + +define {, , , } @luti2_f16( %x) { +; CHECK-LABEL: luti2_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.h - z3.h }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, %x, i32 3) + ret {, , , } %res +} + +define {, , , } @luti2_bf16( %x) { +; CHECK-LABEL: luti2_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.h - z3.h }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, %x, i32 3) + ret {, , , } %res +} + +define {, , , } @luti2_f32( %x) { +; CHECK-LABEL: luti2_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 { z0.s - z3.s }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, %x, i32 3) + ret {, , , }%res +} + + +declare {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32, , i32) +declare {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32, , i32) +declare {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32, , i32) +declare {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32, , i32) +declare {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32, , i32) +declare {, , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32, , i32) diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane.ll new file mode 100644 index 000000000000..1516e301196a --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti2-lane.ll @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s + +; lookup table expand one register + +define @luti2_i8( %x) { +; CHECK-LABEL: luti2_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 z0.b, zt0, z0[15] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %x, i32 15) + ret %res +} + +define @luti2_i16( %x) { +; CHECK-LABEL: luti2_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 z0.h, zt0, z0[15] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, %x, i32 15) + ret %res +} + +define @luti2_i32( %x) { +; CHECK-LABEL: luti2_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 z0.s, zt0, z0[15] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, %x, i32 15) + ret %res +} + +define @luti2_f16( %x) { +; CHECK-LABEL: luti2_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 z0.h, zt0, z0[15] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, %x, i32 15) + ret %res +} + +define @luti2_bf16( %x) { +; CHECK-LABEL: luti2_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 z0.h, zt0, z0[15] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, %x, i32 15) + ret %res +} + +define @luti2_f32( %x) { +; CHECK-LABEL: luti2_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti2 z0.s, zt0, z0[15] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, %x, i32 15) + ret %res +} + +declare @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32, , i32) +declare @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32, , i32) +declare @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32, , i32) +declare @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32, , i32) +declare @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32, , i32) +declare @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32, , i32) diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x2.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x2.ll new file mode 100644 index 000000000000..1be2253dd923 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x2.ll @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s + +; lookup table expand one register + +define {, } @luti4_i8( %x) { +; CHECK-LABEL: luti4_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.b, z1.b }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %x, i32 3) + ret {, } %res +} + +define {, } @luti4_i16( %x) { +; CHECK-LABEL: luti4_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.h, z1.h }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, %x, i32 3) + ret {, } %res +} + +define {, } @luti4_i32( %x) { +; CHECK-LABEL: luti4_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.s, z1.s }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, %x, i32 3) + ret {, } %res +} + +define {, } @luti4_f16( %x) { +; CHECK-LABEL: luti4_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.h, z1.h }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, %x, i32 3) + ret {, } %res +} + +define {, } @luti4_bf16( %x) { +; CHECK-LABEL: luti4_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.h, z1.h }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, %x, i32 3) + ret {, } %res +} + +define {, } @luti4_f32( %x) { +; CHECK-LABEL: luti4_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.s, z1.s }, zt0, z0[3] +; CHECK-NEXT: ret + %res = call {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, %x, i32 3) + ret {, } %res +} + +declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32, , i32) +declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32, , i32) +declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32, , i32) +declare {, } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32, , i32) diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x4.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x4.ll new file mode 100644 index 000000000000..0e47a3916c10 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x4.ll @@ -0,0 +1,55 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s + +; lookup table expand one register + +define {, , , } @luti4_i16( %x) { +; CHECK-LABEL: luti4_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.h - z3.h }, zt0, z0[1] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, %x, i32 1) + ret {, , , } %res +} + +define {, , , } @luti4_i32( %x) { +; CHECK-LABEL: luti4_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.s - z3.s }, zt0, z0[1] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, %x, i32 1) + ret {, , , } %res +} + +define {, , , } @luti4_bf16( %x) { +; CHECK-LABEL: luti4_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.h - z3.h }, zt0, z0[1] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, %x, i32 1) + ret {, , , } %res +} + +define {, , , } @luti4_f16( %x) { +; CHECK-LABEL: luti4_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.h - z3.h }, zt0, z0[1] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, %x, i32 1) + ret {, , , } %res +} + +define {, , , } @luti4_f32( %x) { +; CHECK-LABEL: luti4_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 { z0.s - z3.s }, zt0, z0[1] +; CHECK-NEXT: ret + %res = call {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, %x, i32 1) + ret {, , , } %res +} + +declare {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32, , i32) +declare {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32, , i32) +declare {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32, , i32) +declare {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32, , i32) +declare {, , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32, , i32) diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane.ll new file mode 100644 index 000000000000..6202398b1534 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane.ll @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s + +; lookup table expand one register + +define @luti4_i8( %x) { +; CHECK-LABEL: luti4_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 z0.b, zt0, z0[7] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %x, i32 7) + ret %res +} + +define @luti4_i16( %x) { +; CHECK-LABEL: luti4_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 z0.h, zt0, z0[7] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, %x, i32 7) + ret %res +} + +define @luti4_i32( %x) { +; CHECK-LABEL: luti4_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 z0.s, zt0, z0[7] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, %x, i32 7) + ret %res +} + +define @luti4_f16( %x) { +; CHECK-LABEL: luti4_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 z0.h, zt0, z0[7] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, %x, i32 7) + ret %res +} + +define @luti4_bf16( %x) { +; CHECK-LABEL: luti4_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 z0.h, zt0, z0[7] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, %x, i32 7) + ret %res +} + +define @luti4_f32( %x) { +; CHECK-LABEL: luti4_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: luti4 z0.s, zt0, z0[7] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, %x, i32 7) + ret %res +} + +declare @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32, , i32) +declare @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32, , i32) +declare @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32, , i32) +declare @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32, , i32) +declare @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32, , i32) +declare @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32, , i32) diff --git a/llvm/test/CodeGen/AArch64/store-swift-async-context-clobber-live-reg.ll b/llvm/test/CodeGen/AArch64/store-swift-async-context-clobber-live-reg.ll index 217fb9bbfbeb..a202bfb6bca4 100644 --- a/llvm/test/CodeGen/AArch64/store-swift-async-context-clobber-live-reg.ll +++ b/llvm/test/CodeGen/AArch64/store-swift-async-context-clobber-live-reg.ll @@ -1,10 +1,64 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: not --crash llc -o - -mtriple=arm64e-apple-macosx -aarch64-min-jump-table-entries=2 %s -; REQUIRES: asserts +; RUN: llc -o - -mtriple=arm64e-apple-macosx -aarch64-min-jump-table-entries=2 %s | FileCheck %s target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" define swifttailcc void @test_async_with_jumptable_x16_clobbered(ptr %src, ptr swiftasync %as) #0 { +; CHECK-LABEL: test_async_with_jumptable_x16_clobbered: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: orr x29, x29, #0x1000000000000000 +; CHECK-NEXT: str x19, [sp, #-32]! ; 8-byte Folded Spill +; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill +; CHECK-NEXT: add x16, sp, #8 +; CHECK-NEXT: movk x16, #49946, lsl #48 +; CHECK-NEXT: mov x17, x22 +; CHECK-NEXT: pacdb x17, x16 +; CHECK-NEXT: str x17, [sp, #8] +; CHECK-NEXT: add x29, sp, #16 +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: .cfi_offset w19, -32 +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: mov x20, x22 +; CHECK-NEXT: mov x22, x0 +; CHECK-NEXT: Lloh0: +; CHECK-NEXT: adrp x9, LJTI0_0@PAGE +; CHECK-NEXT: Lloh1: +; CHECK-NEXT: add x9, x9, LJTI0_0@PAGEOFF +; CHECK-NEXT: Ltmp0: +; CHECK-NEXT: adr x10, Ltmp0 +; CHECK-NEXT: ldrsw x11, [x9, x8, lsl #2] +; CHECK-NEXT: add x10, x10, x11 +; CHECK-NEXT: mov x19, x20 +; CHECK-NEXT: br x10 +; CHECK-NEXT: LBB0_1: ; %then.2 +; CHECK-NEXT: mov x19, #0 ; =0x0 +; CHECK-NEXT: b LBB0_3 +; CHECK-NEXT: LBB0_2: ; %then.3 +; CHECK-NEXT: mov x19, x22 +; CHECK-NEXT: LBB0_3: ; %exit +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: bl _foo +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: mov x0, x19 +; CHECK-NEXT: mov x1, x20 +; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload +; CHECK-NEXT: ldr x19, [sp], #32 ; 8-byte Folded Reload +; CHECK-NEXT: and x29, x29, #0xefffffffffffffff +; CHECK-NEXT: br x2 +; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1 +; CHECK-NEXT: .cfi_endproc +; CHECK-NEXT: .section __TEXT,__const +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: LJTI0_0: +; CHECK-NEXT: .long LBB0_3-Ltmp0 +; CHECK-NEXT: .long LBB0_1-Ltmp0 +; CHECK-NEXT: .long LBB0_1-Ltmp0 +; CHECK-NEXT: .long LBB0_2-Ltmp0 entry: %x16 = tail call i64 asm "", "={x16}"() %l = load i64, ptr %src, align 8 @@ -37,6 +91,61 @@ exit: } define swifttailcc void @test_async_with_jumptable_x17_clobbered(ptr %src, ptr swiftasync %as) #0 { +; CHECK-LABEL: test_async_with_jumptable_x17_clobbered: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: orr x29, x29, #0x1000000000000000 +; CHECK-NEXT: str x19, [sp, #-32]! ; 8-byte Folded Spill +; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill +; CHECK-NEXT: add x16, sp, #8 +; CHECK-NEXT: movk x16, #49946, lsl #48 +; CHECK-NEXT: mov x17, x22 +; CHECK-NEXT: pacdb x17, x16 +; CHECK-NEXT: str x17, [sp, #8] +; CHECK-NEXT: add x29, sp, #16 +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: .cfi_offset w19, -32 +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: mov x20, x22 +; CHECK-NEXT: mov x22, x0 +; CHECK-NEXT: Lloh2: +; CHECK-NEXT: adrp x9, LJTI1_0@PAGE +; CHECK-NEXT: Lloh3: +; CHECK-NEXT: add x9, x9, LJTI1_0@PAGEOFF +; CHECK-NEXT: Ltmp1: +; CHECK-NEXT: adr x10, Ltmp1 +; CHECK-NEXT: ldrsw x11, [x9, x8, lsl #2] +; CHECK-NEXT: add x10, x10, x11 +; CHECK-NEXT: mov x19, x20 +; CHECK-NEXT: br x10 +; CHECK-NEXT: LBB1_1: ; %then.2 +; CHECK-NEXT: mov x19, #0 ; =0x0 +; CHECK-NEXT: b LBB1_3 +; CHECK-NEXT: LBB1_2: ; %then.3 +; CHECK-NEXT: mov x19, x22 +; CHECK-NEXT: LBB1_3: ; %exit +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: bl _foo +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: mov x0, x19 +; CHECK-NEXT: mov x1, x20 +; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload +; CHECK-NEXT: ldr x19, [sp], #32 ; 8-byte Folded Reload +; CHECK-NEXT: and x29, x29, #0xefffffffffffffff +; CHECK-NEXT: br x2 +; CHECK-NEXT: .loh AdrpAdd Lloh2, Lloh3 +; CHECK-NEXT: .cfi_endproc +; CHECK-NEXT: .section __TEXT,__const +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: LJTI1_0: +; CHECK-NEXT: .long LBB1_3-Ltmp1 +; CHECK-NEXT: .long LBB1_1-Ltmp1 +; CHECK-NEXT: .long LBB1_1-Ltmp1 +; CHECK-NEXT: .long LBB1_2-Ltmp1 entry: %x17 = tail call i64 asm "", "={x17}"() %l = load i64, ptr %src, align 8 @@ -69,6 +178,61 @@ exit: } define swifttailcc void @test_async_with_jumptable_x1_clobbered(ptr %src, ptr swiftasync %as) #0 { +; CHECK-LABEL: test_async_with_jumptable_x1_clobbered: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: orr x29, x29, #0x1000000000000000 +; CHECK-NEXT: str x19, [sp, #-32]! ; 8-byte Folded Spill +; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill +; CHECK-NEXT: add x16, sp, #8 +; CHECK-NEXT: movk x16, #49946, lsl #48 +; CHECK-NEXT: mov x17, x22 +; CHECK-NEXT: pacdb x17, x16 +; CHECK-NEXT: str x17, [sp, #8] +; CHECK-NEXT: add x29, sp, #16 +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: .cfi_offset w19, -32 +; CHECK-NEXT: mov x20, x22 +; CHECK-NEXT: mov x22, x0 +; CHECK-NEXT: Lloh4: +; CHECK-NEXT: adrp x9, LJTI2_0@PAGE +; CHECK-NEXT: Lloh5: +; CHECK-NEXT: add x9, x9, LJTI2_0@PAGEOFF +; CHECK-NEXT: Ltmp2: +; CHECK-NEXT: adr x10, Ltmp2 +; CHECK-NEXT: ldrsw x11, [x9, x8, lsl #2] +; CHECK-NEXT: add x10, x10, x11 +; CHECK-NEXT: mov x19, x20 +; CHECK-NEXT: br x10 +; CHECK-NEXT: LBB2_1: ; %then.2 +; CHECK-NEXT: mov x19, #0 ; =0x0 +; CHECK-NEXT: b LBB2_3 +; CHECK-NEXT: LBB2_2: ; %then.3 +; CHECK-NEXT: mov x19, x22 +; CHECK-NEXT: LBB2_3: ; %exit +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: bl _foo +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: mov x0, x19 +; CHECK-NEXT: mov x1, x20 +; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload +; CHECK-NEXT: ldr x19, [sp], #32 ; 8-byte Folded Reload +; CHECK-NEXT: and x29, x29, #0xefffffffffffffff +; CHECK-NEXT: br x2 +; CHECK-NEXT: .loh AdrpAdd Lloh4, Lloh5 +; CHECK-NEXT: .cfi_endproc +; CHECK-NEXT: .section __TEXT,__const +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: LJTI2_0: +; CHECK-NEXT: .long LBB2_3-Ltmp2 +; CHECK-NEXT: .long LBB2_1-Ltmp2 +; CHECK-NEXT: .long LBB2_1-Ltmp2 +; CHECK-NEXT: .long LBB2_2-Ltmp2 entry: %x1 = tail call i64 asm "", "={x1}"() %l = load i64, ptr %src, align 8 @@ -101,6 +265,65 @@ exit: } define swifttailcc void @test_async_with_jumptable_x1_x9_clobbered(ptr %src, ptr swiftasync %as) #0 { +; CHECK-LABEL: test_async_with_jumptable_x1_x9_clobbered: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: orr x29, x29, #0x1000000000000000 +; CHECK-NEXT: str x19, [sp, #-32]! ; 8-byte Folded Spill +; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill +; CHECK-NEXT: add x16, sp, #8 +; CHECK-NEXT: movk x16, #49946, lsl #48 +; CHECK-NEXT: mov x17, x22 +; CHECK-NEXT: pacdb x17, x16 +; CHECK-NEXT: str x17, [sp, #8] +; CHECK-NEXT: add x29, sp, #16 +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: .cfi_offset w19, -32 +; CHECK-NEXT: mov x20, x22 +; CHECK-NEXT: mov x22, x0 +; CHECK-NEXT: Lloh6: +; CHECK-NEXT: adrp x10, LJTI3_0@PAGE +; CHECK-NEXT: Lloh7: +; CHECK-NEXT: add x10, x10, LJTI3_0@PAGEOFF +; CHECK-NEXT: Ltmp3: +; CHECK-NEXT: adr x11, Ltmp3 +; CHECK-NEXT: ldrsw x12, [x10, x8, lsl #2] +; CHECK-NEXT: add x11, x11, x12 +; CHECK-NEXT: mov x19, x20 +; CHECK-NEXT: br x11 +; CHECK-NEXT: LBB3_1: ; %then.2 +; CHECK-NEXT: mov x19, #0 ; =0x0 +; CHECK-NEXT: b LBB3_3 +; CHECK-NEXT: LBB3_2: ; %then.3 +; CHECK-NEXT: mov x19, x22 +; CHECK-NEXT: LBB3_3: ; %exit +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: bl _foo +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: mov x0, x19 +; CHECK-NEXT: mov x1, x20 +; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload +; CHECK-NEXT: ldr x19, [sp], #32 ; 8-byte Folded Reload +; CHECK-NEXT: and x29, x29, #0xefffffffffffffff +; CHECK-NEXT: br x2 +; CHECK-NEXT: .loh AdrpAdd Lloh6, Lloh7 +; CHECK-NEXT: .cfi_endproc +; CHECK-NEXT: .section __TEXT,__const +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: LJTI3_0: +; CHECK-NEXT: .long LBB3_3-Ltmp3 +; CHECK-NEXT: .long LBB3_1-Ltmp3 +; CHECK-NEXT: .long LBB3_1-Ltmp3 +; CHECK-NEXT: .long LBB3_2-Ltmp3 entry: %x1 = tail call i64 asm "", "={x1}"() %x9 = tail call i64 asm "", "={x9}"() @@ -136,6 +359,117 @@ exit: ; There are 2 available scratch registers left, shrink-wrapping can happen. define swifttailcc void @test_async_with_jumptable_2_available_regs_left(ptr %src, ptr swiftasync %as) #0 { +; CHECK-LABEL: test_async_with_jumptable_2_available_regs_left: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: orr x29, x29, #0x1000000000000000 +; CHECK-NEXT: str x19, [sp, #-32]! ; 8-byte Folded Spill +; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill +; CHECK-NEXT: add x16, sp, #8 +; CHECK-NEXT: movk x16, #49946, lsl #48 +; CHECK-NEXT: mov x17, x22 +; CHECK-NEXT: pacdb x17, x16 +; CHECK-NEXT: str x17, [sp, #8] +; CHECK-NEXT: add x29, sp, #16 +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: .cfi_offset w19, -32 +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ldr x10, [x0] +; CHECK-NEXT: mov x20, x22 +; CHECK-NEXT: mov x22, x0 +; CHECK-NEXT: Lloh8: +; CHECK-NEXT: adrp x17, LJTI4_0@PAGE +; CHECK-NEXT: Lloh9: +; CHECK-NEXT: add x17, x17, LJTI4_0@PAGEOFF +; CHECK-NEXT: Ltmp4: +; CHECK-NEXT: adr x0, Ltmp4 +; CHECK-NEXT: ldrsw x19, [x17, x10, lsl #2] +; CHECK-NEXT: add x0, x0, x19 +; CHECK-NEXT: mov x19, x20 +; CHECK-NEXT: br x0 +; CHECK-NEXT: LBB4_1: ; %then.2 +; CHECK-NEXT: mov x19, #0 ; =0x0 +; CHECK-NEXT: b LBB4_3 +; CHECK-NEXT: LBB4_2: ; %then.3 +; CHECK-NEXT: mov x19, x22 +; CHECK-NEXT: LBB4_3: ; %exit +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: bl _foo +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: mov x0, x19 +; CHECK-NEXT: mov x1, x20 +; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload +; CHECK-NEXT: ldr x19, [sp], #32 ; 8-byte Folded Reload +; CHECK-NEXT: and x29, x29, #0xefffffffffffffff +; CHECK-NEXT: br x2 +; CHECK-NEXT: .loh AdrpAdd Lloh8, Lloh9 +; CHECK-NEXT: .cfi_endproc +; CHECK-NEXT: .section __TEXT,__const +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: LJTI4_0: +; CHECK-NEXT: .long LBB4_3-Ltmp4 +; CHECK-NEXT: .long LBB4_1-Ltmp4 +; CHECK-NEXT: .long LBB4_1-Ltmp4 +; CHECK-NEXT: .long LBB4_2-Ltmp4 entry: %x1 = tail call i64 asm "", "={x1}"() %x2 = tail call i64 asm "", "={x2}"() @@ -198,6 +532,124 @@ exit: ; There is only 1 available scratch registers left, shrink-wrapping cannot ; happen because StoreSwiftAsyncContext needs 2 free scratch registers. define swifttailcc void @test_async_with_jumptable_1_available_reg_left(ptr %src, ptr swiftasync %as) #0 { +; CHECK-LABEL: test_async_with_jumptable_1_available_reg_left: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: orr x29, x29, #0x1000000000000000 +; CHECK-NEXT: sub sp, sp, #48 +; CHECK-NEXT: stp x21, x19, [sp, #8] ; 16-byte Folded Spill +; CHECK-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill +; CHECK-NEXT: add x16, sp, #24 +; CHECK-NEXT: movk x16, #49946, lsl #48 +; CHECK-NEXT: mov x17, x22 +; CHECK-NEXT: pacdb x17, x16 +; CHECK-NEXT: str x17, [sp, #24] +; CHECK-NEXT: add x29, sp, #32 +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: .cfi_offset w19, -32 +; CHECK-NEXT: .cfi_offset w21, -40 +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ldr x10, [x0] +; CHECK-NEXT: mov x20, x22 +; CHECK-NEXT: mov x22, x0 +; CHECK-NEXT: Lloh10: +; CHECK-NEXT: adrp x0, LJTI5_0@PAGE +; CHECK-NEXT: Lloh11: +; CHECK-NEXT: add x0, x0, LJTI5_0@PAGEOFF +; CHECK-NEXT: Ltmp5: +; CHECK-NEXT: adr x21, Ltmp5 +; CHECK-NEXT: ldrsw x19, [x0, x10, lsl #2] +; CHECK-NEXT: add x21, x21, x19 +; CHECK-NEXT: mov x19, x20 +; CHECK-NEXT: br x21 +; CHECK-NEXT: LBB5_1: ; %then.2 +; CHECK-NEXT: mov x19, #0 ; =0x0 +; CHECK-NEXT: b LBB5_3 +; CHECK-NEXT: LBB5_2: ; %then.3 +; CHECK-NEXT: mov x19, x22 +; CHECK-NEXT: LBB5_3: ; %exit +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: ; InlineAsm Start +; CHECK-NEXT: ; InlineAsm End +; CHECK-NEXT: bl _foo +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: mov x0, x19 +; CHECK-NEXT: mov x1, x20 +; CHECK-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload +; CHECK-NEXT: ldp x21, x19, [sp, #8] ; 16-byte Folded Reload +; CHECK-NEXT: and x29, x29, #0xefffffffffffffff +; CHECK-NEXT: add sp, sp, #48 +; CHECK-NEXT: br x2 +; CHECK-NEXT: .loh AdrpAdd Lloh10, Lloh11 +; CHECK-NEXT: .cfi_endproc +; CHECK-NEXT: .section __TEXT,__const +; CHECK-NEXT: .p2align 2, 0x0 +; CHECK-NEXT: LJTI5_0: +; CHECK-NEXT: .long LBB5_3-Ltmp5 +; CHECK-NEXT: .long LBB5_1-Ltmp5 +; CHECK-NEXT: .long LBB5_1-Ltmp5 +; CHECK-NEXT: .long LBB5_2-Ltmp5 entry: %x1 = tail call i64 asm "", "={x1}"() %x2 = tail call i64 asm "", "={x2}"() diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll index 69346de9bb79..80dc3dead35a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll @@ -124,71 +124,71 @@ define float @test_add_mul_multiple_defs_z(float %x, float %y, ptr addrspace(1) ; GFX9-LABEL: test_add_mul_multiple_defs_z: ; GFX9: ; %bb.0: ; %.entry ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX9-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_add_f32_e32 v0, v0, v3 +; GFX9-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-CONTRACT-LABEL: test_add_mul_multiple_defs_z: ; GFX9-CONTRACT: ; %bb.0: ; %.entry ; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-CONTRACT-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX9-CONTRACT-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) -; GFX9-CONTRACT-NEXT: v_fma_f32 v0, v0, v1, v3 +; GFX9-CONTRACT-NEXT: v_fma_f32 v0, v0, v1, v2 ; GFX9-CONTRACT-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-DENORM-LABEL: test_add_mul_multiple_defs_z: ; GFX9-DENORM: ; %bb.0: ; %.entry ; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-DENORM-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX9-DENORM-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) -; GFX9-DENORM-NEXT: v_mac_f32_e32 v3, v0, v1 -; GFX9-DENORM-NEXT: v_mov_b32_e32 v0, v3 +; GFX9-DENORM-NEXT: v_mac_f32_e32 v2, v0, v1 +; GFX9-DENORM-NEXT: v_mov_b32_e32 v0, v2 ; GFX9-DENORM-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-UNSAFE-LABEL: test_add_mul_multiple_defs_z: ; GFX9-UNSAFE: ; %bb.0: ; %.entry ; GFX9-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-UNSAFE-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX9-UNSAFE-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX9-UNSAFE-NEXT: s_waitcnt vmcnt(0) -; GFX9-UNSAFE-NEXT: v_fma_f32 v0, v0, v1, v3 +; GFX9-UNSAFE-NEXT: v_fma_f32 v0, v0, v1, v2 ; GFX9-UNSAFE-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_add_mul_multiple_defs_z: ; GFX10: ; %bb.0: ; %.entry ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX10-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add_f32_e32 v0, v0, v3 +; GFX10-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-CONTRACT-LABEL: test_add_mul_multiple_defs_z: ; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-CONTRACT-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX10-CONTRACT-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) -; GFX10-CONTRACT-NEXT: v_fmac_f32_e32 v3, v0, v1 -; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v3 +; GFX10-CONTRACT-NEXT: v_fmac_f32_e32 v2, v0, v1 +; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-DENORM-LABEL: test_add_mul_multiple_defs_z: ; GFX10-DENORM: ; %bb.0: ; %.entry ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-DENORM-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX10-DENORM-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) -; GFX10-DENORM-NEXT: v_mac_f32_e32 v3, v0, v1 -; GFX10-DENORM-NEXT: v_mov_b32_e32 v0, v3 +; GFX10-DENORM-NEXT: v_mac_f32_e32 v2, v0, v1 +; GFX10-DENORM-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-DENORM-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-UNSAFE-LABEL: test_add_mul_multiple_defs_z: ; GFX10-UNSAFE: ; %bb.0: ; %.entry ; GFX10-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-UNSAFE-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX10-UNSAFE-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX10-UNSAFE-NEXT: s_waitcnt vmcnt(0) -; GFX10-UNSAFE-NEXT: v_fmac_f32_e32 v3, v0, v1 -; GFX10-UNSAFE-NEXT: v_mov_b32_e32 v0, v3 +; GFX10-UNSAFE-NEXT: v_fmac_f32_e32 v2, v0, v1 +; GFX10-UNSAFE-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-UNSAFE-NEXT: s_setpc_b64 s[30:31] .entry: %a = fmul float %x, %y @@ -202,71 +202,71 @@ define float @test_add_mul_rhs_multiple_defs_z(float %x, float %y, ptr addrspace ; GFX9-LABEL: test_add_mul_rhs_multiple_defs_z: ; GFX9: ; %bb.0: ; %.entry ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX9-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_add_f32_e32 v0, v3, v0 +; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-CONTRACT-LABEL: test_add_mul_rhs_multiple_defs_z: ; GFX9-CONTRACT: ; %bb.0: ; %.entry ; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-CONTRACT-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX9-CONTRACT-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX9-CONTRACT-NEXT: s_waitcnt vmcnt(0) -; GFX9-CONTRACT-NEXT: v_fma_f32 v0, v0, v1, v3 +; GFX9-CONTRACT-NEXT: v_fma_f32 v0, v0, v1, v2 ; GFX9-CONTRACT-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-DENORM-LABEL: test_add_mul_rhs_multiple_defs_z: ; GFX9-DENORM: ; %bb.0: ; %.entry ; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-DENORM-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX9-DENORM-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX9-DENORM-NEXT: s_waitcnt vmcnt(0) -; GFX9-DENORM-NEXT: v_mac_f32_e32 v3, v0, v1 -; GFX9-DENORM-NEXT: v_mov_b32_e32 v0, v3 +; GFX9-DENORM-NEXT: v_mac_f32_e32 v2, v0, v1 +; GFX9-DENORM-NEXT: v_mov_b32_e32 v0, v2 ; GFX9-DENORM-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-UNSAFE-LABEL: test_add_mul_rhs_multiple_defs_z: ; GFX9-UNSAFE: ; %bb.0: ; %.entry ; GFX9-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-UNSAFE-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX9-UNSAFE-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX9-UNSAFE-NEXT: s_waitcnt vmcnt(0) -; GFX9-UNSAFE-NEXT: v_fma_f32 v0, v0, v1, v3 +; GFX9-UNSAFE-NEXT: v_fma_f32 v0, v0, v1, v2 ; GFX9-UNSAFE-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_add_mul_rhs_multiple_defs_z: ; GFX10: ; %bb.0: ; %.entry ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX10-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_add_f32_e32 v0, v3, v0 +; GFX10-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-CONTRACT-LABEL: test_add_mul_rhs_multiple_defs_z: ; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-CONTRACT-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX10-CONTRACT-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX10-CONTRACT-NEXT: s_waitcnt vmcnt(0) -; GFX10-CONTRACT-NEXT: v_fmac_f32_e32 v3, v0, v1 -; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v3 +; GFX10-CONTRACT-NEXT: v_fmac_f32_e32 v2, v0, v1 +; GFX10-CONTRACT-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-CONTRACT-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-DENORM-LABEL: test_add_mul_rhs_multiple_defs_z: ; GFX10-DENORM: ; %bb.0: ; %.entry ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-DENORM-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX10-DENORM-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX10-DENORM-NEXT: s_waitcnt vmcnt(0) -; GFX10-DENORM-NEXT: v_mac_f32_e32 v3, v0, v1 -; GFX10-DENORM-NEXT: v_mov_b32_e32 v0, v3 +; GFX10-DENORM-NEXT: v_mac_f32_e32 v2, v0, v1 +; GFX10-DENORM-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-DENORM-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-UNSAFE-LABEL: test_add_mul_rhs_multiple_defs_z: ; GFX10-UNSAFE: ; %bb.0: ; %.entry ; GFX10-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-UNSAFE-NEXT: global_load_dwordx2 v[2:3], v[2:3], off +; GFX10-UNSAFE-NEXT: global_load_dword v2, v[2:3], off offset:4 ; GFX10-UNSAFE-NEXT: s_waitcnt vmcnt(0) -; GFX10-UNSAFE-NEXT: v_fmac_f32_e32 v3, v0, v1 -; GFX10-UNSAFE-NEXT: v_mov_b32_e32 v0, v3 +; GFX10-UNSAFE-NEXT: v_fmac_f32_e32 v2, v0, v1 +; GFX10-UNSAFE-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-UNSAFE-NEXT: s_setpc_b64 s[30:31] .entry: %a = fmul float %x, %y diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll index 33a4d3c5494f..a13c60b4e841 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll @@ -8,170 +8,12 @@ define i32 @v_extract_v64i32_varidx(ptr addrspace(1) %ptr, i32 %idx) { ; GCN-LABEL: v_extract_v64i32_varidx: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_add_i32 s33, s32, 0x3fc0 -; GCN-NEXT: s_and_b32 s33, s33, 0xffffc000 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: v_mov_b32_e32 v6, v2 -; GCN-NEXT: global_load_dwordx4 v[2:5], v[0:1], off -; GCN-NEXT: global_load_dwordx4 v[16:19], v[0:1], off offset:16 -; GCN-NEXT: global_load_dwordx4 v[56:59], v[0:1], off offset:32 -; GCN-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:48 -; GCN-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:64 -; GCN-NEXT: global_load_dwordx4 v[44:47], v[0:1], off offset:80 -; GCN-NEXT: global_load_dwordx4 v[40:43], v[0:1], off offset:96 -; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:112 -; GCN-NEXT: global_load_dwordx4 v[36:39], v[0:1], off offset:128 -; GCN-NEXT: global_load_dwordx4 v[32:35], v[0:1], off offset:144 -; GCN-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:160 -; GCN-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:176 -; GCN-NEXT: global_load_dwordx4 v[24:27], v[0:1], off offset:192 -; GCN-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:208 -; GCN-NEXT: s_add_i32 s32, s32, 0x10000 -; GCN-NEXT: s_add_i32 s32, s32, 0xffff0000 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill -; GCN-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:224 -; GCN-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:240 -; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33 -; GCN-NEXT: v_add_u32_e32 v1, 0x100, v1 -; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:256 -; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:260 -; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:264 -; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:268 -; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:272 -; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:276 -; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:280 -; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:284 -; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:288 -; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:292 -; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:296 -; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:300 -; GCN-NEXT: buffer_store_dword v48, off, s[0:3], s33 offset:304 -; GCN-NEXT: buffer_store_dword v49, off, s[0:3], s33 offset:308 -; GCN-NEXT: buffer_store_dword v50, off, s[0:3], s33 offset:312 -; GCN-NEXT: buffer_store_dword v51, off, s[0:3], s33 offset:316 -; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s33 offset:320 -; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s33 offset:324 -; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s33 offset:328 -; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s33 offset:332 -; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:336 -; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:340 -; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:344 -; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:348 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:352 -; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:356 -; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:360 -; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:364 -; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:368 -; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:372 -; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:376 -; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:380 -; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s33 offset:384 -; GCN-NEXT: buffer_store_dword v37, off, s[0:3], s33 offset:388 -; GCN-NEXT: buffer_store_dword v38, off, s[0:3], s33 offset:392 -; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:396 -; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:400 -; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s33 offset:404 -; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s33 offset:408 -; GCN-NEXT: buffer_store_dword v35, off, s[0:3], s33 offset:412 -; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s33 offset:416 -; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s33 offset:420 -; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s33 offset:424 -; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s33 offset:428 -; GCN-NEXT: buffer_store_dword v52, off, s[0:3], s33 offset:432 -; GCN-NEXT: buffer_store_dword v53, off, s[0:3], s33 offset:436 -; GCN-NEXT: buffer_store_dword v54, off, s[0:3], s33 offset:440 -; GCN-NEXT: buffer_store_dword v55, off, s[0:3], s33 offset:444 -; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s33 offset:448 -; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s33 offset:452 -; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s33 offset:456 -; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s33 offset:460 -; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload -; GCN-NEXT: v_and_b32_e32 v0, 63, v6 -; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GCN-NEXT: v_add_u32_e32 v0, v1, v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v16, v20 -; GCN-NEXT: v_mov_b32_e32 v17, v21 -; GCN-NEXT: v_mov_b32_e32 v18, v22 -; GCN-NEXT: v_mov_b32_e32 v19, v23 -; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:464 -; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:468 -; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:472 -; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:476 -; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:480 -; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:484 -; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:488 -; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:492 -; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:496 -; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:500 -; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:504 -; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:508 -; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen -; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b32 s33, s4 +; GCN-NEXT: v_and_b32_e32 v2, 63, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v2 +; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GCN-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GCN-NEXT: global_load_dword v0, v[0:1], off ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_setpc_b64 s[30:31] %vec = load <64 x i32>, ptr addrspace(1) %ptr @@ -183,174 +25,12 @@ define i16 @v_extract_v128i16_varidx(ptr addrspace(1) %ptr, i32 %idx) { ; GCN-LABEL: v_extract_v128i16_varidx: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_add_i32 s33, s32, 0x3fc0 -; GCN-NEXT: s_and_b32 s33, s33, 0xffffc000 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: v_mov_b32_e32 v6, v2 -; GCN-NEXT: global_load_dwordx4 v[2:5], v[0:1], off -; GCN-NEXT: global_load_dwordx4 v[16:19], v[0:1], off offset:16 -; GCN-NEXT: global_load_dwordx4 v[56:59], v[0:1], off offset:32 -; GCN-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:48 -; GCN-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:64 -; GCN-NEXT: global_load_dwordx4 v[44:47], v[0:1], off offset:80 -; GCN-NEXT: global_load_dwordx4 v[40:43], v[0:1], off offset:96 -; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:112 -; GCN-NEXT: global_load_dwordx4 v[36:39], v[0:1], off offset:128 -; GCN-NEXT: global_load_dwordx4 v[32:35], v[0:1], off offset:144 -; GCN-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:160 -; GCN-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:176 -; GCN-NEXT: global_load_dwordx4 v[24:27], v[0:1], off offset:192 -; GCN-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:208 -; GCN-NEXT: s_add_i32 s32, s32, 0x10000 -; GCN-NEXT: s_add_i32 s32, s32, 0xffff0000 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill -; GCN-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:224 -; GCN-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:240 -; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33 -; GCN-NEXT: v_add_u32_e32 v1, 0x100, v1 -; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:256 -; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:260 -; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:264 -; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:268 -; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:272 -; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:276 -; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:280 -; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:284 -; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:288 -; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:292 -; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:296 -; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:300 -; GCN-NEXT: buffer_store_dword v48, off, s[0:3], s33 offset:304 -; GCN-NEXT: buffer_store_dword v49, off, s[0:3], s33 offset:308 -; GCN-NEXT: buffer_store_dword v50, off, s[0:3], s33 offset:312 -; GCN-NEXT: buffer_store_dword v51, off, s[0:3], s33 offset:316 -; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s33 offset:320 -; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s33 offset:324 -; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s33 offset:328 -; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s33 offset:332 -; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:336 -; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:340 -; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:344 -; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:348 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:352 -; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:356 -; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:360 -; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:364 -; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:368 -; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:372 -; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:376 -; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:380 -; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s33 offset:384 -; GCN-NEXT: buffer_store_dword v37, off, s[0:3], s33 offset:388 -; GCN-NEXT: buffer_store_dword v38, off, s[0:3], s33 offset:392 -; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:396 -; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:400 -; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s33 offset:404 -; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s33 offset:408 -; GCN-NEXT: buffer_store_dword v35, off, s[0:3], s33 offset:412 -; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s33 offset:416 -; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s33 offset:420 -; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s33 offset:424 -; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s33 offset:428 -; GCN-NEXT: buffer_store_dword v52, off, s[0:3], s33 offset:432 -; GCN-NEXT: buffer_store_dword v53, off, s[0:3], s33 offset:436 -; GCN-NEXT: buffer_store_dword v54, off, s[0:3], s33 offset:440 -; GCN-NEXT: buffer_store_dword v55, off, s[0:3], s33 offset:444 -; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s33 offset:448 -; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s33 offset:452 -; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s33 offset:456 -; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s33 offset:460 -; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload -; GCN-NEXT: v_bfe_u32 v0, v6, 1, 6 -; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GCN-NEXT: v_add_u32_e32 v0, v1, v0 -; GCN-NEXT: v_and_b32_e32 v1, 1, v6 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 4, v1 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v16, v20 -; GCN-NEXT: v_mov_b32_e32 v17, v21 -; GCN-NEXT: v_mov_b32_e32 v18, v22 -; GCN-NEXT: v_mov_b32_e32 v19, v23 -; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:464 -; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:468 -; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:472 -; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:476 -; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:480 -; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:484 -; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:488 -; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:492 -; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:496 -; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:500 -; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:504 -; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:508 -; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen -; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b32 s33, s4 -; GCN-NEXT: s_waitcnt vmcnt(16) -; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 +; GCN-NEXT: v_and_b32_e32 v2, 0x7f, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GCN-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GCN-NEXT: global_load_ushort v0, v[0:1], off ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_setpc_b64 s[30:31] %vec = load <128 x i16>, ptr addrspace(1) %ptr @@ -362,171 +42,12 @@ define i64 @v_extract_v32i64_varidx(ptr addrspace(1) %ptr, i32 %idx) { ; GCN-LABEL: v_extract_v32i64_varidx: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s33 -; GCN-NEXT: s_add_i32 s33, s32, 0x3fc0 -; GCN-NEXT: s_and_b32 s33, s33, 0xffffc000 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 ; 4-byte Folded Spill -; GCN-NEXT: v_mov_b32_e32 v6, v2 -; GCN-NEXT: global_load_dwordx4 v[2:5], v[0:1], off -; GCN-NEXT: global_load_dwordx4 v[16:19], v[0:1], off offset:16 -; GCN-NEXT: global_load_dwordx4 v[56:59], v[0:1], off offset:32 -; GCN-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:48 -; GCN-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:64 -; GCN-NEXT: global_load_dwordx4 v[44:47], v[0:1], off offset:80 -; GCN-NEXT: global_load_dwordx4 v[40:43], v[0:1], off offset:96 -; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:112 -; GCN-NEXT: global_load_dwordx4 v[36:39], v[0:1], off offset:128 -; GCN-NEXT: global_load_dwordx4 v[32:35], v[0:1], off offset:144 -; GCN-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:160 -; GCN-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:176 -; GCN-NEXT: global_load_dwordx4 v[24:27], v[0:1], off offset:192 -; GCN-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:208 -; GCN-NEXT: s_add_i32 s32, s32, 0x10000 -; GCN-NEXT: s_add_i32 s32, s32, 0xffff0000 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill -; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill -; GCN-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:224 -; GCN-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:240 -; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:256 -; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:260 -; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:264 -; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:268 -; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:272 -; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:276 -; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:280 -; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:284 -; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:288 -; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:292 -; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:296 -; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:300 -; GCN-NEXT: buffer_store_dword v48, off, s[0:3], s33 offset:304 -; GCN-NEXT: buffer_store_dword v49, off, s[0:3], s33 offset:308 -; GCN-NEXT: buffer_store_dword v50, off, s[0:3], s33 offset:312 -; GCN-NEXT: buffer_store_dword v51, off, s[0:3], s33 offset:316 -; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s33 offset:320 -; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s33 offset:324 -; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s33 offset:328 -; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s33 offset:332 -; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:336 -; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:340 -; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:344 -; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:348 -; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:352 -; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:356 -; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:360 -; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:364 -; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:368 -; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:372 -; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:376 -; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:380 -; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s33 offset:384 -; GCN-NEXT: buffer_store_dword v37, off, s[0:3], s33 offset:388 -; GCN-NEXT: buffer_store_dword v38, off, s[0:3], s33 offset:392 -; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:396 -; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:400 -; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s33 offset:404 -; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s33 offset:408 -; GCN-NEXT: buffer_store_dword v35, off, s[0:3], s33 offset:412 -; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s33 offset:416 -; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s33 offset:420 -; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s33 offset:424 -; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s33 offset:428 -; GCN-NEXT: buffer_store_dword v52, off, s[0:3], s33 offset:432 -; GCN-NEXT: buffer_store_dword v53, off, s[0:3], s33 offset:436 -; GCN-NEXT: buffer_store_dword v54, off, s[0:3], s33 offset:440 -; GCN-NEXT: buffer_store_dword v55, off, s[0:3], s33 offset:444 -; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s33 offset:448 -; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s33 offset:452 -; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s33 offset:456 -; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s33 offset:460 -; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload -; GCN-NEXT: v_and_b32_e32 v0, 31, v6 -; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33 -; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GCN-NEXT: v_add_u32_e32 v2, 0x100, v2 -; GCN-NEXT: v_add_u32_e32 v1, v2, v0 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v16, v20 -; GCN-NEXT: v_mov_b32_e32 v17, v21 -; GCN-NEXT: v_mov_b32_e32 v18, v22 -; GCN-NEXT: v_mov_b32_e32 v19, v23 -; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:464 -; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:468 -; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:472 -; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:476 -; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:480 -; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:484 -; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:488 -; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:492 -; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:496 -; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:500 -; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:504 -; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:508 -; GCN-NEXT: buffer_load_dword v0, v1, s[0:3], 0 offen -; GCN-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen offset:4 -; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s33 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload -; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload -; GCN-NEXT: s_mov_b32 s33, s4 +; GCN-NEXT: v_and_b32_e32 v2, 31, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 3, v2 +; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GCN-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_setpc_b64 s[30:31] %vec = load <32 x i64>, ptr addrspace(1) %ptr diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll index 786d65f7dcc4..057790617204 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll @@ -8,29 +8,36 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_sgpr_idx(ptr addrspace(4) inreg %ptr, i32 inreg %idx) { ; GCN-LABEL: extractelement_sgpr_v4i128_sgpr_idx: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx16 s[8:23], s[2:3], 0x0 -; GCN-NEXT: s_lshl_b32 m0, s4, 1 +; GCN-NEXT: s_and_b32 s0, s4, 3 +; GCN-NEXT: s_lshl_b32 s0, s0, 4 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: s_add_u32 s0, s2, s0 +; GCN-NEXT: s_addc_u32 s1, s3, s1 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_movrels_b64 s[0:1], s[8:9] -; GCN-NEXT: s_movrels_b64 s[2:3], s[10:11] ; GCN-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i128_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx16 s[8:23], s[2:3], 0x0 -; GFX10-NEXT: s_lshl_b32 m0, s4, 1 +; GFX10-NEXT: s_and_b32 s0, s4, 3 +; GFX10-NEXT: s_lshl_b32 s0, s0, 4 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: s_add_u32 s0, s2, s0 +; GFX10-NEXT: s_addc_u32 s1, s3, s1 +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_movrels_b64 s[0:1], s[8:9] -; GFX10-NEXT: s_movrels_b64 s[2:3], s[10:11] ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i128_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b512 s[8:23], s[2:3], 0x0 -; GFX11-NEXT: s_lshl_b32 m0, s4, 1 +; GFX11-NEXT: s_and_b32 s0, s4, 3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_lshl_b32 s0, s0, 4 +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: s_add_u32 s0, s2, s0 +; GFX11-NEXT: s_addc_u32 s1, s3, s1 +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_movrels_b64 s[0:1], s[8:9] -; GFX11-NEXT: s_movrels_b64 s[2:3], s[10:11] ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i128>, ptr addrspace(4) %ptr %element = extractelement <4 x i128> %vector, i32 %idx @@ -40,46 +47,32 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_sgpr_idx(ptr addrspace(4) inre define amdgpu_ps i128 @extractelement_vgpr_v4i128_sgpr_idx(ptr addrspace(1) %ptr, i32 inreg %idx) { ; GFX9-LABEL: extractelement_vgpr_v4i128_sgpr_idx: ; GFX9: ; %bb.0: -; GFX9-NEXT: global_load_dwordx4 v[2:5], v[0:1], off -; GFX9-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:16 -; GFX9-NEXT: global_load_dwordx4 v[10:13], v[0:1], off offset:32 -; GFX9-NEXT: global_load_dwordx4 v[14:17], v[0:1], off offset:48 -; GFX9-NEXT: s_lshl_b32 s0, s2, 1 -; GFX9-NEXT: s_lshl_b32 s2, s0, 1 +; GFX9-NEXT: s_and_b32 s0, s2, 3 +; GFX9-NEXT: s_lshl_b32 s0, s0, 4 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0) -; GFX9-NEXT: v_mov_b32_e32 v0, v2 -; GFX9-NEXT: v_mov_b32_e32 v1, v3 -; GFX9-NEXT: v_mov_b32_e32 v18, v2 -; GFX9-NEXT: s_set_gpr_idx_off ; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1 -; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0) -; GFX9-NEXT: v_mov_b32_e32 v3, v3 -; GFX9-NEXT: s_set_gpr_idx_off -; GFX9-NEXT: v_readfirstlane_b32 s2, v18 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: extractelement_vgpr_v4i128_sgpr_idx: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_add_u32_e32 v6, vcc, 16, v0 -; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc -; GFX8-NEXT: v_add_u32_e32 v10, vcc, 32, v0 -; GFX8-NEXT: v_addc_u32_e32 v11, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_dwordx4 v[2:5], v[0:1] -; GFX8-NEXT: flat_load_dwordx4 v[6:9], v[6:7] -; GFX8-NEXT: v_add_u32_e32 v0, vcc, 48, v0 -; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_dwordx4 v[10:13], v[10:11] -; GFX8-NEXT: flat_load_dwordx4 v[14:17], v[0:1] -; GFX8-NEXT: s_lshl_b32 s0, s2, 1 -; GFX8-NEXT: s_lshl_b32 m0, s0, 1 +; GFX8-NEXT: s_and_b32 s0, s2, 3 +; GFX8-NEXT: s_lshl_b32 s0, s0, 4 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_movrels_b32_e32 v1, v3 -; GFX8-NEXT: v_movrels_b32_e32 v0, v2 -; GFX8-NEXT: v_mov_b32_e32 v3, v1 -; GFX8-NEXT: v_mov_b32_e32 v2, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s2, v2 @@ -88,20 +81,13 @@ define amdgpu_ps i128 @extractelement_vgpr_v4i128_sgpr_idx(ptr addrspace(1) %ptr ; ; GFX7-LABEL: extractelement_vgpr_v4i128_sgpr_idx: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_mov_b32 s6, 0 -; GFX7-NEXT: s_mov_b32 s7, 0xf000 -; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[2:5], v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: buffer_load_dwordx4 v[6:9], v[0:1], s[4:7], 0 addr64 offset:16 -; GFX7-NEXT: buffer_load_dwordx4 v[10:13], v[0:1], s[4:7], 0 addr64 offset:32 -; GFX7-NEXT: buffer_load_dwordx4 v[14:17], v[0:1], s[4:7], 0 addr64 offset:48 -; GFX7-NEXT: s_lshl_b32 s0, s2, 1 -; GFX7-NEXT: s_lshl_b32 m0, s0, 1 +; GFX7-NEXT: s_and_b32 s0, s2, 3 +; GFX7-NEXT: s_lshl_b32 s0, s0, 4 +; GFX7-NEXT: s_ashr_i32 s1, s0, 31 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_movrels_b32_e32 v1, v3 -; GFX7-NEXT: v_movrels_b32_e32 v0, v2 -; GFX7-NEXT: v_mov_b32_e32 v3, v1 -; GFX7-NEXT: v_mov_b32_e32 v2, v0 ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s1, v1 ; GFX7-NEXT: v_readfirstlane_b32 s2, v2 @@ -110,44 +96,38 @@ define amdgpu_ps i128 @extractelement_vgpr_v4i128_sgpr_idx(ptr addrspace(1) %ptr ; ; GFX10-LABEL: extractelement_vgpr_v4i128_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_clause 0x3 -; GFX10-NEXT: global_load_dwordx4 v[2:5], v[0:1], off -; GFX10-NEXT: global_load_dwordx4 v[6:9], v[0:1], off offset:16 -; GFX10-NEXT: global_load_dwordx4 v[10:13], v[0:1], off offset:32 -; GFX10-NEXT: global_load_dwordx4 v[14:17], v[0:1], off offset:48 -; GFX10-NEXT: s_lshl_b32 s0, s2, 1 -; GFX10-NEXT: s_lshl_b32 m0, s0, 1 +; GFX10-NEXT: s_and_b32 s0, s2, 3 +; GFX10-NEXT: s_lshl_b32 s0, s0, 4 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: v_mov_b32_e32 v3, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s0 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_movrels_b32_e32 v1, v3 -; GFX10-NEXT: v_movrels_b32_e32 v0, v2 -; GFX10-NEXT: v_mov_b32_e32 v3, v1 -; GFX10-NEXT: v_mov_b32_e32 v2, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1 -; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_vgpr_v4i128_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x3 -; GFX11-NEXT: global_load_b128 v[2:5], v[0:1], off -; GFX11-NEXT: global_load_b128 v[6:9], v[0:1], off offset:16 -; GFX11-NEXT: global_load_b128 v[10:13], v[0:1], off offset:32 -; GFX11-NEXT: global_load_b128 v[14:17], v[0:1], off offset:48 -; GFX11-NEXT: s_lshl_b32 s0, s2, 1 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-NEXT: s_lshl_b32 m0, s0, 1 +; GFX11-NEXT: s_and_b32 s0, s2, 3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_lshl_b32 s0, s0, 4 +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_movrels_b32_e32 v0, v2 -; GFX11-NEXT: v_movrels_b32_e32 v1, v3 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1 -; GFX11-NEXT: v_readfirstlane_b32 s3, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-NEXT: v_readfirstlane_b32 s2, v2 +; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i128>, ptr addrspace(1) %ptr %element = extractelement <4 x i128> %vector, i32 %idx @@ -158,298 +138,66 @@ define i128 @extractelement_vgpr_v4i128_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx ; GFX9-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[3:6], v[0:1], off -; GFX9-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16 -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2 -; GFX9-NEXT: v_add_u32_e32 v16, 1, v2 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16 -; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v2 -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_cndmask_b32_e64 v11, v3, v5, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e64 v12, v4, v6, s[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v5, v11, v7, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v6, v12, v8, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc -; GFX9-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:32 -; GFX9-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:48 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2 -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2 +; GFX9-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 4, v2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v13, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v14, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v15, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1] -; GFX8-NEXT: v_add_u32_e32 v7, vcc, 16, v0 -; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_dwordx4 v[7:10], v[7:8] -; GFX8-NEXT: v_lshlrev_b32_e32 v16, 1, v2 -; GFX8-NEXT: v_add_u32_e32 v17, vcc, 1, v16 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17 -; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v16 -; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: v_cndmask_b32_e64 v11, v3, v5, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v12, v4, v6, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX8-NEXT: v_add_u32_e32 v2, vcc, 32, v0 -; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16 -; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v6, v11, v7, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v11, v12, v8, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v10, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc -; GFX8-NEXT: flat_load_dwordx4 v[8:11], v[2:3] -; GFX8-NEXT: v_add_u32_e32 v0, vcc, 48, v0 -; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; GFX8-NEXT: flat_load_dwordx4 v[12:15], v[0:1] -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16 -; GFX8-NEXT: s_waitcnt vmcnt(1) -; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v9, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16 +; GFX8-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 4, v2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v16 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v17 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: s_mov_b32 s10, 0 -; GFX7-NEXT: s_mov_b32 s11, 0xf000 -; GFX7-NEXT: s_mov_b64 s[8:9], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[8:11], 0 addr64 -; GFX7-NEXT: buffer_load_dwordx4 v[7:10], v[0:1], s[8:11], 0 addr64 offset:16 -; GFX7-NEXT: v_lshlrev_b32_e32 v2, 1, v2 -; GFX7-NEXT: v_add_i32_e32 v16, vcc, 1, v2 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16 -; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v2 -; GFX7-NEXT: s_waitcnt vmcnt(1) -; GFX7-NEXT: v_cndmask_b32_e64 v11, v3, v5, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e64 v12, v4, v6, s[4:5] -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2 -; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v5, v11, v7, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v6, v12, v8, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc -; GFX7-NEXT: buffer_load_dwordx4 v[8:11], v[0:1], s[8:11], 0 addr64 offset:32 -; GFX7-NEXT: buffer_load_dwordx4 v[12:15], v[0:1], s[8:11], 0 addr64 offset:48 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2 -; GFX7-NEXT: s_waitcnt vmcnt(1) -; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2 +; GFX7-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX7-NEXT: v_lshlrev_b32_e32 v2, 4, v2 +; GFX7-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX7-NEXT: s_mov_b32 s6, 0 +; GFX7-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-NEXT: s_mov_b64 s[4:5], 0 +; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v13, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v16 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v14, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v15, vcc ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off -; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:16 -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v2 -; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:32 -; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v2 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v3 -; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: v_cndmask_b32_e32 v16, v12, v14, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v17, v13, v15, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v18, v12, v14, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v19, v13, v15, s4 -; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:48 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 2, v3 -; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v4, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, v4, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v19, v5, s4 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 3, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v6, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v7, s4 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 4, v3 -; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v8, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s4 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v11, s4 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v3 +; GFX10-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v2 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v12, s4 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v2 -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s4 -; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 7, v3 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v14, s4 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v15, s4 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_clause 0x3 -; GFX11-NEXT: global_load_b128 v[16:19], v[0:1], off -; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off offset:16 -; GFX11-NEXT: global_load_b128 v[8:11], v[0:1], off offset:32 -; GFX11-NEXT: global_load_b128 v[12:15], v[0:1], off offset:48 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: s_waitcnt vmcnt(3) -; GFX11-NEXT: v_cndmask_b32_e32 v3, v17, v19, vcc_lo -; GFX11-NEXT: v_dual_cndmask_b32 v2, v16, v18 :: v_dual_add_nc_u32 v1, 1, v0 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v1 -; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v18, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v19, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1 -; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_cndmask_b32 v3, v3, v7 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e64 v4, v16, v4, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v5, v17, v5, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v1 -; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v8 :: v_dual_cndmask_b32 v3, v3, v9 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v6, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v7, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 4, v1 -; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v8, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v9, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v1 +; GFX11-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v2 +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v12 :: v_dual_cndmask_b32 v3, v3, v13 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v11, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 6, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v14, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v12, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v13, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 7, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v15, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v14, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, v15, s0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i128>, ptr addrspace(1) %ptr %element = extractelement <4 x i128> %vector, i32 %idx @@ -459,68 +207,15 @@ define i128 @extractelement_vgpr_v4i128_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) { ; GFX9-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX9-NEXT: v_add_u32_e32 v19, 1, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v1, s0 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_mov_b32_e32 v3, s2 -; GFX9-NEXT: v_mov_b32_e32 v4, s3 -; GFX9-NEXT: v_mov_b32_e32 v5, s4 -; GFX9-NEXT: v_mov_b32_e32 v6, s5 -; GFX9-NEXT: v_cndmask_b32_e32 v17, v1, v3, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v18, v2, v4, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 -; GFX9-NEXT: v_mov_b32_e32 v7, s6 -; GFX9-NEXT: v_mov_b32_e32 v8, s7 -; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v5, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v6, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 -; GFX9-NEXT: v_mov_b32_e32 v9, s8 -; GFX9-NEXT: v_mov_b32_e32 v10, s9 -; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v7, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v8, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0 -; GFX9-NEXT: v_mov_b32_e32 v11, s10 -; GFX9-NEXT: v_mov_b32_e32 v12, s11 -; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 -; GFX9-NEXT: v_mov_b32_e32 v13, s12 -; GFX9-NEXT: v_mov_b32_e32 v14, s13 -; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19 -; GFX9-NEXT: v_mov_b32_e32 v15, s14 -; GFX9-NEXT: v_mov_b32_e32 v16, s15 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] -; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 3, v19 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v3, v1, v7, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v16, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[0:1] -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v19 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v19 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v19 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v14, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v19 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v15, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc +; GFX9-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s2, v2 @@ -529,68 +224,15 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inre ; ; GFX8-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: s_waitcnt lgkmcnt(0) -; GFX8-NEXT: v_mov_b32_e32 v1, s0 -; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: v_mov_b32_e32 v3, s2 -; GFX8-NEXT: v_mov_b32_e32 v4, s3 -; GFX8-NEXT: v_mov_b32_e32 v5, s4 -; GFX8-NEXT: v_mov_b32_e32 v6, s5 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v1, v3, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v18, v2, v4, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 -; GFX8-NEXT: v_mov_b32_e32 v7, s6 -; GFX8-NEXT: v_mov_b32_e32 v8, s7 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v5, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v6, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 -; GFX8-NEXT: v_mov_b32_e32 v9, s8 -; GFX8-NEXT: v_mov_b32_e32 v10, s9 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v7, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v8, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0 -; GFX8-NEXT: v_mov_b32_e32 v11, s10 -; GFX8-NEXT: v_mov_b32_e32 v12, s11 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 -; GFX8-NEXT: v_mov_b32_e32 v13, s12 -; GFX8-NEXT: v_mov_b32_e32 v14, s13 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc -; GFX8-NEXT: v_add_u32_e32 v19, vcc, 1, v0 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19 -; GFX8-NEXT: v_mov_b32_e32 v15, s14 -; GFX8-NEXT: v_mov_b32_e32 v16, s15 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 -; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] -; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] -; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 3, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v3, v1, v7, s[0:1] -; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v16, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[0:1] -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v14, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v19 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v15, vcc -; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc +; GFX8-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 4, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s2, v2 @@ -599,68 +241,15 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inre ; ; GFX7-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v1, s0 -; GFX7-NEXT: v_mov_b32_e32 v2, s1 -; GFX7-NEXT: v_mov_b32_e32 v3, s2 -; GFX7-NEXT: v_mov_b32_e32 v4, s3 -; GFX7-NEXT: v_mov_b32_e32 v5, s4 -; GFX7-NEXT: v_mov_b32_e32 v6, s5 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v1, v3, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v18, v2, v4, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 -; GFX7-NEXT: v_mov_b32_e32 v7, s6 -; GFX7-NEXT: v_mov_b32_e32 v8, s7 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v5, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v6, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 -; GFX7-NEXT: v_mov_b32_e32 v9, s8 -; GFX7-NEXT: v_mov_b32_e32 v10, s9 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v7, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v8, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0 -; GFX7-NEXT: v_mov_b32_e32 v11, s10 -; GFX7-NEXT: v_mov_b32_e32 v12, s11 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 -; GFX7-NEXT: v_mov_b32_e32 v13, s12 -; GFX7-NEXT: v_mov_b32_e32 v14, s13 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc -; GFX7-NEXT: v_add_i32_e32 v19, vcc, 1, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19 -; GFX7-NEXT: v_mov_b32_e32 v15, s14 -; GFX7-NEXT: v_mov_b32_e32 v16, s15 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 -; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] -; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] -; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 3, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v3, v1, v7, s[0:1] -; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v16, vcc -; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[0:1] -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v4, v2, v14, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v19 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v15, vcc -; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc +; GFX7-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 4, v0 +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s1, v1 ; GFX7-NEXT: v_readfirstlane_b32 s2, v2 @@ -669,54 +258,15 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inre ; ; GFX10-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x0 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v0 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v1 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v2, s6 -; GFX10-NEXT: v_mov_b32_e32 v3, s7 -; GFX10-NEXT: v_cndmask_b32_e32 v4, s4, v2, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v5, s5, v3, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, s4, v2, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, s5, v3, s0 -; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 2, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s8, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s9, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s8, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s9, s0 -; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s10, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s11, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s10, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s11, s0 -; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 4, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s12, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s13, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s12, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s13, s0 -; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s14, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s15, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s14, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s15, s0 -; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 6, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s16, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s17, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s16, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s17, s0 -; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 7, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, s18, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, s19, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s18, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s19, s0 +; GFX10-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 4, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2 @@ -725,63 +275,18 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inre ; ; GFX11-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b512 s[4:19], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_dual_mov_b32 v3, s7 :: v_dual_lshlrev_b32 v0, 1, v0 +; GFX11-NEXT: v_and_b32_e32 v0, 3, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_add_nc_u32 v1, 1, v0 -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v4, s4, v2, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e32 v5, s5, v3, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v2, s4, v2, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, s5, v3, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s8, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s9, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s8, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s9, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s10, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s11, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s10, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s11, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 4, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s12, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s13, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s12, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s13, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s14, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s15, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s14, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s15, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 6, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s16, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s17, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s16, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s17, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 7, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, s18, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, s19, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s18, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s19, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v0 +; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_readfirstlane_b32 s2, v2 ; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: ; return to shader part epilog @@ -793,19 +298,19 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inre define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx0(ptr addrspace(4) inreg %ptr) { ; GCN-LABEL: extractelement_sgpr_v4i128_idx0: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i128_idx0: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i128_idx0: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b512 s[0:15], s[2:3], 0x0 +; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i128>, ptr addrspace(4) %ptr @@ -814,34 +319,34 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx0(ptr addrspace(4) inreg %p } define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx1(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i128_idx1: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_mov_b32 s2, s6 -; GCN-NEXT: s_mov_b32 s3, s7 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i128_idx1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x10 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i128_idx1: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x10 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i128_idx1: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x4 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i128_idx1: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x10 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_mov_b32 s0, s4 -; GFX10-NEXT: s_mov_b32 s1, s5 -; GFX10-NEXT: s_mov_b32 s2, s6 -; GFX10-NEXT: s_mov_b32 s3, s7 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i128_idx1: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b512 s[0:15], s[2:3], 0x0 +; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x10 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s0, s4 -; GFX11-NEXT: s_mov_b32 s1, s5 -; GFX11-NEXT: s_mov_b32 s2, s6 -; GFX11-NEXT: s_mov_b32 s3, s7 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i128>, ptr addrspace(4) %ptr %element = extractelement <4 x i128> %vector, i32 1 @@ -849,34 +354,34 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx1(ptr addrspace(4) inreg %p } define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx2(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i128_idx2: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s8 -; GCN-NEXT: s_mov_b32 s1, s9 -; GCN-NEXT: s_mov_b32 s2, s10 -; GCN-NEXT: s_mov_b32 s3, s11 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i128_idx2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x20 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i128_idx2: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x20 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i128_idx2: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x8 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i128_idx2: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x20 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_mov_b32 s0, s8 -; GFX10-NEXT: s_mov_b32 s1, s9 -; GFX10-NEXT: s_mov_b32 s2, s10 -; GFX10-NEXT: s_mov_b32 s3, s11 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i128_idx2: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b512 s[0:15], s[2:3], 0x0 +; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x20 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s0, s8 -; GFX11-NEXT: s_mov_b32 s1, s9 -; GFX11-NEXT: s_mov_b32 s2, s10 -; GFX11-NEXT: s_mov_b32 s3, s11 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i128>, ptr addrspace(4) %ptr %element = extractelement <4 x i128> %vector, i32 2 @@ -884,34 +389,34 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx2(ptr addrspace(4) inreg %p } define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx3(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i128_idx3: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s12 -; GCN-NEXT: s_mov_b32 s1, s13 -; GCN-NEXT: s_mov_b32 s2, s14 -; GCN-NEXT: s_mov_b32 s3, s15 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i128_idx3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x30 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i128_idx3: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x30 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i128_idx3: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0xc +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i128_idx3: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x30 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_mov_b32 s0, s12 -; GFX10-NEXT: s_mov_b32 s1, s13 -; GFX10-NEXT: s_mov_b32 s2, s14 -; GFX10-NEXT: s_mov_b32 s3, s15 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i128_idx3: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b512 s[0:15], s[2:3], 0x0 +; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x30 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s0, s12 -; GFX11-NEXT: s_mov_b32 s1, s13 -; GFX11-NEXT: s_mov_b32 s2, s14 -; GFX11-NEXT: s_mov_b32 s3, s15 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i128>, ptr addrspace(4) %ptr %element = extractelement <4 x i128> %vector, i32 3 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll index 7028d1157787..6d772df3fa28 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll @@ -6,42 +6,74 @@ ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s define amdgpu_ps i16 @extractelement_sgpr_v4i16_sgpr_idx(ptr addrspace(4) inreg %ptr, i32 inreg %idx) { -; GCN-LABEL: extractelement_sgpr_v4i16_sgpr_idx: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_lshr_b32 s2, s4, 1 -; GCN-NEXT: s_cmp_eq_u32 s2, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_cselect_b32 s0, s1, s0 -; GCN-NEXT: s_and_b32 s1, s4, 1 -; GCN-NEXT: s_lshl_b32 s1, s1, 4 -; GCN-NEXT: s_lshr_b32 s0, s0, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i16_sgpr_idx: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_and_b32 s0, s4, 3 +; GFX9-NEXT: s_lshl_b32 s0, s0, 1 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: s_add_u32 s0, s2, s0 +; GFX9-NEXT: s_addc_u32 s1, s3, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i16_sgpr_idx: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_and_b32 s0, s4, 3 +; GFX8-NEXT: s_lshl_b32 s0, s0, 1 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: s_add_u32 s0, s2, s0 +; GFX8-NEXT: s_addc_u32 s1, s3, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i16_sgpr_idx: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_and_b32 s2, s4, 3 +; GFX7-NEXT: s_lshl_b32 s4, s2, 1 +; GFX7-NEXT: s_ashr_i32 s5, s4, 31 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i16_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_lshr_b32 s2, s4, 1 -; GFX10-NEXT: s_cmp_eq_u32 s2, 1 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_cselect_b32 s0, s1, s0 -; GFX10-NEXT: s_and_b32 s1, s4, 1 -; GFX10-NEXT: s_lshl_b32 s1, s1, 4 -; GFX10-NEXT: s_lshr_b32 s0, s0, s1 +; GFX10-NEXT: s_and_b32 s0, s4, 3 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_lshl_b32 s0, s0, 1 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: s_add_u32 s0, s2, s0 +; GFX10-NEXT: s_addc_u32 s1, s3, s1 +; GFX10-NEXT: global_load_ushort v0, v0, s[0:1] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i16_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_lshr_b32 s2, s4, 1 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_cmp_eq_u32 s2, 1 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_cselect_b32 s0, s1, s0 -; GFX11-NEXT: s_and_b32 s1, s4, 1 -; GFX11-NEXT: s_lshl_b32 s1, s1, 4 +; GFX11-NEXT: s_and_b32 s0, s4, 3 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_lshl_b32 s0, s0, 1 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_lshr_b32 s0, s0, s1 +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: s_add_u32 s0, s2, s0 +; GFX11-NEXT: s_addc_u32 s1, s3, s1 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i16>, ptr addrspace(4) %ptr %element = extractelement <4 x i16> %vector, i32 %idx @@ -51,71 +83,71 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_sgpr_idx(ptr addrspace(4) inreg define amdgpu_ps i16 @extractelement_vgpr_v4i16_sgpr_idx(ptr addrspace(1) %ptr, i32 inreg %idx) { ; GFX9-LABEL: extractelement_vgpr_v4i16_sgpr_idx: ; GFX9: ; %bb.0: -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX9-NEXT: s_lshr_b32 s0, s2, 1 -; GFX9-NEXT: s_and_b32 s1, s2, 1 -; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX9-NEXT: s_lshl_b32 s0, s1, 4 +; GFX9-NEXT: s_and_b32 s0, s2, 3 +; GFX9-NEXT: s_lshl_b32 s0, s0, 1 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: extractelement_vgpr_v4i16_sgpr_idx: ; GFX8: ; %bb.0: -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] -; GFX8-NEXT: s_lshr_b32 s0, s2, 1 -; GFX8-NEXT: s_and_b32 s1, s2, 1 -; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX8-NEXT: s_lshl_b32 s0, s1, 4 +; GFX8-NEXT: s_and_b32 s0, s2, 3 +; GFX8-NEXT: s_lshl_b32 s0, s0, 1 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX7-LABEL: extractelement_vgpr_v4i16_sgpr_idx: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_mov_b32 s6, 0 -; GFX7-NEXT: s_mov_b32 s7, 0xf000 -; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: s_lshr_b32 s0, s2, 1 -; GFX7-NEXT: s_and_b32 s1, s2, 1 -; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX7-NEXT: s_lshl_b32 s0, s1, 4 +; GFX7-NEXT: s_and_b32 s0, s2, 3 +; GFX7-NEXT: s_lshl_b32 s0, s0, 1 +; GFX7-NEXT: s_ashr_i32 s1, s0, 31 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_vgpr_v4i16_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-NEXT: s_lshr_b32 s0, s2, 1 -; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1 -; GFX10-NEXT: s_and_b32 s0, s2, 1 -; GFX10-NEXT: s_lshl_b32 s0, s0, 4 +; GFX10-NEXT: s_and_b32 s0, s2, 3 +; GFX10-NEXT: s_lshl_b32 s0, s0, 1 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: v_mov_b32_e32 v3, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s0 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_vgpr_v4i16_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: s_lshr_b32 s0, s2, 1 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1 -; GFX11-NEXT: s_and_b32 s0, s2, 1 -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 +; GFX11-NEXT: s_and_b32 s0, s2, 3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_lshl_b32 s0, s0, 1 +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u16 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i16>, ptr addrspace(1) %ptr @@ -127,70 +159,66 @@ define i16 @extractelement_vgpr_v4i16_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) ; GFX9-LABEL: extractelement_vgpr_v4i16_vgpr_idx: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3 +; GFX9-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i16_vgpr_idx: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v2 -; GFX8-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3 +; GFX8-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v4i16_vgpr_idx: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX7-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX7-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: v_lshrrev_b32_e32 v3, 1, v2 -; GFX7-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v2 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i16_vgpr_idx: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 +; GFX10-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i16_vgpr_idx: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: v_lshrrev_b32_e32 v3, 1, v2 -; GFX11-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 +; GFX11-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u16 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_lshlrev_b32 v1, 4, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i16>, ptr addrspace(1) %ptr %element = extractelement <4 x i16> %vector, i32 %idx @@ -198,48 +226,74 @@ define i16 @extractelement_vgpr_v4i16_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) } define amdgpu_ps i16 @extractelement_sgpr_v4i16_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) { -; GCN-LABEL: extractelement_sgpr_v4i16_vgpr_idx: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v0 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 -; GCN-NEXT: v_and_b32_e32 v0, 1, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v2, s0 -; GCN-NEXT: v_mov_b32_e32 v3, s1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, v0, v1 -; GCN-NEXT: v_readfirstlane_b32 s0, v0 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i16_vgpr_idx: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ushort v0, v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i16_vgpr_idx: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i16_vgpr_idx: +; GFX7: ; %bb.0: +; GFX7-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i16_vgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v0 -; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v2, s1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, s0, v2, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v0, v0, v1 +; GFX10-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ushort v0, v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i16_vgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-NEXT: v_dual_cndmask_b32 v1, s0, v2 :: v_dual_and_b32 v0, 1, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v0, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u16 v0, v[0:1], off +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i16>, ptr addrspace(4) %ptr @@ -248,22 +302,48 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_vgpr_idx(ptr addrspace(4) inreg } define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx0(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i16_idx0: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i16_idx0: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i16_idx0: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i16_idx0: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i16_idx0: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i16_idx0: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i16>, ptr addrspace(4) %ptr %element = extractelement <4 x i16> %vector, i32 0 @@ -271,25 +351,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx0(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx1(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i16_idx1: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s0, 16 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i16_idx1: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:2 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i16_idx1: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 2 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i16_idx1: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:2 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i16_idx1: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s0, 16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:2 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i16_idx1: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s0, 16 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:2 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i16>, ptr addrspace(4) %ptr %element = extractelement <4 x i16> %vector, i32 1 @@ -297,25 +402,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx1(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx2(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i16_idx2: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i16_idx2: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i16_idx2: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 4 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i16_idx2: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i16_idx2: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_mov_b32 s0, s1 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:4 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i16_idx2: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s0, s1 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:4 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i16>, ptr addrspace(4) %ptr %element = extractelement <4 x i16> %vector, i32 2 @@ -323,25 +453,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx2(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx3(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i16_idx3: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s1, 16 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i16_idx3: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:6 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i16_idx3: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 6 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i16_idx3: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:6 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i16_idx3: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s1, 16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:6 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i16_idx3: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s1, 16 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:6 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i16>, ptr addrspace(4) %ptr %element = extractelement <4 x i16> %vector, i32 3 @@ -352,14 +507,14 @@ define i16 @extractelement_vgpr_v4i16_idx0(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v4i16_idx0: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i16_idx0: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -369,21 +524,21 @@ define i16 @extractelement_vgpr_v4i16_idx0(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i16_idx0: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i16_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i16>, ptr addrspace(1) %ptr @@ -395,17 +550,17 @@ define i16 @extractelement_vgpr_v4i16_idx1(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v4i16_idx1: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:2 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i16_idx1: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v4i16_idx1: @@ -414,25 +569,22 @@ define i16 @extractelement_vgpr_v4i16_idx1(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:2 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i16_idx1: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:2 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i16_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:2 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i16>, ptr addrspace(1) %ptr %element = extractelement <4 x i16> %vector, i32 1 @@ -443,17 +595,17 @@ define i16 @extractelement_vgpr_v4i16_idx2(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v4i16_idx2: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:4 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i16_idx2: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v4i16_idx2: @@ -462,25 +614,22 @@ define i16 @extractelement_vgpr_v4i16_idx2(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v0, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i16_idx2: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i16_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i16>, ptr addrspace(1) %ptr %element = extractelement <4 x i16> %vector, i32 2 @@ -491,17 +640,17 @@ define i16 @extractelement_vgpr_v4i16_idx3(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v4i16_idx3: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:6 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i16_idx3: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 6, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v4i16_idx3: @@ -510,25 +659,22 @@ define i16 @extractelement_vgpr_v4i16_idx3(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:6 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i16_idx3: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:6 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i16_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:6 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i16>, ptr addrspace(1) %ptr %element = extractelement <4 x i16> %vector, i32 3 @@ -536,54 +682,74 @@ define i16 @extractelement_vgpr_v4i16_idx3(ptr addrspace(1) %ptr) { } define amdgpu_ps i16 @extractelement_sgpr_v8i16_sgpr_idx(ptr addrspace(4) inreg %ptr, i32 inreg %idx) { -; GCN-LABEL: extractelement_sgpr_v8i16_sgpr_idx: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_lshr_b32 s5, s4, 1 -; GCN-NEXT: s_cmp_eq_u32 s5, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_cselect_b32 s0, s1, s0 -; GCN-NEXT: s_cmp_eq_u32 s5, 2 -; GCN-NEXT: s_cselect_b32 s0, s2, s0 -; GCN-NEXT: s_cmp_eq_u32 s5, 3 -; GCN-NEXT: s_cselect_b32 s0, s3, s0 -; GCN-NEXT: s_and_b32 s1, s4, 1 -; GCN-NEXT: s_lshl_b32 s1, s1, 4 -; GCN-NEXT: s_lshr_b32 s0, s0, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_sgpr_idx: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_and_b32 s0, s4, 7 +; GFX9-NEXT: s_lshl_b32 s0, s0, 1 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: s_add_u32 s0, s2, s0 +; GFX9-NEXT: s_addc_u32 s1, s3, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_sgpr_idx: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_and_b32 s0, s4, 7 +; GFX8-NEXT: s_lshl_b32 s0, s0, 1 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: s_add_u32 s0, s2, s0 +; GFX8-NEXT: s_addc_u32 s1, s3, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_sgpr_idx: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_and_b32 s2, s4, 7 +; GFX7-NEXT: s_lshl_b32 s4, s2, 1 +; GFX7-NEXT: s_ashr_i32 s5, s4, 31 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_lshr_b32 s5, s4, 1 -; GFX10-NEXT: s_cmp_eq_u32 s5, 1 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_cselect_b32 s0, s1, s0 -; GFX10-NEXT: s_cmp_eq_u32 s5, 2 -; GFX10-NEXT: s_cselect_b32 s0, s2, s0 -; GFX10-NEXT: s_cmp_eq_u32 s5, 3 -; GFX10-NEXT: s_cselect_b32 s0, s3, s0 -; GFX10-NEXT: s_and_b32 s1, s4, 1 -; GFX10-NEXT: s_lshl_b32 s1, s1, 4 -; GFX10-NEXT: s_lshr_b32 s0, s0, s1 +; GFX10-NEXT: s_and_b32 s0, s4, 7 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_lshl_b32 s0, s0, 1 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: s_add_u32 s0, s2, s0 +; GFX10-NEXT: s_addc_u32 s1, s3, s1 +; GFX10-NEXT: global_load_ushort v0, v0, s[0:1] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_lshr_b32 s5, s4, 1 +; GFX11-NEXT: s_and_b32 s0, s4, 7 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_lshl_b32 s0, s0, 1 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_cmp_eq_u32 s5, 1 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_cselect_b32 s0, s1, s0 -; GFX11-NEXT: s_cmp_eq_u32 s5, 2 -; GFX11-NEXT: s_cselect_b32 s0, s2, s0 -; GFX11-NEXT: s_cmp_eq_u32 s5, 3 -; GFX11-NEXT: s_cselect_b32 s0, s3, s0 -; GFX11-NEXT: s_and_b32 s1, s4, 1 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_lshl_b32 s1, s1, 4 -; GFX11-NEXT: s_lshr_b32 s0, s0, s1 +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: s_add_u32 s0, s2, s0 +; GFX11-NEXT: s_addc_u32 s1, s3, s1 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr %element = extractelement <8 x i16> %vector, i32 %idx @@ -593,92 +759,71 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_sgpr_idx(ptr addrspace(4) inreg define amdgpu_ps i16 @extractelement_vgpr_v8i16_sgpr_idx(ptr addrspace(1) %ptr, i32 inreg %idx) { ; GFX9-LABEL: extractelement_vgpr_v8i16_sgpr_idx: ; GFX9: ; %bb.0: -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX9-NEXT: s_lshr_b32 s0, s2, 1 -; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX9-NEXT: s_and_b32 s1, s2, 1 +; GFX9-NEXT: s_and_b32 s0, s2, 7 +; GFX9-NEXT: s_lshl_b32 s0, s0, 1 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX9-NEXT: s_lshl_b32 s0, s1, 4 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: extractelement_vgpr_v8i16_sgpr_idx: ; GFX8: ; %bb.0: -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] -; GFX8-NEXT: s_lshr_b32 s0, s2, 1 -; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX8-NEXT: s_and_b32 s1, s2, 1 +; GFX8-NEXT: s_and_b32 s0, s2, 7 +; GFX8-NEXT: s_lshl_b32 s0, s0, 1 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX8-NEXT: s_lshl_b32 s0, s1, 4 -; GFX8-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX7-LABEL: extractelement_vgpr_v8i16_sgpr_idx: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_mov_b32 s6, 0 -; GFX7-NEXT: s_mov_b32 s7, 0xf000 -; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: s_lshr_b32 s0, s2, 1 -; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX7-NEXT: s_and_b32 s1, s2, 1 +; GFX7-NEXT: s_and_b32 s0, s2, 7 +; GFX7-NEXT: s_lshl_b32 s0, s0, 1 +; GFX7-NEXT: s_ashr_i32 s1, s0, 31 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX7-NEXT: s_lshl_b32 s0, s1, 4 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_vgpr_v8i16_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-NEXT: s_lshr_b32 s0, s2, 1 -; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1 +; GFX10-NEXT: s_and_b32 s0, s2, 7 +; GFX10-NEXT: s_lshl_b32 s0, s0, 1 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: v_mov_b32_e32 v3, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s0 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 3 -; GFX10-NEXT: s_and_b32 s0, s2, 1 -; GFX10-NEXT: s_lshl_b32 s0, s0, 4 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_vgpr_v8i16_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off -; GFX11-NEXT: s_lshr_b32 s0, s2, 1 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1 +; GFX11-NEXT: s_and_b32 s0, s2, 7 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_lshl_b32 s0, s0, 1 +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u16 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 3 -; GFX11-NEXT: s_and_b32 s0, s2, 1 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(1) %ptr @@ -690,91 +835,66 @@ define i16 @extractelement_vgpr_v8i16_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) ; GFX9-LABEL: extractelement_vgpr_v8i16_vgpr_idx: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[3:6], v[0:1], off -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 1, v2 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX9-NEXT: v_and_b32_e32 v1, 1, v2 -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 4, v1 +; GFX9-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i16_vgpr_idx: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1] -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 1, v2 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_and_b32_e32 v1, 1, v2 -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1 +; GFX8-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i16_vgpr_idx: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX7-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX7-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 1, v2 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX7-NEXT: v_and_b32_e32 v1, 1, v2 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v1 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i16_vgpr_idx: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX10-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v6, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v1, 4, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i16_vgpr_idx: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v2 -; GFX11-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX11-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 1, v2 +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u16 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v6, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v1, 4, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i16>, ptr addrspace(1) %ptr %element = extractelement <8 x i16> %vector, i32 %idx @@ -782,64 +902,74 @@ define i16 @extractelement_vgpr_v8i16_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) } define amdgpu_ps i16 @extractelement_sgpr_v8i16_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) { -; GCN-LABEL: extractelement_sgpr_v8i16_vgpr_idx: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v0 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 -; GCN-NEXT: v_and_b32_e32 v0, 1, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v2, s0 -; GCN-NEXT: v_mov_b32_e32 v3, s1 -; GCN-NEXT: v_mov_b32_e32 v4, s2 -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1 -; GCN-NEXT: v_mov_b32_e32 v5, s3 -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, v0, v1 -; GCN-NEXT: v_readfirstlane_b32 s0, v0 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_vgpr_idx: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_and_b32_e32 v0, 7, v0 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ushort v0, v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_vgpr_idx: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_and_b32_e32 v0, 7, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_vgpr_idx: +; GFX7: ; %bb.0: +; GFX7-NEXT: v_and_b32_e32 v0, 7, v0 +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_vgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v0 -; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v2, s1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s3, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v0, v0, v1 +; GFX10-NEXT: v_and_b32_e32 v0, 7, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ushort v0, v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_vgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v0 -; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v2, s1 +; GFX11-NEXT: v_and_b32_e32 v0, 7, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s3, vcc_lo -; GFX11-NEXT: v_lshrrev_b32_e32 v0, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 1, v0 +; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u16 v0, v[0:1], off +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr @@ -848,22 +978,48 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_vgpr_idx(ptr addrspace(4) inreg } define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx0(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i16_idx0: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_idx0: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_idx0: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_idx0: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_idx0: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_idx0: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr %element = extractelement <8 x i16> %vector, i32 0 @@ -871,25 +1027,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx0(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx1(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i16_idx1: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s0, 16 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_idx1: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:2 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_idx1: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 2 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_idx1: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:2 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_idx1: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s0, 16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:2 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_idx1: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s0, 16 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:2 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr %element = extractelement <8 x i16> %vector, i32 1 @@ -897,25 +1078,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx1(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx2(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i16_idx2: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_idx2: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_idx2: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 4 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_idx2: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_idx2: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_mov_b32 s0, s1 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:4 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_idx2: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s0, s1 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:4 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr %element = extractelement <8 x i16> %vector, i32 2 @@ -923,25 +1129,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx2(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx3(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i16_idx3: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s1, 16 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_idx3: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:6 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_idx3: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 6 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_idx3: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:6 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_idx3: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s1, 16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:6 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_idx3: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s1, 16 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:6 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr %element = extractelement <8 x i16> %vector, i32 3 @@ -949,25 +1180,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx3(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx4(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i16_idx4: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s2 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_idx4: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:8 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_idx4: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 8 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_idx4: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:8 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_idx4: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:8 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_idx4: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s0, s2 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:8 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr %element = extractelement <8 x i16> %vector, i32 4 @@ -975,25 +1231,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx4(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx5(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i16_idx5: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s2, 16 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_idx5: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:10 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_idx5: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 10 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_idx5: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:10 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_idx5: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s2, 16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:10 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_idx5: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s2, 16 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:10 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr %element = extractelement <8 x i16> %vector, i32 5 @@ -1001,25 +1282,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx5(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx6(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i16_idx6: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s3 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_idx6: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:12 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_idx6: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 12 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_idx6: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:12 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_idx6: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_mov_b32 s0, s3 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:12 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_idx6: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s0, s3 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:12 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr %element = extractelement <8 x i16> %vector, i32 6 @@ -1027,25 +1333,50 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx6(ptr addrspace(4) inreg %ptr } define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx7(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i16_idx7: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s3, 16 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i16_idx7: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ushort v0, v0, s[2:3] offset:14 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i16_idx7: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 14 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i16_idx7: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:14 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i16_idx7: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s3, 16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ushort v0, v0, s[2:3] offset:14 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i16_idx7: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s3, 16 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:14 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i16>, ptr addrspace(4) %ptr %element = extractelement <8 x i16> %vector, i32 7 @@ -1056,14 +1387,14 @@ define i16 @extractelement_vgpr_v8i16_idx0(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i16_idx0: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i16_idx0: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -1073,21 +1404,21 @@ define i16 @extractelement_vgpr_v8i16_idx0(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i16_idx0: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i16_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i16>, ptr addrspace(1) %ptr @@ -1099,17 +1430,17 @@ define i16 @extractelement_vgpr_v8i16_idx1(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i16_idx1: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:2 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i16_idx1: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i16_idx1: @@ -1118,25 +1449,22 @@ define i16 @extractelement_vgpr_v8i16_idx1(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:2 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i16_idx1: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:2 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i16_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:2 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i16>, ptr addrspace(1) %ptr %element = extractelement <8 x i16> %vector, i32 1 @@ -1147,17 +1475,17 @@ define i16 @extractelement_vgpr_v8i16_idx2(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i16_idx2: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:4 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i16_idx2: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i16_idx2: @@ -1166,25 +1494,22 @@ define i16 @extractelement_vgpr_v8i16_idx2(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v0, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i16_idx2: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i16_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i16>, ptr addrspace(1) %ptr %element = extractelement <8 x i16> %vector, i32 2 @@ -1195,17 +1520,17 @@ define i16 @extractelement_vgpr_v8i16_idx3(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i16_idx3: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:6 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i16_idx3: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 6, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i16_idx3: @@ -1214,25 +1539,22 @@ define i16 @extractelement_vgpr_v8i16_idx3(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:6 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i16_idx3: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:6 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i16_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:6 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i16>, ptr addrspace(1) %ptr %element = extractelement <8 x i16> %vector, i32 3 @@ -1243,17 +1565,17 @@ define i16 @extractelement_vgpr_v8i16_idx4(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i16_idx4: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:8 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i16_idx4: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_mov_b32_e32 v0, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i16_idx4: @@ -1262,25 +1584,22 @@ define i16 @extractelement_vgpr_v8i16_idx4(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:8 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v0, v2 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i16_idx4: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:8 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i16_idx4: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:8 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i16>, ptr addrspace(1) %ptr %element = extractelement <8 x i16> %vector, i32 4 @@ -1291,17 +1610,17 @@ define i16 @extractelement_vgpr_v8i16_idx5(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i16_idx5: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:10 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i16_idx5: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 10, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i16_idx5: @@ -1310,25 +1629,22 @@ define i16 @extractelement_vgpr_v8i16_idx5(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:10 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i16_idx5: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:10 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i16_idx5: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:10 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i16>, ptr addrspace(1) %ptr %element = extractelement <8 x i16> %vector, i32 5 @@ -1339,17 +1655,17 @@ define i16 @extractelement_vgpr_v8i16_idx6(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i16_idx6: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:12 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i16_idx6: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 12, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_mov_b32_e32 v0, v3 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i16_idx6: @@ -1358,25 +1674,22 @@ define i16 @extractelement_vgpr_v8i16_idx6(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:12 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v0, v3 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i16_idx6: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:12 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i16_idx6: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:12 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i16>, ptr addrspace(1) %ptr %element = extractelement <8 x i16> %vector, i32 6 @@ -1387,17 +1700,17 @@ define i16 @extractelement_vgpr_v8i16_idx7(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i16_idx7: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:14 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i16_idx7: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 14, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i16_idx7: @@ -1406,27 +1719,26 @@ define i16 @extractelement_vgpr_v8i16_idx7(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:14 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i16_idx7: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ushort v0, v[0:1], off offset:14 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i16_idx7: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:14 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i16>, ptr addrspace(1) %ptr %element = extractelement <8 x i16> %vector, i32 7 ret i16 %element } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GCN: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll index c7f49d526fac..c2394ec46149 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll @@ -6,32 +6,68 @@ ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s define amdgpu_ps i8 @extractelement_sgpr_v4i8_sgpr_idx(ptr addrspace(4) inreg %ptr, i32 inreg %idx) { -; GCN-LABEL: extractelement_sgpr_v4i8_sgpr_idx: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s0, s[2:3], 0x0 -; GCN-NEXT: s_and_b32 s1, s4, 3 -; GCN-NEXT: s_lshl_b32 s1, s1, 3 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s0, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i8_sgpr_idx: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_and_b32 s0, s4, 3 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: s_add_u32 s0, s2, s0 +; GFX9-NEXT: s_addc_u32 s1, s3, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i8_sgpr_idx: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_and_b32 s0, s4, 3 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: s_add_u32 s0, s2, s0 +; GFX8-NEXT: s_addc_u32 s1, s3, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i8_sgpr_idx: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_and_b32 s4, s4, 3 +; GFX7-NEXT: s_ashr_i32 s5, s4, 31 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i8_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX10-NEXT: s_and_b32 s1, s4, 3 -; GFX10-NEXT: s_lshl_b32 s1, s1, 3 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s0, s1 +; GFX10-NEXT: s_and_b32 s0, s4, 3 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: s_add_u32 s0, s2, s0 +; GFX10-NEXT: s_addc_u32 s1, s3, s1 +; GFX10-NEXT: global_load_ubyte v0, v0, s[0:1] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s1, s4, 3 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_lshl_b32 s1, s1, 3 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s0, s1 +; GFX11-NEXT: s_and_b32 s0, s4, 3 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: s_add_u32 s0, s2, s0 +; GFX11-NEXT: s_addc_u32 s1, s3, s1 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i8>, ptr addrspace(4) %ptr %element = extractelement <4 x i8> %vector, i32 %idx @@ -41,55 +77,65 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_sgpr_idx(ptr addrspace(4) inreg %p define amdgpu_ps i8 @extractelement_vgpr_v4i8_sgpr_idx(ptr addrspace(1) %ptr, i32 inreg %idx) { ; GFX9-LABEL: extractelement_vgpr_v4i8_sgpr_idx: ; GFX9: ; %bb.0: -; GFX9-NEXT: global_load_dword v0, v[0:1], off ; GFX9-NEXT: s_and_b32 s0, s2, 3 -; GFX9-NEXT: s_lshl_b32 s0, s0, 3 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: extractelement_vgpr_v4i8_sgpr_idx: ; GFX8: ; %bb.0: -; GFX8-NEXT: flat_load_dword v0, v[0:1] ; GFX8-NEXT: s_and_b32 s0, s2, 3 -; GFX8-NEXT: s_lshl_b32 s0, s0, 3 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX7-LABEL: extractelement_vgpr_v4i8_sgpr_idx: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_mov_b32 s6, 0 -; GFX7-NEXT: s_mov_b32 s7, 0xf000 -; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_and_b32 s0, s2, 3 -; GFX7-NEXT: s_lshl_b32 s0, s0, 3 +; GFX7-NEXT: s_ashr_i32 s1, s0, 31 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_vgpr_v4i8_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: global_load_dword v0, v[0:1], off ; GFX10-NEXT: s_and_b32 s0, s2, 3 -; GFX10-NEXT: s_lshl_b32 s0, s0, 3 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: v_mov_b32_e32 v3, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s0 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_vgpr_v4i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_and_b32 s0, s2, 3 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NEXT: s_lshl_b32 s0, s0, 3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i8>, ptr addrspace(1) %ptr @@ -101,55 +147,60 @@ define i8 @extractelement_vgpr_v4i8_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) { ; GFX9-LABEL: extractelement_vgpr_v4i8_vgpr_idx: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dword v0, v[0:1], off -; GFX9-NEXT: v_and_b32_e32 v1, 3, v2 -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GFX9-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i8_vgpr_idx: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dword v0, v[0:1] -; GFX8-NEXT: v_and_b32_e32 v1, 3, v2 -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GFX8-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v4i8_vgpr_idx: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX7-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: v_and_b32_e32 v1, 3, v2 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i8_vgpr_idx: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dword v0, v[0:1], off -; GFX10-NEXT: v_and_b32_e32 v1, 3, v2 -; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GFX10-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i8_vgpr_idx: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b32 v0, v[0:1], off -; GFX11-NEXT: v_and_b32_e32 v1, 3, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GFX11-NEXT: v_and_b32_e32 v2, 3, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i8>, ptr addrspace(1) %ptr %element = extractelement <4 x i8> %vector, i32 %idx @@ -159,53 +210,67 @@ define i8 @extractelement_vgpr_v4i8_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) { define amdgpu_ps i8 @extractelement_sgpr_v4i8_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) { ; GFX9-LABEL: extractelement_sgpr_v4i8_vgpr_idx: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX9-NEXT: v_and_b32_e32 v0, 3, v0 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s0 +; GFX9-NEXT: v_and_b32_e32 v2, 3, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: extractelement_sgpr_v4i8_vgpr_idx: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX8-NEXT: v_and_b32_e32 v0, 3, v0 -; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX8-NEXT: s_waitcnt lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s0 +; GFX8-NEXT: v_and_b32_e32 v2, 3, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX7-LABEL: extractelement_sgpr_v4i8_vgpr_idx: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_load_dword s0, s[2:3], 0x0 ; GFX7-NEXT: v_and_b32_e32 v0, 3, v0 -; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: v_lshr_b32_e32 v0, s0, v0 +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i8_vgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX10-NEXT: v_and_b32_e32 v0, 3, v0 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s0 +; GFX10-NEXT: v_and_b32_e32 v2, 3, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i8_vgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: v_and_b32_e32 v0, 3, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e64 v0, v0, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_and_b32_e32 v2, 3, v0 +; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i8>, ptr addrspace(4) %ptr @@ -214,22 +279,48 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_vgpr_idx(ptr addrspace(4) inreg %p } define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx0(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i8_idx0: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s0, s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i8_idx0: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i8_idx0: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i8_idx0: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i8_idx0: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i8_idx0: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i8>, ptr addrspace(4) %ptr %element = extractelement <4 x i8> %vector, i32 0 @@ -237,25 +328,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx0(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx1(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i8_idx1: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s0, s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s0, 8 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i8_idx1: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:1 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i8_idx1: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 1 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i8_idx1: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:1 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i8_idx1: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s0, 8 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:1 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i8_idx1: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s0, 8 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:1 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i8>, ptr addrspace(4) %ptr %element = extractelement <4 x i8> %vector, i32 1 @@ -263,25 +379,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx1(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx2(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i8_idx2: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s0, s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s0, 16 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i8_idx2: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i8_idx2: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 2 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i8_idx2: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:2 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i8_idx2: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s0, 16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i8_idx2: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s0, 16 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:2 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i8>, ptr addrspace(4) %ptr %element = extractelement <4 x i8> %vector, i32 2 @@ -289,25 +430,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx2(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx3(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v4i8_idx3: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s0, s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s0, 24 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v4i8_idx3: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:3 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v4i8_idx3: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 3 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v4i8_idx3: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:3 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v4i8_idx3: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dword s0, s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s0, 24 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:3 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v4i8_idx3: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s0, 24 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:3 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <4 x i8>, ptr addrspace(4) %ptr %element = extractelement <4 x i8> %vector, i32 3 @@ -318,14 +484,14 @@ define i8 @extractelement_vgpr_v4i8_idx0(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v4i8_idx0: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i8_idx0: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dword v0, v[0:1] +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -335,21 +501,21 @@ define i8 @extractelement_vgpr_v4i8_idx0(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i8_idx0: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dword v0, v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i8_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b32 v0, v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i8>, ptr addrspace(1) %ptr @@ -361,17 +527,17 @@ define i8 @extractelement_vgpr_v4i8_idx1(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v4i8_idx1: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:1 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i8_idx1: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dword v0, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 1, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v4i8_idx1: @@ -380,25 +546,22 @@ define i8 @extractelement_vgpr_v4i8_idx1(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:1 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i8_idx1: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dword v0, v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:1 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i8_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b32 v0, v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:1 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i8>, ptr addrspace(1) %ptr %element = extractelement <4 x i8> %vector, i32 1 @@ -409,17 +572,17 @@ define i8 @extractelement_vgpr_v4i8_idx2(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v4i8_idx2: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:2 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i8_idx2: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dword v0, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v4i8_idx2: @@ -428,25 +591,22 @@ define i8 @extractelement_vgpr_v4i8_idx2(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:2 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i8_idx2: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dword v0, v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i8_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b32 v0, v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:2 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i8>, ptr addrspace(1) %ptr %element = extractelement <4 x i8> %vector, i32 2 @@ -457,17 +617,17 @@ define i8 @extractelement_vgpr_v4i8_idx3(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v4i8_idx3: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:3 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v4i8_idx3: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dword v0, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 3, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v4i8_idx3: @@ -476,25 +636,22 @@ define i8 @extractelement_vgpr_v4i8_idx3(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:3 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v4i8_idx3: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dword v0, v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:3 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v4i8_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b32 v0, v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:3 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <4 x i8>, ptr addrspace(1) %ptr %element = extractelement <4 x i8> %vector, i32 3 @@ -502,42 +659,68 @@ define i8 @extractelement_vgpr_v4i8_idx3(ptr addrspace(1) %ptr) { } define amdgpu_ps i8 @extractelement_sgpr_v8i8_sgpr_idx(ptr addrspace(4) inreg %ptr, i32 inreg %idx) { -; GCN-LABEL: extractelement_sgpr_v8i8_sgpr_idx: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_lshr_b32 s2, s4, 2 -; GCN-NEXT: s_cmp_eq_u32 s2, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_cselect_b32 s0, s1, s0 -; GCN-NEXT: s_and_b32 s1, s4, 3 -; GCN-NEXT: s_lshl_b32 s1, s1, 3 -; GCN-NEXT: s_lshr_b32 s0, s0, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_sgpr_idx: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_and_b32 s0, s4, 7 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: s_add_u32 s0, s2, s0 +; GFX9-NEXT: s_addc_u32 s1, s3, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_sgpr_idx: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_and_b32 s0, s4, 7 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: s_add_u32 s0, s2, s0 +; GFX8-NEXT: s_addc_u32 s1, s3, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_sgpr_idx: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_and_b32 s4, s4, 7 +; GFX7-NEXT: s_ashr_i32 s5, s4, 31 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_lshr_b32 s2, s4, 2 -; GFX10-NEXT: s_cmp_eq_u32 s2, 1 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_cselect_b32 s0, s1, s0 -; GFX10-NEXT: s_and_b32 s1, s4, 3 -; GFX10-NEXT: s_lshl_b32 s1, s1, 3 -; GFX10-NEXT: s_lshr_b32 s0, s0, s1 +; GFX10-NEXT: s_and_b32 s0, s4, 7 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: s_add_u32 s0, s2, s0 +; GFX10-NEXT: s_addc_u32 s1, s3, s1 +; GFX10-NEXT: global_load_ubyte v0, v0, s[0:1] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_lshr_b32 s2, s4, 2 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_cmp_eq_u32 s2, 1 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_cselect_b32 s0, s1, s0 -; GFX11-NEXT: s_and_b32 s1, s4, 3 -; GFX11-NEXT: s_lshl_b32 s1, s1, 3 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_lshr_b32 s0, s0, s1 +; GFX11-NEXT: s_and_b32 s0, s4, 7 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: s_add_u32 s0, s2, s0 +; GFX11-NEXT: s_addc_u32 s1, s3, s1 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr %element = extractelement <8 x i8> %vector, i32 %idx @@ -547,71 +730,65 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_sgpr_idx(ptr addrspace(4) inreg %p define amdgpu_ps i8 @extractelement_vgpr_v8i8_sgpr_idx(ptr addrspace(1) %ptr, i32 inreg %idx) { ; GFX9-LABEL: extractelement_vgpr_v8i8_sgpr_idx: ; GFX9: ; %bb.0: -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX9-NEXT: s_lshr_b32 s0, s2, 2 -; GFX9-NEXT: s_and_b32 s1, s2, 3 -; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX9-NEXT: s_lshl_b32 s0, s1, 3 +; GFX9-NEXT: s_and_b32 s0, s2, 7 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: extractelement_vgpr_v8i8_sgpr_idx: ; GFX8: ; %bb.0: -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] -; GFX8-NEXT: s_lshr_b32 s0, s2, 2 -; GFX8-NEXT: s_and_b32 s1, s2, 3 -; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX8-NEXT: s_lshl_b32 s0, s1, 3 +; GFX8-NEXT: s_and_b32 s0, s2, 7 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX7-LABEL: extractelement_vgpr_v8i8_sgpr_idx: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_mov_b32 s6, 0 -; GFX7-NEXT: s_mov_b32 s7, 0xf000 -; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: s_lshr_b32 s0, s2, 2 -; GFX7-NEXT: s_and_b32 s1, s2, 3 -; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX7-NEXT: s_lshl_b32 s0, s1, 3 +; GFX7-NEXT: s_and_b32 s0, s2, 7 +; GFX7-NEXT: s_ashr_i32 s1, s0, 31 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_vgpr_v8i8_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-NEXT: s_lshr_b32 s0, s2, 2 -; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1 -; GFX10-NEXT: s_and_b32 s0, s2, 3 -; GFX10-NEXT: s_lshl_b32 s0, s0, 3 +; GFX10-NEXT: s_and_b32 s0, s2, 7 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: v_mov_b32_e32 v3, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s0 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_vgpr_v8i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: s_lshr_b32 s0, s2, 2 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1 -; GFX11-NEXT: s_and_b32 s0, s2, 3 -; GFX11-NEXT: s_lshl_b32 s0, s0, 3 +; GFX11-NEXT: s_and_b32 s0, s2, 7 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(1) %ptr @@ -623,70 +800,60 @@ define i8 @extractelement_vgpr_v8i8_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) { ; GFX9-LABEL: extractelement_vgpr_v8i8_vgpr_idx: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 2, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 3, v2 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3 +; GFX9-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 3, v2 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i8_vgpr_idx: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 2, v2 -; GFX8-NEXT: v_and_b32_e32 v2, 3, v2 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3 +; GFX8-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i8_vgpr_idx: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX7-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: v_lshrrev_b32_e32 v3, 2, v2 -; GFX7-NEXT: v_and_b32_e32 v2, 3, v2 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v2 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i8_vgpr_idx: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 2, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 3, v2 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 +; GFX10-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i8_vgpr_idx: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: v_lshrrev_b32_e32 v3, 2, v2 -; GFX11-NEXT: v_and_b32_e32 v2, 3, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 +; GFX11-NEXT: v_and_b32_e32 v2, 7, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_lshlrev_b32 v1, 3, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i8>, ptr addrspace(1) %ptr %element = extractelement <8 x i8> %vector, i32 %idx @@ -694,48 +861,69 @@ define i8 @extractelement_vgpr_v8i8_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) { } define amdgpu_ps i8 @extractelement_sgpr_v8i8_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) { -; GCN-LABEL: extractelement_sgpr_v8i8_vgpr_idx: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: v_lshrrev_b32_e32 v1, 2, v0 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 -; GCN-NEXT: v_and_b32_e32 v0, 3, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v2, s0 -; GCN-NEXT: v_mov_b32_e32 v3, s1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, v0, v1 -; GCN-NEXT: v_readfirstlane_b32 s0, v0 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_vgpr_idx: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_and_b32_e32 v2, 7, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_vgpr_idx: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_and_b32_e32 v2, 7, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_vgpr_idx: +; GFX7: ; %bb.0: +; GFX7-NEXT: v_and_b32_e32 v0, 7, v0 +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_vgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 2, v0 -; GFX10-NEXT: v_and_b32_e32 v0, 3, v0 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v2, s1 -; GFX10-NEXT: v_cndmask_b32_e32 v1, s0, v2, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v0, v0, v1 +; GFX10-NEXT: v_and_b32_e32 v2, 7, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_vgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: v_lshrrev_b32_e32 v1, 2, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-NEXT: v_dual_cndmask_b32 v1, s0, v2 :: v_dual_and_b32 v0, 3, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX11-NEXT: v_lshrrev_b32_e32 v0, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_and_b32_e32 v2, 7, v0 +; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr @@ -744,22 +932,48 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_vgpr_idx(ptr addrspace(4) inreg %p } define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx0(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i8_idx0: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_idx0: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_idx0: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_idx0: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_idx0: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_idx0: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr %element = extractelement <8 x i8> %vector, i32 0 @@ -767,25 +981,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx0(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx1(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i8_idx1: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s0, 8 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_idx1: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:1 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_idx1: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 1 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_idx1: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:1 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_idx1: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s0, 8 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:1 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_idx1: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s0, 8 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:1 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr %element = extractelement <8 x i8> %vector, i32 1 @@ -793,25 +1032,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx1(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx2(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i8_idx2: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s0, 16 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_idx2: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_idx2: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 2 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_idx2: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:2 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_idx2: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s0, 16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_idx2: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s0, 16 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:2 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr %element = extractelement <8 x i8> %vector, i32 2 @@ -819,25 +1083,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx2(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx3(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i8_idx3: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s0, 24 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_idx3: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:3 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_idx3: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 3 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_idx3: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:3 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_idx3: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s0, 24 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:3 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_idx3: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s0, 24 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:3 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr %element = extractelement <8 x i8> %vector, i32 3 @@ -845,25 +1134,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx3(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx4(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i8_idx4: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_idx4: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_idx4: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 4 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_idx4: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:4 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_idx4: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_mov_b32 s0, s1 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:4 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_idx4: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s0, s1 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:4 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr %element = extractelement <8 x i8> %vector, i32 4 @@ -871,25 +1185,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx4(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx5(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i8_idx5: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s1, 8 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_idx5: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:5 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_idx5: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 5 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_idx5: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:5 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_idx5: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s1, 8 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:5 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_idx5: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s1, 8 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:5 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr %element = extractelement <8 x i8> %vector, i32 5 @@ -897,25 +1236,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx5(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx6(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i8_idx6: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s1, 16 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_idx6: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:6 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_idx6: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 6 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_idx6: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:6 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_idx6: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s1, 16 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:6 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_idx6: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s1, 16 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:6 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr %element = extractelement <8 x i8> %vector, i32 6 @@ -923,25 +1287,50 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx6(ptr addrspace(4) inreg %ptr) } define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx7(ptr addrspace(4) inreg %ptr) { -; GCN-LABEL: extractelement_sgpr_v8i8_idx7: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s0, s1, 24 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v8i8_idx7: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:7 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v8i8_idx7: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_add_u32 s0, s2, 7 +; GFX8-NEXT: s_addc_u32 s1, s3, 0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v8i8_idx7: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:7 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v8i8_idx7: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_lshr_b32 s0, s1, 24 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:7 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v8i8_idx7: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s0, s1, 24 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:7 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <8 x i8>, ptr addrspace(4) %ptr %element = extractelement <8 x i8> %vector, i32 7 @@ -952,14 +1341,14 @@ define i8 @extractelement_vgpr_v8i8_idx0(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i8_idx0: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i8_idx0: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -969,21 +1358,21 @@ define i8 @extractelement_vgpr_v8i8_idx0(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i8_idx0: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i8_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i8>, ptr addrspace(1) %ptr @@ -995,17 +1384,17 @@ define i8 @extractelement_vgpr_v8i8_idx1(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i8_idx1: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:1 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i8_idx1: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 1, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i8_idx1: @@ -1014,25 +1403,22 @@ define i8 @extractelement_vgpr_v8i8_idx1(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:1 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i8_idx1: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:1 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i8_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:1 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i8>, ptr addrspace(1) %ptr %element = extractelement <8 x i8> %vector, i32 1 @@ -1043,17 +1429,17 @@ define i8 @extractelement_vgpr_v8i8_idx2(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i8_idx2: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:2 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i8_idx2: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i8_idx2: @@ -1062,25 +1448,22 @@ define i8 @extractelement_vgpr_v8i8_idx2(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:2 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i8_idx2: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i8_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:2 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i8>, ptr addrspace(1) %ptr %element = extractelement <8 x i8> %vector, i32 2 @@ -1091,17 +1474,17 @@ define i8 @extractelement_vgpr_v8i8_idx3(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i8_idx3: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:3 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i8_idx3: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 3, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i8_idx3: @@ -1110,25 +1493,22 @@ define i8 @extractelement_vgpr_v8i8_idx3(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:3 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i8_idx3: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:3 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i8_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:3 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i8>, ptr addrspace(1) %ptr %element = extractelement <8 x i8> %vector, i32 3 @@ -1139,17 +1519,17 @@ define i8 @extractelement_vgpr_v8i8_idx4(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i8_idx4: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:4 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i8_idx4: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i8_idx4: @@ -1158,25 +1538,22 @@ define i8 @extractelement_vgpr_v8i8_idx4(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v0, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i8_idx4: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i8_idx4: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i8>, ptr addrspace(1) %ptr %element = extractelement <8 x i8> %vector, i32 4 @@ -1187,17 +1564,17 @@ define i8 @extractelement_vgpr_v8i8_idx5(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i8_idx5: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:5 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i8_idx5: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 5, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i8_idx5: @@ -1206,25 +1583,22 @@ define i8 @extractelement_vgpr_v8i8_idx5(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:5 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i8_idx5: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:5 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i8_idx5: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:5 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i8>, ptr addrspace(1) %ptr %element = extractelement <8 x i8> %vector, i32 5 @@ -1235,17 +1609,17 @@ define i8 @extractelement_vgpr_v8i8_idx6(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i8_idx6: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:6 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i8_idx6: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 6, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i8_idx6: @@ -1254,25 +1628,22 @@ define i8 @extractelement_vgpr_v8i8_idx6(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:6 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i8_idx6: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:6 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i8_idx6: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:6 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i8>, ptr addrspace(1) %ptr %element = extractelement <8 x i8> %vector, i32 6 @@ -1283,17 +1654,17 @@ define i8 @extractelement_vgpr_v8i8_idx7(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v8i8_idx7: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:7 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v8i8_idx7: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 7, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v8i8_idx7: @@ -1302,25 +1673,22 @@ define i8 @extractelement_vgpr_v8i8_idx7(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:7 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v8i8_idx7: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:7 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v8i8_idx7: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:7 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <8 x i8>, ptr addrspace(1) %ptr %element = extractelement <8 x i8> %vector, i32 7 @@ -1328,54 +1696,68 @@ define i8 @extractelement_vgpr_v8i8_idx7(ptr addrspace(1) %ptr) { } define amdgpu_ps i8 @extractelement_sgpr_v16i8_sgpr_idx(ptr addrspace(4) inreg %ptr, i32 inreg %idx) { -; GCN-LABEL: extractelement_sgpr_v16i8_sgpr_idx: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: s_lshr_b32 s5, s4, 2 -; GCN-NEXT: s_cmp_eq_u32 s5, 1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_cselect_b32 s0, s1, s0 -; GCN-NEXT: s_cmp_eq_u32 s5, 2 -; GCN-NEXT: s_cselect_b32 s0, s2, s0 -; GCN-NEXT: s_cmp_eq_u32 s5, 3 -; GCN-NEXT: s_cselect_b32 s0, s3, s0 -; GCN-NEXT: s_and_b32 s1, s4, 3 -; GCN-NEXT: s_lshl_b32 s1, s1, 3 -; GCN-NEXT: s_lshr_b32 s0, s0, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v16i8_sgpr_idx: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_and_b32 s0, s4, 15 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: s_add_u32 s0, s2, s0 +; GFX9-NEXT: s_addc_u32 s1, s3, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v16i8_sgpr_idx: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_and_b32 s0, s4, 15 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: s_add_u32 s0, s2, s0 +; GFX8-NEXT: s_addc_u32 s1, s3, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v16i8_sgpr_idx: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_and_b32 s4, s4, 15 +; GFX7-NEXT: s_ashr_i32 s5, s4, 31 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v16i8_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: s_lshr_b32 s5, s4, 2 -; GFX10-NEXT: s_cmp_eq_u32 s5, 1 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_cselect_b32 s0, s1, s0 -; GFX10-NEXT: s_cmp_eq_u32 s5, 2 -; GFX10-NEXT: s_cselect_b32 s0, s2, s0 -; GFX10-NEXT: s_cmp_eq_u32 s5, 3 -; GFX10-NEXT: s_cselect_b32 s0, s3, s0 -; GFX10-NEXT: s_and_b32 s1, s4, 3 -; GFX10-NEXT: s_lshl_b32 s1, s1, 3 -; GFX10-NEXT: s_lshr_b32 s0, s0, s1 +; GFX10-NEXT: s_and_b32 s0, s4, 15 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: s_add_u32 s0, s2, s0 +; GFX10-NEXT: s_addc_u32 s1, s3, s1 +; GFX10-NEXT: global_load_ubyte v0, v0, s[0:1] +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v16i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_lshr_b32 s5, s4, 2 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_cmp_eq_u32 s5, 1 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_cselect_b32 s0, s1, s0 -; GFX11-NEXT: s_cmp_eq_u32 s5, 2 -; GFX11-NEXT: s_cselect_b32 s0, s2, s0 -; GFX11-NEXT: s_cmp_eq_u32 s5, 3 -; GFX11-NEXT: s_cselect_b32 s0, s3, s0 -; GFX11-NEXT: s_and_b32 s1, s4, 3 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_lshl_b32 s1, s1, 3 -; GFX11-NEXT: s_lshr_b32 s0, s0, s1 +; GFX11-NEXT: s_and_b32 s0, s4, 15 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: s_add_u32 s0, s2, s0 +; GFX11-NEXT: s_addc_u32 s1, s3, s1 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <16 x i8>, ptr addrspace(4) %ptr %element = extractelement <16 x i8> %vector, i32 %idx @@ -1385,92 +1767,65 @@ define amdgpu_ps i8 @extractelement_sgpr_v16i8_sgpr_idx(ptr addrspace(4) inreg % define amdgpu_ps i8 @extractelement_vgpr_v16i8_sgpr_idx(ptr addrspace(1) %ptr, i32 inreg %idx) { ; GFX9-LABEL: extractelement_vgpr_v16i8_sgpr_idx: ; GFX9: ; %bb.0: -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX9-NEXT: s_lshr_b32 s0, s2, 2 -; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX9-NEXT: s_and_b32 s1, s2, 3 +; GFX9-NEXT: s_and_b32 s0, s2, 15 +; GFX9-NEXT: s_ashr_i32 s1, s0, 31 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX9-NEXT: s_lshl_b32 s0, s1, 3 -; GFX9-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: extractelement_vgpr_v16i8_sgpr_idx: ; GFX8: ; %bb.0: -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] -; GFX8-NEXT: s_lshr_b32 s0, s2, 2 -; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX8-NEXT: s_and_b32 s1, s2, 3 +; GFX8-NEXT: s_and_b32 s0, s2, 15 +; GFX8-NEXT: s_ashr_i32 s1, s0, 31 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX8-NEXT: s_lshl_b32 s0, s1, 3 -; GFX8-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX7-LABEL: extractelement_vgpr_v16i8_sgpr_idx: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_mov_b32 s6, 0 -; GFX7-NEXT: s_mov_b32 s7, 0xf000 -; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: s_lshr_b32 s0, s2, 2 -; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1 -; GFX7-NEXT: s_and_b32 s1, s2, 3 +; GFX7-NEXT: s_and_b32 s0, s2, 15 +; GFX7-NEXT: s_ashr_i32 s1, s0, 31 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX7-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX7-NEXT: s_lshl_b32 s0, s1, 3 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_vgpr_v16i8_sgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-NEXT: s_lshr_b32 s0, s2, 2 -; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1 +; GFX10-NEXT: s_and_b32 s0, s2, 15 +; GFX10-NEXT: s_ashr_i32 s1, s0, 31 +; GFX10-NEXT: v_mov_b32_e32 v3, s1 +; GFX10-NEXT: v_mov_b32_e32 v2, s0 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 2 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 3 -; GFX10-NEXT: s_and_b32 s0, s2, 3 -; GFX10-NEXT: s_lshl_b32 s0, s0, 3 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_vgpr_v16i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off -; GFX11-NEXT: s_lshr_b32 s0, s2, 2 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 1 +; GFX11-NEXT: s_and_b32 s0, s2, 15 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_ashr_i32 s1, s0, 31 +; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 2 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s0, 3 -; GFX11-NEXT: s_and_b32 s0, s2, 3 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: s_lshl_b32 s0, s0, 3 -; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <16 x i8>, ptr addrspace(1) %ptr @@ -1482,91 +1837,60 @@ define i8 @extractelement_vgpr_v16i8_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) { ; GFX9-LABEL: extractelement_vgpr_v16i8_vgpr_idx: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[3:6], v[0:1], off -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 2, v2 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX9-NEXT: v_and_b32_e32 v1, 3, v2 -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GFX9-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_vgpr_idx: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1] -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 2, v2 -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_and_b32_e32 v1, 3, v2 -; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GFX8-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc -; GFX8-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_vgpr_idx: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX7-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[4:7], 0 addr64 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 2, v2 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX7-NEXT: v_and_b32_e32 v1, 3, v2 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc -; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_vgpr_idx: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 2, v2 -; GFX10-NEXT: v_and_b32_e32 v2, 3, v2 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX10-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v6, vcc_lo -; GFX10-NEXT: v_lshlrev_b32_e32 v1, 3, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_vgpr_idx: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 2, v2 -; GFX11-NEXT: v_and_b32_e32 v2, 3, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX11-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v6, vcc_lo -; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 %idx @@ -1574,64 +1898,69 @@ define i8 @extractelement_vgpr_v16i8_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) { } define amdgpu_ps i8 @extractelement_sgpr_v16i8_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) { -; GCN-LABEL: extractelement_sgpr_v16i8_vgpr_idx: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GCN-NEXT: v_lshrrev_b32_e32 v1, 2, v0 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 -; GCN-NEXT: v_and_b32_e32 v0, 3, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v2, s0 -; GCN-NEXT: v_mov_b32_e32 v3, s1 -; GCN-NEXT: v_mov_b32_e32 v4, s2 -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1 -; GCN-NEXT: v_mov_b32_e32 v5, s3 -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc -; GCN-NEXT: v_lshrrev_b32_e32 v0, v0, v1 -; GCN-NEXT: v_readfirstlane_b32 s0, v0 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: extractelement_sgpr_v16i8_vgpr_idx: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_and_b32_e32 v2, 15, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX8-LABEL: extractelement_sgpr_v16i8_vgpr_idx: +; GFX8: ; %bb.0: +; GFX8-NEXT: v_and_b32_e32 v2, 15, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: ; return to shader part epilog +; +; GFX7-LABEL: extractelement_sgpr_v16i8_vgpr_idx: +; GFX7: ; %bb.0: +; GFX7-NEXT: v_and_b32_e32 v0, 15, v0 +; GFX7-NEXT: s_mov_b32 s0, s2 +; GFX7-NEXT: s_mov_b32 s1, s3 +; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GFX7-NEXT: s_mov_b32 s2, 0 +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[0:3], 0 addr64 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_readfirstlane_b32 s0, v0 +; GFX7-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: extractelement_sgpr_v16i8_vgpr_idx: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 2, v0 -; GFX10-NEXT: v_and_b32_e32 v0, 3, v0 -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v2, s1 -; GFX10-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo -; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s3, vcc_lo -; GFX10-NEXT: v_lshrrev_b32_e32 v0, v0, v1 +; GFX10-NEXT: v_and_b32_e32 v2, 15, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: extractelement_sgpr_v16i8_vgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: v_lshrrev_b32_e32 v1, 2, v0 -; GFX11-NEXT: v_and_b32_e32 v0, 3, v0 +; GFX11-NEXT: v_and_b32_e32 v2, 15, v0 +; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v2, s1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s3, vcc_lo -; GFX11-NEXT: v_lshrrev_b32_e32 v0, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog %vector = load <16 x i8>, ptr addrspace(4) %ptr @@ -1643,14 +1972,14 @@ define i8 @extractelement_vgpr_v16i8_idx0(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx0: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx0: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -1660,21 +1989,21 @@ define i8 @extractelement_vgpr_v16i8_idx0(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx0: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr @@ -1686,17 +2015,17 @@ define i8 @extractelement_vgpr_v16i8_idx1(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx1: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:1 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx1: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 1, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx1: @@ -1705,25 +2034,22 @@ define i8 @extractelement_vgpr_v16i8_idx1(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:1 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx1: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:1 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:1 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 1 @@ -1734,17 +2060,17 @@ define i8 @extractelement_vgpr_v16i8_idx2(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx2: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:2 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx2: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx2: @@ -1753,25 +2079,22 @@ define i8 @extractelement_vgpr_v16i8_idx2(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:2 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx2: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:2 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 2 @@ -1782,17 +2105,17 @@ define i8 @extractelement_vgpr_v16i8_idx3(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx3: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:3 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx3: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 3, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx3: @@ -1801,25 +2124,22 @@ define i8 @extractelement_vgpr_v16i8_idx3(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:3 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx3: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:3 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:3 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 24, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 3 @@ -1830,17 +2150,17 @@ define i8 @extractelement_vgpr_v16i8_idx4(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx4: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:4 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx4: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_mov_b32_e32 v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx4: @@ -1849,25 +2169,22 @@ define i8 @extractelement_vgpr_v16i8_idx4(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v0, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx4: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx4: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 4 @@ -1878,17 +2195,17 @@ define i8 @extractelement_vgpr_v16i8_idx5(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx5: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:5 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx5: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 5, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx5: @@ -1897,25 +2214,22 @@ define i8 @extractelement_vgpr_v16i8_idx5(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:5 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx5: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:5 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx5: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:5 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 8, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 5 @@ -1926,17 +2240,17 @@ define i8 @extractelement_vgpr_v16i8_idx6(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx6: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:6 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx6: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 6, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx6: @@ -1945,25 +2259,22 @@ define i8 @extractelement_vgpr_v16i8_idx6(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:6 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx6: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:6 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx6: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:6 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 6 @@ -1974,17 +2285,17 @@ define i8 @extractelement_vgpr_v16i8_idx7(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx7: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:7 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx7: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 7, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx7: @@ -1993,25 +2304,22 @@ define i8 @extractelement_vgpr_v16i8_idx7(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:7 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx7: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:7 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx7: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:7 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 24, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 7 @@ -2022,17 +2330,17 @@ define i8 @extractelement_vgpr_v16i8_idx8(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:8 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx8: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_mov_b32_e32 v0, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx8: @@ -2041,25 +2349,22 @@ define i8 @extractelement_vgpr_v16i8_idx8(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:8 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v0, v2 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx8: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:8 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx8: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:8 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 8 @@ -2070,17 +2375,17 @@ define i8 @extractelement_vgpr_v16i8_idx9(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx9: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:9 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx9: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 9, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx9: @@ -2089,25 +2394,22 @@ define i8 @extractelement_vgpr_v16i8_idx9(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:9 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v2 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx9: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:9 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v2 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx9: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:9 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 8, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 9 @@ -2118,17 +2420,17 @@ define i8 @extractelement_vgpr_v16i8_idx10(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx10: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:10 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx10: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 10, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx10: @@ -2137,25 +2439,22 @@ define i8 @extractelement_vgpr_v16i8_idx10(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:10 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx10: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:10 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx10: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:10 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 10 @@ -2166,17 +2465,17 @@ define i8 @extractelement_vgpr_v16i8_idx11(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx11: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:11 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 24, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx11: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 11, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx11: @@ -2185,25 +2484,22 @@ define i8 @extractelement_vgpr_v16i8_idx11(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:11 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v2 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx11: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:11 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v2 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx11: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:11 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 24, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 11 @@ -2214,17 +2510,17 @@ define i8 @extractelement_vgpr_v16i8_idx12(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx12: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:12 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx12: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 12, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_mov_b32_e32 v0, v3 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx12: @@ -2233,25 +2529,22 @@ define i8 @extractelement_vgpr_v16i8_idx12(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:12 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v0, v3 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx12: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:12 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx12: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:12 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 12 @@ -2262,17 +2555,17 @@ define i8 @extractelement_vgpr_v16i8_idx13(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx13: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:13 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx13: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 13, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v3 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx13: @@ -2281,25 +2574,22 @@ define i8 @extractelement_vgpr_v16i8_idx13(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:13 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v3 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx13: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:13 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx13: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:13 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 8, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 13 @@ -2310,17 +2600,17 @@ define i8 @extractelement_vgpr_v16i8_idx14(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx14: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:14 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx14: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 14, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx14: @@ -2329,25 +2619,22 @@ define i8 @extractelement_vgpr_v16i8_idx14(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:14 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx14: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:14 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx14: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:14 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 14 @@ -2358,17 +2645,17 @@ define i8 @extractelement_vgpr_v16i8_idx15(ptr addrspace(1) %ptr) { ; GFX9-LABEL: extractelement_vgpr_v16i8_idx15: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:15 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 24, v3 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: extractelement_vgpr_v16i8_idx15: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 15, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v3 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX7-LABEL: extractelement_vgpr_v16i8_idx15: @@ -2377,27 +2664,26 @@ define i8 @extractelement_vgpr_v16i8_idx15(ptr addrspace(1) %ptr) { ; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b64 s[4:5], 0 -; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 offset:15 ; GFX7-NEXT: s_waitcnt vmcnt(0) -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v3 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: extractelement_vgpr_v16i8_idx15: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:15 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: extractelement_vgpr_v16i8_idx15: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:15 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_lshrrev_b32_e32 v0, 24, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vector = load <16 x i8>, ptr addrspace(1) %ptr %element = extractelement <16 x i8> %vector, i32 15 ret i8 %element } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GCN: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll index 8bf34caea405..d4c536bdd5eb 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll @@ -4738,35 +4738,31 @@ define i32 @v_extract_v64i32_7(ptr addrspace(1) %ptr) { ; GPRIDX-LABEL: v_extract_v64i32_7: ; GPRIDX: ; %bb.0: ; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GPRIDX-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:16 +; GPRIDX-NEXT: global_load_dword v0, v[0:1], off offset:28 ; GPRIDX-NEXT: s_waitcnt vmcnt(0) -; GPRIDX-NEXT: v_mov_b32_e32 v0, v7 ; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; ; MOVREL-LABEL: v_extract_v64i32_7: ; MOVREL: ; %bb.0: ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 16, v0 +; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 28, v0 ; MOVREL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; MOVREL-NEXT: flat_load_dwordx4 v[4:7], v[0:1] +; MOVREL-NEXT: flat_load_dword v0, v[0:1] ; MOVREL-NEXT: s_waitcnt vmcnt(0) -; MOVREL-NEXT: v_mov_b32_e32 v0, v7 ; MOVREL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_extract_v64i32_7: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:16 +; GFX10-NEXT: global_load_dword v0, v[0:1], off offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v7 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_extract_v64i32_7: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off offset:16 +; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v7 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vec = load <64 x i32>, ptr addrspace(1) %ptr %elt = extractelement <64 x i32> %vec, i32 7 @@ -4777,7 +4773,7 @@ define i32 @v_extract_v64i32_32(ptr addrspace(1) %ptr) { ; GPRIDX-LABEL: v_extract_v64i32_32: ; GPRIDX: ; %bb.0: ; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GPRIDX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 +; GPRIDX-NEXT: global_load_dword v0, v[0:1], off offset:128 ; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; @@ -4786,21 +4782,21 @@ define i32 @v_extract_v64i32_32(ptr addrspace(1) %ptr) { ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 0x80, v0 ; MOVREL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; MOVREL-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; MOVREL-NEXT: flat_load_dword v0, v[0:1] ; MOVREL-NEXT: s_waitcnt vmcnt(0) ; MOVREL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_extract_v64i32_32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 +; GFX10-NEXT: global_load_dword v0, v[0:1], off offset:128 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_extract_v64i32_32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off offset:128 +; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] %vec = load <64 x i32>, ptr addrspace(1) %ptr @@ -4812,35 +4808,31 @@ define i32 @v_extract_v64i32_33(ptr addrspace(1) %ptr) { ; GPRIDX-LABEL: v_extract_v64i32_33: ; GPRIDX: ; %bb.0: ; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GPRIDX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 +; GPRIDX-NEXT: global_load_dword v0, v[0:1], off offset:132 ; GPRIDX-NEXT: s_waitcnt vmcnt(0) -; GPRIDX-NEXT: v_mov_b32_e32 v0, v1 ; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; ; MOVREL-LABEL: v_extract_v64i32_33: ; MOVREL: ; %bb.0: ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 0x80, v0 +; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 0x84, v0 ; MOVREL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; MOVREL-NEXT: flat_load_dwordx4 v[0:3], v[0:1] +; MOVREL-NEXT: flat_load_dword v0, v[0:1] ; MOVREL-NEXT: s_waitcnt vmcnt(0) -; MOVREL-NEXT: v_mov_b32_e32 v0, v1 ; MOVREL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_extract_v64i32_33: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:128 +; GFX10-NEXT: global_load_dword v0, v[0:1], off offset:132 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_extract_v64i32_33: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off offset:128 +; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:132 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vec = load <64 x i32>, ptr addrspace(1) %ptr %elt = extractelement <64 x i32> %vec, i32 33 @@ -4851,35 +4843,31 @@ define i32 @v_extract_v64i32_37(ptr addrspace(1) %ptr) { ; GPRIDX-LABEL: v_extract_v64i32_37: ; GPRIDX: ; %bb.0: ; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GPRIDX-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:144 +; GPRIDX-NEXT: global_load_dword v0, v[0:1], off offset:148 ; GPRIDX-NEXT: s_waitcnt vmcnt(0) -; GPRIDX-NEXT: v_mov_b32_e32 v0, v5 ; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; ; MOVREL-LABEL: v_extract_v64i32_37: ; MOVREL: ; %bb.0: ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 0x90, v0 +; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 0x94, v0 ; MOVREL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; MOVREL-NEXT: flat_load_dwordx4 v[4:7], v[0:1] +; MOVREL-NEXT: flat_load_dword v0, v[0:1] ; MOVREL-NEXT: s_waitcnt vmcnt(0) -; MOVREL-NEXT: v_mov_b32_e32 v0, v5 ; MOVREL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_extract_v64i32_37: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:144 +; GFX10-NEXT: global_load_dword v0, v[0:1], off offset:148 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_mov_b32_e32 v0, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_extract_v64i32_37: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off offset:144 +; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:148 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v0, v5 ; GFX11-NEXT: s_setpc_b64 s[30:31] %vec = load <64 x i32>, ptr addrspace(1) %ptr %elt = extractelement <64 x i32> %vec, i32 37 diff --git a/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir b/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir new file mode 100644 index 000000000000..7864564d2891 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir @@ -0,0 +1,143 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-regalloc -start-before=greedy,0 -stop-after=virtregrewriter,0 -simplify-mir -o - %s | FileCheck %s + +--- | + + define void @main() #0 { + bb: + ret void + } + + attributes #0 = { "amdgpu-waves-per-eu"="10,10" } + +... +--- +name: main +tracksRegLiveness: true +machineFunctionInfo: + scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' + frameOffsetReg: '$sgpr33' + stackPtrOffsetReg: '$sgpr32' + occupancy: 8 + sgprForEXECCopy: '$sgpr58_sgpr59' +body: | + ; CHECK-LABEL: name: main + ; CHECK: bb.0: + ; CHECK-NEXT: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $sgpr5 = IMPLICIT_DEF + ; CHECK-NEXT: dead undef [[DEF:%[0-9]+]].sub0:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: dead undef [[DEF2:%[0-9]+]].sub0:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = S_LOAD_DWORDX16_IMM renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4) + ; CHECK-NEXT: renamable $sgpr24 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = S_LOAD_DWORDX16_IMM undef renamable $sgpr4_sgpr5, 0, 0 :: (invariant load (s512), align 32, addrspace 4) + ; CHECK-NEXT: $exec = S_MOV_B64_term undef renamable $sgpr4_sgpr5 + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.6, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $exec = S_MOV_B64_term undef renamable $sgpr4_sgpr5 + ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.4, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_1:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: SI_RETURN + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $sgpr12 = IMPLICIT_DEF + ; CHECK-NEXT: SI_SPILL_S512_SAVE renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s512) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF + ; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_2:%[0-9]+]].sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = SI_SPILL_S512_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s512) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF + ; CHECK-NEXT: dead undef [[IMAGE_SAMPLE_LZ_V1_V2_3:%[0-9]+]].sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF2]], undef renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = COPY killed renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 + ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_4:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], killed renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr24_sgpr25_sgpr26_sgpr27, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + ; CHECK-NEXT: renamable $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51 = COPY killed renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 + ; CHECK-NEXT: S_BRANCH %bb.7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6: + ; CHECK-NEXT: liveins: $sgpr24_sgpr25_sgpr26_sgpr27:0x000000000000000F, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x000000000000FFFF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, undef renamable $sgpr4_sgpr5, implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.8, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7: + ; CHECK-NEXT: liveins: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19:0x000000000000FFFF, $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51:0x00000000FFFFFFFF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[IMAGE_SAMPLE_LZ_V1_V2_5:%[0-9]+]]:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef [[DEF]], renamable $sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, undef renamable $sgpr8_sgpr9_sgpr10_sgpr11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + ; CHECK-NEXT: renamable $sgpr25 = COPY undef renamable $sgpr24 + ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.7, implicit undef $vcc + ; CHECK-NEXT: S_BRANCH %bb.6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8: + ; CHECK-NEXT: SI_RETURN + bb.0: + liveins: $vgpr0 + + undef %0.sub1:sreg_64 = IMPLICIT_DEF + %1:sgpr_512 = IMPLICIT_DEF + dead undef %2.sub0:vreg_64 = IMPLICIT_DEF + %3:sgpr_256 = IMPLICIT_DEF + dead %4:vgpr_32 = IMPLICIT_DEF + dead undef %5.sub0:vreg_64 = IMPLICIT_DEF + %6:sgpr_512 = S_LOAD_DWORDX16_IMM %0, 0, 0 :: (invariant load (s512), align 32, addrspace 4) + undef %7.sub0:sgpr_128 = IMPLICIT_DEF + %8:sgpr_512 = S_LOAD_DWORDX16_IMM undef %0, 0, 0 :: (invariant load (s512), align 32, addrspace 4) + $exec = S_MOV_B64_term undef %0 + S_CBRANCH_EXECZ %bb.6, implicit $exec + S_BRANCH %bb.5 + + bb.1: + $exec = S_MOV_B64_term undef %0 + S_CBRANCH_EXECNZ %bb.4, implicit $exec + + bb.2: + dead %9:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %5, %6.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, undef %7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + dead %10:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %5, %8.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, %7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + + bb.3: + SI_RETURN + + bb.4: + undef %11.sub0:sgpr_128 = IMPLICIT_DEF + dead undef %12.sub0:vreg_96 = IMAGE_SAMPLE_LZ_V1_V2 undef %5, %1.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7, %11, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + dead undef %13.sub0:vreg_128 = IMAGE_SAMPLE_LZ_V1_V2 undef %5, undef %6.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, %3.sub0_sub1_sub2_sub3, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + S_BRANCH %bb.2 + + bb.5: + dead %14:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %2, %1.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, undef %7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + S_BRANCH %bb.7 + + bb.6: + $exec = S_XOR_B64_term $exec, undef %0, implicit-def $scc + S_CBRANCH_EXECZ %bb.8, implicit $exec + S_BRANCH %bb.1 + + bb.7: + dead %15:vgpr_32 = IMAGE_SAMPLE_LZ_V1_V2 undef %2, %6.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, undef %3.sub4_sub5_sub6_sub7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32), addrspace 8) + undef %7.sub1:sgpr_128 = COPY undef %7.sub0 + S_CBRANCH_VCCNZ %bb.7, implicit undef $vcc + S_BRANCH %bb.6 + + bb.8: + SI_RETURN + +... diff --git a/llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll b/llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll new file mode 100644 index 000000000000..50de3541e05b --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=WARN %s + +; 1024 flat work group size across 2560 possible threads -> occupancy should be 8 max. +; WARN: warning: :0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'occupancy_8_target_9': desired occupancy was 9, final occupancy is 8 +define amdgpu_kernel void @occupancy_8_target_9() #0 { + ret void +} + +; Impossible occupancy target +; WARN: warning: :0:0: failed to meet occupancy target given by 'amdgpu-waves-per-eu' in 'impossible_occupancy': desired occupancy was 11, final occupancy is 10 +define amdgpu_kernel void @impossible_occupancy() #1 { + ret void +} + +attributes #0 = { "amdgpu-flat-work-group-size"="1,1024" "amdgpu-waves-per-eu"="9" } +attributes #1 = { "amdgpu-flat-work-group-size"="1,256" "amdgpu-waves-per-eu"="11" } diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll index 3d12e44d46d2..85cd00cbfc53 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll @@ -961,61 +961,61 @@ for.body: ; preds = %for.body, %for.cond %load1 = load i64, ptr addrspace(1) %add.ptr8, align 8 %add = add i64 %load1, %sum.128 - %add9 = or i32 %block.029, 256 + %add9 = or disjoint i32 %block.029, 256 %conv3.1 = zext i32 %add9 to i64 %add.ptr8.1 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.1 %load2 = load i64, ptr addrspace(1) %add.ptr8.1, align 8 %add.1 = add i64 %load2, %add - %add9.1 = or i32 %block.029, 512 + %add9.1 = or disjoint i32 %block.029, 512 %conv3.2 = zext i32 %add9.1 to i64 %add.ptr8.2 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.2 %l3 = load i64, ptr addrspace(1) %add.ptr8.2, align 8 %add.2 = add i64 %l3, %add.1 - %add9.2 = or i32 %block.029, 768 + %add9.2 = or disjoint i32 %block.029, 768 %conv3.3 = zext i32 %add9.2 to i64 %add.ptr8.3 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.3 %l4 = load i64, ptr addrspace(1) %add.ptr8.3, align 8 %add.3 = add i64 %l4, %add.2 - %add9.3 = or i32 %block.029, 1024 + %add9.3 = or disjoint i32 %block.029, 1024 %conv3.4 = zext i32 %add9.3 to i64 %add.ptr8.4 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.4 %l5 = load i64, ptr addrspace(1) %add.ptr8.4, align 8 %add.4 = add i64 %l5, %add.3 - %add9.4 = or i32 %block.029, 1280 + %add9.4 = or disjoint i32 %block.029, 1280 %conv3.5 = zext i32 %add9.4 to i64 %add.ptr8.5 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.5 %l6 = load i64, ptr addrspace(1) %add.ptr8.5, align 8 %add.5 = add i64 %l6, %add.4 - %add9.5 = or i32 %block.029, 1536 + %add9.5 = or disjoint i32 %block.029, 1536 %conv3.6 = zext i32 %add9.5 to i64 %add.ptr8.6 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.6 %load7 = load i64, ptr addrspace(1) %add.ptr8.6, align 8 %add.6 = add i64 %load7, %add.5 - %add9.6 = or i32 %block.029, 1792 + %add9.6 = or disjoint i32 %block.029, 1792 %conv3.7 = zext i32 %add9.6 to i64 %add.ptr8.7 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.7 %load8 = load i64, ptr addrspace(1) %add.ptr8.7, align 8 %add.7 = add i64 %load8, %add.6 - %add9.7 = or i32 %block.029, 2048 + %add9.7 = or disjoint i32 %block.029, 2048 %conv3.8 = zext i32 %add9.7 to i64 %add.ptr8.8 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.8 %load9 = load i64, ptr addrspace(1) %add.ptr8.8, align 8 %add.8 = add i64 %load9, %add.7 - %add9.8 = or i32 %block.029, 2304 + %add9.8 = or disjoint i32 %block.029, 2304 %conv3.9 = zext i32 %add9.8 to i64 %add.ptr8.9 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.9 %load10 = load i64, ptr addrspace(1) %add.ptr8.9, align 8 %add.9 = add i64 %load10, %add.8 - %add9.9 = or i32 %block.029, 2560 + %add9.9 = or disjoint i32 %block.029, 2560 %conv3.10 = zext i32 %add9.9 to i64 %add.ptr8.10 = getelementptr inbounds i64, ptr addrspace(1) %add.ptr6, i64 %conv3.10 %load11 = load i64, ptr addrspace(1) %add.ptr8.10, align 8 diff --git a/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir b/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir index a1722c42b189..83e85ccf7f8f 100644 --- a/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir +++ b/llvm/test/CodeGen/AMDGPU/regpressure_printer.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --filetype=null --run-pass=amdgpu-print-rp %s 2>&1 >/dev/null | FileCheck %s --check-prefix=RP --check-prefix=RPU -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --filetype=null --run-pass=amdgpu-print-rp -amdgpu-print-rp-downward %s 2>&1 >/dev/null | FileCheck %s --check-prefix=RP --check-prefix=RPD +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --filetype=null -verify-machineinstrs --run-pass=amdgpu-print-rp %s 2>&1 >/dev/null | FileCheck %s --check-prefix=RP --check-prefix=RPU +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --filetype=null -verify-machineinstrs --run-pass=amdgpu-print-rp -amdgpu-print-rp-downward %s 2>&1 >/dev/null | FileCheck %s --check-prefix=RP --check-prefix=RPD --- @@ -666,3 +666,114 @@ body: | EXP_DONE 0, %49:vgpr_32, undef %51:vgpr_32, undef %53:vgpr_32, undef %55:vgpr_32, -1, 0, 1, implicit $exec S_ENDPGM 0 ... +--- +name: test_partially_used_def +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0_sgpr1_sgpr2_sgpr3 + ; RPU-LABEL: name: test_partially_used_def + ; RPU: Live-in: + ; RPU-NEXT: SGPR VGPR + ; RPU-NEXT: 0 0 + ; RPU-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 + ; RPU-NEXT: 4 0 + ; RPU-NEXT: 4 0 %1:sgpr_128 = COPY %0:sgpr_128 + ; RPU-NEXT: 1 0 + ; RPU-NEXT: 1 0 S_NOP 0, implicit %1.sub1:sgpr_128 + ; RPU-NEXT: 0 0 + ; RPU-NEXT: Live-out: + ; RPU-NEXT: Live-thr: + ; RPU-NEXT: 0 0 + ; + ; RPD-LABEL: name: test_partially_used_def + ; RPD: Live-in: + ; RPD-NEXT: SGPR VGPR + ; RPD-NEXT: 0 0 + ; RPD-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 + ; RPD-NEXT: 4 0 + ; RPD-NEXT: 8 0 %1:sgpr_128 = COPY %0:sgpr_128 + ; RPD-NEXT: 1 0 + ; RPD-NEXT: 1 0 S_NOP 0, implicit %1.sub1:sgpr_128 + ; RPD-NEXT: 0 0 + ; RPD-NEXT: Live-out: + ; RPD-NEXT: Live-thr: + ; RPD-NEXT: 0 0 + %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 + %1:sgpr_128 = COPY %0:sgpr_128 + S_NOP 0, implicit %1.sub1 +... +--- +name: test_partially_used_early_clobber_def +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0_sgpr1_sgpr2_sgpr3 + ; RPU-LABEL: name: test_partially_used_early_clobber_def + ; RPU: Live-in: + ; RPU-NEXT: SGPR VGPR + ; RPU-NEXT: 0 0 + ; RPU-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 + ; RPU-NEXT: 4 0 + ; RPU-NEXT: 5 0 early-clobber %1:sgpr_128 = COPY %0:sgpr_128 + ; RPU-NEXT: 1 0 + ; RPU-NEXT: 1 0 S_NOP 0, implicit %1.sub1:sgpr_128 + ; RPU-NEXT: 0 0 + ; RPU-NEXT: Live-out: + ; RPU-NEXT: Live-thr: + ; RPU-NEXT: 0 0 + ; + ; RPD-LABEL: name: test_partially_used_early_clobber_def + ; RPD: Live-in: + ; RPD-NEXT: SGPR VGPR + ; RPD-NEXT: 0 0 + ; RPD-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 + ; RPD-NEXT: 4 0 + ; RPD-NEXT: 8 0 early-clobber %1:sgpr_128 = COPY %0:sgpr_128 + ; RPD-NEXT: 1 0 + ; RPD-NEXT: 1 0 S_NOP 0, implicit %1.sub1:sgpr_128 + ; RPD-NEXT: 0 0 + ; RPD-NEXT: Live-out: + ; RPD-NEXT: Live-thr: + ; RPD-NEXT: 0 0 + %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 + early-clobber %1:sgpr_128 = COPY %0:sgpr_128 + S_NOP 0, implicit %1.sub1 +... +--- +name: test_partially_used_def_and_early_clobber_def +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0_sgpr1_sgpr2_sgpr3 + ; RPU-LABEL: name: test_partially_used_def_and_early_clobber_def + ; RPU: Live-in: + ; RPU-NEXT: SGPR VGPR + ; RPU-NEXT: 0 0 + ; RPU-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 + ; RPU-NEXT: 4 0 + ; RPU-NEXT: 7 0 %1:sgpr_128 = COPY %0:sgpr_128, implicit-def %2:sgpr_128, implicit-def early-clobber %3:sgpr_128, implicit-def dead early-clobber %4:sgpr_128 + ; RPU-NEXT: 6 0 + ; RPU-NEXT: 6 0 S_NOP 0, implicit %1.sub1:sgpr_128, implicit %2.sub0_sub1:sgpr_128, implicit %3.sub0_sub1_sub2:sgpr_128 + ; RPU-NEXT: 0 0 + ; RPU-NEXT: Live-out: + ; RPU-NEXT: Live-thr: + ; RPU-NEXT: 0 0 + ; + ; RPD-LABEL: name: test_partially_used_def_and_early_clobber_def + ; RPD: Live-in: + ; RPD-NEXT: SGPR VGPR + ; RPD-NEXT: 0 0 + ; RPD-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 + ; RPD-NEXT: 4 0 + ; RPD-NEXT: 20 0 %1:sgpr_128 = COPY %0:sgpr_128, implicit-def %2:sgpr_128, implicit-def early-clobber %3:sgpr_128, implicit-def dead early-clobber %4:sgpr_128 + ; RPD-NEXT: 6 0 + ; RPD-NEXT: 6 0 S_NOP 0, implicit %1.sub1:sgpr_128, implicit %2.sub0_sub1:sgpr_128, implicit %3.sub0_sub1_sub2:sgpr_128 + ; RPD-NEXT: 0 0 + ; RPD-NEXT: Live-out: + ; RPD-NEXT: Live-thr: + ; RPD-NEXT: 0 0 + %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 + %1:sgpr_128 = COPY %0:sgpr_128, implicit-def %2:sgpr_128, implicit-def early-clobber %3:sgpr_128, implicit-def early-clobber %4:sgpr_128 + S_NOP 0, implicit %1.sub1, implicit %2.sub0_sub1, implicit %3.sub0_sub1_sub2 +... diff --git a/llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll b/llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll new file mode 100644 index 000000000000..4987664dae02 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll @@ -0,0 +1,46 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GISEL + +define amdgpu_gfx i32 @sink_scratch_pointer(ptr addrspace(5) %stack, i32 inreg %flag) { +; GCN-LABEL: sink_scratch_pointer: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_cbranch_scc0 .LBB0_2 +; GCN-NEXT: ; %bb.1: ; %bb2 +; GCN-NEXT: scratch_load_b32 v0, v0, off offset:-4 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; GCN-NEXT: .LBB0_2: ; %bb1 +; GCN-NEXT: v_mov_b32_e32 v1, 1 +; GCN-NEXT: scratch_store_b32 v0, v1, off offset:-4 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-LABEL: sink_scratch_pointer: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_cbranch_scc0 .LBB0_2 +; GISEL-NEXT: ; %bb.1: ; %bb2 +; GISEL-NEXT: scratch_load_b32 v0, v0, off offset:-4 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_setpc_b64 s[30:31] +; GISEL-NEXT: .LBB0_2: ; %bb1 +; GISEL-NEXT: v_mov_b32_e32 v1, 1 +; GISEL-NEXT: scratch_store_b32 v0, v1, off offset:-4 +; GISEL-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-NEXT: s_setpc_b64 s[30:31] + %ptr = getelementptr inbounds i32, ptr addrspace(5) %stack, i32 -1 + %cond = icmp eq i32 %flag, 0 + br i1 %cond, label %bb1, label %bb2 + +bb1: + store i32 1, ptr addrspace(5) %ptr, align 4 + ret i32 0 + +bb2: + %value = load i32, ptr addrspace(5) %ptr, align 4 + ret i32 %value +} diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll index d9af38782fe8..0d5e8d61e16b 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll @@ -91,14 +91,14 @@ for.body: %i.056 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ] %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.056 %0 = load i16, ptr %arrayidx, align 2 - %add1 = or i32 %i.056, 1 + %add1 = or disjoint i32 %i.056, 1 %arrayidx2 = getelementptr inbounds i16, ptr %arg3, i32 %add1 %1 = load i16, ptr %arrayidx2, align 2 - %add3 = or i32 %i.056, 2 + %add3 = or disjoint i32 %i.056, 2 %arrayidx4 = getelementptr inbounds i16, ptr %arg3, i32 %add3 %2 = load i16, ptr %arrayidx4, align 2 - %add5 = or i32 %i.056, 3 + %add5 = or disjoint i32 %i.056, 3 %arrayidx6 = getelementptr inbounds i16, ptr %arg3, i32 %add5 %3 = load i16, ptr %arrayidx6, align 2 %arrayidx8 = getelementptr inbounds i16, ptr %arg2, i32 %i.056 diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll index 061603db79be..bb3b2917e8d3 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll @@ -33,13 +33,13 @@ for.body: %i.053 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ] %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.053 %0 = load i16, ptr %arrayidx, align 2 - %add1 = or i32 %i.053, 1 + %add1 = or disjoint i32 %i.053, 1 %arrayidx2 = getelementptr inbounds i16, ptr %arg3, i32 %add1 %1 = load i16, ptr %arrayidx2, align 2 - %add3 = or i32 %i.053, 2 + %add3 = or disjoint i32 %i.053, 2 %arrayidx4 = getelementptr inbounds i16, ptr %arg3, i32 %add3 %2 = load i16, ptr %arrayidx4, align 2 - %add5 = or i32 %i.053, 3 + %add5 = or disjoint i32 %i.053, 3 %arrayidx6 = getelementptr inbounds i16, ptr %arg3, i32 %add5 %3 = load i16, ptr %arrayidx6, align 2 %arrayidx8 = getelementptr inbounds i16, ptr %arg2, i32 %i.053 diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll index c7705468dc91..9001671ba7f1 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll @@ -69,17 +69,17 @@ for.body: %In2 = load i16, ptr %pIn2Base, align 2 %pIn1.0 = getelementptr inbounds i16, ptr %pIn1, i32 %i.011 %In1 = load i16, ptr %pIn1.0, align 2 - %inc = or i32 %i.011, 1 + %inc = or disjoint i32 %i.011, 1 %pIn2.1 = getelementptr inbounds i16, ptr %pIn2Base, i32 -1 %In2.1 = load i16, ptr %pIn2.1, align 2 %pIn1.1 = getelementptr inbounds i16, ptr %pIn1, i32 %inc %In1.1 = load i16, ptr %pIn1.1, align 2 - %inc.1 = or i32 %i.011, 2 + %inc.1 = or disjoint i32 %i.011, 2 %pIn2.2 = getelementptr inbounds i16, ptr %pIn2Base, i32 -2 %In2.2 = load i16, ptr %pIn2.2, align 2 %pIn1.2 = getelementptr inbounds i16, ptr %pIn1, i32 %inc.1 %In1.2 = load i16, ptr %pIn1.2, align 2 - %inc.2 = or i32 %i.011, 3 + %inc.2 = or disjoint i32 %i.011, 3 %pIn2.3 = getelementptr inbounds i16, ptr %pIn2Base, i32 -3 %In2.3 = load i16, ptr %pIn2.3, align 2 %pIn1.3 = getelementptr inbounds i16, ptr %pIn1, i32 %inc.2 diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll index 843776f4edd4..d4f64297c848 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll @@ -91,14 +91,14 @@ for.body: %i.056 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ] %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.056 %0 = load i16, ptr %arrayidx, align 2 - %add1 = or i32 %i.056, 1 + %add1 = or disjoint i32 %i.056, 1 %arrayidx2 = getelementptr inbounds i16, ptr %arg3, i32 %add1 %1 = load i16, ptr %arrayidx2, align 2 - %add3 = or i32 %i.056, 2 + %add3 = or disjoint i32 %i.056, 2 %arrayidx4 = getelementptr inbounds i16, ptr %arg3, i32 %add3 %2 = load i16, ptr %arrayidx4, align 2 - %add5 = or i32 %i.056, 3 + %add5 = or disjoint i32 %i.056, 3 %arrayidx6 = getelementptr inbounds i16, ptr %arg3, i32 %add5 %3 = load i16, ptr %arrayidx6, align 2 %arrayidx8 = getelementptr inbounds i16, ptr %arg2, i32 %i.056 diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll index 9d721ac22c84..df2393466735 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll @@ -92,14 +92,14 @@ for.body: %i.056 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ] %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.056 %0 = load i16, ptr %arrayidx, align 2 - %add1 = or i32 %i.056, 1 + %add1 = or disjoint i32 %i.056, 1 %arrayidx2 = getelementptr inbounds i16, ptr %arg3, i32 %add1 %1 = load i16, ptr %arrayidx2, align 2 - %add3 = or i32 %i.056, 2 + %add3 = or disjoint i32 %i.056, 2 %arrayidx4 = getelementptr inbounds i16, ptr %arg3, i32 %add3 %2 = load i16, ptr %arrayidx4, align 2 - %add5 = or i32 %i.056, 3 + %add5 = or disjoint i32 %i.056, 3 %arrayidx6 = getelementptr inbounds i16, ptr %arg3, i32 %add5 %3 = load i16, ptr %arrayidx6, align 2 %arrayidx8 = getelementptr inbounds i16, ptr %arg2, i32 %i.056 diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll index d6a18bceab59..88d6abdd8348 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll @@ -68,17 +68,17 @@ for.body: %In2 = load i16, ptr %pIn2Base, align 2 %pIn1.0 = getelementptr inbounds i16, ptr %pIn1, i32 %i.011 %In1 = load i16, ptr %pIn1.0, align 2 - %inc = or i32 %i.011, 1 + %inc = or disjoint i32 %i.011, 1 %pIn2.1 = getelementptr inbounds i16, ptr %pIn2Base, i32 -1 %In2.1 = load i16, ptr %pIn2.1, align 2 %pIn1.1 = getelementptr inbounds i16, ptr %pIn1, i32 %inc %In1.1 = load i16, ptr %pIn1.1, align 2 - %inc.1 = or i32 %i.011, 2 + %inc.1 = or disjoint i32 %i.011, 2 %pIn2.2 = getelementptr inbounds i16, ptr %pIn2Base, i32 -2 %In2.2 = load i16, ptr %pIn2.2, align 2 %pIn1.2 = getelementptr inbounds i16, ptr %pIn1, i32 %inc.1 %In1.2 = load i16, ptr %pIn1.2, align 2 - %inc.2 = or i32 %i.011, 3 + %inc.2 = or disjoint i32 %i.011, 3 %pIn2.3 = getelementptr inbounds i16, ptr %pIn2Base, i32 -3 %In2.3 = load i16, ptr %pIn2.3, align 2 %pIn1.3 = getelementptr inbounds i16, ptr %pIn1, i32 %inc.2 diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll b/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll index e47cf75bc8d0..75c202629f01 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll @@ -68,17 +68,17 @@ for.body: %In2 = load i16, ptr %pIn2Base, align 2 %pIn1.0 = getelementptr inbounds i16, ptr %pIn1, i32 %i.011 %In1 = load i16, ptr %pIn1.0, align 2 - %inc = or i32 %i.011, 1 + %inc = or disjoint i32 %i.011, 1 %pIn2.1 = getelementptr inbounds i16, ptr %pIn2Base, i32 -1 %In2.1 = load i16, ptr %pIn2.1, align 2 %pIn1.1 = getelementptr inbounds i16, ptr %pIn1, i32 %inc %In1.1 = load i16, ptr %pIn1.1, align 2 - %inc.1 = or i32 %i.011, 2 + %inc.1 = or disjoint i32 %i.011, 2 %pIn2.2 = getelementptr inbounds i16, ptr %pIn2Base, i32 -2 %In2.2 = load i16, ptr %pIn2.2, align 2 %pIn1.2 = getelementptr inbounds i16, ptr %pIn1, i32 %inc.1 %In1.2 = load i16, ptr %pIn1.2, align 2 - %inc.2 = or i32 %i.011, 3 + %inc.2 = or disjoint i32 %i.011, 3 %pIn2.3 = getelementptr inbounds i16, ptr %pIn2Base, i32 -3 %In2.3 = load i16, ptr %pIn2.3, align 2 %pIn1.3 = getelementptr inbounds i16, ptr %pIn1, i32 %inc.2 diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll index 3890edeaa353..51d113376a37 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll @@ -16,15 +16,15 @@ entry: %arrayidx.us.i117.i = getelementptr inbounds i32, ptr %res, i32 %idx store i32 0, ptr %arrayidx.us.i117.i, align 4 %mul.us.i118.i = mul i32 %idx, %N - %inc11.us.i.i = or i32 %idx, 1 + %inc11.us.i.i = or disjoint i32 %idx, 1 %arrayidx.us.i117.1.i = getelementptr inbounds i32, ptr %res, i32 %inc11.us.i.i store i32 0, ptr %arrayidx.us.i117.1.i, align 4 %mul.us.i118.1.i = mul i32 %inc11.us.i.i, %N - %inc11.us.i.1.i = or i32 %idx, 2 + %inc11.us.i.1.i = or disjoint i32 %idx, 2 %arrayidx.us.i117.2.i = getelementptr inbounds i32, ptr %res, i32 %inc11.us.i.1.i store i32 0, ptr %arrayidx.us.i117.2.i, align 4 %mul.us.i118.2.i = mul i32 %inc11.us.i.1.i, %N - %inc11.us.i.2.i = or i32 %idx, 3 + %inc11.us.i.2.i = or disjoint i32 %idx, 3 %arrayidx.us.i117.3.i = getelementptr inbounds i32, ptr %res, i32 %inc11.us.i.2.i store i32 0, ptr %arrayidx.us.i117.3.i, align 4 %mul.us.i118.3.i = mul i32 %inc11.us.i.2.i, %N @@ -63,7 +63,7 @@ for.body: %conv6.us.i.i = sext i16 %A8 to i32 %mul7.us.i.i = mul nsw i32 %conv6.us.i.i, %conv.us.i.i %add9.us.i.i = add nsw i32 %mul7.us.i.i, %A3 - %inc.us.i.i = or i32 %j.026.us.i.i, 1 + %inc.us.i.i = or disjoint i32 %j.026.us.i.i, 1 %add.us.i.1.i = add i32 %j.026.us.i.i, %mul.us.i118.1.i %arrayidx4.us.i.1.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.1.i %A9 = load i16, ptr %arrayidx4.us.i.1.i, align 2 @@ -73,7 +73,7 @@ for.body: %conv6.us.i.1.i = sext i16 %B0 to i32 %mul7.us.i.1.i = mul nsw i32 %conv6.us.i.1.i, %conv.us.i.1.i %add9.us.i.1.i = add nsw i32 %mul7.us.i.1.i, %A4 - %inc.us.i.1.i = or i32 %j.026.us.i.i, 1 + %inc.us.i.1.i = or disjoint i32 %j.026.us.i.i, 1 %add.us.i.2.i = add i32 %j.026.us.i.i, %mul.us.i118.2.i %arrayidx4.us.i.2.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.2.i %B1 = load i16, ptr %arrayidx4.us.i.2.i, align 2 @@ -83,7 +83,7 @@ for.body: %conv6.us.i.2.i = sext i16 %B2 to i32 %mul7.us.i.2.i = mul nsw i32 %conv6.us.i.2.i, %conv.us.i.2.i %add9.us.i.2.i = add nsw i32 %mul7.us.i.2.i, %A5 - %inc.us.i.2.i = or i32 %j.026.us.i.i, 1 + %inc.us.i.2.i = or disjoint i32 %j.026.us.i.i, 1 %add.us.i.3.i = add i32 %j.026.us.i.i, %mul.us.i118.3.i %arrayidx4.us.i.3.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.3.i %B3 = load i16, ptr %arrayidx4.us.i.3.i, align 2 @@ -93,7 +93,7 @@ for.body: %conv6.us.i.3.i = sext i16 %B4 to i32 %mul7.us.i.3.i = mul nsw i32 %conv6.us.i.3.i, %conv.us.i.3.i %add9.us.i.3.i = add nsw i32 %mul7.us.i.3.i, %A6 - %inc.us.i.3.i = or i32 %j.026.us.i.i, 1 + %inc.us.i.3.i = or disjoint i32 %j.026.us.i.i, 1 %add.us.i.1337.i = add i32 %inc.us.i.i, %mul.us.i118.i %arrayidx4.us.i.1338.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.1337.i %B5 = load i16, ptr %arrayidx4.us.i.1338.i, align 2 @@ -103,7 +103,7 @@ for.body: %conv6.us.i.1341.i = sext i16 %B6 to i32 %mul7.us.i.1342.i = mul nsw i32 %conv6.us.i.1341.i, %conv.us.i.1339.i %add9.us.i.1343.i = add nsw i32 %mul7.us.i.1342.i, %add9.us.i.i - %inc.us.i.1344.i = or i32 %j.026.us.i.i, 2 + %inc.us.i.1344.i = or disjoint i32 %j.026.us.i.i, 2 %add.us.i.1.1.i = add i32 %inc.us.i.1.i, %mul.us.i118.1.i %arrayidx4.us.i.1.1.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.1.1.i %B7 = load i16, ptr %arrayidx4.us.i.1.1.i, align 2 @@ -113,7 +113,7 @@ for.body: %conv6.us.i.1.1.i = sext i16 %B6.dup to i32 %mul7.us.i.1.1.i = mul nsw i32 %conv6.us.i.1.1.i, %conv.us.i.1.1.i %add9.us.i.1.1.i = add nsw i32 %mul7.us.i.1.1.i, %add9.us.i.1.i - %inc.us.i.1.1.i = or i32 %j.026.us.i.i, 2 + %inc.us.i.1.1.i = or disjoint i32 %j.026.us.i.i, 2 %add.us.i.2.1.i = add i32 %inc.us.i.2.i, %mul.us.i118.2.i %arrayidx4.us.i.2.1.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.2.1.i %B9 = load i16, ptr %arrayidx4.us.i.2.1.i, align 2 @@ -123,7 +123,7 @@ for.body: %conv6.us.i.2.1.i = sext i16 %B6.dup.i to i32 %mul7.us.i.2.1.i = mul nsw i32 %conv6.us.i.2.1.i, %conv.us.i.2.1.i %add9.us.i.2.1.i = add nsw i32 %mul7.us.i.2.1.i, %add9.us.i.2.i - %inc.us.i.2.1.i = or i32 %j.026.us.i.i, 2 + %inc.us.i.2.1.i = or disjoint i32 %j.026.us.i.i, 2 %add.us.i.3.1.i = add i32 %inc.us.i.3.i, %mul.us.i118.3.i %arrayidx4.us.i.3.1.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.3.1.i %B11 = load i16, ptr %arrayidx4.us.i.3.1.i, align 2 @@ -133,7 +133,7 @@ for.body: %conv6.us.i.3.1.i = sext i16 %B6.dup.i.i to i32 %mul7.us.i.3.1.i = mul nsw i32 %conv6.us.i.3.1.i, %conv.us.i.3.1.i %add9.us.i.3.1.i = add nsw i32 %mul7.us.i.3.1.i, %add9.us.i.3.i - %inc.us.i.3.1.i = or i32 %j.026.us.i.i, 2 + %inc.us.i.3.1.i = or disjoint i32 %j.026.us.i.i, 2 %add.us.i.2346.i = add i32 %inc.us.i.1344.i, %mul.us.i118.i %arrayidx4.us.i.2347.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.2346.i %B13 = load i16, ptr %arrayidx4.us.i.2347.i, align 2 @@ -143,7 +143,7 @@ for.body: %conv6.us.i.2350.i = sext i16 %B14 to i32 %mul7.us.i.2351.i = mul nsw i32 %conv6.us.i.2350.i, %conv.us.i.2348.i %add9.us.i.2352.i = add nsw i32 %mul7.us.i.2351.i, %add9.us.i.1343.i - %inc.us.i.2353.i = or i32 %j.026.us.i.i, 3 + %inc.us.i.2353.i = or disjoint i32 %j.026.us.i.i, 3 %add.us.i.1.2.i = add i32 %inc.us.i.1.1.i, %mul.us.i118.1.i %arrayidx4.us.i.1.2.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.1.2.i %B15 = load i16, ptr %arrayidx4.us.i.1.2.i, align 2 @@ -153,7 +153,7 @@ for.body: %conv6.us.i.1.2.i = sext i16 %B14.dup to i32 %mul7.us.i.1.2.i = mul nsw i32 %conv6.us.i.1.2.i, %conv.us.i.1.2.i %add9.us.i.1.2.i = add nsw i32 %mul7.us.i.1.2.i, %add9.us.i.1.1.i - %inc.us.i.1.2.i = or i32 %j.026.us.i.i, 3 + %inc.us.i.1.2.i = or disjoint i32 %j.026.us.i.i, 3 %add.us.i.2.2.i = add i32 %inc.us.i.2.1.i, %mul.us.i118.2.i %arrayidx4.us.i.2.2.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.2.2.i %B17 = load i16, ptr %arrayidx4.us.i.2.2.i, align 2 @@ -163,7 +163,7 @@ for.body: %conv6.us.i.2.2.i = sext i16 %B14.dup.i to i32 %mul7.us.i.2.2.i = mul nsw i32 %conv6.us.i.2.2.i, %conv.us.i.2.2.i %add9.us.i.2.2.i = add nsw i32 %mul7.us.i.2.2.i, %add9.us.i.2.1.i - %inc.us.i.2.2.i = or i32 %j.026.us.i.i, 3 + %inc.us.i.2.2.i = or disjoint i32 %j.026.us.i.i, 3 %add.us.i.3.2.i = add i32 %inc.us.i.3.1.i, %mul.us.i118.3.i %arrayidx4.us.i.3.2.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.3.2.i %B19 = load i16, ptr %arrayidx4.us.i.3.2.i, align 2 @@ -173,7 +173,7 @@ for.body: %conv6.us.i.3.2.i = sext i16 %B14.dup.i.i to i32 %mul7.us.i.3.2.i = mul nsw i32 %conv6.us.i.3.2.i, %conv.us.i.3.2.i %add9.us.i.3.2.i = add nsw i32 %mul7.us.i.3.2.i, %add9.us.i.3.1.i - %inc.us.i.3.2.i = or i32 %j.026.us.i.i, 3 + %inc.us.i.3.2.i = or disjoint i32 %j.026.us.i.i, 3 %add.us.i.3355.i = add i32 %inc.us.i.2353.i, %mul.us.i118.i %arrayidx4.us.i.3356.i = getelementptr inbounds i16, ptr %A, i32 %add.us.i.3355.i %B21 = load i16, ptr %arrayidx4.us.i.3356.i, align 2 diff --git a/llvm/test/CodeGen/ARM/aapcs-hfa-code.ll b/llvm/test/CodeGen/ARM/aapcs-hfa-code.ll index 8d31485175af..e32f19ef6745 100644 --- a/llvm/test/CodeGen/ARM/aapcs-hfa-code.ll +++ b/llvm/test/CodeGen/ARM/aapcs-hfa-code.ll @@ -1,65 +1,96 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc < %s -mtriple=armv7-linux-gnueabihf -o - | FileCheck %s ; RUN: llc < %s -mtriple=thumbv7em-none-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK-M4F target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64" define arm_aapcs_vfpcc void @test_1float({ float } %a) { - call arm_aapcs_vfpcc void @test_1float({ float } { float 1.0 }) - ret void - ; CHECK-LABEL: test_1float: -; CHECK-DAG: vmov.f32 s0, #1.{{0+}}e+00 -; CHECK: bl test_1float - +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: vmov.f32 s0, #1.000000e+00 +; CHECK-NEXT: bl test_1float +; CHECK-NEXT: pop {r11, pc} +; ; CHECK-M4F-LABEL: test_1float: -; CHECK-M4F-DAG: vmov.f32 s0, #1.{{0+}}e+00 -; CHECK-M4F: bl test_1float +; CHECK-M4F: @ %bb.0: +; CHECK-M4F-NEXT: .save {r7, lr} +; CHECK-M4F-NEXT: push {r7, lr} +; CHECK-M4F-NEXT: vmov.f32 s0, #1.000000e+00 +; CHECK-M4F-NEXT: bl test_1float +; CHECK-M4F-NEXT: pop {r7, pc} + call arm_aapcs_vfpcc void @test_1float({ float } { float 1.0 }) + ret void } define arm_aapcs_vfpcc void @test_2float({ float, float } %a) { - call arm_aapcs_vfpcc void @test_2float({ float, float } { float 1.0, float 2.0 }) - ret void - ; CHECK-LABEL: test_2float: -; CHECK-DAG: vmov.f32 s0, #1.{{0+}}e+00 -; CHECK-DAG: vmov.f32 s1, #2.{{0+}}e+00 -; CHECK: bl test_2float - +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: vmov.f32 s0, #1.000000e+00 +; CHECK-NEXT: vmov.f32 s1, #2.000000e+00 +; CHECK-NEXT: bl test_2float +; CHECK-NEXT: pop {r11, pc} +; ; CHECK-M4F-LABEL: test_2float: -; CHECK-M4F-DAG: vmov.f32 s0, #1.{{0+}}e+00 -; CHECK-M4F-DAG: vmov.f32 s1, #2.{{0+}}e+00 -; CHECK-M4F: bl test_2float +; CHECK-M4F: @ %bb.0: +; CHECK-M4F-NEXT: .save {r7, lr} +; CHECK-M4F-NEXT: push {r7, lr} +; CHECK-M4F-NEXT: vmov.f32 s0, #1.000000e+00 +; CHECK-M4F-NEXT: vmov.f32 s1, #2.000000e+00 +; CHECK-M4F-NEXT: bl test_2float +; CHECK-M4F-NEXT: pop {r7, pc} + call arm_aapcs_vfpcc void @test_2float({ float, float } { float 1.0, float 2.0 }) + ret void } define arm_aapcs_vfpcc void @test_3float({ float, float, float } %a) { - call arm_aapcs_vfpcc void @test_3float({ float, float, float } { float 1.0, float 2.0, float 3.0 }) - ret void - ; CHECK-LABEL: test_3float: -; CHECK-DAG: vmov.f32 s0, #1.{{0+}}e+00 -; CHECK-DAG: vmov.f32 s1, #2.{{0+}}e+00 -; CHECK-DAG: vmov.f32 s2, #3.{{0+}}e+00 -; CHECK: bl test_3float - +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: vmov.f32 s0, #1.000000e+00 +; CHECK-NEXT: vmov.f32 s1, #2.000000e+00 +; CHECK-NEXT: vmov.f32 s2, #3.000000e+00 +; CHECK-NEXT: bl test_3float +; CHECK-NEXT: pop {r11, pc} +; ; CHECK-M4F-LABEL: test_3float: -; CHECK-M4F-DAG: vmov.f32 s0, #1.{{0+}}e+00 -; CHECK-M4F-DAG: vmov.f32 s1, #2.{{0+}}e+00 -; CHECK-M4F-DAG: vmov.f32 s2, #3.{{0+}}e+00 -; CHECK-M4F: bl test_3float +; CHECK-M4F: @ %bb.0: +; CHECK-M4F-NEXT: .save {r7, lr} +; CHECK-M4F-NEXT: push {r7, lr} +; CHECK-M4F-NEXT: vmov.f32 s0, #1.000000e+00 +; CHECK-M4F-NEXT: vmov.f32 s1, #2.000000e+00 +; CHECK-M4F-NEXT: vmov.f32 s2, #3.000000e+00 +; CHECK-M4F-NEXT: bl test_3float +; CHECK-M4F-NEXT: pop {r7, pc} + call arm_aapcs_vfpcc void @test_3float({ float, float, float } { float 1.0, float 2.0, float 3.0 }) + ret void } define arm_aapcs_vfpcc void @test_1double({ double } %a) { ; CHECK-LABEL: test_1double: -; CHECK-DAG: vmov.f64 d0, #1.{{0+}}e+00 -; CHECK: bl test_1double - +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: vmov.f64 d0, #1.000000e+00 +; CHECK-NEXT: bl test_1double +; CHECK-NEXT: pop {r11, pc} +; ; CHECK-M4F-LABEL: test_1double: -; CHECK-M4F: vldr d0, [[CP_LABEL:.*]] -; CHECK-M4F: bl test_1double -; CHECK-M4F: [[CP_LABEL]] -; CHECK-M4F-NEXT: .long 0 -; CHECK-M4F-NEXT: .long 1072693248 - +; CHECK-M4F: @ %bb.0: +; CHECK-M4F-NEXT: .save {r7, lr} +; CHECK-M4F-NEXT: push {r7, lr} +; CHECK-M4F-NEXT: vldr d0, .LCPI3_0 +; CHECK-M4F-NEXT: bl test_1double +; CHECK-M4F-NEXT: pop {r7, pc} +; CHECK-M4F-NEXT: .p2align 3 +; CHECK-M4F-NEXT: @ %bb.1: +; CHECK-M4F-NEXT: .LCPI3_0: +; CHECK-M4F-NEXT: .long 0 @ double 1 +; CHECK-M4F-NEXT: .long 1072693248 call arm_aapcs_vfpcc void @test_1double({ double } { double 1.0 }) ret void } @@ -68,18 +99,32 @@ define arm_aapcs_vfpcc void @test_1double({ double } %a) { ; go all on the stack. define arm_aapcs_vfpcc void @test_1double_nosplit([4 x float], [4 x double], [3 x float], double %a) { ; CHECK-LABEL: test_1double_nosplit: -; CHECK-DAG: mov [[ONELO:r[0-9]+]], #0 -; CHECK-DAG: movw [[ONEHI:r[0-9]+]], #0 -; CHECK-DAG: movt [[ONEHI]], #16368 -; CHECK: strd [[ONELO]], [[ONEHI]], [sp] -; CHECK: bl test_1double_nosplit - +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: .pad #8 +; CHECK-NEXT: sub sp, sp, #8 +; CHECK-NEXT: movw r1, #0 +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: movt r1, #16368 +; CHECK-NEXT: strd r0, r1, [sp] +; CHECK-NEXT: bl test_1double_nosplit +; CHECK-NEXT: add sp, sp, #8 +; CHECK-NEXT: pop {r11, pc} +; ; CHECK-M4F-LABEL: test_1double_nosplit: -; CHECK-M4F: movs [[ONEHI:r[0-9]+]], #0 -; CHECK-M4F: movt [[ONEHI]], #16368 -; CHECK-M4F: movs [[ONELO:r[0-9]+]], #0 -; CHECK-M4F: strd [[ONELO]], [[ONEHI]], [sp] -; CHECK-M4F: bl test_1double_nosplit +; CHECK-M4F: @ %bb.0: +; CHECK-M4F-NEXT: .save {r7, lr} +; CHECK-M4F-NEXT: push {r7, lr} +; CHECK-M4F-NEXT: .pad #8 +; CHECK-M4F-NEXT: sub sp, #8 +; CHECK-M4F-NEXT: movs r0, #0 +; CHECK-M4F-NEXT: movt r0, #16368 +; CHECK-M4F-NEXT: movs r1, #0 +; CHECK-M4F-NEXT: strd r1, r0, [sp] +; CHECK-M4F-NEXT: bl test_1double_nosplit +; CHECK-M4F-NEXT: add sp, #8 +; CHECK-M4F-NEXT: pop {r7, pc} call arm_aapcs_vfpcc void @test_1double_nosplit([4 x float] undef, [4 x double] undef, [3 x float] undef, double 1.0) ret void } @@ -87,20 +132,34 @@ define arm_aapcs_vfpcc void @test_1double_nosplit([4 x float], [4 x double], [3 ; Final double argument might go at [sp, #4] if we're careless. Should go at ; [sp, #8] to preserve alignment. define arm_aapcs_vfpcc void @test_1double_misaligned([4 x double], [4 x double], float, double) { - call arm_aapcs_vfpcc void @test_1double_misaligned([4 x double] undef, [4 x double] undef, float undef, double 1.0) - ; CHECK-LABEL: test_1double_misaligned: -; CHECK-DAG: movw [[ONEHI:r[0-9]+]], #0 -; CHECK-DAG: mov [[ONELO:r[0-9]+]], #0 -; CHECK-DAG: movt [[ONEHI]], #16368 -; CHECK-DAG: strd [[ONELO]], [[ONEHI]], [sp, #8] - +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: .pad #16 +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: movw r1, #0 +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: movt r1, #16368 +; CHECK-NEXT: strd r0, r1, [sp, #8] +; CHECK-NEXT: bl test_1double_misaligned +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: pop {r11, pc} +; ; CHECK-M4F-LABEL: test_1double_misaligned: -; CHECK-M4F: movs [[ONEHI:r[0-9]+]], #0 -; CHECK-M4F: movt [[ONEHI]], #16368 -; CHECK-M4F: movs [[ONELO:r[0-9]+]], #0 -; CHECK-M4F: strd [[ONELO]], [[ONEHI]], [sp, #8] -; CHECK-M4F: bl test_1double_misaligned +; CHECK-M4F: @ %bb.0: +; CHECK-M4F-NEXT: .save {r7, lr} +; CHECK-M4F-NEXT: push {r7, lr} +; CHECK-M4F-NEXT: .pad #16 +; CHECK-M4F-NEXT: sub sp, #16 +; CHECK-M4F-NEXT: movs r0, #0 +; CHECK-M4F-NEXT: movt r0, #16368 +; CHECK-M4F-NEXT: movs r1, #0 +; CHECK-M4F-NEXT: strd r1, r0, [sp, #8] +; CHECK-M4F-NEXT: bl test_1double_misaligned +; CHECK-M4F-NEXT: add sp, #16 +; CHECK-M4F-NEXT: pop {r7, pc} + call arm_aapcs_vfpcc void @test_1double_misaligned([4 x double] undef, [4 x double] undef, float undef, double 1.0) ret void } diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll index c940158437fe..9fb64471e988 100644 --- a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll +++ b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll @@ -49,7 +49,7 @@ loop: %qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1) %addr.1 = getelementptr inbounds i32, ptr %out.array, i32 %idx.1 store i32 %qadd.1, ptr %addr.1 - %idx.2 = or i32 %idx.1, 1 + %idx.2 = or disjoint i32 %idx.1, 1 %gep.a.2 = getelementptr inbounds i32, ptr %a.array, i32 %idx.2 %a.2 = load i32, ptr %gep.a.2 %gep.b.2 = getelementptr inbounds i32, ptr %b.array, i32 %idx.2 @@ -228,7 +228,7 @@ loop: %qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1) %addr.1 = getelementptr inbounds i32, ptr %out.array, i32 %idx.1 store i32 %qadd.1, ptr %addr.1 - %idx.2 = or i32 %idx.1, 1 + %idx.2 = or disjoint i32 %idx.1, 1 %gep.a.2 = getelementptr inbounds i32, ptr %a.array, i32 %idx.2 %a.2 = load i32, ptr %gep.a.2 %gep.b.2 = getelementptr inbounds i32, ptr %b.array, i32 %idx.2 @@ -236,7 +236,7 @@ loop: %qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2) %addr.2 = getelementptr inbounds i32, ptr %out.array, i32 %idx.2 store i32 %qadd.2, ptr %addr.2 - %idx.3 = or i32 %idx.1, 2 + %idx.3 = or disjoint i32 %idx.1, 2 %gep.a.3 = getelementptr inbounds i32, ptr %a.array, i32 %idx.3 %a.3 = load i32, ptr %gep.a.3 %gep.b.3 = getelementptr inbounds i32, ptr %b.array, i32 %idx.3 @@ -244,7 +244,7 @@ loop: %qadd.3 = call i32 @llvm.arm.qadd(i32 %a.3, i32 %b.3) %addr.3 = getelementptr inbounds i32, ptr %out.array, i32 %idx.3 store i32 %qadd.3, ptr %addr.3 - %idx.4 = or i32 %idx.1, 3 + %idx.4 = or disjoint i32 %idx.1, 3 %gep.a.4 = getelementptr inbounds i32, ptr %a.array, i32 %idx.4 %a.4 = load i32, ptr %gep.a.4 %gep.b.4 = getelementptr inbounds i32, ptr %b.array, i32 %idx.4 diff --git a/llvm/test/CodeGen/ARM/fpclamptosat.ll b/llvm/test/CodeGen/ARM/fpclamptosat.ll index 6c3c74a47ebf..8bd8aa7b34de 100644 --- a/llvm/test/CodeGen/ARM/fpclamptosat.ll +++ b/llvm/test/CodeGen/ARM/fpclamptosat.ll @@ -4158,7 +4158,7 @@ define void @unroll_maxmin(ptr nocapture %0, ptr nocapture readonly %1, i32 %2) %15 = trunc i64 %14 to i32 %16 = getelementptr inbounds i32, ptr %0, i32 %6 store i32 %15, ptr %16, align 4 - %17 = or i32 %6, 1 + %17 = or disjoint i32 %6, 1 %18 = getelementptr inbounds float, ptr %1, i32 %17 %19 = load float, ptr %18, align 4 %20 = fmul float %19, 0x41E0000000000000 @@ -4354,7 +4354,7 @@ define void @unroll_minmax(ptr nocapture %0, ptr nocapture readonly %1, i32 %2) %15 = trunc i64 %14 to i32 %16 = getelementptr inbounds i32, ptr %0, i32 %6 store i32 %15, ptr %16, align 4 - %17 = or i32 %6, 1 + %17 = or disjoint i32 %6, 1 %18 = getelementptr inbounds float, ptr %1, i32 %17 %19 = load float, ptr %18, align 4 %20 = fmul float %19, 0x41E0000000000000 diff --git a/llvm/test/CodeGen/ARM/loop-indexing.ll b/llvm/test/CodeGen/ARM/loop-indexing.ll index 110342c7f3ba..bb859b202bbc 100644 --- a/llvm/test/CodeGen/ARM/loop-indexing.ll +++ b/llvm/test/CodeGen/ARM/loop-indexing.ll @@ -51,7 +51,7 @@ loop: %b.1 = load float, ptr %gep.b.1 %fmul.1 = fmul float %a.1, %b.1 %fma.1 = fadd float %fmul.1, %res - %idx.2 = or i32 %idx.1, 1 + %idx.2 = or disjoint i32 %idx.1, 1 %gep.a.2 = getelementptr inbounds float, ptr %a, i32 %idx.2 %a.2 = load float, ptr %gep.a.2 %gep.b.2 = getelementptr inbounds float, ptr %b, i32 %idx.2 @@ -123,7 +123,7 @@ for.body12.us.us: ; preds = %for.body12.us.us, % %conv17.us.us = sext i16 %tmp10 to i32 %mul.us.us = mul nsw i32 %conv17.us.us, %conv.us.us %add18.us.us = add nsw i32 %mul.us.us, %result_element.152.us.us - %inc.us.us = or i32 %filter_x.053.us.us, 1 + %inc.us.us = or disjoint i32 %filter_x.053.us.us, 1 %add13.us.us.1 = add i32 %inc.us.us, %res_x.060.us %arrayidx14.us.us.1 = getelementptr inbounds i16, ptr %tmp5, i32 %inc.us.us %tmp11 = load i16, ptr %arrayidx14.us.us.1, align 2 @@ -133,7 +133,7 @@ for.body12.us.us: ; preds = %for.body12.us.us, % %conv17.us.us.1 = sext i16 %tmp12 to i32 %mul.us.us.1 = mul nsw i32 %conv17.us.us.1, %conv.us.us.1 %add18.us.us.1 = add nsw i32 %mul.us.us.1, %add18.us.us - %inc.us.us.1 = or i32 %filter_x.053.us.us, 2 + %inc.us.us.1 = or disjoint i32 %filter_x.053.us.us, 2 %add13.us.us.2 = add i32 %inc.us.us.1, %res_x.060.us %arrayidx14.us.us.2 = getelementptr inbounds i16, ptr %tmp5, i32 %inc.us.us.1 %tmp13 = load i16, ptr %arrayidx14.us.us.2, align 2 @@ -143,7 +143,7 @@ for.body12.us.us: ; preds = %for.body12.us.us, % %conv17.us.us.2 = sext i16 %tmp14 to i32 %mul.us.us.2 = mul nsw i32 %conv17.us.us.2, %conv.us.us.2 %add18.us.us.2 = add nsw i32 %mul.us.us.2, %add18.us.us.1 - %inc.us.us.2 = or i32 %filter_x.053.us.us, 3 + %inc.us.us.2 = or disjoint i32 %filter_x.053.us.us, 3 %add13.us.us.3 = add i32 %inc.us.us.2, %res_x.060.us %arrayidx14.us.us.3 = getelementptr inbounds i16, ptr %tmp5, i32 %inc.us.us.2 %tmp15 = load i16, ptr %arrayidx14.us.us.3, align 2 @@ -250,7 +250,7 @@ for.body: ; preds = %for.body, %for.body %mul = mul nuw nsw i32 %conv2, %conv %arrayidx3 = getelementptr inbounds i32, ptr %C, i32 %i.010 store i32 %mul, ptr %arrayidx3, align 4 - %inc = or i32 %i.010, 1 + %inc = or disjoint i32 %i.010, 1 %arrayidx.1 = getelementptr inbounds i8, ptr %A, i32 %inc %tmp6 = load i8, ptr %arrayidx.1, align 1 %conv.1 = zext i8 %tmp6 to i32 @@ -260,7 +260,7 @@ for.body: ; preds = %for.body, %for.body %mul.1 = mul nuw nsw i32 %conv2.1, %conv.1 %arrayidx3.1 = getelementptr inbounds i32, ptr %C, i32 %inc store i32 %mul.1, ptr %arrayidx3.1, align 4 - %inc.1 = or i32 %i.010, 2 + %inc.1 = or disjoint i32 %i.010, 2 %arrayidx.2 = getelementptr inbounds i8, ptr %A, i32 %inc.1 %tmp8 = load i8, ptr %arrayidx.2, align 1 %conv.2 = zext i8 %tmp8 to i32 @@ -270,7 +270,7 @@ for.body: ; preds = %for.body, %for.body %mul.2 = mul nuw nsw i32 %conv2.2, %conv.2 %arrayidx3.2 = getelementptr inbounds i32, ptr %C, i32 %inc.1 store i32 %mul.2, ptr %arrayidx3.2, align 4 - %inc.2 = or i32 %i.010, 3 + %inc.2 = or disjoint i32 %i.010, 3 %arrayidx.3 = getelementptr inbounds i8, ptr %A, i32 %inc.2 %tmp10 = load i8, ptr %arrayidx.3, align 1 %conv.3 = zext i8 %tmp10 to i32 @@ -356,7 +356,7 @@ for.body: ; preds = %for.body, %for.body %mul = mul nsw i32 %conv2, %conv %arrayidx3 = getelementptr inbounds i32, ptr %C, i32 %i.010 store i32 %mul, ptr %arrayidx3, align 4 - %inc = or i32 %i.010, 1 + %inc = or disjoint i32 %i.010, 1 %arrayidx.1 = getelementptr inbounds i16, ptr %A, i32 %inc %tmp6 = load i16, ptr %arrayidx.1, align 2 %conv.1 = sext i16 %tmp6 to i32 @@ -366,7 +366,7 @@ for.body: ; preds = %for.body, %for.body %mul.1 = mul nsw i32 %conv2.1, %conv.1 %arrayidx3.1 = getelementptr inbounds i32, ptr %C, i32 %inc store i32 %mul.1, ptr %arrayidx3.1, align 4 - %inc.1 = or i32 %i.010, 2 + %inc.1 = or disjoint i32 %i.010, 2 %arrayidx.2 = getelementptr inbounds i16, ptr %A, i32 %inc.1 %tmp8 = load i16, ptr %arrayidx.2, align 2 %conv.2 = sext i16 %tmp8 to i32 @@ -376,7 +376,7 @@ for.body: ; preds = %for.body, %for.body %mul.2 = mul nsw i32 %conv2.2, %conv.2 %arrayidx3.2 = getelementptr inbounds i32, ptr %C, i32 %inc.1 store i32 %mul.2, ptr %arrayidx3.2, align 4 - %inc.2 = or i32 %i.010, 3 + %inc.2 = or disjoint i32 %i.010, 3 %arrayidx.3 = getelementptr inbounds i16, ptr %A, i32 %inc.2 %tmp10 = load i16, ptr %arrayidx.3, align 2 %conv.3 = sext i16 %tmp10 to i32 @@ -464,7 +464,7 @@ for.body: ; preds = %for.body, %for.body %mul = mul nsw i32 %conv2, %conv %arrayidx3 = getelementptr inbounds i32, ptr %C, i32 %i.010 store i32 %mul, ptr %arrayidx3, align 4 - %inc = or i32 %i.010, 1 + %inc = or disjoint i32 %i.010, 1 %arrayidx.1 = getelementptr inbounds i16, ptr %A, i32 %inc %tmp6 = load i16, ptr %arrayidx.1, align 2 %conv.1 = sext i16 %tmp6 to i32 @@ -474,7 +474,7 @@ for.body: ; preds = %for.body, %for.body %mul.1 = mul nsw i32 %conv2.1, %conv.1 %arrayidx3.1 = getelementptr inbounds i32, ptr %C, i32 %inc store i32 %mul.1, ptr %arrayidx3.1, align 4 - %inc.1 = or i32 %i.010, 2 + %inc.1 = or disjoint i32 %i.010, 2 %arrayidx.2 = getelementptr inbounds i16, ptr %A, i32 %inc.1 %tmp8 = load i16, ptr %arrayidx.2, align 2 %conv.2 = sext i16 %tmp8 to i32 @@ -484,7 +484,7 @@ for.body: ; preds = %for.body, %for.body %mul.2 = mul nsw i32 %conv2.2, %conv.2 %arrayidx3.2 = getelementptr inbounds i32, ptr %C, i32 %inc.1 store i32 %mul.2, ptr %arrayidx3.2, align 4 - %inc.2 = or i32 %i.010, 3 + %inc.2 = or disjoint i32 %i.010, 3 %arrayidx.3 = getelementptr inbounds i16, ptr %A, i32 %inc.2 %tmp10 = load i16, ptr %arrayidx.3, align 2 %conv.3 = sext i16 %tmp10 to i32 @@ -550,7 +550,7 @@ for.body4.us: ; preds = %for.body4.us, %for. %tmp4 = load i32, ptr %arrayidx9.us, align 4 %add.us = add nsw i32 %tmp4, %mul.us store i32 %add.us, ptr %arrayidx9.us, align 4 - %inc.us = or i32 %j.023.us, 1 + %inc.us = or disjoint i32 %j.023.us, 1 %tmp5 = load i8, ptr %arrayidx.us, align 1 %conv.us.1 = zext i8 %tmp5 to i32 %arrayidx6.us.1 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us @@ -561,7 +561,7 @@ for.body4.us: ; preds = %for.body4.us, %for. %tmp7 = load i32, ptr %arrayidx9.us.1, align 4 %add.us.1 = add nsw i32 %tmp7, %mul.us.1 store i32 %add.us.1, ptr %arrayidx9.us.1, align 4 - %inc.us.1 = or i32 %j.023.us, 2 + %inc.us.1 = or disjoint i32 %j.023.us, 2 %tmp8 = load i8, ptr %arrayidx.us, align 1 %conv.us.2 = zext i8 %tmp8 to i32 %arrayidx6.us.2 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us.1 @@ -572,7 +572,7 @@ for.body4.us: ; preds = %for.body4.us, %for. %tmp10 = load i32, ptr %arrayidx9.us.2, align 4 %add.us.2 = add nsw i32 %tmp10, %mul.us.2 store i32 %add.us.2, ptr %arrayidx9.us.2, align 4 - %inc.us.2 = or i32 %j.023.us, 3 + %inc.us.2 = or disjoint i32 %j.023.us, 3 %tmp11 = load i8, ptr %arrayidx.us, align 1 %conv.us.3 = zext i8 %tmp11 to i32 %arrayidx6.us.3 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us.2 @@ -669,7 +669,7 @@ for.body4.us: ; preds = %for.body4.us, %for. %tmp6 = load i32, ptr %arrayidx9.us, align 4 %add.us = add nsw i32 %tmp6, %mul.us store i32 %add.us, ptr %arrayidx9.us, align 4 - %inc.us = or i32 %j.023.us, 1 + %inc.us = or disjoint i32 %j.023.us, 1 %arrayidx6.us.1 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us %tmp7 = load i16, ptr %arrayidx6.us.1, align 2 %conv7.us.1 = sext i16 %tmp7 to i32 @@ -678,7 +678,7 @@ for.body4.us: ; preds = %for.body4.us, %for. %tmp8 = load i32, ptr %arrayidx9.us.1, align 4 %add.us.1 = add nsw i32 %tmp8, %mul.us.1 store i32 %add.us.1, ptr %arrayidx9.us.1, align 4 - %inc.us.1 = or i32 %j.023.us, 2 + %inc.us.1 = or disjoint i32 %j.023.us, 2 %arrayidx6.us.2 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us.1 %tmp9 = load i16, ptr %arrayidx6.us.2, align 2 %conv7.us.2 = sext i16 %tmp9 to i32 @@ -687,7 +687,7 @@ for.body4.us: ; preds = %for.body4.us, %for. %tmp10 = load i32, ptr %arrayidx9.us.2, align 4 %add.us.2 = add nsw i32 %tmp10, %mul.us.2 store i32 %add.us.2, ptr %arrayidx9.us.2, align 4 - %inc.us.2 = or i32 %j.023.us, 3 + %inc.us.2 = or disjoint i32 %j.023.us, 3 %arrayidx6.us.3 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us.2 %tmp11 = load i16, ptr %arrayidx6.us.3, align 2 %conv7.us.3 = sext i16 %tmp11 to i32 @@ -785,7 +785,7 @@ for.body4.us: ; preds = %for.body4.us, %for. %mul.us = mul nuw nsw i32 %conv7.us, %conv.us %add.us = add nsw i32 %mul.us, %tmp2 store i32 %add.us, ptr %arrayidx8.us, align 4 - %inc.us = or i32 %j.021.us, 1 + %inc.us = or disjoint i32 %j.021.us, 1 %tmp5 = load i8, ptr %arrayidx.us, align 1 %conv.us.1 = zext i8 %tmp5 to i32 %arrayidx6.us.1 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us @@ -794,7 +794,7 @@ for.body4.us: ; preds = %for.body4.us, %for. %mul.us.1 = mul nuw nsw i32 %conv7.us.1, %conv.us.1 %add.us.1 = add nsw i32 %mul.us.1, %add.us store i32 %add.us.1, ptr %arrayidx8.us, align 4 - %inc.us.1 = or i32 %j.021.us, 2 + %inc.us.1 = or disjoint i32 %j.021.us, 2 %tmp7 = load i8, ptr %arrayidx.us, align 1 %conv.us.2 = zext i8 %tmp7 to i32 %arrayidx6.us.2 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us.1 @@ -803,7 +803,7 @@ for.body4.us: ; preds = %for.body4.us, %for. %mul.us.2 = mul nuw nsw i32 %conv7.us.2, %conv.us.2 %add.us.2 = add nsw i32 %mul.us.2, %add.us.1 store i32 %add.us.2, ptr %arrayidx8.us, align 4 - %inc.us.2 = or i32 %j.021.us, 3 + %inc.us.2 = or disjoint i32 %j.021.us, 3 %tmp9 = load i8, ptr %arrayidx.us, align 1 %conv.us.3 = zext i8 %tmp9 to i32 %arrayidx6.us.3 = getelementptr inbounds i8, ptr %.pre, i32 %inc.us.2 @@ -898,19 +898,19 @@ for.body4.us: ; preds = %for.body4.us, %for. %conv7.us = sext i16 %tmp4 to i32 %mul.us = mul nsw i32 %conv7.us, %conv.us %add.us = add nsw i32 %mul.us, %add22.us - %inc.us = or i32 %j.021.us, 1 + %inc.us = or disjoint i32 %j.021.us, 1 %arrayidx6.us.1 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us %tmp5 = load i16, ptr %arrayidx6.us.1, align 2 %conv7.us.1 = sext i16 %tmp5 to i32 %mul.us.1 = mul nsw i32 %conv7.us.1, %conv.us %add.us.1 = add nsw i32 %mul.us.1, %add.us - %inc.us.1 = or i32 %j.021.us, 2 + %inc.us.1 = or disjoint i32 %j.021.us, 2 %arrayidx6.us.2 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us.1 %tmp6 = load i16, ptr %arrayidx6.us.2, align 2 %conv7.us.2 = sext i16 %tmp6 to i32 %mul.us.2 = mul nsw i32 %conv7.us.2, %conv.us %add.us.2 = add nsw i32 %mul.us.2, %add.us.1 - %inc.us.2 = or i32 %j.021.us, 3 + %inc.us.2 = or disjoint i32 %j.021.us, 3 %arrayidx6.us.3 = getelementptr inbounds i16, ptr %tmp3, i32 %inc.us.2 %tmp7 = load i16, ptr %arrayidx6.us.3, align 2 %conv7.us.3 = sext i16 %tmp7 to i32 @@ -1100,7 +1100,7 @@ for.body: ; preds = %for.body, %for.body %mul = mul nsw i32 %tmp5, %tmp4 %arrayidx2 = getelementptr inbounds i32, ptr %a, i32 %i.09 store i32 %mul, ptr %arrayidx2, align 4 - %inc = or i32 %i.09, 1 + %inc = or disjoint i32 %i.09, 1 %arrayidx.1 = getelementptr inbounds i32, ptr %b, i32 %inc %tmp6 = load i32, ptr %arrayidx.1, align 4 %arrayidx1.1 = getelementptr inbounds i32, ptr %c, i32 %inc @@ -1108,7 +1108,7 @@ for.body: ; preds = %for.body, %for.body %mul.1 = mul nsw i32 %tmp7, %tmp6 %arrayidx2.1 = getelementptr inbounds i32, ptr %a, i32 %inc store i32 %mul.1, ptr %arrayidx2.1, align 4 - %inc.1 = or i32 %i.09, 2 + %inc.1 = or disjoint i32 %i.09, 2 %arrayidx.2 = getelementptr inbounds i32, ptr %b, i32 %inc.1 %tmp8 = load i32, ptr %arrayidx.2, align 4 %arrayidx1.2 = getelementptr inbounds i32, ptr %c, i32 %inc.1 @@ -1116,7 +1116,7 @@ for.body: ; preds = %for.body, %for.body %mul.2 = mul nsw i32 %tmp9, %tmp8 %arrayidx2.2 = getelementptr inbounds i32, ptr %a, i32 %inc.1 store i32 %mul.2, ptr %arrayidx2.2, align 4 - %inc.2 = or i32 %i.09, 3 + %inc.2 = or disjoint i32 %i.09, 3 %arrayidx.3 = getelementptr inbounds i32, ptr %b, i32 %inc.2 %tmp10 = load i32, ptr %arrayidx.3, align 4 %arrayidx1.3 = getelementptr inbounds i32, ptr %c, i32 %inc.2 diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll index f62f195e1d73..bf2e8aa911c6 100644 --- a/llvm/test/CodeGen/ARM/shifter_operand.ll +++ b/llvm/test/CodeGen/ARM/shifter_operand.ll @@ -508,14 +508,14 @@ for.cond: ; preds = %for.cond1.for.cond. for.cond2.preheader: ; preds = %for.cond2.preheader.2, %for.cond %indvar24 = phi i32 [ 0, %for.cond ], [ %indvar.next25.3, %for.cond2.preheader.2 ] - %indvar.next25 = or i32 %indvar24, 1 + %indvar.next25 = or disjoint i32 %indvar24, 1 %l5 = mul i32 %2, %indvar.next25 %scevgep.1 = getelementptr [15 x [25 x [18 x i8]]], ptr @arr_9, i32 -217196, i32 %4, i32 %0, i32 %l5 store i32 0, ptr %scevgep.1, align 1 br i1 %cc, label %for.cond1.for.cond.cleanup_crit_edge, label %for.cond2.preheader.2 for.cond2.preheader.2: ; preds = %for.cond2.preheader - %indvar.next25.1 = or i32 %indvar24, 2 + %indvar.next25.1 = or disjoint i32 %indvar24, 2 %l8 = mul i32 %2, %indvar.next25.1 %scevgep.2 = getelementptr [15 x [25 x [18 x i8]]], ptr @arr_9, i32 -217196, i32 %4, i32 %0, i32 %l8 store i32 0, ptr %scevgep.2, align 1 diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll new file mode 100644 index 000000000000..0a0f3c22e374 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-align.ll @@ -0,0 +1,66 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a load instruction for a field with non-standard +; alignment by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; typedef int aligned_int __attribute__((aligned(128))); +; +; struct foo { +; int _; +; aligned_int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 2 + %1 = load i32, ptr %a, align 128, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) +; ^^^^ +; alignment 2**7 +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) +; CHECK: attributes #[[v2]] = { memory(argmem: read) } + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 128} +!3 = !{!"foo", !4, i64 0, !4, i64 128} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll new file mode 100644 index 000000000000..d6b1f30fa386 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-arr-pai.ll @@ -0,0 +1,93 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct bar { +; int a[7]; +; } __pai __ctx; +; +; int buz(struct bar *p) { +; return p->a[5]; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { [7 x i32] } + +; Function Attrs: nounwind +define dso_local i32 @buz(ptr noundef %p) #0 !dbg !10 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !18, metadata !DIExpression()), !dbg !19 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !20 + %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %0, i32 0, i32 0), !dbg !20, !llvm.preserve.access.index !14 + %2 = call ptr @llvm.preserve.array.access.index.p0.p0(ptr elementtype([7 x i32]) %1, i32 1, i32 5), !dbg !21, !llvm.preserve.access.index !3 + %3 = load i32, ptr %2, align 4, !dbg !21, !tbaa !22 + ret i32 %3, !dbg !26 +} + +; CHECK: define dso_local i32 @buz(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: %[[v5:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 0, i32 immarg 5) +; CHECK-SAME: #[[v6:.*]], !tbaa +; CHECK-NEXT: ret i32 %[[v5]] +; CHECK-NEXT: } +; CHECK: attributes #[[v6]] = { memory(argmem: read) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.array.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{!3} +!3 = !DICompositeType(tag: DW_TAG_array_type, baseType: !4, size: 224, elements: !5) +!4 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!5 = !{!6} +!6 = !DISubrange(count: 7) +!7 = !{i32 2, !"Debug Info Version", i32 3} +!8 = !{i32 1, !"wchar_size", i32 4} +!9 = !{!"clang"} +!10 = distinct !DISubprogram(name: "buz", scope: !1, file: !1, line: 8, type: !11, scopeLine: 8, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !17) +!11 = !DISubroutineType(types: !12) +!12 = !{!4, !13} +!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 64) +!14 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 4, size: 224, elements: !15) +!15 = !{!16} +!16 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !14, file: !1, line: 5, baseType: !3, size: 224) +!17 = !{!18} +!18 = !DILocalVariable(name: "p", arg: 1, scope: !10, file: !1, line: 8, type: !13) +!19 = !DILocation(line: 0, scope: !10) +!20 = !DILocation(line: 9, column: 13, scope: !10) +!21 = !DILocation(line: 9, column: 10, scope: !10) +!22 = !{!23, !23, i64 0} +!23 = !{!"int", !24, i64 0} +!24 = !{!"omnipotent char", !25, i64 0} +!25 = !{!"Simple C/C++ TBAA"} +!26 = !DILocation(line: 9, column: 3, scope: !10) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll new file mode 100644 index 000000000000..0a0c8ce9af5f --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-atomic.ll @@ -0,0 +1,66 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of atomic load instruction by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; int r; +; __atomic_load(&p->a, &r, 2); +; consume(r); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %1 = load atomic i32, ptr %a acquire, align 4 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr elementtype(%struct.foo) %[[p:.*]], +; i1 false, i8 4, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; ^^^^ +; atomic order +; CHECK-NOT: #{{[0-9]+}} +; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +declare void @consume(i32 noundef) #3 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll new file mode 100644 index 000000000000..4832fb2a50c0 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-2.ll @@ -0,0 +1,82 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds GEP chains that end by +; getelementptr.and.load. +; +; Source (modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->b.bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; And modified to fold last getelementptr/load as a single +; getelementptr.and.load. + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %bb1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.bar) %b, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) + #4, !tbaa !2 + call void @consume(i32 noundef %bb1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[bb1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[bb1]]) +; CHECK: attributes #[[v2]] = { memory(argmem: read) } + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll new file mode 100644 index 000000000000..c4a92481a0b1 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-oob.ll @@ -0,0 +1,73 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset keeps track of 'inbounds' flags while +; folding chain of GEP instructions. +; +; Source (IR modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a[2]; +; }; +; +; struct bar { +; int a; +; struct foo b; +; } __ctx; +; +; extern void consume(int); +; +; void buz(struct bar *p) { +; consume(p->b.a[1]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; Modified to remove one of the 'inbounds' from one of the GEP instructions. + +%struct.bar = type { i32, %struct.foo } +%struct.foo = type { [2 x i32] } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %a = getelementptr %struct.foo, ptr %b, i32 0, i32 0 + %arrayidx = getelementptr inbounds [2 x i32], ptr %a, i64 0, i64 1 + %1 = load i32, ptr %arrayidx, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[v1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 false, +; ^^^^^^^^ +; not inbounds +; CHECK-SAME: i32 immarg 0, i32 immarg 1, i32 immarg 0, i64 immarg 1) +; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +; folded gep chain +; CHECK-NEXT: call void @consume(i32 noundef %[[v1]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll new file mode 100644 index 000000000000..da3e01a455a5 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-oob.ll @@ -0,0 +1,74 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has unexpected shape and thus is +; folded as i8 access. +; +; Source (IR modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char a[2]; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; extern void consume(char); +; +; void buz(struct bar *p) { +; consume((&p->b)[1].a[1]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; Modified to remove 'inbounds' from one of the GEP instructions. + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { [2 x i8] } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %arrayidx = getelementptr inbounds %struct.foo, ptr %b, i64 1 +; ^^^^^ +; folded as i8 access because of this index + %a = getelementptr %struct.foo, ptr %arrayidx, i32 0, i32 0 + %arrayidx1 = getelementptr inbounds [2 x i8], ptr %a, i64 0, i64 1 + %1 = load i8, ptr %arrayidx1, align 1, !tbaa !2 + call void @consume(i8 noundef signext %1) + ret void +} + +; CHECK: %[[v1:.*]] = call i8 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i8 +; CHECK-SAME: (ptr readonly elementtype(i8) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 false, i64 immarg 4) +; ^^^^^^^^ ^^^^^^^^^^^^ +; not inbounds ---' | +; offset from 'struct bar' start -------------' +; CHECK-NEXT: call void @consume(i8 noundef signext %[[v1]]) + +declare void @consume(i8 noundef signext) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll new file mode 100644 index 000000000000..757e06c507c6 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8-type-mismatch.ll @@ -0,0 +1,73 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has unexpected shape and thus is +; folded as i8 access. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; extern void consume(char); +; +; void buz(struct bar *p) { +; consume(((struct foo *)(((char*)&p->b) + 1))->bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { i8, i8 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %add.ptr = getelementptr inbounds i8, ptr %b, i64 1 +; ~~ +; these types do not match, thus GEP chain is folded as an offset +; ~~~~~~~~~~~ + %bb = getelementptr inbounds %struct.foo, ptr %add.ptr, i32 0, i32 1 + %1 = load i8, ptr %bb, align 1, !tbaa !2 + call void @consume(i8 noundef signext %1) + ret void +} + +; CHECK: %[[bb1:.*]] = call i8 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i8 +; CHECK-SAME: (ptr readonly elementtype(i8) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) +; ^^^^^^^^^^^^ +; offset from 'struct bar' start +; CHECK-NEXT: call void @consume(i8 noundef signext %[[bb1]]) + +declare void @consume(i8 noundef signext) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll new file mode 100644 index 000000000000..e91aa93775e1 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain-u8.ll @@ -0,0 +1,71 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has unexpected shape and thus is +; folded as i8 access. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char a[2]; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; extern void consume(char); +; +; void buz(struct bar *p) { +; consume((&p->b)[1].a[1]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { [2 x i8] } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %arrayidx = getelementptr inbounds %struct.foo, ptr %b, i64 1 +; ^^^^^ +; folded as i8 access because of this index + %a = getelementptr inbounds %struct.foo, ptr %arrayidx, i32 0, i32 0 + %arrayidx1 = getelementptr inbounds [2 x i8], ptr %a, i64 0, i64 1 + %1 = load i8, ptr %arrayidx1, align 1, !tbaa !2 + call void @consume(i8 noundef signext %1) + ret void +} + +; CHECK: %[[v1:.*]] = call i8 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i8 +; CHECK-SAME: (ptr readonly elementtype(i8) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 4) +; ^^^^^^^^^^^^ +; offset from 'struct bar' start +; CHECK-NEXT: call void @consume(i8 noundef signext %[[v1]]) + +declare void @consume(i8 noundef signext) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll new file mode 100644 index 000000000000..ac08fed70c8a --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-chain.ll @@ -0,0 +1,68 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a[2]; +; }; +; +; struct bar { +; int a; +; struct foo b; +; } __ctx; +; +; extern void consume(int); +; +; void buz(struct bar *p) { +; consume(p->b.a[1]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i32, %struct.foo } +%struct.foo = type { [2 x i32] } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %a = getelementptr inbounds %struct.foo, ptr %b, i32 0, i32 0 + %arrayidx = getelementptr inbounds [2 x i32], ptr %a, i64 0, i64 1 + %1 = load i32, ptr %arrayidx, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[v1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %{{[^,]+}}, +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, +; CHECK-SAME: i32 immarg 0, i32 immarg 1, i32 immarg 0, i64 immarg 1) +; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +; folded gep chain +; CHECK-NEXT: call void @consume(i32 noundef %[[v1]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll new file mode 100644 index 000000000000..9149b350dd89 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll @@ -0,0 +1,85 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check position of bpf-preserve-static-offset pass in the pipeline: +; - preserve.static.offset call is preserved if address is passed as +; a parameter to an inline-able function; +; - second bpf-preserve-static-offset pass (after inlining) should introduce +; getelementptr.and.load call using the preserved marker. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; extern void consume(int); +; +; static inline void bar(struct bar *p){ +; consume(p->bb); +; } +; +; void quux(struct foo *p) { +; bar(&p->b); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @quux(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + call void @bar(ptr noundef %b) + ret void +} + +; Function Attrs: inlinehint nounwind +define internal void @bar(ptr noundef %p) #1 { +entry: + %bb = getelementptr inbounds %struct.bar, ptr %p, i32 0, i32 1 + %0 = load i32, ptr %bb, align 4, !tbaa !2 + call void @consume(i32 noundef %0) + ret void +} + +; CHECK: define dso_local void @quux(ptr nocapture noundef readonly %[[p:.*]]) +; CHECK: %[[bb_i1:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK-NEXT: tail call void @consume(i32 noundef %[[bb_i1]]) +; CHECK: attributes #[[v2]] = { memory(argmem: read) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +declare void @consume(i32 noundef) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { inlinehint nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"bar", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll new file mode 100644 index 000000000000..2dd6edf4c4b8 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-non-const.ll @@ -0,0 +1,75 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s 2>&1 | FileCheck %s +; +; If load offset is not a constant bpf-preserve-static-offset should report a +; warning and remove preserve.static.offset call. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a[7]; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p, unsigned long i) { +; consume(p->a[i]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -debug-info-kind=line-tables-only -triple bpf \ +; -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +; CHECK: warning: some-file.c:10:11: in function bar void (ptr, i64): +; CHECK-SAME: Non-constant offset in access to a field of a type marked with +; CHECK-SAME: preserve_static_offset might be rejected by BPF verifier + +%struct.foo = type { [7 x i32] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p, i64 noundef %i) #0 !dbg !5 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !8 + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 0, !dbg !8 + %arrayidx = getelementptr inbounds [7 x i32], ptr %a, i64 0, i64 %i, !dbg !9 + %1 = load i32, ptr %arrayidx, align 4, !dbg !9, !tbaa !10 + call void @consume(i32 noundef %1), !dbg !14 + ret void, !dbg !15 +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]], i64 noundef %[[i:.*]]) +; CHECK: %[[a:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 0, !dbg +; CHECK-NEXT: %[[arrayidx:.*]] = getelementptr inbounds [7 x i32], ptr %[[a]], i64 0, i64 %[[i]], !dbg +; CHECK-NEXT: %[[v5:.*]] = load i32, ptr %[[arrayidx]], align 4, !dbg {{.*}}, !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[v5]]), !dbg + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!llvm.ident = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !{i32 1, !"wchar_size", i32 4} +!4 = !{!"clang"} +!5 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 9, type: !6, scopeLine: 9, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0) +!6 = !DISubroutineType(types: !7) +!7 = !{} +!8 = !DILocation(line: 10, column: 14, scope: !5) +!9 = !DILocation(line: 10, column: 11, scope: !5) +!10 = !{!11, !11, i64 0} +!11 = !{!"int", !12, i64 0} +!12 = !{!"omnipotent char", !13, i64 0} +!13 = !{!"Simple C/C++ TBAA"} +!14 = !DILocation(line: 10, column: 3, scope: !5) +!15 = !DILocation(line: 11, column: 1, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll new file mode 100644 index 000000000000..6ec59c6b2c02 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-ptr-pai.ll @@ -0,0 +1,114 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct bar { +; int a; +; int b; +; } __pai; +; +; struct buz { +; int _1; +; struct bar *b; +; } __pai __ctx; +; +; void foo(struct buz *p) { +; p->b->b = 42; +; } +; +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes \ +; -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.buz = type { i32, ptr } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @foo(ptr noundef %p) #0 !dbg !5 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !20, metadata !DIExpression()), !dbg !21 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !22 + %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.buz) %0, i32 1, i32 1), !dbg !22, !llvm.preserve.access.index !9 + %2 = load ptr, ptr %1, align 8, !dbg !22, !tbaa !23 + %3 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %2, i32 1, i32 1), !dbg !29, !llvm.preserve.access.index !15 + store i32 42, ptr %3, align 4, !dbg !30, !tbaa !31 + ret void, !dbg !33 +} + +; CHECK: define dso_local void @foo(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: %[[v5:.*]] = call ptr (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.p0 +; CHECK-SAME: (ptr readonly elementtype(%struct.buz) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 3, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-SAME: #[[v6:.*]], !tbaa +; CHECK-NEXT: %[[v8:.*]] = +; CHECK-SAME: call ptr @llvm.preserve.struct.access.index.p0.p0 +; CHECK-SAME: (ptr elementtype(%struct.bar) %[[v5]], i32 1, i32 1), +; CHECK-SAME: !dbg ![[#]], !llvm.preserve.access.index ![[#]] +; CHECK-NEXT: store i32 42, ptr %[[v8]], align 4, !dbg ![[#]], !tbaa +; CHECK-NEXT: ret void, !dbg +; CHECK-NEXT: } + +; CHECK : attributes #[[v6]] = { memory(argmem: read) } + + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!llvm.ident = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !{i32 1, !"wchar_size", i32 4} +!4 = !{!"clang"} +!5 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 14, type: !6, scopeLine: 14, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !19) +!6 = !DISubroutineType(types: !7) +!7 = !{null, !8} +!8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64) +!9 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "buz", file: !1, line: 9, size: 128, elements: !10) +!10 = !{!11, !13} +!11 = !DIDerivedType(tag: DW_TAG_member, name: "_1", scope: !9, file: !1, line: 10, baseType: !12, size: 32) +!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!13 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !9, file: !1, line: 11, baseType: !14, size: 64, offset: 64) +!14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 64) +!15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 4, size: 64, elements: !16) +!16 = !{!17, !18} +!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !15, file: !1, line: 5, baseType: !12, size: 32) +!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !15, file: !1, line: 6, baseType: !12, size: 32, offset: 32) +!19 = !{!20} +!20 = !DILocalVariable(name: "p", arg: 1, scope: !5, file: !1, line: 14, type: !8) +!21 = !DILocation(line: 0, scope: !5) +!22 = !DILocation(line: 15, column: 6, scope: !5) +!23 = !{!24, !28, i64 8} +!24 = !{!"buz", !25, i64 0, !28, i64 8} +!25 = !{!"int", !26, i64 0} +!26 = !{!"omnipotent char", !27, i64 0} +!27 = !{!"Simple C/C++ TBAA"} +!28 = !{!"any pointer", !26, i64 0} +!29 = !DILocation(line: 15, column: 9, scope: !5) +!30 = !DILocation(line: 15, column: 11, scope: !5) +!31 = !{!32, !25, i64 4} +!32 = !{!"bar", !25, i64 0, !25, i64 4} +!33 = !DILocation(line: 16, column: 1, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll new file mode 100644 index 000000000000..03ae7f3272dc --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-simple.ll @@ -0,0 +1,71 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a simple load instruction by bpf-preserve-static-offset. +; Verify: +; - presence of gep.and.load intrinsic call +; - correct attributes for intrinsic call +; - presence of tbaa annotations +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %1 = load i32, ptr %a, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-SAME: #[[v1:.*]], !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) + +; CHECK: declare i32 +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, {{.*}}) #[[v2:.*]] + +; CHECK: attributes #[[v2]] = { nocallback nofree nounwind willreturn } +; CHECK: attributes #[[v1]] = { memory(argmem: read) } + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll new file mode 100644 index 000000000000..5baa7ad0242c --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-struct-pai.ll @@ -0,0 +1,105 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct foo { +; int a; +; int b; +; }; +; +; struct bar { +; int _1; +; int _2; +; struct foo c; +; } __pai __ctx; +; +; int buz(struct bar *p) { +; return p->c.b; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes \ +; -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i32, i32, %struct.foo } +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local i32 @buz(ptr noundef %p) #0 !dbg !5 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !20, metadata !DIExpression()), !dbg !21 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !22 + %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %0, i32 2, i32 2), !dbg !22, !llvm.preserve.access.index !10 + %b = getelementptr inbounds %struct.foo, ptr %1, i32 0, i32 1, !dbg !23 + %2 = load i32, ptr %b, align 4, !dbg !23, !tbaa !24 + ret i32 %2, !dbg !30 +} + +; CHECK: define dso_local i32 @buz(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: %[[b1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 2, i32 immarg 1) +; CHECK-SAME: #[[v5:.*]], !tbaa +; CHECK-NEXT: ret i32 %[[b1]] +; CHECK-NEXT: } + +; CHECK: attributes #[[v5]] = { memory(argmem: read) } + + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!llvm.ident = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !{i32 1, !"wchar_size", i32 4} +!4 = !{!"clang"} +!5 = distinct !DISubprogram(name: "buz", scope: !1, file: !1, line: 15, type: !6, scopeLine: 15, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !19) +!6 = !DISubroutineType(types: !7) +!7 = !{!8, !9} +!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64) +!10 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 9, size: 128, elements: !11) +!11 = !{!12, !13, !14} +!12 = !DIDerivedType(tag: DW_TAG_member, name: "_1", scope: !10, file: !1, line: 10, baseType: !8, size: 32) +!13 = !DIDerivedType(tag: DW_TAG_member, name: "_2", scope: !10, file: !1, line: 11, baseType: !8, size: 32, offset: 32) +!14 = !DIDerivedType(tag: DW_TAG_member, name: "c", scope: !10, file: !1, line: 12, baseType: !15, size: 64, offset: 64) +!15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 4, size: 64, elements: !16) +!16 = !{!17, !18} +!17 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !15, file: !1, line: 5, baseType: !8, size: 32) +!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !15, file: !1, line: 6, baseType: !8, size: 32, offset: 32) +!19 = !{!20} +!20 = !DILocalVariable(name: "p", arg: 1, scope: !5, file: !1, line: 15, type: !9) +!21 = !DILocation(line: 0, scope: !5) +!22 = !DILocation(line: 16, column: 13, scope: !5) +!23 = !DILocation(line: 16, column: 15, scope: !5) +!24 = !{!25, !26, i64 12} +!25 = !{!"bar", !26, i64 0, !26, i64 4, !29, i64 8} +!26 = !{!"int", !27, i64 0} +!27 = !{!"omnipotent char", !28, i64 0} +!28 = !{!"Simple C/C++ TBAA"} +!29 = !{!"foo", !26, i64 0, !26, i64 4} +!30 = !DILocation(line: 16, column: 3, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll new file mode 100644 index 000000000000..019c93c424b1 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-align.ll @@ -0,0 +1,67 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that getelementptr.and.load unroll restores alignment spec. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; typedef int aligned_int __attribute__((aligned(128))); +; +; struct foo { +; int _; +; aligned_int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %a1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) + #4, !tbaa !2 + call void @consume(i32 noundef %a1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[a11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 2 +; CHECK: %[[v2:.*]] = load i32, ptr %[[a11]], align 128 +; CHECK: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 128} +!3 = !{!"foo", !4, i64 0, !4, i64 128} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll new file mode 100644 index 000000000000..d8fa3482b6cc --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-oob.ll @@ -0,0 +1,74 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that getelementptr.and.load unroll can skip 'inbounds' flag. +; +; Source (IR modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; extern void consume(int); +; +; void buz(struct foo *p) { +; consume(p->b.bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - +; +; Modified to set 'inbounds' flag to false. + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %bb1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 false, i32 immarg 0, i32 immarg 1, i32 immarg 1) + #4, !tbaa !2 + call void @consume(i32 noundef %bb1) + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[bb11:.*]] = getelementptr %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 +; CHECK: %[[v2:.*]] = load i32, ptr %[[bb11]], align 4 +; CHECK: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll new file mode 100644 index 000000000000..ac6f830bf5d4 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain-u8.ll @@ -0,0 +1,68 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.load when direct memory offset is +; used instead of field indexes. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; extern void consume(char); +; +; void buz(struct bar *p) { +; consume(((struct foo *)(((char*)&p->b) + 1))->bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %bb1 = call i8 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i8 + (ptr readonly elementtype(i8) %p, + i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) + #4, !tbaa !2 + call void @consume(i8 noundef signext %bb1) + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[bb11:.*]] = getelementptr inbounds i8, ptr %[[p]], i64 3 +; CHECK: %[[v2:.*]] = load i8, ptr %[[bb11]], align 1 +; CHECK: call void @consume(i8 noundef signext %[[v2]]) + +declare void @consume(i8 noundef signext) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i8 @llvm.bpf.getelementptr.and.load.i8(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll new file mode 100644 index 000000000000..d6ffb270529a --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-chain.ll @@ -0,0 +1,73 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.load when several field indexes +; are specified in a chain. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; extern void consume(int); +; +; void buz(struct foo *p) { +; consume(p->b.bb); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %bb1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) + #4, !tbaa !2 + call void @consume(i32 noundef %bb1) + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[bb11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 +; CHECK: %[[v2:.*]] = load i32, ptr %[[bb11]], align 4 +; CHECK: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll new file mode 100644 index 000000000000..ae19dd7ad98d --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-simple.ll @@ -0,0 +1,65 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.load. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; consume(p->b); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %b1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr readonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) + #4, !tbaa !2 + call void @consume(i32 noundef %b1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) #[[v1:.*]] { +; CHECK: %[[b11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 +; CHECK-NEXT: %[[v2:.*]] = load i32, ptr %[[b11]], align 4 +; CHECK-NEXT: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } +attributes #4 = { memory(argmem: read) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll new file mode 100644 index 000000000000..d9634a3fc3a9 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-undo-volatile.ll @@ -0,0 +1,64 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that unroll of getelementptr.and.load restores volatile. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; volatile int b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; consume(p->b); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %b1 = call i32 (ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.load.i32 + (ptr elementtype(%struct.foo) %p, + i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1), + !tbaa !2 + call void @consume(i32 noundef %b1) + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[b11:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 +; CHECK: %[[v2:.*]] = load volatile i32, ptr %[[b11]], align 4 +; CHECK: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nounwind willreturn +declare i32 @llvm.bpf.getelementptr.and.load.i32(ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #3 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { nocallback nofree nounwind willreturn } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll new file mode 100644 index 000000000000..f90e3c54b072 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-union-pai.ll @@ -0,0 +1,110 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct foo { +; char a[10]; +; } __pai; +; +; struct bar { +; int a; +; int b; +; } __pai; +; +; union buz { +; struct foo a; +; struct bar b; +; } __pai __ctx; +; +; int quux(union buz *p) { +; return p->b.b; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local i32 @quux(ptr noundef %p) #0 !dbg !5 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !26, metadata !DIExpression()), !dbg !27 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !28 + %1 = call ptr @llvm.preserve.union.access.index.p0.p0(ptr %0, i32 1), !dbg !28, !llvm.preserve.access.index !10 + %2 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %1, i32 1, i32 1), !dbg !29, !llvm.preserve.access.index !21 + %3 = load i32, ptr %2, align 4, !dbg !29, !tbaa !30 + ret i32 %3, !dbg !33 +} + +; CHECK: define dso_local i32 @quux(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: %[[v5:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.bar) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-SAME: #[[v6:.*]], !tbaa +; CHECK-NEXT: ret i32 %[[v5]] +; CHECK-NEXT: } +; CHECK: attributes #[[v6]] = { memory(argmem: read) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.union.access.index.p0.p0(ptr, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} +!llvm.ident = !{!4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !{i32 1, !"wchar_size", i32 4} +!4 = !{!"clang"} +!5 = distinct !DISubprogram(name: "quux", scope: !1, file: !1, line: 18, type: !6, scopeLine: 18, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !25) +!6 = !DISubroutineType(types: !7) +!7 = !{!8, !9} +!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64) +!10 = distinct !DICompositeType(tag: DW_TAG_union_type, name: "buz", file: !1, line: 13, size: 96, elements: !11) +!11 = !{!12, !20} +!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !10, file: !1, line: 14, baseType: !13, size: 80) +!13 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 4, size: 80, elements: !14) +!14 = !{!15} +!15 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !13, file: !1, line: 5, baseType: !16, size: 80) +!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 80, elements: !18) +!17 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) +!18 = !{!19} +!19 = !DISubrange(count: 10) +!20 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !10, file: !1, line: 15, baseType: !21, size: 64) +!21 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 8, size: 64, elements: !22) +!22 = !{!23, !24} +!23 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !21, file: !1, line: 9, baseType: !8, size: 32) +!24 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !21, file: !1, line: 10, baseType: !8, size: 32, offset: 32) +!25 = !{!26} +!26 = !DILocalVariable(name: "p", arg: 1, scope: !5, file: !1, line: 18, type: !9) +!27 = !DILocation(line: 0, scope: !5) +!28 = !DILocation(line: 19, column: 13, scope: !5) +!29 = !DILocation(line: 19, column: 15, scope: !5) +!30 = !{!31, !31, i64 0} +!31 = !{!"omnipotent char", !32, i64 0} +!32 = !{!"Simple C/C++ TBAA"} +!33 = !DILocation(line: 19, column: 3, scope: !5) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll new file mode 100644 index 000000000000..78172cd17dca --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll @@ -0,0 +1,108 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check position of bpf-preserve-static-offset pass in the pipeline: +; - preserve.static.offset call is preserved if address is passed as +; a parameter to an inline-able function; +; - second bpf-preserve-static-offset pass (after inlining) should introduce +; getelementptr.and.load call using the preserved marker after loops +; unrolling; +; - readonly and tbaa attributes should allow replacement of +; getelementptr.and.load calls by CSE transformation. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b[4]; +; } __ctx; +; +; extern void consume(int); +; +; static inline void bar(int * restrict p) { +; consume(p[1]); +; } +; +; void quux(struct foo *p){ +; unsigned long i = 0; +; #pragma clang loop unroll(full) +; while (i < 2) { +; bar(p->b); +; ++i; +; } +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [4 x i32] } + +; Function Attrs: nounwind +define dso_local void @quux(ptr noundef %p) #0 { +entry: + br label %while.cond + +while.cond: ; preds = %while.body, %entry + %i.0 = phi i64 [ 0, %entry ], [ %inc, %while.body ] + %cmp = icmp ult i64 %i.0, 2 + br i1 %cmp, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %arraydecay = getelementptr inbounds [4 x i32], ptr %b, i64 0, i64 0 + call void @bar(ptr noundef %arraydecay) + %inc = add i64 %i.0, 1 + br label %while.cond, !llvm.loop !2 + +while.end: ; preds = %while.cond + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: inlinehint nounwind +define internal void @bar(ptr noalias noundef %p) #2 { +entry: + %arrayidx = getelementptr inbounds i32, ptr %p, i64 1 + %0 = load i32, ptr %arrayidx, align 4, !tbaa !5 + call void @consume(i32 noundef %0) + ret void +} + +; CHECK: define dso_local void @quux(ptr nocapture noundef readonly %[[p:.*]]) +; CHECK: %[[v1:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i64 immarg 1) +; CHECK: tail call void @consume(i32 noundef %[[v1]]) +; CHECK: tail call void @consume(i32 noundef %[[v1]]) + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #3 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +declare void @consume(i32 noundef) #4 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { inlinehint nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #4 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = distinct !{!2, !3, !4} +!3 = !{!"llvm.loop.mustprogress"} +!4 = !{!"llvm.loop.unroll.full"} +!5 = !{!6, !6, i64 0} +!6 = !{!"int", !7, i64 0} +!7 = !{!"omnipotent char", !8, i64 0} +!8 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll new file mode 100644 index 000000000000..7c3303342bb6 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll @@ -0,0 +1,95 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check position of bpf-preserve-static-offset pass in the pipeline: +; preserve.static.offset call should be preserved long enough to allow +; introduction of getelementptr.and.load after loops unrolling. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b[4]; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; unsigned long i = 0; +; #pragma clang loop unroll(full) +; while (i < 2) +; consume(p->b[i++]); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [4 x i32] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + br label %while.cond + +while.cond: ; preds = %while.body, %entry + %i.0 = phi i64 [ 0, %entry ], [ %inc, %while.body ] + %cmp = icmp ult i64 %i.0, 2 + br i1 %cmp, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %inc = add i64 %i.0, 1 + %arrayidx = getelementptr inbounds [4 x i32], ptr %b, i64 0, i64 %i.0 + %1 = load i32, ptr %arrayidx, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + br label %while.cond, !llvm.loop !6 + +while.end: ; preds = %while.cond + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef readonly %[[p:.*]]) +; CHECK: %[[v1:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i64 immarg 0) +; CHECK-SAME: #[[attrs:.*]], !tbaa +; CHECK-NEXT: tail call void @consume(i32 noundef %[[v1]]) +; CHECK-NEXT: %[[v2:.*]] = tail call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr readonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1, i64 immarg 1) +; CHECK-SAME: #[[attrs]], !tbaa +; CHECK-NEXT: tail call void @consume(i32 noundef %[[v2]]) +; CHECK: attributes #[[attrs]] = { memory(argmem: read) } + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +declare void @consume(i32 noundef) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #3 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} +!6 = distinct !{!6, !7, !8} +!7 = !{!"llvm.loop.mustprogress"} +!8 = !{!"llvm.loop.unroll.full"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll new file mode 100644 index 000000000000..819a4b31fb23 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-volatile.ll @@ -0,0 +1,62 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a volatile load instruction by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; volatile int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %1 = load volatile i32, ptr %a, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: %[[a1:.*]] = call i32 (ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.load.i32 +; CHECK-SAME: (ptr elementtype(%struct.foo) %{{[^,]+}}, +; CHECK-SAME: i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; ^^^^^^^^ +; volatile +; CHECK-NOT: #{{[0-9]+}} +; CHECK-NEXT: call void @consume(i32 noundef %[[a1]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll new file mode 100644 index 000000000000..681c9640cbb8 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/load-zero.ll @@ -0,0 +1,57 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that loads from zero offset are not modified by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p) { +; consume(p->a); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 0 + %1 = load i32, ptr %a, align 4, !tbaa !2 + call void @consume(i32 noundef %1) + ret void +} + +; CHECK: entry: +; CHECK-NEXT: %[[a:.*]] = getelementptr inbounds %struct.foo, ptr %[[p:.*]], i32 0, i32 0 +; CHECK-NEXT: %[[v2:.*]] = load i32, ptr %[[a]], align 4, !tbaa +; CHECK-NEXT: call void @consume(i32 noundef %[[v2]]) + +declare void @consume(i32 noundef) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 0} +!3 = !{!"foo", !4, i64 0} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll new file mode 100644 index 000000000000..667f8f5a8d8b --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-align.ll @@ -0,0 +1,59 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a store instruction for a field with non-standard +; alignment by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; typedef int aligned_int __attribute__((aligned(128))); +; +; struct foo { +; int _; +; aligned_int a; +; } __ctx; +; +; void bar(struct foo *p) { +; p->a = 7; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 2 + store i32 7, ptr %a, align 128, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 7, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 128} +!3 = !{!"foo", !4, i64 0, !4, i64 128} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll new file mode 100644 index 000000000000..443966337b9d --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-atomic.ll @@ -0,0 +1,60 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of atomic store instruction by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; int a; +; } __ctx; +; +; void bar(struct foo *p) { +; int r; +; r = 7; +; __atomic_store(&p->a, &r, 3); +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + store atomic i32 7, ptr %a release, align 4 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 7, +; CHECK-SAME: ptr elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 5, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-NOT: #{{[0-9]+}} +; CHECK-NEXT: ret void + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll new file mode 100644 index 000000000000..49f3fa5b8383 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-2.ll @@ -0,0 +1,77 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds GEP chains that end by +; getelementptr.and.store. +; +; Source (modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; And modified to fold last getelementptr/store as a single +; getelementptr.and.store. + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.bar) %b, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll new file mode 100644 index 000000000000..e2878f091303 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-oob.ll @@ -0,0 +1,67 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset keeps track of 'inbounds' flags while +; folding chain of GEP instructions. +; +; Source (IR modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; Modified to remove one of the 'inbounds' from one of the GEP instructions. + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %bb = getelementptr %struct.bar, ptr %b, i32 0, i32 1 + store i32 42, ptr %bb, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 false, i32 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll new file mode 100644 index 000000000000..a33732546677 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8-oob.ll @@ -0,0 +1,67 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has type mismatch and thus is +; folded as i8 access. +; +; Source (modified by hand): +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; void buz(struct bar *p) { +; ((struct foo *)(((char*)&p->b) + 1))->bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - +; +; Modified to remove one of the 'inbounds' from one of the getelementptr. + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { i8, i8 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %add.ptr = getelementptr i8, ptr %b, i64 1 + %bb = getelementptr inbounds %struct.foo, ptr %add.ptr, i32 0, i32 1 + store i8 42, ptr %bb, align 1, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i8, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i8 +; CHECK-SAME: (i8 42, +; CHECK-SAME: ptr writeonly elementtype(i8) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 false, i64 immarg 3) +; CHECK-SAME: #[[v2:.*]], !tbaa ![[v3:.*]] +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll new file mode 100644 index 000000000000..92740603ae69 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain-u8.ll @@ -0,0 +1,68 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; The GEP chain in this example has type mismatch and thus is +; folded as i8 access. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; void buz(struct bar *p) { +; ((struct foo *)(((char*)&p->b) + 1))->bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.bar = type { i8, %struct.foo } +%struct.foo = type { i8, i8 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.bar, ptr %0, i32 0, i32 1 + %add.ptr = getelementptr inbounds i8, ptr %b, i64 1 +; ~~ +; these types do not match, thus GEP chain is folded as an offset +; ~~~~~~~~~~~ + %bb = getelementptr inbounds %struct.foo, ptr %add.ptr, i32 0, i32 1 + store i8 42, ptr %bb, align 1, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i8, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i8 +; CHECK-SAME: (i8 42, +; CHECK-SAME: ptr writeonly elementtype(i8) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) +; CHECK-SAME: #[[v2:.*]], !tbaa ![[v3:.*]] +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll new file mode 100644 index 000000000000..d4c90616bf5c --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-chain.ll @@ -0,0 +1,64 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that bpf-preserve-static-offset folds chain of GEP instructions. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %bb = getelementptr inbounds %struct.bar, ptr %b, i32 0, i32 1 + store i32 42, ptr %bb, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll new file mode 100644 index 000000000000..b22b26836826 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-pai.ll @@ -0,0 +1,136 @@ +; RUN: opt -passes=bpf-preserve-static-offset -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; #define __pai __attribute__((preserve_access_index)) +; +; struct foo { +; char a[10]; +; } __pai; +; +; struct bar { +; int a; +; int b; +; } __pai; +; +; struct buz { +; int _1; +; int _2; +; int _3; +; union { +; struct foo a; +; struct bar b[7]; +; }; +; } __pai __ctx; +; +; void quux(struct buz *p) { +; p->b[5].b = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes \ +; -debug-info-kind=limited -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.buz = type { i32, i32, i32, %union.anon } +%union.anon = type { [7 x %struct.bar] } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @quux(ptr noundef %p) #0 !dbg !31 { +entry: + call void @llvm.dbg.value(metadata ptr %p, metadata !36, metadata !DIExpression()), !dbg !37 + %0 = call ptr @llvm.preserve.static.offset(ptr %p), !dbg !38 + %1 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.buz) %0, i32 3, i32 3), !dbg !38, !llvm.preserve.access.index !4 + %2 = call ptr @llvm.preserve.union.access.index.p0.p0(ptr %1, i32 1), !dbg !38, !llvm.preserve.access.index !3 + %3 = call ptr @llvm.preserve.array.access.index.p0.p0(ptr elementtype([7 x %struct.bar]) %2, i32 1, i32 5), !dbg !39, !llvm.preserve.access.index !21 + %4 = call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%struct.bar) %3, i32 1, i32 1), !dbg !40, !llvm.preserve.access.index !22 + store i32 42, ptr %4, align 4, !dbg !41, !tbaa !42 + ret void, !dbg !45 +} + +; CHECK: define dso_local void @quux(ptr noundef %[[p:.*]]) {{.*}} { +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.dbg.value +; CHECK-NEXT: call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr writeonly elementtype(i8) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 56) +; CHECK-SAME: #[[v5:.*]], !tbaa +; CHECK-NEXT: ret void, !dbg +; CHECK-NEXT: } +; CHECK: attributes #[[v5]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.struct.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.union.access.index.p0.p0(ptr, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare ptr @llvm.preserve.array.access.index.p0.p0(ptr, i32 immarg, i32 immarg) #2 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!28, !29} +!llvm.ident = !{!30} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "some-file.c", directory: "/some/dir/") +!2 = !{!3, !21} +!3 = distinct !DICompositeType(tag: DW_TAG_union_type, scope: !4, file: !1, line: 17, size: 448, elements: !11) +!4 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "buz", file: !1, line: 13, size: 544, elements: !5) +!5 = !{!6, !8, !9, !10} +!6 = !DIDerivedType(tag: DW_TAG_member, name: "_1", scope: !4, file: !1, line: 14, baseType: !7, size: 32) +!7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!8 = !DIDerivedType(tag: DW_TAG_member, name: "_2", scope: !4, file: !1, line: 15, baseType: !7, size: 32, offset: 32) +!9 = !DIDerivedType(tag: DW_TAG_member, name: "_3", scope: !4, file: !1, line: 16, baseType: !7, size: 32, offset: 64) +!10 = !DIDerivedType(tag: DW_TAG_member, scope: !4, file: !1, line: 17, baseType: !3, size: 448, offset: 96) +!11 = !{!12, !20} +!12 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !3, file: !1, line: 18, baseType: !13, size: 80) +!13 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo", file: !1, line: 4, size: 80, elements: !14) +!14 = !{!15} +!15 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !13, file: !1, line: 5, baseType: !16, size: 80) +!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 80, elements: !18) +!17 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) +!18 = !{!19} +!19 = !DISubrange(count: 10) +!20 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !3, file: !1, line: 19, baseType: !21, size: 448) +!21 = !DICompositeType(tag: DW_TAG_array_type, baseType: !22, size: 448, elements: !26) +!22 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "bar", file: !1, line: 8, size: 64, elements: !23) +!23 = !{!24, !25} +!24 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !22, file: !1, line: 9, baseType: !7, size: 32) +!25 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !22, file: !1, line: 10, baseType: !7, size: 32, offset: 32) +!26 = !{!27} +!27 = !DISubrange(count: 7) +!28 = !{i32 2, !"Debug Info Version", i32 3} +!29 = !{i32 1, !"wchar_size", i32 4} +!30 = !{!"clang"} +!31 = distinct !DISubprogram(name: "quux", scope: !1, file: !1, line: 23, type: !32, scopeLine: 23, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !35) +!32 = !DISubroutineType(types: !33) +!33 = !{null, !34} +!34 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !4, size: 64) +!35 = !{!36} +!36 = !DILocalVariable(name: "p", arg: 1, scope: !31, file: !1, line: 23, type: !34) +!37 = !DILocation(line: 0, scope: !31) +!38 = !DILocation(line: 24, column: 6, scope: !31) +!39 = !DILocation(line: 24, column: 3, scope: !31) +!40 = !DILocation(line: 24, column: 11, scope: !31) +!41 = !DILocation(line: 24, column: 13, scope: !31) +!42 = !{!43, !43, i64 0} +!43 = !{!"omnipotent char", !44, i64 0} +!44 = !{!"Simple C/C++ TBAA"} +!45 = !DILocation(line: 25, column: 1, scope: !31) diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll new file mode 100644 index 000000000000..a603ad866739 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-simple.ll @@ -0,0 +1,60 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a simple store instruction by bpf-preserve-static-offset. +; Verify: +; - presence of gep.and.store intrinsic call +; - correct attributes for intrinsic call +; - presence of tbaa annotations +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int _; +; int a; +; } __ctx; +; +; void bar(struct foo *p) { +; p->a = 7; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + store i32 7, ptr %a, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 7, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) +; CHECK-SAME: #[[v2:.*]], !tbaa +; CHECK: attributes #[[v2]] = { memory(argmem: write) } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll new file mode 100644 index 000000000000..7996fe0d1bb2 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-align.ll @@ -0,0 +1,62 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that getelementptr.and.store unroll restores alignment spec. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; typedef int aligned_int __attribute__((aligned(128))); +; +; struct foo { +; int _; +; aligned_int a; +; } __ctx; +; +; void bar(struct foo *p) { +; p->a = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, [124 x i8], i32, [124 x i8] } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 7, i1 true, i32 immarg 0, i32 immarg 2) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 2 +; CHECK: store i32 42, ptr %[[v2]], align 128 +; CHECK: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 128} +!3 = !{!"foo", !4, i64 0, !4, i64 128} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll new file mode 100644 index 000000000000..d2731d32ed4c --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-oob.ll @@ -0,0 +1,67 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that getelementptr.and.load unroll can skip 'inbounds' flag. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 false, i32 immarg 0, i32 immarg 1, i32 immarg 1) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 +; CHECK: store i32 42, ptr %[[v2]], align 4 +; CHECK: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll new file mode 100644 index 000000000000..184c5c334905 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain-u8.ll @@ -0,0 +1,62 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.store when direct memory offset is +; used instead of field indexes. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; char aa; +; char bb; +; }; +; +; struct bar { +; char a; +; struct foo b; +; } __ctx; +; +; void buz(struct bar *p) { +; ((struct foo *)(((char*)&p->b) + 1))->bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + call void (i8, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i8 + (i8 42, + ptr writeonly elementtype(i8) %p, + i1 false, i8 0, i8 1, i8 0, i1 true, i64 immarg 3) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr inbounds i8, ptr %[[p]], i64 3 +; CHECK: store i8 42, ptr %[[v2]], align 1 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i8(i8, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 1} +!3 = !{!"foo", !4, i64 0, !4, i64 1} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll new file mode 100644 index 000000000000..2899ab03f50d --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-chain.ll @@ -0,0 +1,68 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.store when several field indexes +; are specified in a chain. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct bar { +; int aa; +; int bb; +; }; +; +; struct foo { +; int a; +; struct bar b; +; } __ctx; +; +; void buz(struct foo *p) { +; p->b.bb = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, %struct.bar } +%struct.bar = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @buz(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1, i32 immarg 1) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @buz(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1, i32 1 +; CHECK: store i32 42, ptr %[[v2]], align 4 +; CHECK: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 8} +!3 = !{!"foo", !4, i64 0, !7, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!"bar", !4, i64 0, !4, i64 4} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll new file mode 100644 index 000000000000..8ad5eae98475 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-simple.ll @@ -0,0 +1,61 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check unroll of getelementptr.and.store. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; p->b = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr writeonly elementtype(%struct.foo) %p, + i1 false, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1) + #3, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 +; CHECK: store i32 42, ptr %[[v2]], align 4 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } +attributes #3 = { memory(argmem: write) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll new file mode 100644 index 000000000000..79495732f972 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-undo-volatile.ll @@ -0,0 +1,61 @@ +; RUN: opt --bpf-check-and-opt-ir -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that unroll of getelementptr.and.store restores volatile. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; volatile int b; +; } __ctx; +; +; extern void consume(int); +; +; void bar(struct foo *p){ +; p->b = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=sroa,bpf-preserve-static-offset -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + call void (i32, ptr, i1, i8, i8, i8, i1, ...) + @llvm.bpf.getelementptr.and.store.i32 + (i32 42, + ptr elementtype(%struct.foo) %p, + i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1), + !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr noundef %[[p:.*]]) +; CHECK: entry: +; CHECK: %[[v2:.*]] = getelementptr inbounds %struct.foo, ptr %[[p]], i32 0, i32 1 +; CHECK: store volatile i32 42, ptr %[[v2]], align 4 + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +; Function Attrs: nocallback nofree nounwind willreturn +declare void @llvm.bpf.getelementptr.and.store.i32(i32, ptr nocapture, i1 immarg, i8 immarg, i8 immarg, i8 immarg, i1 immarg, ...) #2 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nocallback nofree nounwind willreturn } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll new file mode 100644 index 000000000000..161aded79eac --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll @@ -0,0 +1,104 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check position of bpf-preserve-static-offset pass in the pipeline: +; - preserve.static.offset call is preserved if address is passed as +; a parameter to an inline-able function; +; - second bpf-preserve-static-offset pass (after inlining) should introduce +; getelementptr.and.store call using the preserved marker after loops +; unrolling; +; - memory(argmem: readwrite) and tbaa attributes should allow +; removing one getelementptr.and.store call. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; int b[4]; +; } __ctx; +; +; static inline void bar(int * restrict p, unsigned long i) { +; p[0] = i; +; } +; +; void quux(struct foo *p){ +; unsigned long i = 0; +; #pragma clang loop unroll(full) +; while (i < 2) { +; bar(p->b, i); +; ++i; +; } +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, [4 x i32] } + +; Function Attrs: nounwind +define dso_local void @quux(ptr noundef %p) #0 { +entry: + br label %while.cond + +while.cond: ; preds = %while.body, %entry + %i.0 = phi i64 [ 0, %entry ], [ %inc, %while.body ] + %cmp = icmp ult i64 %i.0, 2 + br i1 %cmp, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + %arraydecay = getelementptr inbounds [4 x i32], ptr %b, i64 0, i64 0 + call void @bar(ptr noundef %arraydecay, i64 noundef %i.0) + %inc = add i64 %i.0, 1 + br label %while.cond, !llvm.loop !2 + +while.end: ; preds = %while.cond + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + +; Function Attrs: inlinehint nounwind +define internal void @bar(ptr noalias noundef %p, i64 noundef %i) #2 { +entry: + %conv = trunc i64 %i to i32 + %arrayidx = getelementptr inbounds i32, ptr %p, i64 0 + store i32 %conv, ptr %arrayidx, align 4, !tbaa !5 + ret void +} + +; CHECK: define dso_local void @quux(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK-NEXT: entry: +; CHECK-NEXT: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 1, +; CHECK-SAME: ptr writeonly elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 false, i8 0, i8 1, i8 2, i1 true, i64 immarg 0, i32 immarg 1) +; CHECK-NEXT: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #3 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } +attributes #2 = { inlinehint nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = distinct !{!2, !3, !4} +!3 = !{!"llvm.loop.mustprogress"} +!4 = !{!"llvm.loop.unroll.full"} +!5 = !{!6, !6, i64 0} +!6 = !{!"int", !7, i64 0} +!7 = !{!"omnipotent char", !8, i64 0} +!8 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll new file mode 100644 index 000000000000..8b0493a38efa --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-volatile.ll @@ -0,0 +1,56 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check handling of a volatile store instruction by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; volatile int b; +; } __ctx; +; +; void bar(struct foo *p) { +; p->b = 42; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %b = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 1 + store volatile i32 42, ptr %b, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef %[[p:.*]]) +; CHECK: tail call void (i32, ptr, i1, i8, i8, i8, i1, ...) +; CHECK-SAME: @llvm.bpf.getelementptr.and.store.i32 +; CHECK-SAME: (i32 42, +; CHECK-SAME: ptr elementtype(%struct.foo) %[[p]], +; CHECK-SAME: i1 true, i8 0, i8 1, i8 2, i1 true, i32 immarg 0, i32 immarg 1), +; CHECK-NOT: #{{[0-9]+}} +; CHECK-SAME: !tbaa + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 4} +!3 = !{!"foo", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll b/llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll new file mode 100644 index 000000000000..7f2a06af8d10 --- /dev/null +++ b/llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll @@ -0,0 +1,51 @@ +; RUN: opt -O2 -mtriple=bpf-pc-linux -S -o - %s | FileCheck %s +; +; Check that stores from zero offset are not modified by bpf-preserve-static-offset. +; +; Source: +; #define __ctx __attribute__((preserve_static_offset)) +; +; struct foo { +; int a; +; } __ctx; +; +; void bar(struct foo *p) { +; p->a = 0; +; } +; +; Compilation flag: +; clang -cc1 -O2 -triple bpf -S -emit-llvm -disable-llvm-passes -o - \ +; | opt -passes=function(sroa) -S -o - + +%struct.foo = type { i32 } + +; Function Attrs: nounwind +define dso_local void @bar(ptr noundef %p) #0 { +entry: + %0 = call ptr @llvm.preserve.static.offset(ptr %p) + %a = getelementptr inbounds %struct.foo, ptr %0, i32 0, i32 0 + store i32 0, ptr %a, align 4, !tbaa !2 + ret void +} + +; CHECK: define dso_local void @bar(ptr nocapture noundef writeonly %[[p:.*]]) +; CHECK-NEXT: entry: +; CHECK-NEXT: store i32 0, ptr %[[p]], align 4, !tbaa +; CHECK-NEXT: ret void + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare ptr @llvm.preserve.static.offset(ptr readnone) #1 + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang"} +!2 = !{!3, !4, i64 0} +!3 = !{!"foo", !4, i64 0} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll b/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll index 0367721f6a67..a4b24a1a6110 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll @@ -27,7 +27,7 @@ b4: ; preds = %b4, %b1 %v5 = load i32, ptr %v4, align 4, !tbaa !1 %v6 = add nsw i32 %v5, %v3 store i32 %v6, ptr %v4, align 4, !tbaa !1 - %v7 = or i32 %v1, 1 + %v7 = or disjoint i32 %v1, 1 %v8 = getelementptr inbounds i32, ptr %a1, i32 %v7 %v9 = load i32, ptr %v8, align 4, !tbaa !1 %v10 = getelementptr inbounds i32, ptr %a0, i32 %v7 diff --git a/llvm/test/CodeGen/LoongArch/lasx/vselect.ll b/llvm/test/CodeGen/LoongArch/lasx/vselect.ll new file mode 100644 index 000000000000..78b99701832a --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/vselect.ll @@ -0,0 +1,85 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s + +define void @select_v32i8_imm(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: select_v32i8_imm: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvrepli.h $xr1, -256 +; CHECK-NEXT: xvbitseli.b $xr0, $xr1, 1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <32 x i8>, ptr %a0 + %sel = select <32 x i1> , <32 x i8> %v0, <32 x i8> + store <32 x i8> %sel, ptr %res + ret void +} + +define void @select_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: select_v32i8: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvrepli.h $xr2, -256 +; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <32 x i8>, ptr %a0 + %v1 = load <32 x i8>, ptr %a1 + %sel = select <32 x i1> , <32 x i8> %v0, <32 x i8> %v1 + store <32 x i8> %sel, ptr %res + ret void +} + +define void @select_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: select_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: lu12i.w $a3, -16 +; CHECK-NEXT: xvreplgr2vr.w $xr0, $a3 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvld $xr2, $a2, 0 +; CHECK-NEXT: xvbitsel.v $xr0, $xr2, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <16 x i16>, ptr %a0 + %v1 = load <16 x i16>, ptr %a1 + %sel = select <16 x i1> , <16 x i16> %v0, <16 x i16> %v1 + store <16 x i16> %sel, ptr %res + ret void +} + +define void @select_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: select_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: ori $a1, $zero, 0 +; CHECK-NEXT: lu32i.d $a1, -1 +; CHECK-NEXT: xvreplgr2vr.d $xr2, $a1 +; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <8 x i32>, ptr %a0 + %v1 = load <8 x i32>, ptr %a1 + %sel = select <8 x i1> , <8 x i32> %v0, <8 x i32> %v1 + store <8 x i32> %sel, ptr %res + ret void +} + +define void @select_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: select_v4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: pcalau12i $a3, %pc_hi20(.LCPI4_0) +; CHECK-NEXT: addi.d $a3, $a3, %pc_lo12(.LCPI4_0) +; CHECK-NEXT: xvld $xr0, $a3, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvld $xr2, $a2, 0 +; CHECK-NEXT: xvbitsel.v $xr0, $xr2, $xr1, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <4 x i64>, ptr %a0 + %v1 = load <4 x i64>, ptr %a1 + %sel = select <4 x i1> , <4 x i64> %v0, <4 x i64> %v1 + store <4 x i64> %sel, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/vselect.ll b/llvm/test/CodeGen/LoongArch/lsx/vselect.ll new file mode 100644 index 000000000000..823bd9baba91 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lsx/vselect.ll @@ -0,0 +1,85 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s + +define void @select_v16i8_imm(ptr %res, ptr %a0) nounwind { +; CHECK-LABEL: select_v16i8_imm: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vrepli.h $vr1, -256 +; CHECK-NEXT: vbitseli.b $vr0, $vr1, 255 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <16 x i8>, ptr %a0 + %sel = select <16 x i1> , <16 x i8> %v0, <16 x i8> + store <16 x i8> %sel, ptr %res + ret void +} + +define void @select_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: select_v16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vld $vr1, $a2, 0 +; CHECK-NEXT: vrepli.h $vr2, -256 +; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <16 x i8>, ptr %a0 + %v1 = load <16 x i8>, ptr %a1 + %sel = select <16 x i1> , <16 x i8> %v0, <16 x i8> %v1 + store <16 x i8> %sel, ptr %res + ret void +} + +define void @select_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: select_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: lu12i.w $a3, -16 +; CHECK-NEXT: vreplgr2vr.w $vr0, $a3 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vld $vr2, $a2, 0 +; CHECK-NEXT: vbitsel.v $vr0, $vr2, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <8 x i16>, ptr %a0 + %v1 = load <8 x i16>, ptr %a1 + %sel = select <8 x i1> , <8 x i16> %v0, <8 x i16> %v1 + store <8 x i16> %sel, ptr %res + ret void +} + +define void @select_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: select_v4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vld $vr1, $a2, 0 +; CHECK-NEXT: ori $a1, $zero, 0 +; CHECK-NEXT: lu32i.d $a1, -1 +; CHECK-NEXT: vreplgr2vr.d $vr2, $a1 +; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <4 x i32>, ptr %a0 + %v1 = load <4 x i32>, ptr %a1 + %sel = select <4 x i1> , <4 x i32> %v0, <4 x i32> %v1 + store <4 x i32> %sel, ptr %res + ret void +} + +define void @select_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind { +; CHECK-LABEL: select_v2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: pcalau12i $a3, %pc_hi20(.LCPI4_0) +; CHECK-NEXT: addi.d $a3, $a3, %pc_lo12(.LCPI4_0) +; CHECK-NEXT: vld $vr0, $a3, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vld $vr2, $a2, 0 +; CHECK-NEXT: vbitsel.v $vr0, $vr2, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <2 x i64>, ptr %a0 + %v1 = load <2 x i64>, ptr %a1 + %sel = select <2 x i1> , <2 x i64> %v0, <2 x i64> %v1 + store <2 x i64> %sel, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll index 55cf6fb82576..1ec68b4a271b 100644 --- a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll +++ b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll @@ -790,9 +790,10 @@ define void @test_ldst_v8i8(ptr %a, ptr %b) { ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ld.param.u64 %rd2, [test_ldst_v8i8_param_1]; ; CHECK-NEXT: ld.param.u64 %rd1, [test_ldst_v8i8_param_0]; -; CHECK-NEXT: ld.u32 %r1, [%rd1+4]; -; CHECK-NEXT: ld.u32 %r2, [%rd1]; -; CHECK-NEXT: st.v2.u32 [%rd2], {%r2, %r1}; +; CHECK-NEXT: ld.u32 %r1, [%rd1]; +; CHECK-NEXT: ld.u32 %r2, [%rd1+4]; +; CHECK-NEXT: st.u32 [%rd2+4], %r2; +; CHECK-NEXT: st.u32 [%rd2], %r1; ; CHECK-NEXT: ret; %t1 = load <8 x i8>, ptr %a store <8 x i8> %t1, ptr %b, align 16 diff --git a/llvm/test/CodeGen/NVPTX/vector-stores.ll b/llvm/test/CodeGen/NVPTX/vector-stores.ll index 8248bdbc1ee1..df14553a7720 100644 --- a/llvm/test/CodeGen/NVPTX/vector-stores.ll +++ b/llvm/test/CodeGen/NVPTX/vector-stores.ll @@ -37,19 +37,3 @@ define void @v16i8(ptr %a, ptr %b) { store <16 x i8> %v, ptr %b ret void } - -; CHECK-LABEL: .visible .func v16i8_store -define void @v16i8_store(ptr %a, <16 x i8> %v) { - ; CHECK: ld.param.u64 %rd1, [v16i8_store_param_0]; - ; CHECK-NEXT: ld.param.v4.u32 {%r1, %r2, %r3, %r4}, [v16i8_store_param_1]; - ; CHECK-NEXT: st.v4.u32 [%rd1], {%r1, %r2, %r3, %r4}; - store <16 x i8> %v, ptr %a - ret void -} - -; CHECK-LABEL: .visible .func v8i8_store -define void @v8i8_store(ptr %a, <8 x i8> %v) { - ; CHECK: st.v2.u32 - store <8 x i8> %v, ptr %a - ret void -} diff --git a/llvm/test/CodeGen/PowerPC/aix-alias.ll b/llvm/test/CodeGen/PowerPC/aix-alias.ll index 189b95c1b81d..5b5d2857e26e 100644 --- a/llvm/test/CodeGen/PowerPC/aix-alias.ll +++ b/llvm/test/CodeGen/PowerPC/aix-alias.ll @@ -55,7 +55,7 @@ entry: ; ASM-NEXT: .csect fun[DS] ; ASM-NEXT: fun_weak: # @fun ; ASM-NEXT: fun_hidden: -; ASM: .csect [PR],5 +; ASM: .csect ..text..[PR],5 ; ASM-NEXT: .fun: ; ASM-NEXT: .fun_weak: ; ASM-NEXT: .fun_hidden: @@ -63,7 +63,7 @@ entry: ; ASM-NEXT: li 3, 0 ; ASM-NEXT: blr ; ASM-NEXT: # -- End function -; ASM: .csect [PR],5 +; ASM: .csect ..text..[PR],5 ; ASM-NEXT: .test: ; ASM-NEXT: # %bb.0: # %entry ; ASM: bl .fun diff --git a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll index 209c3f154e47..0cfe120f0ae4 100644 --- a/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll +++ b/llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll @@ -99,7 +99,7 @@ entry: ; COMMON-NEXT: .align 2 ; COMMON-NEXT: .vbyte 4, 0 ; COMMON-NEXT: .vbyte 4, 0 -; CHECK-ASM-NEXT: .csect [PR],5 +; CHECK-ASM-NEXT: .csect ..text..[PR],5 ; CHECK-FUNC-NEXT: .csect .foov[PR],5 ; COMMON-NEXT: # -- End function ; COMMON: .toc diff --git a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll index 154bd6418947..11b6827c33b1 100644 --- a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll +++ b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll @@ -41,7 +41,7 @@ declare extern_weak void @foo_ext_weak(ptr) ; BIT64-NEXT: .vbyte 8, .main # @main ; BIT64-NEXT: .vbyte 8, TOC[TC0] ; BIT64-NEXT: .vbyte 8, 0 -; COMMON-NEXT: .csect [PR] +; COMMON-NEXT: .csect ..text..[PR] ; COMMON-NEXT: .main: ; COMMON: .csect .data[RW] diff --git a/llvm/test/CodeGen/PowerPC/aix-extern.ll b/llvm/test/CodeGen/PowerPC/aix-extern.ll index 23bf7ecab350..905e45847390 100644 --- a/llvm/test/CodeGen/PowerPC/aix-extern.ll +++ b/llvm/test/CodeGen/PowerPC/aix-extern.ll @@ -51,7 +51,7 @@ declare i32 @bar_extern(ptr) ; BIT64-NEXT: .vbyte 8, .foo # @foo ; BIT64-NEXT: .vbyte 8, TOC[TC0] ; BIT64-NEXT: .vbyte 8, 0 -; COMMON-NEXT: .csect [PR] +; COMMON-NEXT: .csect ..text..[PR] ; COMMON-NEXT: .foo: ; COMMON: .globl main[DS] # -- Begin function main @@ -64,7 +64,7 @@ declare i32 @bar_extern(ptr) ; BIT64-NEXT: .vbyte 8, .main # @main ; BIT64-NEXT: .vbyte 8, TOC[TC0] ; BIT64-NEXT: .vbyte 8, 0 -; COMMON-NEXT: .csect [PR] +; COMMON-NEXT: .csect ..text..[PR] ; COMMON-NEXT: .main: ; COMMON: .csect .data[RW] diff --git a/llvm/test/CodeGen/PowerPC/aix-func-align.ll b/llvm/test/CodeGen/PowerPC/aix-func-align.ll index 22b39a5e1e42..0e4564aa9e56 100644 --- a/llvm/test/CodeGen/PowerPC/aix-func-align.ll +++ b/llvm/test/CodeGen/PowerPC/aix-func-align.ll @@ -23,10 +23,10 @@ entry: ret i32 0 } -; CHECK: .csect [PR],6 +; CHECK: .csect ..text..[PR],6 ; CHECK-NEXT: .foo: -; CHECK: .csect [PR],6 +; CHECK: .csect ..text..[PR],6 ; CHECK-NEXT: .bar: ; SYMS: Symbol {{[{][[:space:]] *}}Index: [[#INDX:]]{{[[:space:]] *Name: $}} diff --git a/llvm/test/CodeGen/PowerPC/aix-personality-alias.ll b/llvm/test/CodeGen/PowerPC/aix-personality-alias.ll index 6e07d276dc8b..fd4b4103d2f8 100644 --- a/llvm/test/CodeGen/PowerPC/aix-personality-alias.ll +++ b/llvm/test/CodeGen/PowerPC/aix-personality-alias.ll @@ -56,7 +56,7 @@ declare void @_Z3barv() ; SYM64: .vbyte 8, .__gxx_personality_v0 ; SYM64: .vbyte 8, TOC[TC0] ; SYM64: .vbyte 8, 0 -; SYM: .csect [PR],5 +; SYM: .csect ..text..[PR],5 ; SYM: .__gxx_personality_v0: ; SYM: .__xlcxx_personality_v1: ; SYM: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/PowerPC/aix-weak.ll b/llvm/test/CodeGen/PowerPC/aix-weak.ll index bc098b83e372..84ef83a9b966 100644 --- a/llvm/test/CodeGen/PowerPC/aix-weak.ll +++ b/llvm/test/CodeGen/PowerPC/aix-weak.ll @@ -50,7 +50,7 @@ entry: ; BIT64-NEXT: .vbyte 8, .foo_weak # @foo_weak ; BIT64-NEXT: .vbyte 8, TOC[TC0] ; BIT64-NEXT: .vbyte 8, 0 -; COMMON-NEXT: .csect [PR] +; COMMON-NEXT: .csect ..text..[PR] ; COMMON-NEXT: .foo_weak: ; COMMON: .weak foo_ref_weak[DS] # -- Begin function foo_ref_weak @@ -63,7 +63,7 @@ entry: ; BIT64-NEXT: .vbyte 8, .foo_ref_weak # @foo_ref_weak ; BIT64-NEXT: .vbyte 8, TOC[TC0] ; BIT64-NEXT: .vbyte 8, 0 -; COMMON-NEXT: .csect [PR] +; COMMON-NEXT: .csect ..text..[PR] ; COMMON-NEXT: .foo_ref_weak: ; COMMON: .globl main[DS] # -- Begin function main @@ -76,7 +76,7 @@ entry: ; BIT64-NEXT: .vbyte 8, .main # @main ; BIT64-NEXT: .vbyte 8, TOC[TC0] ; BIT64-NEXT: .vbyte 8, 0 -; COMMON-NEXT: .csect [PR] +; COMMON-NEXT: .csect ..text..[PR] ; COMMON-NEXT: .main: ; COMMON: .csect .data[RW] diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll index e84f0b138d25..58958e399cb0 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll @@ -46,7 +46,7 @@ ; CHECK-NOT: .toc ; CHECK: .file -; CHECK-NEXT: .csect [PR],5 +; CHECK-NEXT: .csect ..text..[PR],5 ; CHECK: .csect .data[RW],5 ; CHECK-NEXT: .globl ivar diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll index 2600fac01425..a5056d407b76 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll @@ -50,6 +50,8 @@ entry: ret void } +; ASM: .csect ..text..[PR],5 +; ASM-NEXT: .rename ..text..[PR],"" ; ASM: .csect .foo[PR],5 ; ASM-NEXT: .globl foo[DS] # -- Begin function foo ; ASM-NEXT: .globl .foo[PR] diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll index 6fe40fedcdfd..494078010fd0 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll @@ -54,7 +54,7 @@ declare i32 @"f\40o"(...) ; ASM-NEXT: .vbyte 4, ._Renamed..24f_o # @"f$o" ; ASM-NEXT: .vbyte 4, TOC[TC0] ; ASM-NEXT: .vbyte 4, 0 -; ASM-NEXT: .csect [PR],5 +; ASM-NEXT: .csect ..text..[PR],5 ; ASM-NEXT: ._Renamed..24f_o: ; ASM: bl ._Renamed..40f_o[PR] ; ASM-NEXT: nop @@ -67,7 +67,7 @@ declare i32 @"f\40o"(...) ; ASM-NEXT: .vbyte 4, ._Renamed..26f_o # @"f&o" ; ASM-NEXT: .vbyte 4, TOC[TC0] ; ASM-NEXT: .vbyte 4, 0 -; ASM-NEXT: .csect [PR],5 +; ASM-NEXT: .csect ..text..[PR],5 ; ASM-NEXT: ._Renamed..26f_o: ; ASM: bl ._Renamed..24f_o ; ASM: .globl _Renamed..265ff__o[DS] # -- Begin function f&_o @@ -79,7 +79,7 @@ declare i32 @"f\40o"(...) ; ASM-NEXT: .vbyte 4, ._Renamed..265ff__o # @"f&_o" ; ASM-NEXT: .vbyte 4, TOC[TC0] ; ASM-NEXT: .vbyte 4, 0 -; ASM-NEXT: .csect [PR],5 +; ASM-NEXT: .csect ..text..[PR],5 ; ASM-NEXT: ._Renamed..265ff__o: ; ASM: .csect .data[RW],2 ; ASM-NEXT: .globl _Renamed..60f_o diff --git a/llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll b/llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll index 82a50d6ac174..33356e922fba 100644 --- a/llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll +++ b/llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll @@ -460,13 +460,13 @@ define zeroext i32 @test1(i64 %0, ptr %1) { %23 = phi i64 [ 0, %20 ], [ %107, %22 ] %24 = mul i64 %23, 400000 %25 = getelementptr i64, ptr %3, i64 %24 - %26 = or i64 %23, 1 + %26 = or disjoint i64 %23, 1 %27 = mul i64 %26, 400000 %28 = getelementptr i64, ptr %3, i64 %27 - %29 = or i64 %23, 2 + %29 = or disjoint i64 %23, 2 %30 = mul i64 %29, 400000 %31 = getelementptr i64, ptr %3, i64 %30 - %32 = or i64 %23, 3 + %32 = or disjoint i64 %23, 3 %33 = mul i64 %32, 400000 %34 = getelementptr i64, ptr %3, i64 %33 %35 = mul i64 %23, 400000 diff --git a/llvm/test/CodeGen/PowerPC/test_func_desc.ll b/llvm/test/CodeGen/PowerPC/test_func_desc.ll index d4bc83acfbd1..f909e36067ce 100644 --- a/llvm/test/CodeGen/PowerPC/test_func_desc.ll +++ b/llvm/test/CodeGen/PowerPC/test_func_desc.ll @@ -37,7 +37,7 @@ entry: ; 64BIT-NEXT: .vbyte 8, .foo ; 64BIT-NEXT: .vbyte 8, TOC[TC0] ; 64BIT-NEXT: .vbyte 8, 0 -; CHECK-NEXT: .csect [PR],5 +; CHECK-NEXT: .csect ..text..[PR],5 ; CHECK-LABEL: .foo: ; CHECK: .globl main[DS] @@ -50,7 +50,7 @@ entry: ; 64BIT-NEXT: .vbyte 8, .main ; 64BIT-NEXT: .vbyte 8, TOC[TC0] ; 64BIT-NEXT: .vbyte 8, 0 -; CHECK-NEXT: .csect [PR],5 +; CHECK-NEXT: .csect ..text..[PR],5 ; CHECK-LABEL: .main: ; CHECK: bl .foo ; CHECK: bl .extern_foo @@ -66,7 +66,7 @@ entry: ; 64BIT-NEXT: .vbyte 8, .static_foo ; 64BIT-NEXT: .vbyte 8, TOC[TC0] ; 64BIT-NEXT: .vbyte 8, 0 -; CHECK-NEXT: .csect [PR],5 +; CHECK-NEXT: .csect ..text..[PR],5 ; CHECK-LABEL: .static_foo: ; CHECK-NOT: .csect extern_foo diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv32.mir new file mode 100644 index 000000000000..f1f570f08ae4 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv32.mir @@ -0,0 +1,94 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: rotl_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ROL:%[0-9]+]]:gpr = ROL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ROL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ROTL %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: rotr_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ROR:%[0-9]+]]:gpr = ROR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ROR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ROTR %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: rotl_imm_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotl_imm_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 27 + ; CHECK-NEXT: $x10 = COPY [[RORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 5 + %2:gprb(s32) = G_ROTL %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: rotr_imm_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotr_imm_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 5 + ; CHECK-NEXT: $x10 = COPY [[RORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 5 + %2:gprb(s32) = G_ROTR %0, %1(s32) + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir new file mode 100644 index 000000000000..2210b8887041 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir @@ -0,0 +1,206 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: rotl_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY1]], 32 + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SLLI]], 32 + ; CHECK-NEXT: [[ROLW:%[0-9]+]]:gpr = ROLW [[COPY]], [[SRLI]] + ; CHECK-NEXT: $x10 = COPY [[ROLW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s32) = G_TRUNC %0(s64) + %2:gprb(s64) = COPY $x11 + %7:gprb(s64) = G_CONSTANT i64 4294967295 + %6:gprb(s64) = G_AND %2, %7 + %4:gprb(s32) = G_ROTL %1, %6(s64) + %5:gprb(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: rotl_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotl_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ROL:%[0-9]+]]:gpr = ROL [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ROL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ROTL %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_i32 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i32 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY1]], 32 + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SLLI]], 32 + ; CHECK-NEXT: [[RORW:%[0-9]+]]:gpr = RORW [[COPY]], [[SRLI]] + ; CHECK-NEXT: $x10 = COPY [[RORW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s32) = G_TRUNC %0(s64) + %2:gprb(s64) = COPY $x11 + %7:gprb(s64) = G_CONSTANT i64 4294967295 + %6:gprb(s64) = G_AND %2, %7 + %4:gprb(s32) = G_ROTR %1, %6(s64) + %5:gprb(s64) = G_ANYEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_i64 +legalized: true +regBankSelected: true +body: | + bb.0: + liveins: $x10, $x11 + + ; CHECK-LABEL: name: rotr_i64 + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[ROR:%[0-9]+]]:gpr = ROR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[ROR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ROTR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotl_imm_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotl_imm_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORIW:%[0-9]+]]:gpr = RORIW [[COPY]], 17 + ; CHECK-NEXT: $x10 = COPY [[RORIW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s32) = G_TRUNC %0(s64) + %2:gprb(s64) = G_CONSTANT i64 15 + %3:gprb(s32) = G_ROTL %1, %2(s64) + %4:gprb(s64) = G_ANYEXT %3(s32) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: rotl_imm_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotl_imm_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 31 + ; CHECK-NEXT: $x10 = COPY [[RORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 33 + %2:gprb(s64) = G_ROTL %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_imm_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotr_imm_i32 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORIW:%[0-9]+]]:gpr = RORIW [[COPY]], 15 + ; CHECK-NEXT: $x10 = COPY [[RORIW]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s32) = G_TRUNC %0(s64) + %2:gprb(s64) = G_CONSTANT i64 15 + %3:gprb(s32) = G_ROTR %1, %2(s64) + %4:gprb(s64) = G_ANYEXT %3(s32) + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: rotr_imm_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: rotr_imm_i64 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 33 + ; CHECK-NEXT: $x10 = COPY [[RORI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 33 + %2:gprb(s64) = G_ROTR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll index ecfccc48bb34..020f17107699 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/lower-args-vararg.ll @@ -10,27 +10,29 @@ define void @va1arg(ptr %a, ...) { ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 - ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 - ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1) + ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 - ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 - ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX1]](p0) :: (store (s32), align 8) + ; RV32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4) + ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32) ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 - ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 - ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX2]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8) + ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32) ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 - ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX3]](p0) :: (store (s32), align 16) + ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12) + ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32) ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 - ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX4]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16) + ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32) ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 - ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX5]](p0) :: (store (s32), align 8) + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20) + ; RV32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32) ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 - ; RV32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX6]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24) + ; RV32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32) ; RV32-NEXT: PseudoRET ; ; RV64-LABEL: name: va1arg @@ -38,27 +40,29 @@ define void @va1arg(ptr %a, ...) { ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 - ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1) + ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 - ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 - ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX1]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8) + ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64) ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 - ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 - ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX2]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16) + ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 - ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX3]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24) + ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64) ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 - ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX4]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32) + ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64) ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 - ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX5]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40) + ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64) ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 - ; RV64-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX6]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48) + ; RV64-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64) ; RV64-NEXT: PseudoRET ret void } @@ -70,24 +74,26 @@ define void @va2arg(ptr %a, ptr %b, ...) { ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 - ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 - ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX]](p0) :: (store (s32), align 8) + ; RV32-NEXT: G_STORE [[COPY2]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.0, align 8) + ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 - ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 - ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX1]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.0 + 4) + ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32) ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 - ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX2]](p0) :: (store (s32), align 16) + ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.0 + 8, align 8) + ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32) ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 - ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX3]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.0 + 12) + ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32) ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 - ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX4]](p0) :: (store (s32), align 8) + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.0 + 16, align 8) + ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32) ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 - ; RV32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX5]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.0 + 20) + ; RV32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32) ; RV32-NEXT: PseudoRET ; ; RV64-LABEL: name: va2arg @@ -96,24 +102,26 @@ define void @va2arg(ptr %a, ptr %b, ...) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 - ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 - ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.0, align 16) + ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 - ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 - ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX1]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.0 + 8) + ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64) ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 - ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX2]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.0 + 16, align 16) + ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 - ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX3]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.0 + 24) + ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64) ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 - ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX4]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.0 + 32, align 16) + ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64) ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 - ; RV64-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX5]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.0 + 40) + ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64) ; RV64-NEXT: PseudoRET ret void } @@ -126,21 +134,23 @@ define void @va3arg(ptr %a, ptr %b, ptr %c, ...) { ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 - ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 - ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1) + ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 - ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX1]](p0) :: (store (s32), align 16) + ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4) + ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32) ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 - ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX2]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8) + ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32) ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 - ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX3]](p0) :: (store (s32), align 8) + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12) + ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32) ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 - ; RV32-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX4]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16) + ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32) ; RV32-NEXT: PseudoRET ; ; RV64-LABEL: name: va3arg @@ -150,21 +160,23 @@ define void @va3arg(ptr %a, ptr %b, ptr %c, ...) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13 - ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 - ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY3]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1) + ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 - ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX1]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8) + ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64) ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 - ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX2]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16) + ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 - ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX3]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24) + ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64) ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 - ; RV64-NEXT: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX4]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32) + ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64) ; RV64-NEXT: PseudoRET ret void } @@ -178,18 +190,20 @@ define void @va4arg(ptr %a, ptr %b, ptr %c, ptr %d, ...) { ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 - ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX]](p0) :: (store (s32), align 16) + ; RV32-NEXT: G_STORE [[COPY4]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.0, align 16) + ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 - ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX1]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.0 + 4) + ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32) ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 - ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX2]](p0) :: (store (s32), align 8) + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.0 + 8, align 8) + ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32) ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 - ; RV32-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX3]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.0 + 12) + ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32) ; RV32-NEXT: PseudoRET ; ; RV64-LABEL: name: va4arg @@ -200,18 +214,20 @@ define void @va4arg(ptr %a, ptr %b, ptr %c, ptr %d, ...) { ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14 - ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 - ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY4]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.0, align 16) + ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 - ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX1]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.0 + 8) + ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64) ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 - ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX2]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.0 + 16, align 16) + ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 - ; RV64-NEXT: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX3]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.0 + 24) + ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64) ; RV64-NEXT: PseudoRET ret void } @@ -226,15 +242,17 @@ define void @va5arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ...) { ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 - ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY5]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1) + ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 - ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX1]](p0) :: (store (s32), align 8) + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4) + ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32) ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 - ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX2]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8) + ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32) ; RV32-NEXT: PseudoRET ; ; RV64-LABEL: name: va5arg @@ -246,15 +264,17 @@ define void @va5arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ...) { ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x12 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15 - ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 - ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY5]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1) + ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 - ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX1]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8) + ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64) ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 - ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX2]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16) + ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; RV64-NEXT: PseudoRET ret void } @@ -270,12 +290,14 @@ define void @va6arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ...) { ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 - ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX]](p0) :: (store (s32), align 8) + ; RV32-NEXT: G_STORE [[COPY6]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.0, align 8) + ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 - ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX1]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.0 + 4) + ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32) ; RV32-NEXT: PseudoRET ; ; RV64-LABEL: name: va6arg @@ -288,12 +310,14 @@ define void @va6arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ...) { ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x13 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16 - ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX]](p0) :: (store (s64), align 16) + ; RV64-NEXT: G_STORE [[COPY6]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.0, align 16) + ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 - ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX1]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.0 + 8) + ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64) ; RV64-NEXT: PseudoRET ret void } @@ -310,9 +334,11 @@ define void @va7arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ptr %g, ...) ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(p0) = COPY $x16 + ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 - ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX]](p0) :: (store (s32)) + ; RV32-NEXT: G_STORE [[COPY7]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1) + ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32) ; RV32-NEXT: PseudoRET ; ; RV64-LABEL: name: va7arg @@ -326,9 +352,11 @@ define void @va7arg(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ptr %g, ...) ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x14 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x15 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(p0) = COPY $x16 + ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17 - ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX]](p0) :: (store (s64)) + ; RV64-NEXT: G_STORE [[COPY7]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1) + ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64) ; RV64-NEXT: PseudoRET ret void } diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir index 2e2a5b062ec6..4395481328b6 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ -# RUN: | FileCheck %s +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I +# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB --- name: rotl_i8 @@ -74,21 +76,30 @@ body: | bb.1: liveins: $x10, $x11 - ; CHECK-LABEL: name: rotl_i32 - ; CHECK: liveins: $x10, $x11 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 - ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND1]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]] - ; CHECK-NEXT: $x10 = COPY [[OR]](s32) - ; CHECK-NEXT: PseudoRET implicit $x10 + ; RV32I-LABEL: name: rotl_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32) + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]] + ; RV32I-NEXT: $x10 = COPY [[OR]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: rotl_i32 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[COPY1]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[ROTL]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 %0:_(s32) = COPY $x10 %1:_(s32) = COPY $x11 %2:_(s32) = G_ROTL %0, %1(s32) @@ -233,21 +244,30 @@ body: | bb.1: liveins: $x10, $x11 - ; CHECK-LABEL: name: rotr_i32 - ; CHECK: liveins: $x10, $x11 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 - ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] - ; CHECK-NEXT: $x10 = COPY [[OR]](s32) - ; CHECK-NEXT: PseudoRET implicit $x10 + ; RV32I-LABEL: name: rotr_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]] + ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] + ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND]](s32) + ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32) + ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; RV32I-NEXT: $x10 = COPY [[OR]](s32) + ; RV32I-NEXT: PseudoRET implicit $x10 + ; + ; RV32ZBB-LABEL: name: rotr_i32 + ; RV32ZBB: liveins: $x10, $x11 + ; RV32ZBB-NEXT: {{ $}} + ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[COPY1]](s32) + ; RV32ZBB-NEXT: $x10 = COPY [[ROTR]](s32) + ; RV32ZBB-NEXT: PseudoRET implicit $x10 %0:_(s32) = COPY $x10 %1:_(s32) = COPY $x11 %2:_(s32) = G_ROTR %0, %1(s32) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir index fbc1415dade3..91e6eeaee576 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ -# RUN: | FileCheck %s +# RUN: | FileCheck %s --check-prefixes=CHECK,RV64I +# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB --- name: rotl_i8 @@ -84,24 +86,37 @@ body: | bb.1: liveins: $x10, $x11 - ; CHECK-LABEL: name: rotl_i32 - ; CHECK: liveins: $x10, $x11 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 - ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC1]] - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]] - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[AND]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[AND1]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]] - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) - ; CHECK-NEXT: PseudoRET implicit $x10 + ; RV64I-LABEL: name: rotl_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC1]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]] + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[AND]](s32) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[AND1]](s32) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: rotl_i32 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64ZBB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[TRUNC]], [[AND]](s64) + ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTL]](s32) + ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 %0:_(s32) = G_TRUNC %2(s64) %3:_(s64) = COPY $x11 @@ -118,21 +133,30 @@ body: | bb.1: liveins: $x10, $x11 - ; CHECK-LABEL: name: rotl_i64 - ; CHECK: liveins: $x10, $x11 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 - ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND1]](s64) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]] - ; CHECK-NEXT: $x10 = COPY [[OR]](s64) - ; CHECK-NEXT: PseudoRET implicit $x10 + ; RV64I-LABEL: name: rotl_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND1]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]] + ; RV64I-NEXT: $x10 = COPY [[OR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: rotl_i64 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[COPY]], [[COPY1]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[ROTL]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 %2:_(s64) = G_ROTL %0, %1(s64) @@ -222,24 +246,37 @@ body: | bb.1: liveins: $x10, $x11 - ; CHECK-LABEL: name: rotr_i32 - ; CHECK: liveins: $x10, $x11 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 - ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC1]] - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]] - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[AND]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[AND1]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) - ; CHECK-NEXT: PseudoRET implicit $x10 + ; RV64I-LABEL: name: rotr_i32 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC1]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[AND]](s32) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[AND1]](s32) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32) + ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: rotr_i32 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; RV64ZBB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[TRUNC]], [[AND]](s64) + ; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTR]](s32) + ; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 %0:_(s32) = G_TRUNC %2(s64) %3:_(s64) = COPY $x11 @@ -256,21 +293,30 @@ body: | bb.1: liveins: $x10, $x11 - ; CHECK-LABEL: name: rotr_i64 - ; CHECK: liveins: $x10, $x11 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 - ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s64) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] - ; CHECK-NEXT: $x10 = COPY [[OR]](s64) - ; CHECK-NEXT: PseudoRET implicit $x10 + ; RV64I-LABEL: name: rotr_i64 + ; RV64I: liveins: $x10, $x11 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63 + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s64) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; RV64I-NEXT: $x10 = COPY [[OR]](s64) + ; RV64I-NEXT: PseudoRET implicit $x10 + ; + ; RV64ZBB-LABEL: name: rotr_i64 + ; RV64ZBB: liveins: $x10, $x11 + ; RV64ZBB-NEXT: {{ $}} + ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; RV64ZBB-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[COPY]], [[COPY1]](s64) + ; RV64ZBB-NEXT: $x10 = COPY [[ROTR]](s64) + ; RV64ZBB-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 %2:_(s64) = G_ROTR %0, %1(s64) diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll index 0e4702d13a8c..649234efaad9 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll @@ -364,8 +364,8 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-FPELIM-NEXT: sw zero, 16(sp) ; RV32I-FPELIM-NEXT: sw zero, 52(sp) ; RV32I-FPELIM-NEXT: sw zero, 48(sp) -; RV32I-FPELIM-NEXT: sw zero, 44(sp) -; RV32I-FPELIM-NEXT: li t0, 8 +; RV32I-FPELIM-NEXT: li a0, 8 +; RV32I-FPELIM-NEXT: sw a0, 40(sp) ; RV32I-FPELIM-NEXT: li a0, 1 ; RV32I-FPELIM-NEXT: li a1, 2 ; RV32I-FPELIM-NEXT: li a2, 3 @@ -374,7 +374,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-FPELIM-NEXT: li a5, 6 ; RV32I-FPELIM-NEXT: li a6, 7 ; RV32I-FPELIM-NEXT: addi a7, sp, 40 -; RV32I-FPELIM-NEXT: sw t0, 40(sp) +; RV32I-FPELIM-NEXT: sw zero, 44(sp) ; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs@plt ; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-FPELIM-NEXT: addi sp, sp, 64 @@ -397,8 +397,8 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-WITHFP-NEXT: sw zero, -48(s0) ; RV32I-WITHFP-NEXT: sw zero, -12(s0) ; RV32I-WITHFP-NEXT: sw zero, -16(s0) -; RV32I-WITHFP-NEXT: sw zero, -20(s0) -; RV32I-WITHFP-NEXT: li t0, 8 +; RV32I-WITHFP-NEXT: li a0, 8 +; RV32I-WITHFP-NEXT: sw a0, -24(s0) ; RV32I-WITHFP-NEXT: li a0, 1 ; RV32I-WITHFP-NEXT: li a1, 2 ; RV32I-WITHFP-NEXT: li a2, 3 @@ -407,7 +407,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-WITHFP-NEXT: li a5, 6 ; RV32I-WITHFP-NEXT: li a6, 7 ; RV32I-WITHFP-NEXT: addi a7, s0, -24 -; RV32I-WITHFP-NEXT: sw t0, -24(s0) +; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs@plt ; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll index adf3630d2a0c..c2690d15665e 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll @@ -140,11 +140,11 @@ define i64 @caller_large_scalars() nounwind { ; RV64I-NEXT: sd a0, 0(sp) ; RV64I-NEXT: sd zero, 56(sp) ; RV64I-NEXT: sd zero, 48(sp) -; RV64I-NEXT: sd zero, 40(sp) -; RV64I-NEXT: li a2, 1 +; RV64I-NEXT: li a0, 1 +; RV64I-NEXT: sd a0, 32(sp) ; RV64I-NEXT: addi a0, sp, 32 ; RV64I-NEXT: mv a1, sp -; RV64I-NEXT: sd a2, 32(sp) +; RV64I-NEXT: sd zero, 40(sp) ; RV64I-NEXT: call callee_large_scalars@plt ; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 80 @@ -199,8 +199,8 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind { ; RV64I-NEXT: sd a0, 16(sp) ; RV64I-NEXT: sd zero, 72(sp) ; RV64I-NEXT: sd zero, 64(sp) -; RV64I-NEXT: sd zero, 56(sp) -; RV64I-NEXT: li t0, 8 +; RV64I-NEXT: li a0, 8 +; RV64I-NEXT: sd a0, 48(sp) ; RV64I-NEXT: li a0, 1 ; RV64I-NEXT: li a1, 2 ; RV64I-NEXT: li a2, 3 @@ -209,7 +209,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind { ; RV64I-NEXT: li a5, 6 ; RV64I-NEXT: li a6, 7 ; RV64I-NEXT: addi a7, sp, 48 -; RV64I-NEXT: sd t0, 48(sp) +; RV64I-NEXT: sd zero, 56(sp) ; RV64I-NEXT: call callee_large_scalars_exhausted_regs@plt ; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 96 diff --git a/llvm/test/CodeGen/RISCV/push-pop-popret.ll b/llvm/test/CodeGen/RISCV/push-pop-popret.ll index 776944b17763..9ff4235746ca 100644 --- a/llvm/test/CodeGen/RISCV/push-pop-popret.ll +++ b/llvm/test/CodeGen/RISCV/push-pop-popret.ll @@ -1015,24 +1015,16 @@ define i32 @varargs(ptr %fmt, ...) nounwind { ; RV64IZCMP-LABEL: varargs: ; RV64IZCMP: # %bb.0: ; RV64IZCMP-NEXT: addi sp, sp, -80 +; RV64IZCMP-NEXT: sd a1, 24(sp) ; RV64IZCMP-NEXT: sd a7, 72(sp) ; RV64IZCMP-NEXT: sd a6, 64(sp) +; RV64IZCMP-NEXT: addi a0, sp, 28 +; RV64IZCMP-NEXT: sd a0, 8(sp) +; RV64IZCMP-NEXT: lw a0, 24(sp) ; RV64IZCMP-NEXT: sd a5, 56(sp) ; RV64IZCMP-NEXT: sd a4, 48(sp) ; RV64IZCMP-NEXT: sd a3, 40(sp) ; RV64IZCMP-NEXT: sd a2, 32(sp) -; RV64IZCMP-NEXT: sd a1, 24(sp) -; RV64IZCMP-NEXT: addi a0, sp, 24 -; RV64IZCMP-NEXT: sd a0, 8(sp) -; RV64IZCMP-NEXT: lwu a0, 12(sp) -; RV64IZCMP-NEXT: lwu a1, 8(sp) -; RV64IZCMP-NEXT: slli a0, a0, 32 -; RV64IZCMP-NEXT: or a0, a0, a1 -; RV64IZCMP-NEXT: addi a1, a0, 4 -; RV64IZCMP-NEXT: sw a1, 8(sp) -; RV64IZCMP-NEXT: srli a1, a1, 32 -; RV64IZCMP-NEXT: sw a1, 12(sp) -; RV64IZCMP-NEXT: lw a0, 0(a0) ; RV64IZCMP-NEXT: addi sp, sp, 80 ; RV64IZCMP-NEXT: ret ; @@ -1055,24 +1047,16 @@ define i32 @varargs(ptr %fmt, ...) nounwind { ; RV64IZCMP-SR-LABEL: varargs: ; RV64IZCMP-SR: # %bb.0: ; RV64IZCMP-SR-NEXT: addi sp, sp, -80 +; RV64IZCMP-SR-NEXT: sd a1, 24(sp) ; RV64IZCMP-SR-NEXT: sd a7, 72(sp) ; RV64IZCMP-SR-NEXT: sd a6, 64(sp) +; RV64IZCMP-SR-NEXT: addi a0, sp, 28 +; RV64IZCMP-SR-NEXT: sd a0, 8(sp) +; RV64IZCMP-SR-NEXT: lw a0, 24(sp) ; RV64IZCMP-SR-NEXT: sd a5, 56(sp) ; RV64IZCMP-SR-NEXT: sd a4, 48(sp) ; RV64IZCMP-SR-NEXT: sd a3, 40(sp) ; RV64IZCMP-SR-NEXT: sd a2, 32(sp) -; RV64IZCMP-SR-NEXT: sd a1, 24(sp) -; RV64IZCMP-SR-NEXT: addi a0, sp, 24 -; RV64IZCMP-SR-NEXT: sd a0, 8(sp) -; RV64IZCMP-SR-NEXT: lwu a0, 12(sp) -; RV64IZCMP-SR-NEXT: lwu a1, 8(sp) -; RV64IZCMP-SR-NEXT: slli a0, a0, 32 -; RV64IZCMP-SR-NEXT: or a0, a0, a1 -; RV64IZCMP-SR-NEXT: addi a1, a0, 4 -; RV64IZCMP-SR-NEXT: sw a1, 8(sp) -; RV64IZCMP-SR-NEXT: srli a1, a1, 32 -; RV64IZCMP-SR-NEXT: sw a1, 12(sp) -; RV64IZCMP-SR-NEXT: lw a0, 0(a0) ; RV64IZCMP-SR-NEXT: addi sp, sp, 80 ; RV64IZCMP-SR-NEXT: ret ; @@ -1095,32 +1079,24 @@ define i32 @varargs(ptr %fmt, ...) nounwind { ; RV64I-LABEL: varargs: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -80 +; RV64I-NEXT: sd a1, 24(sp) ; RV64I-NEXT: sd a7, 72(sp) ; RV64I-NEXT: sd a6, 64(sp) +; RV64I-NEXT: addi a0, sp, 28 +; RV64I-NEXT: sd a0, 8(sp) +; RV64I-NEXT: lw a0, 24(sp) ; RV64I-NEXT: sd a5, 56(sp) ; RV64I-NEXT: sd a4, 48(sp) ; RV64I-NEXT: sd a3, 40(sp) ; RV64I-NEXT: sd a2, 32(sp) -; RV64I-NEXT: sd a1, 24(sp) -; RV64I-NEXT: addi a0, sp, 24 -; RV64I-NEXT: sd a0, 8(sp) -; RV64I-NEXT: lwu a0, 12(sp) -; RV64I-NEXT: lwu a1, 8(sp) -; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: addi a1, a0, 4 -; RV64I-NEXT: sw a1, 8(sp) -; RV64I-NEXT: srli a1, a1, 32 -; RV64I-NEXT: sw a1, 12(sp) -; RV64I-NEXT: lw a0, 0(a0) ; RV64I-NEXT: addi sp, sp, 80 ; RV64I-NEXT: ret - %va = alloca ptr, align 4 + %va = alloca ptr call void @llvm.va_start(ptr %va) - %argp.cur = load ptr, ptr %va, align 4 + %argp.cur = load ptr, ptr %va %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4 - store ptr %argp.next, ptr %va, align 4 - %1 = load i32, ptr %argp.cur, align 4 + store ptr %argp.next, ptr %va + %1 = load i32, ptr %argp.cur call void @llvm.va_end(ptr %va) ret i32 %1 } diff --git a/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll b/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll new file mode 100644 index 000000000000..bb65f408c77a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll @@ -0,0 +1,119 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I %s + +@PL_reg_match_utf8 = external global i8, align 1 + +declare signext i32 @test1(i8 signext) + +declare signext i32 @test2(i8 signext) + +declare signext i32 @test3(i8 signext) + +define signext i32 @test() nounwind { +; RV64I-LABEL: test: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: lui a0, %hi(PL_reg_match_utf8) +; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(a0) +; RV64I-NEXT: beqz s0, .LBB0_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: call test1@plt +; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: call test2@plt +; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: call test3@plt +; RV64I-NEXT: j .LBB0_3 +; RV64I-NEXT: .LBB0_2: +; RV64I-NEXT: li a0, 0 +; RV64I-NEXT: call test2@plt +; RV64I-NEXT: .LBB0_3: +; RV64I-NEXT: li a0, 0 +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret + %1 = load i8, ptr @PL_reg_match_utf8, align 1 + %2 = icmp eq i8 %1, 0 + br i1 %2, label %7, label %3 + +3: + %4 = tail call signext i32 @test1(i8 signext %1) + %5 = tail call signext i32 @test2(i8 signext %1) + %6 = tail call signext i32 @test3(i8 signext %1) + br label %9 + +7: + %8 = tail call signext i32 @test2(i8 signext 0) + br label %9 + +9: + ret i32 0 +} + + +define signext i32 @test_loop() nounwind { +; RV64I-LABEL: test_loop: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -32 +; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: li s1, -16 +; RV64I-NEXT: lui s2, %hi(PL_reg_match_utf8) +; RV64I-NEXT: j .LBB1_2 +; RV64I-NEXT: .LBB1_1: # in Loop: Header=BB1_2 Depth=1 +; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: call test2@plt +; RV64I-NEXT: addiw s1, s1, 1 +; RV64I-NEXT: beqz s1, .LBB1_4 +; RV64I-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=1 +; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(s2) +; RV64I-NEXT: beqz s0, .LBB1_1 +; RV64I-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=1 +; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: call test1@plt +; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: call test2@plt +; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: call test3@plt +; RV64I-NEXT: addiw s1, s1, 1 +; RV64I-NEXT: bnez s1, .LBB1_2 +; RV64I-NEXT: .LBB1_4: +; RV64I-NEXT: li a0, 0 +; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 32 +; RV64I-NEXT: ret + br label %1 + +1: + %2 = phi i32 [ 16, %0 ], [ %12, %11 ] + %3 = load i8, ptr @PL_reg_match_utf8, align 1 + %4 = icmp eq i8 %3, 0 + br i1 %4, label %9, label %5 + +5: + %6 = tail call signext i32 @test1(i8 signext %3) + %7 = tail call signext i32 @test2(i8 signext %3) + %8 = tail call signext i32 @test3(i8 signext %3) + br label %11 + +9: + %10 = tail call signext i32 @test2(i8 signext %3) + br label %11 + +11: + %12 = add nsw i32 %2, -1 + %13 = icmp eq i32 %12, 0 + br i1 %13, label %14, label %1 + +14: + ret i32 0 +} diff --git a/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll b/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll index 78f2ca8f128d..e73249739f35 100644 --- a/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll +++ b/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll @@ -118,7 +118,7 @@ for.body: ; preds = %for.body, %for.body %2 = load i32, ptr %arrayidx, align 4 %add = add nsw i32 %2, 4 store i32 %add, ptr %arrayidx, align 4 - %indvars.iv.next = or i64 %indvars.iv, 1 + %indvars.iv.next = or disjoint i64 %indvars.iv, 1 %arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next %3 = load i32, ptr %arrayidx.1, align 4 %add.1 = add nsw i32 %3, 4 diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll index a8a165e54929..407c782d3377 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll @@ -3,6 +3,8 @@ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s ; RUN: llc -mtriple=riscv32 -mattr=+v -mattr=+m -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s +; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-max=128 -O2 < %s \ +; RUN: | FileCheck --check-prefix=SPILL-O2-VLEN128 %s define @spill_zvlsseg_nxv1i32(ptr %base, i32 %vl) nounwind { ; SPILL-O0-LABEL: spill_zvlsseg_nxv1i32: @@ -56,6 +58,28 @@ define @spill_zvlsseg_nxv1i32(ptr %base, i32 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv1i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -32 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, mf2, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 16 +; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 16 +; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32( undef, undef, ptr %base, i32 %vl) call void asm sideeffect "", @@ -116,6 +140,28 @@ define @spill_zvlsseg_nxv2i32(ptr %base, i32 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv2i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -32 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m1, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 16 +; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 16 +; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32( undef, undef, ptr %base, i32 %vl) call void asm sideeffect "", @@ -179,6 +225,28 @@ define @spill_zvlsseg_nxv4i32(ptr %base, i32 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv4i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -64 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 32 +; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 32 +; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 64 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32( undef, undef, ptr %base, i32 %vl) call void asm sideeffect "", @@ -242,6 +310,28 @@ define @spill_zvlsseg_nxv8i32(ptr %base, i32 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv8i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -128 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m4, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 64 +; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs4r.v v12, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 64 +; SPILL-O2-VLEN128-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 128 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32( undef, undef, ptr %base, i32 %vl) call void asm sideeffect "", @@ -314,6 +404,32 @@ define @spill_zvlsseg3_nxv4i32(ptr %base, i32 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg3_nxv4i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -96 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg3e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 32 +; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 32 +; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 96 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32( undef, undef, undef, ptr %base, i32 %vl) call void asm sideeffect "", diff --git a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll index a3c0ed47e113..1c1544b4efa0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll @@ -3,6 +3,8 @@ ; RUN: | FileCheck --check-prefix=SPILL-O0 %s ; RUN: llc -mtriple=riscv64 -mattr=+v -mattr=+m -O2 < %s \ ; RUN: | FileCheck --check-prefix=SPILL-O2 %s +; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -O2 < %s \ +; RUN: | FileCheck --check-prefix=SPILL-O2-VLEN128 %s define @spill_zvlsseg_nxv1i32(ptr %base, i64 %vl) nounwind { ; SPILL-O0-LABEL: spill_zvlsseg_nxv1i32: @@ -56,6 +58,28 @@ define @spill_zvlsseg_nxv1i32(ptr %base, i64 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv1i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -32 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, mf2, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 16 +; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 16 +; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32( undef, undef, ptr %base, i64 %vl) call void asm sideeffect "", @@ -116,6 +140,28 @@ define @spill_zvlsseg_nxv2i32(ptr %base, i64 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv2i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -32 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m1, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 16 +; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 16 +; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32( undef, undef, ptr %base, i64 %vl) call void asm sideeffect "", @@ -179,6 +225,28 @@ define @spill_zvlsseg_nxv4i32(ptr %base, i64 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv4i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -64 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 32 +; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 32 +; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 64 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32( undef, undef, ptr %base, i64 %vl) call void asm sideeffect "", @@ -242,6 +310,28 @@ define @spill_zvlsseg_nxv8i32(ptr %base, i64 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv8i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -128 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m4, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 64 +; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs4r.v v12, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 64 +; SPILL-O2-VLEN128-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 128 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32( undef, undef, ptr %base, i64 %vl) call void asm sideeffect "", @@ -314,6 +404,32 @@ define @spill_zvlsseg3_nxv4i32(ptr %base, i64 %vl) nounwind { ; SPILL-O2-NEXT: add sp, sp, a0 ; SPILL-O2-NEXT: addi sp, sp, 16 ; SPILL-O2-NEXT: ret +; +; SPILL-O2-VLEN128-LABEL: spill_zvlsseg3_nxv4i32: +; SPILL-O2-VLEN128: # %bb.0: # %entry +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, -96 +; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; SPILL-O2-VLEN128-NEXT: vlseg3e32.v v8, (a0) +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 32 +; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill +; SPILL-O2-VLEN128-NEXT: #APP +; SPILL-O2-VLEN128-NEXT: #NO_APP +; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16 +; SPILL-O2-VLEN128-NEXT: li a1, 32 +; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: add a0, a0, a1 +; SPILL-O2-VLEN128-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 96 +; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16 +; SPILL-O2-VLEN128-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32( undef, undef, undef, ptr %base, i64 %vl) call void asm sideeffect "", diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll index 59aa1d9ae289..67d1bfac4d61 100644 --- a/llvm/test/CodeGen/RISCV/vararg.ll +++ b/llvm/test/CodeGen/RISCV/vararg.ll @@ -1,25 +1,25 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=ILP32-ILP32F-FPELIM %s -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all \ ; RUN: | FileCheck -check-prefix=ILP32-ILP32F-WITHFP %s -; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f \ -; RUN: -verify-machineinstrs < %s \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f \ +; RUN: -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s -; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \ -; RUN: -verify-machineinstrs < %s \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \ +; RUN: -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s -; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64f \ -; RUN: -verify-machineinstrs < %s \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d -target-abi lp64f \ +; RUN: -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s -; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \ -; RUN: -verify-machineinstrs < %s \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \ +; RUN: -verify-machineinstrs \ ; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s -; RUN: llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all < %s \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all \ ; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-WITHFP %s ; The same vararg calling convention is used for ilp32/ilp32f/ilp32d and for @@ -104,13 +104,13 @@ define i32 @va1(ptr %fmt, ...) { ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 28 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) +; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 28 -; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; @@ -127,13 +127,13 @@ define i32 @va1(ptr %fmt, ...) { ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 12 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 12 -; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 @@ -489,12 +489,12 @@ define i64 @va2(ptr %fmt, ...) nounwind { ; ILP32-ILP32F-FPELIM: # %bb.0: ; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, -48 ; ILP32-ILP32F-FPELIM-NEXT: sw a7, 44(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a5, 36(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a4, 32(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a3, 28(sp) -; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) -; ILP32-ILP32F-FPELIM-NEXT: sw a6, 40(sp) ; ILP32-ILP32F-FPELIM-NEXT: sw a2, 24(sp) +; ILP32-ILP32F-FPELIM-NEXT: sw a1, 20(sp) ; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 20 ; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp) ; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27 @@ -513,12 +513,12 @@ define i64 @va2(ptr %fmt, ...) nounwind { ; ILP32-ILP32F-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; ILP32-ILP32F-WITHFP-NEXT: addi s0, sp, 16 ; ILP32-ILP32F-WITHFP-NEXT: sw a7, 28(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a5, 20(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a4, 16(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a3, 12(s0) -; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) -; ILP32-ILP32F-WITHFP-NEXT: sw a6, 24(s0) ; ILP32-ILP32F-WITHFP-NEXT: sw a2, 8(s0) +; ILP32-ILP32F-WITHFP-NEXT: sw a1, 4(s0) ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 4 ; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0) ; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11 @@ -536,12 +536,12 @@ define i64 @va2(ptr %fmt, ...) nounwind { ; RV32D-ILP32-ILP32F-ILP32D-FPELIM: # %bb.0: ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, -48 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 44(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a5, 36(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a4, 32(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 28(sp) -; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) -; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 40(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 24(sp) +; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 20(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 20 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp) ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27 @@ -556,6 +556,7 @@ define i64 @va2(ptr %fmt, ...) nounwind { ; LP64-LP64F-LP64D-FPELIM-LABEL: va2: ; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -80 +; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 72(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 64(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 56(sp) @@ -563,17 +564,8 @@ define i64 @va2(ptr %fmt, ...) nounwind { ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24 -; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7 -; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 32 -; LP64-LP64F-LP64D-FPELIM-NEXT: srli a1, a1, 32 -; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 39 ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: srliw a0, a0, 3 -; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 3 -; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; @@ -583,6 +575,7 @@ define i64 @va2(ptr %fmt, ...) nounwind { ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 32 +; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) @@ -590,30 +583,22 @@ define i64 @va2(ptr %fmt, ...) nounwind { ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8 -; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7 -; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 32 -; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32 -; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 23 ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: srliw a0, a0, 3 -; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 3 -; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96 ; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca ptr call void @llvm.va_start(ptr %va) - %argp.cur = load i32, ptr %va, align 4 - %1 = add i32 %argp.cur, 7 - %2 = and i32 %1, -8 - %argp.cur.aligned = inttoptr i32 %1 to ptr + %argp.cur = load ptr, ptr %va + %ptrint = ptrtoint ptr %argp.cur to iXLen + %1 = add iXLen %ptrint, 7 + %2 = and iXLen %1, -8 + %argp.cur.aligned = inttoptr iXLen %1 to ptr %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8 - store ptr %argp.next, ptr %va, align 4 - %3 = inttoptr i32 %2 to ptr + store ptr %argp.next, ptr %va + %3 = inttoptr iXLen %2 to ptr %4 = load double, ptr %3, align 8 %5 = bitcast double %4 to i64 call void @llvm.va_end(ptr %va) @@ -884,19 +869,10 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind { ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 40(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 16 -; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7 -; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 32 -; LP64-LP64F-LP64D-FPELIM-NEXT: srli a2, a2, 32 -; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a2, 8 -; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 8(sp) -; LP64-LP64F-LP64D-FPELIM-NEXT: srliw a0, a0, 3 -; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a0, 3 -; LP64-LP64F-LP64D-FPELIM-NEXT: ld a0, 0(a0) -; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a0 +; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, sp, 31 +; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a2 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp) ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64 ; LP64-LP64F-LP64D-FPELIM-NEXT: ret ; @@ -911,32 +887,24 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind { ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0 -; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7 -; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 32 -; LP64-LP64F-LP64D-WITHFP-NEXT: srli a2, a2, 32 -; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, 8 -; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, -24(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: srliw a0, a0, 3 -; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a0, 3 -; LP64-LP64F-LP64D-WITHFP-NEXT: ld a0, 0(a0) -; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a0 +; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, s0, 15 +; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a2 +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -24(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 80 ; LP64-LP64F-LP64D-WITHFP-NEXT: ret %va = alloca ptr call void @llvm.va_start(ptr %va) - %argp.cur = load i32, ptr %va, align 4 - %1 = add i32 %argp.cur, 7 - %2 = and i32 %1, -8 - %argp.cur.aligned = inttoptr i32 %1 to ptr + %argp.cur = load ptr, ptr %va + %ptrint = ptrtoint ptr %argp.cur to iXLen + %1 = add iXLen %ptrint, 7 + %2 = and iXLen %1, -8 + %argp.cur.aligned = inttoptr iXLen %1 to ptr %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8 - store ptr %argp.next, ptr %va, align 4 - %3 = inttoptr i32 %2 to ptr + store ptr %argp.next, ptr %va + %3 = inttoptr iXLen %2 to ptr %4 = load double, ptr %3, align 8 call void @llvm.va_end(ptr %va) %5 = bitcast double %4 to i64 @@ -1805,18 +1773,6 @@ define i32 @va_large_stack(ptr %fmt, ...) { ; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 320(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414 -; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0 -; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 312(a0) -; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414 -; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0 -; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 304(a0) -; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414 -; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0 -; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 296(a0) -; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414 -; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0 -; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 288(a0) -; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414 ; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 284 ; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp) @@ -1824,6 +1780,18 @@ define i32 @va_large_stack(ptr %fmt, ...) { ; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0 ; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 280(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414 +; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 312(a1) +; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414 +; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 304(a1) +; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414 +; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 296(a1) +; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414 +; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1 +; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 288(a1) +; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414 ; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 336 ; LP64-LP64F-LP64D-FPELIM-NEXT: add sp, sp, a1 ; LP64-LP64F-LP64D-FPELIM-NEXT: ret @@ -1844,15 +1812,15 @@ define i32 @va_large_stack(ptr %fmt, ...) { ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a7, 56(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a6, 48(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) -; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 12 ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 24414 ; LP64-LP64F-LP64D-WITHFP-NEXT: sub a1, s0, a1 ; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -288(a1) ; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a5, 40(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0) +; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 24414 ; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -1680 ; LP64-LP64F-LP64D-WITHFP-NEXT: add sp, sp, a1 diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll index 1838b9297ff4..0e8f04468022 100644 --- a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll +++ b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll @@ -1,103 +1,511 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; Test i128 atomicrmw operations. ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s +; +; Test expansion of AtomicRMW instructions, which assume a natural alignment. +; Note that the multiple regmoves inside the CDSG loops hopefully will go away +; when the new i128 support is added. ; Check register exchange. -define i128 @f1(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f1: -; CHECK: brasl %r14, __sync_lock_test_and_set_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_xchg(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_xchg: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r12, %r15, 96(%r15) +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r14, 8(%r4) +; CHECK-NEXT: lg %r0, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: lgr %r1, %r14 +; CHECK-NEXT: .LBB0_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: lgr %r12, %r5 +; CHECK-NEXT: lgr %r13, %r4 +; CHECK-NEXT: cdsg %r12, %r0, 0(%r3) +; CHECK-NEXT: lgr %r4, %r13 +; CHECK-NEXT: lgr %r5, %r12 +; CHECK-NEXT: jl .LBB0_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r12, %r15, 96(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw xchg ptr %src, i128 %b seq_cst ret i128 %res } ; Check addition of a variable. -define i128 @f2(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f2: -; CHECK: brasl %r14, __sync_fetch_and_add_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_add(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_add: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB1_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: algrk %r13, %r4, %r0 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: alcgr %r5, %r1 +; CHECK-NEXT: lgr %r12, %r5 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB1_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw add ptr %src, i128 %b seq_cst ret i128 %res } ; Check subtraction of a variable. -define i128 @f3(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f3: -; CHECK: brasl %r14, __sync_fetch_and_sub_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_sub(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_sub: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB2_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: slgrk %r13, %r4, %r0 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: slbgr %r5, %r1 +; CHECK-NEXT: lgr %r12, %r5 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB2_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw sub ptr %src, i128 %b seq_cst ret i128 %res } ; Check AND of a variable. -define i128 @f4(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f4: -; CHECK: brasl %r14, __sync_fetch_and_and_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_and(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_and: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB3_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: ngrk %r12, %r5, %r1 +; CHECK-NEXT: ngrk %r13, %r4, %r0 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB3_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw and ptr %src, i128 %b seq_cst ret i128 %res } ; Check NAND of a variable. -define i128 @f5(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f5: -; CHECK: brasl %r14, __sync_fetch_and_nand_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_nand(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_nand: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB4_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: nngrk %r12, %r5, %r1 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: nngrk %r13, %r4, %r0 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB4_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw nand ptr %src, i128 %b seq_cst ret i128 %res } ; Check OR of a variable. -define i128 @f6(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f6: -; CHECK: brasl %r14, __sync_fetch_and_or_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_or(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_or: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB5_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: ogrk %r12, %r5, %r1 +; CHECK-NEXT: ogrk %r13, %r4, %r0 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB5_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw or ptr %src, i128 %b seq_cst ret i128 %res } ; Check XOR of a variable. -define i128 @f7(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f7: -; CHECK: brasl %r14, __sync_fetch_and_xor_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_xor(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_xor: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB6_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: xgrk %r12, %r5, %r1 +; CHECK-NEXT: xgrk %r13, %r4, %r0 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB6_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw xor ptr %src, i128 %b seq_cst ret i128 %res } ; Check signed minimum. -define i128 @f8(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f8: -; CHECK: brasl %r14, __sync_fetch_and_min_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_min(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_min: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB7_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: clgr %r4, %r0 +; CHECK-NEXT: lhi %r14, 0 +; CHECK-NEXT: lochile %r14, 1 +; CHECK-NEXT: cgr %r5, %r1 +; CHECK-NEXT: lhi %r13, 0 +; CHECK-NEXT: lochile %r13, 1 +; CHECK-NEXT: locrlh %r14, %r13 +; CHECK-NEXT: chi %r14, 0 +; CHECK-NEXT: selgrlh %r13, %r4, %r0 +; CHECK-NEXT: selgrlh %r12, %r5, %r1 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB7_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw min ptr %src, i128 %b seq_cst ret i128 %res } ; Check signed maximum. -define i128 @f9(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f9: -; CHECK: brasl %r14, __sync_fetch_and_max_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_max(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_max: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB8_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: clgr %r4, %r0 +; CHECK-NEXT: lhi %r14, 0 +; CHECK-NEXT: lochih %r14, 1 +; CHECK-NEXT: cgr %r5, %r1 +; CHECK-NEXT: lhi %r13, 0 +; CHECK-NEXT: lochih %r13, 1 +; CHECK-NEXT: locrlh %r14, %r13 +; CHECK-NEXT: chi %r14, 0 +; CHECK-NEXT: selgrlh %r13, %r4, %r0 +; CHECK-NEXT: selgrlh %r12, %r5, %r1 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB8_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw max ptr %src, i128 %b seq_cst ret i128 %res } ; Check unsigned minimum. -define i128 @f10(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f10: -; CHECK: brasl %r14, __sync_fetch_and_umin_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_umin(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_umin: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB9_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: clgr %r5, %r1 +; CHECK-NEXT: lhi %r14, 0 +; CHECK-NEXT: lochile %r14, 1 +; CHECK-NEXT: clgr %r4, %r0 +; CHECK-NEXT: lhi %r13, 0 +; CHECK-NEXT: lochile %r13, 1 +; CHECK-NEXT: cgr %r5, %r1 +; CHECK-NEXT: locre %r14, %r13 +; CHECK-NEXT: chi %r14, 0 +; CHECK-NEXT: selgrlh %r13, %r4, %r0 +; CHECK-NEXT: selgrlh %r12, %r5, %r1 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB9_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw umin ptr %src, i128 %b seq_cst ret i128 %res } ; Check unsigned maximum. -define i128 @f11(i128 %dummy, ptr %src, i128 %b) { -; CHECK-LABEL: f11: -; CHECK: brasl %r14, __sync_fetch_and_umax_16@PLT -; CHECK: br %r14 +define i128 @atomicrmw_umax(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_umax: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r10, %r15, 80(%r15) +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: .LBB10_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: clgr %r5, %r1 +; CHECK-NEXT: lhi %r14, 0 +; CHECK-NEXT: lochih %r14, 1 +; CHECK-NEXT: clgr %r4, %r0 +; CHECK-NEXT: lhi %r13, 0 +; CHECK-NEXT: lochih %r13, 1 +; CHECK-NEXT: cgr %r5, %r1 +; CHECK-NEXT: locre %r14, %r13 +; CHECK-NEXT: chi %r14, 0 +; CHECK-NEXT: selgrlh %r13, %r4, %r0 +; CHECK-NEXT: selgrlh %r12, %r5, %r1 +; CHECK-NEXT: lgr %r10, %r5 +; CHECK-NEXT: lgr %r11, %r4 +; CHECK-NEXT: cdsg %r10, %r12, 0(%r3) +; CHECK-NEXT: lgr %r4, %r11 +; CHECK-NEXT: lgr %r5, %r10 +; CHECK-NEXT: jl .LBB10_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r10, %r15, 80(%r15) +; CHECK-NEXT: br %r14 %res = atomicrmw umax ptr %src, i128 %b seq_cst ret i128 %res } +; Check increment with wraparound. +define i128 @atomicrmw_uinc_wrap(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_uinc_wrap: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r8, %r15, 64(%r15) +; CHECK-NEXT: .cfi_offset %r8, -96 +; CHECK-NEXT: .cfi_offset %r9, -88 +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r5, 8(%r3) +; CHECK-NEXT: lg %r14, 0(%r3) +; CHECK-NEXT: lghi %r4, 0 +; CHECK-NEXT: .LBB11_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: alghsik %r13, %r5, 1 +; CHECK-NEXT: lgr %r12, %r14 +; CHECK-NEXT: lhi %r11, 0 +; CHECK-NEXT: alcgr %r12, %r4 +; CHECK-NEXT: clgr %r14, %r1 +; CHECK-NEXT: lochihe %r11, 1 +; CHECK-NEXT: clgr %r5, %r0 +; CHECK-NEXT: lhi %r10, 0 +; CHECK-NEXT: lochihe %r10, 1 +; CHECK-NEXT: cgr %r14, %r1 +; CHECK-NEXT: locre %r11, %r10 +; CHECK-NEXT: chi %r11, 0 +; CHECK-NEXT: locghilh %r13, 0 +; CHECK-NEXT: locghilh %r12, 0 +; CHECK-NEXT: lgr %r8, %r14 +; CHECK-NEXT: lgr %r9, %r5 +; CHECK-NEXT: cdsg %r8, %r12, 0(%r3) +; CHECK-NEXT: lgr %r5, %r9 +; CHECK-NEXT: lgr %r14, %r8 +; CHECK-NEXT: jl .LBB11_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r14, 0(%r2) +; CHECK-NEXT: stg %r5, 8(%r2) +; CHECK-NEXT: lmg %r8, %r15, 64(%r15) +; CHECK-NEXT: br %r14 + %res = atomicrmw uinc_wrap ptr %src, i128 %b seq_cst + ret i128 %res +} + +; Check decrement with wraparound. +define i128 @atomicrmw_udec_wrap(ptr %src, i128 %b) { +; CHECK-LABEL: atomicrmw_udec_wrap: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r6, %r15, 48(%r15) +; CHECK-NEXT: .cfi_offset %r6, -112 +; CHECK-NEXT: .cfi_offset %r7, -104 +; CHECK-NEXT: .cfi_offset %r9, -88 +; CHECK-NEXT: .cfi_offset %r10, -80 +; CHECK-NEXT: .cfi_offset %r11, -72 +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: lg %r0, 8(%r4) +; CHECK-NEXT: lg %r1, 0(%r4) +; CHECK-NEXT: lg %r5, 8(%r3) +; CHECK-NEXT: lg %r14, 0(%r3) +; CHECK-NEXT: lghi %r4, -1 +; CHECK-NEXT: .LBB12_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: alghsik %r13, %r5, -1 +; CHECK-NEXT: lgr %r12, %r14 +; CHECK-NEXT: lhi %r10, 0 +; CHECK-NEXT: alcgr %r12, %r4 +; CHECK-NEXT: ogrk %r11, %r5, %r14 +; CHECK-NEXT: lhi %r11, 0 +; CHECK-NEXT: lochie %r11, 1 +; CHECK-NEXT: clgr %r14, %r1 +; CHECK-NEXT: lochih %r10, 1 +; CHECK-NEXT: clgr %r5, %r0 +; CHECK-NEXT: lhi %r9, 0 +; CHECK-NEXT: lochih %r9, 1 +; CHECK-NEXT: cgr %r14, %r1 +; CHECK-NEXT: locre %r10, %r9 +; CHECK-NEXT: or %r11, %r10 +; CHECK-NEXT: selgrl %r11, %r0, %r13 +; CHECK-NEXT: selgrl %r10, %r1, %r12 +; CHECK-NEXT: lgr %r6, %r14 +; CHECK-NEXT: lgr %r7, %r5 +; CHECK-NEXT: cdsg %r6, %r10, 0(%r3) +; CHECK-NEXT: lgr %r5, %r7 +; CHECK-NEXT: lgr %r14, %r6 +; CHECK-NEXT: jl .LBB12_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r14, 0(%r2) +; CHECK-NEXT: stg %r5, 8(%r2) +; CHECK-NEXT: lmg %r6, %r15, 48(%r15) +; CHECK-NEXT: br %r14 + %res = atomicrmw udec_wrap ptr %src, i128 %b seq_cst + ret i128 %res +} diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll index 80cc85158e45..b9e29599af7e 100644 --- a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll +++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll @@ -2,23 +2,28 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -define void @f1(ptr %ret, ptr %src, ptr %b) { +define void @f1(ptr align 16 %ret, ptr align 16 %src, ptr align 16 %b) { ; CHECK-LABEL: f1: -; CHECK: lg [[RH:%r[0-9]+]], 8(%r4) -; CHECK: lgr [[RET:%r[0-9]+]], %r2 -; CHECK: lg [[RL:%r[0-9]+]], 0(%r4) -; CHECK: stg [[RH]], 168(%r15) -; CHECK: la %r2, 176(%r15) -; CHECK: la %r4, 160(%r15) -; CHECK: stg [[RL]], 160(%r15) -; CHECK: brasl %r14, __sync_lock_test_and_set_16@PLT -; CHECK: lg [[RH2:%r[0-9]+]], 184(%r15) -; CHECK: lg [[RL2:%r[0-9]+]], 176(%r15) -; CHECK: stg [[RH]], 8([[RET]]) -; CHECK: stg [[RL]], 0([[RET]]) -; CHECK: br %r14 - %val = load fp128, ptr %b, align 8 +; CHECK: lg %r14, 8(%r4) +; CHECK-NEXT: lg %r0, 0(%r4) +; CHECK-NEXT: lg %r4, 8(%r3) +; CHECK-NEXT: lg %r5, 0(%r3) +; CHECK-NEXT: lgr %r1, %r14 +; CHECK-NEXT:.LBB0_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: lgr %r12, %r5 +; CHECK-NEXT: lgr %r13, %r4 +; CHECK-NEXT: cdsg %r12, %r0, 0(%r3) +; CHECK-NEXT: lgr %r4, %r13 +; CHECK-NEXT: lgr %r5, %r12 +; CHECK-NEXT: jl .LBB0_1 +; CHECK-NEXT:# %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r5, 0(%r2) +; CHECK-NEXT: stg %r4, 8(%r2) +; CHECK-NEXT: lmg %r12, %r15, 96(%r15) +; CHECK-NEXT: br %r14 + %val = load fp128, ptr %b, align 16 %res = atomicrmw xchg ptr %src, fp128 %val seq_cst - store fp128 %res, ptr %ret, align 8 + store fp128 %res, ptr %ret, align 16 ret void } diff --git a/llvm/test/CodeGen/SystemZ/vec-load-element.ll b/llvm/test/CodeGen/SystemZ/vec-load-element.ll index 25d29127ebf0..2baaed19546d 100644 --- a/llvm/test/CodeGen/SystemZ/vec-load-element.ll +++ b/llvm/test/CodeGen/SystemZ/vec-load-element.ll @@ -18,8 +18,8 @@ entry: vector.body: ; preds = %vector.body, %entry %index = phi i64 [ 0, %entry ], [ %index.next.3, %vector.body ] %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %57, %vector.body ] - %0 = or i64 %index, 2 - %1 = or i64 %index, 3 + %0 = or disjoint i64 %index, 2 + %1 = or disjoint i64 %index, 3 %2 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 0, i32 3 %3 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 %0, i32 3 %4 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 %1, i32 3 @@ -31,7 +31,7 @@ vector.body: ; preds = %vector.body, %entry %10 = insertelement <4 x i32> %9, i32 %6, i32 2 %11 = insertelement <4 x i32> %10, i32 %7, i32 3 %12 = add nsw <4 x i32> %11, %vec.phi - %13 = or i64 %index, 7 + %13 = or disjoint i64 %index, 7 %14 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 undef, i32 3 %15 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 0, i32 3 %16 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 %13, i32 3 @@ -44,9 +44,9 @@ vector.body: ; preds = %vector.body, %entry %23 = insertelement <4 x i32> %22, i32 %19, i32 2 %24 = insertelement <4 x i32> %23, i32 %20, i32 3 %25 = add nsw <4 x i32> %24, %12 - %26 = or i64 %index, 9 - %27 = or i64 %index, 10 - %28 = or i64 %index, 11 + %26 = or disjoint i64 %index, 9 + %27 = or disjoint i64 %index, 10 + %28 = or disjoint i64 %index, 11 %29 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 undef, i32 3 %30 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 %26, i32 3 %31 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 %27, i32 3 @@ -60,9 +60,9 @@ vector.body: ; preds = %vector.body, %entry %39 = insertelement <4 x i32> %38, i32 %35, i32 2 %40 = insertelement <4 x i32> %39, i32 %36, i32 3 %41 = add nsw <4 x i32> %40, %25 - %42 = or i64 %index, 13 - %43 = or i64 %index, 14 - %44 = or i64 %index, 15 + %42 = or disjoint i64 %index, 13 + %43 = or disjoint i64 %index, 14 + %44 = or disjoint i64 %index, 15 %45 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 undef, i32 3 %46 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 %42, i32 3 %47 = getelementptr inbounds [150 x %type0], ptr @Mem, i64 0, i64 %43, i32 3 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll index 9933720953d3..2fdf534d5265 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll @@ -166,7 +166,7 @@ for.body: ; preds = %for.body, %for.body %mul = fmul fast float %i14, %i13 %arrayidx2 = getelementptr inbounds float, ptr %a, i32 %i.09 store float %mul, ptr %arrayidx2, align 4 - %inc = or i32 %i.09, 1 + %inc = or disjoint i32 %i.09, 1 %arrayidx.1 = getelementptr inbounds float, ptr %b, i32 %inc %i15 = load float, ptr %arrayidx.1, align 4 %arrayidx1.1 = getelementptr inbounds float, ptr %c, i32 %inc @@ -174,7 +174,7 @@ for.body: ; preds = %for.body, %for.body %mul.1 = fmul fast float %i16, %i15 %arrayidx2.1 = getelementptr inbounds float, ptr %a, i32 %inc store float %mul.1, ptr %arrayidx2.1, align 4 - %inc.1 = or i32 %i.09, 2 + %inc.1 = or disjoint i32 %i.09, 2 %arrayidx.2 = getelementptr inbounds float, ptr %b, i32 %inc.1 %i17 = load float, ptr %arrayidx.2, align 4 %arrayidx1.2 = getelementptr inbounds float, ptr %c, i32 %inc.1 @@ -182,7 +182,7 @@ for.body: ; preds = %for.body, %for.body %mul.2 = fmul fast float %i18, %i17 %arrayidx2.2 = getelementptr inbounds float, ptr %a, i32 %inc.1 store float %mul.2, ptr %arrayidx2.2, align 4 - %inc.2 = or i32 %i.09, 3 + %inc.2 = or disjoint i32 %i.09, 3 %arrayidx.3 = getelementptr inbounds float, ptr %b, i32 %inc.2 %i19 = load float, ptr %arrayidx.3, align 4 %arrayidx1.3 = getelementptr inbounds float, ptr %c, i32 %inc.2 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll index cc6d0925d180..8b71987246ee 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll @@ -1526,7 +1526,7 @@ for.body: ; preds = %for.body, %for.body %mul = fmul half %4, %5 %conv = fpext half %mul to float %add = fadd float %res.09, %conv - %inc = or i32 %i.010, 1 + %inc = or disjoint i32 %i.010, 1 %arrayidx.1 = getelementptr inbounds half, ptr %a, i32 %inc %6 = load half, ptr %arrayidx.1, align 2 %arrayidx1.1 = getelementptr inbounds half, ptr %b, i32 %inc @@ -1534,7 +1534,7 @@ for.body: ; preds = %for.body, %for.body %mul.1 = fmul half %6, %7 %conv.1 = fpext half %mul.1 to float %add.1 = fadd float %add, %conv.1 - %inc.1 = or i32 %i.010, 2 + %inc.1 = or disjoint i32 %i.010, 2 %arrayidx.2 = getelementptr inbounds half, ptr %a, i32 %inc.1 %8 = load half, ptr %arrayidx.2, align 2 %arrayidx1.2 = getelementptr inbounds half, ptr %b, i32 %inc.1 @@ -1542,7 +1542,7 @@ for.body: ; preds = %for.body, %for.body %mul.2 = fmul half %8, %9 %conv.2 = fpext half %mul.2 to float %add.2 = fadd float %add.1, %conv.2 - %inc.2 = or i32 %i.010, 3 + %inc.2 = or disjoint i32 %i.010, 3 %arrayidx.3 = getelementptr inbounds half, ptr %a, i32 %inc.2 %10 = load half, ptr %arrayidx.3, align 2 %arrayidx1.3 = getelementptr inbounds half, ptr %b, i32 %inc.2 @@ -1681,7 +1681,7 @@ for.body: ; preds = %for.body, %for.body %add = fadd half %4, %5 %conv = fpext half %add to float %add2 = fadd float %res.010, %conv - %inc = or i32 %i.011, 1 + %inc = or disjoint i32 %i.011, 1 %arrayidx.1 = getelementptr inbounds half, ptr %a, i32 %inc %6 = load half, ptr %arrayidx.1, align 2 %arrayidx1.1 = getelementptr inbounds half, ptr %b, i32 %inc @@ -1689,7 +1689,7 @@ for.body: ; preds = %for.body, %for.body %add.1 = fadd half %6, %7 %conv.1 = fpext half %add.1 to float %add2.1 = fadd float %add2, %conv.1 - %inc.1 = or i32 %i.011, 2 + %inc.1 = or disjoint i32 %i.011, 2 %arrayidx.2 = getelementptr inbounds half, ptr %a, i32 %inc.1 %8 = load half, ptr %arrayidx.2, align 2 %arrayidx1.2 = getelementptr inbounds half, ptr %b, i32 %inc.1 @@ -1697,7 +1697,7 @@ for.body: ; preds = %for.body, %for.body %add.2 = fadd half %8, %9 %conv.2 = fpext half %add.2 to float %add2.2 = fadd float %add2.1, %conv.2 - %inc.2 = or i32 %i.011, 3 + %inc.2 = or disjoint i32 %i.011, 3 %arrayidx.3 = getelementptr inbounds half, ptr %a, i32 %inc.2 %10 = load half, ptr %arrayidx.3, align 2 %arrayidx1.3 = getelementptr inbounds half, ptr %b, i32 %inc.2 @@ -1846,7 +1846,7 @@ for.body: ; preds = %for.body, %for.body %mul = fmul half %4, %conv2 %conv3 = fpext half %mul to float %add = fadd float %res.011, %conv3 - %inc = or i32 %i.012, 1 + %inc = or disjoint i32 %i.012, 1 %arrayidx.1 = getelementptr inbounds half, ptr %a, i32 %inc %6 = load half, ptr %arrayidx.1, align 2 %arrayidx1.1 = getelementptr inbounds i16, ptr %b, i32 %inc @@ -1855,7 +1855,7 @@ for.body: ; preds = %for.body, %for.body %mul.1 = fmul half %6, %conv2.1 %conv3.1 = fpext half %mul.1 to float %add.1 = fadd float %add, %conv3.1 - %inc.1 = or i32 %i.012, 2 + %inc.1 = or disjoint i32 %i.012, 2 %arrayidx.2 = getelementptr inbounds half, ptr %a, i32 %inc.1 %8 = load half, ptr %arrayidx.2, align 2 %arrayidx1.2 = getelementptr inbounds i16, ptr %b, i32 %inc.1 @@ -1864,7 +1864,7 @@ for.body: ; preds = %for.body, %for.body %mul.2 = fmul half %8, %conv2.2 %conv3.2 = fpext half %mul.2 to float %add.2 = fadd float %add.1, %conv3.2 - %inc.2 = or i32 %i.012, 3 + %inc.2 = or disjoint i32 %i.012, 3 %arrayidx.3 = getelementptr inbounds half, ptr %a, i32 %inc.2 %10 = load half, ptr %arrayidx.3, align 2 %arrayidx1.3 = getelementptr inbounds i16, ptr %b, i32 %inc.2 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll index d41d7d2c1a51..cfa6eb3aca82 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll @@ -506,7 +506,7 @@ for.body: ; preds = %for.body, %for.body %add = add nuw nsw i32 %mul, %conv3 %arrayidx4 = getelementptr inbounds i32, i32* %res, i32 %i.011 store i32 %add, i32* %arrayidx4, align 4 - %inc = or i32 %i.011, 1 + %inc = or disjoint i32 %i.011, 1 %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %inc %18 = load i8, i8* %arrayidx.1, align 1 %conv.1 = zext i8 %18 to i32 @@ -517,7 +517,7 @@ for.body: ; preds = %for.body, %for.body %add.1 = add nuw nsw i32 %mul.1, %conv3 %arrayidx4.1 = getelementptr inbounds i32, i32* %res, i32 %inc store i32 %add.1, i32* %arrayidx4.1, align 4 - %inc.1 = or i32 %i.011, 2 + %inc.1 = or disjoint i32 %i.011, 2 %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %inc.1 %20 = load i8, i8* %arrayidx.2, align 1 %conv.2 = zext i8 %20 to i32 @@ -528,7 +528,7 @@ for.body: ; preds = %for.body, %for.body %add.2 = add nuw nsw i32 %mul.2, %conv3 %arrayidx4.2 = getelementptr inbounds i32, i32* %res, i32 %inc.1 store i32 %add.2, i32* %arrayidx4.2, align 4 - %inc.2 = or i32 %i.011, 3 + %inc.2 = or disjoint i32 %i.011, 3 %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %inc.2 %22 = load i8, i8* %arrayidx.3, align 1 %conv.3 = zext i8 %22 to i32 @@ -782,7 +782,7 @@ for.body: ; preds = %for.body, %for.body %add = add nuw nsw i32 %mul, %conv3 %arrayidx4 = getelementptr inbounds i32, i32* %res, i32 %i.011 store i32 %add, i32* %arrayidx4, align 4 - %inc = or i32 %i.011, 1 + %inc = or disjoint i32 %i.011, 1 %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %inc %18 = load i8, i8* %arrayidx.1, align 1 %conv.1 = zext i8 %18 to i32 @@ -793,7 +793,7 @@ for.body: ; preds = %for.body, %for.body %add.1 = add nuw nsw i32 %mul.1, %conv3 %arrayidx4.1 = getelementptr inbounds i32, i32* %res, i32 %inc store i32 %add.1, i32* %arrayidx4.1, align 4 - %inc.1 = or i32 %i.011, 2 + %inc.1 = or disjoint i32 %i.011, 2 %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %inc.1 %20 = load i8, i8* %arrayidx.2, align 1 %conv.2 = zext i8 %20 to i32 @@ -804,7 +804,7 @@ for.body: ; preds = %for.body, %for.body %add.2 = add nuw nsw i32 %mul.2, %conv3 %arrayidx4.2 = getelementptr inbounds i32, i32* %res, i32 %inc.1 store i32 %add.2, i32* %arrayidx4.2, align 4 - %inc.2 = or i32 %i.011, 3 + %inc.2 = or disjoint i32 %i.011, 3 %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %inc.2 %22 = load i8, i8* %arrayidx.3, align 1 %conv.3 = zext i8 %22 to i32 @@ -1051,7 +1051,7 @@ for.body: ; preds = %for.body, %for.body %add = add nsw i32 %mul, %c %arrayidx2 = getelementptr inbounds i32, i32* %res, i32 %i.09 store i32 %add, i32* %arrayidx2, align 4 - %inc = or i32 %i.09, 1 + %inc = or disjoint i32 %i.09, 1 %arrayidx.1 = getelementptr inbounds i32, i32* %a, i32 %inc %16 = load i32, i32* %arrayidx.1, align 4 %arrayidx1.1 = getelementptr inbounds i32, i32* %b, i32 %inc @@ -1060,7 +1060,7 @@ for.body: ; preds = %for.body, %for.body %add.1 = add nsw i32 %mul.1, %c %arrayidx2.1 = getelementptr inbounds i32, i32* %res, i32 %inc store i32 %add.1, i32* %arrayidx2.1, align 4 - %inc.1 = or i32 %i.09, 2 + %inc.1 = or disjoint i32 %i.09, 2 %arrayidx.2 = getelementptr inbounds i32, i32* %a, i32 %inc.1 %18 = load i32, i32* %arrayidx.2, align 4 %arrayidx1.2 = getelementptr inbounds i32, i32* %b, i32 %inc.1 @@ -1069,7 +1069,7 @@ for.body: ; preds = %for.body, %for.body %add.2 = add nsw i32 %mul.2, %c %arrayidx2.2 = getelementptr inbounds i32, i32* %res, i32 %inc.1 store i32 %add.2, i32* %arrayidx2.2, align 4 - %inc.2 = or i32 %i.09, 3 + %inc.2 = or disjoint i32 %i.09, 3 %arrayidx.3 = getelementptr inbounds i32, i32* %a, i32 %inc.2 %20 = load i32, i32* %arrayidx.3, align 4 %arrayidx1.3 = getelementptr inbounds i32, i32* %b, i32 %inc.2 diff --git a/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll b/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll index e22fd4cabfa5..cc7b5a7f3f81 100644 --- a/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll +++ b/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll @@ -213,7 +213,7 @@ cond.end22: ; preds = %for.body10, %cond.t %tobool24 = icmp ne i32 %cond23, 0 %frombool = zext i1 %tobool24 to i8 store i8 %frombool, ptr @var_36, align 1 - %add = or i32 %i_15.044, 1 + %add = or disjoint i32 %i_15.044, 1 %arraydecay.1 = getelementptr inbounds [18 x [22 x i8]], ptr %arr_60, i32 %add, i32 0 %2 = ptrtoint ptr %arraydecay.1 to i32 %arrayidx13.1 = getelementptr inbounds [1 x i32], ptr @arr_61, i32 0, i32 %add @@ -258,7 +258,7 @@ cond.end22.1119: ; preds = %cond.true19.1114, % %tobool24.1116 = icmp ne i32 %cond23.1115, 0 %frombool.1117 = zext i1 %tobool24.1116 to i8 store i8 %frombool.1117, ptr @var_36, align 1 - %add.1118 = or i32 %i_15.044.1, 1 + %add.1118 = or disjoint i32 %i_15.044.1, 1 %arraydecay.1.1 = getelementptr inbounds [18 x [22 x i8]], ptr %arr_60, i32 %add.1118, i32 0 %6 = ptrtoint ptr %arraydecay.1.1 to i32 %arrayidx13.1.1 = getelementptr inbounds [1 x i32], ptr @arr_61, i32 0, i32 %add.1118 @@ -308,7 +308,7 @@ cond.end22.2: ; preds = %cond.true19.2, %for %tobool24.2 = icmp ne i32 %cond23.2, 0 %frombool.2 = zext i1 %tobool24.2 to i8 store i8 %frombool.2, ptr @var_36, align 1 - %add.2 = or i32 %i_15.044.2, 1 + %add.2 = or disjoint i32 %i_15.044.2, 1 %arraydecay.1.2 = getelementptr inbounds [18 x [22 x i8]], ptr %arr_60, i32 %add.2, i32 0 %10 = ptrtoint ptr %arraydecay.1.2 to i32 %arrayidx13.1.2 = getelementptr inbounds [1 x i32], ptr @arr_61, i32 0, i32 %add.2 diff --git a/llvm/test/CodeGen/Thumb2/mve-tailpred-loopinvariant.ll b/llvm/test/CodeGen/Thumb2/mve-tailpred-loopinvariant.ll index 750947dc2618..6b2a6e63af23 100644 --- a/llvm/test/CodeGen/Thumb2/mve-tailpred-loopinvariant.ll +++ b/llvm/test/CodeGen/Thumb2/mve-tailpred-loopinvariant.ll @@ -43,35 +43,35 @@ while.body.preheader: ; preds = %entry vector.body: ; preds = %vector.body, %while.body.preheader %index = phi i32 [ 0, %while.body.preheader ], [ %index.next, %vector.body ] %next.gep = getelementptr i8, ptr %c, i32 %index - %1 = or i32 %index, 1 + %1 = or disjoint i32 %index, 1 %next.gep7 = getelementptr i8, ptr %c, i32 %1 - %2 = or i32 %index, 2 + %2 = or disjoint i32 %index, 2 %next.gep8 = getelementptr i8, ptr %c, i32 %2 - %3 = or i32 %index, 3 + %3 = or disjoint i32 %index, 3 %next.gep9 = getelementptr i8, ptr %c, i32 %3 - %4 = or i32 %index, 4 + %4 = or disjoint i32 %index, 4 %next.gep10 = getelementptr i8, ptr %c, i32 %4 - %5 = or i32 %index, 5 + %5 = or disjoint i32 %index, 5 %next.gep11 = getelementptr i8, ptr %c, i32 %5 - %6 = or i32 %index, 6 + %6 = or disjoint i32 %index, 6 %next.gep12 = getelementptr i8, ptr %c, i32 %6 - %7 = or i32 %index, 7 + %7 = or disjoint i32 %index, 7 %next.gep13 = getelementptr i8, ptr %c, i32 %7 - %8 = or i32 %index, 8 + %8 = or disjoint i32 %index, 8 %next.gep14 = getelementptr i8, ptr %c, i32 %8 - %9 = or i32 %index, 9 + %9 = or disjoint i32 %index, 9 %next.gep15 = getelementptr i8, ptr %c, i32 %9 - %10 = or i32 %index, 10 + %10 = or disjoint i32 %index, 10 %next.gep16 = getelementptr i8, ptr %c, i32 %10 - %11 = or i32 %index, 11 + %11 = or disjoint i32 %index, 11 %next.gep17 = getelementptr i8, ptr %c, i32 %11 - %12 = or i32 %index, 12 + %12 = or disjoint i32 %index, 12 %next.gep18 = getelementptr i8, ptr %c, i32 %12 - %13 = or i32 %index, 13 + %13 = or disjoint i32 %index, 13 %next.gep19 = getelementptr i8, ptr %c, i32 %13 - %14 = or i32 %index, 14 + %14 = or disjoint i32 %index, 14 %next.gep20 = getelementptr i8, ptr %c, i32 %14 - %15 = or i32 %index, 15 + %15 = or disjoint i32 %index, 15 %next.gep21 = getelementptr i8, ptr %c, i32 %15 %16 = insertelement <16 x ptr> poison, ptr %next.gep, i32 0 %17 = insertelement <16 x ptr> %16, ptr %next.gep7, i32 1 diff --git a/llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll b/llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll index aa556b4418f5..853a56d41af8 100644 --- a/llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll +++ b/llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll @@ -55,15 +55,15 @@ for.body: ; preds = %for.body, %for.body %arrayidx = getelementptr inbounds i32, ptr %vla, i32 %i.010 %3 = load i32, ptr %arrayidx, align 4 %add = add nsw i32 %3, %s.09 - %inc = or i32 %i.010, 1 + %inc = or disjoint i32 %i.010, 1 %arrayidx.1 = getelementptr inbounds i32, ptr %vla, i32 %inc %4 = load i32, ptr %arrayidx.1, align 4 %add.1 = add nsw i32 %4, %add - %inc.1 = or i32 %i.010, 2 + %inc.1 = or disjoint i32 %i.010, 2 %arrayidx.2 = getelementptr inbounds i32, ptr %vla, i32 %inc.1 %5 = load i32, ptr %arrayidx.2, align 4 %add.2 = add nsw i32 %5, %add.1 - %inc.2 = or i32 %i.010, 3 + %inc.2 = or disjoint i32 %i.010, 3 %arrayidx.3 = getelementptr inbounds i32, ptr %vla, i32 %inc.2 %6 = load i32, ptr %arrayidx.3, align 4 %add.3 = add nsw i32 %6, %add.2 diff --git a/llvm/test/CodeGen/WebAssembly/unrolled-mem-indices.ll b/llvm/test/CodeGen/WebAssembly/unrolled-mem-indices.ll index 5178f1ec0c15..a232853688cb 100644 --- a/llvm/test/CodeGen/WebAssembly/unrolled-mem-indices.ll +++ b/llvm/test/CodeGen/WebAssembly/unrolled-mem-indices.ll @@ -70,7 +70,7 @@ bb4: ; preds = %bb4, %bb %i11 = add nsw i32 %i10, %i7 %i12 = getelementptr inbounds i32, ptr %arg2, i32 %i store i32 %i11, ptr %i12, align 4 - %i13 = or i32 %i, 1 + %i13 = or disjoint i32 %i, 1 %i14 = getelementptr inbounds i16, ptr %arg, i32 %i13 %i15 = load i16, ptr %i14, align 2 %i16 = sext i16 %i15 to i32 @@ -152,7 +152,7 @@ bb4: ; preds = %bb4, %bb %i11 = add nsw i32 %i10, %i7 %i12 = getelementptr inbounds i32, ptr %arg2, i32 %i store i32 %i11, ptr %i12, align 4 - %i13 = or i32 %i, 1 + %i13 = or disjoint i32 %i, 1 %i14 = getelementptr i16, ptr %arg, i32 %i13 %i15 = load i16, ptr %i14, align 2 %i16 = sext i16 %i15 to i32 @@ -303,7 +303,7 @@ bb14: ; preds = %bb14, %bb3 %i22 = sext i16 %i21 to i32 %i23 = add nsw i32 %i22, %i19 %i24 = add nsw i32 %i23, %i16 - %i25 = or i32 %i15, 1 + %i25 = or disjoint i32 %i15, 1 %i26 = getelementptr inbounds i16, ptr %i5, i32 %i25 %i27 = load i16, ptr %i26, align 2 %i28 = sext i16 %i27 to i32 @@ -312,7 +312,7 @@ bb14: ; preds = %bb14, %bb3 %i31 = sext i16 %i30 to i32 %i32 = add nsw i32 %i31, %i28 %i33 = add nsw i32 %i32, %i24 - %i34 = or i32 %i15, 2 + %i34 = or disjoint i32 %i15, 2 %i35 = getelementptr inbounds i16, ptr %i5, i32 %i34 %i36 = load i16, ptr %i35, align 2 %i37 = sext i16 %i36 to i32 @@ -321,7 +321,7 @@ bb14: ; preds = %bb14, %bb3 %i40 = sext i16 %i39 to i32 %i41 = add nsw i32 %i40, %i37 %i42 = add nsw i32 %i41, %i33 - %i43 = or i32 %i15, 3 + %i43 = or disjoint i32 %i15, 3 %i44 = getelementptr inbounds i16, ptr %i5, i32 %i43 %i45 = load i16, ptr %i44, align 2 %i46 = sext i16 %i45 to i32 @@ -478,7 +478,7 @@ bb20: ; preds = %bb20, %bb7 %i27 = fadd float %i24, %i26 %i28 = getelementptr inbounds float, ptr %arg2, i32 %i21 store float %i27, ptr %i28, align 4 - %i29 = or i32 %i21, 1 + %i29 = or disjoint i32 %i21, 1 %i30 = getelementptr inbounds float, ptr %arg, i32 %i29 %i31 = load float, ptr %i30, align 4 %i32 = getelementptr inbounds float, ptr %arg1, i32 %i29 diff --git a/llvm/test/CodeGen/WebAssembly/wasmehprepare.ll b/llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll similarity index 95% rename from llvm/test/CodeGen/WebAssembly/wasmehprepare.ll rename to llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll index a418eb4ec890..e3de25101738 100644 --- a/llvm/test/CodeGen/WebAssembly/wasmehprepare.ll +++ b/llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll @@ -1,5 +1,7 @@ -; RUN: opt < %s -winehprepare -demote-catchswitch-only -wasmehprepare -S | FileCheck %s -; RUN: opt < %s -winehprepare -demote-catchswitch-only -wasmehprepare -S --mattr=+atomics,+bulk-memory | FileCheck %s +; RUN: opt < %s -winehprepare -demote-catchswitch-only -wasm-eh-prepare -S | FileCheck %s +; RUN: opt < %s -winehprepare -demote-catchswitch-only -wasm-eh-prepare -S --mattr=+atomics,+bulk-memory | FileCheck %s +; RUN: opt < %s -passes='win-eh-prepare,wasm-eh-prepare' -S | FileCheck %s +; RUN: opt < %s -passes='win-eh-prepare,wasm-eh-prepare' -S --mattr=+atomics,+bulk-memory | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target triple = "wasm32-unknown-unknown" diff --git a/llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll b/llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll index dfe1662492a3..ca92c555058a 100644 --- a/llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll +++ b/llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll @@ -31,7 +31,7 @@ forbody: %i.0 = phi i32 [ 0, %entry ], [ %inc, %forbody ] ; [#uses=3] %sub14 = sub i32 1027, %i.0 ; [#uses=1] %mul15 = mul i32 %sub14, 10 ; [#uses=1] - %add166 = or i32 %mul15, 1 ; ptr + %add166 = or disjoint i32 %mul15, 1 ; ptr call i32 (ptr, ...) @printf( ptr noalias @.str, i32 %add166 ) nounwind %inc = add i32 %i.0, 1 ; [#uses=3] %cmp = icmp ne i32 %inc, 1027 ; [#uses=1] diff --git a/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll b/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll index ecf38980573d..78a0a849f13e 100644 --- a/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll +++ b/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll @@ -979,7 +979,7 @@ define void @MergeLoadStoreBaseIndexOffsetComplicated(i8* %a, i8* %b, i8* %c, i6 %8 = load i8, i8* %7, align 1 %9 = getelementptr inbounds i8, i8* %a, i64 %.09 store i8 %5, i8* %9, align 1 - %10 = or i64 %.09, 1 + %10 = or disjoint i64 %.09, 1 %11 = getelementptr inbounds i8, i8* %a, i64 %10 store i8 %8, i8* %11, align 1 %12 = getelementptr inbounds i8, i8* %.08, i64 1 diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll index b66988c8bd24..df123be53474 100644 --- a/llvm/test/CodeGen/X86/atomic-unordered.ll +++ b/llvm/test/CodeGen/X86/atomic-unordered.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O0 < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mcpu=skylake -x86-experimental-unordered-atomic-isel=0 | FileCheck --check-prefixes=CHECK,CHECK-O0,CHECK-O0-CUR %s -; RUN: llc -O3 < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mcpu=skylake -x86-experimental-unordered-atomic-isel=0 | FileCheck --check-prefixes=CHECK,CHECK-O3,CHECK-O3-CUR %s -; RUN: llc -O0 < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mcpu=skylake -x86-experimental-unordered-atomic-isel=1 | FileCheck --check-prefixes=CHECK,CHECK-O0,CHECK-O0-EX %s -; RUN: llc -O3 < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mcpu=skylake -x86-experimental-unordered-atomic-isel=1 | FileCheck --check-prefixes=CHECK,CHECK-O3,CHECK-O3-EX %s +; RUN: llc -O0 < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mcpu=skylake | FileCheck --check-prefixes=CHECK,CHECK-O0 %s +; RUN: llc -O3 < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mcpu=skylake | FileCheck --check-prefixes=CHECK,CHECK-O3 %s define i8 @load_i8(ptr %ptr) { ; CHECK-O0-LABEL: load_i8: @@ -408,33 +406,21 @@ define void @store_i256(ptr %ptr, i256 %v) { ; Legal if wider type is also atomic (TODO) define void @vec_store(ptr %p0, <2 x i32> %vec) { -; CHECK-O0-CUR-LABEL: vec_store: -; CHECK-O0-CUR: # %bb.0: -; CHECK-O0-CUR-NEXT: vmovd %xmm0, %ecx -; CHECK-O0-CUR-NEXT: vpextrd $1, %xmm0, %eax -; CHECK-O0-CUR-NEXT: movl %ecx, (%rdi) -; CHECK-O0-CUR-NEXT: movl %eax, 4(%rdi) -; CHECK-O0-CUR-NEXT: retq -; -; CHECK-O3-CUR-LABEL: vec_store: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: vmovd %xmm0, %eax -; CHECK-O3-CUR-NEXT: vpextrd $1, %xmm0, %ecx -; CHECK-O3-CUR-NEXT: movl %eax, (%rdi) -; CHECK-O3-CUR-NEXT: movl %ecx, 4(%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O0-EX-LABEL: vec_store: -; CHECK-O0-EX: # %bb.0: -; CHECK-O0-EX-NEXT: vmovd %xmm0, (%rdi) -; CHECK-O0-EX-NEXT: vpextrd $1, %xmm0, 4(%rdi) -; CHECK-O0-EX-NEXT: retq -; -; CHECK-O3-EX-LABEL: vec_store: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: vmovss %xmm0, (%rdi) -; CHECK-O3-EX-NEXT: vextractps $1, %xmm0, 4(%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-O0-LABEL: vec_store: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: vmovd %xmm0, %ecx +; CHECK-O0-NEXT: vpextrd $1, %xmm0, %eax +; CHECK-O0-NEXT: movl %ecx, (%rdi) +; CHECK-O0-NEXT: movl %eax, 4(%rdi) +; CHECK-O0-NEXT: retq +; +; CHECK-O3-LABEL: vec_store: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: vmovd %xmm0, %eax +; CHECK-O3-NEXT: vpextrd $1, %xmm0, %ecx +; CHECK-O3-NEXT: movl %eax, (%rdi) +; CHECK-O3-NEXT: movl %ecx, 4(%rdi) +; CHECK-O3-NEXT: retq %v1 = extractelement <2 x i32> %vec, i32 0 %v2 = extractelement <2 x i32> %vec, i32 1 %p1 = getelementptr i32, ptr %p0, i64 1 @@ -445,33 +431,21 @@ define void @vec_store(ptr %p0, <2 x i32> %vec) { ; Not legal to widen due to alignment restriction define void @vec_store_unaligned(ptr %p0, <2 x i32> %vec) { -; CHECK-O0-CUR-LABEL: vec_store_unaligned: -; CHECK-O0-CUR: # %bb.0: -; CHECK-O0-CUR-NEXT: vmovd %xmm0, %ecx -; CHECK-O0-CUR-NEXT: vpextrd $1, %xmm0, %eax -; CHECK-O0-CUR-NEXT: movl %ecx, (%rdi) -; CHECK-O0-CUR-NEXT: movl %eax, 4(%rdi) -; CHECK-O0-CUR-NEXT: retq -; -; CHECK-O3-CUR-LABEL: vec_store_unaligned: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: vmovd %xmm0, %eax -; CHECK-O3-CUR-NEXT: vpextrd $1, %xmm0, %ecx -; CHECK-O3-CUR-NEXT: movl %eax, (%rdi) -; CHECK-O3-CUR-NEXT: movl %ecx, 4(%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O0-EX-LABEL: vec_store_unaligned: -; CHECK-O0-EX: # %bb.0: -; CHECK-O0-EX-NEXT: vmovd %xmm0, (%rdi) -; CHECK-O0-EX-NEXT: vpextrd $1, %xmm0, 4(%rdi) -; CHECK-O0-EX-NEXT: retq -; -; CHECK-O3-EX-LABEL: vec_store_unaligned: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: vmovss %xmm0, (%rdi) -; CHECK-O3-EX-NEXT: vextractps $1, %xmm0, 4(%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-O0-LABEL: vec_store_unaligned: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: vmovd %xmm0, %ecx +; CHECK-O0-NEXT: vpextrd $1, %xmm0, %eax +; CHECK-O0-NEXT: movl %ecx, (%rdi) +; CHECK-O0-NEXT: movl %eax, 4(%rdi) +; CHECK-O0-NEXT: retq +; +; CHECK-O3-LABEL: vec_store_unaligned: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: vmovd %xmm0, %eax +; CHECK-O3-NEXT: vpextrd $1, %xmm0, %ecx +; CHECK-O3-NEXT: movl %eax, (%rdi) +; CHECK-O3-NEXT: movl %ecx, 4(%rdi) +; CHECK-O3-NEXT: retq %v1 = extractelement <2 x i32> %vec, i32 0 %v2 = extractelement <2 x i32> %vec, i32 1 %p1 = getelementptr i32, ptr %p0, i64 1 @@ -485,31 +459,12 @@ define void @vec_store_unaligned(ptr %p0, <2 x i32> %vec) { ; Legal if wider type is also atomic (TODO) ; Also, can avoid register move from xmm to eax (TODO) define void @widen_broadcast2(ptr %p0, <2 x i32> %vec) { -; CHECK-O0-CUR-LABEL: widen_broadcast2: -; CHECK-O0-CUR: # %bb.0: -; CHECK-O0-CUR-NEXT: vmovd %xmm0, %eax -; CHECK-O0-CUR-NEXT: movl %eax, (%rdi) -; CHECK-O0-CUR-NEXT: movl %eax, 4(%rdi) -; CHECK-O0-CUR-NEXT: retq -; -; CHECK-O3-CUR-LABEL: widen_broadcast2: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: vmovd %xmm0, %eax -; CHECK-O3-CUR-NEXT: movl %eax, (%rdi) -; CHECK-O3-CUR-NEXT: movl %eax, 4(%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O0-EX-LABEL: widen_broadcast2: -; CHECK-O0-EX: # %bb.0: -; CHECK-O0-EX-NEXT: vmovd %xmm0, (%rdi) -; CHECK-O0-EX-NEXT: vmovd %xmm0, 4(%rdi) -; CHECK-O0-EX-NEXT: retq -; -; CHECK-O3-EX-LABEL: widen_broadcast2: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: vmovss %xmm0, (%rdi) -; CHECK-O3-EX-NEXT: vmovss %xmm0, 4(%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: widen_broadcast2: +; CHECK: # %bb.0: +; CHECK-NEXT: vmovd %xmm0, %eax +; CHECK-NEXT: movl %eax, (%rdi) +; CHECK-NEXT: movl %eax, 4(%rdi) +; CHECK-NEXT: retq %v1 = extractelement <2 x i32> %vec, i32 0 %p1 = getelementptr i32, ptr %p0, i64 1 store atomic i32 %v1, ptr %p0 unordered, align 8 @@ -519,31 +474,12 @@ define void @widen_broadcast2(ptr %p0, <2 x i32> %vec) { ; Not legal to widen due to alignment restriction define void @widen_broadcast2_unaligned(ptr %p0, <2 x i32> %vec) { -; CHECK-O0-CUR-LABEL: widen_broadcast2_unaligned: -; CHECK-O0-CUR: # %bb.0: -; CHECK-O0-CUR-NEXT: vmovd %xmm0, %eax -; CHECK-O0-CUR-NEXT: movl %eax, (%rdi) -; CHECK-O0-CUR-NEXT: movl %eax, 4(%rdi) -; CHECK-O0-CUR-NEXT: retq -; -; CHECK-O3-CUR-LABEL: widen_broadcast2_unaligned: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: vmovd %xmm0, %eax -; CHECK-O3-CUR-NEXT: movl %eax, (%rdi) -; CHECK-O3-CUR-NEXT: movl %eax, 4(%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O0-EX-LABEL: widen_broadcast2_unaligned: -; CHECK-O0-EX: # %bb.0: -; CHECK-O0-EX-NEXT: vmovd %xmm0, (%rdi) -; CHECK-O0-EX-NEXT: vmovd %xmm0, 4(%rdi) -; CHECK-O0-EX-NEXT: retq -; -; CHECK-O3-EX-LABEL: widen_broadcast2_unaligned: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: vmovss %xmm0, (%rdi) -; CHECK-O3-EX-NEXT: vmovss %xmm0, 4(%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: widen_broadcast2_unaligned: +; CHECK: # %bb.0: +; CHECK-NEXT: vmovd %xmm0, %eax +; CHECK-NEXT: movl %eax, (%rdi) +; CHECK-NEXT: movl %eax, 4(%rdi) +; CHECK-NEXT: retq %v1 = extractelement <2 x i32> %vec, i32 0 %p1 = getelementptr i32, ptr %p0, i64 1 store atomic i32 %v1, ptr %p0 unordered, align 4 @@ -610,17 +546,11 @@ define i64 @load_fold_add3(ptr %p1, ptr %p2) { ; CHECK-O0-NEXT: addq (%rsi), %rax ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: load_fold_add3: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rsi), %rax -; CHECK-O3-CUR-NEXT: addq (%rdi), %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_fold_add3: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq (%rdi), %rax -; CHECK-O3-EX-NEXT: addq (%rsi), %rax -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: load_fold_add3: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movq (%rsi), %rax +; CHECK-O3-NEXT: addq (%rdi), %rax +; CHECK-O3-NEXT: retq %v = load atomic i64, ptr %p1 unordered, align 8 %v2 = load atomic i64, ptr %p2 unordered, align 8 %ret = add i64 %v, %v2 @@ -704,17 +634,11 @@ define i64 @load_fold_mul3(ptr %p1, ptr %p2) { ; CHECK-O0-NEXT: imulq (%rsi), %rax ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: load_fold_mul3: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rsi), %rax -; CHECK-O3-CUR-NEXT: imulq (%rdi), %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_fold_mul3: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq (%rdi), %rax -; CHECK-O3-EX-NEXT: imulq (%rsi), %rax -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: load_fold_mul3: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movq (%rsi), %rax +; CHECK-O3-NEXT: imulq (%rdi), %rax +; CHECK-O3-NEXT: retq %v = load atomic i64, ptr %p1 unordered, align 8 %v2 = load atomic i64, ptr %p2 unordered, align 8 %ret = mul i64 %v, %v2 @@ -823,20 +747,13 @@ define i64 @load_fold_udiv1(ptr %p) { ; CHECK-O0-NEXT: divq %rcx ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: load_fold_udiv1: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rdi), %rdx -; CHECK-O3-CUR-NEXT: movabsq $-8608480567731124087, %rax # imm = 0x8888888888888889 -; CHECK-O3-CUR-NEXT: mulxq %rax, %rax, %rax -; CHECK-O3-CUR-NEXT: shrq $3, %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_fold_udiv1: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movabsq $-8608480567731124087, %rdx # imm = 0x8888888888888889 -; CHECK-O3-EX-NEXT: mulxq (%rdi), %rax, %rax -; CHECK-O3-EX-NEXT: shrq $3, %rax -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: load_fold_udiv1: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movq (%rdi), %rdx +; CHECK-O3-NEXT: movabsq $-8608480567731124087, %rax # imm = 0x8888888888888889 +; CHECK-O3-NEXT: mulxq %rax, %rax, %rax +; CHECK-O3-NEXT: shrq $3, %rax +; CHECK-O3-NEXT: retq %v = load atomic i64, ptr %p unordered, align 8 %ret = udiv i64 %v, 15 ret i64 %ret @@ -1288,17 +1205,11 @@ define i64 @load_fold_and3(ptr %p1, ptr %p2) { ; CHECK-O0-NEXT: andq (%rsi), %rax ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: load_fold_and3: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rsi), %rax -; CHECK-O3-CUR-NEXT: andq (%rdi), %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_fold_and3: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq (%rdi), %rax -; CHECK-O3-EX-NEXT: andq (%rsi), %rax -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: load_fold_and3: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movq (%rsi), %rax +; CHECK-O3-NEXT: andq (%rdi), %rax +; CHECK-O3-NEXT: retq %v = load atomic i64, ptr %p1 unordered, align 8 %v2 = load atomic i64, ptr %p2 unordered, align 8 %ret = and i64 %v, %v2 @@ -1335,17 +1246,11 @@ define i64 @load_fold_or3(ptr %p1, ptr %p2) { ; CHECK-O0-NEXT: orq (%rsi), %rax ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: load_fold_or3: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rsi), %rax -; CHECK-O3-CUR-NEXT: orq (%rdi), %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_fold_or3: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq (%rdi), %rax -; CHECK-O3-EX-NEXT: orq (%rsi), %rax -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: load_fold_or3: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movq (%rsi), %rax +; CHECK-O3-NEXT: orq (%rdi), %rax +; CHECK-O3-NEXT: retq %v = load atomic i64, ptr %p1 unordered, align 8 %v2 = load atomic i64, ptr %p2 unordered, align 8 %ret = or i64 %v, %v2 @@ -1382,17 +1287,11 @@ define i64 @load_fold_xor3(ptr %p1, ptr %p2) { ; CHECK-O0-NEXT: xorq (%rsi), %rax ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: load_fold_xor3: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rsi), %rax -; CHECK-O3-CUR-NEXT: xorq (%rdi), %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_fold_xor3: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq (%rdi), %rax -; CHECK-O3-EX-NEXT: xorq (%rsi), %rax -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: load_fold_xor3: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movq (%rsi), %rax +; CHECK-O3-NEXT: xorq (%rdi), %rax +; CHECK-O3-NEXT: retq %v = load atomic i64, ptr %p1 unordered, align 8 %v2 = load atomic i64, ptr %p2 unordered, align 8 %ret = xor i64 %v, %v2 @@ -1444,19 +1343,12 @@ define i1 @load_fold_icmp3(ptr %p1, ptr %p2) { ; CHECK-O0-NEXT: sete %al ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: load_fold_icmp3: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rsi), %rax -; CHECK-O3-CUR-NEXT: cmpq %rax, (%rdi) -; CHECK-O3-CUR-NEXT: sete %al -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_fold_icmp3: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq (%rdi), %rax -; CHECK-O3-EX-NEXT: cmpq (%rsi), %rax -; CHECK-O3-EX-NEXT: sete %al -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: load_fold_icmp3: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movq (%rsi), %rax +; CHECK-O3-NEXT: cmpq %rax, (%rdi) +; CHECK-O3-NEXT: sete %al +; CHECK-O3-NEXT: retq %v = load atomic i64, ptr %p1 unordered, align 8 %v2 = load atomic i64, ptr %p2 unordered, align 8 %ret = icmp eq i64 %v, %v2 @@ -1653,31 +1545,14 @@ define void @rmw_fold_sdiv2(ptr %p, i64 %v) { ; Legal, as expected define void @rmw_fold_udiv1(ptr %p, i64 %v) { -; CHECK-O0-LABEL: rmw_fold_udiv1: -; CHECK-O0: # %bb.0: -; CHECK-O0-NEXT: movq (%rdi), %rdx -; CHECK-O0-NEXT: movabsq $-8608480567731124087, %rax # imm = 0x8888888888888889 -; CHECK-O0-NEXT: mulxq %rax, %rax, %rax -; CHECK-O0-NEXT: shrq $3, %rax -; CHECK-O0-NEXT: movq %rax, (%rdi) -; CHECK-O0-NEXT: retq -; -; CHECK-O3-CUR-LABEL: rmw_fold_udiv1: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rdi), %rdx -; CHECK-O3-CUR-NEXT: movabsq $-8608480567731124087, %rax # imm = 0x8888888888888889 -; CHECK-O3-CUR-NEXT: mulxq %rax, %rax, %rax -; CHECK-O3-CUR-NEXT: shrq $3, %rax -; CHECK-O3-CUR-NEXT: movq %rax, (%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: rmw_fold_udiv1: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movabsq $-8608480567731124087, %rdx # imm = 0x8888888888888889 -; CHECK-O3-EX-NEXT: mulxq (%rdi), %rax, %rax -; CHECK-O3-EX-NEXT: shrq $3, %rax -; CHECK-O3-EX-NEXT: movq %rax, (%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: rmw_fold_udiv1: +; CHECK: # %bb.0: +; CHECK-NEXT: movq (%rdi), %rdx +; CHECK-NEXT: movabsq $-8608480567731124087, %rax # imm = 0x8888888888888889 +; CHECK-NEXT: mulxq %rax, %rax, %rax +; CHECK-NEXT: shrq $3, %rax +; CHECK-NEXT: movq %rax, (%rdi) +; CHECK-NEXT: retq %prev = load atomic i64, ptr %p unordered, align 8 %val = udiv i64 %prev, 15 store atomic i64 %val, ptr %p unordered, align 8 @@ -1868,24 +1743,12 @@ define void @rmw_fold_urem2(ptr %p, i64 %v) { ; Legal to fold (TODO) define void @rmw_fold_shl1(ptr %p, i64 %v) { -; CHECK-O0-LABEL: rmw_fold_shl1: -; CHECK-O0: # %bb.0: -; CHECK-O0-NEXT: movq (%rdi), %rax -; CHECK-O0-NEXT: shlq $15, %rax -; CHECK-O0-NEXT: movq %rax, (%rdi) -; CHECK-O0-NEXT: retq -; -; CHECK-O3-CUR-LABEL: rmw_fold_shl1: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rdi), %rax -; CHECK-O3-CUR-NEXT: shlq $15, %rax -; CHECK-O3-CUR-NEXT: movq %rax, (%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: rmw_fold_shl1: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: shlq $15, (%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: rmw_fold_shl1: +; CHECK: # %bb.0: +; CHECK-NEXT: movq (%rdi), %rax +; CHECK-NEXT: shlq $15, %rax +; CHECK-NEXT: movq %rax, (%rdi) +; CHECK-NEXT: retq %prev = load atomic i64, ptr %p unordered, align 8 %val = shl i64 %prev, 15 store atomic i64 %val, ptr %p unordered, align 8 @@ -1904,18 +1767,11 @@ define void @rmw_fold_shl2(ptr %p, i64 %v) { ; CHECK-O0-NEXT: movq %rax, (%rdi) ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: rmw_fold_shl2: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: shlxq %rsi, (%rdi), %rax -; CHECK-O3-CUR-NEXT: movq %rax, (%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: rmw_fold_shl2: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq %rsi, %rcx -; CHECK-O3-EX-NEXT: # kill: def $cl killed $cl killed $rcx -; CHECK-O3-EX-NEXT: shlq %cl, (%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: rmw_fold_shl2: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: shlxq %rsi, (%rdi), %rax +; CHECK-O3-NEXT: movq %rax, (%rdi) +; CHECK-O3-NEXT: retq %prev = load atomic i64, ptr %p unordered, align 8 %val = shl i64 %prev, %v store atomic i64 %val, ptr %p unordered, align 8 @@ -1924,24 +1780,12 @@ define void @rmw_fold_shl2(ptr %p, i64 %v) { ; Legal to fold (TODO) define void @rmw_fold_lshr1(ptr %p, i64 %v) { -; CHECK-O0-LABEL: rmw_fold_lshr1: -; CHECK-O0: # %bb.0: -; CHECK-O0-NEXT: movq (%rdi), %rax -; CHECK-O0-NEXT: shrq $15, %rax -; CHECK-O0-NEXT: movq %rax, (%rdi) -; CHECK-O0-NEXT: retq -; -; CHECK-O3-CUR-LABEL: rmw_fold_lshr1: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rdi), %rax -; CHECK-O3-CUR-NEXT: shrq $15, %rax -; CHECK-O3-CUR-NEXT: movq %rax, (%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: rmw_fold_lshr1: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: shrq $15, (%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: rmw_fold_lshr1: +; CHECK: # %bb.0: +; CHECK-NEXT: movq (%rdi), %rax +; CHECK-NEXT: shrq $15, %rax +; CHECK-NEXT: movq %rax, (%rdi) +; CHECK-NEXT: retq %prev = load atomic i64, ptr %p unordered, align 8 %val = lshr i64 %prev, 15 store atomic i64 %val, ptr %p unordered, align 8 @@ -1960,18 +1804,11 @@ define void @rmw_fold_lshr2(ptr %p, i64 %v) { ; CHECK-O0-NEXT: movq %rax, (%rdi) ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: rmw_fold_lshr2: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: shrxq %rsi, (%rdi), %rax -; CHECK-O3-CUR-NEXT: movq %rax, (%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: rmw_fold_lshr2: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq %rsi, %rcx -; CHECK-O3-EX-NEXT: # kill: def $cl killed $cl killed $rcx -; CHECK-O3-EX-NEXT: shrq %cl, (%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: rmw_fold_lshr2: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: shrxq %rsi, (%rdi), %rax +; CHECK-O3-NEXT: movq %rax, (%rdi) +; CHECK-O3-NEXT: retq %prev = load atomic i64, ptr %p unordered, align 8 %val = lshr i64 %prev, %v store atomic i64 %val, ptr %p unordered, align 8 @@ -1980,24 +1817,12 @@ define void @rmw_fold_lshr2(ptr %p, i64 %v) { ; Legal to fold (TODO) define void @rmw_fold_ashr1(ptr %p, i64 %v) { -; CHECK-O0-LABEL: rmw_fold_ashr1: -; CHECK-O0: # %bb.0: -; CHECK-O0-NEXT: movq (%rdi), %rax -; CHECK-O0-NEXT: sarq $15, %rax -; CHECK-O0-NEXT: movq %rax, (%rdi) -; CHECK-O0-NEXT: retq -; -; CHECK-O3-CUR-LABEL: rmw_fold_ashr1: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rdi), %rax -; CHECK-O3-CUR-NEXT: sarq $15, %rax -; CHECK-O3-CUR-NEXT: movq %rax, (%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: rmw_fold_ashr1: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: sarq $15, (%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: rmw_fold_ashr1: +; CHECK: # %bb.0: +; CHECK-NEXT: movq (%rdi), %rax +; CHECK-NEXT: sarq $15, %rax +; CHECK-NEXT: movq %rax, (%rdi) +; CHECK-NEXT: retq %prev = load atomic i64, ptr %p unordered, align 8 %val = ashr i64 %prev, 15 store atomic i64 %val, ptr %p unordered, align 8 @@ -2016,18 +1841,11 @@ define void @rmw_fold_ashr2(ptr %p, i64 %v) { ; CHECK-O0-NEXT: movq %rax, (%rdi) ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: rmw_fold_ashr2: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: sarxq %rsi, (%rdi), %rax -; CHECK-O3-CUR-NEXT: movq %rax, (%rdi) -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: rmw_fold_ashr2: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq %rsi, %rcx -; CHECK-O3-EX-NEXT: # kill: def $cl killed $cl killed $rcx -; CHECK-O3-EX-NEXT: sarq %cl, (%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: rmw_fold_ashr2: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: sarxq %rsi, (%rdi), %rax +; CHECK-O3-NEXT: movq %rax, (%rdi) +; CHECK-O3-NEXT: retq %prev = load atomic i64, ptr %p unordered, align 8 %val = ashr i64 %prev, %v store atomic i64 %val, ptr %p unordered, align 8 @@ -2391,26 +2209,12 @@ define i64 @fold_constant(i64 %arg) { } define i64 @fold_constant_clobber(ptr %p, i64 %arg) { -; CHECK-O0-LABEL: fold_constant_clobber: -; CHECK-O0: # %bb.0: -; CHECK-O0-NEXT: movq Constant(%rip), %rax -; CHECK-O0-NEXT: movq $5, (%rdi) -; CHECK-O0-NEXT: addq %rsi, %rax -; CHECK-O0-NEXT: retq -; -; CHECK-O3-CUR-LABEL: fold_constant_clobber: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq Constant(%rip), %rax -; CHECK-O3-CUR-NEXT: movq $5, (%rdi) -; CHECK-O3-CUR-NEXT: addq %rsi, %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: fold_constant_clobber: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq %rsi, %rax -; CHECK-O3-EX-NEXT: addq Constant(%rip), %rax -; CHECK-O3-EX-NEXT: movq $5, (%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: fold_constant_clobber: +; CHECK: # %bb.0: +; CHECK-NEXT: movq Constant(%rip), %rax +; CHECK-NEXT: movq $5, (%rdi) +; CHECK-NEXT: addq %rsi, %rax +; CHECK-NEXT: retq %v = load atomic i64, ptr @Constant unordered, align 8 store i64 5, ptr %p %ret = add i64 %v, %arg @@ -2418,26 +2222,12 @@ define i64 @fold_constant_clobber(ptr %p, i64 %arg) { } define i64 @fold_constant_fence(i64 %arg) { -; CHECK-O0-LABEL: fold_constant_fence: -; CHECK-O0: # %bb.0: -; CHECK-O0-NEXT: movq Constant(%rip), %rax -; CHECK-O0-NEXT: mfence -; CHECK-O0-NEXT: addq %rdi, %rax -; CHECK-O0-NEXT: retq -; -; CHECK-O3-CUR-LABEL: fold_constant_fence: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq Constant(%rip), %rax -; CHECK-O3-CUR-NEXT: mfence -; CHECK-O3-CUR-NEXT: addq %rdi, %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: fold_constant_fence: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq %rdi, %rax -; CHECK-O3-EX-NEXT: addq Constant(%rip), %rax -; CHECK-O3-EX-NEXT: mfence -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: fold_constant_fence: +; CHECK: # %bb.0: +; CHECK-NEXT: movq Constant(%rip), %rax +; CHECK-NEXT: mfence +; CHECK-NEXT: addq %rdi, %rax +; CHECK-NEXT: retq %v = load atomic i64, ptr @Constant unordered, align 8 fence seq_cst %ret = add i64 %v, %arg @@ -2445,26 +2235,12 @@ define i64 @fold_constant_fence(i64 %arg) { } define i64 @fold_invariant_clobber(ptr dereferenceable(8) %p, i64 %arg) { -; CHECK-O0-LABEL: fold_invariant_clobber: -; CHECK-O0: # %bb.0: -; CHECK-O0-NEXT: movq (%rdi), %rax -; CHECK-O0-NEXT: movq $5, (%rdi) -; CHECK-O0-NEXT: addq %rsi, %rax -; CHECK-O0-NEXT: retq -; -; CHECK-O3-CUR-LABEL: fold_invariant_clobber: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rdi), %rax -; CHECK-O3-CUR-NEXT: movq $5, (%rdi) -; CHECK-O3-CUR-NEXT: addq %rsi, %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: fold_invariant_clobber: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq %rsi, %rax -; CHECK-O3-EX-NEXT: addq (%rdi), %rax -; CHECK-O3-EX-NEXT: movq $5, (%rdi) -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: fold_invariant_clobber: +; CHECK: # %bb.0: +; CHECK-NEXT: movq (%rdi), %rax +; CHECK-NEXT: movq $5, (%rdi) +; CHECK-NEXT: addq %rsi, %rax +; CHECK-NEXT: retq %v = load atomic i64, ptr %p unordered, align 8, !invariant.load !{} store i64 5, ptr %p %ret = add i64 %v, %arg @@ -2473,26 +2249,12 @@ define i64 @fold_invariant_clobber(ptr dereferenceable(8) %p, i64 %arg) { define i64 @fold_invariant_fence(ptr dereferenceable(8) %p, i64 %arg) { -; CHECK-O0-LABEL: fold_invariant_fence: -; CHECK-O0: # %bb.0: -; CHECK-O0-NEXT: movq (%rdi), %rax -; CHECK-O0-NEXT: mfence -; CHECK-O0-NEXT: addq %rsi, %rax -; CHECK-O0-NEXT: retq -; -; CHECK-O3-CUR-LABEL: fold_invariant_fence: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movq (%rdi), %rax -; CHECK-O3-CUR-NEXT: mfence -; CHECK-O3-CUR-NEXT: addq %rsi, %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: fold_invariant_fence: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: movq %rsi, %rax -; CHECK-O3-EX-NEXT: addq (%rdi), %rax -; CHECK-O3-EX-NEXT: mfence -; CHECK-O3-EX-NEXT: retq +; CHECK-LABEL: fold_invariant_fence: +; CHECK: # %bb.0: +; CHECK-NEXT: movq (%rdi), %rax +; CHECK-NEXT: mfence +; CHECK-NEXT: addq %rsi, %rax +; CHECK-NEXT: retq %v = load atomic i64, ptr %p unordered, align 8, !invariant.load !{} fence seq_cst %ret = add i64 %v, %arg @@ -2503,32 +2265,18 @@ define i64 @fold_invariant_fence(ptr dereferenceable(8) %p, i64 %arg) { ; Exercise a few cases involving any extend idioms define i16 @load_i8_anyext_i16(ptr %ptr) { -; CHECK-O0-CUR-LABEL: load_i8_anyext_i16: -; CHECK-O0-CUR: # %bb.0: -; CHECK-O0-CUR-NEXT: movb (%rdi), %al -; CHECK-O0-CUR-NEXT: movzbl %al, %eax -; CHECK-O0-CUR-NEXT: # kill: def $ax killed $ax killed $eax -; CHECK-O0-CUR-NEXT: retq -; -; CHECK-O3-CUR-LABEL: load_i8_anyext_i16: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movzbl (%rdi), %eax -; CHECK-O3-CUR-NEXT: # kill: def $ax killed $ax killed $eax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O0-EX-LABEL: load_i8_anyext_i16: -; CHECK-O0-EX: # %bb.0: -; CHECK-O0-EX-NEXT: vpbroadcastb (%rdi), %xmm0 -; CHECK-O0-EX-NEXT: vmovd %xmm0, %eax -; CHECK-O0-EX-NEXT: # kill: def $ax killed $ax killed $eax -; CHECK-O0-EX-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_i8_anyext_i16: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: vpbroadcastb (%rdi), %xmm0 -; CHECK-O3-EX-NEXT: vmovd %xmm0, %eax -; CHECK-O3-EX-NEXT: # kill: def $ax killed $ax killed $eax -; CHECK-O3-EX-NEXT: retq +; CHECK-O0-LABEL: load_i8_anyext_i16: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: movb (%rdi), %al +; CHECK-O0-NEXT: movzbl %al, %eax +; CHECK-O0-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-O0-NEXT: retq +; +; CHECK-O3-LABEL: load_i8_anyext_i16: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movzbl (%rdi), %eax +; CHECK-O3-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-O3-NEXT: retq %v = load atomic i8, ptr %ptr unordered, align 2 %vec = insertelement <2 x i8> undef, i8 %v, i32 0 %res = bitcast <2 x i8> %vec to i16 @@ -2536,28 +2284,16 @@ define i16 @load_i8_anyext_i16(ptr %ptr) { } define i32 @load_i8_anyext_i32(ptr %ptr) { -; CHECK-O0-CUR-LABEL: load_i8_anyext_i32: -; CHECK-O0-CUR: # %bb.0: -; CHECK-O0-CUR-NEXT: movb (%rdi), %al -; CHECK-O0-CUR-NEXT: movzbl %al, %eax -; CHECK-O0-CUR-NEXT: retq -; -; CHECK-O3-CUR-LABEL: load_i8_anyext_i32: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movzbl (%rdi), %eax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O0-EX-LABEL: load_i8_anyext_i32: -; CHECK-O0-EX: # %bb.0: -; CHECK-O0-EX-NEXT: vpbroadcastb (%rdi), %xmm0 -; CHECK-O0-EX-NEXT: vmovd %xmm0, %eax -; CHECK-O0-EX-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_i8_anyext_i32: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: vpbroadcastb (%rdi), %xmm0 -; CHECK-O3-EX-NEXT: vmovd %xmm0, %eax -; CHECK-O3-EX-NEXT: retq +; CHECK-O0-LABEL: load_i8_anyext_i32: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: movb (%rdi), %al +; CHECK-O0-NEXT: movzbl %al, %eax +; CHECK-O0-NEXT: retq +; +; CHECK-O3-LABEL: load_i8_anyext_i32: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movzbl (%rdi), %eax +; CHECK-O3-NEXT: retq %v = load atomic i8, ptr %ptr unordered, align 4 %vec = insertelement <4 x i8> undef, i8 %v, i32 0 %res = bitcast <4 x i8> %vec to i32 @@ -2565,29 +2301,17 @@ define i32 @load_i8_anyext_i32(ptr %ptr) { } define i32 @load_i16_anyext_i32(ptr %ptr) { -; CHECK-O0-CUR-LABEL: load_i16_anyext_i32: -; CHECK-O0-CUR: # %bb.0: -; CHECK-O0-CUR-NEXT: movw (%rdi), %cx -; CHECK-O0-CUR-NEXT: # implicit-def: $eax -; CHECK-O0-CUR-NEXT: movw %cx, %ax -; CHECK-O0-CUR-NEXT: retq -; -; CHECK-O3-CUR-LABEL: load_i16_anyext_i32: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movzwl (%rdi), %eax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O0-EX-LABEL: load_i16_anyext_i32: -; CHECK-O0-EX: # %bb.0: -; CHECK-O0-EX-NEXT: vpbroadcastw (%rdi), %xmm0 -; CHECK-O0-EX-NEXT: vmovd %xmm0, %eax -; CHECK-O0-EX-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_i16_anyext_i32: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: vpbroadcastw (%rdi), %xmm0 -; CHECK-O3-EX-NEXT: vmovd %xmm0, %eax -; CHECK-O3-EX-NEXT: retq +; CHECK-O0-LABEL: load_i16_anyext_i32: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: movw (%rdi), %cx +; CHECK-O0-NEXT: # implicit-def: $eax +; CHECK-O0-NEXT: movw %cx, %ax +; CHECK-O0-NEXT: retq +; +; CHECK-O3-LABEL: load_i16_anyext_i32: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movzwl (%rdi), %eax +; CHECK-O3-NEXT: retq %v = load atomic i16, ptr %ptr unordered, align 4 %vec = insertelement <2 x i16> undef, i16 %v, i64 0 %res = bitcast <2 x i16> %vec to i32 @@ -2595,33 +2319,21 @@ define i32 @load_i16_anyext_i32(ptr %ptr) { } define i64 @load_i16_anyext_i64(ptr %ptr) { -; CHECK-O0-CUR-LABEL: load_i16_anyext_i64: -; CHECK-O0-CUR: # %bb.0: -; CHECK-O0-CUR-NEXT: movw (%rdi), %cx -; CHECK-O0-CUR-NEXT: # implicit-def: $eax -; CHECK-O0-CUR-NEXT: movw %cx, %ax -; CHECK-O0-CUR-NEXT: vmovd %eax, %xmm0 -; CHECK-O0-CUR-NEXT: vmovq %xmm0, %rax -; CHECK-O0-CUR-NEXT: retq -; -; CHECK-O3-CUR-LABEL: load_i16_anyext_i64: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movzwl (%rdi), %eax -; CHECK-O3-CUR-NEXT: vmovd %eax, %xmm0 -; CHECK-O3-CUR-NEXT: vmovq %xmm0, %rax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O0-EX-LABEL: load_i16_anyext_i64: -; CHECK-O0-EX: # %bb.0: -; CHECK-O0-EX-NEXT: vpbroadcastw (%rdi), %xmm0 -; CHECK-O0-EX-NEXT: vmovq %xmm0, %rax -; CHECK-O0-EX-NEXT: retq -; -; CHECK-O3-EX-LABEL: load_i16_anyext_i64: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: vpbroadcastw (%rdi), %xmm0 -; CHECK-O3-EX-NEXT: vmovq %xmm0, %rax -; CHECK-O3-EX-NEXT: retq +; CHECK-O0-LABEL: load_i16_anyext_i64: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: movw (%rdi), %cx +; CHECK-O0-NEXT: # implicit-def: $eax +; CHECK-O0-NEXT: movw %cx, %ax +; CHECK-O0-NEXT: vmovd %eax, %xmm0 +; CHECK-O0-NEXT: vmovq %xmm0, %rax +; CHECK-O0-NEXT: retq +; +; CHECK-O3-LABEL: load_i16_anyext_i64: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movzwl (%rdi), %eax +; CHECK-O3-NEXT: vmovd %eax, %xmm0 +; CHECK-O3-NEXT: vmovq %xmm0, %rax +; CHECK-O3-NEXT: retq %v = load atomic i16, ptr %ptr unordered, align 8 %vec = insertelement <4 x i16> undef, i16 %v, i64 0 %res = bitcast <4 x i16> %vec to i64 @@ -2675,30 +2387,18 @@ define i1 @fold_cmp_over_fence(ptr %p, i32 %v1) { ; CHECK-O0-NEXT: # kill: def $al killed $al killed $eax ; CHECK-O0-NEXT: retq ; -; CHECK-O3-CUR-LABEL: fold_cmp_over_fence: -; CHECK-O3-CUR: # %bb.0: -; CHECK-O3-CUR-NEXT: movl (%rdi), %eax -; CHECK-O3-CUR-NEXT: mfence -; CHECK-O3-CUR-NEXT: cmpl %eax, %esi -; CHECK-O3-CUR-NEXT: jne .LBB116_2 -; CHECK-O3-CUR-NEXT: # %bb.1: # %taken -; CHECK-O3-CUR-NEXT: movb $1, %al -; CHECK-O3-CUR-NEXT: retq -; CHECK-O3-CUR-NEXT: .LBB116_2: # %untaken -; CHECK-O3-CUR-NEXT: xorl %eax, %eax -; CHECK-O3-CUR-NEXT: retq -; -; CHECK-O3-EX-LABEL: fold_cmp_over_fence: -; CHECK-O3-EX: # %bb.0: -; CHECK-O3-EX-NEXT: cmpl (%rdi), %esi -; CHECK-O3-EX-NEXT: mfence -; CHECK-O3-EX-NEXT: jne .LBB116_2 -; CHECK-O3-EX-NEXT: # %bb.1: # %taken -; CHECK-O3-EX-NEXT: movb $1, %al -; CHECK-O3-EX-NEXT: retq -; CHECK-O3-EX-NEXT: .LBB116_2: # %untaken -; CHECK-O3-EX-NEXT: xorl %eax, %eax -; CHECK-O3-EX-NEXT: retq +; CHECK-O3-LABEL: fold_cmp_over_fence: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movl (%rdi), %eax +; CHECK-O3-NEXT: mfence +; CHECK-O3-NEXT: cmpl %eax, %esi +; CHECK-O3-NEXT: jne .LBB116_2 +; CHECK-O3-NEXT: # %bb.1: # %taken +; CHECK-O3-NEXT: movb $1, %al +; CHECK-O3-NEXT: retq +; CHECK-O3-NEXT: .LBB116_2: # %untaken +; CHECK-O3-NEXT: xorl %eax, %eax +; CHECK-O3-NEXT: retq %v2 = load atomic i32, ptr %p unordered, align 4 fence seq_cst %cmp = icmp eq i32 %v1, %v2 diff --git a/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll b/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll index 8879f04687ba..d2d88d6b7571 100644 --- a/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll +++ b/llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll @@ -4,7 +4,7 @@ ; Test that we can unfold constant pool loads when we're using avx512's ; ability to fold a broadcast load into an operation. -define void @bcast_unfold_add_v16i32(i32* %arg) { +define void @bcast_unfold_add_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_add_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -24,12 +24,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <16 x i32>* - %tmp5 = load <16 x i32>, <16 x i32>* %tmp4, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <16 x i32>, ptr %tmp3, align 4 %tmp6 = add nsw <16 x i32> %tmp5, - %tmp7 = bitcast i32* %tmp3 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp3, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -38,7 +36,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_add_v8i32(i32* %arg) { +define void @bcast_unfold_add_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_add_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -58,12 +56,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <8 x i32>* - %tmp5 = load <8 x i32>, <8 x i32>* %tmp4, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <8 x i32>, ptr %tmp3, align 4 %tmp6 = add nsw <8 x i32> %tmp5, - %tmp7 = bitcast i32* %tmp3 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp3, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -72,7 +68,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_add_v4i32(i32* %arg) { +define void @bcast_unfold_add_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_add_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -91,12 +87,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <4 x i32>* - %tmp5 = load <4 x i32>, <4 x i32>* %tmp4, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <4 x i32>, ptr %tmp3, align 4 %tmp6 = add nsw <4 x i32> %tmp5, - %tmp7 = bitcast i32* %tmp3 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp3, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -105,7 +99,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_add_v8i64(i64* %arg) { +define void @bcast_unfold_add_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_add_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -125,12 +119,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp4 = bitcast i64* %tmp3 to <8 x i64>* - %tmp5 = load <8 x i64>, <8 x i64>* %tmp4, align 8 + %tmp3 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp5 = load <8 x i64>, ptr %tmp3, align 8 %tmp6 = add nsw <8 x i64> %tmp5, - %tmp7 = bitcast i64* %tmp3 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 8 + store <8 x i64> %tmp6, ptr %tmp3, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -139,7 +131,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_add_v4i64(i64* %arg) { +define void @bcast_unfold_add_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_add_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -159,12 +151,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp4 = bitcast i64* %tmp3 to <4 x i64>* - %tmp5 = load <4 x i64>, <4 x i64>* %tmp4, align 8 + %tmp3 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp5 = load <4 x i64>, ptr %tmp3, align 8 %tmp6 = add nsw <4 x i64> %tmp5, - %tmp7 = bitcast i64* %tmp3 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 8 + store <4 x i64> %tmp6, ptr %tmp3, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -173,7 +163,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_add_v2i64(i64* %arg) { +define void @bcast_unfold_add_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_add_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -192,12 +182,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp4 = bitcast i64* %tmp3 to <2 x i64>* - %tmp5 = load <2 x i64>, <2 x i64>* %tmp4, align 8 + %tmp3 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp5 = load <2 x i64>, ptr %tmp3, align 8 %tmp6 = add nsw <2 x i64> %tmp5, - %tmp7 = bitcast i64* %tmp3 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 8 + store <2 x i64> %tmp6, ptr %tmp3, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -206,7 +194,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_mul_v16i32(i32* %arg) { +define void @bcast_unfold_mul_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_mul_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -227,12 +215,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <16 x i32>* - %tmp5 = load <16 x i32>, <16 x i32>* %tmp4, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <16 x i32>, ptr %tmp3, align 4 %tmp6 = mul nsw <16 x i32> %tmp5, - %tmp7 = bitcast i32* %tmp3 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp3, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -241,7 +227,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_mul_v8i32(i32* %arg) { +define void @bcast_unfold_mul_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_mul_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -262,12 +248,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <8 x i32>* - %tmp5 = load <8 x i32>, <8 x i32>* %tmp4, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <8 x i32>, ptr %tmp3, align 4 %tmp6 = mul nsw <8 x i32> %tmp5, - %tmp7 = bitcast i32* %tmp3 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp3, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -276,7 +260,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_mul_v4i32(i32* %arg) { +define void @bcast_unfold_mul_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_mul_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -296,12 +280,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <4 x i32>* - %tmp5 = load <4 x i32>, <4 x i32>* %tmp4, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <4 x i32>, ptr %tmp3, align 4 %tmp6 = mul nsw <4 x i32> %tmp5, - %tmp7 = bitcast i32* %tmp3 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp3, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -310,7 +292,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_mul_v8i64(i64* %arg) { +define void @bcast_unfold_mul_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_mul_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -331,12 +313,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp4 = bitcast i64* %tmp3 to <8 x i64>* - %tmp5 = load <8 x i64>, <8 x i64>* %tmp4, align 8 + %tmp3 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp5 = load <8 x i64>, ptr %tmp3, align 8 %tmp6 = mul nsw <8 x i64> %tmp5, - %tmp7 = bitcast i64* %tmp3 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 8 + store <8 x i64> %tmp6, ptr %tmp3, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -345,7 +325,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_mul_v4i64(i64* %arg) { +define void @bcast_unfold_mul_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_mul_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -366,12 +346,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp4 = bitcast i64* %tmp3 to <4 x i64>* - %tmp5 = load <4 x i64>, <4 x i64>* %tmp4, align 8 + %tmp3 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp5 = load <4 x i64>, ptr %tmp3, align 8 %tmp6 = mul nsw <4 x i64> %tmp5, - %tmp7 = bitcast i64* %tmp3 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 8 + store <4 x i64> %tmp6, ptr %tmp3, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -380,7 +358,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_mul_v2i64(i64* %arg) { +define void @bcast_unfold_mul_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_mul_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -400,12 +378,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp4 = bitcast i64* %tmp3 to <2 x i64>* - %tmp5 = load <2 x i64>, <2 x i64>* %tmp4, align 8 + %tmp3 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp5 = load <2 x i64>, ptr %tmp3, align 8 %tmp6 = mul nsw <2 x i64> %tmp5, - %tmp7 = bitcast i64* %tmp3 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 8 + store <2 x i64> %tmp6, ptr %tmp3, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -414,7 +390,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_or_v16i32(i32* %arg) { +define void @bcast_unfold_or_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_or_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -434,12 +410,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <16 x i32>* - %tmp5 = load <16 x i32>, <16 x i32>* %tmp4, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <16 x i32>, ptr %tmp3, align 4 %tmp6 = or <16 x i32> %tmp5, - %tmp7 = bitcast i32* %tmp3 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp3, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -448,7 +422,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_or_v8i32(i32* %arg) { +define void @bcast_unfold_or_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_or_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -468,12 +442,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <8 x i32>* - %tmp5 = load <8 x i32>, <8 x i32>* %tmp4, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <8 x i32>, ptr %tmp3, align 4 %tmp6 = or <8 x i32> %tmp5, - %tmp7 = bitcast i32* %tmp3 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp3, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -482,7 +454,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_or_v4i32(i32* %arg) { +define void @bcast_unfold_or_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_or_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -501,12 +473,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <4 x i32>* - %tmp5 = load <4 x i32>, <4 x i32>* %tmp4, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <4 x i32>, ptr %tmp3, align 4 %tmp6 = or <4 x i32> %tmp5, - %tmp7 = bitcast i32* %tmp3 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp3, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -515,7 +485,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_or_v8i64(i64* %arg) { +define void @bcast_unfold_or_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_or_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -535,12 +505,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp4 = bitcast i64* %tmp3 to <8 x i64>* - %tmp5 = load <8 x i64>, <8 x i64>* %tmp4, align 8 + %tmp3 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp5 = load <8 x i64>, ptr %tmp3, align 8 %tmp6 = or <8 x i64> %tmp5, - %tmp7 = bitcast i64* %tmp3 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 8 + store <8 x i64> %tmp6, ptr %tmp3, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -549,7 +517,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_or_v4i64(i64* %arg) { +define void @bcast_unfold_or_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_or_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -569,12 +537,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp4 = bitcast i64* %tmp3 to <4 x i64>* - %tmp5 = load <4 x i64>, <4 x i64>* %tmp4, align 8 + %tmp3 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp5 = load <4 x i64>, ptr %tmp3, align 8 %tmp6 = or <4 x i64> %tmp5, - %tmp7 = bitcast i64* %tmp3 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 8 + store <4 x i64> %tmp6, ptr %tmp3, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -583,7 +549,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_or_v2i64(i64* %arg) { +define void @bcast_unfold_or_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_or_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -603,12 +569,10 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb2 ] - %tmp3 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp4 = bitcast i64* %tmp3 to <2 x i64>* - %tmp5 = load <2 x i64>, <2 x i64>* %tmp4, align 8 + %tmp3 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp5 = load <2 x i64>, ptr %tmp3, align 8 %tmp6 = or <2 x i64> %tmp5, - %tmp7 = bitcast i64* %tmp3 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 8 + store <2 x i64> %tmp6, ptr %tmp3, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb2 @@ -617,7 +581,7 @@ bb10: ; preds = %bb2 ret void } -define void @bcast_unfold_fneg_v16f32(float* %arg) { +define void @bcast_unfold_fneg_v16f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fneg_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -637,12 +601,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <16 x float>* - %tmp4 = load <16 x float>, <16 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <16 x float>, ptr %tmp2, align 4 %tmp5 = fneg <16 x float> %tmp4 - %tmp6 = bitcast float* %tmp2 to <16 x float>* - store <16 x float> %tmp5, <16 x float>* %tmp6, align 4 + store <16 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 16 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -651,7 +613,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fneg_v8f32(float* %arg) { +define void @bcast_unfold_fneg_v8f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fneg_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -671,12 +633,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <8 x float>* - %tmp4 = load <8 x float>, <8 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <8 x float>, ptr %tmp2, align 4 %tmp5 = fneg <8 x float> %tmp4 - %tmp6 = bitcast float* %tmp2 to <8 x float>* - store <8 x float> %tmp5, <8 x float>* %tmp6, align 4 + store <8 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -685,7 +645,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fneg_v4f32(float* %arg) { +define void @bcast_unfold_fneg_v4f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fneg_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -704,12 +664,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <4 x float>* - %tmp4 = load <4 x float>, <4 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <4 x float>, ptr %tmp2, align 4 %tmp5 = fneg <4 x float> %tmp4 - %tmp6 = bitcast float* %tmp2 to <4 x float>* - store <4 x float> %tmp5, <4 x float>* %tmp6, align 4 + store <4 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -718,7 +676,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fneg_v8f64(double* %arg) { +define void @bcast_unfold_fneg_v8f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fneg_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -738,12 +696,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <8 x double>* - %tmp4 = load <8 x double>, <8 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <8 x double>, ptr %tmp2, align 8 %tmp5 = fneg <8 x double> %tmp4 - %tmp6 = bitcast double* %tmp2 to <8 x double>* - store <8 x double> %tmp5, <8 x double>* %tmp6, align 8 + store <8 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -752,7 +708,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fneg_v4f64(double* %arg) { +define void @bcast_unfold_fneg_v4f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fneg_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -772,12 +728,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <4 x double>* - %tmp4 = load <4 x double>, <4 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <4 x double>, ptr %tmp2, align 8 %tmp5 = fneg <4 x double> %tmp4 - %tmp6 = bitcast double* %tmp2 to <4 x double>* - store <4 x double> %tmp5, <4 x double>* %tmp6, align 8 + store <4 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -786,7 +740,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fneg_v2f64(double* %arg) { +define void @bcast_unfold_fneg_v2f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fneg_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -806,12 +760,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <2 x double>* - %tmp4 = load <2 x double>, <2 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <2 x double>, ptr %tmp2, align 8 %tmp5 = fneg <2 x double> %tmp4 - %tmp6 = bitcast double* %tmp2 to <2 x double>* - store <2 x double> %tmp5, <2 x double>* %tmp6, align 8 + store <2 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 2 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -820,7 +772,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fabs_v16f32(float* %arg) { +define void @bcast_unfold_fabs_v16f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fabs_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -840,12 +792,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <16 x float>* - %tmp4 = load <16 x float>, <16 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <16 x float>, ptr %tmp2, align 4 %tmp5 = call <16 x float> @llvm.fabs.v16f32(<16 x float> %tmp4) - %tmp6 = bitcast float* %tmp2 to <16 x float>* - store <16 x float> %tmp5, <16 x float>* %tmp6, align 4 + store <16 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 16 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -854,10 +804,10 @@ bb9: ; preds = %bb1 ret void } -; Function Attrs: nounwind readnone speculatable willreturn +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare <16 x float> @llvm.fabs.v16f32(<16 x float>) #0 -define void @bcast_unfold_fabs_v8f32(float* %arg) { +define void @bcast_unfold_fabs_v8f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fabs_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -877,12 +827,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <8 x float>* - %tmp4 = load <8 x float>, <8 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <8 x float>, ptr %tmp2, align 4 %tmp5 = call <8 x float> @llvm.fabs.v8f32(<8 x float> %tmp4) - %tmp6 = bitcast float* %tmp2 to <8 x float>* - store <8 x float> %tmp5, <8 x float>* %tmp6, align 4 + store <8 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -891,10 +839,10 @@ bb9: ; preds = %bb1 ret void } -; Function Attrs: nounwind readnone speculatable willreturn +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare <8 x float> @llvm.fabs.v8f32(<8 x float>) #0 -define void @bcast_unfold_fabs_v4f32(float* %arg) { +define void @bcast_unfold_fabs_v4f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fabs_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -913,12 +861,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <4 x float>* - %tmp4 = load <4 x float>, <4 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <4 x float>, ptr %tmp2, align 4 %tmp5 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %tmp4) - %tmp6 = bitcast float* %tmp2 to <4 x float>* - store <4 x float> %tmp5, <4 x float>* %tmp6, align 4 + store <4 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -927,10 +873,10 @@ bb9: ; preds = %bb1 ret void } -; Function Attrs: nounwind readnone speculatable willreturn +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #0 -define void @bcast_unfold_fabs_v8f64(double* %arg) { +define void @bcast_unfold_fabs_v8f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fabs_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -950,12 +896,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <8 x double>* - %tmp4 = load <8 x double>, <8 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <8 x double>, ptr %tmp2, align 8 %tmp5 = call <8 x double> @llvm.fabs.v8f64(<8 x double> %tmp4) - %tmp6 = bitcast double* %tmp2 to <8 x double>* - store <8 x double> %tmp5, <8 x double>* %tmp6, align 8 + store <8 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -964,10 +908,10 @@ bb9: ; preds = %bb1 ret void } -; Function Attrs: nounwind readnone speculatable willreturn +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare <8 x double> @llvm.fabs.v8f64(<8 x double>) #0 -define void @bcast_unfold_fabs_v4f64(double* %arg) { +define void @bcast_unfold_fabs_v4f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fabs_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -987,12 +931,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <4 x double>* - %tmp4 = load <4 x double>, <4 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <4 x double>, ptr %tmp2, align 8 %tmp5 = call <4 x double> @llvm.fabs.v4f64(<4 x double> %tmp4) - %tmp6 = bitcast double* %tmp2 to <4 x double>* - store <4 x double> %tmp5, <4 x double>* %tmp6, align 8 + store <4 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1001,10 +943,10 @@ bb9: ; preds = %bb1 ret void } -; Function Attrs: nounwind readnone speculatable willreturn +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare <4 x double> @llvm.fabs.v4f64(<4 x double>) #0 -define void @bcast_unfold_fabs_v2f64(double* %arg) { +define void @bcast_unfold_fabs_v2f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fabs_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1024,12 +966,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <2 x double>* - %tmp4 = load <2 x double>, <2 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <2 x double>, ptr %tmp2, align 8 %tmp5 = call <2 x double> @llvm.fabs.v2f64(<2 x double> %tmp4) - %tmp6 = bitcast double* %tmp2 to <2 x double>* - store <2 x double> %tmp5, <2 x double>* %tmp6, align 8 + store <2 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 2 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1038,10 +978,10 @@ bb9: ; preds = %bb1 ret void } -; Function Attrs: nounwind readnone speculatable willreturn +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare <2 x double> @llvm.fabs.v2f64(<2 x double>) #0 -define void @bcast_unfold_fadd_v16f32(float* nocapture %arg) { +define void @bcast_unfold_fadd_v16f32(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fadd_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1061,12 +1001,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <16 x float>* - %tmp4 = load <16 x float>, <16 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <16 x float>, ptr %tmp2, align 4 %tmp5 = fadd <16 x float> %tmp4, - %tmp6 = bitcast float* %tmp2 to <16 x float>* - store <16 x float> %tmp5, <16 x float>* %tmp6, align 4 + store <16 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 16 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1075,7 +1013,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fadd_v8f32(float* nocapture %arg) { +define void @bcast_unfold_fadd_v8f32(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fadd_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1095,12 +1033,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <8 x float>* - %tmp4 = load <8 x float>, <8 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <8 x float>, ptr %tmp2, align 4 %tmp5 = fadd <8 x float> %tmp4, - %tmp6 = bitcast float* %tmp2 to <8 x float>* - store <8 x float> %tmp5, <8 x float>* %tmp6, align 4 + store <8 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1109,7 +1045,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fadd_v4f32(float* nocapture %arg) { +define void @bcast_unfold_fadd_v4f32(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fadd_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1128,12 +1064,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <4 x float>* - %tmp4 = load <4 x float>, <4 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <4 x float>, ptr %tmp2, align 4 %tmp5 = fadd <4 x float> %tmp4, - %tmp6 = bitcast float* %tmp2 to <4 x float>* - store <4 x float> %tmp5, <4 x float>* %tmp6, align 4 + store <4 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1142,7 +1076,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fadd_v8f64(double* nocapture %arg) { +define void @bcast_unfold_fadd_v8f64(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fadd_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1162,12 +1096,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <8 x double>* - %tmp4 = load <8 x double>, <8 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <8 x double>, ptr %tmp2, align 8 %tmp5 = fadd <8 x double> %tmp4, - %tmp6 = bitcast double* %tmp2 to <8 x double>* - store <8 x double> %tmp5, <8 x double>* %tmp6, align 8 + store <8 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1176,7 +1108,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fadd_v4f64(double* nocapture %arg) { +define void @bcast_unfold_fadd_v4f64(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fadd_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1196,12 +1128,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <4 x double>* - %tmp4 = load <4 x double>, <4 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <4 x double>, ptr %tmp2, align 8 %tmp5 = fadd <4 x double> %tmp4, - %tmp6 = bitcast double* %tmp2 to <4 x double>* - store <4 x double> %tmp5, <4 x double>* %tmp6, align 8 + store <4 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1210,7 +1140,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fadd_v2f64(double* nocapture %arg) { +define void @bcast_unfold_fadd_v2f64(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fadd_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1230,12 +1160,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <2 x double>* - %tmp4 = load <2 x double>, <2 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <2 x double>, ptr %tmp2, align 8 %tmp5 = fadd <2 x double> %tmp4, - %tmp6 = bitcast double* %tmp2 to <2 x double>* - store <2 x double> %tmp5, <2 x double>* %tmp6, align 8 + store <2 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 2 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1244,7 +1172,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fmul_v16f32(float* nocapture %arg) { +define void @bcast_unfold_fmul_v16f32(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fmul_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1264,12 +1192,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <16 x float>* - %tmp4 = load <16 x float>, <16 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <16 x float>, ptr %tmp2, align 4 %tmp5 = fmul <16 x float> %tmp4, - %tmp6 = bitcast float* %tmp2 to <16 x float>* - store <16 x float> %tmp5, <16 x float>* %tmp6, align 4 + store <16 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 16 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1278,7 +1204,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fmul_v8f32(float* nocapture %arg) { +define void @bcast_unfold_fmul_v8f32(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fmul_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1298,12 +1224,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <8 x float>* - %tmp4 = load <8 x float>, <8 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <8 x float>, ptr %tmp2, align 4 %tmp5 = fmul <8 x float> %tmp4, - %tmp6 = bitcast float* %tmp2 to <8 x float>* - store <8 x float> %tmp5, <8 x float>* %tmp6, align 4 + store <8 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1312,7 +1236,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fmul_v4f32(float* nocapture %arg) { +define void @bcast_unfold_fmul_v4f32(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fmul_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1331,12 +1255,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <4 x float>* - %tmp4 = load <4 x float>, <4 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <4 x float>, ptr %tmp2, align 4 %tmp5 = fmul <4 x float> %tmp4, - %tmp6 = bitcast float* %tmp2 to <4 x float>* - store <4 x float> %tmp5, <4 x float>* %tmp6, align 4 + store <4 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1345,7 +1267,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fmul_v8f64(double* nocapture %arg) { +define void @bcast_unfold_fmul_v8f64(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fmul_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1365,12 +1287,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <8 x double>* - %tmp4 = load <8 x double>, <8 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <8 x double>, ptr %tmp2, align 8 %tmp5 = fmul <8 x double> %tmp4, - %tmp6 = bitcast double* %tmp2 to <8 x double>* - store <8 x double> %tmp5, <8 x double>* %tmp6, align 8 + store <8 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1379,7 +1299,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fmul_v4f64(double* nocapture %arg) { +define void @bcast_unfold_fmul_v4f64(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fmul_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1399,12 +1319,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <4 x double>* - %tmp4 = load <4 x double>, <4 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <4 x double>, ptr %tmp2, align 8 %tmp5 = fmul <4 x double> %tmp4, - %tmp6 = bitcast double* %tmp2 to <4 x double>* - store <4 x double> %tmp5, <4 x double>* %tmp6, align 8 + store <4 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1413,7 +1331,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fmul_v2f64(double* nocapture %arg) { +define void @bcast_unfold_fmul_v2f64(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fmul_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1433,12 +1351,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <2 x double>* - %tmp4 = load <2 x double>, <2 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <2 x double>, ptr %tmp2, align 8 %tmp5 = fmul <2 x double> %tmp4, - %tmp6 = bitcast double* %tmp2 to <2 x double>* - store <2 x double> %tmp5, <2 x double>* %tmp6, align 8 + store <2 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 2 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1447,7 +1363,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fdiv_v16f32(float* nocapture %arg) { +define void @bcast_unfold_fdiv_v16f32(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fdiv_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1468,12 +1384,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <16 x float>* - %tmp4 = load <16 x float>, <16 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <16 x float>, ptr %tmp2, align 4 %tmp5 = fdiv <16 x float> %tmp4, - %tmp6 = bitcast float* %tmp2 to <16 x float>* - store <16 x float> %tmp5, <16 x float>* %tmp6, align 4 + store <16 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 16 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1482,7 +1396,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fdiv_v8f32(float* nocapture %arg) { +define void @bcast_unfold_fdiv_v8f32(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fdiv_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1503,12 +1417,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <8 x float>* - %tmp4 = load <8 x float>, <8 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <8 x float>, ptr %tmp2, align 4 %tmp5 = fdiv <8 x float> %tmp4, - %tmp6 = bitcast float* %tmp2 to <8 x float>* - store <8 x float> %tmp5, <8 x float>* %tmp6, align 4 + store <8 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1517,7 +1429,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fdiv_v4f32(float* nocapture %arg) { +define void @bcast_unfold_fdiv_v4f32(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fdiv_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1537,12 +1449,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <4 x float>* - %tmp4 = load <4 x float>, <4 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <4 x float>, ptr %tmp2, align 4 %tmp5 = fdiv <4 x float> %tmp4, - %tmp6 = bitcast float* %tmp2 to <4 x float>* - store <4 x float> %tmp5, <4 x float>* %tmp6, align 4 + store <4 x float> %tmp5, ptr %tmp2, align 4 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1551,7 +1461,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fdiv_v8f64(double* nocapture %arg) { +define void @bcast_unfold_fdiv_v8f64(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fdiv_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1572,12 +1482,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <8 x double>* - %tmp4 = load <8 x double>, <8 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <8 x double>, ptr %tmp2, align 8 %tmp5 = fdiv <8 x double> %tmp4, - %tmp6 = bitcast double* %tmp2 to <8 x double>* - store <8 x double> %tmp5, <8 x double>* %tmp6, align 8 + store <8 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 8 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1586,7 +1494,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fdiv_v4f64(double* nocapture %arg) { +define void @bcast_unfold_fdiv_v4f64(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fdiv_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1607,12 +1515,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <4 x double>* - %tmp4 = load <4 x double>, <4 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <4 x double>, ptr %tmp2, align 8 %tmp5 = fdiv <4 x double> %tmp4, - %tmp6 = bitcast double* %tmp2 to <4 x double>* - store <4 x double> %tmp5, <4 x double>* %tmp6, align 8 + store <4 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 4 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1621,7 +1527,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fdiv_v2f64(double* nocapture %arg) { +define void @bcast_unfold_fdiv_v2f64(ptr nocapture %arg) { ; CHECK-LABEL: bcast_unfold_fdiv_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1642,12 +1548,10 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp7, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <2 x double>* - %tmp4 = load <2 x double>, <2 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <2 x double>, ptr %tmp2, align 8 %tmp5 = fdiv <2 x double> %tmp4, - %tmp6 = bitcast double* %tmp2 to <2 x double>* - store <2 x double> %tmp5, <2 x double>* %tmp6, align 8 + store <2 x double> %tmp5, ptr %tmp2, align 8 %tmp7 = add i64 %tmp, 2 %tmp8 = icmp eq i64 %tmp7, 1024 br i1 %tmp8, label %bb9, label %bb1 @@ -1656,7 +1560,7 @@ bb9: ; preds = %bb1 ret void } -define void @bcast_unfold_fma213_v4f32(float* %arg) { +define void @bcast_unfold_fma213_v4f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma213_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1676,13 +1580,11 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp9, %bb2 ] - %tmp3 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp4 = bitcast float* %tmp3 to <4 x float>* - %tmp5 = load <4 x float>, <4 x float>* %tmp4, align 4 + %tmp3 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp5 = load <4 x float>, ptr %tmp3, align 4 %tmp6 = fmul contract <4 x float> %tmp5, %tmp5 %tmp7 = fadd contract <4 x float> %tmp6, - %tmp8 = bitcast float* %tmp3 to <4 x float>* - store <4 x float> %tmp7, <4 x float>* %tmp8, align 4 + store <4 x float> %tmp7, ptr %tmp3, align 4 %tmp9 = add i64 %tmp, 4 %tmp10 = icmp eq i64 %tmp9, 1024 br i1 %tmp10, label %bb11, label %bb2 @@ -1691,7 +1593,7 @@ bb11: ; preds = %bb2 ret void } -define void @bcast_unfold_fma231_v4f32(float* %arg) { +define void @bcast_unfold_fma231_v4f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma231_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1711,13 +1613,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <4 x float>* - %tmp4 = load <4 x float>, <4 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <4 x float>, ptr %tmp2, align 4 %tmp5 = fmul contract <4 x float> %tmp4, %tmp6 = fadd contract <4 x float> %tmp4, %tmp5 - %tmp7 = bitcast float* %tmp2 to <4 x float>* - store <4 x float> %tmp6, <4 x float>* %tmp7, align 4 + store <4 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -1726,7 +1626,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fma213_v8f32(float* %arg) { +define void @bcast_unfold_fma213_v8f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma213_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1747,13 +1647,11 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp9, %bb2 ] - %tmp3 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp4 = bitcast float* %tmp3 to <8 x float>* - %tmp5 = load <8 x float>, <8 x float>* %tmp4, align 4 + %tmp3 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp5 = load <8 x float>, ptr %tmp3, align 4 %tmp6 = fmul contract <8 x float> %tmp5, %tmp5 %tmp7 = fadd contract <8 x float> %tmp6, - %tmp8 = bitcast float* %tmp3 to <8 x float>* - store <8 x float> %tmp7, <8 x float>* %tmp8, align 4 + store <8 x float> %tmp7, ptr %tmp3, align 4 %tmp9 = add i64 %tmp, 8 %tmp10 = icmp eq i64 %tmp9, 1024 br i1 %tmp10, label %bb11, label %bb2 @@ -1762,7 +1660,7 @@ bb11: ; preds = %bb2 ret void } -define void @bcast_unfold_fma231_v8f32(float* %arg) { +define void @bcast_unfold_fma231_v8f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma231_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1783,13 +1681,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <8 x float>* - %tmp4 = load <8 x float>, <8 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <8 x float>, ptr %tmp2, align 4 %tmp5 = fmul contract <8 x float> %tmp4, %tmp6 = fadd contract <8 x float> %tmp4, %tmp5 - %tmp7 = bitcast float* %tmp2 to <8 x float>* - store <8 x float> %tmp6, <8 x float>* %tmp7, align 4 + store <8 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -1798,7 +1694,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fma213_v16f32(float* %arg) { +define void @bcast_unfold_fma213_v16f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma213_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1819,13 +1715,11 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp9, %bb2 ] - %tmp3 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp4 = bitcast float* %tmp3 to <16 x float>* - %tmp5 = load <16 x float>, <16 x float>* %tmp4, align 4 + %tmp3 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp5 = load <16 x float>, ptr %tmp3, align 4 %tmp6 = fmul contract <16 x float> %tmp5, %tmp5 %tmp7 = fadd contract <16 x float> %tmp6, - %tmp8 = bitcast float* %tmp3 to <16 x float>* - store <16 x float> %tmp7, <16 x float>* %tmp8, align 4 + store <16 x float> %tmp7, ptr %tmp3, align 4 %tmp9 = add i64 %tmp, 16 %tmp10 = icmp eq i64 %tmp9, 1024 br i1 %tmp10, label %bb11, label %bb2 @@ -1834,7 +1728,7 @@ bb11: ; preds = %bb2 ret void } -define void @bcast_unfold_fma231_v16f32(float* %arg) { +define void @bcast_unfold_fma231_v16f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma231_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -1855,13 +1749,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <16 x float>* - %tmp4 = load <16 x float>, <16 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <16 x float>, ptr %tmp2, align 4 %tmp5 = fmul contract <16 x float> %tmp4, %tmp6 = fadd contract <16 x float> %tmp4, %tmp5 - %tmp7 = bitcast float* %tmp2 to <16 x float>* - store <16 x float> %tmp6, <16 x float>* %tmp7, align 4 + store <16 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -1870,7 +1762,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fma213_v2f64(double* %arg) { +define void @bcast_unfold_fma213_v2f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma213_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1891,13 +1783,11 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp9, %bb2 ] - %tmp3 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp4 = bitcast double* %tmp3 to <2 x double>* - %tmp5 = load <2 x double>, <2 x double>* %tmp4, align 4 + %tmp3 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp5 = load <2 x double>, ptr %tmp3, align 4 %tmp6 = fmul contract <2 x double> %tmp5, %tmp5 %tmp7 = fadd contract <2 x double> %tmp6, - %tmp8 = bitcast double* %tmp3 to <2 x double>* - store <2 x double> %tmp7, <2 x double>* %tmp8, align 8 + store <2 x double> %tmp7, ptr %tmp3, align 8 %tmp9 = add i64 %tmp, 2 %tmp10 = icmp eq i64 %tmp9, 1024 br i1 %tmp10, label %bb11, label %bb2 @@ -1906,7 +1796,7 @@ bb11: ; preds = %bb2 ret void } -define void @bcast_unfold_fma231_v2f64(double* %arg) { +define void @bcast_unfold_fma231_v2f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma231_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1927,13 +1817,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <2 x double>* - %tmp4 = load <2 x double>, <2 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <2 x double>, ptr %tmp2, align 8 %tmp5 = fmul contract <2 x double> %tmp4, %tmp6 = fadd contract <2 x double> %tmp4, %tmp5 - %tmp7 = bitcast double* %tmp2 to <2 x double>* - store <2 x double> %tmp6, <2 x double>* %tmp7, align 8 + store <2 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -1942,7 +1830,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fma213_v4f64(double* %arg) { +define void @bcast_unfold_fma213_v4f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma213_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1963,13 +1851,11 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp9, %bb2 ] - %tmp3 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp4 = bitcast double* %tmp3 to <4 x double>* - %tmp5 = load <4 x double>, <4 x double>* %tmp4, align 8 + %tmp3 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp5 = load <4 x double>, ptr %tmp3, align 8 %tmp6 = fmul contract <4 x double> %tmp5, %tmp5 %tmp7 = fadd contract <4 x double> %tmp6, - %tmp8 = bitcast double* %tmp3 to <4 x double>* - store <4 x double> %tmp7, <4 x double>* %tmp8, align 8 + store <4 x double> %tmp7, ptr %tmp3, align 8 %tmp9 = add i64 %tmp, 4 %tmp10 = icmp eq i64 %tmp9, 1024 br i1 %tmp10, label %bb11, label %bb2 @@ -1978,7 +1864,7 @@ bb11: ; preds = %bb2 ret void } -define void @bcast_unfold_fma231_v4f64(double* %arg) { +define void @bcast_unfold_fma231_v4f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma231_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -1999,13 +1885,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <4 x double>* - %tmp4 = load <4 x double>, <4 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <4 x double>, ptr %tmp2, align 8 %tmp5 = fmul contract <4 x double> %tmp4, %tmp6 = fadd contract <4 x double> %tmp4, %tmp5 - %tmp7 = bitcast double* %tmp2 to <4 x double>* - store <4 x double> %tmp6, <4 x double>* %tmp7, align 8 + store <4 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2014,7 +1898,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fma213_v8f64(double* %arg) { +define void @bcast_unfold_fma213_v8f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma213_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2035,13 +1919,11 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp9, %bb2 ] - %tmp3 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp4 = bitcast double* %tmp3 to <8 x double>* - %tmp5 = load <8 x double>, <8 x double>* %tmp4, align 8 + %tmp3 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp5 = load <8 x double>, ptr %tmp3, align 8 %tmp6 = fmul contract <8 x double> %tmp5, %tmp5 %tmp7 = fadd contract <8 x double> %tmp6, - %tmp8 = bitcast double* %tmp3 to <8 x double>* - store <8 x double> %tmp7, <8 x double>* %tmp8, align 8 + store <8 x double> %tmp7, ptr %tmp3, align 8 %tmp9 = add i64 %tmp, 8 %tmp10 = icmp eq i64 %tmp9, 1024 br i1 %tmp10, label %bb11, label %bb2 @@ -2050,7 +1932,7 @@ bb11: ; preds = %bb2 ret void } -define void @bcast_unfold_fma231_v8f64(double* %arg) { +define void @bcast_unfold_fma231_v8f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fma231_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2071,13 +1953,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <8 x double>* - %tmp4 = load <8 x double>, <8 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <8 x double>, ptr %tmp2, align 8 %tmp5 = fmul contract <8 x double> %tmp4, %tmp6 = fadd contract <8 x double> %tmp4, %tmp5 - %tmp7 = bitcast double* %tmp2 to <8 x double>* - store <8 x double> %tmp6, <8 x double>* %tmp7, align 8 + store <8 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2086,7 +1966,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmax_v4f32(float* %arg) { +define void @bcast_unfold_fmax_v4f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmax_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2106,13 +1986,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <4 x float>* - %tmp4 = load <4 x float>, <4 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <4 x float>, ptr %tmp2, align 4 %tmp5 = fcmp ogt <4 x float> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x float> %tmp4, <4 x float> - %tmp7 = bitcast float* %tmp2 to <4 x float>* - store <4 x float> %tmp6, <4 x float>* %tmp7, align 4 + store <4 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2121,7 +1999,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmax_v8f32(float* %arg) { +define void @bcast_unfold_fmax_v8f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmax_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2142,13 +2020,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <8 x float>* - %tmp4 = load <8 x float>, <8 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <8 x float>, ptr %tmp2, align 4 %tmp5 = fcmp ogt <8 x float> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x float> %tmp4, <8 x float> - %tmp7 = bitcast float* %tmp2 to <8 x float>* - store <8 x float> %tmp6, <8 x float>* %tmp7, align 4 + store <8 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2157,7 +2033,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmax_v16f32(float* %arg) { +define void @bcast_unfold_fmax_v16f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmax_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2178,13 +2054,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <16 x float>* - %tmp4 = load <16 x float>, <16 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <16 x float>, ptr %tmp2, align 4 %tmp5 = fcmp ogt <16 x float> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x float> %tmp4, <16 x float> - %tmp7 = bitcast float* %tmp2 to <16 x float>* - store <16 x float> %tmp6, <16 x float>* %tmp7, align 4 + store <16 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2193,7 +2067,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmax_v2f64(double* %arg) { +define void @bcast_unfold_fmax_v2f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmax_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2214,13 +2088,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <2 x double>* - %tmp4 = load <2 x double>, <2 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <2 x double>, ptr %tmp2, align 8 %tmp5 = fcmp ogt <2 x double> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x double> %tmp4, <2 x double> - %tmp7 = bitcast double* %tmp2 to <2 x double>* - store <2 x double> %tmp6, <2 x double>* %tmp7, align 8 + store <2 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2229,7 +2101,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmax_v4f64(double* %arg) { +define void @bcast_unfold_fmax_v4f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmax_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2250,13 +2122,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <4 x double>* - %tmp4 = load <4 x double>, <4 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <4 x double>, ptr %tmp2, align 8 %tmp5 = fcmp ogt <4 x double> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x double> %tmp4, <4 x double> - %tmp7 = bitcast double* %tmp2 to <4 x double>* - store <4 x double> %tmp6, <4 x double>* %tmp7, align 8 + store <4 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2265,7 +2135,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmax_v8f64(double* %arg) { +define void @bcast_unfold_fmax_v8f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmax_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2286,13 +2156,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <8 x double>* - %tmp4 = load <8 x double>, <8 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <8 x double>, ptr %tmp2, align 8 %tmp5 = fcmp ogt <8 x double> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x double> %tmp4, <8 x double> - %tmp7 = bitcast double* %tmp2 to <8 x double>* - store <8 x double> %tmp6, <8 x double>* %tmp7, align 8 + store <8 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2301,7 +2169,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmin_v4f32(float* %arg) { +define void @bcast_unfold_fmin_v4f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmin_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2321,13 +2189,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <4 x float>* - %tmp4 = load <4 x float>, <4 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <4 x float>, ptr %tmp2, align 4 %tmp5 = fcmp olt <4 x float> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x float> %tmp4, <4 x float> - %tmp7 = bitcast float* %tmp2 to <4 x float>* - store <4 x float> %tmp6, <4 x float>* %tmp7, align 4 + store <4 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2336,7 +2202,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmin_v8f32(float* %arg) { +define void @bcast_unfold_fmin_v8f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmin_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2357,13 +2223,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <8 x float>* - %tmp4 = load <8 x float>, <8 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <8 x float>, ptr %tmp2, align 4 %tmp5 = fcmp olt <8 x float> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x float> %tmp4, <8 x float> - %tmp7 = bitcast float* %tmp2 to <8 x float>* - store <8 x float> %tmp6, <8 x float>* %tmp7, align 4 + store <8 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2372,7 +2236,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmin_v16f32(float* %arg) { +define void @bcast_unfold_fmin_v16f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmin_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2393,13 +2257,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <16 x float>* - %tmp4 = load <16 x float>, <16 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <16 x float>, ptr %tmp2, align 4 %tmp5 = fcmp olt <16 x float> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x float> %tmp4, <16 x float> - %tmp7 = bitcast float* %tmp2 to <16 x float>* - store <16 x float> %tmp6, <16 x float>* %tmp7, align 4 + store <16 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2408,7 +2270,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmin_v2f64(double* %arg) { +define void @bcast_unfold_fmin_v2f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmin_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2429,13 +2291,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <2 x double>* - %tmp4 = load <2 x double>, <2 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <2 x double>, ptr %tmp2, align 8 %tmp5 = fcmp olt <2 x double> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x double> %tmp4, <2 x double> - %tmp7 = bitcast double* %tmp2 to <2 x double>* - store <2 x double> %tmp6, <2 x double>* %tmp7, align 8 + store <2 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2444,7 +2304,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmin_v4f64(double* %arg) { +define void @bcast_unfold_fmin_v4f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmin_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2465,13 +2325,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <4 x double>* - %tmp4 = load <4 x double>, <4 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <4 x double>, ptr %tmp2, align 8 %tmp5 = fcmp olt <4 x double> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x double> %tmp4, <4 x double> - %tmp7 = bitcast double* %tmp2 to <4 x double>* - store <4 x double> %tmp6, <4 x double>* %tmp7, align 8 + store <4 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2480,7 +2338,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_fmin_v8f64(double* %arg) { +define void @bcast_unfold_fmin_v8f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_fmin_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2501,13 +2359,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <8 x double>* - %tmp4 = load <8 x double>, <8 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <8 x double>, ptr %tmp2, align 8 %tmp5 = fcmp olt <8 x double> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x double> %tmp4, <8 x double> - %tmp7 = bitcast double* %tmp2 to <8 x double>* - store <8 x double> %tmp6, <8 x double>* %tmp7, align 8 + store <8 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2516,7 +2372,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smin_v4i32(i32* %arg) { +define void @bcast_unfold_smin_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smin_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2535,13 +2391,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp5 = icmp slt <4 x i32> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i32> %tmp4, <4 x i32> - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2550,7 +2404,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smin_v8i32(i32* %arg) { +define void @bcast_unfold_smin_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smin_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2570,13 +2424,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <8 x i32>* - %tmp4 = load <8 x i32>, <8 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <8 x i32>, ptr %tmp2, align 4 %tmp5 = icmp slt <8 x i32> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i32> %tmp4, <8 x i32> - %tmp7 = bitcast i32* %tmp2 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2585,7 +2437,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smin_v16i32(i32* %arg) { +define void @bcast_unfold_smin_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smin_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2605,13 +2457,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <16 x i32>* - %tmp4 = load <16 x i32>, <16 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <16 x i32>, ptr %tmp2, align 4 %tmp5 = icmp slt <16 x i32> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x i32> %tmp4, <16 x i32> - %tmp7 = bitcast i32* %tmp2 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2620,7 +2470,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smin_v2i64(i64* %arg) { +define void @bcast_unfold_smin_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smin_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2639,13 +2489,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <2 x i64>* - %tmp4 = load <2 x i64>, <2 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <2 x i64>, ptr %tmp2, align 8 %tmp5 = icmp slt <2 x i64> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x i64> %tmp4, <2 x i64> - %tmp7 = bitcast i64* %tmp2 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 8 + store <2 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2654,7 +2502,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smin_v4i64(i64* %arg) { +define void @bcast_unfold_smin_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smin_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2674,13 +2522,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 8 %tmp5 = icmp slt <4 x i64> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i64> %tmp4, <4 x i64> - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 8 + store <4 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2689,7 +2535,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smin_v8i64(i64* %arg) { +define void @bcast_unfold_smin_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smin_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2709,13 +2555,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <8 x i64>* - %tmp4 = load <8 x i64>, <8 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <8 x i64>, ptr %tmp2, align 8 %tmp5 = icmp slt <8 x i64> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i64> %tmp4, <8 x i64> - %tmp7 = bitcast i64* %tmp2 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 8 + store <8 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2724,7 +2568,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smax_v4i32(i32* %arg) { +define void @bcast_unfold_smax_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smax_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2743,13 +2587,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp5 = icmp sgt <4 x i32> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i32> %tmp4, <4 x i32> - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2758,7 +2600,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smax_v8i32(i32* %arg) { +define void @bcast_unfold_smax_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smax_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2778,13 +2620,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <8 x i32>* - %tmp4 = load <8 x i32>, <8 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <8 x i32>, ptr %tmp2, align 4 %tmp5 = icmp sgt <8 x i32> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i32> %tmp4, <8 x i32> - %tmp7 = bitcast i32* %tmp2 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2793,7 +2633,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smax_v16i32(i32* %arg) { +define void @bcast_unfold_smax_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smax_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2813,13 +2653,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <16 x i32>* - %tmp4 = load <16 x i32>, <16 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <16 x i32>, ptr %tmp2, align 4 %tmp5 = icmp sgt <16 x i32> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x i32> %tmp4, <16 x i32> - %tmp7 = bitcast i32* %tmp2 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2828,7 +2666,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smax_v2i64(i64* %arg) { +define void @bcast_unfold_smax_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smax_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2847,13 +2685,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <2 x i64>* - %tmp4 = load <2 x i64>, <2 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <2 x i64>, ptr %tmp2, align 8 %tmp5 = icmp sgt <2 x i64> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x i64> %tmp4, <2 x i64> - %tmp7 = bitcast i64* %tmp2 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 8 + store <2 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2862,7 +2698,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smax_v4i64(i64* %arg) { +define void @bcast_unfold_smax_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smax_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2882,13 +2718,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 8 %tmp5 = icmp sgt <4 x i64> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i64> %tmp4, <4 x i64> - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 8 + store <4 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2897,7 +2731,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_smax_v8i64(i64* %arg) { +define void @bcast_unfold_smax_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_smax_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -2917,13 +2751,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <8 x i64>* - %tmp4 = load <8 x i64>, <8 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <8 x i64>, ptr %tmp2, align 8 %tmp5 = icmp sgt <8 x i64> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i64> %tmp4, <8 x i64> - %tmp7 = bitcast i64* %tmp2 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 8 + store <8 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2932,7 +2764,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umin_v4i32(i32* %arg) { +define void @bcast_unfold_umin_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umin_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2951,13 +2783,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp5 = icmp ult <4 x i32> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i32> %tmp4, <4 x i32> - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -2966,7 +2796,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umin_v8i32(i32* %arg) { +define void @bcast_unfold_umin_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umin_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -2986,13 +2816,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <8 x i32>* - %tmp4 = load <8 x i32>, <8 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <8 x i32>, ptr %tmp2, align 4 %tmp5 = icmp ult <8 x i32> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i32> %tmp4, <8 x i32> - %tmp7 = bitcast i32* %tmp2 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3001,7 +2829,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umin_v16i32(i32* %arg) { +define void @bcast_unfold_umin_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umin_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3021,13 +2849,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <16 x i32>* - %tmp4 = load <16 x i32>, <16 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <16 x i32>, ptr %tmp2, align 4 %tmp5 = icmp ult <16 x i32> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x i32> %tmp4, <16 x i32> - %tmp7 = bitcast i32* %tmp2 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3036,7 +2862,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umin_v2i64(i64* %arg) { +define void @bcast_unfold_umin_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umin_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3055,13 +2881,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <2 x i64>* - %tmp4 = load <2 x i64>, <2 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <2 x i64>, ptr %tmp2, align 8 %tmp5 = icmp ult <2 x i64> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x i64> %tmp4, <2 x i64> - %tmp7 = bitcast i64* %tmp2 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 8 + store <2 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3070,7 +2894,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umin_v4i64(i64* %arg) { +define void @bcast_unfold_umin_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umin_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3090,13 +2914,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 8 %tmp5 = icmp ult <4 x i64> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i64> %tmp4, <4 x i64> - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 8 + store <4 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3105,7 +2927,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umin_v8i64(i64* %arg) { +define void @bcast_unfold_umin_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umin_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3125,13 +2947,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <8 x i64>* - %tmp4 = load <8 x i64>, <8 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <8 x i64>, ptr %tmp2, align 8 %tmp5 = icmp ult <8 x i64> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i64> %tmp4, <8 x i64> - %tmp7 = bitcast i64* %tmp2 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 8 + store <8 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3140,7 +2960,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umax_v4i32(i32* %arg) { +define void @bcast_unfold_umax_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umax_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3159,13 +2979,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp5 = icmp ugt <4 x i32> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i32> %tmp4, <4 x i32> - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3174,7 +2992,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umax_v8i32(i32* %arg) { +define void @bcast_unfold_umax_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umax_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3194,13 +3012,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <8 x i32>* - %tmp4 = load <8 x i32>, <8 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <8 x i32>, ptr %tmp2, align 4 %tmp5 = icmp ugt <8 x i32> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i32> %tmp4, <8 x i32> - %tmp7 = bitcast i32* %tmp2 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3209,7 +3025,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umax_v16i32(i32* %arg) { +define void @bcast_unfold_umax_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umax_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3229,13 +3045,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <16 x i32>* - %tmp4 = load <16 x i32>, <16 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <16 x i32>, ptr %tmp2, align 4 %tmp5 = icmp ugt <16 x i32> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x i32> %tmp4, <16 x i32> - %tmp7 = bitcast i32* %tmp2 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3244,7 +3058,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umax_v2i64(i64* %arg) { +define void @bcast_unfold_umax_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umax_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3263,13 +3077,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <2 x i64>* - %tmp4 = load <2 x i64>, <2 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <2 x i64>, ptr %tmp2, align 8 %tmp5 = icmp ugt <2 x i64> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x i64> %tmp4, <2 x i64> - %tmp7 = bitcast i64* %tmp2 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 8 + store <2 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3278,7 +3090,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umax_v4i64(i64* %arg) { +define void @bcast_unfold_umax_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umax_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3298,13 +3110,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 8 %tmp5 = icmp ugt <4 x i64> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i64> %tmp4, <4 x i64> - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 8 + store <4 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3313,7 +3123,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_umax_v8i64(i64* %arg) { +define void @bcast_unfold_umax_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_umax_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3333,13 +3143,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <8 x i64>* - %tmp4 = load <8 x i64>, <8 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <8 x i64>, ptr %tmp2, align 8 %tmp5 = icmp ugt <8 x i64> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i64> %tmp4, <8 x i64> - %tmp7 = bitcast i64* %tmp2 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 8 + store <8 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3348,7 +3156,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpgt_v4i32(i32* %arg) { +define void @bcast_unfold_pcmpgt_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpgt_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3369,13 +3177,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp5 = icmp sgt <4 x i32> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i32> , <4 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3384,7 +3190,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpgt_v8i32(i32* %arg) { +define void @bcast_unfold_pcmpgt_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpgt_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3406,13 +3212,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <8 x i32>* - %tmp4 = load <8 x i32>, <8 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <8 x i32>, ptr %tmp2, align 4 %tmp5 = icmp sgt <8 x i32> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i32> , <8 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3421,7 +3225,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpgt_v16i32(i32* %arg) { +define void @bcast_unfold_pcmpgt_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpgt_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3443,13 +3247,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <16 x i32>* - %tmp4 = load <16 x i32>, <16 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <16 x i32>, ptr %tmp2, align 4 %tmp5 = icmp sgt <16 x i32> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x i32> , <16 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3458,7 +3260,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpgt_v2i64(i64* %arg) { +define void @bcast_unfold_pcmpgt_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpgt_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3479,13 +3281,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <2 x i64>* - %tmp4 = load <2 x i64>, <2 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <2 x i64>, ptr %tmp2, align 4 %tmp5 = icmp sgt <2 x i64> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x i64> , <2 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 4 + store <2 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3493,7 +3293,8 @@ bb1: ; preds = %bb1, %bb bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpgt_v4i64(i64* %arg) { + +define void @bcast_unfold_pcmpgt_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpgt_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3515,13 +3316,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 4 %tmp5 = icmp sgt <4 x i64> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i64> , <4 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 4 + store <4 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3530,7 +3329,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpgt_v8i64(i64* %arg) { +define void @bcast_unfold_pcmpgt_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpgt_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3552,13 +3351,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <8 x i64>* - %tmp4 = load <8 x i64>, <8 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <8 x i64>, ptr %tmp2, align 4 %tmp5 = icmp sgt <8 x i64> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i64> , <8 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 4 + store <8 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3567,7 +3364,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpeq_v4i32(i32* %arg) { +define void @bcast_unfold_pcmpeq_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpeq_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3588,13 +3385,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp5 = icmp eq <4 x i32> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i32> , <4 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3603,7 +3398,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpeq_v8i32(i32* %arg) { +define void @bcast_unfold_pcmpeq_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpeq_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3625,13 +3420,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <8 x i32>* - %tmp4 = load <8 x i32>, <8 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <8 x i32>, ptr %tmp2, align 4 %tmp5 = icmp eq <8 x i32> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i32> , <8 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3640,7 +3433,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpeq_v16i32(i32* %arg) { +define void @bcast_unfold_pcmpeq_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpeq_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -3662,13 +3455,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <16 x i32>* - %tmp4 = load <16 x i32>, <16 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <16 x i32>, ptr %tmp2, align 4 %tmp5 = icmp eq <16 x i32> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x i32> , <16 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3677,7 +3468,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpeq_v2i64(i64* %arg) { +define void @bcast_unfold_pcmpeq_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpeq_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3698,13 +3489,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <2 x i64>* - %tmp4 = load <2 x i64>, <2 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <2 x i64>, ptr %tmp2, align 4 %tmp5 = icmp eq <2 x i64> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x i64> , <2 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 4 + store <2 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3712,7 +3501,8 @@ bb1: ; preds = %bb1, %bb bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpeq_v4i64(i64* %arg) { + +define void @bcast_unfold_pcmpeq_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpeq_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3734,13 +3524,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 4 %tmp5 = icmp eq <4 x i64> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i64> , <4 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 4 + store <4 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3749,7 +3537,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpeq_v8i64(i64* %arg) { +define void @bcast_unfold_pcmpeq_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpeq_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -3771,13 +3559,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <8 x i64>* - %tmp4 = load <8 x i64>, <8 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <8 x i64>, ptr %tmp2, align 4 %tmp5 = icmp eq <8 x i64> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i64> , <8 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 4 + store <8 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3786,7 +3572,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmp_v4i32(i32* %arg) { +define void @bcast_unfold_pcmp_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmp_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -3808,13 +3594,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp5 = icmp slt <4 x i32> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i32> , <4 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp slt i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3823,7 +3607,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmp_v8i32(i32* %arg) { +define void @bcast_unfold_pcmp_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmp_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -3846,13 +3630,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <8 x i32>* - %tmp4 = load <8 x i32>, <8 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <8 x i32>, ptr %tmp2, align 4 %tmp5 = icmp slt <8 x i32> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i32> , <8 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp slt i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3861,7 +3643,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmp_v16i32(i32* %arg) { +define void @bcast_unfold_pcmp_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmp_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -3884,13 +3666,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <16 x i32>* - %tmp4 = load <16 x i32>, <16 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <16 x i32>, ptr %tmp2, align 4 %tmp5 = icmp slt <16 x i32> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x i32> , <16 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp slt i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3899,7 +3679,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmp_v2i64(i64* %arg) { +define void @bcast_unfold_pcmp_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmp_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -3921,13 +3701,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <2 x i64>* - %tmp4 = load <2 x i64>, <2 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <2 x i64>, ptr %tmp2, align 4 %tmp5 = icmp slt <2 x i64> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x i64> , <2 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 4 + store <2 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp slt i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3935,7 +3713,8 @@ bb1: ; preds = %bb1, %bb bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmp_v4i64(i64* %arg) { + +define void @bcast_unfold_pcmp_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmp_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -3958,13 +3737,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 4 %tmp5 = icmp slt <4 x i64> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i64> , <4 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 4 + store <4 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp slt i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -3973,7 +3750,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmp_v8i64(i64* %arg) { +define void @bcast_unfold_pcmp_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmp_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -3996,13 +3773,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <8 x i64>* - %tmp4 = load <8 x i64>, <8 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <8 x i64>, ptr %tmp2, align 4 %tmp5 = icmp slt <8 x i64> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i64> , <8 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 4 + store <8 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp slt i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4011,7 +3786,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpu_v4i32(i32* %arg) { +define void @bcast_unfold_pcmpu_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpu_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -4033,13 +3808,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp5 = icmp ult <4 x i32> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i32> , <4 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp ult i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4048,7 +3821,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpu_v8i32(i32* %arg) { +define void @bcast_unfold_pcmpu_v8i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpu_v8i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -4071,13 +3844,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <8 x i32>* - %tmp4 = load <8 x i32>, <8 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <8 x i32>, ptr %tmp2, align 4 %tmp5 = icmp ult <8 x i32> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i32> , <8 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <8 x i32>* - store <8 x i32> %tmp6, <8 x i32>* %tmp7, align 4 + store <8 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp ult i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4086,7 +3857,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpu_v16i32(i32* %arg) { +define void @bcast_unfold_pcmpu_v16i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpu_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -4109,13 +3880,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <16 x i32>* - %tmp4 = load <16 x i32>, <16 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <16 x i32>, ptr %tmp2, align 4 %tmp5 = icmp ult <16 x i32> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x i32> , <16 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <16 x i32>* - store <16 x i32> %tmp6, <16 x i32>* %tmp7, align 4 + store <16 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp ult i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4124,7 +3893,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpu_v2i64(i64* %arg) { +define void @bcast_unfold_pcmpu_v2i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpu_v2i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -4146,13 +3915,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <2 x i64>* - %tmp4 = load <2 x i64>, <2 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <2 x i64>, ptr %tmp2, align 4 %tmp5 = icmp ult <2 x i64> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x i64> , <2 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <2 x i64>* - store <2 x i64> %tmp6, <2 x i64>* %tmp7, align 4 + store <2 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp ult i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4160,7 +3927,8 @@ bb1: ; preds = %bb1, %bb bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpu_v4i64(i64* %arg) { + +define void @bcast_unfold_pcmpu_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpu_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -4183,13 +3951,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 4 %tmp5 = icmp ult <4 x i64> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x i64> , <4 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 4 + store <4 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp ult i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4198,7 +3964,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_pcmpu_v8i64(i64* %arg) { +define void @bcast_unfold_pcmpu_v8i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_pcmpu_v8i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: xorl %eax, %eax @@ -4221,13 +3987,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <8 x i64>* - %tmp4 = load <8 x i64>, <8 x i64>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <8 x i64>, ptr %tmp2, align 4 %tmp5 = icmp ult <8 x i64> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x i64> , <8 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <8 x i64>* - store <8 x i64> %tmp6, <8 x i64>* %tmp7, align 4 + store <8 x i64> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp ult i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4236,7 +4000,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_cmp_v4f32(float* %arg) { +define void @bcast_unfold_cmp_v4f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_cmp_v4f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -4258,13 +4022,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <4 x float>* - %tmp4 = load <4 x float>, <4 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <4 x float>, ptr %tmp2, align 4 %tmp5 = fcmp olt <4 x float> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x float> %tmp4, <4 x float> - %tmp7 = bitcast float* %tmp2 to <4 x float>* - store <4 x float> %tmp6, <4 x float>* %tmp7, align 4 + store <4 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4273,7 +4035,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_cmp_v8f32(float* %arg) { +define void @bcast_unfold_cmp_v8f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_cmp_v8f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -4296,13 +4058,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <8 x float>* - %tmp4 = load <8 x float>, <8 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <8 x float>, ptr %tmp2, align 4 %tmp5 = fcmp olt <8 x float> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x float> %tmp4, <8 x float> - %tmp7 = bitcast float* %tmp2 to <8 x float>* - store <8 x float> %tmp6, <8 x float>* %tmp7, align 4 + store <8 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4311,7 +4071,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_cmp_v16f32(float* %arg) { +define void @bcast_unfold_cmp_v16f32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_cmp_v16f32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -4334,13 +4094,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds float, float* %arg, i64 %tmp - %tmp3 = bitcast float* %tmp2 to <16 x float>* - %tmp4 = load <16 x float>, <16 x float>* %tmp3, align 4 + %tmp2 = getelementptr inbounds float, ptr %arg, i64 %tmp + %tmp4 = load <16 x float>, ptr %tmp2, align 4 %tmp5 = fcmp olt <16 x float> %tmp4, %tmp6 = select <16 x i1> %tmp5, <16 x float> %tmp4, <16 x float> - %tmp7 = bitcast float* %tmp2 to <16 x float>* - store <16 x float> %tmp6, <16 x float>* %tmp7, align 4 + store <16 x float> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 16 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4349,7 +4107,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_cmp_v2f64(double* %arg) { +define void @bcast_unfold_cmp_v2f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_cmp_v2f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -4373,13 +4131,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <2 x double>* - %tmp4 = load <2 x double>, <2 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <2 x double>, ptr %tmp2, align 8 %tmp5 = fcmp olt <2 x double> %tmp4, %tmp6 = select <2 x i1> %tmp5, <2 x double> %tmp4, <2 x double> - %tmp7 = bitcast double* %tmp2 to <2 x double>* - store <2 x double> %tmp6, <2 x double>* %tmp7, align 8 + store <2 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 2 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4388,7 +4144,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_cmp_v4f64(double* %arg) { +define void @bcast_unfold_cmp_v4f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_cmp_v4f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -4411,13 +4167,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <4 x double>* - %tmp4 = load <4 x double>, <4 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <4 x double>, ptr %tmp2, align 8 %tmp5 = fcmp olt <4 x double> %tmp4, %tmp6 = select <4 x i1> %tmp5, <4 x double> %tmp4, <4 x double> - %tmp7 = bitcast double* %tmp2 to <4 x double>* - store <4 x double> %tmp6, <4 x double>* %tmp7, align 8 + store <4 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4426,7 +4180,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_cmp_v8f64(double* %arg) { +define void @bcast_unfold_cmp_v8f64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_cmp_v8f64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -4449,13 +4203,11 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds double, double* %arg, i64 %tmp - %tmp3 = bitcast double* %tmp2 to <8 x double>* - %tmp4 = load <8 x double>, <8 x double>* %tmp3, align 8 + %tmp2 = getelementptr inbounds double, ptr %arg, i64 %tmp + %tmp4 = load <8 x double>, ptr %tmp2, align 8 %tmp5 = fcmp olt <8 x double> %tmp4, %tmp6 = select <8 x i1> %tmp5, <8 x double> %tmp4, <8 x double> - %tmp7 = bitcast double* %tmp2 to <8 x double>* - store <8 x double> %tmp6, <8 x double>* %tmp7, align 8 + store <8 x double> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 8 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4464,7 +4216,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_cmp_v8f32_refold(float* nocapture %0) { +define void @bcast_unfold_cmp_v8f32_refold(ptr nocapture %0) { ; CHECK-LABEL: bcast_unfold_cmp_v8f32_refold: ; CHECK: # %bb.0: ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -4483,23 +4235,21 @@ define void @bcast_unfold_cmp_v8f32_refold(float* nocapture %0) { br label %2 2: ; preds = %2, %1 - %3 = phi i64 [ 0, %1 ], [ %10, %2 ] - %4 = getelementptr inbounds float, float* %0, i64 %3 - %5 = bitcast float* %4 to <8 x float>* - %6 = load <8 x float>, <8 x float>* %5, align 4 - %7 = fcmp olt <8 x float> %6, - %8 = select <8 x i1> %7, <8 x float> , <8 x float> - %9 = bitcast float* %4 to <8 x float>* - store <8 x float> %8, <8 x float>* %9, align 4 - %10 = add i64 %3, 8 - %11 = icmp eq i64 %10, 1024 - br i1 %11, label %12, label %2 + %3 = phi i64 [ 0, %1 ], [ %8, %2 ] + %4 = getelementptr inbounds float, ptr %0, i64 %3 + %5 = load <8 x float>, ptr %4, align 4 + %6 = fcmp olt <8 x float> %5, + %7 = select <8 x i1> %6, <8 x float> , <8 x float> + store <8 x float> %7, ptr %4, align 4 + %8 = add i64 %3, 8 + %9 = icmp eq i64 %8, 1024 + br i1 %9, label %10, label %2 -12: ; preds = %2 +10: ; preds = %2 ret void } -define void @bcast_unfold_ptestm_v4i32(i32* %arg) { +define void @bcast_unfold_ptestm_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_ptestm_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -4520,14 +4270,12 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp4b = and <4 x i32> %tmp4, %tmp5 = icmp ne <4 x i32> %tmp4b, zeroinitializer %tmp6 = select <4 x i1> %tmp5, <4 x i32> , <4 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4536,7 +4284,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_ptestnm_v4i32(i32* %arg) { +define void @bcast_unfold_ptestnm_v4i32(ptr %arg) { ; CHECK-LABEL: bcast_unfold_ptestnm_v4i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -4557,14 +4305,12 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp3 = bitcast i32* %tmp2 to <4 x i32>* - %tmp4 = load <4 x i32>, <4 x i32>* %tmp3, align 4 + %tmp2 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp4 = load <4 x i32>, ptr %tmp2, align 4 %tmp4b = and <4 x i32> %tmp4, %tmp5 = icmp eq <4 x i32> %tmp4b, zeroinitializer %tmp6 = select <4 x i1> %tmp5, <4 x i32> , <4 x i32> %tmp4 - %tmp7 = bitcast i32* %tmp2 to <4 x i32>* - store <4 x i32> %tmp6, <4 x i32>* %tmp7, align 4 + store <4 x i32> %tmp6, ptr %tmp2, align 4 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4573,7 +4319,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_ptestm_v4i64(i64* %arg) { +define void @bcast_unfold_ptestm_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_ptestm_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -4595,14 +4341,12 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 8 %tmp4b = and <4 x i64> %tmp4, %tmp5 = icmp ne <4 x i64> %tmp4b, zeroinitializer %tmp6 = select <4 x i1> %tmp5, <4 x i64> , <4 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 8 + store <4 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4611,7 +4355,7 @@ bb10: ; preds = %bb1 ret void } -define void @bcast_unfold_ptestnm_v4i64(i64* %arg) { +define void @bcast_unfold_ptestnm_v4i64(ptr %arg) { ; CHECK-LABEL: bcast_unfold_ptestnm_v4i64: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000 @@ -4633,14 +4377,12 @@ bb: bb1: ; preds = %bb1, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ] - %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp - %tmp3 = bitcast i64* %tmp2 to <4 x i64>* - %tmp4 = load <4 x i64>, <4 x i64>* %tmp3, align 8 + %tmp2 = getelementptr inbounds i64, ptr %arg, i64 %tmp + %tmp4 = load <4 x i64>, ptr %tmp2, align 8 %tmp4b = and <4 x i64> %tmp4, %tmp5 = icmp eq <4 x i64> %tmp4b, zeroinitializer %tmp6 = select <4 x i1> %tmp5, <4 x i64> , <4 x i64> %tmp4 - %tmp7 = bitcast i64* %tmp2 to <4 x i64>* - store <4 x i64> %tmp6, <4 x i64>* %tmp7, align 8 + store <4 x i64> %tmp6, ptr %tmp2, align 8 %tmp8 = add i64 %tmp, 4 %tmp9 = icmp eq i64 %tmp8, 1024 br i1 %tmp9, label %bb10, label %bb1 @@ -4649,10 +4391,7 @@ bb10: ; preds = %bb1 ret void } -; The or/and pattern here should be turned into vpternlog. The multiply is -; there to increase the use count of the loads so they can't fold. We want to -; unfold the broadcast and pull it out of the loop. -define void @bcast_unfold_vpternlog_v16i32(i32* %arg, i32* %arg1) { +define void @bcast_unfold_vpternlog_v16i32(ptr %arg, ptr %arg1) { ; CHECK-LABEL: bcast_unfold_vpternlog_v16i32: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: movq $-4096, %rax # imm = 0xF000 @@ -4676,19 +4415,16 @@ bb: bb2: ; preds = %bb2, %bb %tmp = phi i64 [ 0, %bb ], [ %tmp18, %bb2 ] - %tmp3 = getelementptr inbounds i32, i32* %arg, i64 %tmp - %tmp4 = bitcast i32* %tmp3 to <16 x i32>* - %tmp5 = load <16 x i32>, <16 x i32>* %tmp4, align 4 - %tmp6 = getelementptr inbounds i32, i32* %arg1, i64 %tmp - %tmp10 = bitcast i32* %tmp6 to <16 x i32>* - %tmp11 = load <16 x i32>, <16 x i32>* %tmp10, align 4 + %tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp + %tmp5 = load <16 x i32>, ptr %tmp3, align 4 + %tmp6 = getelementptr inbounds i32, ptr %arg1, i64 %tmp + %tmp11 = load <16 x i32>, ptr %tmp6, align 4 %tmp12 = and <16 x i32> %tmp5, %tmp13 = and <16 x i32> %tmp11, %tmp14 = or <16 x i32> %tmp12, %tmp13 %tmp15 = mul <16 x i32> %tmp14, %tmp5 %tmp16 = mul <16 x i32> %tmp15, %tmp11 - %tmp17 = bitcast i32* %tmp3 to <16 x i32>* - store <16 x i32> %tmp16, <16 x i32>* %tmp17, align 4 + store <16 x i32> %tmp16, ptr %tmp3, align 4 %tmp18 = add i64 %tmp, 16 %tmp19 = icmp eq i64 %tmp18, 1024 br i1 %tmp19, label %bb20, label %bb2 @@ -4697,3 +4433,4 @@ bb20: ; preds = %bb2 ret void } +attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } diff --git a/llvm/test/CodeGen/X86/avx512vnni-combine.ll b/llvm/test/CodeGen/X86/avx512vnni-combine.ll index f0c8a7e20832..c491a952682d 100644 --- a/llvm/test/CodeGen/X86/avx512vnni-combine.ll +++ b/llvm/test/CodeGen/X86/avx512vnni-combine.ll @@ -135,17 +135,17 @@ define <8 x i64> @foo_512(i32 %0, <8 x i64> %1, <8 x i64> %2, ptr %3) { %40 = load <32 x i16>, ptr %39, align 64 %41 = tail call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %7, <32 x i16> %40) %42 = add <16 x i32> %41, %37 - %43 = or i64 %36, 1 + %43 = or disjoint i64 %36, 1 %44 = getelementptr inbounds <8 x i64>, ptr %3, i64 %43 %45 = load <32 x i16>, ptr %44, align 64 %46 = tail call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %7, <32 x i16> %45) %47 = add <16 x i32> %46, %42 - %48 = or i64 %36, 2 + %48 = or disjoint i64 %36, 2 %49 = getelementptr inbounds <8 x i64>, ptr %3, i64 %48 %50 = load <32 x i16>, ptr %49, align 64 %51 = tail call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %7, <32 x i16> %50) %52 = add <16 x i32> %51, %47 - %53 = or i64 %36, 3 + %53 = or disjoint i64 %36, 3 %54 = getelementptr inbounds <8 x i64>, ptr %3, i64 %53 %55 = load <32 x i16>, ptr %54, align 64 %56 = tail call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %7, <32 x i16> %55) @@ -243,7 +243,7 @@ define void @bar_512(i32 %0, ptr %1, <8 x i64> %2, ptr %3) { %29 = load <16 x i32>, ptr %28, align 64 %30 = tail call <16 x i32> @llvm.x86.avx512.vpdpwssd.512(<16 x i32> %29, <16 x i32> %7, <16 x i32> %27) store <16 x i32> %30, ptr %28, align 64 - %31 = or i64 %24, 1 + %31 = or disjoint i64 %24, 1 %32 = getelementptr inbounds <8 x i64>, ptr %3, i64 %31 %33 = load <16 x i32>, ptr %32, align 64 %34 = getelementptr inbounds <8 x i64>, ptr %1, i64 %31 diff --git a/llvm/test/CodeGen/X86/avxvnni-combine.ll b/llvm/test/CodeGen/X86/avxvnni-combine.ll index 75e29df9f34a..158a1fdf44fc 100644 --- a/llvm/test/CodeGen/X86/avxvnni-combine.ll +++ b/llvm/test/CodeGen/X86/avxvnni-combine.ll @@ -187,17 +187,17 @@ define <2 x i64> @foo_128(i32 %0, <2 x i64> %1, <2 x i64> %2, ptr %3) { %40 = load <8 x i16>, ptr %39, align 16 %41 = tail call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %7, <8 x i16> %40) %42 = add <4 x i32> %41, %37 - %43 = or i64 %36, 1 + %43 = or disjoint i64 %36, 1 %44 = getelementptr inbounds <2 x i64>, ptr %3, i64 %43 %45 = load <8 x i16>, ptr %44, align 16 %46 = tail call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %7, <8 x i16> %45) %47 = add <4 x i32> %46, %42 - %48 = or i64 %36, 2 + %48 = or disjoint i64 %36, 2 %49 = getelementptr inbounds <2 x i64>, ptr %3, i64 %48 %50 = load <8 x i16>, ptr %49, align 16 %51 = tail call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %7, <8 x i16> %50) %52 = add <4 x i32> %51, %47 - %53 = or i64 %36, 3 + %53 = or disjoint i64 %36, 3 %54 = getelementptr inbounds <2 x i64>, ptr %3, i64 %53 %55 = load <8 x i16>, ptr %54, align 16 %56 = tail call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %7, <8 x i16> %55) @@ -328,7 +328,7 @@ define void @bar_128(i32 %0, ptr %1, <2 x i64> %2, ptr %3) { %29 = load <4 x i32>, ptr %28, align 16 %30 = tail call <4 x i32> @llvm.x86.avx512.vpdpwssd.128(<4 x i32> %29, <4 x i32> %7, <4 x i32> %27) store <4 x i32> %30, ptr %28, align 16 - %31 = or i64 %24, 1 + %31 = or disjoint i64 %24, 1 %32 = getelementptr inbounds <2 x i64>, ptr %3, i64 %31 %33 = load <4 x i32>, ptr %32, align 16 %34 = getelementptr inbounds <2 x i64>, ptr %1, i64 %31 @@ -534,17 +534,17 @@ define <4 x i64> @foo_256(i32 %0, <4 x i64> %1, <4 x i64> %2, ptr %3) { %40 = load <16 x i16>, ptr %39, align 32 %41 = tail call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %7, <16 x i16> %40) %42 = add <8 x i32> %41, %37 - %43 = or i64 %36, 1 + %43 = or disjoint i64 %36, 1 %44 = getelementptr inbounds <4 x i64>, ptr %3, i64 %43 %45 = load <16 x i16>, ptr %44, align 32 %46 = tail call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %7, <16 x i16> %45) %47 = add <8 x i32> %46, %42 - %48 = or i64 %36, 2 + %48 = or disjoint i64 %36, 2 %49 = getelementptr inbounds <4 x i64>, ptr %3, i64 %48 %50 = load <16 x i16>, ptr %49, align 32 %51 = tail call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %7, <16 x i16> %50) %52 = add <8 x i32> %51, %47 - %53 = or i64 %36, 3 + %53 = or disjoint i64 %36, 3 %54 = getelementptr inbounds <4 x i64>, ptr %3, i64 %53 %55 = load <16 x i16>, ptr %54, align 32 %56 = tail call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %7, <16 x i16> %55) @@ -684,7 +684,7 @@ define void @bar_256(i32 %0, ptr %1, <4 x i64> %2, ptr %3) { %29 = load <8 x i32>, ptr %28, align 32 %30 = tail call <8 x i32> @llvm.x86.avx512.vpdpwssd.256(<8 x i32> %29, <8 x i32> %7, <8 x i32> %27) store <8 x i32> %30, ptr %28, align 32 - %31 = or i64 %24, 1 + %31 = or disjoint i64 %24, 1 %32 = getelementptr inbounds <4 x i64>, ptr %3, i64 %31 %33 = load <8 x i32>, ptr %32, align 32 %34 = getelementptr inbounds <4 x i64>, ptr %1, i64 %31 diff --git a/llvm/test/CodeGen/X86/code-model-elf-sections.ll b/llvm/test/CodeGen/X86/code-model-elf-sections.ll index 0b99a70c4044..749d5b6bf904 100644 --- a/llvm/test/CodeGen/X86/code-model-elf-sections.ll +++ b/llvm/test/CodeGen/X86/code-model-elf-sections.ll @@ -21,9 +21,16 @@ ; SMALL: .data {{.*}} WA {{.*}} ; SMALL: .data.x {{.*}} WA {{.*}} ; SMALL: .data0 {{.*}} WA {{.*}} +; SMALL: .ldata {{.*}} WAl {{.*}} +; SMALL: .ldata.x {{.*}} WAl {{.*}} +; SMALL: .ldata0 {{.*}} WA {{.*}} +; SMALL: force_small {{.*}} WA {{.*}} +; SMALL: force_large {{.*}} WAl {{.*}} ; SMALL: foo {{.*}} WA {{.*}} ; SMALL: .bss {{.*}} WA {{.*}} +; SMALL: .lbss {{.*}} WAl {{.*}} ; SMALL: .rodata {{.*}} A {{.*}} +; SMALL: .lrodata {{.*}} Al {{.*}} ; SMALL: .data.rel.ro {{.*}} WA {{.*}} ; SMALL: .tbss {{.*}} WAT {{.*}} ; SMALL: .tdata {{.*}} WAT {{.*}} @@ -31,9 +38,16 @@ ; SMALL-DS: .data {{.*}} WA {{.*}} ; SMALL-DS: .data.x {{.*}} WA {{.*}} ; SMALL-DS: .data0 {{.*}} WA {{.*}} +; SMALL-DS: .ldata {{.*}} WAl {{.*}} +; SMALL-DS: .ldata.x {{.*}} WAl {{.*}} +; SMALL-DS: .ldata0 {{.*}} WA {{.*}} ; SMALL-DS: .data.data {{.*}} WA {{.*}} +; SMALL-DS: force_small {{.*}} WA {{.*}} +; SMALL-DS: force_large {{.*}} WAl {{.*}} ; SMALL-DS: foo {{.*}} WA {{.*}} +; SMALL-DS: .lbss {{.*}} WAl {{.*}} ; SMALL-DS: .bss.bss {{.*}} WA {{.*}} +; SMALL-DS: .lrodata {{.*}} Al {{.*}} ; SMALL-DS: .rodata.rodata {{.*}} A {{.*}} ; SMALL-DS: .data.rel.ro.relro {{.*}} WA {{.*}} ; SMALL-DS: .tbss.tbss {{.*}} WAT {{.*}} @@ -43,6 +57,10 @@ ; LARGE: .data.x {{.*}} WA {{.*}} ; LARGE: .data0 {{.*}} WAl {{.*}} ; LARGE: .ldata {{.*}} WAl {{.*}} +; LARGE: .ldata.x {{.*}} WAl {{.*}} +; LARGE: .ldata0 {{.*}} WAl {{.*}} +; LARGE: force_small {{.*}} WA {{.*}} +; LARGE: force_large {{.*}} WAl {{.*}} ; LARGE: foo {{.*}} WAl {{.*}} ; LARGE: .bss {{.*}} WA {{.*}} ; LARGE: .lbss {{.*}} WAl {{.*}} @@ -55,7 +73,12 @@ ; LARGE-DS: .data {{.*}} WA {{.*}} ; LARGE-DS: .data.x {{.*}} WA {{.*}} ; LARGE-DS: .data0 {{.*}} WAl {{.*}} +; LARGE-DS: .ldata {{.*}} WAl {{.*}} +; LARGE-DS: .ldata.x {{.*}} WAl {{.*}} +; LARGE-DS: .ldata0 {{.*}} WAl {{.*}} ; LARGE-DS: .ldata.data {{.*}} WAl {{.*}} +; LARGE-DS: force_small {{.*}} WA {{.*}} +; LARGE-DS: force_large {{.*}} WAl {{.*}} ; LARGE-DS: foo {{.*}} WAl {{.*}} ; LARGE-DS: .bss {{.*}} WA {{.*}} ; LARGE-DS: .lbss.bss {{.*}} WAl {{.*}} @@ -71,11 +94,20 @@ target triple = "x86_64--linux" @data_with_explicit_section = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], section ".data" @data_with_explicit_section2 = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], section ".data.x" @data_with_explicit_section0 = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], section ".data0" +@ldata_with_explicit_section = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], section ".ldata" +@ldata_with_explicit_section2 = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], section ".ldata.x" +@ldata_with_explicit_section0 = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], section ".ldata0" @data = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0] +@data_force_small = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], code_model "small", section "force_small" +@data_force_large = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], code_model "large", section "force_large" +@data_force_small_ldata = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], code_model "small", section ".ldata" +@data_force_large_data = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], code_model "large", section ".data" @foo_with_explicit_section = internal global [10 x i64] [i64 1, i64 2, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0], section "foo" @bss_with_explicit_section = internal global [10 x i64] zeroinitializer, section ".bss" +@lbss_with_explicit_section = internal global [10 x i64] zeroinitializer, section ".lbss" @bss = internal global [10 x i64] zeroinitializer @rodata_with_explicit_section = internal constant [10 x i64] zeroinitializer, section ".rodata" +@lrodata_with_explicit_section = internal constant [10 x i64] zeroinitializer, section ".lrodata" @rodata = internal constant [10 x i64] zeroinitializer @relro = internal constant [10 x ptr] [ptr @func, ptr @func, ptr @func, ptr @func, ptr @func, ptr @func, ptr @func, ptr @func, ptr @func, ptr @func] @tbss = internal thread_local global [10 x i64] zeroinitializer diff --git a/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll b/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll index 88425ea87845..5dcb1d63207d 100644 --- a/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll +++ b/llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=basic | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=basic | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -regalloc=basic | FileCheck %s --check-prefix=X64 ; This testcase should need to spill the -1 value on both x86-32 and x86-64, @@ -15,87 +15,87 @@ %struct._image2d_t = type <{ ptr, %struct._cl_image_format_t, i32, i32, i32, i32, i32, i32 }> define void @program_1(ptr %dest, ptr %t0, <4 x float> %p0, <4 x float> %p1, <4 x float> %p4, <4 x float> %p5, <4 x float> %p6) nounwind { -; X32-LABEL: program_1: -; X32: ## %bb.0: ## %entry -; X32-NEXT: cmpl $0, 0 -; X32-NEXT: jle LBB0_2 -; X32-NEXT: ## %bb.1: ## %forcond -; X32-NEXT: cmpl $0, 0 -; X32-NEXT: jg LBB0_3 -; X32-NEXT: LBB0_2: ## %ifthen -; X32-NEXT: retl -; X32-NEXT: LBB0_3: ## %forbody -; X32-NEXT: pushl %esi -; X32-NEXT: subl $88, %esp -; X32-NEXT: movaps {{.*#+}} xmm1 = [1.28E+2,1.28E+2,1.28E+2,1.28E+2] -; X32-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 -; X32-NEXT: cvttps2dq %xmm1, %xmm0 -; X32-NEXT: cvtdq2ps %xmm0, %xmm0 -; X32-NEXT: subps %xmm0, %xmm1 -; X32-NEXT: movaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: mulps %xmm1, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: mulps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: cmpunordps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) -; X32-NEXT: movl $0, (%esp) -; X32-NEXT: xorl %esi, %esi -; X32-NEXT: xorps %xmm3, %xmm3 -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload -; X32-NEXT: calll *%esi -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: pxor %xmm1, %xmm1 -; X32-NEXT: psubd {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Folded Reload -; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X32-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: por %xmm1, %xmm0 -; X32-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill -; X32-NEXT: pxor %xmm0, %xmm0 -; X32-NEXT: movdqa %xmm0, {{[0-9]+}}(%esp) -; X32-NEXT: movl $0, (%esp) -; X32-NEXT: xorps %xmm3, %xmm3 -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload -; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload -; X32-NEXT: calll *%esi -; X32-NEXT: ud2 +; X86-LABEL: program_1: +; X86: ## %bb.0: ## %entry +; X86-NEXT: cmpl $0, 0 +; X86-NEXT: jle LBB0_2 +; X86-NEXT: ## %bb.1: ## %forcond +; X86-NEXT: cmpl $0, 0 +; X86-NEXT: jg LBB0_3 +; X86-NEXT: LBB0_2: ## %ifthen +; X86-NEXT: retl +; X86-NEXT: LBB0_3: ## %forbody +; X86-NEXT: pushl %esi +; X86-NEXT: subl $88, %esp +; X86-NEXT: movaps {{.*#+}} xmm1 = [1.28E+2,1.28E+2,1.28E+2,1.28E+2] +; X86-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 +; X86-NEXT: cvttps2dq %xmm1, %xmm0 +; X86-NEXT: cvtdq2ps %xmm0, %xmm0 +; X86-NEXT: subps %xmm0, %xmm1 +; X86-NEXT: movaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: mulps %xmm1, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: mulps %xmm0, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: cmpunordps %xmm0, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) +; X86-NEXT: movl $0, (%esp) +; X86-NEXT: xorl %esi, %esi +; X86-NEXT: xorps %xmm3, %xmm3 +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload +; X86-NEXT: calll *%esi +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: minps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: pxor %xmm1, %xmm1 +; X86-NEXT: psubd {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Folded Reload +; X86-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: por %xmm1, %xmm0 +; X86-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill +; X86-NEXT: pxor %xmm0, %xmm0 +; X86-NEXT: movdqa %xmm0, {{[0-9]+}}(%esp) +; X86-NEXT: movl $0, (%esp) +; X86-NEXT: xorps %xmm3, %xmm3 +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload +; X86-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload +; X86-NEXT: calll *%esi +; X86-NEXT: ud2 ; ; X64-LABEL: program_1: ; X64: ## %bb.0: ## %entry diff --git a/llvm/test/CodeGen/X86/loop-strength-reduce4.ll b/llvm/test/CodeGen/X86/loop-strength-reduce4.ll index 3e4d620b6dc8..4bb1150bf702 100644 --- a/llvm/test/CodeGen/X86/loop-strength-reduce4.ll +++ b/llvm/test/CodeGen/X86/loop-strength-reduce4.ll @@ -35,21 +35,21 @@ bb: ; preds = %bb, %entry %tmp7 = load i32, ptr %tmp6, align 4 ; [#uses=1] %tmp8 = xor i32 %tmp7, %tmp4 ; [#uses=2] store i32 %tmp8, ptr %tmp3, align 4 - %tmp1378 = or i32 %j.065.0, 1 ; [#uses=1] + %tmp1378 = or disjoint i32 %j.065.0, 1 ; [#uses=1] %tmp16 = getelementptr [0 x i32], ptr @state, i32 0, i32 %tmp1378 ; [#uses=2] %tmp17 = load i32, ptr %tmp16, align 4 ; [#uses=1] %tmp19 = getelementptr [0 x i32], ptr @S, i32 0, i32 %tmp8 ; [#uses=1] %tmp20 = load i32, ptr %tmp19, align 4 ; [#uses=1] %tmp21 = xor i32 %tmp20, %tmp17 ; [#uses=2] store i32 %tmp21, ptr %tmp16, align 4 - %tmp2680 = or i32 %j.065.0, 2 ; [#uses=1] + %tmp2680 = or disjoint i32 %j.065.0, 2 ; [#uses=1] %tmp29 = getelementptr [0 x i32], ptr @state, i32 0, i32 %tmp2680 ; [#uses=2] %tmp30 = load i32, ptr %tmp29, align 4 ; [#uses=1] %tmp32 = getelementptr [0 x i32], ptr @S, i32 0, i32 %tmp21 ; [#uses=1] %tmp33 = load i32, ptr %tmp32, align 4 ; [#uses=1] %tmp34 = xor i32 %tmp33, %tmp30 ; [#uses=2] store i32 %tmp34, ptr %tmp29, align 4 - %tmp3982 = or i32 %j.065.0, 3 ; [#uses=1] + %tmp3982 = or disjoint i32 %j.065.0, 3 ; [#uses=1] %tmp42 = getelementptr [0 x i32], ptr @state, i32 0, i32 %tmp3982 ; [#uses=2] %tmp43 = load i32, ptr %tmp42, align 4 ; [#uses=1] %tmp45 = getelementptr [0 x i32], ptr @S, i32 0, i32 %tmp34 ; [#uses=1] diff --git a/llvm/test/CodeGen/X86/lsr-addrecloops.ll b/llvm/test/CodeGen/X86/lsr-addrecloops.ll index b0f97e3fc2a3..74a8d68a850f 100644 --- a/llvm/test/CodeGen/X86/lsr-addrecloops.ll +++ b/llvm/test/CodeGen/X86/lsr-addrecloops.ll @@ -68,25 +68,25 @@ vector.body807: ; preds = %vector.body807, %ve %niter = phi i64 [ 0, %vector.body807.preheader.new ], [ %niter.next.7, %vector.body807 ] %uglygep1197 = getelementptr i8, ptr %lsr.iv1135, i64 %lsr.iv1194 store <8 x float> zeroinitializer, ptr %uglygep1197, align 4 - %lsr.iv.next1195 = or i64 %lsr.iv1194, 1 + %lsr.iv.next1195 = or disjoint i64 %lsr.iv1194, 1 %uglygep1197.1 = getelementptr i8, ptr %lsr.iv1135, i64 %lsr.iv.next1195 store <8 x float> zeroinitializer, ptr %uglygep1197.1, align 4 - %lsr.iv.next1195.1 = or i64 %lsr.iv1194, 2 + %lsr.iv.next1195.1 = or disjoint i64 %lsr.iv1194, 2 %uglygep1197.2 = getelementptr i8, ptr %lsr.iv1135, i64 %lsr.iv.next1195.1 store <8 x float> zeroinitializer, ptr %uglygep1197.2, align 4 - %lsr.iv.next1195.2 = or i64 %lsr.iv1194, 3 + %lsr.iv.next1195.2 = or disjoint i64 %lsr.iv1194, 3 %uglygep1197.3 = getelementptr i8, ptr %lsr.iv1135, i64 %lsr.iv.next1195.2 store <8 x float> zeroinitializer, ptr %uglygep1197.3, align 4 - %lsr.iv.next1195.3 = or i64 %lsr.iv1194, 4 + %lsr.iv.next1195.3 = or disjoint i64 %lsr.iv1194, 4 %uglygep1197.4 = getelementptr i8, ptr %lsr.iv1135, i64 %lsr.iv.next1195.3 store <8 x float> zeroinitializer, ptr %uglygep1197.4, align 4 - %lsr.iv.next1195.4 = or i64 %lsr.iv1194, 5 + %lsr.iv.next1195.4 = or disjoint i64 %lsr.iv1194, 5 %uglygep1197.5 = getelementptr i8, ptr %lsr.iv1135, i64 %lsr.iv.next1195.4 store <8 x float> zeroinitializer, ptr %uglygep1197.5, align 4 - %lsr.iv.next1195.5 = or i64 %lsr.iv1194, 6 + %lsr.iv.next1195.5 = or disjoint i64 %lsr.iv1194, 6 %uglygep1197.6 = getelementptr i8, ptr %lsr.iv1135, i64 %lsr.iv.next1195.5 store <8 x float> zeroinitializer, ptr %uglygep1197.6, align 4 - %lsr.iv.next1195.6 = or i64 %lsr.iv1194, 7 + %lsr.iv.next1195.6 = or disjoint i64 %lsr.iv1194, 7 %uglygep1197.7 = getelementptr i8, ptr %lsr.iv1135, i64 %lsr.iv.next1195.6 store <8 x float> zeroinitializer, ptr %uglygep1197.7, align 4 %lsr.iv.next1195.7 = add i64 %lsr.iv1194, 8 @@ -136,25 +136,25 @@ vector.body847: ; preds = %vector.body847, %ve %niter16 = phi i64 [ 0, %vector.body847.preheader.new ], [ %niter16.next.7, %vector.body847 ] %uglygep1156 = getelementptr i8, ptr %uglygep11551, i64 %lsr.iv1152 store <8 x float> zeroinitializer, ptr %uglygep1156, align 4 - %lsr.iv.next1153 = or i64 %lsr.iv1152, 1 + %lsr.iv.next1153 = or disjoint i64 %lsr.iv1152, 1 %uglygep1156.1 = getelementptr i8, ptr %uglygep11551, i64 %lsr.iv.next1153 store <8 x float> zeroinitializer, ptr %uglygep1156.1, align 4 - %lsr.iv.next1153.1 = or i64 %lsr.iv1152, 2 + %lsr.iv.next1153.1 = or disjoint i64 %lsr.iv1152, 2 %uglygep1156.2 = getelementptr i8, ptr %uglygep11551, i64 %lsr.iv.next1153.1 store <8 x float> zeroinitializer, ptr %uglygep1156.2, align 4 - %lsr.iv.next1153.2 = or i64 %lsr.iv1152, 3 + %lsr.iv.next1153.2 = or disjoint i64 %lsr.iv1152, 3 %uglygep1156.3 = getelementptr i8, ptr %uglygep11551, i64 %lsr.iv.next1153.2 store <8 x float> zeroinitializer, ptr %uglygep1156.3, align 4 - %lsr.iv.next1153.3 = or i64 %lsr.iv1152, 4 + %lsr.iv.next1153.3 = or disjoint i64 %lsr.iv1152, 4 %uglygep1156.4 = getelementptr i8, ptr %uglygep11551, i64 %lsr.iv.next1153.3 store <8 x float> zeroinitializer, ptr %uglygep1156.4, align 4 - %lsr.iv.next1153.4 = or i64 %lsr.iv1152, 5 + %lsr.iv.next1153.4 = or disjoint i64 %lsr.iv1152, 5 %uglygep1156.5 = getelementptr i8, ptr %uglygep11551, i64 %lsr.iv.next1153.4 store <8 x float> zeroinitializer, ptr %uglygep1156.5, align 4 - %lsr.iv.next1153.5 = or i64 %lsr.iv1152, 6 + %lsr.iv.next1153.5 = or disjoint i64 %lsr.iv1152, 6 %uglygep1156.6 = getelementptr i8, ptr %uglygep11551, i64 %lsr.iv.next1153.5 store <8 x float> zeroinitializer, ptr %uglygep1156.6, align 4 - %lsr.iv.next1153.6 = or i64 %lsr.iv1152, 7 + %lsr.iv.next1153.6 = or disjoint i64 %lsr.iv1152, 7 %uglygep1156.7 = getelementptr i8, ptr %uglygep11551, i64 %lsr.iv.next1153.6 store <8 x float> zeroinitializer, ptr %uglygep1156.7, align 4 %lsr.iv.next1153.7 = add i64 %lsr.iv1152, 8 diff --git a/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll b/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll index a2e4e4784d36..85449b01265b 100644 --- a/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll +++ b/llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll @@ -195,7 +195,7 @@ bb: ; preds = %bb1, %entry %9 = zext i32 %8 to i64 ; [#uses=1] %10 = getelementptr [256 x i32], [256 x i32]* @Te1, i64 0, i64 %9 ; [#uses=1] %11 = load i32, i32* %10, align 4 ; [#uses=1] - %ctg2.sum2728 = or i64 %tmp18, 8 ; [#uses=1] + %ctg2.sum2728 = or disjoint i64 %tmp18, 8 ; [#uses=1] %12 = getelementptr i8, i8* %rk26, i64 %ctg2.sum2728 ; [#uses=1] %13 = bitcast i8* %12 to i32* ; [#uses=1] %14 = load i32, i32* %13, align 4 ; [#uses=1] @@ -209,7 +209,7 @@ bb: ; preds = %bb1, %entry %22 = zext i32 %21 to i64 ; [#uses=1] %23 = getelementptr [256 x i32], [256 x i32]* @Te3, i64 0, i64 %22 ; [#uses=1] %24 = load i32, i32* %23, align 4 ; [#uses=1] - %ctg2.sum2930 = or i64 %tmp18, 12 ; [#uses=1] + %ctg2.sum2930 = or disjoint i64 %tmp18, 12 ; [#uses=1] %25 = getelementptr i8, i8* %rk26, i64 %ctg2.sum2930 ; [#uses=1] %26 = bitcast i8* %25 to i32* ; [#uses=1] %27 = load i32, i32* %26, align 4 ; [#uses=1] diff --git a/llvm/test/CodeGen/X86/merge_store.ll b/llvm/test/CodeGen/X86/merge_store.ll index 0e57b43d2f84..1cf3b9a83bac 100644 --- a/llvm/test/CodeGen/X86/merge_store.ll +++ b/llvm/test/CodeGen/X86/merge_store.ll @@ -23,13 +23,13 @@ entry: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv store i32 1, ptr %arrayidx, align 4 - %0 = or i64 %indvars.iv, 1 + %0 = or disjoint i64 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds i32, ptr %a, i64 %0 store i32 1, ptr %arrayidx2, align 4 - %1 = or i64 %indvars.iv, 2 + %1 = or disjoint i64 %indvars.iv, 2 %arrayidx5 = getelementptr inbounds i32, ptr %a, i64 %1 store i32 1, ptr %arrayidx5, align 4 - %2 = or i64 %indvars.iv, 3 + %2 = or disjoint i64 %indvars.iv, 3 %arrayidx8 = getelementptr inbounds i32, ptr %a, i64 %2 store i32 1, ptr %arrayidx8, align 4 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 4 diff --git a/llvm/test/CodeGen/X86/optimize-max-0.ll b/llvm/test/CodeGen/X86/optimize-max-0.ll index 4b398095b549..1bd427c4a4b0 100644 --- a/llvm/test/CodeGen/X86/optimize-max-0.ll +++ b/llvm/test/CodeGen/X86/optimize-max-0.ll @@ -324,7 +324,7 @@ bb14: ; preds = %bb15, %bb.nph3 %29 = getelementptr i8, ptr %j, i32 %.sum store i8 %28, ptr %29, align 1 %30 = shl i32 %x.12, 2 - %31 = or i32 %30, 2 + %31 = or disjoint i32 %30, 2 %32 = add i32 %31, %21 %33 = getelementptr i8, ptr %r, i32 %32 %34 = load i8, ptr %33, align 1 @@ -761,7 +761,7 @@ bb14: ; preds = %bb15, %bb.nph3 %29 = getelementptr i8, ptr %j, i32 %.sum store i8 %28, ptr %29, align 1 %30 = shl i32 %x.12, 2 - %31 = or i32 %30, 2 + %31 = or disjoint i32 %30, 2 %32 = add i32 %31, %21 %33 = getelementptr i8, ptr %r, i32 %32 %34 = load i8, ptr %33, align 1 diff --git a/llvm/test/CodeGen/X86/preserve_mostcc64_win.ll b/llvm/test/CodeGen/X86/preserve_mostcc64_win.ll new file mode 100644 index 000000000000..7042a2e77da1 --- /dev/null +++ b/llvm/test/CodeGen/X86/preserve_mostcc64_win.ll @@ -0,0 +1,91 @@ +; RUN: sed -e "s/RETTYPE/void/;s/RETVAL//" %s | llc -mtriple=x86_64-win32 -mcpu=corei7 | FileCheck --check-prefixes=ALL,VOID %s +; RUN: sed -e "s/RETTYPE/i32/;s/RETVAL/undef/" %s | llc -mtriple=x86_64-win32 -mcpu=corei7 | FileCheck --check-prefixes=ALL,INT %s +; RUN: sed -e "s/RETTYPE/\{i64\,i64\}/;s/RETVAL/undef/" %s | llc -mtriple=x86_64-win32 -mcpu=corei7 | FileCheck --check-prefixes=ALL,INT128 %s + +; Every GPR should be saved, except r11 and return registers. +; XMM registers 6-15 should also be saved. +define preserve_mostcc RETTYPE @preserve_mostcc1(i64, i64, double, double) nounwind { +entry: +;ALL-LABEL: preserve_mostcc1 +;ALL: pushq %r10 +;ALL-NEXT: pushq %r9 +;ALL-NEXT: pushq %r8 +;ALL-NEXT: pushq %rdi +;ALL-NEXT: pushq %rsi +;VOID-NEXT: pushq %rdx +;INT-NEXT: pushq %rdx +;INT128-NOT: pushq %rdx +;ALL-NEXT: pushq %rcx +;VOID-NEXT: pushq %rax +;INT-NOT: pushq %rax +;INT128-NOT: pushq %rax +;ALL-NEXT: pushq %rbp +;ALL-NEXT: pushq %r15 +;ALL-NEXT: pushq %r14 +;ALL-NEXT: pushq %r13 +;ALL-NEXT: pushq %r12 +;ALL-NEXT: pushq %rbx +;ALL: movaps %xmm15 +;ALL-NEXT: movaps %xmm14 +;ALL-NEXT: movaps %xmm13 +;ALL-NEXT: movaps %xmm12 +;ALL-NEXT: movaps %xmm11 +;ALL-NEXT: movaps %xmm10 +;ALL-NEXT: movaps %xmm9 +;ALL-NEXT: movaps %xmm8 +;ALL-NEXT: movaps %xmm7 +;ALL-NEXT: movaps %xmm6 +;ALL-NOT: movaps %xmm5 +;ALL-NOT: movaps %xmm4 +;ALL-NOT: movaps %xmm3 +;ALL-NOT: movaps %xmm2 +;ALL-NOT: movaps %xmm1 +;ALL-NOT: movaps %xmm0 +;ALL-NOT: movaps {{.*}} %xmm0 +;ALL-NOT: movaps {{.*}} %xmm1 +;ALL-NOT: movaps {{.*}} %xmm2 +;ALL-NOT: movaps {{.*}} %xmm3 +;ALL-NOT: movaps {{.*}} %xmm4 +;ALL-NOT: movaps {{.*}} %xmm5 +;ALL: movaps {{.*}} %xmm6 +;ALL-NEXT: movaps {{.*}} %xmm7 +;ALL-NEXT: movaps {{.*}} %xmm8 +;ALL-NEXT: movaps {{.*}} %xmm9 +;ALL-NEXT: movaps {{.*}} %xmm10 +;ALL-NEXT: movaps {{.*}} %xmm11 +;ALL-NEXT: movaps {{.*}} %xmm12 +;ALL-NEXT: movaps {{.*}} %xmm13 +;ALL-NEXT: movaps {{.*}} %xmm14 +;ALL-NEXT: movaps {{.*}} %xmm15 +;ALL: popq %rbx +;ALL-NEXT: popq %r12 +;ALL-NEXT: popq %r13 +;ALL-NEXT: popq %r14 +;ALL-NEXT: popq %r15 +;ALL-NEXT: popq %rbp +;VOID-NEXT: popq %rax +;INT-NOT: popq %rax +;INT128-NOT: popq %rax +;ALL-NEXT: popq %rcx +;VOID-NEXT: popq %rdx +;INT-NEXT: popq %rdx +;INT128-NOT: popq %rdx +;ALL-NEXT: popq %rsi +;ALL-NEXT: popq %rdi +;ALL-NEXT: popq %r8 +;ALL-NEXT: popq %r9 +;ALL-NEXT: popq %r10 + call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{rbp},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15}"() + ret RETTYPE RETVAL +} + +; Make sure XMMs are not saved before the call +declare preserve_mostcc RETTYPE @foo(i64, i64, double, double) +define void @preserve_mostcc2() nounwind { +entry: +;ALL-LABEL: preserve_mostcc2 +;ALL-NOT: movaps +;ALL-NOT: {{.*xmm[0-1,4-9].*}} + call preserve_mostcc RETTYPE @foo(i64 1, i64 2, double 3.0, double 4.0) + ret void +} diff --git a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll index ce3e1840797b..85afa83e3f08 100644 --- a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll +++ b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll @@ -1,59 +1,59 @@ ; Intel chips with slow unaligned memory accesses -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefix=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefixes=SLOW ; Intel chips with fast unaligned memory accesses -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nehalem 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=westmere 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=sandybridge 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=ivybridge 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=haswell 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=broadwell 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=knl 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=skylake-avx512 2>&1 | FileCheck %s --check-prefix=FAST +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nehalem 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=westmere 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=sandybridge 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX128 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=ivybridge 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX128 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=haswell 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=broadwell 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=knl 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=skylake-avx512 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 ; AMD chips with slow unaligned memory accesses -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-fx 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8-sse3 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron-sse3 2>&1 | FileCheck %s --check-prefix=SLOW -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64-sse3 2>&1 | FileCheck %s --check-prefix=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon-fx 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=k8-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=opteron-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=athlon64-sse3 2>&1 | FileCheck %s --check-prefixes=SLOW ; AMD chips with fast unaligned memory accesses -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=amdfam10 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=barcelona 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver1 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver2 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver3 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver4 2>&1 | FileCheck %s --check-prefix=FAST +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=amdfam10 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=barcelona 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver3 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver4 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512 ; Other chips with slow unaligned memory accesses -; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefix=SLOW +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefixes=SLOW ; Verify that the slow/fast unaligned memory attribute is set correctly for each CPU model. ; Slow chips use 4-byte stores. Fast chips with SSE or later use something other than 4-byte stores. @@ -61,36 +61,67 @@ ; Also verify that SSE4.2 or SSE4a imply fast unaligned accesses. -; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4.2 2>&1 | FileCheck %s --check-prefix=FAST -; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4a 2>&1 | FileCheck %s --check-prefix=FAST +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4.2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4a 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE -define void @store_zeros(ptr %a) { ; SLOW-NOT: not a recognized processor +; FAST-NOT: not a recognized processor +define void @store_zeros(ptr %a) { ; SLOW-LABEL: store_zeros: ; SLOW: # %bb.0: -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl -; SLOW-NEXT: movl +; SLOW-NEXT: movl {{[0-9]+}}(%esp), %eax +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NEXT: movl $0 +; SLOW-NOT: movl ; -; FAST-NOT: not a recognized processor -; FAST-LABEL: store_zeros: -; FAST: # %bb.0: -; FAST-NEXT: movl {{[0-9]+}}(%esp), %eax -; FAST-NOT: movl +; FAST-SSE-LABEL: store_zeros: +; FAST-SSE: # %bb.0: +; FAST-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax +; FAST-SSE-NEXT: xorps %xmm0, %xmm0 +; FAST-SSE-NEXT: movups %xmm0 +; FAST-SSE-NEXT: movups %xmm0 +; FAST-SSE-NEXT: movups %xmm0 +; FAST-SSE-NEXT: movups %xmm0 +; FAST-SSE-NOT: movups +; +; FAST-AVX128-LABEL: store_zeros: +; FAST-AVX128: # %bb.0: +; FAST-AVX128-NEXT: movl {{[0-9]+}}(%esp), %eax +; FAST-AVX128-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; FAST-AVX128-NEXT: vmovups %xmm0 +; FAST-AVX128-NEXT: vmovups %xmm0 +; FAST-AVX128-NEXT: vmovups %xmm0 +; FAST-AVX128-NEXT: vmovups %xmm0 +; FAST-AVX128-NOT: vmovups +; +; FAST-AVX256-LABEL: store_zeros: +; FAST-AVX256: # %bb.0: +; FAST-AVX256-NEXT: movl {{[0-9]+}}(%esp), %eax +; FAST-AVX256-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; FAST-AVX256-NEXT: vmovups %ymm0 +; FAST-AVX256-NEXT: vmovups %ymm0 +; FAST-AVX256-NOT: vmovups +; +; FAST-AVX512-LABEL: store_zeros: +; FAST-AVX512: # %bb.0: +; FAST-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax +; FAST-AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; FAST-AVX512-NEXT: vmovups %zmm0, (%eax) +; FAST-AVX512-NOT: vmovups call void @llvm.memset.p0.i64(ptr %a, i8 0, i64 64, i1 false) ret void } diff --git a/llvm/test/CodeGen/X86/swifterror.ll b/llvm/test/CodeGen/X86/swifterror.ll index 5814146a5461..8fff6405d0d8 100644 --- a/llvm/test/CodeGen/X86/swifterror.ll +++ b/llvm/test/CodeGen/X86/swifterror.ll @@ -243,8 +243,6 @@ define float @caller2(ptr %error_ref) { ; CHECK-i386-NEXT: .cfi_offset %edi, -8 ; CHECK-i386-NEXT: movl 32(%esp), %esi ; CHECK-i386-NEXT: leal 16(%esp), %edi -; CHECK-i386-NEXT: fld1 -; CHECK-i386-NEXT: fstps {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill ; CHECK-i386-NEXT: LBB2_1: ## %bb_loop ; CHECK-i386-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-i386-NEXT: movl $0, 16(%esp) @@ -255,7 +253,7 @@ define float @caller2(ptr %error_ref) { ; CHECK-i386-NEXT: jne LBB2_4 ; CHECK-i386-NEXT: ## %bb.2: ## %cont ; CHECK-i386-NEXT: ## in Loop: Header=BB2_1 Depth=1 -; CHECK-i386-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Reload +; CHECK-i386-NEXT: fld1 ; CHECK-i386-NEXT: fxch %st(1) ; CHECK-i386-NEXT: fucompp ; CHECK-i386-NEXT: fnstsw %ax @@ -270,7 +268,7 @@ define float @caller2(ptr %error_ref) { ; CHECK-i386-NEXT: fstp %st(0) ; CHECK-i386-NEXT: movl %ecx, (%esp) ; CHECK-i386-NEXT: calll _free -; CHECK-i386-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Reload +; CHECK-i386-NEXT: fld1 ; CHECK-i386-NEXT: addl $20, %esp ; CHECK-i386-NEXT: popl %esi ; CHECK-i386-NEXT: popl %edi @@ -470,8 +468,6 @@ define float @foo_loop(ptr swifterror %error_ptr_ref, i32 %cc, float %cc2) { ; CHECK-i386-NEXT: fstps {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill ; CHECK-i386-NEXT: movl 36(%esp), %esi ; CHECK-i386-NEXT: movl 32(%esp), %edi -; CHECK-i386-NEXT: fld1 -; CHECK-i386-NEXT: fstps {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill ; CHECK-i386-NEXT: LBB4_1: ## %bb_loop ; CHECK-i386-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-i386-NEXT: testl %esi, %esi @@ -486,7 +482,7 @@ define float @foo_loop(ptr swifterror %error_ptr_ref, i32 %cc, float %cc2) { ; CHECK-i386-NEXT: LBB4_3: ## %bb_cont ; CHECK-i386-NEXT: ## in Loop: Header=BB4_1 Depth=1 ; CHECK-i386-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Reload -; CHECK-i386-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Reload +; CHECK-i386-NEXT: fld1 ; CHECK-i386-NEXT: fxch %st(1) ; CHECK-i386-NEXT: fucompp ; CHECK-i386-NEXT: fnstsw %ax diff --git a/llvm/test/CodeGen/X86/unused_stackslots.ll b/llvm/test/CodeGen/X86/unused_stackslots.ll index 5aeaca7e84c3..d909dd478cae 100644 --- a/llvm/test/CodeGen/X86/unused_stackslots.ll +++ b/llvm/test/CodeGen/X86/unused_stackslots.ll @@ -42,9 +42,9 @@ for.body: ; preds = %for.inc73, %entry %shl1 = shl nsw i32 %rem, 3 %tmp9 = sext i32 %shl1 to i64 %tmp10 = sext i32 %shl to i64 - %tmp11 = or i32 %shl1, 4 + %tmp11 = or disjoint i32 %shl1, 4 %tmp12 = sext i32 %tmp11 to i64 - %tmp13 = or i32 %shl, 4 + %tmp13 = or disjoint i32 %shl, 4 %tmp14 = sext i32 %tmp13 to i64 br label %for.body4 @@ -59,14 +59,14 @@ for.body4: ; preds = %for.inc48, %for.bod %tmp18 = sub nuw nsw i64 %indvars.iv148, %tmp10 %tmp19 = sext i32 %add5 to i64 %tmp20 = add nsw i64 %tmp19, 1 - %tmp21 = or i64 %indvars.iv148, 1 - %tmp22 = or i64 %tmp18, 1 + %tmp21 = or disjoint i64 %indvars.iv148, 1 + %tmp22 = or disjoint i64 %tmp18, 1 %tmp23 = add nsw i64 %tmp19, 2 - %tmp24 = or i64 %indvars.iv148, 2 - %tmp25 = or i64 %tmp18, 2 + %tmp24 = or disjoint i64 %indvars.iv148, 2 + %tmp25 = or disjoint i64 %tmp18, 2 %tmp26 = add nsw i64 %tmp19, 3 - %tmp27 = or i64 %indvars.iv148, 3 - %tmp28 = or i64 %tmp18, 3 + %tmp27 = or disjoint i64 %indvars.iv148, 3 + %tmp28 = or disjoint i64 %tmp18, 3 br label %for.body9 for.body9: ; preds = %for.inc45.for.body9_crit_edge, %for.body4 diff --git a/llvm/test/CodeGen/X86/vec_zero_cse.ll b/llvm/test/CodeGen/X86/vec_zero_cse.ll index 99185277ba74..21da191d8d69 100644 --- a/llvm/test/CodeGen/X86/vec_zero_cse.ll +++ b/llvm/test/CodeGen/X86/vec_zero_cse.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -relocation-model=static -mtriple=i686-unknown -mattr=+mmx,+sse3 | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -relocation-model=static -mtriple=i686-unknown -mattr=+mmx,+sse3 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -relocation-model=static -mtriple=x86_64-unknown -mattr=+mmx,+sse3 | FileCheck %s --check-prefix=X64 ; 64-bit stores here do not use MMX. @@ -11,13 +11,13 @@ @S2 = external dso_local global <4 x i32> define void @test1() { -; X32-LABEL: test1: -; X32: # %bb.0: -; X32-NEXT: movl $0, M1+4 -; X32-NEXT: movl $0, M1 -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: movlps %xmm0, M2 -; X32-NEXT: retl +; X86-LABEL: test1: +; X86: # %bb.0: +; X86-NEXT: movl $0, M1+4 +; X86-NEXT: movl $0, M1 +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movlps %xmm0, M2 +; X86-NEXT: retl ; ; X64-LABEL: test1: ; X64: # %bb.0: @@ -30,13 +30,13 @@ define void @test1() { } define void @test2() { -; X32-LABEL: test2: -; X32: # %bb.0: -; X32-NEXT: movl $-1, M1+4 -; X32-NEXT: movl $-1, M1 -; X32-NEXT: pcmpeqd %xmm0, %xmm0 -; X32-NEXT: movq %xmm0, M2 -; X32-NEXT: retl +; X86-LABEL: test2: +; X86: # %bb.0: +; X86-NEXT: movl $-1, M1+4 +; X86-NEXT: movl $-1, M1 +; X86-NEXT: pcmpeqd %xmm0, %xmm0 +; X86-NEXT: movq %xmm0, M2 +; X86-NEXT: retl ; ; X64-LABEL: test2: ; X64: # %bb.0: @@ -49,12 +49,12 @@ define void @test2() { } define void @test3() { -; X32-LABEL: test3: -; X32: # %bb.0: -; X32-NEXT: xorps %xmm0, %xmm0 -; X32-NEXT: movaps %xmm0, S1 -; X32-NEXT: movaps %xmm0, S2 -; X32-NEXT: retl +; X86-LABEL: test3: +; X86: # %bb.0: +; X86-NEXT: xorps %xmm0, %xmm0 +; X86-NEXT: movaps %xmm0, S1 +; X86-NEXT: movaps %xmm0, S2 +; X86-NEXT: retl ; ; X64-LABEL: test3: ; X64: # %bb.0: @@ -68,12 +68,12 @@ define void @test3() { } define void @test4() { -; X32-LABEL: test4: -; X32: # %bb.0: -; X32-NEXT: pcmpeqd %xmm0, %xmm0 -; X32-NEXT: movdqa %xmm0, S1 -; X32-NEXT: movdqa %xmm0, S2 -; X32-NEXT: retl +; X86-LABEL: test4: +; X86: # %bb.0: +; X86-NEXT: pcmpeqd %xmm0, %xmm0 +; X86-NEXT: movdqa %xmm0, S1 +; X86-NEXT: movdqa %xmm0, S2 +; X86-NEXT: retl ; ; X64-LABEL: test4: ; X64: # %bb.0: diff --git a/llvm/test/CodeGen/X86/zero-remat.ll b/llvm/test/CodeGen/X86/zero-remat.ll index 04d7a2c2c558..60bb2c420cda 100644 --- a/llvm/test/CodeGen/X86/zero-remat.ll +++ b/llvm/test/CodeGen/X86/zero-remat.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=CHECK-64 ; RUN: llc < %s -mtriple=x86_64-- -o /dev/null -stats -info-output-file - | grep asm-printer | grep 12 @@ -7,35 +8,45 @@ declare void @bar(double %x) declare void @barf(float %x) define double @foo() nounwind { - +; CHECK-64-LABEL: foo: +; CHECK-64: # %bb.0: +; CHECK-64-NEXT: pushq %rax +; CHECK-64-NEXT: xorps %xmm0, %xmm0 +; CHECK-64-NEXT: callq bar@PLT +; CHECK-64-NEXT: xorps %xmm0, %xmm0 +; CHECK-64-NEXT: popq %rax +; CHECK-64-NEXT: retq +; +; CHECK-32-LABEL: foo: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: pushl $0 +; CHECK-32-NEXT: pushl $0 +; CHECK-32-NEXT: calll bar@PLT +; CHECK-32-NEXT: addl $8, %esp +; CHECK-32-NEXT: fldz +; CHECK-32-NEXT: retl call void @bar(double 0.0) ret double 0.0 - -;CHECK-32-LABEL: foo: -;CHECK-32: call -;CHECK-32: fldz -;CHECK-32: ret - -;CHECK-64-LABEL: foo: -;CHECK-64: xorps -;CHECK-64: call -;CHECK-64: xorps -;CHECK-64: ret } define float @foof() nounwind { +; CHECK-64-LABEL: foof: +; CHECK-64: # %bb.0: +; CHECK-64-NEXT: pushq %rax +; CHECK-64-NEXT: xorps %xmm0, %xmm0 +; CHECK-64-NEXT: callq barf@PLT +; CHECK-64-NEXT: xorps %xmm0, %xmm0 +; CHECK-64-NEXT: popq %rax +; CHECK-64-NEXT: retq +; +; CHECK-32-LABEL: foof: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: pushl $0 +; CHECK-32-NEXT: calll barf@PLT +; CHECK-32-NEXT: addl $4, %esp +; CHECK-32-NEXT: fldz +; CHECK-32-NEXT: retl call void @barf(float 0.0) ret float 0.0 - -;CHECK-32-LABEL: foof: -;CHECK-32: call -;CHECK-32: fldz -;CHECK-32: ret - -;CHECK-64-LABEL: foof: -;CHECK-64: xorps -;CHECK-64: call -;CHECK-64: xorps -;CHECK-64: ret } diff --git a/llvm/test/CodeGen/XCore/atomic.ll b/llvm/test/CodeGen/XCore/atomic.ll index 02cef0722fc0..8c11e43f52ac 100644 --- a/llvm/test/CodeGen/XCore/atomic.ll +++ b/llvm/test/CodeGen/XCore/atomic.ll @@ -21,71 +21,23 @@ define void @atomicloadstore() nounwind { entry: ; CHECK-LABEL: atomicloadstore -; CHECK: ldw r[[R0:[0-9]+]], dp[pool] -; CHECK-NEXT: ldaw r[[R1:[0-9]+]], dp[pool] -; CHECK-NEXT: #MEMBARRIER -; CHECK-NEXT: ldc r[[R2:[0-9]+]], 0 - %0 = load atomic i32, ptr @pool acquire, align 4 +; CHECK: __atomic_load_4 + %0 = load atomic i32, ptr @pool seq_cst, align 4 -; CHECK-NEXT: ld16s r3, r[[R1]][r[[R2]]] -; CHECK-NEXT: #MEMBARRIER - %1 = load atomic i16, ptr @pool acquire, align 2 +; CHECK: __atomic_load_2 + %1 = load atomic i16, ptr @pool seq_cst, align 2 -; CHECK-NEXT: ld8u r11, r[[R1]][r[[R2]]] -; CHECK-NEXT: #MEMBARRIER - %2 = load atomic i8, ptr @pool acquire, align 1 +; CHECK: __atomic_load_1 + %2 = load atomic i8, ptr @pool seq_cst, align 1 -; CHECK-NEXT: ldw r4, dp[pool] -; CHECK-NEXT: #MEMBARRIER - %3 = load atomic i32, ptr @pool seq_cst, align 4 +; CHECK: __atomic_store_4 + store atomic i32 %0, ptr @pool seq_cst, align 4 -; CHECK-NEXT: ld16s r5, r[[R1]][r[[R2]]] -; CHECK-NEXT: #MEMBARRIER - %4 = load atomic i16, ptr @pool seq_cst, align 2 +; CHECK: __atomic_store_2 + store atomic i16 %1, ptr @pool seq_cst, align 2 -; CHECK-NEXT: ld8u r6, r[[R1]][r[[R2]]] -; CHECK-NEXT: #MEMBARRIER - %5 = load atomic i8, ptr @pool seq_cst, align 1 - -; CHECK-NEXT: #MEMBARRIER -; CHECK-NEXT: stw r[[R0]], dp[pool] - store atomic i32 %0, ptr @pool release, align 4 - -; CHECK-NEXT: #MEMBARRIER -; CHECK-NEXT: st16 r3, r[[R1]][r[[R2]]] - store atomic i16 %1, ptr @pool release, align 2 - -; CHECK-NEXT: #MEMBARRIER -; CHECK-NEXT: st8 r11, r[[R1]][r[[R2]]] - store atomic i8 %2, ptr @pool release, align 1 - -; CHECK-NEXT: #MEMBARRIER -; CHECK-NEXT: stw r4, dp[pool] -; CHECK-NEXT: #MEMBARRIER - store atomic i32 %3, ptr @pool seq_cst, align 4 - -; CHECK-NEXT: #MEMBARRIER -; CHECK-NEXT: st16 r5, r[[R1]][r[[R2]]] -; CHECK-NEXT: #MEMBARRIER - store atomic i16 %4, ptr @pool seq_cst, align 2 - -; CHECK-NEXT: #MEMBARRIER -; CHECK-NEXT: st8 r6, r[[R1]][r[[R2]]] -; CHECK-NEXT: #MEMBARRIER - store atomic i8 %5, ptr @pool seq_cst, align 1 - -; CHECK-NEXT: ldw r[[R0]], dp[pool] -; CHECK-NEXT: stw r[[R0]], dp[pool] -; CHECK-NEXT: ld16s r[[R0]], r[[R1]][r[[R2]]] -; CHECK-NEXT: st16 r[[R0]], r[[R1]][r[[R2]]] -; CHECK-NEXT: ld8u r[[R0]], r[[R1]][r[[R2]]] -; CHECK-NEXT: st8 r[[R0]], r[[R1]][r[[R2]]] - %6 = load atomic i32, ptr @pool monotonic, align 4 - store atomic i32 %6, ptr @pool monotonic, align 4 - %7 = load atomic i16, ptr @pool monotonic, align 2 - store atomic i16 %7, ptr @pool monotonic, align 2 - %8 = load atomic i8, ptr @pool monotonic, align 1 - store atomic i8 %8, ptr @pool monotonic, align 1 +; CHECK: __atomic_store_1 + store atomic i8 %2, ptr @pool seq_cst, align 1 ret void } diff --git a/llvm/test/DebugInfo/Inputs/dwarfdump-test3-decl.h b/llvm/test/DebugInfo/Inputs/dwarfdump-test3-decl.h deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/llvm/test/DebugInfo/Inputs/dwarfdump-test3.cc b/llvm/test/DebugInfo/Inputs/dwarfdump-test3.cc deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/llvm/test/DebugInfo/X86/debug-names-types.ll b/llvm/test/DebugInfo/X86/debug-names-types.ll index fc23e604b386..d32691305d1c 100644 --- a/llvm/test/DebugInfo/X86/debug-names-types.ll +++ b/llvm/test/DebugInfo/X86/debug-names-types.ll @@ -1,15 +1,10 @@ ; UNSUPPORTED: system-windows -; This checks that .debug_names can be generated with monolithic -fdebug-type-sections, and does not generate when split-dwarf is enabled. +; This checks that .debug_names can be generated with monolithic, and split-dwarf, when -fdebug-type-sections is enabled. ; Generated with: clang++ main.cpp -g2 -gdwarf-5 -gpubnames -fdebug-types-section ; RUN: llc -mtriple=x86_64 -generate-type-units -dwarf-version=5 -filetype=obj %s -o %t ; RUN: llvm-dwarfdump -debug-info -debug-names %t | FileCheck %s -; RUN: llc -mtriple=x86_64 -generate-type-units -dwarf-version=5 -filetype=obj -split-dwarf-file=%t.mainTypes.dwo --split-dwarf-output=%t.mainTypes.dwo %s -o %t -; RUN: llvm-readelf --sections %t | FileCheck %s --check-prefixes=CHECK-SPLIT - -; CHECK-SPLIT-NOT: .debug_names - ; CHECK: .debug_info contents: ; CHECK: DW_TAG_type_unit ; CHECK-NEXT: DW_AT_language (DW_LANG_C_plus_plus_14) @@ -117,6 +112,99 @@ ; CHECK-NEXT: ] ; CHECK-NEXT: } +; RUN: llc -mtriple=x86_64 -generate-type-units -dwarf-version=5 -filetype=obj -split-dwarf-file=%t.mainTypes.dwo --split-dwarf-output=%t.mainTypes.dwo %s -o %t +; RUN: llvm-dwarfdump -debug-names %t | FileCheck %s --check-prefixes=CHECK-SPLIT + +; CHECK-SPLIT: .debug_names contents +; CHECK-SPLIT: Foreign TU count: 1 +; CHECK-SPLIT-NEXT: Bucket count: 4 +; CHECK-SPLIT-NEXT: Name count: 4 +; CHECK-SPLIT-NEXT: Abbreviations table size: 0x28 +; CHECK-SPLIT-NEXT: Augmentation: 'LLVM0700' +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: Compilation Unit offsets [ +; CHECK-SPLIT-NEXT: CU[0]: 0x00000000 +; CHECK-SPLIT-NEXT: ] +; CHECK-SPLIT-NEXT: Foreign Type Unit signatures [ +; CHECK-SPLIT-NEXT: ForeignTU[0]: 0x675d23e4f33235f2 +; CHECK-SPLIT-NEXT: ] +; CHECK-SPLIT-NEXT: Abbreviations [ +; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV:0x[0-9a-f]*]] { +; CHECK-SPLIT-NEXT: Tag: DW_TAG_structure_type +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4 +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV1:0x[0-9a-f]*]] { +; CHECK-SPLIT-NEXT: Tag: DW_TAG_structure_type +; CHECK-SPLIT-NEXT: DW_IDX_type_unit: DW_FORM_data1 +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4 +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV2:0x[0-9a-f]*]] { +; CHECK-SPLIT-NEXT: Tag: DW_TAG_base_type +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4 +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV3:0x[0-9a-f]*]] { +; CHECK-SPLIT-NEXT: Tag: DW_TAG_subprogram +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4 +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV4:0x[0-9a-f]*]] { +; CHECK-SPLIT-NEXT: Tag: DW_TAG_base_type +; CHECK-SPLIT-NEXT: DW_IDX_type_unit: DW_FORM_data1 +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4 +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: ] +; CHECK-SPLIT-NEXT: Bucket 0 [ +; CHECK-SPLIT-NEXT: Name 1 { +; CHECK-SPLIT-NEXT: Hash: 0xB888030 +; CHECK-SPLIT-NEXT: String: {{.+}} "int" +; CHECK-SPLIT-NEXT: Entry @ {{.+}} { +; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV2]] +; CHECK-SPLIT-NEXT: Tag: DW_TAG_base_type +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x00000035 +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: ] +; CHECK-SPLIT-NEXT: Bucket 1 [ +; CHECK-SPLIT-NEXT: Name 2 { +; CHECK-SPLIT-NEXT: Hash: 0xB887389 +; CHECK-SPLIT-NEXT: String: {{.+}} "Foo" +; CHECK-SPLIT-NEXT: Entry @ {{.+}} { +; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV1]] +; CHECK-SPLIT-NEXT: Tag: DW_TAG_structure_type +; CHECK-SPLIT-NEXT: DW_IDX_type_unit: 0x00 +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x0000001f +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: Entry @ 0xae { +; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV]] +; CHECK-SPLIT-NEXT: Tag: DW_TAG_structure_type +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x00000039 +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: ] +; CHECK-SPLIT-NEXT: Bucket 2 [ +; CHECK-SPLIT-NEXT: Name 3 { +; CHECK-SPLIT-NEXT: Hash: 0x7C9A7F6A +; CHECK-SPLIT-NEXT: String: {{.+}} "main" +; CHECK-SPLIT-NEXT: Entry @ {{.+}} { +; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV3]] +; CHECK-SPLIT-NEXT: Tag: DW_TAG_subprogram +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x0000001a +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: ] +; CHECK-SPLIT-NEXT: Bucket 3 [ +; CHECK-SPLIT-NEXT: Name 4 { +; CHECK-SPLIT-NEXT: Hash: 0x7C952063 +; CHECK-SPLIT-NEXT: String: {{.+}} "char" +; CHECK-SPLIT-NEXT: Entry @ {{.+}} { +; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV4]] +; CHECK-SPLIT-NEXT: Tag: DW_TAG_base_type +; CHECK-SPLIT-NEXT: DW_IDX_type_unit: 0x00 +; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x00000034 +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: } +; CHECK-SPLIT-NEXT: ] +; CHECK-SPLIT-NEXT: } + ; ModuleID = 'main.cpp' source_filename = "main.cpp" diff --git a/llvm/test/DebugInfo/XCOFF/empty.ll b/llvm/test/DebugInfo/XCOFF/empty.ll index be7933485e31..c1393907169f 100644 --- a/llvm/test/DebugInfo/XCOFF/empty.ll +++ b/llvm/test/DebugInfo/XCOFF/empty.ll @@ -36,7 +36,8 @@ entry: !12 = !DILocation(line: 3, column: 3, scope: !8) ; ASM32: .file "1.c" -; ASM32-NEXT: .csect [PR],5 +; ASM32-NEXT: .csect ..text..[PR],5 +; ASM32-NEXT: .rename ..text..[PR],"" ; ASM32-NEXT: .globl main[DS] # -- Begin function main ; ASM32-NEXT: .globl .main ; ASM32-NEXT: .align 2 @@ -44,7 +45,7 @@ entry: ; ASM32-NEXT: .vbyte 4, .main # @main ; ASM32-NEXT: .vbyte 4, TOC[TC0] ; ASM32-NEXT: .vbyte 4, 0 -; ASM32-NEXT: .csect [PR],5 +; ASM32-NEXT: .csect ..text..[PR],5 ; ASM32-NEXT: .main: ; ASM32-NEXT: L..func_begin0: ; ASM32-NEXT: # %bb.0: # %entry @@ -237,7 +238,8 @@ entry: ; ASM32-NEXT: L..debug_line_end0: ; ASM64: .file "1.c" -; ASM64-NEXT: .csect [PR],5 +; ASM64-NEXT: .csect ..text..[PR],5 +; ASM64-NEXT: .rename ..text..[PR],"" ; ASM64-NEXT: .globl main[DS] # -- Begin function main ; ASM64-NEXT: .globl .main ; ASM64-NEXT: .align 2 @@ -245,7 +247,7 @@ entry: ; ASM64-NEXT: .vbyte 8, .main # @main ; ASM64-NEXT: .vbyte 8, TOC[TC0] ; ASM64-NEXT: .vbyte 8, 0 -; ASM64-NEXT: .csect [PR],5 +; ASM64-NEXT: .csect ..text..[PR],5 ; ASM64-NEXT: .main: ; ASM64-NEXT: L..func_begin0: ; ASM64-NEXT: # %bb.0: # %entry diff --git a/llvm/test/DebugInfo/XCOFF/explicit-section.ll b/llvm/test/DebugInfo/XCOFF/explicit-section.ll index 88ca64e7eda1..ed2ffb709168 100644 --- a/llvm/test/DebugInfo/XCOFF/explicit-section.ll +++ b/llvm/test/DebugInfo/XCOFF/explicit-section.ll @@ -43,7 +43,8 @@ entry: !16 = !DILocation(line: 3, column: 3, scope: !14) ; CHECK: .file "2.c" -; CHECK-NEXT: .csect [PR],5 +; CHECK-NEXT: .csect ..text..[PR],5 +; CHECK-NEXT: .rename ..text..[PR],"" ; CHECK-NEXT: .globl bar[DS] # -- Begin function bar ; CHECK-NEXT: .globl .bar ; CHECK-NEXT: .align 2 @@ -51,7 +52,7 @@ entry: ; CHECK-NEXT: .vbyte 4, .bar # @bar ; CHECK-NEXT: .vbyte 4, TOC[TC0] ; CHECK-NEXT: .vbyte 4, 0 -; CHECK-NEXT: .csect [PR],5 +; CHECK-NEXT: .csect ..text..[PR],5 ; CHECK-NEXT: .bar: ; CHECK-NEXT: L..func_begin0: ; CHECK-NEXT: # %bb.0: # %entry diff --git a/llvm/test/DebugInfo/XCOFF/function-sections.ll b/llvm/test/DebugInfo/XCOFF/function-sections.ll index 9137c9b2585f..c899089102c6 100644 --- a/llvm/test/DebugInfo/XCOFF/function-sections.ll +++ b/llvm/test/DebugInfo/XCOFF/function-sections.ll @@ -38,7 +38,8 @@ entry: !14 = !DILocation(line: 8, column: 3, scope: !13) ; CHECK: .file "1.c" -; CHECK-NEXT: .csect [PR],5 +; CHECK-NEXT: .csect ..text..[PR],5 +; CHECK-NEXT: .rename ..text..[PR],"" ; CHECK-NEXT: .csect .foo[PR],5 ; CHECK-NEXT: .globl foo[DS] # -- Begin function foo ; CHECK-NEXT: .globl .foo[PR] diff --git a/llvm/test/ExecutionEngine/JITLink/AArch32/ELF_thumbv7_printf.s b/llvm/test/ExecutionEngine/JITLink/AArch32/ELF_thumbv7_printf.s index 11a77c95cfa8..457ce6a4cc53 100644 --- a/llvm/test/ExecutionEngine/JITLink/AArch32/ELF_thumbv7_printf.s +++ b/llvm/test/ExecutionEngine/JITLink/AArch32/ELF_thumbv7_printf.s @@ -3,7 +3,9 @@ // Check that main is a thumb symbol (with LSB set) and printf is arm (with LSB clear) // -// CHECK-LABEL: Symbol table: +// CHECK-LABEL: JITDylib "main" +// CHECK-NEXT: Link order: [ ("main", MatchAllSymbols), ("Process", MatchExportedSymbolsOnly) ] +// CHECK-NEXT: Symbol table: // CHECK-NEXT: "main": 0x{{[0-9a-f]+[13579bdf]}} [Callable] Ready // CHECK-NEXT: "printf": 0x76bbe880 [Data] Ready diff --git a/llvm/test/ExecutionEngine/JITLink/Generic/Inputs/main-ret-0.ll b/llvm/test/ExecutionEngine/JITLink/Generic/Inputs/main-ret-0.ll new file mode 100644 index 000000000000..3d03142d6ca2 --- /dev/null +++ b/llvm/test/ExecutionEngine/JITLink/Generic/Inputs/main-ret-0.ll @@ -0,0 +1,4 @@ +define i32 @main(i32 %argc, i8** %argv) { +entry: + ret i32 0 +} diff --git a/llvm/test/ExecutionEngine/JITLink/Generic/error-object-passed-as-archive.test b/llvm/test/ExecutionEngine/JITLink/Generic/error-object-passed-as-archive.test new file mode 100644 index 000000000000..04e67adee744 --- /dev/null +++ b/llvm/test/ExecutionEngine/JITLink/Generic/error-object-passed-as-archive.test @@ -0,0 +1,6 @@ +# RUN: llc -filetype=obj -o %t.o %S/Inputs/main-ret-0.ll +# RUN: cp %t.o %t.a +# RUN: not llvm-jitlink -noexec %t.o %t.a +# +# Try to load an object file as if it were an archive. Should result in an +# error, rather than a crash. diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_smem.s b/llvm/test/MC/AMDGPU/gfx12_asm_smem.s new file mode 100644 index 000000000000..ed7ad5bb0c4e --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_smem.s @@ -0,0 +1,35 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s + +//===----------------------------------------------------------------------===// +// ENC_SMEM. +//===----------------------------------------------------------------------===// + +s_prefetch_inst s[12:13], 16, s4, 2 +// GFX12: s_prefetch_inst s[12:13], 0x10, s4, 2 ; encoding: [0x86,0x80,0x04,0xf4,0x10,0x00,0x00,0x08] + +s_prefetch_inst s[14:15], 0, m0, 7 +// GFX12: s_prefetch_inst s[14:15], 0x0, m0, 7 ; encoding: [0xc7,0x81,0x04,0xf4,0x00,0x00,0x00,0xfa] + +s_prefetch_inst s[14:15], 0x7fffff, m0, 7 +// GFX12: s_prefetch_inst s[14:15], 0x7fffff, m0, 7 ; encoding: [0xc7,0x81,0x04,0xf4,0xff,0xff,0x7f,0xfa] + +s_prefetch_inst s[14:15], -1, m0, 7 +// GFX12: s_prefetch_inst s[14:15], -0x1, m0, 7 ; encoding: [0xc7,0x81,0x04,0xf4,0xff,0xff,0xff,0xfa] + +s_prefetch_inst s[14:15], 100, m0, 31 +// GFX12: s_prefetch_inst s[14:15], 0x64, m0, 31 ; encoding: [0xc7,0x87,0x04,0xf4,0x64,0x00,0x00,0xfa] + +s_prefetch_inst_pc_rel 100, s10, 7 +// GFX12: s_prefetch_inst_pc_rel 0x64, s10, 7 ; encoding: [0xc0,0xa1,0x04,0xf4,0x64,0x00,0x00,0x14] + +s_prefetch_data s[18:19], 100, s10, 7 +// GFX12: s_prefetch_data s[18:19], 0x64, s10, 7 ; encoding: [0xc9,0xc1,0x04,0xf4,0x64,0x00,0x00,0x14] + +s_prefetch_data_pc_rel 100, s10, 7 +// GFX12: s_prefetch_data_pc_rel 0x64, s10, 7 ; encoding: [0xc0,0x01,0x05,0xf4,0x64,0x00,0x00,0x14] + +s_buffer_prefetch_data s[20:23], 100, s10, 7 +// GFX12: s_buffer_prefetch_data s[20:23], 0x64, s10, 7 ; encoding: [0xca,0xe1,0x04,0xf4,0x64,0x00,0x00,0x14] + +s_buffer_prefetch_data s[20:23], 100, null, 7 +// GFX12: s_buffer_prefetch_data s[20:23], 0x64, null, 7 ; encoding: [0xca,0xe1,0x04,0xf4,0x64,0x00,0x00,0xf8] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s new file mode 100644 index 000000000000..494b8399a26f --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s @@ -0,0 +1,4216 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s + +s_cvt_f32_i32 s5, s1 +// GFX12: encoding: [0x01,0x64,0x85,0xbe] + +s_cvt_f32_i32 s105, s1 +// GFX12: encoding: [0x01,0x64,0xe9,0xbe] + +s_cvt_f32_i32 s5, s105 +// GFX12: encoding: [0x69,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, s103 +// GFX12: encoding: [0x67,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, ttmp11 +// GFX12: encoding: [0x77,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, m0 +// GFX12: encoding: [0x7d,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, exec_lo +// GFX12: encoding: [0x7e,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, exec_hi +// GFX12: encoding: [0x7f,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, 0 +// GFX12: encoding: [0x80,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, -1 +// GFX12: encoding: [0xc1,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, 0.5 +// GFX12: encoding: [0xf0,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, -4.0 +// GFX12: encoding: [0xf7,0x64,0x85,0xbe] + +s_cvt_f32_i32 s5, 0xaf123456 +// GFX12: encoding: [0xff,0x64,0x85,0xbe,0x56,0x34,0x12,0xaf] + +s_cvt_f32_i32 s5, 0x3f717273 +// GFX12: encoding: [0xff,0x64,0x85,0xbe,0x73,0x72,0x71,0x3f] + +s_cvt_f32_u32 s5, s1 +// GFX12: encoding: [0x01,0x65,0x85,0xbe] + +s_cvt_f32_u32 s105, s1 +// GFX12: encoding: [0x01,0x65,0xe9,0xbe] + +s_cvt_f32_u32 s5, s105 +// GFX12: encoding: [0x69,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, s103 +// GFX12: encoding: [0x67,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, ttmp11 +// GFX12: encoding: [0x77,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, m0 +// GFX12: encoding: [0x7d,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, exec_lo +// GFX12: encoding: [0x7e,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, exec_hi +// GFX12: encoding: [0x7f,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, 0 +// GFX12: encoding: [0x80,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, -1 +// GFX12: encoding: [0xc1,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, 0.5 +// GFX12: encoding: [0xf0,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, -4.0 +// GFX12: encoding: [0xf7,0x65,0x85,0xbe] + +s_cvt_f32_u32 s5, 0xaf123456 +// GFX12: encoding: [0xff,0x65,0x85,0xbe,0x56,0x34,0x12,0xaf] + +s_cvt_f32_u32 s5, 0x3f717273 +// GFX12: encoding: [0xff,0x65,0x85,0xbe,0x73,0x72,0x71,0x3f] + +s_cvt_u32_f32 s5, s1 +// GFX12: encoding: [0x01,0x67,0x85,0xbe] + +s_cvt_u32_f32 s105, s1 +// GFX12: encoding: [0x01,0x67,0xe9,0xbe] + +s_cvt_u32_f32 s5, s105 +// GFX12: encoding: [0x69,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, s103 +// GFX12: encoding: [0x67,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, ttmp11 +// GFX12: encoding: [0x77,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, m0 +// GFX12: encoding: [0x7d,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, exec_lo +// GFX12: encoding: [0x7e,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, exec_hi +// GFX12: encoding: [0x7f,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, 0 +// GFX12: encoding: [0x80,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, -1 +// GFX12: encoding: [0xc1,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, 0.5 +// GFX12: encoding: [0xf0,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, -4.0 +// GFX12: encoding: [0xf7,0x67,0x85,0xbe] + +s_cvt_u32_f32 s5, 0xaf123456 +// GFX12: encoding: [0xff,0x67,0x85,0xbe,0x56,0x34,0x12,0xaf] + +s_cvt_u32_f32 s5, 0x3f717273 +// GFX12: encoding: [0xff,0x67,0x85,0xbe,0x73,0x72,0x71,0x3f] + +s_cvt_i32_f32 s5, s1 +// GFX12: encoding: [0x01,0x66,0x85,0xbe] + +s_cvt_i32_f32 s105, s1 +// GFX12: encoding: [0x01,0x66,0xe9,0xbe] + +s_cvt_i32_f32 s5, s105 +// GFX12: encoding: [0x69,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, s103 +// GFX12: encoding: [0x67,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, ttmp11 +// GFX12: encoding: [0x77,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, m0 +// GFX12: encoding: [0x7d,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, exec_lo +// GFX12: encoding: [0x7e,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, exec_hi +// GFX12: encoding: [0x7f,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, 0 +// GFX12: encoding: [0x80,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, -1 +// GFX12: encoding: [0xc1,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, 0.5 +// GFX12: encoding: [0xf0,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, -4.0 +// GFX12: encoding: [0xf7,0x66,0x85,0xbe] + +s_cvt_i32_f32 s5, 0xaf123456 +// GFX12: encoding: [0xff,0x66,0x85,0xbe,0x56,0x34,0x12,0xaf] + +s_cvt_i32_f32 s5, 0x3f717273 +// GFX12: encoding: [0xff,0x66,0x85,0xbe,0x73,0x72,0x71,0x3f] + +s_cvt_f16_f32 s5, s1 +// GFX12: encoding: [0x01,0x68,0x85,0xbe] + +s_cvt_f16_f32 s105, s1 +// GFX12: encoding: [0x01,0x68,0xe9,0xbe] + +s_cvt_f16_f32 s5, s105 +// GFX12: encoding: [0x69,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, s103 +// GFX12: encoding: [0x67,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, ttmp11 +// GFX12: encoding: [0x77,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, m0 +// GFX12: encoding: [0x7d,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, exec_lo +// GFX12: encoding: [0x7e,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, exec_hi +// GFX12: encoding: [0x7f,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, 0 +// GFX12: encoding: [0x80,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, -1 +// GFX12: encoding: [0xc1,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, 0.5 +// GFX12: encoding: [0xf0,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, -4.0 +// GFX12: encoding: [0xf7,0x68,0x85,0xbe] + +s_cvt_f16_f32 s5, 0xaf123456 +// GFX12: encoding: [0xff,0x68,0x85,0xbe,0x56,0x34,0x12,0xaf] + +s_cvt_f16_f32 s5, 0x3f717273 +// GFX12: encoding: [0xff,0x68,0x85,0xbe,0x73,0x72,0x71,0x3f] + +s_cvt_f32_f16 s5, s1 +// GFX12: encoding: [0x01,0x69,0x85,0xbe] + +s_cvt_f32_f16 s105, s1 +// GFX12: encoding: [0x01,0x69,0xe9,0xbe] + +s_cvt_f32_f16 s5, s105 +// GFX12: encoding: [0x69,0x69,0x85,0xbe] + +s_cvt_f32_f16 s5, s103 +// GFX12: encoding: [0x67,0x69,0x85,0xbe] + +s_cvt_f32_f16 s5, vcc_lo +// GFX12: encoding: [0x6a,0x69,0x85,0xbe] + +s_cvt_f32_f16 s5, vcc_hi +// GFX12: encoding: [0x6b,0x69,0x85,0xbe] + +s_cvt_f32_f16 s5, ttmp11 +// GFX12: encoding: [0x77,0x69,0x85,0xbe] + +s_cvt_f32_f16 s5, m0 +// GFX12: encoding: [0x7d,0x69,0x85,0xbe] + +s_cvt_f32_f16 s5, exec_lo +// GFX12: encoding: [0x7e,0x69,0x85,0xbe] + +s_cvt_f32_f16 s5, exec_hi +// GFX12: encoding: [0x7f,0x69,0x85,0xbe] + +s_cvt_f32_f16 s5, 0 +// GFX12: encoding: [0x80,0x69,0x85,0xbe] + +s_cvt_f32_f16 s5, -1 +// GFX12: encoding: [0xc1,0x69,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, s1 +// GFX12: encoding: [0x01,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s105, s1 +// GFX12: encoding: [0x01,0x6a,0xe9,0xbe] + +s_cvt_hi_f32_f16 s5, s105 +// GFX12: encoding: [0x69,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, s103 +// GFX12: encoding: [0x67,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, vcc_lo +// GFX12: encoding: [0x6a,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, vcc_hi +// GFX12: encoding: [0x6b,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, ttmp11 +// GFX12: encoding: [0x77,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, m0 +// GFX12: encoding: [0x7d,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, exec_lo +// GFX12: encoding: [0x7e,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, exec_hi +// GFX12: encoding: [0x7f,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, 0 +// GFX12: encoding: [0x80,0x6a,0x85,0xbe] + +s_cvt_hi_f32_f16 s5, -1 +// GFX12: encoding: [0xc1,0x6a,0x85,0xbe] + +s_trunc_f32 s5, s1 +// GFX12: encoding: [0x01,0x62,0x85,0xbe] + +s_trunc_f32 s105, s1 +// GFX12: encoding: [0x01,0x62,0xe9,0xbe] + +s_trunc_f32 s5, s105 +// GFX12: encoding: [0x69,0x62,0x85,0xbe] + +s_trunc_f32 s5, s103 +// GFX12: encoding: [0x67,0x62,0x85,0xbe] + +s_trunc_f32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x62,0x85,0xbe] + +s_trunc_f32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x62,0x85,0xbe] + +s_trunc_f32 s5, ttmp11 +// GFX12: encoding: [0x77,0x62,0x85,0xbe] + +s_trunc_f32 s5, m0 +// GFX12: encoding: [0x7d,0x62,0x85,0xbe] + +s_trunc_f32 s5, exec_lo +// GFX12: encoding: [0x7e,0x62,0x85,0xbe] + +s_trunc_f32 s5, exec_hi +// GFX12: encoding: [0x7f,0x62,0x85,0xbe] + +s_trunc_f32 s5, 0 +// GFX12: encoding: [0x80,0x62,0x85,0xbe] + +s_trunc_f32 s5, -1 +// GFX12: encoding: [0xc1,0x62,0x85,0xbe] + +s_trunc_f32 s5, 0.5 +// GFX12: encoding: [0xf0,0x62,0x85,0xbe] + +s_trunc_f32 s5, -4.0 +// GFX12: encoding: [0xf7,0x62,0x85,0xbe] + +s_trunc_f32 s5, 0xaf123456 +// GFX12: encoding: [0xff,0x62,0x85,0xbe,0x56,0x34,0x12,0xaf] + +s_trunc_f32 s5, 0x3f717273 +// GFX12: encoding: [0xff,0x62,0x85,0xbe,0x73,0x72,0x71,0x3f] + +s_ceil_f32 s5, s1 +// GFX12: encoding: [0x01,0x60,0x85,0xbe] + +s_ceil_f32 s105, s1 +// GFX12: encoding: [0x01,0x60,0xe9,0xbe] + +s_ceil_f32 s5, s105 +// GFX12: encoding: [0x69,0x60,0x85,0xbe] + +s_ceil_f32 s5, s103 +// GFX12: encoding: [0x67,0x60,0x85,0xbe] + +s_ceil_f32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x60,0x85,0xbe] + +s_ceil_f32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x60,0x85,0xbe] + +s_ceil_f32 s5, ttmp11 +// GFX12: encoding: [0x77,0x60,0x85,0xbe] + +s_ceil_f32 s5, m0 +// GFX12: encoding: [0x7d,0x60,0x85,0xbe] + +s_ceil_f32 s5, exec_lo +// GFX12: encoding: [0x7e,0x60,0x85,0xbe] + +s_ceil_f32 s5, exec_hi +// GFX12: encoding: [0x7f,0x60,0x85,0xbe] + +s_ceil_f32 s5, 0 +// GFX12: encoding: [0x80,0x60,0x85,0xbe] + +s_ceil_f32 s5, -1 +// GFX12: encoding: [0xc1,0x60,0x85,0xbe] + +s_ceil_f32 s5, 0.5 +// GFX12: encoding: [0xf0,0x60,0x85,0xbe] + +s_ceil_f32 s5, -4.0 +// GFX12: encoding: [0xf7,0x60,0x85,0xbe] + +s_ceil_f32 s5, 0xaf123456 +// GFX12: encoding: [0xff,0x60,0x85,0xbe,0x56,0x34,0x12,0xaf] + +s_ceil_f32 s5, 0x3f717273 +// GFX12: encoding: [0xff,0x60,0x85,0xbe,0x73,0x72,0x71,0x3f] + +s_rndne_f32 s5, s1 +// GFX12: encoding: [0x01,0x63,0x85,0xbe] + +s_rndne_f32 s105, s1 +// GFX12: encoding: [0x01,0x63,0xe9,0xbe] + +s_rndne_f32 s5, s105 +// GFX12: encoding: [0x69,0x63,0x85,0xbe] + +s_rndne_f32 s5, s103 +// GFX12: encoding: [0x67,0x63,0x85,0xbe] + +s_rndne_f32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x63,0x85,0xbe] + +s_rndne_f32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x63,0x85,0xbe] + +s_rndne_f32 s5, ttmp11 +// GFX12: encoding: [0x77,0x63,0x85,0xbe] + +s_rndne_f32 s5, m0 +// GFX12: encoding: [0x7d,0x63,0x85,0xbe] + +s_rndne_f32 s5, exec_lo +// GFX12: encoding: [0x7e,0x63,0x85,0xbe] + +s_rndne_f32 s5, exec_hi +// GFX12: encoding: [0x7f,0x63,0x85,0xbe] + +s_rndne_f32 s5, 0 +// GFX12: encoding: [0x80,0x63,0x85,0xbe] + +s_rndne_f32 s5, -1 +// GFX12: encoding: [0xc1,0x63,0x85,0xbe] + +s_rndne_f32 s5, 0.5 +// GFX12: encoding: [0xf0,0x63,0x85,0xbe] + +s_rndne_f32 s5, -4.0 +// GFX12: encoding: [0xf7,0x63,0x85,0xbe] + +s_rndne_f32 s5, 0xaf123456 +// GFX12: encoding: [0xff,0x63,0x85,0xbe,0x56,0x34,0x12,0xaf] + +s_rndne_f32 s5, 0x3f717273 +// GFX12: encoding: [0xff,0x63,0x85,0xbe,0x73,0x72,0x71,0x3f] + +s_floor_f32 s5, s1 +// GFX12: encoding: [0x01,0x61,0x85,0xbe] + +s_floor_f32 s105, s1 +// GFX12: encoding: [0x01,0x61,0xe9,0xbe] + +s_floor_f32 s5, s105 +// GFX12: encoding: [0x69,0x61,0x85,0xbe] + +s_floor_f32 s5, s103 +// GFX12: encoding: [0x67,0x61,0x85,0xbe] + +s_floor_f32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x61,0x85,0xbe] + +s_floor_f32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x61,0x85,0xbe] + +s_floor_f32 s5, ttmp11 +// GFX12: encoding: [0x77,0x61,0x85,0xbe] + +s_floor_f32 s5, m0 +// GFX12: encoding: [0x7d,0x61,0x85,0xbe] + +s_floor_f32 s5, exec_lo +// GFX12: encoding: [0x7e,0x61,0x85,0xbe] + +s_floor_f32 s5, exec_hi +// GFX12: encoding: [0x7f,0x61,0x85,0xbe] + +s_floor_f32 s5, 0 +// GFX12: encoding: [0x80,0x61,0x85,0xbe] + +s_floor_f32 s5, -1 +// GFX12: encoding: [0xc1,0x61,0x85,0xbe] + +s_floor_f32 s5, 0.5 +// GFX12: encoding: [0xf0,0x61,0x85,0xbe] + +s_floor_f32 s5, -4.0 +// GFX12: encoding: [0xf7,0x61,0x85,0xbe] + +s_floor_f32 s5, 0xaf123456 +// GFX12: encoding: [0xff,0x61,0x85,0xbe,0x56,0x34,0x12,0xaf] + +s_floor_f32 s5, 0x3f717273 +// GFX12: encoding: [0xff,0x61,0x85,0xbe,0x73,0x72,0x71,0x3f] + +s_floor_f16 s5, s1 +// GFX12: encoding: [0x01,0x6c,0x85,0xbe] + +s_floor_f16 s105, s1 +// GFX12: encoding: [0x01,0x6c,0xe9,0xbe] + +s_floor_f16 s5, s105 +// GFX12: encoding: [0x69,0x6c,0x85,0xbe] + +s_floor_f16 s5, s101 +// GFX12: encoding: [0x65,0x6c,0x85,0xbe] + +s_floor_f16 s5, vcc_lo +// GFX12: encoding: [0x6a,0x6c,0x85,0xbe] + +s_floor_f16 s5, vcc_hi +// GFX12: encoding: [0x6b,0x6c,0x85,0xbe] + +s_floor_f16 s5, m0 +// GFX12: encoding: [0x7d,0x6c,0x85,0xbe] + +s_floor_f16 s5, exec_lo +// GFX12: encoding: [0x7e,0x6c,0x85,0xbe] + +s_floor_f16 s5, exec_hi +// GFX12: encoding: [0x7f,0x6c,0x85,0xbe] + +s_floor_f16 s5, 0 +// GFX12: encoding: [0x80,0x6c,0x85,0xbe] + +s_floor_f16 s5, -1 +// GFX12: encoding: [0xc1,0x6c,0x85,0xbe] + +s_floor_f16 s5, 0.5 +// GFX12: encoding: [0xf0,0x6c,0x85,0xbe] + +s_floor_f16 s5, -4.0 +// GFX12: encoding: [0xf7,0x6c,0x85,0xbe] + +s_floor_f16 s5, 0xfe0b +// GFX12: encoding: [0xff,0x6c,0x85,0xbe,0x0b,0xfe,0x00,0x00] + +s_floor_f16 s5, 0x3456 +// GFX12: encoding: [0xff,0x6c,0x85,0xbe,0x56,0x34,0x00,0x00] + +s_ceil_f16 s5, s1 +// GFX12: encoding: [0x01,0x6b,0x85,0xbe] + +s_ceil_f16 s105, s1 +// GFX12: encoding: [0x01,0x6b,0xe9,0xbe] + +s_ceil_f16 s5, s105 +// GFX12: encoding: [0x69,0x6b,0x85,0xbe] + +s_ceil_f16 s5, s101 +// GFX12: encoding: [0x65,0x6b,0x85,0xbe] + +s_ceil_f16 s5, vcc_lo +// GFX12: encoding: [0x6a,0x6b,0x85,0xbe] + +s_ceil_f16 s5, vcc_hi +// GFX12: encoding: [0x6b,0x6b,0x85,0xbe] + +s_ceil_f16 s5, m0 +// GFX12: encoding: [0x7d,0x6b,0x85,0xbe] + +s_ceil_f16 s5, exec_lo +// GFX12: encoding: [0x7e,0x6b,0x85,0xbe] + +s_ceil_f16 s5, exec_hi +// GFX12: encoding: [0x7f,0x6b,0x85,0xbe] + +s_ceil_f16 s5, 0 +// GFX12: encoding: [0x80,0x6b,0x85,0xbe] + +s_ceil_f16 s5, -1 +// GFX12: encoding: [0xc1,0x6b,0x85,0xbe] + +s_ceil_f16 s5, 0.5 +// GFX12: encoding: [0xf0,0x6b,0x85,0xbe] + +s_ceil_f16 s5, -4.0 +// GFX12: encoding: [0xf7,0x6b,0x85,0xbe] + +s_ceil_f16 s5, 0xfe0b +// GFX12: encoding: [0xff,0x6b,0x85,0xbe,0x0b,0xfe,0x00,0x00] + +s_ceil_f16 s5, 0x3456 +// GFX12: encoding: [0xff,0x6b,0x85,0xbe,0x56,0x34,0x00,0x00] + +s_trunc_f16 s5, s1 +// GFX12: encoding: [0x01,0x6d,0x85,0xbe] + +s_trunc_f16 s105, s1 +// GFX12: encoding: [0x01,0x6d,0xe9,0xbe] + +s_trunc_f16 s5, s105 +// GFX12: encoding: [0x69,0x6d,0x85,0xbe] + +s_trunc_f16 s5, s101 +// GFX12: encoding: [0x65,0x6d,0x85,0xbe] + +s_trunc_f16 s5, vcc_lo +// GFX12: encoding: [0x6a,0x6d,0x85,0xbe] + +s_trunc_f16 s5, vcc_hi +// GFX12: encoding: [0x6b,0x6d,0x85,0xbe] + +s_trunc_f16 s5, m0 +// GFX12: encoding: [0x7d,0x6d,0x85,0xbe] + +s_trunc_f16 s5, exec_lo +// GFX12: encoding: [0x7e,0x6d,0x85,0xbe] + +s_trunc_f16 s5, exec_hi +// GFX12: encoding: [0x7f,0x6d,0x85,0xbe] + +s_trunc_f16 s5, 0 +// GFX12: encoding: [0x80,0x6d,0x85,0xbe] + +s_trunc_f16 s5, -1 +// GFX12: encoding: [0xc1,0x6d,0x85,0xbe] + +s_trunc_f16 s5, 0.5 +// GFX12: encoding: [0xf0,0x6d,0x85,0xbe] + +s_trunc_f16 s5, -4.0 +// GFX12: encoding: [0xf7,0x6d,0x85,0xbe] + +s_trunc_f16 s5, 0xfe0b +// GFX12: encoding: [0xff,0x6d,0x85,0xbe,0x0b,0xfe,0x00,0x00] + +s_trunc_f16 s5, 0x3456 +// GFX12: encoding: [0xff,0x6d,0x85,0xbe,0x56,0x34,0x00,0x00] + +s_rndne_f16 s5, s1 +// GFX12: encoding: [0x01,0x6e,0x85,0xbe] + +s_rndne_f16 s105, s1 +// GFX12: encoding: [0x01,0x6e,0xe9,0xbe] + +s_rndne_f16 s5, s105 +// GFX12: encoding: [0x69,0x6e,0x85,0xbe] + +s_rndne_f16 s5, s101 +// GFX12: encoding: [0x65,0x6e,0x85,0xbe] + +s_rndne_f16 s5, vcc_lo +// GFX12: encoding: [0x6a,0x6e,0x85,0xbe] + +s_rndne_f16 s5, vcc_hi +// GFX12: encoding: [0x6b,0x6e,0x85,0xbe] + +s_rndne_f16 s5, m0 +// GFX12: encoding: [0x7d,0x6e,0x85,0xbe] + +s_rndne_f16 s5, exec_lo +// GFX12: encoding: [0x7e,0x6e,0x85,0xbe] + +s_rndne_f16 s5, exec_hi +// GFX12: encoding: [0x7f,0x6e,0x85,0xbe] + +s_rndne_f16 s5, 0 +// GFX12: encoding: [0x80,0x6e,0x85,0xbe] + +s_rndne_f16 s5, -1 +// GFX12: encoding: [0xc1,0x6e,0x85,0xbe] + +s_rndne_f16 s5, 0.5 +// GFX12: encoding: [0xf0,0x6e,0x85,0xbe] + +s_rndne_f16 s5, -4.0 +// GFX12: encoding: [0xf7,0x6e,0x85,0xbe] + +s_rndne_f16 s5, 0xfe0b +// GFX12: encoding: [0xff,0x6e,0x85,0xbe,0x0b,0xfe,0x00,0x00] + +s_rndne_f16 s5, 0x3456 +// GFX12: encoding: [0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00] + +s_mov_b32 s0, s1 +// GFX12: encoding: [0x01,0x00,0x80,0xbe] + +s_mov_b32 s105, s104 +// GFX12: encoding: [0x68,0x00,0xe9,0xbe] + +s_mov_b32 s0, s104 +// GFX12: encoding: [0x68,0x00,0x80,0xbe] + +s_mov_b32 s105, s1 +// GFX12: encoding: [0x01,0x00,0xe9,0xbe] + +s_mov_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x00,0xfe,0xbe] + +s_mov_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x00,0xff,0xbe] + +s_mov_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x00,0xea,0xbe] + +s_mov_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x00,0xeb,0xbe] + +s_mov_b32 m0, s1 +// GFX12: encoding: [0x01,0x00,0xfd,0xbe] + +s_mov_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x00,0x80,0xbe] + +s_mov_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x00,0x80,0xbe] + +s_mov_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x00,0x80,0xbe] + +s_mov_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x00,0x80,0xbe] + +s_mov_b32 s0, m0 +// GFX12: encoding: [0x7d,0x00,0x80,0xbe] + +s_mov_b32 s0, 0 +// GFX12: encoding: [0x80,0x00,0x80,0xbe] + +s_mov_b32 s0, -1 +// GFX12: encoding: [0xc1,0x00,0x80,0xbe] + +s_mov_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x00,0x80,0xbe] + +s_mov_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x00,0x80,0xbe] + +s_mov_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x00,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_mov_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x00,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_mov_b32 s0, null +// GFX12: encoding: [0x7c,0x00,0x80,0xbe] + +s_mov_b32 null, s1 +// GFX12: encoding: [0x01,0x00,0xfc,0xbe] + +s_mov_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x01,0x80,0xbe] + +s_mov_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x01,0xe8,0xbe] + +s_mov_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x01,0x80,0xbe] + +s_mov_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x01,0xe8,0xbe] + +s_mov_b64 exec, s[2:3] +// GFX12: encoding: [0x02,0x01,0xfe,0xbe] + +s_mov_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x01,0xea,0xbe] + +s_mov_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x01,0x80,0xbe] + +s_mov_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x01,0x80,0xbe] + +s_mov_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x01,0x80,0xbe] + +s_mov_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x01,0x80,0xbe] + +s_mov_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x01,0x80,0xbe] + +s_mov_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x01,0x80,0xbe] + +s_mov_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x01,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_mov_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_mov_b64 s[0:1], null +// GFX12: encoding: [0x7c,0x01,0x80,0xbe] + +s_mov_b64 null, s[2:3] +// GFX12: encoding: [0x02,0x01,0xfc,0xbe] + +s_cmov_b32 s0, s1 +// GFX12: encoding: [0x01,0x02,0x80,0xbe] + +s_cmov_b32 s105, s104 +// GFX12: encoding: [0x68,0x02,0xe9,0xbe] + +s_cmov_b32 s0, s104 +// GFX12: encoding: [0x68,0x02,0x80,0xbe] + +s_cmov_b32 s105, s1 +// GFX12: encoding: [0x01,0x02,0xe9,0xbe] + +s_cmov_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x02,0xfe,0xbe] + +s_cmov_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x02,0xff,0xbe] + +s_cmov_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x02,0xea,0xbe] + +s_cmov_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x02,0xeb,0xbe] + +s_cmov_b32 m0, s1 +// GFX12: encoding: [0x01,0x02,0xfd,0xbe] + +s_cmov_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x02,0x80,0xbe] + +s_cmov_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x02,0x80,0xbe] + +s_cmov_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x02,0x80,0xbe] + +s_cmov_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x02,0x80,0xbe] + +s_cmov_b32 s0, m0 +// GFX12: encoding: [0x7d,0x02,0x80,0xbe] + +s_cmov_b32 s0, 0 +// GFX12: encoding: [0x80,0x02,0x80,0xbe] + +s_cmov_b32 s0, -1 +// GFX12: encoding: [0xc1,0x02,0x80,0xbe] + +s_cmov_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x02,0x80,0xbe] + +s_cmov_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x02,0x80,0xbe] + +s_cmov_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x02,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_cmov_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x02,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_cmov_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x03,0x80,0xbe] + +s_cmov_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x03,0xe8,0xbe] + +s_cmov_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x03,0x80,0xbe] + +s_cmov_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x03,0xe8,0xbe] + +s_cmov_b64 exec, s[2:3] +// GFX12: encoding: [0x02,0x03,0xfe,0xbe] + +s_cmov_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x03,0xea,0xbe] + +s_cmov_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x03,0x80,0xbe] + +s_cmov_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x03,0x80,0xbe] + +s_cmov_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x03,0x80,0xbe] + +s_cmov_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x03,0x80,0xbe] + +s_cmov_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x03,0x80,0xbe] + +s_cmov_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x03,0x80,0xbe] + +s_cmov_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x03,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_cmov_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_not_b32 s0, s1 +// GFX12: encoding: [0x01,0x1e,0x80,0xbe] + +s_not_b32 s105, s104 +// GFX12: encoding: [0x68,0x1e,0xe9,0xbe] + +s_not_b32 s0, s104 +// GFX12: encoding: [0x68,0x1e,0x80,0xbe] + +s_not_b32 s105, s1 +// GFX12: encoding: [0x01,0x1e,0xe9,0xbe] + +s_not_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x1e,0xfe,0xbe] + +s_not_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x1e,0xff,0xbe] + +s_not_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x1e,0xea,0xbe] + +s_not_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x1e,0xeb,0xbe] + +s_not_b32 m0, s1 +// GFX12: encoding: [0x01,0x1e,0xfd,0xbe] + +s_not_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x1e,0x80,0xbe] + +s_not_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x1e,0x80,0xbe] + +s_not_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x1e,0x80,0xbe] + +s_not_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x1e,0x80,0xbe] + +s_not_b32 s0, m0 +// GFX12: encoding: [0x7d,0x1e,0x80,0xbe] + +s_not_b32 s0, 0 +// GFX12: encoding: [0x80,0x1e,0x80,0xbe] + +s_not_b32 s0, -1 +// GFX12: encoding: [0xc1,0x1e,0x80,0xbe] + +s_not_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x1e,0x80,0xbe] + +s_not_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x1e,0x80,0xbe] + +s_not_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x1e,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_not_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x1e,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_not_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x1f,0x80,0xbe] + +s_not_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x1f,0xe8,0xbe] + +s_not_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x1f,0x80,0xbe] + +s_not_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x1f,0xe8,0xbe] + +s_not_b64 exec, s[2:3] +// GFX12: encoding: [0x02,0x1f,0xfe,0xbe] + +s_not_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x1f,0xea,0xbe] + +s_not_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x1f,0x80,0xbe] + +s_not_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x1f,0x80,0xbe] + +s_not_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x1f,0x80,0xbe] + +s_not_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x1f,0x80,0xbe] + +s_not_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x1f,0x80,0xbe] + +s_not_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x1f,0x80,0xbe] + +s_not_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x1f,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_not_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_wqm_b32 s0, s1 +// GFX12: encoding: [0x01,0x1c,0x80,0xbe] + +s_wqm_b32 s105, s104 +// GFX12: encoding: [0x68,0x1c,0xe9,0xbe] + +s_wqm_b32 s0, s104 +// GFX12: encoding: [0x68,0x1c,0x80,0xbe] + +s_wqm_b32 s105, s1 +// GFX12: encoding: [0x01,0x1c,0xe9,0xbe] + +s_wqm_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x1c,0xfe,0xbe] + +s_wqm_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x1c,0xff,0xbe] + +s_wqm_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x1c,0xea,0xbe] + +s_wqm_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x1c,0xeb,0xbe] + +s_wqm_b32 m0, s1 +// GFX12: encoding: [0x01,0x1c,0xfd,0xbe] + +s_wqm_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x1c,0x80,0xbe] + +s_wqm_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x1c,0x80,0xbe] + +s_wqm_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x1c,0x80,0xbe] + +s_wqm_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x1c,0x80,0xbe] + +s_wqm_b32 s0, m0 +// GFX12: encoding: [0x7d,0x1c,0x80,0xbe] + +s_wqm_b32 s0, 0 +// GFX12: encoding: [0x80,0x1c,0x80,0xbe] + +s_wqm_b32 s0, -1 +// GFX12: encoding: [0xc1,0x1c,0x80,0xbe] + +s_wqm_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x1c,0x80,0xbe] + +s_wqm_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x1c,0x80,0xbe] + +s_wqm_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x1c,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_wqm_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x1c,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_wqm_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x1d,0x80,0xbe] + +s_wqm_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x1d,0xe8,0xbe] + +s_wqm_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x1d,0x80,0xbe] + +s_wqm_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x1d,0xe8,0xbe] + +s_wqm_b64 exec, s[2:3] +// GFX12: encoding: [0x02,0x1d,0xfe,0xbe] + +s_wqm_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x1d,0xea,0xbe] + +s_wqm_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x1d,0x80,0xbe] + +s_wqm_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x1d,0x80,0xbe] + +s_wqm_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x1d,0x80,0xbe] + +s_wqm_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x1d,0x80,0xbe] + +s_wqm_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x1d,0x80,0xbe] + +s_wqm_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x1d,0x80,0xbe] + +s_wqm_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x1d,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_wqm_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_brev_b32 s0, s1 +// GFX12: encoding: [0x01,0x04,0x80,0xbe] + +s_brev_b32 s105, s104 +// GFX12: encoding: [0x68,0x04,0xe9,0xbe] + +s_brev_b32 s0, s104 +// GFX12: encoding: [0x68,0x04,0x80,0xbe] + +s_brev_b32 s105, s1 +// GFX12: encoding: [0x01,0x04,0xe9,0xbe] + +s_brev_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x04,0xfe,0xbe] + +s_brev_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x04,0xff,0xbe] + +s_brev_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x04,0xea,0xbe] + +s_brev_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x04,0xeb,0xbe] + +s_brev_b32 m0, s1 +// GFX12: encoding: [0x01,0x04,0xfd,0xbe] + +s_brev_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x04,0x80,0xbe] + +s_brev_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x04,0x80,0xbe] + +s_brev_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x04,0x80,0xbe] + +s_brev_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x04,0x80,0xbe] + +s_brev_b32 s0, m0 +// GFX12: encoding: [0x7d,0x04,0x80,0xbe] + +s_brev_b32 s0, 0 +// GFX12: encoding: [0x80,0x04,0x80,0xbe] + +s_brev_b32 s0, -1 +// GFX12: encoding: [0xc1,0x04,0x80,0xbe] + +s_brev_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x04,0x80,0xbe] + +s_brev_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x04,0x80,0xbe] + +s_brev_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x04,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_brev_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x04,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_brev_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x05,0x80,0xbe] + +s_brev_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x05,0xe8,0xbe] + +s_brev_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x05,0x80,0xbe] + +s_brev_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x05,0xe8,0xbe] + +s_brev_b64 exec, s[2:3] +// GFX12: encoding: [0x02,0x05,0xfe,0xbe] + +s_brev_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x05,0xea,0xbe] + +s_brev_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x05,0x80,0xbe] + +s_brev_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x05,0x80,0xbe] + +s_brev_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x05,0x80,0xbe] + +s_brev_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x05,0x80,0xbe] + +s_brev_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x05,0x80,0xbe] + +s_brev_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x05,0x80,0xbe] + +s_brev_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x05,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_brev_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_bcnt0_i32_b32 s0, s1 +// GFX12: encoding: [0x01,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s105, s104 +// GFX12: encoding: [0x68,0x16,0xe9,0xbe] + +s_bcnt0_i32_b32 s0, s104 +// GFX12: encoding: [0x68,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s105, s1 +// GFX12: encoding: [0x01,0x16,0xe9,0xbe] + +s_bcnt0_i32_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x16,0xfe,0xbe] + +s_bcnt0_i32_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x16,0xff,0xbe] + +s_bcnt0_i32_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x16,0xea,0xbe] + +s_bcnt0_i32_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x16,0xeb,0xbe] + +s_bcnt0_i32_b32 m0, s1 +// GFX12: encoding: [0x01,0x16,0xfd,0xbe] + +s_bcnt0_i32_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s0, m0 +// GFX12: encoding: [0x7d,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s0, 0 +// GFX12: encoding: [0x80,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s0, -1 +// GFX12: encoding: [0xc1,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x16,0x80,0xbe] + +s_bcnt0_i32_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x16,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_bcnt0_i32_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x16,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_bcnt0_i32_b64 s0, s[2:3] +// GFX12: encoding: [0x02,0x17,0x80,0xbe] + +s_bcnt0_i32_b64 s105, s[102:103] +// GFX12: encoding: [0x66,0x17,0xe9,0xbe] + +s_bcnt0_i32_b64 s0, s[102:103] +// GFX12: encoding: [0x66,0x17,0x80,0xbe] + +s_bcnt0_i32_b64 s105, s[2:3] +// GFX12: encoding: [0x02,0x17,0xe9,0xbe] + +s_bcnt0_i32_b64 exec_lo, s[2:3] +// GFX12: encoding: [0x02,0x17,0xfe,0xbe] + +s_bcnt0_i32_b64 exec_hi, s[2:3] +// GFX12: encoding: [0x02,0x17,0xff,0xbe] + +s_bcnt0_i32_b64 vcc_lo, s[2:3] +// GFX12: encoding: [0x02,0x17,0xea,0xbe] + +s_bcnt0_i32_b64 vcc_hi, s[2:3] +// GFX12: encoding: [0x02,0x17,0xeb,0xbe] + +s_bcnt0_i32_b64 m0, s[2:3] +// GFX12: encoding: [0x02,0x17,0xfd,0xbe] + +s_bcnt0_i32_b64 s0, exec +// GFX12: encoding: [0x7e,0x17,0x80,0xbe] + +s_bcnt0_i32_b64 s0, vcc +// GFX12: encoding: [0x6a,0x17,0x80,0xbe] + +s_bcnt0_i32_b64 s0, 0 +// GFX12: encoding: [0x80,0x17,0x80,0xbe] + +s_bcnt0_i32_b64 s0, -1 +// GFX12: encoding: [0xc1,0x17,0x80,0xbe] + +s_bcnt0_i32_b64 s0, 0.5 +// GFX12: encoding: [0xf0,0x17,0x80,0xbe] + +s_bcnt0_i32_b64 s0, -4.0 +// GFX12: encoding: [0xf7,0x17,0x80,0xbe] + +s_bcnt0_i32_b64 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x17,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_bcnt0_i32_b64 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_bcnt1_i32_b32 s0, s1 +// GFX12: encoding: [0x01,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s105, s104 +// GFX12: encoding: [0x68,0x18,0xe9,0xbe] + +s_bcnt1_i32_b32 s0, s104 +// GFX12: encoding: [0x68,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s105, s1 +// GFX12: encoding: [0x01,0x18,0xe9,0xbe] + +s_bcnt1_i32_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x18,0xfe,0xbe] + +s_bcnt1_i32_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x18,0xff,0xbe] + +s_bcnt1_i32_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x18,0xea,0xbe] + +s_bcnt1_i32_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x18,0xeb,0xbe] + +s_bcnt1_i32_b32 m0, s1 +// GFX12: encoding: [0x01,0x18,0xfd,0xbe] + +s_bcnt1_i32_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s0, m0 +// GFX12: encoding: [0x7d,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s0, 0 +// GFX12: encoding: [0x80,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s0, -1 +// GFX12: encoding: [0xc1,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x18,0x80,0xbe] + +s_bcnt1_i32_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x18,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_bcnt1_i32_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x18,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_bcnt1_i32_b64 s0, s[2:3] +// GFX12: encoding: [0x02,0x19,0x80,0xbe] + +s_bcnt1_i32_b64 s105, s[102:103] +// GFX12: encoding: [0x66,0x19,0xe9,0xbe] + +s_bcnt1_i32_b64 s0, s[102:103] +// GFX12: encoding: [0x66,0x19,0x80,0xbe] + +s_bcnt1_i32_b64 s105, s[2:3] +// GFX12: encoding: [0x02,0x19,0xe9,0xbe] + +s_bcnt1_i32_b64 exec_lo, s[2:3] +// GFX12: encoding: [0x02,0x19,0xfe,0xbe] + +s_bcnt1_i32_b64 exec_hi, s[2:3] +// GFX12: encoding: [0x02,0x19,0xff,0xbe] + +s_bcnt1_i32_b64 vcc_lo, s[2:3] +// GFX12: encoding: [0x02,0x19,0xea,0xbe] + +s_bcnt1_i32_b64 vcc_hi, s[2:3] +// GFX12: encoding: [0x02,0x19,0xeb,0xbe] + +s_bcnt1_i32_b64 m0, s[2:3] +// GFX12: encoding: [0x02,0x19,0xfd,0xbe] + +s_bcnt1_i32_b64 s0, exec +// GFX12: encoding: [0x7e,0x19,0x80,0xbe] + +s_bcnt1_i32_b64 s0, vcc +// GFX12: encoding: [0x6a,0x19,0x80,0xbe] + +s_bcnt1_i32_b64 s0, 0 +// GFX12: encoding: [0x80,0x19,0x80,0xbe] + +s_bcnt1_i32_b64 s0, -1 +// GFX12: encoding: [0xc1,0x19,0x80,0xbe] + +s_bcnt1_i32_b64 s0, 0.5 +// GFX12: encoding: [0xf0,0x19,0x80,0xbe] + +s_bcnt1_i32_b64 s0, -4.0 +// GFX12: encoding: [0xf7,0x19,0x80,0xbe] + +s_bcnt1_i32_b64 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x19,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_bcnt1_i32_b64 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_ff1_i32_b32 s0, s1 +// GFX12: encoding: [0x01,0x08,0x80,0xbe] + +s_ff1_i32_b32 s105, s104 +// GFX12: encoding: [0x68,0x08,0xe9,0xbe] + +s_ff1_i32_b32 s0, s104 +// GFX12: encoding: [0x68,0x08,0x80,0xbe] + +s_ff1_i32_b32 s105, s1 +// GFX12: encoding: [0x01,0x08,0xe9,0xbe] + +s_ff1_i32_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x08,0xfe,0xbe] + +s_ff1_i32_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x08,0xff,0xbe] + +s_ff1_i32_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x08,0xea,0xbe] + +s_ff1_i32_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x08,0xeb,0xbe] + +s_ff1_i32_b32 m0, s1 +// GFX12: encoding: [0x01,0x08,0xfd,0xbe] + +s_ff1_i32_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x08,0x80,0xbe] + +s_ff1_i32_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x08,0x80,0xbe] + +s_ff1_i32_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x08,0x80,0xbe] + +s_ff1_i32_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x08,0x80,0xbe] + +s_ff1_i32_b32 s0, m0 +// GFX12: encoding: [0x7d,0x08,0x80,0xbe] + +s_ff1_i32_b32 s0, 0 +// GFX12: encoding: [0x80,0x08,0x80,0xbe] + +s_ff1_i32_b32 s0, -1 +// GFX12: encoding: [0xc1,0x08,0x80,0xbe] + +s_ff1_i32_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x08,0x80,0xbe] + +s_ff1_i32_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x08,0x80,0xbe] + +s_ff1_i32_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x08,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_ff1_i32_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x08,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_ff1_i32_b64 s0, s[2:3] +// GFX12: encoding: [0x02,0x09,0x80,0xbe] + +s_ff1_i32_b64 s105, s[102:103] +// GFX12: encoding: [0x66,0x09,0xe9,0xbe] + +s_ff1_i32_b64 s0, s[102:103] +// GFX12: encoding: [0x66,0x09,0x80,0xbe] + +s_ff1_i32_b64 s105, s[2:3] +// GFX12: encoding: [0x02,0x09,0xe9,0xbe] + +s_ff1_i32_b64 exec_lo, s[2:3] +// GFX12: encoding: [0x02,0x09,0xfe,0xbe] + +s_ff1_i32_b64 exec_hi, s[2:3] +// GFX12: encoding: [0x02,0x09,0xff,0xbe] + +s_ff1_i32_b64 vcc_lo, s[2:3] +// GFX12: encoding: [0x02,0x09,0xea,0xbe] + +s_ff1_i32_b64 vcc_hi, s[2:3] +// GFX12: encoding: [0x02,0x09,0xeb,0xbe] + +s_ff1_i32_b64 m0, s[2:3] +// GFX12: encoding: [0x02,0x09,0xfd,0xbe] + +s_ff1_i32_b64 s0, exec +// GFX12: encoding: [0x7e,0x09,0x80,0xbe] + +s_ff1_i32_b64 s0, vcc +// GFX12: encoding: [0x6a,0x09,0x80,0xbe] + +s_ff1_i32_b64 s0, 0 +// GFX12: encoding: [0x80,0x09,0x80,0xbe] + +s_ff1_i32_b64 s0, -1 +// GFX12: encoding: [0xc1,0x09,0x80,0xbe] + +s_ff1_i32_b64 s0, 0.5 +// GFX12: encoding: [0xf0,0x09,0x80,0xbe] + +s_ff1_i32_b64 s0, -4.0 +// GFX12: encoding: [0xf7,0x09,0x80,0xbe] + +s_ff1_i32_b64 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x09,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_ff1_i32_b64 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_flbit_i32_b32 s0, s1 +// GFX12: encoding: [0x01,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s105, s104 +// GFX12: encoding: [0x68,0x0a,0xe9,0xbe] + +s_flbit_i32_b32 s0, s104 +// GFX12: encoding: [0x68,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s105, s1 +// GFX12: encoding: [0x01,0x0a,0xe9,0xbe] + +s_flbit_i32_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x0a,0xfe,0xbe] + +s_flbit_i32_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x0a,0xff,0xbe] + +s_flbit_i32_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x0a,0xea,0xbe] + +s_flbit_i32_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x0a,0xeb,0xbe] + +s_flbit_i32_b32 m0, s1 +// GFX12: encoding: [0x01,0x0a,0xfd,0xbe] + +s_flbit_i32_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s0, m0 +// GFX12: encoding: [0x7d,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s0, 0 +// GFX12: encoding: [0x80,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s0, -1 +// GFX12: encoding: [0xc1,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x0a,0x80,0xbe] + +s_flbit_i32_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x0a,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_flbit_i32_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x0a,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_flbit_i32_b64 s0, s[2:3] +// GFX12: encoding: [0x02,0x0b,0x80,0xbe] + +s_flbit_i32_b64 s105, s[102:103] +// GFX12: encoding: [0x66,0x0b,0xe9,0xbe] + +s_flbit_i32_b64 s0, s[102:103] +// GFX12: encoding: [0x66,0x0b,0x80,0xbe] + +s_flbit_i32_b64 s105, s[2:3] +// GFX12: encoding: [0x02,0x0b,0xe9,0xbe] + +s_flbit_i32_b64 exec_lo, s[2:3] +// GFX12: encoding: [0x02,0x0b,0xfe,0xbe] + +s_flbit_i32_b64 exec_hi, s[2:3] +// GFX12: encoding: [0x02,0x0b,0xff,0xbe] + +s_flbit_i32_b64 vcc_lo, s[2:3] +// GFX12: encoding: [0x02,0x0b,0xea,0xbe] + +s_flbit_i32_b64 vcc_hi, s[2:3] +// GFX12: encoding: [0x02,0x0b,0xeb,0xbe] + +s_flbit_i32_b64 m0, s[2:3] +// GFX12: encoding: [0x02,0x0b,0xfd,0xbe] + +s_flbit_i32_b64 s0, exec +// GFX12: encoding: [0x7e,0x0b,0x80,0xbe] + +s_flbit_i32_b64 s0, vcc +// GFX12: encoding: [0x6a,0x0b,0x80,0xbe] + +s_flbit_i32_b64 s0, 0 +// GFX12: encoding: [0x80,0x0b,0x80,0xbe] + +s_flbit_i32_b64 s0, -1 +// GFX12: encoding: [0xc1,0x0b,0x80,0xbe] + +s_flbit_i32_b64 s0, 0.5 +// GFX12: encoding: [0xf0,0x0b,0x80,0xbe] + +s_flbit_i32_b64 s0, -4.0 +// GFX12: encoding: [0xf7,0x0b,0x80,0xbe] + +s_flbit_i32_b64 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x0b,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_flbit_i32_b64 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_flbit_i32 s0, s1 +// GFX12: encoding: [0x01,0x0c,0x80,0xbe] + +s_flbit_i32 s105, s104 +// GFX12: encoding: [0x68,0x0c,0xe9,0xbe] + +s_flbit_i32 s0, s104 +// GFX12: encoding: [0x68,0x0c,0x80,0xbe] + +s_flbit_i32 s105, s1 +// GFX12: encoding: [0x01,0x0c,0xe9,0xbe] + +s_flbit_i32 exec_lo, s1 +// GFX12: encoding: [0x01,0x0c,0xfe,0xbe] + +s_flbit_i32 exec_hi, s1 +// GFX12: encoding: [0x01,0x0c,0xff,0xbe] + +s_flbit_i32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x0c,0xea,0xbe] + +s_flbit_i32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x0c,0xeb,0xbe] + +s_flbit_i32 m0, s1 +// GFX12: encoding: [0x01,0x0c,0xfd,0xbe] + +s_flbit_i32 s0, exec_lo +// GFX12: encoding: [0x7e,0x0c,0x80,0xbe] + +s_flbit_i32 s0, exec_hi +// GFX12: encoding: [0x7f,0x0c,0x80,0xbe] + +s_flbit_i32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x0c,0x80,0xbe] + +s_flbit_i32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x0c,0x80,0xbe] + +s_flbit_i32 s0, m0 +// GFX12: encoding: [0x7d,0x0c,0x80,0xbe] + +s_flbit_i32 s0, 0 +// GFX12: encoding: [0x80,0x0c,0x80,0xbe] + +s_flbit_i32 s0, -1 +// GFX12: encoding: [0xc1,0x0c,0x80,0xbe] + +s_flbit_i32 s0, 0.5 +// GFX12: encoding: [0xf0,0x0c,0x80,0xbe] + +s_flbit_i32 s0, -4.0 +// GFX12: encoding: [0xf7,0x0c,0x80,0xbe] + +s_flbit_i32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x0c,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_flbit_i32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x0c,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_flbit_i32_i64 s0, s[2:3] +// GFX12: encoding: [0x02,0x0d,0x80,0xbe] + +s_flbit_i32_i64 s105, s[102:103] +// GFX12: encoding: [0x66,0x0d,0xe9,0xbe] + +s_flbit_i32_i64 s0, s[102:103] +// GFX12: encoding: [0x66,0x0d,0x80,0xbe] + +s_flbit_i32_i64 s105, s[2:3] +// GFX12: encoding: [0x02,0x0d,0xe9,0xbe] + +s_flbit_i32_i64 exec_lo, s[2:3] +// GFX12: encoding: [0x02,0x0d,0xfe,0xbe] + +s_flbit_i32_i64 exec_hi, s[2:3] +// GFX12: encoding: [0x02,0x0d,0xff,0xbe] + +s_flbit_i32_i64 vcc_lo, s[2:3] +// GFX12: encoding: [0x02,0x0d,0xea,0xbe] + +s_flbit_i32_i64 vcc_hi, s[2:3] +// GFX12: encoding: [0x02,0x0d,0xeb,0xbe] + +s_flbit_i32_i64 m0, s[2:3] +// GFX12: encoding: [0x02,0x0d,0xfd,0xbe] + +s_flbit_i32_i64 s0, exec +// GFX12: encoding: [0x7e,0x0d,0x80,0xbe] + +s_flbit_i32_i64 s0, vcc +// GFX12: encoding: [0x6a,0x0d,0x80,0xbe] + +s_flbit_i32_i64 s0, 0 +// GFX12: encoding: [0x80,0x0d,0x80,0xbe] + +s_flbit_i32_i64 s0, -1 +// GFX12: encoding: [0xc1,0x0d,0x80,0xbe] + +s_flbit_i32_i64 s0, 0.5 +// GFX12: encoding: [0xf0,0x0d,0x80,0xbe] + +s_flbit_i32_i64 s0, -4.0 +// GFX12: encoding: [0xf7,0x0d,0x80,0xbe] + +s_flbit_i32_i64 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x0d,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_flbit_i32_i64 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_sext_i32_i8 s0, s1 +// GFX12: encoding: [0x01,0x0e,0x80,0xbe] + +s_sext_i32_i8 s105, s104 +// GFX12: encoding: [0x68,0x0e,0xe9,0xbe] + +s_sext_i32_i8 s0, s104 +// GFX12: encoding: [0x68,0x0e,0x80,0xbe] + +s_sext_i32_i8 s105, s1 +// GFX12: encoding: [0x01,0x0e,0xe9,0xbe] + +s_sext_i32_i8 exec_lo, s1 +// GFX12: encoding: [0x01,0x0e,0xfe,0xbe] + +s_sext_i32_i8 exec_hi, s1 +// GFX12: encoding: [0x01,0x0e,0xff,0xbe] + +s_sext_i32_i8 vcc_lo, s1 +// GFX12: encoding: [0x01,0x0e,0xea,0xbe] + +s_sext_i32_i8 vcc_hi, s1 +// GFX12: encoding: [0x01,0x0e,0xeb,0xbe] + +s_sext_i32_i8 m0, s1 +// GFX12: encoding: [0x01,0x0e,0xfd,0xbe] + +s_sext_i32_i8 s0, exec_lo +// GFX12: encoding: [0x7e,0x0e,0x80,0xbe] + +s_sext_i32_i8 s0, exec_hi +// GFX12: encoding: [0x7f,0x0e,0x80,0xbe] + +s_sext_i32_i8 s0, vcc_lo +// GFX12: encoding: [0x6a,0x0e,0x80,0xbe] + +s_sext_i32_i8 s0, vcc_hi +// GFX12: encoding: [0x6b,0x0e,0x80,0xbe] + +s_sext_i32_i8 s0, m0 +// GFX12: encoding: [0x7d,0x0e,0x80,0xbe] + +s_sext_i32_i8 s0, 0 +// GFX12: encoding: [0x80,0x0e,0x80,0xbe] + +s_sext_i32_i8 s0, -1 +// GFX12: encoding: [0xc1,0x0e,0x80,0xbe] + +s_sext_i32_i8 s0, 0.5 +// GFX12: encoding: [0xf0,0x0e,0x80,0xbe] + +s_sext_i32_i8 s0, -4.0 +// GFX12: encoding: [0xf7,0x0e,0x80,0xbe] + +s_sext_i32_i8 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x0e,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_sext_i32_i8 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x0e,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_sext_i32_i16 s0, s1 +// GFX12: encoding: [0x01,0x0f,0x80,0xbe] + +s_sext_i32_i16 s105, s104 +// GFX12: encoding: [0x68,0x0f,0xe9,0xbe] + +s_sext_i32_i16 s0, s104 +// GFX12: encoding: [0x68,0x0f,0x80,0xbe] + +s_sext_i32_i16 s105, s1 +// GFX12: encoding: [0x01,0x0f,0xe9,0xbe] + +s_sext_i32_i16 exec_lo, s1 +// GFX12: encoding: [0x01,0x0f,0xfe,0xbe] + +s_sext_i32_i16 exec_hi, s1 +// GFX12: encoding: [0x01,0x0f,0xff,0xbe] + +s_sext_i32_i16 vcc_lo, s1 +// GFX12: encoding: [0x01,0x0f,0xea,0xbe] + +s_sext_i32_i16 vcc_hi, s1 +// GFX12: encoding: [0x01,0x0f,0xeb,0xbe] + +s_sext_i32_i16 m0, s1 +// GFX12: encoding: [0x01,0x0f,0xfd,0xbe] + +s_sext_i32_i16 s0, exec_lo +// GFX12: encoding: [0x7e,0x0f,0x80,0xbe] + +s_sext_i32_i16 s0, exec_hi +// GFX12: encoding: [0x7f,0x0f,0x80,0xbe] + +s_sext_i32_i16 s0, vcc_lo +// GFX12: encoding: [0x6a,0x0f,0x80,0xbe] + +s_sext_i32_i16 s0, vcc_hi +// GFX12: encoding: [0x6b,0x0f,0x80,0xbe] + +s_sext_i32_i16 s0, m0 +// GFX12: encoding: [0x7d,0x0f,0x80,0xbe] + +s_sext_i32_i16 s0, 0 +// GFX12: encoding: [0x80,0x0f,0x80,0xbe] + +s_sext_i32_i16 s0, -1 +// GFX12: encoding: [0xc1,0x0f,0x80,0xbe] + +s_sext_i32_i16 s0, 0.5 +// GFX12: encoding: [0xf0,0x0f,0x80,0xbe] + +s_sext_i32_i16 s0, -4.0 +// GFX12: encoding: [0xf7,0x0f,0x80,0xbe] + +s_sext_i32_i16 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x0f,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_sext_i32_i16 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x0f,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_bitset0_b32 s0, s1 +// GFX12: encoding: [0x01,0x10,0x80,0xbe] + +s_bitset0_b32 s105, s104 +// GFX12: encoding: [0x68,0x10,0xe9,0xbe] + +s_bitset0_b32 s0, s104 +// GFX12: encoding: [0x68,0x10,0x80,0xbe] + +s_bitset0_b32 s105, s1 +// GFX12: encoding: [0x01,0x10,0xe9,0xbe] + +s_bitset0_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x10,0xfe,0xbe] + +s_bitset0_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x10,0xff,0xbe] + +s_bitset0_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x10,0xea,0xbe] + +s_bitset0_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x10,0xeb,0xbe] + +s_bitset0_b32 m0, s1 +// GFX12: encoding: [0x01,0x10,0xfd,0xbe] + +s_bitset0_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x10,0x80,0xbe] + +s_bitset0_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x10,0x80,0xbe] + +s_bitset0_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x10,0x80,0xbe] + +s_bitset0_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x10,0x80,0xbe] + +s_bitset0_b32 s0, m0 +// GFX12: encoding: [0x7d,0x10,0x80,0xbe] + +s_bitset0_b32 s0, 0 +// GFX12: encoding: [0x80,0x10,0x80,0xbe] + +s_bitset0_b32 s0, -1 +// GFX12: encoding: [0xc1,0x10,0x80,0xbe] + +s_bitset0_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x10,0x80,0xbe] + +s_bitset0_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x10,0x80,0xbe] + +s_bitset0_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x10,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_bitset0_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x10,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_bitset0_b64 s[0:1], s2 +// GFX12: encoding: [0x02,0x11,0x80,0xbe] + +s_bitset0_b64 s[104:105], s102 +// GFX12: encoding: [0x66,0x11,0xe8,0xbe] + +s_bitset0_b64 s[0:1], s102 +// GFX12: encoding: [0x66,0x11,0x80,0xbe] + +s_bitset0_b64 s[104:105], s2 +// GFX12: encoding: [0x02,0x11,0xe8,0xbe] + +s_bitset0_b64 exec, s2 +// GFX12: encoding: [0x02,0x11,0xfe,0xbe] + +s_bitset0_b64 vcc, s2 +// GFX12: encoding: [0x02,0x11,0xea,0xbe] + +s_bitset0_b64 s[0:1], exec_lo +// GFX12: encoding: [0x7e,0x11,0x80,0xbe] + +s_bitset0_b64 s[0:1], exec_hi +// GFX12: encoding: [0x7f,0x11,0x80,0xbe] + +s_bitset0_b64 s[0:1], vcc_lo +// GFX12: encoding: [0x6a,0x11,0x80,0xbe] + +s_bitset0_b64 s[0:1], vcc_hi +// GFX12: encoding: [0x6b,0x11,0x80,0xbe] + +s_bitset0_b64 s[0:1], m0 +// GFX12: encoding: [0x7d,0x11,0x80,0xbe] + +s_bitset0_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x11,0x80,0xbe] + +s_bitset0_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x11,0x80,0xbe] + +s_bitset0_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x11,0x80,0xbe] + +s_bitset0_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x11,0x80,0xbe] + +s_bitset0_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x11,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_bitset0_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x11,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_bitset1_b32 s0, s1 +// GFX12: encoding: [0x01,0x12,0x80,0xbe] + +s_bitset1_b32 s105, s104 +// GFX12: encoding: [0x68,0x12,0xe9,0xbe] + +s_bitset1_b32 s0, s104 +// GFX12: encoding: [0x68,0x12,0x80,0xbe] + +s_bitset1_b32 s105, s1 +// GFX12: encoding: [0x01,0x12,0xe9,0xbe] + +s_bitset1_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x12,0xfe,0xbe] + +s_bitset1_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x12,0xff,0xbe] + +s_bitset1_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x12,0xea,0xbe] + +s_bitset1_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x12,0xeb,0xbe] + +s_bitset1_b32 m0, s1 +// GFX12: encoding: [0x01,0x12,0xfd,0xbe] + +s_bitset1_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x12,0x80,0xbe] + +s_bitset1_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x12,0x80,0xbe] + +s_bitset1_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x12,0x80,0xbe] + +s_bitset1_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x12,0x80,0xbe] + +s_bitset1_b32 s0, m0 +// GFX12: encoding: [0x7d,0x12,0x80,0xbe] + +s_bitset1_b32 s0, 0 +// GFX12: encoding: [0x80,0x12,0x80,0xbe] + +s_bitset1_b32 s0, -1 +// GFX12: encoding: [0xc1,0x12,0x80,0xbe] + +s_bitset1_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x12,0x80,0xbe] + +s_bitset1_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x12,0x80,0xbe] + +s_bitset1_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x12,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_bitset1_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x12,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_bitset1_b64 s[0:1], s2 +// GFX12: encoding: [0x02,0x13,0x80,0xbe] + +s_bitset1_b64 s[104:105], s102 +// GFX12: encoding: [0x66,0x13,0xe8,0xbe] + +s_bitset1_b64 s[0:1], s102 +// GFX12: encoding: [0x66,0x13,0x80,0xbe] + +s_bitset1_b64 s[104:105], s2 +// GFX12: encoding: [0x02,0x13,0xe8,0xbe] + +s_bitset1_b64 exec, s2 +// GFX12: encoding: [0x02,0x13,0xfe,0xbe] + +s_bitset1_b64 vcc, s2 +// GFX12: encoding: [0x02,0x13,0xea,0xbe] + +s_bitset1_b64 s[0:1], exec_lo +// GFX12: encoding: [0x7e,0x13,0x80,0xbe] + +s_bitset1_b64 s[0:1], exec_hi +// GFX12: encoding: [0x7f,0x13,0x80,0xbe] + +s_bitset1_b64 s[0:1], vcc_lo +// GFX12: encoding: [0x6a,0x13,0x80,0xbe] + +s_bitset1_b64 s[0:1], vcc_hi +// GFX12: encoding: [0x6b,0x13,0x80,0xbe] + +s_bitset1_b64 s[0:1], m0 +// GFX12: encoding: [0x7d,0x13,0x80,0xbe] + +s_bitset1_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x13,0x80,0xbe] + +s_bitset1_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x13,0x80,0xbe] + +s_bitset1_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x13,0x80,0xbe] + +s_bitset1_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x13,0x80,0xbe] + +s_bitset1_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x13,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_bitset1_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x13,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_getpc_b64 s[0:1] +// GFX12: encoding: [0x00,0x47,0x80,0xbe] + +s_getpc_b64 s[104:105] +// GFX12: encoding: [0x00,0x47,0xe8,0xbe] + +s_getpc_b64 exec +// GFX12: encoding: [0x00,0x47,0xfe,0xbe] + +s_getpc_b64 vcc +// GFX12: encoding: [0x00,0x47,0xea,0xbe] + +s_setpc_b64 s[0:1] +// GFX12: encoding: [0x00,0x48,0x80,0xbe] + +s_setpc_b64 s[104:105] +// GFX12: encoding: [0x68,0x48,0x80,0xbe] + +s_setpc_b64 vcc +// GFX12: encoding: [0x6a,0x48,0x80,0xbe] + +s_swappc_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x49,0x80,0xbe] + +s_swappc_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x49,0xe8,0xbe] + +s_swappc_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x49,0x80,0xbe] + +s_swappc_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x49,0xe8,0xbe] + +s_swappc_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x49,0xea,0xbe] + +s_swappc_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x49,0x80,0xbe] + +s_rfe_b64 s[0:1] +// GFX12: encoding: [0x00,0x4a,0x80,0xbe] + +s_rfe_b64 s[104:105] +// GFX12: encoding: [0x68,0x4a,0x80,0xbe] + +s_rfe_b64 vcc +// GFX12: encoding: [0x6a,0x4a,0x80,0xbe] + +s_and_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x21,0x80,0xbe] + +s_and_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x21,0xe8,0xbe] + +s_and_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x21,0x80,0xbe] + +s_and_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x21,0xe8,0xbe] + +s_and_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x21,0xea,0xbe] + +s_and_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x21,0x80,0xbe] + +s_and_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x21,0x80,0xbe] + +s_and_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x21,0x80,0xbe] + +s_and_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x21,0x80,0xbe] + +s_and_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x21,0x80,0xbe] + +s_and_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x21,0x80,0xbe] + +s_and_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x21,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_and_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_or_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x23,0x80,0xbe] + +s_or_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x23,0xe8,0xbe] + +s_or_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x23,0x80,0xbe] + +s_or_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x23,0xe8,0xbe] + +s_or_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x23,0xea,0xbe] + +s_or_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x23,0x80,0xbe] + +s_or_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x23,0x80,0xbe] + +s_or_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x23,0x80,0xbe] + +s_or_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x23,0x80,0xbe] + +s_or_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x23,0x80,0xbe] + +s_or_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x23,0x80,0xbe] + +s_or_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x23,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_or_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_xor_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x25,0x80,0xbe] + +s_xor_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x25,0xe8,0xbe] + +s_xor_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x25,0x80,0xbe] + +s_xor_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x25,0xe8,0xbe] + +s_xor_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x25,0xea,0xbe] + +s_xor_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x25,0x80,0xbe] + +s_xor_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x25,0x80,0xbe] + +s_xor_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x25,0x80,0xbe] + +s_xor_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x25,0x80,0xbe] + +s_xor_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x25,0x80,0xbe] + +s_xor_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x25,0x80,0xbe] + +s_xor_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x25,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_xor_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_andn2_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x31,0x80,0xbe] + +s_andn2_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x31,0xe8,0xbe] + +s_andn2_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x31,0x80,0xbe] + +s_andn2_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x31,0xe8,0xbe] + +s_andn2_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x31,0xea,0xbe] + +s_andn2_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x31,0x80,0xbe] + +s_andn2_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x31,0x80,0xbe] + +s_andn2_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x31,0x80,0xbe] + +s_andn2_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x31,0x80,0xbe] + +s_andn2_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x31,0x80,0xbe] + +s_andn2_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x31,0x80,0xbe] + +s_andn2_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x31,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_andn2_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_orn2_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x33,0x80,0xbe] + +s_orn2_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x33,0xe8,0xbe] + +s_orn2_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x33,0x80,0xbe] + +s_orn2_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x33,0xe8,0xbe] + +s_orn2_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x33,0xea,0xbe] + +s_orn2_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x33,0x80,0xbe] + +s_orn2_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x33,0x80,0xbe] + +s_orn2_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x33,0x80,0xbe] + +s_orn2_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x33,0x80,0xbe] + +s_orn2_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x33,0x80,0xbe] + +s_orn2_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x33,0x80,0xbe] + +s_orn2_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x33,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_orn2_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_nand_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x27,0x80,0xbe] + +s_nand_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x27,0xe8,0xbe] + +s_nand_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x27,0x80,0xbe] + +s_nand_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x27,0xe8,0xbe] + +s_nand_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x27,0xea,0xbe] + +s_nand_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x27,0x80,0xbe] + +s_nand_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x27,0x80,0xbe] + +s_nand_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x27,0x80,0xbe] + +s_nand_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x27,0x80,0xbe] + +s_nand_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x27,0x80,0xbe] + +s_nand_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x27,0x80,0xbe] + +s_nand_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x27,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_nand_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_nor_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x29,0x80,0xbe] + +s_nor_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x29,0xe8,0xbe] + +s_nor_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x29,0x80,0xbe] + +s_nor_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x29,0xe8,0xbe] + +s_nor_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x29,0xea,0xbe] + +s_nor_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x29,0x80,0xbe] + +s_nor_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x29,0x80,0xbe] + +s_nor_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x29,0x80,0xbe] + +s_nor_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x29,0x80,0xbe] + +s_nor_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x29,0x80,0xbe] + +s_nor_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x29,0x80,0xbe] + +s_nor_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x29,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_nor_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_xnor_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x2b,0x80,0xbe] + +s_xnor_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x2b,0xe8,0xbe] + +s_xnor_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x2b,0x80,0xbe] + +s_xnor_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x2b,0xe8,0xbe] + +s_xnor_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x2b,0xea,0xbe] + +s_xnor_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x2b,0x80,0xbe] + +s_xnor_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x2b,0x80,0xbe] + +s_xnor_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x2b,0x80,0xbe] + +s_xnor_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x2b,0x80,0xbe] + +s_xnor_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x2b,0x80,0xbe] + +s_xnor_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x2b,0x80,0xbe] + +s_xnor_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x2b,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_xnor_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_quadmask_b32 s0, s1 +// GFX12: encoding: [0x01,0x1a,0x80,0xbe] + +s_quadmask_b32 s105, s104 +// GFX12: encoding: [0x68,0x1a,0xe9,0xbe] + +s_quadmask_b32 s0, s104 +// GFX12: encoding: [0x68,0x1a,0x80,0xbe] + +s_quadmask_b32 s105, s1 +// GFX12: encoding: [0x01,0x1a,0xe9,0xbe] + +s_quadmask_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x1a,0xfe,0xbe] + +s_quadmask_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x1a,0xff,0xbe] + +s_quadmask_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x1a,0xea,0xbe] + +s_quadmask_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x1a,0xeb,0xbe] + +s_quadmask_b32 m0, s1 +// GFX12: encoding: [0x01,0x1a,0xfd,0xbe] + +s_quadmask_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x1a,0x80,0xbe] + +s_quadmask_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x1a,0x80,0xbe] + +s_quadmask_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x1a,0x80,0xbe] + +s_quadmask_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x1a,0x80,0xbe] + +s_quadmask_b32 s0, m0 +// GFX12: encoding: [0x7d,0x1a,0x80,0xbe] + +s_quadmask_b32 s0, 0 +// GFX12: encoding: [0x80,0x1a,0x80,0xbe] + +s_quadmask_b32 s0, -1 +// GFX12: encoding: [0xc1,0x1a,0x80,0xbe] + +s_quadmask_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x1a,0x80,0xbe] + +s_quadmask_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x1a,0x80,0xbe] + +s_quadmask_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x1a,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_quadmask_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x1a,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_quadmask_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x1b,0x80,0xbe] + +s_quadmask_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x1b,0xe8,0xbe] + +s_quadmask_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x1b,0x80,0xbe] + +s_quadmask_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x1b,0xe8,0xbe] + +s_quadmask_b64 exec, s[2:3] +// GFX12: encoding: [0x02,0x1b,0xfe,0xbe] + +s_quadmask_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x1b,0xea,0xbe] + +s_quadmask_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x1b,0x80,0xbe] + +s_quadmask_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x1b,0x80,0xbe] + +s_quadmask_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x1b,0x80,0xbe] + +s_quadmask_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x1b,0x80,0xbe] + +s_quadmask_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x1b,0x80,0xbe] + +s_quadmask_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x1b,0x80,0xbe] + +s_quadmask_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x1b,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_quadmask_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_movrels_b32 s0, s1 +// GFX12: encoding: [0x01,0x40,0x80,0xbe] + +s_movrels_b32 s105, s104 +// GFX12: encoding: [0x68,0x40,0xe9,0xbe] + +s_movrels_b32 s0, s104 +// GFX12: encoding: [0x68,0x40,0x80,0xbe] + +s_movrels_b32 s105, s1 +// GFX12: encoding: [0x01,0x40,0xe9,0xbe] + +s_movrels_b32 exec_lo, s1 +// GFX12: encoding: [0x01,0x40,0xfe,0xbe] + +s_movrels_b32 exec_hi, s1 +// GFX12: encoding: [0x01,0x40,0xff,0xbe] + +s_movrels_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x40,0xea,0xbe] + +s_movrels_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x40,0xeb,0xbe] + +s_movrels_b32 m0, s1 +// GFX12: encoding: [0x01,0x40,0xfd,0xbe] + +s_movrels_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x40,0x80,0xbe] + +s_movrels_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x40,0x80,0xbe] + +s_movrels_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x41,0x80,0xbe] + +s_movrels_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x41,0xe8,0xbe] + +s_movrels_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x41,0x80,0xbe] + +s_movrels_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x41,0xe8,0xbe] + +s_movrels_b64 exec, s[2:3] +// GFX12: encoding: [0x02,0x41,0xfe,0xbe] + +s_movrels_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x41,0xea,0xbe] + +s_movrels_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x41,0x80,0xbe] + +s_movreld_b32 s0, s1 +// GFX12: encoding: [0x01,0x42,0x80,0xbe] + +s_movreld_b32 s105, s104 +// GFX12: encoding: [0x68,0x42,0xe9,0xbe] + +s_movreld_b32 s0, s104 +// GFX12: encoding: [0x68,0x42,0x80,0xbe] + +s_movreld_b32 s105, s1 +// GFX12: encoding: [0x01,0x42,0xe9,0xbe] + +s_movreld_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x42,0xea,0xbe] + +s_movreld_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x42,0xeb,0xbe] + +s_movreld_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x42,0x80,0xbe] + +s_movreld_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x42,0x80,0xbe] + +s_movreld_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x42,0x80,0xbe] + +s_movreld_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x42,0x80,0xbe] + +s_movreld_b32 s0, m0 +// GFX12: encoding: [0x7d,0x42,0x80,0xbe] + +s_movreld_b32 s0, 0 +// GFX12: encoding: [0x80,0x42,0x80,0xbe] + +s_movreld_b32 s0, -1 +// GFX12: encoding: [0xc1,0x42,0x80,0xbe] + +s_movreld_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x42,0x80,0xbe] + +s_movreld_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x42,0x80,0xbe] + +s_movreld_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x42,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_movreld_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x42,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_movreld_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x43,0x80,0xbe] + +s_movreld_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x43,0xe8,0xbe] + +s_movreld_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x43,0x80,0xbe] + +s_movreld_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x43,0xe8,0xbe] + +s_movreld_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x43,0xea,0xbe] + +s_movreld_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x43,0x80,0xbe] + +s_movreld_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x43,0x80,0xbe] + +s_movreld_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x43,0x80,0xbe] + +s_movreld_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x43,0x80,0xbe] + +s_movreld_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x43,0x80,0xbe] + +s_movreld_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x43,0x80,0xbe] + +s_movreld_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x43,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_movreld_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_abs_i32 s0, s1 +// GFX12: encoding: [0x01,0x15,0x80,0xbe] + +s_abs_i32 s105, s104 +// GFX12: encoding: [0x68,0x15,0xe9,0xbe] + +s_abs_i32 s0, s104 +// GFX12: encoding: [0x68,0x15,0x80,0xbe] + +s_abs_i32 s105, s1 +// GFX12: encoding: [0x01,0x15,0xe9,0xbe] + +s_abs_i32 exec_lo, s1 +// GFX12: encoding: [0x01,0x15,0xfe,0xbe] + +s_abs_i32 exec_hi, s1 +// GFX12: encoding: [0x01,0x15,0xff,0xbe] + +s_abs_i32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x15,0xea,0xbe] + +s_abs_i32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x15,0xeb,0xbe] + +s_abs_i32 m0, s1 +// GFX12: encoding: [0x01,0x15,0xfd,0xbe] + +s_abs_i32 s0, exec_lo +// GFX12: encoding: [0x7e,0x15,0x80,0xbe] + +s_abs_i32 s0, exec_hi +// GFX12: encoding: [0x7f,0x15,0x80,0xbe] + +s_abs_i32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x15,0x80,0xbe] + +s_abs_i32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x15,0x80,0xbe] + +s_abs_i32 s0, m0 +// GFX12: encoding: [0x7d,0x15,0x80,0xbe] + +s_abs_i32 s0, 0 +// GFX12: encoding: [0x80,0x15,0x80,0xbe] + +s_abs_i32 s0, -1 +// GFX12: encoding: [0xc1,0x15,0x80,0xbe] + +s_abs_i32 s0, 0.5 +// GFX12: encoding: [0xf0,0x15,0x80,0xbe] + +s_abs_i32 s0, -4.0 +// GFX12: encoding: [0xf7,0x15,0x80,0xbe] + +s_abs_i32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x15,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_abs_i32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x15,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_andn1_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x2d,0x80,0xbe] + +s_andn1_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x2d,0xe8,0xbe] + +s_andn1_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x2d,0x80,0xbe] + +s_andn1_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x2d,0xe8,0xbe] + +s_andn1_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x2d,0xea,0xbe] + +s_andn1_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x2d,0x80,0xbe] + +s_andn1_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x2d,0x80,0xbe] + +s_andn1_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x2d,0x80,0xbe] + +s_andn1_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x2d,0x80,0xbe] + +s_andn1_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x2d,0x80,0xbe] + +s_andn1_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x2d,0x80,0xbe] + +s_andn1_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x2d,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_andn1_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_orn1_saveexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x2f,0x80,0xbe] + +s_orn1_saveexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x2f,0xe8,0xbe] + +s_orn1_saveexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x2f,0x80,0xbe] + +s_orn1_saveexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x2f,0xe8,0xbe] + +s_orn1_saveexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x2f,0xea,0xbe] + +s_orn1_saveexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x2f,0x80,0xbe] + +s_orn1_saveexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x2f,0x80,0xbe] + +s_orn1_saveexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x2f,0x80,0xbe] + +s_orn1_saveexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x2f,0x80,0xbe] + +s_orn1_saveexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x2f,0x80,0xbe] + +s_orn1_saveexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x2f,0x80,0xbe] + +s_orn1_saveexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x2f,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_orn1_saveexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_andn1_wrexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x35,0x80,0xbe] + +s_andn1_wrexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x35,0xe8,0xbe] + +s_andn1_wrexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x35,0x80,0xbe] + +s_andn1_wrexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x35,0xe8,0xbe] + +s_andn1_wrexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x35,0xea,0xbe] + +s_andn1_wrexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x35,0x80,0xbe] + +s_andn1_wrexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x35,0x80,0xbe] + +s_andn1_wrexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x35,0x80,0xbe] + +s_andn1_wrexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x35,0x80,0xbe] + +s_andn1_wrexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x35,0x80,0xbe] + +s_andn1_wrexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x35,0x80,0xbe] + +s_andn1_wrexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x35,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_andn1_wrexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_andn2_wrexec_b64 s[0:1], s[2:3] +// GFX12: encoding: [0x02,0x37,0x80,0xbe] + +s_andn2_wrexec_b64 s[104:105], s[102:103] +// GFX12: encoding: [0x66,0x37,0xe8,0xbe] + +s_andn2_wrexec_b64 s[0:1], s[102:103] +// GFX12: encoding: [0x66,0x37,0x80,0xbe] + +s_andn2_wrexec_b64 s[104:105], s[2:3] +// GFX12: encoding: [0x02,0x37,0xe8,0xbe] + +s_andn2_wrexec_b64 vcc, s[2:3] +// GFX12: encoding: [0x02,0x37,0xea,0xbe] + +s_andn2_wrexec_b64 s[0:1], exec +// GFX12: encoding: [0x7e,0x37,0x80,0xbe] + +s_andn2_wrexec_b64 s[0:1], vcc +// GFX12: encoding: [0x6a,0x37,0x80,0xbe] + +s_andn2_wrexec_b64 s[0:1], 0 +// GFX12: encoding: [0x80,0x37,0x80,0xbe] + +s_andn2_wrexec_b64 s[0:1], -1 +// GFX12: encoding: [0xc1,0x37,0x80,0xbe] + +s_andn2_wrexec_b64 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x37,0x80,0xbe] + +s_andn2_wrexec_b64 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x37,0x80,0xbe] + +s_andn2_wrexec_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x37,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_andn2_wrexec_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_bitreplicate_b64_b32 s[0:1], s2 +// GFX12: encoding: [0x02,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[104:105], s102 +// GFX12: encoding: [0x66,0x14,0xe8,0xbe] + +s_bitreplicate_b64_b32 s[0:1], s102 +// GFX12: encoding: [0x66,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[104:105], s2 +// GFX12: encoding: [0x02,0x14,0xe8,0xbe] + +s_bitreplicate_b64_b32 exec, s2 +// GFX12: encoding: [0x02,0x14,0xfe,0xbe] + +s_bitreplicate_b64_b32 vcc, s2 +// GFX12: encoding: [0x02,0x14,0xea,0xbe] + +s_bitreplicate_b64_b32 s[0:1], exec_lo +// GFX12: encoding: [0x7e,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[0:1], exec_hi +// GFX12: encoding: [0x7f,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[0:1], vcc_lo +// GFX12: encoding: [0x6a,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[0:1], vcc_hi +// GFX12: encoding: [0x6b,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[0:1], m0 +// GFX12: encoding: [0x7d,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[0:1], 0 +// GFX12: encoding: [0x80,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[0:1], -1 +// GFX12: encoding: [0xc1,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[0:1], 0.5 +// GFX12: encoding: [0xf0,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[0:1], -4.0 +// GFX12: encoding: [0xf7,0x14,0x80,0xbe] + +s_bitreplicate_b64_b32 s[0:1], 0x3f717273 +// GFX12: encoding: [0xff,0x14,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_bitreplicate_b64_b32 s[0:1], 0xaf123456 +// GFX12: encoding: [0xff,0x14,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_and_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x20,0x80,0xbe] + +s_and_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x20,0xe9,0xbe] + +s_and_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x20,0x80,0xbe] + +s_and_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x20,0xe9,0xbe] + +s_and_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x20,0xea,0xbe] + +s_and_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x20,0xeb,0xbe] + +s_and_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x20,0x80,0xbe] + +s_and_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x20,0x80,0xbe] + +s_and_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x20,0x80,0xbe] + +s_and_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x20,0x80,0xbe] + +s_and_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x20,0x80,0xbe] + +s_and_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x20,0x80,0xbe] + +s_and_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x20,0x80,0xbe] + +s_and_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x20,0x80,0xbe] + +s_and_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x20,0x80,0xbe] + +s_and_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x20,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_and_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x20,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_or_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x22,0x80,0xbe] + +s_or_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x22,0xe9,0xbe] + +s_or_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x22,0x80,0xbe] + +s_or_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x22,0xe9,0xbe] + +s_or_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x22,0xea,0xbe] + +s_or_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x22,0xeb,0xbe] + +s_or_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x22,0x80,0xbe] + +s_or_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x22,0x80,0xbe] + +s_or_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x22,0x80,0xbe] + +s_or_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x22,0x80,0xbe] + +s_or_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x22,0x80,0xbe] + +s_or_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x22,0x80,0xbe] + +s_or_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x22,0x80,0xbe] + +s_or_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x22,0x80,0xbe] + +s_or_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x22,0x80,0xbe] + +s_or_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x22,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_or_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x22,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_xor_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x24,0xe9,0xbe] + +s_xor_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x24,0xe9,0xbe] + +s_xor_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x24,0xea,0xbe] + +s_xor_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x24,0xeb,0xbe] + +s_xor_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x24,0x80,0xbe] + +s_xor_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x24,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_xor_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x24,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_andn2_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x30,0xe9,0xbe] + +s_andn2_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x30,0xe9,0xbe] + +s_andn2_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x30,0xea,0xbe] + +s_andn2_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x30,0xeb,0xbe] + +s_andn2_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x30,0x80,0xbe] + +s_andn2_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x30,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_andn2_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x30,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_orn2_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x32,0xe9,0xbe] + +s_orn2_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x32,0xe9,0xbe] + +s_orn2_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x32,0xea,0xbe] + +s_orn2_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x32,0xeb,0xbe] + +s_orn2_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x32,0x80,0xbe] + +s_orn2_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x32,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_orn2_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x32,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_nand_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x26,0xe9,0xbe] + +s_nand_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x26,0xe9,0xbe] + +s_nand_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x26,0xea,0xbe] + +s_nand_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x26,0xeb,0xbe] + +s_nand_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x26,0x80,0xbe] + +s_nand_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x26,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_nand_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x26,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_nor_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x28,0xe9,0xbe] + +s_nor_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x28,0xe9,0xbe] + +s_nor_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x28,0xea,0xbe] + +s_nor_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x28,0xeb,0xbe] + +s_nor_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x28,0x80,0xbe] + +s_nor_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x28,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_nor_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x28,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_xnor_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x2a,0xe9,0xbe] + +s_xnor_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x2a,0xe9,0xbe] + +s_xnor_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x2a,0xea,0xbe] + +s_xnor_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x2a,0xeb,0xbe] + +s_xnor_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x2a,0x80,0xbe] + +s_xnor_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x2a,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_xnor_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x2a,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_andn1_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x2c,0xe9,0xbe] + +s_andn1_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x2c,0xe9,0xbe] + +s_andn1_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x2c,0xea,0xbe] + +s_andn1_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x2c,0xeb,0xbe] + +s_andn1_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x2c,0x80,0xbe] + +s_andn1_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x2c,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_andn1_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x2c,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_orn1_saveexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x2e,0xe9,0xbe] + +s_orn1_saveexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x2e,0xe9,0xbe] + +s_orn1_saveexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x2e,0xea,0xbe] + +s_orn1_saveexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x2e,0xeb,0xbe] + +s_orn1_saveexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x2e,0x80,0xbe] + +s_orn1_saveexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x2e,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_orn1_saveexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x2e,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_andn1_wrexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x34,0xe9,0xbe] + +s_andn1_wrexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x34,0xe9,0xbe] + +s_andn1_wrexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x34,0xea,0xbe] + +s_andn1_wrexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x34,0xeb,0xbe] + +s_andn1_wrexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x34,0x80,0xbe] + +s_andn1_wrexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x34,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_andn1_wrexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x34,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_andn2_wrexec_b32 s0, s1 +// GFX12: encoding: [0x01,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s105, s104 +// GFX12: encoding: [0x68,0x36,0xe9,0xbe] + +s_andn2_wrexec_b32 s0, s104 +// GFX12: encoding: [0x68,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s105, s1 +// GFX12: encoding: [0x01,0x36,0xe9,0xbe] + +s_andn2_wrexec_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x36,0xea,0xbe] + +s_andn2_wrexec_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x36,0xeb,0xbe] + +s_andn2_wrexec_b32 s0, exec_lo +// GFX12: encoding: [0x7e,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s0, exec_hi +// GFX12: encoding: [0x7f,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s0, m0 +// GFX12: encoding: [0x7d,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s0, 0 +// GFX12: encoding: [0x80,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s0, -1 +// GFX12: encoding: [0xc1,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s0, 0.5 +// GFX12: encoding: [0xf0,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s0, -4.0 +// GFX12: encoding: [0xf7,0x36,0x80,0xbe] + +s_andn2_wrexec_b32 s0, 0x3f717273 +// GFX12: encoding: [0xff,0x36,0x80,0xbe,0x73,0x72,0x71,0x3f] + +s_andn2_wrexec_b32 s0, 0xaf123456 +// GFX12: encoding: [0xff,0x36,0x80,0xbe,0x56,0x34,0x12,0xaf] + +s_movrelsd_2_b32 s0, s1 +// GFX12: encoding: [0x01,0x44,0x80,0xbe] + +s_movrelsd_2_b32 s105, s104 +// GFX12: encoding: [0x68,0x44,0xe9,0xbe] + +s_movrelsd_2_b32 s0, s104 +// GFX12: encoding: [0x68,0x44,0x80,0xbe] + +s_movrelsd_2_b32 s105, s1 +// GFX12: encoding: [0x01,0x44,0xe9,0xbe] + +s_movrelsd_2_b32 vcc_lo, s1 +// GFX12: encoding: [0x01,0x44,0xea,0xbe] + +s_movrelsd_2_b32 vcc_hi, s1 +// GFX12: encoding: [0x01,0x44,0xeb,0xbe] + +s_movrelsd_2_b32 s0, vcc_lo +// GFX12: encoding: [0x6a,0x44,0x80,0xbe] + +s_movrelsd_2_b32 s0, vcc_hi +// GFX12: encoding: [0x6b,0x44,0x80,0xbe] + +s_sendmsg_rtn_b32 s1, 0x0 +// GFX12: encoding: [0x00,0x4c,0x81,0xbe] + +s_sendmsg_rtn_b32 s2, 0x12 +// GFX12: encoding: [0x12,0x4c,0x82,0xbe] + +s_sendmsg_rtn_b32 s3, 0xff +// GFX12: encoding: [0xff,0x4c,0x83,0xbe] + +s_sendmsg_rtn_b64 s[0:1], 0x0 +// GFX12: encoding: [0x00,0x4d,0x80,0xbe] + +s_sendmsg_rtn_b64 s[2:3], 0x12 +// GFX12: encoding: [0x12,0x4d,0x82,0xbe] + +s_sendmsg_rtn_b64 s[4:5], 0xff +// GFX12: encoding: [0xff,0x4d,0x84,0xbe] + +s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL) +// GFX12: encoding: [0x80,0x4c,0x80,0xbe] + +s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DDID) +// GFX12: encoding: [0x81,0x4c,0x80,0xbe] + +s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_TMA) +// GFX12: encoding: [0x82,0x4c,0x80,0xbe] + +s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_REALTIME) +// GFX12: encoding: [0x83,0x4c,0x80,0xbe] + +s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_SAVE_WAVE) +// GFX12: encoding: [0x84,0x4c,0x80,0xbe] + +s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_TBA) +// GFX12: encoding: [0x85,0x4c,0x80,0xbe] + +s_ctz_i32_b32 s5, s1 +// GFX12: encoding: [0x01,0x08,0x85,0xbe] + +s_ctz_i32_b32 s5, s105 +// GFX12: encoding: [0x69,0x08,0x85,0xbe] + +s_ctz_i32_b32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x08,0x85,0xbe] + +s_ctz_i32_b32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x08,0x85,0xbe] + +s_ctz_i32_b32 s5, ttmp15 +// GFX12: encoding: [0x7b,0x08,0x85,0xbe] + +s_ctz_i32_b32 s105, m0 +// GFX12: encoding: [0x7d,0x08,0xe9,0xbe] + +s_ctz_i32_b32 vcc_lo, exec_lo +// GFX12: encoding: [0x7e,0x08,0xea,0xbe] + +s_ctz_i32_b32 vcc_hi, exec_hi +// GFX12: encoding: [0x7f,0x08,0xeb,0xbe] + +s_ctz_i32_b32 ttmp15, null +// GFX12: encoding: [0x7c,0x08,0xfb,0xbe] + +s_ctz_i32_b32 m0, -1 +// GFX12: encoding: [0xc1,0x08,0xfd,0xbe] + +s_ctz_i32_b32 exec_lo, 0.5 +// GFX12: encoding: [0xf0,0x08,0xfe,0xbe] + +s_ctz_i32_b32 exec_hi, src_scc +// GFX12: encoding: [0xfd,0x08,0xff,0xbe] + +s_ctz_i32_b32 null, 0xaf123456 +// GFX12: encoding: [0xff,0x08,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_ctz_i32_b64 s5, s[2:3] +// GFX12: encoding: [0x02,0x09,0x85,0xbe] + +s_ctz_i32_b64 s5, s[104:105] +// GFX12: encoding: [0x68,0x09,0x85,0xbe] + +s_ctz_i32_b64 s105, vcc +// GFX12: encoding: [0x6a,0x09,0xe9,0xbe] + +s_ctz_i32_b64 vcc_lo, ttmp[14:15] +// GFX12: encoding: [0x7a,0x09,0xea,0xbe] + +s_ctz_i32_b64 vcc_hi, exec +// GFX12: encoding: [0x7e,0x09,0xeb,0xbe] + +s_ctz_i32_b64 ttmp15, null +// GFX12: encoding: [0x7c,0x09,0xfb,0xbe] + +s_ctz_i32_b64 m0, -1 +// GFX12: encoding: [0xc1,0x09,0xfd,0xbe] + +s_ctz_i32_b64 exec_lo, 0.5 +// GFX12: encoding: [0xf0,0x09,0xfe,0xbe] + +s_ctz_i32_b64 exec_hi, src_scc +// GFX12: encoding: [0xfd,0x09,0xff,0xbe] + +s_ctz_i32_b64 null, 0xaf123456 +// GFX12: encoding: [0xff,0x09,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_and_not1_saveexec_b64 s[10:11], s[2:3] +// GFX12: encoding: [0x02,0x31,0x8a,0xbe] + +s_and_not1_saveexec_b64 s[10:11], s[104:105] +// GFX12: encoding: [0x68,0x31,0x8a,0xbe] + +s_and_not1_saveexec_b64 s[10:11], vcc +// GFX12: encoding: [0x6a,0x31,0x8a,0xbe] + +s_and_not1_saveexec_b64 s[10:11], ttmp[14:15] +// GFX12: encoding: [0x7a,0x31,0x8a,0xbe] + +s_and_not1_saveexec_b64 s[10:11], null +// GFX12: encoding: [0x7c,0x31,0x8a,0xbe] + +s_and_not1_saveexec_b64 s[104:105], -1 +// GFX12: encoding: [0xc1,0x31,0xe8,0xbe] + +s_and_not1_saveexec_b64 vcc, 0.5 +// GFX12: encoding: [0xf0,0x31,0xea,0xbe] + +s_and_not1_saveexec_b64 ttmp[14:15], src_scc +// GFX12: encoding: [0xfd,0x31,0xfa,0xbe] + +s_and_not1_saveexec_b64 null, 0xaf123456 +// GFX12: encoding: [0xff,0x31,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_and_not0_saveexec_b32 s5, s1 +// GFX12: encoding: [0x01,0x2c,0x85,0xbe] + +s_and_not0_saveexec_b32 s5, s105 +// GFX12: encoding: [0x69,0x2c,0x85,0xbe] + +s_and_not0_saveexec_b32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x2c,0x85,0xbe] + +s_and_not0_saveexec_b32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x2c,0x85,0xbe] + +s_and_not0_saveexec_b32 s5, ttmp15 +// GFX12: encoding: [0x7b,0x2c,0x85,0xbe] + +s_and_not0_saveexec_b32 s5, exec_lo +// GFX12: encoding: [0x7e,0x2c,0x85,0xbe] + +s_and_not0_saveexec_b32 s105, null +// GFX12: encoding: [0x7c,0x2c,0xe9,0xbe] + +s_and_not0_saveexec_b32 vcc_lo, -1 +// GFX12: encoding: [0xc1,0x2c,0xea,0xbe] + +s_and_not0_saveexec_b32 vcc_hi, 0.5 +// GFX12: encoding: [0xf0,0x2c,0xeb,0xbe] + +s_and_not0_saveexec_b32 ttmp15, src_scc +// GFX12: encoding: [0xfd,0x2c,0xfb,0xbe] + +s_and_not0_saveexec_b32 null, 0xaf123456 +// GFX12: encoding: [0xff,0x2c,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_and_not0_saveexec_b64 s[10:11], s[2:3] +// GFX12: encoding: [0x02,0x2d,0x8a,0xbe] + +s_and_not0_saveexec_b64 s[10:11], s[104:105] +// GFX12: encoding: [0x68,0x2d,0x8a,0xbe] + +s_and_not0_saveexec_b64 s[10:11], vcc +// GFX12: encoding: [0x6a,0x2d,0x8a,0xbe] + +s_and_not0_saveexec_b64 s[10:11], ttmp[14:15] +// GFX12: encoding: [0x7a,0x2d,0x8a,0xbe] + +s_and_not0_saveexec_b64 s[10:11], null +// GFX12: encoding: [0x7c,0x2d,0x8a,0xbe] + +s_and_not0_saveexec_b64 s[104:105], -1 +// GFX12: encoding: [0xc1,0x2d,0xe8,0xbe] + +s_and_not0_saveexec_b64 vcc, 0.5 +// GFX12: encoding: [0xf0,0x2d,0xea,0xbe] + +s_and_not0_saveexec_b64 ttmp[14:15], src_scc +// GFX12: encoding: [0xfd,0x2d,0xfa,0xbe] + +s_and_not0_saveexec_b64 null, 0xaf123456 +// GFX12: encoding: [0xff,0x2d,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_and_not0_wrexec_b32 s5, s1 +// GFX12: encoding: [0x01,0x34,0x85,0xbe] + +s_and_not0_wrexec_b32 s5, s105 +// GFX12: encoding: [0x69,0x34,0x85,0xbe] + +s_and_not0_wrexec_b32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x34,0x85,0xbe] + +s_and_not0_wrexec_b32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x34,0x85,0xbe] + +s_and_not0_wrexec_b32 s5, ttmp15 +// GFX12: encoding: [0x7b,0x34,0x85,0xbe] + +s_and_not0_wrexec_b32 s5, exec_lo +// GFX12: encoding: [0x7e,0x34,0x85,0xbe] + +s_and_not0_wrexec_b32 s105, null +// GFX12: encoding: [0x7c,0x34,0xe9,0xbe] + +s_and_not0_wrexec_b32 vcc_lo, -1 +// GFX12: encoding: [0xc1,0x34,0xea,0xbe] + +s_and_not0_wrexec_b32 vcc_hi, 0.5 +// GFX12: encoding: [0xf0,0x34,0xeb,0xbe] + +s_and_not0_wrexec_b32 ttmp15, src_scc +// GFX12: encoding: [0xfd,0x34,0xfb,0xbe] + +s_and_not0_wrexec_b32 null, 0xaf123456 +// GFX12: encoding: [0xff,0x34,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_and_not0_wrexec_b64 s[10:11], s[2:3] +// GFX12: encoding: [0x02,0x35,0x8a,0xbe] + +s_and_not0_wrexec_b64 s[10:11], s[104:105] +// GFX12: encoding: [0x68,0x35,0x8a,0xbe] + +s_and_not0_wrexec_b64 s[10:11], vcc +// GFX12: encoding: [0x6a,0x35,0x8a,0xbe] + +s_and_not0_wrexec_b64 s[10:11], ttmp[14:15] +// GFX12: encoding: [0x7a,0x35,0x8a,0xbe] + +s_and_not0_wrexec_b64 s[10:11], null +// GFX12: encoding: [0x7c,0x35,0x8a,0xbe] + +s_and_not0_wrexec_b64 s[104:105], -1 +// GFX12: encoding: [0xc1,0x35,0xe8,0xbe] + +s_and_not0_wrexec_b64 vcc, 0.5 +// GFX12: encoding: [0xf0,0x35,0xea,0xbe] + +s_and_not0_wrexec_b64 ttmp[14:15], src_scc +// GFX12: encoding: [0xfd,0x35,0xfa,0xbe] + +s_and_not0_wrexec_b64 null, 0xaf123456 +// GFX12: encoding: [0xff,0x35,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_and_not1_saveexec_b32 s5, s1 +// GFX12: encoding: [0x01,0x30,0x85,0xbe] + +s_and_not1_saveexec_b32 s5, s105 +// GFX12: encoding: [0x69,0x30,0x85,0xbe] + +s_and_not1_saveexec_b32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x30,0x85,0xbe] + +s_and_not1_saveexec_b32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x30,0x85,0xbe] + +s_and_not1_saveexec_b32 s5, ttmp15 +// GFX12: encoding: [0x7b,0x30,0x85,0xbe] + +s_and_not1_saveexec_b32 s5, exec_lo +// GFX12: encoding: [0x7e,0x30,0x85,0xbe] + +s_and_not1_saveexec_b32 s105, null +// GFX12: encoding: [0x7c,0x30,0xe9,0xbe] + +s_and_not1_saveexec_b32 vcc_lo, -1 +// GFX12: encoding: [0xc1,0x30,0xea,0xbe] + +s_and_not1_saveexec_b32 vcc_hi, 0.5 +// GFX12: encoding: [0xf0,0x30,0xeb,0xbe] + +s_and_not1_saveexec_b32 ttmp15, src_scc +// GFX12: encoding: [0xfd,0x30,0xfb,0xbe] + +s_and_not1_saveexec_b32 null, 0xaf123456 +// GFX12: encoding: [0xff,0x30,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_and_not1_wrexec_b32 s5, s1 +// GFX12: encoding: [0x01,0x36,0x85,0xbe] + +s_and_not1_wrexec_b32 s5, s105 +// GFX12: encoding: [0x69,0x36,0x85,0xbe] + +s_and_not1_wrexec_b32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x36,0x85,0xbe] + +s_and_not1_wrexec_b32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x36,0x85,0xbe] + +s_and_not1_wrexec_b32 s5, ttmp15 +// GFX12: encoding: [0x7b,0x36,0x85,0xbe] + +s_and_not1_wrexec_b32 s5, exec_lo +// GFX12: encoding: [0x7e,0x36,0x85,0xbe] + +s_and_not1_wrexec_b32 s105, null +// GFX12: encoding: [0x7c,0x36,0xe9,0xbe] + +s_and_not1_wrexec_b32 vcc_lo, -1 +// GFX12: encoding: [0xc1,0x36,0xea,0xbe] + +s_and_not1_wrexec_b32 vcc_hi, 0.5 +// GFX12: encoding: [0xf0,0x36,0xeb,0xbe] + +s_and_not1_wrexec_b32 ttmp15, src_scc +// GFX12: encoding: [0xfd,0x36,0xfb,0xbe] + +s_and_not1_wrexec_b32 null, 0xaf123456 +// GFX12: encoding: [0xff,0x36,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_and_not1_wrexec_b64 s[10:11], s[2:3] +// GFX12: encoding: [0x02,0x37,0x8a,0xbe] + +s_and_not1_wrexec_b64 s[10:11], s[104:105] +// GFX12: encoding: [0x68,0x37,0x8a,0xbe] + +s_and_not1_wrexec_b64 s[10:11], vcc +// GFX12: encoding: [0x6a,0x37,0x8a,0xbe] + +s_and_not1_wrexec_b64 s[10:11], ttmp[14:15] +// GFX12: encoding: [0x7a,0x37,0x8a,0xbe] + +s_and_not1_wrexec_b64 s[10:11], null +// GFX12: encoding: [0x7c,0x37,0x8a,0xbe] + +s_and_not1_wrexec_b64 s[104:105], -1 +// GFX12: encoding: [0xc1,0x37,0xe8,0xbe] + +s_and_not1_wrexec_b64 vcc, 0.5 +// GFX12: encoding: [0xf0,0x37,0xea,0xbe] + +s_and_not1_wrexec_b64 ttmp[14:15], src_scc +// GFX12: encoding: [0xfd,0x37,0xfa,0xbe] + +s_and_not1_wrexec_b64 null, 0xaf123456 +// GFX12: encoding: [0xff,0x37,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_cls_i32 s5, s1 +// GFX12: encoding: [0x01,0x0c,0x85,0xbe] + +s_cls_i32 s5, s105 +// GFX12: encoding: [0x69,0x0c,0x85,0xbe] + +s_cls_i32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x0c,0x85,0xbe] + +s_cls_i32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x0c,0x85,0xbe] + +s_cls_i32 s5, ttmp15 +// GFX12: encoding: [0x7b,0x0c,0x85,0xbe] + +s_cls_i32 s105, m0 +// GFX12: encoding: [0x7d,0x0c,0xe9,0xbe] + +s_cls_i32 vcc_lo, exec_lo +// GFX12: encoding: [0x7e,0x0c,0xea,0xbe] + +s_cls_i32 vcc_hi, exec_hi +// GFX12: encoding: [0x7f,0x0c,0xeb,0xbe] + +s_cls_i32 ttmp15, null +// GFX12: encoding: [0x7c,0x0c,0xfb,0xbe] + +s_cls_i32 m0, -1 +// GFX12: encoding: [0xc1,0x0c,0xfd,0xbe] + +s_cls_i32 exec_lo, 0.5 +// GFX12: encoding: [0xf0,0x0c,0xfe,0xbe] + +s_cls_i32 exec_hi, src_scc +// GFX12: encoding: [0xfd,0x0c,0xff,0xbe] + +s_cls_i32 null, 0xaf123456 +// GFX12: encoding: [0xff,0x0c,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_cls_i32_i64 s5, s[2:3] +// GFX12: encoding: [0x02,0x0d,0x85,0xbe] + +s_cls_i32_i64 s5, s[104:105] +// GFX12: encoding: [0x68,0x0d,0x85,0xbe] + +s_cls_i32_i64 s105, vcc +// GFX12: encoding: [0x6a,0x0d,0xe9,0xbe] + +s_cls_i32_i64 vcc_lo, ttmp[14:15] +// GFX12: encoding: [0x7a,0x0d,0xea,0xbe] + +s_cls_i32_i64 vcc_hi, exec +// GFX12: encoding: [0x7e,0x0d,0xeb,0xbe] + +s_cls_i32_i64 ttmp15, null +// GFX12: encoding: [0x7c,0x0d,0xfb,0xbe] + +s_cls_i32_i64 m0, -1 +// GFX12: encoding: [0xc1,0x0d,0xfd,0xbe] + +s_cls_i32_i64 exec_lo, 0.5 +// GFX12: encoding: [0xf0,0x0d,0xfe,0xbe] + +s_cls_i32_i64 exec_hi, src_scc +// GFX12: encoding: [0xfd,0x0d,0xff,0xbe] + +s_cls_i32_i64 null, 0xaf123456 +// GFX12: encoding: [0xff,0x0d,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_clz_i32_u32 s5, s1 +// GFX12: encoding: [0x01,0x0a,0x85,0xbe] + +s_clz_i32_u32 s5, s105 +// GFX12: encoding: [0x69,0x0a,0x85,0xbe] + +s_clz_i32_u32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x0a,0x85,0xbe] + +s_clz_i32_u32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x0a,0x85,0xbe] + +s_clz_i32_u32 s5, ttmp15 +// GFX12: encoding: [0x7b,0x0a,0x85,0xbe] + +s_clz_i32_u32 s105, m0 +// GFX12: encoding: [0x7d,0x0a,0xe9,0xbe] + +s_clz_i32_u32 vcc_lo, exec_lo +// GFX12: encoding: [0x7e,0x0a,0xea,0xbe] + +s_clz_i32_u32 vcc_hi, exec_hi +// GFX12: encoding: [0x7f,0x0a,0xeb,0xbe] + +s_clz_i32_u32 ttmp15, null +// GFX12: encoding: [0x7c,0x0a,0xfb,0xbe] + +s_clz_i32_u32 m0, -1 +// GFX12: encoding: [0xc1,0x0a,0xfd,0xbe] + +s_clz_i32_u32 exec_lo, 0.5 +// GFX12: encoding: [0xf0,0x0a,0xfe,0xbe] + +s_clz_i32_u32 exec_hi, src_scc +// GFX12: encoding: [0xfd,0x0a,0xff,0xbe] + +s_clz_i32_u32 null, 0xaf123456 +// GFX12: encoding: [0xff,0x0a,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_clz_i32_u64 s5, s[2:3] +// GFX12: encoding: [0x02,0x0b,0x85,0xbe] + +s_clz_i32_u64 s5, s[104:105] +// GFX12: encoding: [0x68,0x0b,0x85,0xbe] + +s_clz_i32_u64 s105, vcc +// GFX12: encoding: [0x6a,0x0b,0xe9,0xbe] + +s_clz_i32_u64 vcc_lo, ttmp[14:15] +// GFX12: encoding: [0x7a,0x0b,0xea,0xbe] + +s_clz_i32_u64 vcc_hi, exec +// GFX12: encoding: [0x7e,0x0b,0xeb,0xbe] + +s_clz_i32_u64 ttmp15, null +// GFX12: encoding: [0x7c,0x0b,0xfb,0xbe] + +s_clz_i32_u64 m0, -1 +// GFX12: encoding: [0xc1,0x0b,0xfd,0xbe] + +s_clz_i32_u64 exec_lo, 0.5 +// GFX12: encoding: [0xf0,0x0b,0xfe,0xbe] + +s_clz_i32_u64 exec_hi, src_scc +// GFX12: encoding: [0xfd,0x0b,0xff,0xbe] + +s_clz_i32_u64 null, 0xaf123456 +// GFX12: encoding: [0xff,0x0b,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_or_not0_saveexec_b32 s5, s1 +// GFX12: encoding: [0x01,0x2e,0x85,0xbe] + +s_or_not0_saveexec_b32 s5, s105 +// GFX12: encoding: [0x69,0x2e,0x85,0xbe] + +s_or_not0_saveexec_b32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x2e,0x85,0xbe] + +s_or_not0_saveexec_b32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x2e,0x85,0xbe] + +s_or_not0_saveexec_b32 s5, ttmp15 +// GFX12: encoding: [0x7b,0x2e,0x85,0xbe] + +s_or_not0_saveexec_b32 s5, exec_lo +// GFX12: encoding: [0x7e,0x2e,0x85,0xbe] + +s_or_not0_saveexec_b32 s105, null +// GFX12: encoding: [0x7c,0x2e,0xe9,0xbe] + +s_or_not0_saveexec_b32 vcc_lo, -1 +// GFX12: encoding: [0xc1,0x2e,0xea,0xbe] + +s_or_not0_saveexec_b32 vcc_hi, 0.5 +// GFX12: encoding: [0xf0,0x2e,0xeb,0xbe] + +s_or_not0_saveexec_b32 ttmp15, src_scc +// GFX12: encoding: [0xfd,0x2e,0xfb,0xbe] + +s_or_not0_saveexec_b32 null, 0xaf123456 +// GFX12: encoding: [0xff,0x2e,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_or_not0_saveexec_b64 s[10:11], s[2:3] +// GFX12: encoding: [0x02,0x2f,0x8a,0xbe] + +s_or_not0_saveexec_b64 s[10:11], s[104:105] +// GFX12: encoding: [0x68,0x2f,0x8a,0xbe] + +s_or_not0_saveexec_b64 s[10:11], vcc +// GFX12: encoding: [0x6a,0x2f,0x8a,0xbe] + +s_or_not0_saveexec_b64 s[10:11], ttmp[14:15] +// GFX12: encoding: [0x7a,0x2f,0x8a,0xbe] + +s_or_not0_saveexec_b64 s[10:11], null +// GFX12: encoding: [0x7c,0x2f,0x8a,0xbe] + +s_or_not0_saveexec_b64 s[104:105], -1 +// GFX12: encoding: [0xc1,0x2f,0xe8,0xbe] + +s_or_not0_saveexec_b64 vcc, 0.5 +// GFX12: encoding: [0xf0,0x2f,0xea,0xbe] + +s_or_not0_saveexec_b64 ttmp[14:15], src_scc +// GFX12: encoding: [0xfd,0x2f,0xfa,0xbe] + +s_or_not0_saveexec_b64 null, 0xaf123456 +// GFX12: encoding: [0xff,0x2f,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_or_not1_saveexec_b32 s5, s1 +// GFX12: encoding: [0x01,0x32,0x85,0xbe] + +s_or_not1_saveexec_b32 s5, s105 +// GFX12: encoding: [0x69,0x32,0x85,0xbe] + +s_or_not1_saveexec_b32 s5, vcc_lo +// GFX12: encoding: [0x6a,0x32,0x85,0xbe] + +s_or_not1_saveexec_b32 s5, vcc_hi +// GFX12: encoding: [0x6b,0x32,0x85,0xbe] + +s_or_not1_saveexec_b32 s5, ttmp15 +// GFX12: encoding: [0x7b,0x32,0x85,0xbe] + +s_or_not1_saveexec_b32 s5, exec_lo +// GFX12: encoding: [0x7e,0x32,0x85,0xbe] + +s_or_not1_saveexec_b32 s105, null +// GFX12: encoding: [0x7c,0x32,0xe9,0xbe] + +s_or_not1_saveexec_b32 vcc_lo, -1 +// GFX12: encoding: [0xc1,0x32,0xea,0xbe] + +s_or_not1_saveexec_b32 vcc_hi, 0.5 +// GFX12: encoding: [0xf0,0x32,0xeb,0xbe] + +s_or_not1_saveexec_b32 ttmp15, src_scc +// GFX12: encoding: [0xfd,0x32,0xfb,0xbe] + +s_or_not1_saveexec_b32 null, 0xaf123456 +// GFX12: encoding: [0xff,0x32,0xfc,0xbe,0x56,0x34,0x12,0xaf] + +s_or_not1_saveexec_b64 s[10:11], s[2:3] +// GFX12: encoding: [0x02,0x33,0x8a,0xbe] + +s_or_not1_saveexec_b64 s[10:11], s[104:105] +// GFX12: encoding: [0x68,0x33,0x8a,0xbe] + +s_or_not1_saveexec_b64 s[10:11], vcc +// GFX12: encoding: [0x6a,0x33,0x8a,0xbe] + +s_or_not1_saveexec_b64 s[10:11], ttmp[14:15] +// GFX12: encoding: [0x7a,0x33,0x8a,0xbe] + +s_or_not1_saveexec_b64 s[10:11], null +// GFX12: encoding: [0x7c,0x33,0x8a,0xbe] + +s_or_not1_saveexec_b64 s[104:105], -1 +// GFX12: encoding: [0xc1,0x33,0xe8,0xbe] + +s_or_not1_saveexec_b64 vcc, 0.5 +// GFX12: encoding: [0xf0,0x33,0xea,0xbe] + +s_or_not1_saveexec_b64 ttmp[14:15], src_scc +// GFX12: encoding: [0xfd,0x33,0xfa,0xbe] + +s_or_not1_saveexec_b64 null, 0xaf123456 +// GFX12: encoding: [0xff,0x33,0xfc,0xbe,0x56,0x34,0x12,0xaf] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s new file mode 100644 index 000000000000..1a898bebde57 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s @@ -0,0 +1,6097 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck -check-prefix=GFX12 %s + +s_add_nc_u64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0xa9] + +s_add_nc_u64 s[100:101], s[102:103], s[104:105] +// GFX12: encoding: [0x66,0x68,0xe4,0xa9] + +s_add_nc_u64 s[0:1], s[104:105], s[102:103] +// GFX12: encoding: [0x68,0x66,0x80,0xa9] + +s_add_nc_u64 s[104:105], s[0:1], s[102:103] +// GFX12: encoding: [0x00,0x66,0xe8,0xa9] + +s_add_nc_u64 s[104:105], s[102:103], s[2:3] +// GFX12: encoding: [0x66,0x02,0xe8,0xa9] + +s_add_nc_u64 s[104:105], s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0xe8,0xa9] + +s_add_nc_u64 s[0:1], s[102:103], s[2:3] +// GFX12: encoding: [0x66,0x02,0x80,0xa9] + +s_add_nc_u64 s[0:1], s[2:3], s[102:103] +// GFX12: encoding: [0x02,0x66,0x80,0xa9] + +s_add_nc_u64 exec, s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0xfe,0xa9] + +s_add_nc_u64 vcc, s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0xea,0xa9] + +s_add_nc_u64 s[0:1], exec, s[2:3] +// GFX12: encoding: [0x7e,0x02,0x80,0xa9] + +s_add_nc_u64 s[0:1], vcc, s[2:3] +// GFX12: encoding: [0x6a,0x02,0x80,0xa9] + +s_add_nc_u64 s[0:1], 0, s[2:3] +// GFX12: encoding: [0x80,0x02,0x80,0xa9] + +s_add_nc_u64 s[0:1], -1, s[2:3] +// GFX12: encoding: [0xc1,0x02,0x80,0xa9] + +s_add_nc_u64 s[0:1], 0.5, s[2:3] +// GFX12: encoding: [0xf0,0x02,0x80,0xa9] + +s_add_nc_u64 s[0:1], -4.0, s[2:3] +// GFX12: encoding: [0xf7,0x02,0x80,0xa9] + +s_add_nc_u64 s[0:1], 0x3f717273, s[2:3] +// GFX12: encoding: [0xff,0x02,0x80,0xa9,0x73,0x72,0x71,0x3f] + +s_add_nc_u64 s[0:1], 0xaf123456, s[2:3] +// GFX12: encoding: [0xff,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf] + +s_add_nc_u64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0xa9] + +s_add_nc_u64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0xa9] + +s_add_nc_u64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0xa9] + +s_add_nc_u64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0xa9] + +s_add_nc_u64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0xa9] + +s_add_nc_u64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0xa9] + +s_add_nc_u64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0xa9,0x73,0x72,0x71,0x3f] + +s_add_nc_u64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0xa9,0x56,0x34,0x12,0xaf] + +s_sub_nc_u64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x00,0xaa] + +s_sub_nc_u64 s[100:101], s[102:103], s[104:105] +// GFX12: encoding: [0x66,0x68,0x64,0xaa] + +s_sub_nc_u64 s[0:1], s[104:105], s[102:103] +// GFX12: encoding: [0x68,0x66,0x00,0xaa] + +s_sub_nc_u64 s[104:105], s[0:1], s[102:103] +// GFX12: encoding: [0x00,0x66,0x68,0xaa] + +s_sub_nc_u64 s[104:105], s[102:103], s[2:3] +// GFX12: encoding: [0x66,0x02,0x68,0xaa] + +s_sub_nc_u64 s[104:105], s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0x68,0xaa] + +s_sub_nc_u64 s[0:1], s[102:103], s[2:3] +// GFX12: encoding: [0x66,0x02,0x00,0xaa] + +s_sub_nc_u64 s[0:1], s[2:3], s[102:103] +// GFX12: encoding: [0x02,0x66,0x00,0xaa] + +s_sub_nc_u64 exec, s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0x7e,0xaa] + +s_sub_nc_u64 vcc, s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0x6a,0xaa] + +s_sub_nc_u64 s[0:1], exec, s[2:3] +// GFX12: encoding: [0x7e,0x02,0x00,0xaa] + +s_sub_nc_u64 s[0:1], vcc, s[2:3] +// GFX12: encoding: [0x6a,0x02,0x00,0xaa] + +s_sub_nc_u64 s[0:1], 0, s[2:3] +// GFX12: encoding: [0x80,0x02,0x00,0xaa] + +s_sub_nc_u64 s[0:1], -1, s[2:3] +// GFX12: encoding: [0xc1,0x02,0x00,0xaa] + +s_sub_nc_u64 s[0:1], 0.5, s[2:3] +// GFX12: encoding: [0xf0,0x02,0x00,0xaa] + +s_sub_nc_u64 s[0:1], -4.0, s[2:3] +// GFX12: encoding: [0xf7,0x02,0x00,0xaa] + +s_sub_nc_u64 s[0:1], 0x3f717273, s[2:3] +// GFX12: encoding: [0xff,0x02,0x00,0xaa,0x73,0x72,0x71,0x3f] + +s_sub_nc_u64 s[0:1], 0xaf123456, s[2:3] +// GFX12: encoding: [0xff,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf] + +s_sub_nc_u64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x00,0xaa] + +s_sub_nc_u64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x00,0xaa] + +s_sub_nc_u64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x00,0xaa] + +s_sub_nc_u64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x00,0xaa] + +s_sub_nc_u64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x00,0xaa] + +s_sub_nc_u64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x00,0xaa] + +s_sub_nc_u64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x00,0xaa,0x73,0x72,0x71,0x3f] + +s_sub_nc_u64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x00,0xaa,0x56,0x34,0x12,0xaf] + +s_mul_u64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0xaa] + +s_mul_u64 s[100:101], s[102:103], s[104:105] +// GFX12: encoding: [0x66,0x68,0xe4,0xaa] + +s_mul_u64 s[0:1], s[104:105], s[102:103] +// GFX12: encoding: [0x68,0x66,0x80,0xaa] + +s_mul_u64 s[104:105], s[0:1], s[102:103] +// GFX12: encoding: [0x00,0x66,0xe8,0xaa] + +s_mul_u64 s[104:105], s[102:103], s[2:3] +// GFX12: encoding: [0x66,0x02,0xe8,0xaa] + +s_mul_u64 s[104:105], s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0xe8,0xaa] + +s_mul_u64 s[0:1], s[102:103], s[2:3] +// GFX12: encoding: [0x66,0x02,0x80,0xaa] + +s_mul_u64 s[0:1], s[2:3], s[102:103] +// GFX12: encoding: [0x02,0x66,0x80,0xaa] + +s_mul_u64 exec, s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0xfe,0xaa] + +s_mul_u64 vcc, s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0xea,0xaa] + +s_mul_u64 s[0:1], exec, s[2:3] +// GFX12: encoding: [0x7e,0x02,0x80,0xaa] + +s_mul_u64 s[0:1], vcc, s[2:3] +// GFX12: encoding: [0x6a,0x02,0x80,0xaa] + +s_mul_u64 s[0:1], 0, s[2:3] +// GFX12: encoding: [0x80,0x02,0x80,0xaa] + +s_mul_u64 s[0:1], -1, s[2:3] +// GFX12: encoding: [0xc1,0x02,0x80,0xaa] + +s_mul_u64 s[0:1], 0.5, s[2:3] +// GFX12: encoding: [0xf0,0x02,0x80,0xaa] + +s_mul_u64 s[0:1], -4.0, s[2:3] +// GFX12: encoding: [0xf7,0x02,0x80,0xaa] + +s_mul_u64 s[0:1], 0x3f717273, s[2:3] +// GFX12: encoding: [0xff,0x02,0x80,0xaa,0x73,0x72,0x71,0x3f] + +s_mul_u64 s[0:1], 0xaf123456, s[2:3] +// GFX12: encoding: [0xff,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf] + +s_mul_u64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0xaa] + +s_mul_u64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0xaa] + +s_mul_u64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0xaa] + +s_mul_u64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0xaa] + +s_mul_u64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0xaa] + +s_mul_u64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0xaa] + +s_mul_u64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0xaa,0x73,0x72,0x71,0x3f] + +s_mul_u64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0xaa,0x56,0x34,0x12,0xaf] + +s_add_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa0] + +s_add_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa0] + +s_add_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa0] + +s_add_f32 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x05,0xa0] + +s_add_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa0] + +s_add_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa0] + +s_add_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa0] + +s_add_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa0] + +s_add_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa0] + +s_add_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa0] + +s_add_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa0] + +s_add_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa0] + +s_add_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa0] + +s_add_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa0,0x56,0x34,0x12,0xaf] + +s_add_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa0,0x73,0x72,0x71,0x3f] + +s_add_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa0] + +s_sub_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa0] + +s_sub_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa0] + +s_sub_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa0] + +s_sub_f32 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x85,0xa0] + +s_sub_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa0] + +s_sub_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa0] + +s_sub_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa0] + +s_sub_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa0] + +s_sub_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa0] + +s_sub_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa0] + +s_sub_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa0] + +s_sub_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa0] + +s_sub_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa0] + +s_sub_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa0,0x56,0x34,0x12,0xaf] + +s_sub_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa0,0x73,0x72,0x71,0x3f] + +s_sub_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa0] + +s_mul_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa2] + +s_mul_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa2] + +s_mul_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa2] + +s_mul_f32 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x05,0xa2] + +s_mul_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa2] + +s_mul_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa2] + +s_mul_f32 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x05,0xa2] + +s_mul_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa2] + +s_mul_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa2] + +s_mul_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa2] + +s_mul_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa2] + +s_mul_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa2] + +s_mul_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa2] + +s_mul_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa2] + +s_mul_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa2,0x56,0x34,0x12,0xaf] + +s_mul_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa2,0x73,0x72,0x71,0x3f] + +s_mul_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa2] + +s_min_num_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa1] + +s_min_num_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa1] + +s_min_num_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa1] + +s_min_num_f32 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x05,0xa1] + +s_min_num_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa1] + +s_min_num_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa1] + +s_min_num_f32 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x05,0xa1] + +s_min_num_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa1] + +s_min_num_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa1] + +s_min_num_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa1] + +s_min_num_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa1] + +s_min_num_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa1] + +s_min_num_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa1] + +s_min_num_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa1] + +s_min_num_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa1,0x56,0x34,0x12,0xaf] + +s_min_num_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa1,0x73,0x72,0x71,0x3f] + +s_min_num_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa1] + +s_max_num_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa1] + +s_max_num_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa1] + +s_max_num_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa1] + +s_max_num_f32 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x85,0xa1] + +s_max_num_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa1] + +s_max_num_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa1] + +s_max_num_f32 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x85,0xa1] + +s_max_num_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa1] + +s_max_num_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa1] + +s_max_num_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa1] + +s_max_num_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa1] + +s_max_num_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa1] + +s_max_num_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa1] + +s_max_num_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa1] + +s_max_num_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa1,0x56,0x34,0x12,0xaf] + +s_max_num_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa1,0x73,0x72,0x71,0x3f] + +s_max_num_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa1] + +s_fmac_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa3] + +s_fmac_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa3] + +s_fmac_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa3] + +s_fmac_f32 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x85,0xa3] + +s_fmac_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa3] + +s_fmac_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa3] + +s_fmac_f32 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x85,0xa3] + +s_fmac_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa3] + +s_fmac_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa3] + +s_fmac_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa3] + +s_fmac_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa3] + +s_fmac_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa3] + +s_fmac_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa3] + +s_fmac_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa3] + +s_fmac_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa3,0x56,0x34,0x12,0xaf] + +s_fmac_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa3,0x73,0x72,0x71,0x3f] + +s_fmac_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa3] + +s_fmamk_f32 s5, s1, 0x11213141, s3 +// GFX12: encoding: [0x01,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] + +s_fmamk_f32 s105, s1, 0x11213141, s3 +// GFX12: encoding: [0x01,0x03,0x69,0xa3,0x41,0x31,0x21,0x11] + +s_fmamk_f32 s5, s105, 0x11213141, s3 +// GFX12: encoding: [0x69,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] + +s_fmamk_f32 s5, 0, 0x11213141, s3 +// GFX12: encoding: [0x80,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] + +s_fmamk_f32 s5, -1, 0x11213141, s3 +// GFX12: encoding: [0xc1,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] + +s_fmamk_f32 s5, 0.5, 0x11213141, s3 +// GFX12: encoding: [0xf0,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] + +s_fmamk_f32 s5, -4.0, 0x11213141, s3 +// GFX12: encoding: [0xf7,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] + +s_fmamk_f32 s5, s1, 0xa1b1c1d1, s3 +// GFX12: encoding: [0x01,0x03,0x05,0xa3,0xd1,0xc1,0xb1,0xa1] + +s_fmamk_f32 s5, s1, 0x11213141, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa3,0x41,0x31,0x21,0x11] + +s_fmamk_f32 s5, 0x11213141, 0x11213141, s105 +// GFX12 encoding: [0xff,0x69,0x05,0xa3,0x41,0x31,0x21,0x11] + +s_fmamk_f32 s5, s105, 0x11213141, 0x11213141 +// GFX12 encoding: [0x69,0xff,0x05,0xa3,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, s1, s2, 0x11213141 +// GFX12: encoding: [0x01,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s105, s1, s2, 0x11213141 +// GFX12: encoding: [0x01,0x02,0xe9,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, s105, s2, 0x11213141 +// GFX12: encoding: [0x69,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, 0, s2, 0x11213141 +// GFX12: encoding: [0x80,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, -1, s2, 0x11213141 +// GFX12: encoding: [0xc1,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, 0.5, s2, 0x11213141 +// GFX12: encoding: [0xf0,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, -4.0, s2, 0x11213141 +// GFX12: encoding: [0xf7,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, s1, s105, 0x11213141 +// GFX12: encoding: [0x01,0x69,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, s1, s2, 0xa1b1c1d1 +// GFX12: encoding: [0x01,0x02,0x85,0xa2,0xd1,0xc1,0xb1,0xa1] + +s_fmaak_f32 s5, 0x11213141, s2, 0x11213141 +// GFX12: encoding: [0xff,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, s105, 0x11213141, 0x11213141 +// GFX12: encoding: [0x69,0xff,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_fmaak_f32 s5, 0x11213141, 0x11213141, 0x11213141 +// GFX12: encoding: [0xff,0xff,0x85,0xa2,0x41,0x31,0x21,0x11] + +s_cvt_pk_rtz_f16_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa4] + +s_cvt_pk_rtz_f16_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa4,0x56,0x34,0x12,0xaf] + +s_cvt_pk_rtz_f16_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa4,0x73,0x72,0x71,0x3f] + +s_cvt_pk_rtz_f16_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa4] + +s_add_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa4] + +s_add_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa4] + +s_add_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa4] + +s_add_f16 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x85,0xa4] + +s_add_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa4] + +s_add_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa4] + +s_add_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa4] + +s_add_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa4] + +s_add_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa4] + +s_add_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa4] + +s_add_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa4] + +s_add_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa4] + +s_add_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa4] + +s_add_f16 s5, 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa4,0x0b,0xfe,0x00,0x00] + +s_add_f16 s5, 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa4,0x56,0x34,0x00,0x00] + +s_add_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa4] + +s_sub_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa5] + +s_sub_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa5] + +s_sub_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa5] + +s_sub_f16 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x05,0xa5] + +s_sub_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa5] + +s_sub_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa5] + +s_sub_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa5] + +s_sub_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa5] + +s_sub_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa5] + +s_sub_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa5] + +s_sub_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa5] + +s_sub_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa5] + +s_sub_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa5] + +s_sub_f16 s5, 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa5,0x0b,0xfe,0x00,0x00] + +s_sub_f16 s5, 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa5,0x56,0x34,0x00,0x00] + +s_sub_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa5] + +s_mul_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa6] + +s_mul_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa6] + +s_mul_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa6] + +s_mul_f16 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x85,0xa6] + +s_mul_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa6] + +s_mul_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa6] + +s_mul_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa6] + +s_mul_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa6] + +s_mul_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa6] + +s_mul_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa6] + +s_mul_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa6] + +s_mul_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa6] + +s_mul_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa6] + +s_mul_f16 s5, 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa6,0x0b,0xfe,0x00,0x00] + +s_mul_f16 s5, 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa6,0x56,0x34,0x00,0x00] + +s_mul_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa6] + +s_fmac_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa7] + +s_fmac_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa7] + +s_fmac_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa7] + +s_fmac_f16 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x05,0xa7] + +s_fmac_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa7] + +s_fmac_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa7] + +s_fmac_f16 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x05,0xa7] + +s_fmac_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa7] + +s_fmac_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa7] + +s_fmac_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa7] + +s_fmac_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa7] + +s_fmac_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa7] + +s_fmac_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa7] + +s_fmac_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa7] + +s_fmac_f16 s5, 0x1234, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa7,0x34,0x12,0x00,0x00] + +s_fmac_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa7] + +s_max_num_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa6] + +s_max_num_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa6] + +s_max_num_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa6] + +s_max_num_f16 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x05,0xa6] + +s_max_num_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa6] + +s_max_num_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa6] + +s_max_num_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa6] + +s_max_num_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa6] + +s_max_num_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa6] + +s_max_num_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa6] + +s_max_num_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa6] + +s_max_num_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa6] + +s_max_num_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa6] + +s_max_num_f16 s5, 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa6,0x0b,0xfe,0x00,0x00] + +s_max_num_f16 s5, 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa6,0x56,0x34,0x00,0x00] + +s_max_num_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa6] + +s_min_num_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa5] + +s_min_num_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa5] + +s_min_num_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa5] + +s_min_num_f16 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x85,0xa5] + +s_min_num_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa5] + +s_min_num_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa5] + +s_min_num_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa5] + +s_min_num_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa5] + +s_min_num_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa5] + +s_min_num_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa5] + +s_min_num_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa5] + +s_min_num_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa5] + +s_min_num_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa5] + +s_min_num_f16 s5, 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa5,0x0b,0xfe,0x00,0x00] + +s_min_num_f16 s5, 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa5,0x56,0x34,0x00,0x00] + +s_min_num_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa5] + +s_add_co_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x80] + +s_add_co_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x80] + +s_add_co_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x80] + +s_add_co_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x80] + +s_add_co_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x80] + +s_add_co_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x80] + +s_add_co_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x80] + +s_add_co_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x80] + +s_add_co_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x80] + +s_add_co_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x80] + +s_add_co_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x80] + +s_add_co_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x80] + +s_add_co_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x80] + +s_add_co_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x80] + +s_add_co_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x80] + +s_add_co_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x80] + +s_add_co_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x80] + +s_add_co_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x80] + +s_add_co_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x80] + +s_add_co_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x80] + +s_add_co_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x80] + +s_add_co_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x80] + +s_add_co_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x80,0x73,0x72,0x71,0x3f] + +s_add_co_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x80,0x56,0x34,0x12,0xaf] + +s_add_co_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x80] + +s_add_co_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x80] + +s_add_co_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x80] + +s_add_co_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x80] + +s_add_co_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x80] + +s_add_co_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x80] + +s_add_co_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x80] + +s_add_co_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x80] + +s_add_co_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x80] + +s_add_co_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x80,0x73,0x72,0x71,0x3f] + +s_add_co_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x80,0x56,0x34,0x12,0xaf] + +s_sub_co_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x80] + +s_sub_co_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x80] + +s_sub_co_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x80] + +s_sub_co_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x80] + +s_sub_co_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x80] + +s_sub_co_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x80] + +s_sub_co_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x80] + +s_sub_co_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x80] + +s_sub_co_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x80] + +s_sub_co_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x80] + +s_sub_co_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x80] + +s_sub_co_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x80] + +s_sub_co_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x80] + +s_sub_co_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x80] + +s_sub_co_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x80] + +s_sub_co_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x80] + +s_sub_co_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x80] + +s_sub_co_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x80] + +s_sub_co_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x80] + +s_sub_co_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x80] + +s_sub_co_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x80] + +s_sub_co_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x80] + +s_sub_co_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x80,0x73,0x72,0x71,0x3f] + +s_sub_co_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x80,0x56,0x34,0x12,0xaf] + +s_sub_co_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x80] + +s_sub_co_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x80] + +s_sub_co_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x80] + +s_sub_co_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x80] + +s_sub_co_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x80] + +s_sub_co_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x80] + +s_sub_co_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x80] + +s_sub_co_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x80] + +s_sub_co_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x80] + +s_sub_co_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x80,0x73,0x72,0x71,0x3f] + +s_sub_co_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x80,0x56,0x34,0x12,0xaf] + +s_add_co_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x81] + +s_add_co_i32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x81] + +s_add_co_i32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x81] + +s_add_co_i32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x81] + +s_add_co_i32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x81] + +s_add_co_i32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x81] + +s_add_co_i32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x81] + +s_add_co_i32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x81] + +s_add_co_i32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x81] + +s_add_co_i32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x81] + +s_add_co_i32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x81] + +s_add_co_i32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x81] + +s_add_co_i32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x81] + +s_add_co_i32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x81] + +s_add_co_i32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x81] + +s_add_co_i32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x81] + +s_add_co_i32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x81] + +s_add_co_i32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x81] + +s_add_co_i32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x81] + +s_add_co_i32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x81] + +s_add_co_i32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x81] + +s_add_co_i32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x81] + +s_add_co_i32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x81,0x73,0x72,0x71,0x3f] + +s_add_co_i32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x81,0x56,0x34,0x12,0xaf] + +s_add_co_i32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x81] + +s_add_co_i32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x81] + +s_add_co_i32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x81] + +s_add_co_i32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x81] + +s_add_co_i32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x81] + +s_add_co_i32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x81] + +s_add_co_i32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x81] + +s_add_co_i32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x81] + +s_add_co_i32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x81] + +s_add_co_i32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x81,0x73,0x72,0x71,0x3f] + +s_add_co_i32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x81,0x56,0x34,0x12,0xaf] + +s_sub_co_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x81] + +s_sub_co_i32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x81] + +s_sub_co_i32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x81] + +s_sub_co_i32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x81] + +s_sub_co_i32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x81] + +s_sub_co_i32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x81] + +s_sub_co_i32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x81] + +s_sub_co_i32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x81] + +s_sub_co_i32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x81] + +s_sub_co_i32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x81] + +s_sub_co_i32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x81] + +s_sub_co_i32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x81] + +s_sub_co_i32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x81] + +s_sub_co_i32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x81] + +s_sub_co_i32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x81] + +s_sub_co_i32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x81] + +s_sub_co_i32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x81] + +s_sub_co_i32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x81] + +s_sub_co_i32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x81] + +s_sub_co_i32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x81] + +s_sub_co_i32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x81] + +s_sub_co_i32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x81] + +s_sub_co_i32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x81,0x73,0x72,0x71,0x3f] + +s_sub_co_i32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x81,0x56,0x34,0x12,0xaf] + +s_sub_co_i32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x81] + +s_sub_co_i32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x81] + +s_sub_co_i32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x81] + +s_sub_co_i32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x81] + +s_sub_co_i32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x81] + +s_sub_co_i32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x81] + +s_sub_co_i32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x81] + +s_sub_co_i32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x81] + +s_sub_co_i32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x81] + +s_sub_co_i32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x81,0x73,0x72,0x71,0x3f] + +s_sub_co_i32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x81,0x56,0x34,0x12,0xaf] + +s_add_co_ci_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x82] + +s_add_co_ci_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x82] + +s_add_co_ci_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x82] + +s_add_co_ci_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x82] + +s_add_co_ci_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x82] + +s_add_co_ci_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x82] + +s_add_co_ci_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x82] + +s_add_co_ci_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x82] + +s_add_co_ci_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x82] + +s_add_co_ci_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x82] + +s_add_co_ci_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x82] + +s_add_co_ci_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x82] + +s_add_co_ci_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x82] + +s_add_co_ci_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x82,0x73,0x72,0x71,0x3f] + +s_add_co_ci_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x82,0x56,0x34,0x12,0xaf] + +s_add_co_ci_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x82] + +s_add_co_ci_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x82] + +s_add_co_ci_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x82] + +s_add_co_ci_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x82] + +s_add_co_ci_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x82] + +s_add_co_ci_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x82] + +s_add_co_ci_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x82] + +s_add_co_ci_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x82] + +s_add_co_ci_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x82] + +s_add_co_ci_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x82,0x73,0x72,0x71,0x3f] + +s_add_co_ci_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x82,0x56,0x34,0x12,0xaf] + +s_sub_co_ci_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x82] + +s_sub_co_ci_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x82] + +s_sub_co_ci_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x82] + +s_sub_co_ci_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x82] + +s_sub_co_ci_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x82] + +s_sub_co_ci_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x82] + +s_sub_co_ci_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x82] + +s_sub_co_ci_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x82] + +s_sub_co_ci_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x82] + +s_sub_co_ci_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x82] + +s_sub_co_ci_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x82] + +s_sub_co_ci_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x82] + +s_sub_co_ci_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x82] + +s_sub_co_ci_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x82,0x73,0x72,0x71,0x3f] + +s_sub_co_ci_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x82,0x56,0x34,0x12,0xaf] + +s_sub_co_ci_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x82] + +s_sub_co_ci_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x82,0x73,0x72,0x71,0x3f] + +s_sub_co_ci_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x82,0x56,0x34,0x12,0xaf] + +s_min_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x89] + +s_min_i32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x89] + +s_min_i32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x89] + +s_min_i32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x89] + +s_min_i32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x89] + +s_min_i32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x89] + +s_min_i32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x89] + +s_min_i32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x89] + +s_min_i32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x89] + +s_min_i32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x89] + +s_min_i32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x89] + +s_min_i32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x89] + +s_min_i32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x89] + +s_min_i32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x89] + +s_min_i32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x89] + +s_min_i32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x89] + +s_min_i32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x89] + +s_min_i32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x89] + +s_min_i32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x89] + +s_min_i32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x89] + +s_min_i32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x89] + +s_min_i32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x89] + +s_min_i32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x89,0x73,0x72,0x71,0x3f] + +s_min_i32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x89,0x56,0x34,0x12,0xaf] + +s_min_i32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x89] + +s_min_i32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x89] + +s_min_i32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x89] + +s_min_i32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x89] + +s_min_i32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x89] + +s_min_i32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x89] + +s_min_i32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x89] + +s_min_i32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x89] + +s_min_i32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x89] + +s_min_i32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x89,0x73,0x72,0x71,0x3f] + +s_min_i32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x89,0x56,0x34,0x12,0xaf] + +s_min_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x89] + +s_min_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x89] + +s_min_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x89] + +s_min_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x89] + +s_min_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x89] + +s_min_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x89] + +s_min_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x89] + +s_min_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x89] + +s_min_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x89] + +s_min_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x89] + +s_min_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x89] + +s_min_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x89] + +s_min_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x89] + +s_min_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x89] + +s_min_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x89] + +s_min_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x89] + +s_min_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x89] + +s_min_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x89] + +s_min_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x89] + +s_min_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x89] + +s_min_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x89] + +s_min_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x89] + +s_min_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x89,0x73,0x72,0x71,0x3f] + +s_min_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x89,0x56,0x34,0x12,0xaf] + +s_min_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x89] + +s_min_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x89] + +s_min_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x89] + +s_min_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x89] + +s_min_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x89] + +s_min_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x89] + +s_min_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x89] + +s_min_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x89] + +s_min_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x89] + +s_min_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x89,0x73,0x72,0x71,0x3f] + +s_min_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x89,0x56,0x34,0x12,0xaf] + +s_max_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x8a] + +s_max_i32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x8a] + +s_max_i32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x8a] + +s_max_i32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x8a] + +s_max_i32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x8a] + +s_max_i32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x8a] + +s_max_i32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x8a] + +s_max_i32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x8a] + +s_max_i32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x8a] + +s_max_i32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x8a] + +s_max_i32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x8a] + +s_max_i32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x8a] + +s_max_i32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x8a] + +s_max_i32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x8a] + +s_max_i32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x8a] + +s_max_i32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x8a] + +s_max_i32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x8a] + +s_max_i32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x8a] + +s_max_i32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x8a] + +s_max_i32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x8a] + +s_max_i32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x8a] + +s_max_i32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x8a] + +s_max_i32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8a,0x73,0x72,0x71,0x3f] + +s_max_i32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8a,0x56,0x34,0x12,0xaf] + +s_max_i32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x8a] + +s_max_i32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x8a] + +s_max_i32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x8a] + +s_max_i32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x8a] + +s_max_i32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x8a] + +s_max_i32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x8a] + +s_max_i32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x8a] + +s_max_i32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x8a] + +s_max_i32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x8a] + +s_max_i32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x8a,0x73,0x72,0x71,0x3f] + +s_max_i32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x8a,0x56,0x34,0x12,0xaf] + +s_max_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x8a] + +s_max_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x8a] + +s_max_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x8a] + +s_max_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x8a] + +s_max_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x8a] + +s_max_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x8a] + +s_max_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x8a] + +s_max_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x8a] + +s_max_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x8a] + +s_max_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x8a] + +s_max_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x8a] + +s_max_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x8a] + +s_max_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x8a] + +s_max_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x8a] + +s_max_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x8a] + +s_max_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x8a] + +s_max_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x8a] + +s_max_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x8a] + +s_max_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x8a] + +s_max_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x8a] + +s_max_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x8a] + +s_max_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x8a] + +s_max_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x8a,0x73,0x72,0x71,0x3f] + +s_max_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x8a,0x56,0x34,0x12,0xaf] + +s_max_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x8a] + +s_max_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x8a] + +s_max_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x8a] + +s_max_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x8a] + +s_max_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x8a] + +s_max_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x8a] + +s_max_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x8a] + +s_max_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x8a] + +s_max_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x8a] + +s_max_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x8a,0x73,0x72,0x71,0x3f] + +s_max_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x8a,0x56,0x34,0x12,0xaf] + +s_cselect_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x98] + +s_cselect_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x98] + +s_cselect_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x98] + +s_cselect_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x98] + +s_cselect_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x98] + +s_cselect_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x98] + +s_cselect_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x98] + +s_cselect_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x98] + +s_cselect_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x98] + +s_cselect_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x98] + +s_cselect_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x98] + +s_cselect_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x98] + +s_cselect_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x98] + +s_cselect_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x98] + +s_cselect_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x98] + +s_cselect_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x98] + +s_cselect_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x98] + +s_cselect_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x98] + +s_cselect_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x98] + +s_cselect_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x98] + +s_cselect_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x98] + +s_cselect_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x98] + +s_cselect_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x98,0x73,0x72,0x71,0x3f] + +s_cselect_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x98,0x56,0x34,0x12,0xaf] + +s_cselect_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x98] + +s_cselect_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x98] + +s_cselect_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x98] + +s_cselect_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x98] + +s_cselect_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x98] + +s_cselect_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x98] + +s_cselect_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x98] + +s_cselect_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x98] + +s_cselect_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x98] + +s_cselect_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x98,0x73,0x72,0x71,0x3f] + +s_cselect_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x98,0x56,0x34,0x12,0xaf] + +s_cselect_b64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0x98] + +s_cselect_b64 s[104:105], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0xe8,0x98] + +s_cselect_b64 s[0:1], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0x80,0x98] + +s_cselect_b64 s[104:105], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0xe8,0x98] + +s_cselect_b64 s[104:105], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0xe8,0x98] + +s_cselect_b64 s[104:105], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xe8,0x98] + +s_cselect_b64 s[0:1], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0x80,0x98] + +s_cselect_b64 s[0:1], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0x80,0x98] + +s_cselect_b64 exec, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xfe,0x98] + +s_cselect_b64 vcc, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xea,0x98] + +s_cselect_b64 s[0:1], exec, s[4:5] +// GFX12: encoding: [0x7e,0x04,0x80,0x98] + +s_cselect_b64 s[0:1], vcc, s[4:5] +// GFX12: encoding: [0x6a,0x04,0x80,0x98] + +s_cselect_b64 s[0:1], 0, s[4:5] +// GFX12: encoding: [0x80,0x04,0x80,0x98] + +s_cselect_b64 s[0:1], -1, s[4:5] +// GFX12: encoding: [0xc1,0x04,0x80,0x98] + +s_cselect_b64 s[0:1], 0.5, s[4:5] +// GFX12: encoding: [0xf0,0x04,0x80,0x98] + +s_cselect_b64 s[0:1], -4.0, s[4:5] +// GFX12: encoding: [0xf7,0x04,0x80,0x98] + +s_cselect_b64 s[0:1], 0x3f717273, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x98,0x73,0x72,0x71,0x3f] + +s_cselect_b64 s[0:1], 0xaf123456, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x98,0x56,0x34,0x12,0xaf] + +s_cselect_b64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0x98] + +s_cselect_b64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0x98] + +s_cselect_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x98] + +s_cselect_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x98] + +s_cselect_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x98] + +s_cselect_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x98] + +s_cselect_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x98,0x73,0x72,0x71,0x3f] + +s_cselect_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x98,0x56,0x34,0x12,0xaf] + +s_and_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x8b] + +s_and_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x8b] + +s_and_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x8b] + +s_and_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x8b] + +s_and_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x8b] + +s_and_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x8b] + +s_and_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x8b] + +s_and_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x8b] + +s_and_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x8b] + +s_and_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x8b] + +s_and_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x8b] + +s_and_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x8b] + +s_and_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x8b] + +s_and_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x8b] + +s_and_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x8b] + +s_and_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x8b] + +s_and_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x8b] + +s_and_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x8b] + +s_and_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x8b] + +s_and_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x8b] + +s_and_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x8b] + +s_and_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x8b] + +s_and_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8b,0x73,0x72,0x71,0x3f] + +s_and_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8b,0x56,0x34,0x12,0xaf] + +s_and_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x8b] + +s_and_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x8b] + +s_and_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x8b] + +s_and_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x8b] + +s_and_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x8b] + +s_and_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x8b] + +s_and_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x8b] + +s_and_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x8b] + +s_and_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x8b] + +s_and_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x8b,0x73,0x72,0x71,0x3f] + +s_and_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x8b,0x56,0x34,0x12,0xaf] + +s_and_b32 s0, s1, null +// GFX12: encoding: [0x01,0x7c,0x00,0x8b] + +s_and_b32 s0, null, s2 +// GFX12: encoding: [0x7c,0x02,0x00,0x8b] + +s_and_b32 null, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7c,0x8b] + +s_and_b64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0x8b] + +s_and_b64 s[104:105], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0xe8,0x8b] + +s_and_b64 s[0:1], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0x80,0x8b] + +s_and_b64 s[104:105], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0xe8,0x8b] + +s_and_b64 s[104:105], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0xe8,0x8b] + +s_and_b64 s[104:105], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xe8,0x8b] + +s_and_b64 s[0:1], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0x80,0x8b] + +s_and_b64 s[0:1], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0x80,0x8b] + +s_and_b64 exec, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xfe,0x8b] + +s_and_b64 vcc, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xea,0x8b] + +s_and_b64 s[0:1], exec, s[4:5] +// GFX12: encoding: [0x7e,0x04,0x80,0x8b] + +s_and_b64 s[0:1], vcc, s[4:5] +// GFX12: encoding: [0x6a,0x04,0x80,0x8b] + +s_and_b64 s[0:1], 0, s[4:5] +// GFX12: encoding: [0x80,0x04,0x80,0x8b] + +s_and_b64 s[0:1], -1, s[4:5] +// GFX12: encoding: [0xc1,0x04,0x80,0x8b] + +s_and_b64 s[0:1], 0.5, s[4:5] +// GFX12: encoding: [0xf0,0x04,0x80,0x8b] + +s_and_b64 s[0:1], -4.0, s[4:5] +// GFX12: encoding: [0xf7,0x04,0x80,0x8b] + +s_and_b64 s[0:1], 0x3f717273, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8b,0x73,0x72,0x71,0x3f] + +s_and_b64 s[0:1], 0xaf123456, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf] + +s_and_b64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0x8b] + +s_and_b64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0x8b] + +s_and_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x8b] + +s_and_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x8b] + +s_and_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x8b] + +s_and_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x8b] + +s_and_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x8b,0x73,0x72,0x71,0x3f] + +s_and_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x8b,0x56,0x34,0x12,0xaf] + +s_or_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x8c] + +s_or_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x8c] + +s_or_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x8c] + +s_or_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x8c] + +s_or_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x8c] + +s_or_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x8c] + +s_or_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x8c] + +s_or_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x8c] + +s_or_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x8c] + +s_or_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x8c] + +s_or_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x8c] + +s_or_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x8c] + +s_or_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x8c] + +s_or_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x8c] + +s_or_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x8c] + +s_or_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x8c] + +s_or_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x8c] + +s_or_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x8c] + +s_or_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x8c] + +s_or_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x8c] + +s_or_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x8c] + +s_or_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x8c] + +s_or_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8c,0x73,0x72,0x71,0x3f] + +s_or_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8c,0x56,0x34,0x12,0xaf] + +s_or_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x8c] + +s_or_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x8c] + +s_or_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x8c] + +s_or_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x8c] + +s_or_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x8c] + +s_or_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x8c] + +s_or_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x8c] + +s_or_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x8c] + +s_or_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x8c] + +s_or_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x8c,0x73,0x72,0x71,0x3f] + +s_or_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x8c,0x56,0x34,0x12,0xaf] + +s_or_b64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0x8c] + +s_or_b64 s[104:105], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0xe8,0x8c] + +s_or_b64 s[0:1], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0x80,0x8c] + +s_or_b64 s[104:105], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0xe8,0x8c] + +s_or_b64 s[104:105], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0xe8,0x8c] + +s_or_b64 s[104:105], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xe8,0x8c] + +s_or_b64 s[0:1], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0x80,0x8c] + +s_or_b64 s[0:1], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0x80,0x8c] + +s_or_b64 exec, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xfe,0x8c] + +s_or_b64 vcc, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xea,0x8c] + +s_or_b64 s[0:1], exec, s[4:5] +// GFX12: encoding: [0x7e,0x04,0x80,0x8c] + +s_or_b64 s[0:1], vcc, s[4:5] +// GFX12: encoding: [0x6a,0x04,0x80,0x8c] + +s_or_b64 s[0:1], 0, s[4:5] +// GFX12: encoding: [0x80,0x04,0x80,0x8c] + +s_or_b64 s[0:1], -1, s[4:5] +// GFX12: encoding: [0xc1,0x04,0x80,0x8c] + +s_or_b64 s[0:1], 0.5, s[4:5] +// GFX12: encoding: [0xf0,0x04,0x80,0x8c] + +s_or_b64 s[0:1], -4.0, s[4:5] +// GFX12: encoding: [0xf7,0x04,0x80,0x8c] + +s_or_b64 s[0:1], 0x3f717273, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8c,0x73,0x72,0x71,0x3f] + +s_or_b64 s[0:1], 0xaf123456, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf] + +s_or_b64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0x8c] + +s_or_b64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0x8c] + +s_or_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x8c] + +s_or_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x8c] + +s_or_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x8c] + +s_or_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x8c] + +s_or_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x8c,0x73,0x72,0x71,0x3f] + +s_or_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x8c,0x56,0x34,0x12,0xaf] + +s_xor_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x8d] + +s_xor_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x8d] + +s_xor_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x8d] + +s_xor_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x8d] + +s_xor_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x8d] + +s_xor_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x8d] + +s_xor_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x8d] + +s_xor_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x8d] + +s_xor_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x8d] + +s_xor_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x8d] + +s_xor_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x8d] + +s_xor_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x8d] + +s_xor_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x8d] + +s_xor_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x8d] + +s_xor_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x8d] + +s_xor_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x8d] + +s_xor_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x8d] + +s_xor_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x8d] + +s_xor_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x8d] + +s_xor_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x8d] + +s_xor_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x8d] + +s_xor_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x8d] + +s_xor_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8d,0x73,0x72,0x71,0x3f] + +s_xor_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8d,0x56,0x34,0x12,0xaf] + +s_xor_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x8d] + +s_xor_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x8d] + +s_xor_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x8d] + +s_xor_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x8d] + +s_xor_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x8d] + +s_xor_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x8d] + +s_xor_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x8d] + +s_xor_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x8d] + +s_xor_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x8d] + +s_xor_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x8d,0x73,0x72,0x71,0x3f] + +s_xor_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x8d,0x56,0x34,0x12,0xaf] + +s_xor_b64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0x8d] + +s_xor_b64 s[104:105], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0xe8,0x8d] + +s_xor_b64 s[0:1], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0x80,0x8d] + +s_xor_b64 s[104:105], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0xe8,0x8d] + +s_xor_b64 s[104:105], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0xe8,0x8d] + +s_xor_b64 s[104:105], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xe8,0x8d] + +s_xor_b64 s[0:1], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0x80,0x8d] + +s_xor_b64 s[0:1], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0x80,0x8d] + +s_xor_b64 exec, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xfe,0x8d] + +s_xor_b64 vcc, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xea,0x8d] + +s_xor_b64 s[0:1], exec, s[4:5] +// GFX12: encoding: [0x7e,0x04,0x80,0x8d] + +s_xor_b64 s[0:1], vcc, s[4:5] +// GFX12: encoding: [0x6a,0x04,0x80,0x8d] + +s_xor_b64 s[0:1], 0, s[4:5] +// GFX12: encoding: [0x80,0x04,0x80,0x8d] + +s_xor_b64 s[0:1], -1, s[4:5] +// GFX12: encoding: [0xc1,0x04,0x80,0x8d] + +s_xor_b64 s[0:1], 0.5, s[4:5] +// GFX12: encoding: [0xf0,0x04,0x80,0x8d] + +s_xor_b64 s[0:1], -4.0, s[4:5] +// GFX12: encoding: [0xf7,0x04,0x80,0x8d] + +s_xor_b64 s[0:1], 0x3f717273, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8d,0x73,0x72,0x71,0x3f] + +s_xor_b64 s[0:1], 0xaf123456, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf] + +s_xor_b64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0x8d] + +s_xor_b64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0x8d] + +s_xor_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x8d] + +s_xor_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x8d] + +s_xor_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x8d] + +s_xor_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x8d] + +s_xor_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x8d,0x73,0x72,0x71,0x3f] + +s_xor_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x8d,0x56,0x34,0x12,0xaf] + +s_andn2_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x91] + +s_andn2_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x91] + +s_andn2_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x91] + +s_andn2_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x91] + +s_andn2_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x91] + +s_andn2_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x91] + +s_andn2_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x91] + +s_andn2_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x91] + +s_andn2_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x91] + +s_andn2_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x91] + +s_andn2_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x91] + +s_andn2_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x91] + +s_andn2_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x91] + +s_andn2_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x91] + +s_andn2_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x91] + +s_andn2_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x91] + +s_andn2_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x91] + +s_andn2_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x91] + +s_andn2_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x91] + +s_andn2_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x91] + +s_andn2_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x91] + +s_andn2_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x91] + +s_andn2_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x91,0x73,0x72,0x71,0x3f] + +s_andn2_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x91,0x56,0x34,0x12,0xaf] + +s_andn2_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x91] + +s_andn2_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x91] + +s_andn2_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x91] + +s_andn2_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x91] + +s_andn2_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x91] + +s_andn2_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x91] + +s_andn2_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x91] + +s_andn2_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x91] + +s_andn2_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x91] + +s_andn2_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x91,0x73,0x72,0x71,0x3f] + +s_andn2_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x91,0x56,0x34,0x12,0xaf] + +s_andn2_b64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0x91] + +s_andn2_b64 s[104:105], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0xe8,0x91] + +s_andn2_b64 s[0:1], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0x80,0x91] + +s_andn2_b64 s[104:105], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0xe8,0x91] + +s_andn2_b64 s[104:105], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0xe8,0x91] + +s_andn2_b64 s[104:105], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xe8,0x91] + +s_andn2_b64 s[0:1], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0x80,0x91] + +s_andn2_b64 s[0:1], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0x80,0x91] + +s_andn2_b64 exec, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xfe,0x91] + +s_andn2_b64 vcc, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xea,0x91] + +s_andn2_b64 s[0:1], exec, s[4:5] +// GFX12: encoding: [0x7e,0x04,0x80,0x91] + +s_andn2_b64 s[0:1], vcc, s[4:5] +// GFX12: encoding: [0x6a,0x04,0x80,0x91] + +s_andn2_b64 s[0:1], 0, s[4:5] +// GFX12: encoding: [0x80,0x04,0x80,0x91] + +s_andn2_b64 s[0:1], -1, s[4:5] +// GFX12: encoding: [0xc1,0x04,0x80,0x91] + +s_andn2_b64 s[0:1], 0.5, s[4:5] +// GFX12: encoding: [0xf0,0x04,0x80,0x91] + +s_andn2_b64 s[0:1], -4.0, s[4:5] +// GFX12: encoding: [0xf7,0x04,0x80,0x91] + +s_andn2_b64 s[0:1], 0x3f717273, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x91,0x73,0x72,0x71,0x3f] + +s_andn2_b64 s[0:1], 0xaf123456, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x91,0x56,0x34,0x12,0xaf] + +s_andn2_b64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0x91] + +s_andn2_b64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0x91] + +s_andn2_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x91] + +s_andn2_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x91] + +s_andn2_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x91] + +s_andn2_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x91] + +s_andn2_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x91,0x73,0x72,0x71,0x3f] + +s_andn2_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x91,0x56,0x34,0x12,0xaf] + +s_orn2_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x92] + +s_orn2_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x92] + +s_orn2_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x92] + +s_orn2_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x92] + +s_orn2_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x92] + +s_orn2_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x92] + +s_orn2_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x92] + +s_orn2_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x92] + +s_orn2_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x92] + +s_orn2_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x92] + +s_orn2_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x92] + +s_orn2_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x92] + +s_orn2_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x92] + +s_orn2_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x92] + +s_orn2_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x92] + +s_orn2_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x92] + +s_orn2_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x92] + +s_orn2_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x92] + +s_orn2_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x92] + +s_orn2_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x92] + +s_orn2_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x92] + +s_orn2_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x92] + +s_orn2_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x92,0x73,0x72,0x71,0x3f] + +s_orn2_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x92,0x56,0x34,0x12,0xaf] + +s_orn2_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x92] + +s_orn2_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x92] + +s_orn2_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x92] + +s_orn2_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x92] + +s_orn2_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x92] + +s_orn2_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x92] + +s_orn2_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x92] + +s_orn2_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x92] + +s_orn2_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x92] + +s_orn2_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x92,0x73,0x72,0x71,0x3f] + +s_orn2_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x92,0x56,0x34,0x12,0xaf] + +s_orn2_b64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0x92] + +s_orn2_b64 s[104:105], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0xe8,0x92] + +s_orn2_b64 s[0:1], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0x80,0x92] + +s_orn2_b64 s[104:105], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0xe8,0x92] + +s_orn2_b64 s[104:105], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0xe8,0x92] + +s_orn2_b64 s[104:105], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xe8,0x92] + +s_orn2_b64 s[0:1], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0x80,0x92] + +s_orn2_b64 s[0:1], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0x80,0x92] + +s_orn2_b64 exec, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xfe,0x92] + +s_orn2_b64 vcc, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xea,0x92] + +s_orn2_b64 s[0:1], exec, s[4:5] +// GFX12: encoding: [0x7e,0x04,0x80,0x92] + +s_orn2_b64 s[0:1], vcc, s[4:5] +// GFX12: encoding: [0x6a,0x04,0x80,0x92] + +s_orn2_b64 s[0:1], 0, s[4:5] +// GFX12: encoding: [0x80,0x04,0x80,0x92] + +s_orn2_b64 s[0:1], -1, s[4:5] +// GFX12: encoding: [0xc1,0x04,0x80,0x92] + +s_orn2_b64 s[0:1], 0.5, s[4:5] +// GFX12: encoding: [0xf0,0x04,0x80,0x92] + +s_orn2_b64 s[0:1], -4.0, s[4:5] +// GFX12: encoding: [0xf7,0x04,0x80,0x92] + +s_orn2_b64 s[0:1], 0x3f717273, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x92,0x73,0x72,0x71,0x3f] + +s_orn2_b64 s[0:1], 0xaf123456, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x92,0x56,0x34,0x12,0xaf] + +s_orn2_b64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0x92] + +s_orn2_b64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0x92] + +s_orn2_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x92] + +s_orn2_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x92] + +s_orn2_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x92] + +s_orn2_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x92] + +s_orn2_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x92,0x73,0x72,0x71,0x3f] + +s_orn2_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x92,0x56,0x34,0x12,0xaf] + +s_nand_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x8e] + +s_nand_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x8e] + +s_nand_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x8e] + +s_nand_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x8e] + +s_nand_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x8e] + +s_nand_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x8e] + +s_nand_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x8e] + +s_nand_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x8e] + +s_nand_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x8e] + +s_nand_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x8e] + +s_nand_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x8e] + +s_nand_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x8e] + +s_nand_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x8e] + +s_nand_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x8e] + +s_nand_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x8e] + +s_nand_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x8e] + +s_nand_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x8e] + +s_nand_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x8e] + +s_nand_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x8e] + +s_nand_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x8e] + +s_nand_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x8e] + +s_nand_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x8e] + +s_nand_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8e,0x73,0x72,0x71,0x3f] + +s_nand_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8e,0x56,0x34,0x12,0xaf] + +s_nand_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x8e] + +s_nand_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x8e] + +s_nand_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x8e] + +s_nand_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x8e] + +s_nand_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x8e] + +s_nand_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x8e] + +s_nand_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x8e] + +s_nand_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x8e] + +s_nand_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x8e] + +s_nand_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x8e,0x73,0x72,0x71,0x3f] + +s_nand_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x8e,0x56,0x34,0x12,0xaf] + +s_nand_b64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0x8e] + +s_nand_b64 s[104:105], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0xe8,0x8e] + +s_nand_b64 s[0:1], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0x80,0x8e] + +s_nand_b64 s[104:105], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0xe8,0x8e] + +s_nand_b64 s[104:105], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0xe8,0x8e] + +s_nand_b64 s[104:105], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xe8,0x8e] + +s_nand_b64 s[0:1], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0x80,0x8e] + +s_nand_b64 s[0:1], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0x80,0x8e] + +s_nand_b64 exec, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xfe,0x8e] + +s_nand_b64 vcc, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xea,0x8e] + +s_nand_b64 s[0:1], exec, s[4:5] +// GFX12: encoding: [0x7e,0x04,0x80,0x8e] + +s_nand_b64 s[0:1], vcc, s[4:5] +// GFX12: encoding: [0x6a,0x04,0x80,0x8e] + +s_nand_b64 s[0:1], 0, s[4:5] +// GFX12: encoding: [0x80,0x04,0x80,0x8e] + +s_nand_b64 s[0:1], -1, s[4:5] +// GFX12: encoding: [0xc1,0x04,0x80,0x8e] + +s_nand_b64 s[0:1], 0.5, s[4:5] +// GFX12: encoding: [0xf0,0x04,0x80,0x8e] + +s_nand_b64 s[0:1], -4.0, s[4:5] +// GFX12: encoding: [0xf7,0x04,0x80,0x8e] + +s_nand_b64 s[0:1], 0x3f717273, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8e,0x73,0x72,0x71,0x3f] + +s_nand_b64 s[0:1], 0xaf123456, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf] + +s_nand_b64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0x8e] + +s_nand_b64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0x8e] + +s_nand_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x8e] + +s_nand_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x8e] + +s_nand_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x8e] + +s_nand_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x8e] + +s_nand_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x8e,0x73,0x72,0x71,0x3f] + +s_nand_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x8e,0x56,0x34,0x12,0xaf] + +s_nor_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x8f] + +s_nor_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x8f] + +s_nor_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x8f] + +s_nor_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x8f] + +s_nor_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x8f] + +s_nor_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x8f] + +s_nor_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x8f] + +s_nor_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x8f] + +s_nor_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x8f] + +s_nor_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x8f] + +s_nor_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x8f] + +s_nor_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x8f] + +s_nor_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x8f] + +s_nor_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x8f] + +s_nor_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x8f] + +s_nor_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x8f] + +s_nor_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x8f] + +s_nor_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x8f] + +s_nor_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x8f] + +s_nor_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x8f] + +s_nor_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x8f] + +s_nor_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x8f] + +s_nor_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8f,0x73,0x72,0x71,0x3f] + +s_nor_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x8f,0x56,0x34,0x12,0xaf] + +s_nor_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x8f] + +s_nor_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x8f] + +s_nor_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x8f] + +s_nor_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x8f] + +s_nor_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x8f] + +s_nor_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x8f] + +s_nor_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x8f] + +s_nor_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x8f] + +s_nor_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x8f] + +s_nor_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x8f,0x73,0x72,0x71,0x3f] + +s_nor_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x8f,0x56,0x34,0x12,0xaf] + +s_nor_b64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0x8f] + +s_nor_b64 s[104:105], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0xe8,0x8f] + +s_nor_b64 s[0:1], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0x80,0x8f] + +s_nor_b64 s[104:105], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0xe8,0x8f] + +s_nor_b64 s[104:105], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0xe8,0x8f] + +s_nor_b64 s[104:105], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xe8,0x8f] + +s_nor_b64 s[0:1], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0x80,0x8f] + +s_nor_b64 s[0:1], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0x80,0x8f] + +s_nor_b64 exec, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xfe,0x8f] + +s_nor_b64 vcc, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xea,0x8f] + +s_nor_b64 s[0:1], exec, s[4:5] +// GFX12: encoding: [0x7e,0x04,0x80,0x8f] + +s_nor_b64 s[0:1], vcc, s[4:5] +// GFX12: encoding: [0x6a,0x04,0x80,0x8f] + +s_nor_b64 s[0:1], 0, s[4:5] +// GFX12: encoding: [0x80,0x04,0x80,0x8f] + +s_nor_b64 s[0:1], -1, s[4:5] +// GFX12: encoding: [0xc1,0x04,0x80,0x8f] + +s_nor_b64 s[0:1], 0.5, s[4:5] +// GFX12: encoding: [0xf0,0x04,0x80,0x8f] + +s_nor_b64 s[0:1], -4.0, s[4:5] +// GFX12: encoding: [0xf7,0x04,0x80,0x8f] + +s_nor_b64 s[0:1], 0x3f717273, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8f,0x73,0x72,0x71,0x3f] + +s_nor_b64 s[0:1], 0xaf123456, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf] + +s_nor_b64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0x8f] + +s_nor_b64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0x8f] + +s_nor_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x8f] + +s_nor_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x8f] + +s_nor_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x8f] + +s_nor_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x8f] + +s_nor_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x8f,0x73,0x72,0x71,0x3f] + +s_nor_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x8f,0x56,0x34,0x12,0xaf] + +s_xnor_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x90] + +s_xnor_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x90] + +s_xnor_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x90] + +s_xnor_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x90] + +s_xnor_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x90] + +s_xnor_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x90] + +s_xnor_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x90] + +s_xnor_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x90] + +s_xnor_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x90] + +s_xnor_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x90] + +s_xnor_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x90] + +s_xnor_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x90] + +s_xnor_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x90] + +s_xnor_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x90] + +s_xnor_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x90] + +s_xnor_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x90] + +s_xnor_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x90] + +s_xnor_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x90] + +s_xnor_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x90] + +s_xnor_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x90] + +s_xnor_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x90] + +s_xnor_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x90] + +s_xnor_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x90,0x73,0x72,0x71,0x3f] + +s_xnor_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x90,0x56,0x34,0x12,0xaf] + +s_xnor_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x90] + +s_xnor_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x90] + +s_xnor_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x90] + +s_xnor_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x90] + +s_xnor_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x90] + +s_xnor_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x90] + +s_xnor_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x90] + +s_xnor_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x90] + +s_xnor_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x90] + +s_xnor_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x90,0x73,0x72,0x71,0x3f] + +s_xnor_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x90,0x56,0x34,0x12,0xaf] + +s_xnor_b64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0x90] + +s_xnor_b64 s[104:105], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0xe8,0x90] + +s_xnor_b64 s[0:1], s[102:103], s[100:101] +// GFX12: encoding: [0x66,0x64,0x80,0x90] + +s_xnor_b64 s[104:105], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0xe8,0x90] + +s_xnor_b64 s[104:105], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0xe8,0x90] + +s_xnor_b64 s[104:105], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xe8,0x90] + +s_xnor_b64 s[0:1], s[102:103], s[4:5] +// GFX12: encoding: [0x66,0x04,0x80,0x90] + +s_xnor_b64 s[0:1], s[2:3], s[100:101] +// GFX12: encoding: [0x02,0x64,0x80,0x90] + +s_xnor_b64 exec, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xfe,0x90] + +s_xnor_b64 vcc, s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0xea,0x90] + +s_xnor_b64 s[0:1], exec, s[4:5] +// GFX12: encoding: [0x7e,0x04,0x80,0x90] + +s_xnor_b64 s[0:1], vcc, s[4:5] +// GFX12: encoding: [0x6a,0x04,0x80,0x90] + +s_xnor_b64 s[0:1], 0, s[4:5] +// GFX12: encoding: [0x80,0x04,0x80,0x90] + +s_xnor_b64 s[0:1], -1, s[4:5] +// GFX12: encoding: [0xc1,0x04,0x80,0x90] + +s_xnor_b64 s[0:1], 0.5, s[4:5] +// GFX12: encoding: [0xf0,0x04,0x80,0x90] + +s_xnor_b64 s[0:1], -4.0, s[4:5] +// GFX12: encoding: [0xf7,0x04,0x80,0x90] + +s_xnor_b64 s[0:1], 0x3f717273, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x90,0x73,0x72,0x71,0x3f] + +s_xnor_b64 s[0:1], 0xaf123456, s[4:5] +// GFX12: encoding: [0xff,0x04,0x80,0x90,0x56,0x34,0x12,0xaf] + +s_xnor_b64 s[0:1], s[2:3], exec +// GFX12: encoding: [0x02,0x7e,0x80,0x90] + +s_xnor_b64 s[0:1], s[2:3], vcc +// GFX12: encoding: [0x02,0x6a,0x80,0x90] + +s_xnor_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x90] + +s_xnor_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x90] + +s_xnor_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x90] + +s_xnor_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x90] + +s_xnor_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x90,0x73,0x72,0x71,0x3f] + +s_xnor_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x90,0x56,0x34,0x12,0xaf] + +s_lshl_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x84] + +s_lshl_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x84] + +s_lshl_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x84] + +s_lshl_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x84] + +s_lshl_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x84] + +s_lshl_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x84] + +s_lshl_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x84] + +s_lshl_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x84] + +s_lshl_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x84] + +s_lshl_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x84] + +s_lshl_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x84] + +s_lshl_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x84] + +s_lshl_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x84] + +s_lshl_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x84] + +s_lshl_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x84] + +s_lshl_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x84] + +s_lshl_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x84] + +s_lshl_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x84] + +s_lshl_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x84] + +s_lshl_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x84] + +s_lshl_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x84] + +s_lshl_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x84] + +s_lshl_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x84,0x73,0x72,0x71,0x3f] + +s_lshl_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x84,0x56,0x34,0x12,0xaf] + +s_lshl_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x84] + +s_lshl_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x84] + +s_lshl_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x84] + +s_lshl_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x84] + +s_lshl_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x84] + +s_lshl_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x84] + +s_lshl_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x84] + +s_lshl_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x84] + +s_lshl_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x84] + +s_lshl_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x84,0x73,0x72,0x71,0x3f] + +s_lshl_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x84,0x56,0x34,0x12,0xaf] + +s_lshl_b64 s[0:1], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0x80,0x84] + +s_lshl_b64 s[104:105], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0xe8,0x84] + +s_lshl_b64 s[0:1], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0x80,0x84] + +s_lshl_b64 s[104:105], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0xe8,0x84] + +s_lshl_b64 s[104:105], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0xe8,0x84] + +s_lshl_b64 s[104:105], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xe8,0x84] + +s_lshl_b64 s[0:1], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0x80,0x84] + +s_lshl_b64 s[0:1], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0x80,0x84] + +s_lshl_b64 exec, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xfe,0x84] + +s_lshl_b64 vcc, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xea,0x84] + +s_lshl_b64 s[0:1], exec, s4 +// GFX12: encoding: [0x7e,0x04,0x80,0x84] + +s_lshl_b64 s[0:1], vcc, s4 +// GFX12: encoding: [0x6a,0x04,0x80,0x84] + +s_lshl_b64 s[0:1], 0, s4 +// GFX12: encoding: [0x80,0x04,0x80,0x84] + +s_lshl_b64 s[0:1], -1, s4 +// GFX12: encoding: [0xc1,0x04,0x80,0x84] + +s_lshl_b64 s[0:1], 0.5, s4 +// GFX12: encoding: [0xf0,0x04,0x80,0x84] + +s_lshl_b64 s[0:1], -4.0, s4 +// GFX12: encoding: [0xf7,0x04,0x80,0x84] + +s_lshl_b64 s[0:1], 0x3f717273, s4 +// GFX12: encoding: [0xff,0x04,0x80,0x84,0x73,0x72,0x71,0x3f] + +s_lshl_b64 s[0:1], 0xaf123456, s4 +// GFX12: encoding: [0xff,0x04,0x80,0x84,0x56,0x34,0x12,0xaf] + +s_lshl_b64 s[0:1], s[2:3], exec_lo +// GFX12: encoding: [0x02,0x7e,0x80,0x84] + +s_lshl_b64 s[0:1], s[2:3], vcc_lo +// GFX12: encoding: [0x02,0x6a,0x80,0x84] + +s_lshl_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x84] + +s_lshl_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x84] + +s_lshl_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x84] + +s_lshl_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x84] + +s_lshl_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x84,0x73,0x72,0x71,0x3f] + +s_lshl_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x84,0x56,0x34,0x12,0xaf] + +s_lshr_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x85] + +s_lshr_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x85] + +s_lshr_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x85] + +s_lshr_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x85] + +s_lshr_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x85] + +s_lshr_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x85] + +s_lshr_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x85] + +s_lshr_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x85] + +s_lshr_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x85] + +s_lshr_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x85] + +s_lshr_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x85] + +s_lshr_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x85] + +s_lshr_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x85] + +s_lshr_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x85] + +s_lshr_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x85] + +s_lshr_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x85] + +s_lshr_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x85] + +s_lshr_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x85] + +s_lshr_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x85] + +s_lshr_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x85] + +s_lshr_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x85] + +s_lshr_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x85] + +s_lshr_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x85,0x73,0x72,0x71,0x3f] + +s_lshr_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x85,0x56,0x34,0x12,0xaf] + +s_lshr_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x85] + +s_lshr_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x85] + +s_lshr_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x85] + +s_lshr_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x85] + +s_lshr_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x85] + +s_lshr_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x85] + +s_lshr_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x85] + +s_lshr_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x85] + +s_lshr_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x85] + +s_lshr_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x85,0x73,0x72,0x71,0x3f] + +s_lshr_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x85,0x56,0x34,0x12,0xaf] + +s_lshr_b64 s[0:1], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0x80,0x85] + +s_lshr_b64 s[104:105], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0xe8,0x85] + +s_lshr_b64 s[0:1], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0x80,0x85] + +s_lshr_b64 s[104:105], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0xe8,0x85] + +s_lshr_b64 s[104:105], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0xe8,0x85] + +s_lshr_b64 s[104:105], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xe8,0x85] + +s_lshr_b64 s[0:1], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0x80,0x85] + +s_lshr_b64 s[0:1], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0x80,0x85] + +s_lshr_b64 exec, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xfe,0x85] + +s_lshr_b64 vcc, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xea,0x85] + +s_lshr_b64 s[0:1], exec, s4 +// GFX12: encoding: [0x7e,0x04,0x80,0x85] + +s_lshr_b64 s[0:1], vcc, s4 +// GFX12: encoding: [0x6a,0x04,0x80,0x85] + +s_lshr_b64 s[0:1], 0, s4 +// GFX12: encoding: [0x80,0x04,0x80,0x85] + +s_lshr_b64 s[0:1], -1, s4 +// GFX12: encoding: [0xc1,0x04,0x80,0x85] + +s_lshr_b64 s[0:1], 0.5, s4 +// GFX12: encoding: [0xf0,0x04,0x80,0x85] + +s_lshr_b64 s[0:1], -4.0, s4 +// GFX12: encoding: [0xf7,0x04,0x80,0x85] + +s_lshr_b64 s[0:1], 0x3f717273, s4 +// GFX12: encoding: [0xff,0x04,0x80,0x85,0x73,0x72,0x71,0x3f] + +s_lshr_b64 s[0:1], 0xaf123456, s4 +// GFX12: encoding: [0xff,0x04,0x80,0x85,0x56,0x34,0x12,0xaf] + +s_lshr_b64 s[0:1], s[2:3], exec_lo +// GFX12: encoding: [0x02,0x7e,0x80,0x85] + +s_lshr_b64 s[0:1], s[2:3], vcc_lo +// GFX12: encoding: [0x02,0x6a,0x80,0x85] + +s_lshr_b64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x85] + +s_lshr_b64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x85] + +s_lshr_b64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x85] + +s_lshr_b64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x85] + +s_lshr_b64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x85,0x73,0x72,0x71,0x3f] + +s_lshr_b64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x85,0x56,0x34,0x12,0xaf] + +s_ashr_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x86] + +s_ashr_i32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x86] + +s_ashr_i32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x86] + +s_ashr_i32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x86] + +s_ashr_i32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x86] + +s_ashr_i32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x86] + +s_ashr_i32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x86] + +s_ashr_i32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x86] + +s_ashr_i32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x86] + +s_ashr_i32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x86] + +s_ashr_i32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x86] + +s_ashr_i32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x86] + +s_ashr_i32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x86] + +s_ashr_i32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x86] + +s_ashr_i32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x86] + +s_ashr_i32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x86] + +s_ashr_i32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x86] + +s_ashr_i32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x86] + +s_ashr_i32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x86] + +s_ashr_i32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x86] + +s_ashr_i32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x86] + +s_ashr_i32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x86] + +s_ashr_i32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x86,0x73,0x72,0x71,0x3f] + +s_ashr_i32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x86,0x56,0x34,0x12,0xaf] + +s_ashr_i32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x86] + +s_ashr_i32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x86] + +s_ashr_i32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x86] + +s_ashr_i32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x86] + +s_ashr_i32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x86] + +s_ashr_i32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x86] + +s_ashr_i32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x86] + +s_ashr_i32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x86] + +s_ashr_i32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x86] + +s_ashr_i32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x86,0x73,0x72,0x71,0x3f] + +s_ashr_i32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x86,0x56,0x34,0x12,0xaf] + +s_ashr_i64 s[0:1], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0x80,0x86] + +s_ashr_i64 s[104:105], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0xe8,0x86] + +s_ashr_i64 s[0:1], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0x80,0x86] + +s_ashr_i64 s[104:105], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0xe8,0x86] + +s_ashr_i64 s[104:105], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0xe8,0x86] + +s_ashr_i64 s[104:105], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xe8,0x86] + +s_ashr_i64 s[0:1], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0x80,0x86] + +s_ashr_i64 s[0:1], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0x80,0x86] + +s_ashr_i64 exec, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xfe,0x86] + +s_ashr_i64 vcc, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xea,0x86] + +s_ashr_i64 s[0:1], exec, s4 +// GFX12: encoding: [0x7e,0x04,0x80,0x86] + +s_ashr_i64 s[0:1], vcc, s4 +// GFX12: encoding: [0x6a,0x04,0x80,0x86] + +s_ashr_i64 s[0:1], 0, s4 +// GFX12: encoding: [0x80,0x04,0x80,0x86] + +s_ashr_i64 s[0:1], -1, s4 +// GFX12: encoding: [0xc1,0x04,0x80,0x86] + +s_ashr_i64 s[0:1], 0.5, s4 +// GFX12: encoding: [0xf0,0x04,0x80,0x86] + +s_ashr_i64 s[0:1], -4.0, s4 +// GFX12: encoding: [0xf7,0x04,0x80,0x86] + +s_ashr_i64 s[0:1], 0x3f717273, s4 +// GFX12: encoding: [0xff,0x04,0x80,0x86,0x73,0x72,0x71,0x3f] + +s_ashr_i64 s[0:1], 0xaf123456, s4 +// GFX12: encoding: [0xff,0x04,0x80,0x86,0x56,0x34,0x12,0xaf] + +s_ashr_i64 s[0:1], s[2:3], exec_lo +// GFX12: encoding: [0x02,0x7e,0x80,0x86] + +s_ashr_i64 s[0:1], s[2:3], vcc_lo +// GFX12: encoding: [0x02,0x6a,0x80,0x86] + +s_ashr_i64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x86] + +s_ashr_i64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x86] + +s_ashr_i64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x86] + +s_ashr_i64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x86] + +s_ashr_i64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x86,0x73,0x72,0x71,0x3f] + +s_ashr_i64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x86,0x56,0x34,0x12,0xaf] + +s_bfm_b32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x95] + +s_bfm_b32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x95] + +s_bfm_b32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x95] + +s_bfm_b32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x95] + +s_bfm_b32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x95] + +s_bfm_b32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x95] + +s_bfm_b32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x95] + +s_bfm_b32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x95] + +s_bfm_b32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x95] + +s_bfm_b32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x95] + +s_bfm_b32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x95] + +s_bfm_b32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x95] + +s_bfm_b32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x95] + +s_bfm_b32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x95] + +s_bfm_b32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x95] + +s_bfm_b32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x95] + +s_bfm_b32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x95] + +s_bfm_b32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x95] + +s_bfm_b32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x95] + +s_bfm_b32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x95] + +s_bfm_b32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x95] + +s_bfm_b32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x95] + +s_bfm_b32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x95,0x73,0x72,0x71,0x3f] + +s_bfm_b32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x95,0x56,0x34,0x12,0xaf] + +s_bfm_b32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x95] + +s_bfm_b32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x95] + +s_bfm_b32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x95] + +s_bfm_b32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x95] + +s_bfm_b32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x95] + +s_bfm_b32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x95] + +s_bfm_b32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x95] + +s_bfm_b32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x95] + +s_bfm_b32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x95] + +s_bfm_b32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x95,0x73,0x72,0x71,0x3f] + +s_bfm_b32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x95,0x56,0x34,0x12,0xaf] + +s_bfm_b64 s[0:1], s2, s3 +// GFX12: encoding: [0x02,0x03,0x80,0x95] + +s_bfm_b64 s[104:105], s103, s102 +// GFX12: encoding: [0x67,0x66,0xe8,0x95] + +s_bfm_b64 s[0:1], s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x95] + +s_bfm_b64 s[104:105], s2, s103 +// GFX12: encoding: [0x02,0x67,0xe8,0x95] + +s_bfm_b64 s[104:105], s104, s3 +// GFX12: encoding: [0x68,0x03,0xe8,0x95] + +s_bfm_b64 s[104:105], s2, s3 +// GFX12: encoding: [0x02,0x03,0xe8,0x95] + +s_bfm_b64 s[0:1], s104, s3 +// GFX12: encoding: [0x68,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], s2, s103 +// GFX12: encoding: [0x02,0x67,0x80,0x95] + +s_bfm_b64 exec, s2, s3 +// GFX12: encoding: [0x02,0x03,0xfe,0x95] + +s_bfm_b64 vcc, s2, s3 +// GFX12: encoding: [0x02,0x03,0xea,0x95] + +s_bfm_b64 s[0:1], exec_lo, s3 +// GFX12: encoding: [0x7e,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], exec_hi, s3 +// GFX12: encoding: [0x7f,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], vcc_lo, s3 +// GFX12: encoding: [0x6a,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], vcc_hi, s3 +// GFX12: encoding: [0x6b,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], m0, s3 +// GFX12: encoding: [0x7d,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], 0, s3 +// GFX12: encoding: [0x80,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], -1, s3 +// GFX12: encoding: [0xc1,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], 0.5, s3 +// GFX12: encoding: [0xf0,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], -4.0, s3 +// GFX12: encoding: [0xf7,0x03,0x80,0x95] + +s_bfm_b64 s[0:1], 0x3f717273, s3 +// GFX12: encoding: [0xff,0x03,0x80,0x95,0x73,0x72,0x71,0x3f] + +s_bfm_b64 s[0:1], 0xaf123456, s3 +// GFX12: encoding: [0xff,0x03,0x80,0x95,0x56,0x34,0x12,0xaf] + +s_bfm_b64 s[0:1], s2, exec_lo +// GFX12: encoding: [0x02,0x7e,0x80,0x95] + +s_bfm_b64 s[0:1], s2, exec_hi +// GFX12: encoding: [0x02,0x7f,0x80,0x95] + +s_bfm_b64 s[0:1], s2, vcc_lo +// GFX12: encoding: [0x02,0x6a,0x80,0x95] + +s_bfm_b64 s[0:1], s2, vcc_hi +// GFX12: encoding: [0x02,0x6b,0x80,0x95] + +s_bfm_b64 s[0:1], s2, m0 +// GFX12: encoding: [0x02,0x7d,0x80,0x95] + +s_bfm_b64 s[0:1], s2, 0 +// GFX12: encoding: [0x02,0x80,0x80,0x95] + +s_bfm_b64 s[0:1], s2, -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x95] + +s_bfm_b64 s[0:1], s2, 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x95] + +s_bfm_b64 s[0:1], s2, -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x95] + +s_bfm_b64 s[0:1], s2, 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x95,0x73,0x72,0x71,0x3f] + +s_bfm_b64 s[0:1], s2, 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x95,0x56,0x34,0x12,0xaf] + +s_mul_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x96] + +s_mul_i32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x96] + +s_mul_i32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x96] + +s_mul_i32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x96] + +s_mul_i32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x96] + +s_mul_i32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x96] + +s_mul_i32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x96] + +s_mul_i32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x96] + +s_mul_i32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x96] + +s_mul_i32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x96] + +s_mul_i32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x96] + +s_mul_i32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x96] + +s_mul_i32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x96] + +s_mul_i32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x96] + +s_mul_i32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x96] + +s_mul_i32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x96] + +s_mul_i32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x96] + +s_mul_i32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x96] + +s_mul_i32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x96] + +s_mul_i32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x96] + +s_mul_i32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x96] + +s_mul_i32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x96] + +s_mul_i32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x96,0x73,0x72,0x71,0x3f] + +s_mul_i32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x96,0x56,0x34,0x12,0xaf] + +s_mul_i32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x96] + +s_mul_i32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x96] + +s_mul_i32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x96] + +s_mul_i32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x96] + +s_mul_i32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x96] + +s_mul_i32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x96] + +s_mul_i32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x96] + +s_mul_i32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x96] + +s_mul_i32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x96] + +s_mul_i32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x96,0x73,0x72,0x71,0x3f] + +s_mul_i32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x96,0x56,0x34,0x12,0xaf] + +s_bfe_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x93] + +s_bfe_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x93] + +s_bfe_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x93] + +s_bfe_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x93] + +s_bfe_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x93] + +s_bfe_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x93] + +s_bfe_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x93] + +s_bfe_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x93] + +s_bfe_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x93] + +s_bfe_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x93] + +s_bfe_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x93] + +s_bfe_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x93] + +s_bfe_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x93] + +s_bfe_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x93] + +s_bfe_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x93] + +s_bfe_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x93] + +s_bfe_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x93] + +s_bfe_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x93] + +s_bfe_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x93] + +s_bfe_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x93] + +s_bfe_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x93] + +s_bfe_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x93] + +s_bfe_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x93,0x73,0x72,0x71,0x3f] + +s_bfe_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x93,0x56,0x34,0x12,0xaf] + +s_bfe_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x93] + +s_bfe_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x93] + +s_bfe_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x93] + +s_bfe_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x93] + +s_bfe_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x93] + +s_bfe_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x93] + +s_bfe_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x93] + +s_bfe_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x93] + +s_bfe_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x93] + +s_bfe_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x93,0x73,0x72,0x71,0x3f] + +s_bfe_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x93,0x56,0x34,0x12,0xaf] + +s_bfe_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x93] + +s_bfe_i32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x93] + +s_bfe_i32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x93] + +s_bfe_i32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x93] + +s_bfe_i32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x93] + +s_bfe_i32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x93] + +s_bfe_i32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x93] + +s_bfe_i32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x93] + +s_bfe_i32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x93] + +s_bfe_i32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x93] + +s_bfe_i32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x93] + +s_bfe_i32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x93] + +s_bfe_i32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x93] + +s_bfe_i32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x93] + +s_bfe_i32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x93] + +s_bfe_i32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x93] + +s_bfe_i32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x93] + +s_bfe_i32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x93] + +s_bfe_i32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x93] + +s_bfe_i32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x93] + +s_bfe_i32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x93] + +s_bfe_i32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x93] + +s_bfe_i32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x93,0x73,0x72,0x71,0x3f] + +s_bfe_i32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x93,0x56,0x34,0x12,0xaf] + +s_bfe_i32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x93] + +s_bfe_i32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x93] + +s_bfe_i32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x93] + +s_bfe_i32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x93] + +s_bfe_i32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x93] + +s_bfe_i32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x93] + +s_bfe_i32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x93] + +s_bfe_i32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x93] + +s_bfe_i32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x93] + +s_bfe_i32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x93,0x73,0x72,0x71,0x3f] + +s_bfe_i32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x93,0x56,0x34,0x12,0xaf] + +s_bfe_u64 s[0:1], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0x00,0x94] + +s_bfe_u64 s[104:105], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0x68,0x94] + +s_bfe_u64 s[0:1], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0x00,0x94] + +s_bfe_u64 s[104:105], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0x68,0x94] + +s_bfe_u64 s[104:105], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0x68,0x94] + +s_bfe_u64 s[104:105], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0x68,0x94] + +s_bfe_u64 s[0:1], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0x00,0x94] + +s_bfe_u64 s[0:1], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0x00,0x94] + +s_bfe_u64 exec, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0x7e,0x94] + +s_bfe_u64 vcc, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0x6a,0x94] + +s_bfe_u64 s[0:1], exec, s4 +// GFX12: encoding: [0x7e,0x04,0x00,0x94] + +s_bfe_u64 s[0:1], vcc, s4 +// GFX12: encoding: [0x6a,0x04,0x00,0x94] + +s_bfe_u64 s[0:1], 0, s4 +// GFX12: encoding: [0x80,0x04,0x00,0x94] + +s_bfe_u64 s[0:1], -1, s4 +// GFX12: encoding: [0xc1,0x04,0x00,0x94] + +s_bfe_u64 s[0:1], 0.5, s4 +// GFX12: encoding: [0xf0,0x04,0x00,0x94] + +s_bfe_u64 s[0:1], -4.0, s4 +// GFX12: encoding: [0xf7,0x04,0x00,0x94] + +s_bfe_u64 s[0:1], 0x3f717273, s4 +// GFX12: encoding: [0xff,0x04,0x00,0x94,0x73,0x72,0x71,0x3f] + +s_bfe_u64 s[0:1], 0xaf123456, s4 +// GFX12: encoding: [0xff,0x04,0x00,0x94,0x56,0x34,0x12,0xaf] + +s_bfe_u64 s[0:1], s[2:3], exec_lo +// GFX12: encoding: [0x02,0x7e,0x00,0x94] + +s_bfe_u64 s[0:1], s[2:3], vcc_lo +// GFX12: encoding: [0x02,0x6a,0x00,0x94] + +s_bfe_u64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x00,0x94] + +s_bfe_u64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x00,0x94] + +s_bfe_u64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x00,0x94] + +s_bfe_u64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x00,0x94] + +s_bfe_u64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x00,0x94,0x73,0x72,0x71,0x3f] + +s_bfe_u64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x00,0x94,0x56,0x34,0x12,0xaf] + +s_bfe_i64 s[0:1], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0x80,0x94] + +s_bfe_i64 s[104:105], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0xe8,0x94] + +s_bfe_i64 s[0:1], s[102:103], s100 +// GFX12: encoding: [0x66,0x64,0x80,0x94] + +s_bfe_i64 s[104:105], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0xe8,0x94] + +s_bfe_i64 s[104:105], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0xe8,0x94] + +s_bfe_i64 s[104:105], s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xe8,0x94] + +s_bfe_i64 s[0:1], s[102:103], s4 +// GFX12: encoding: [0x66,0x04,0x80,0x94] + +s_bfe_i64 s[0:1], s[2:3], s100 +// GFX12: encoding: [0x02,0x64,0x80,0x94] + +s_bfe_i64 exec, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xfe,0x94] + +s_bfe_i64 vcc, s[2:3], s4 +// GFX12: encoding: [0x02,0x04,0xea,0x94] + +s_bfe_i64 s[0:1], exec, s4 +// GFX12: encoding: [0x7e,0x04,0x80,0x94] + +s_bfe_i64 s[0:1], vcc, s4 +// GFX12: encoding: [0x6a,0x04,0x80,0x94] + +s_bfe_i64 s[0:1], 0, s4 +// GFX12: encoding: [0x80,0x04,0x80,0x94] + +s_bfe_i64 s[0:1], -1, s4 +// GFX12: encoding: [0xc1,0x04,0x80,0x94] + +s_bfe_i64 s[0:1], 0.5, s4 +// GFX12: encoding: [0xf0,0x04,0x80,0x94] + +s_bfe_i64 s[0:1], -4.0, s4 +// GFX12: encoding: [0xf7,0x04,0x80,0x94] + +s_bfe_i64 s[0:1], 0x3f717273, s4 +// GFX12: encoding: [0xff,0x04,0x80,0x94,0x73,0x72,0x71,0x3f] + +s_bfe_i64 s[0:1], 0xaf123456, s4 +// GFX12: encoding: [0xff,0x04,0x80,0x94,0x56,0x34,0x12,0xaf] + +s_bfe_i64 s[0:1], s[2:3], exec_lo +// GFX12: encoding: [0x02,0x7e,0x80,0x94] + +s_bfe_i64 s[0:1], s[2:3], vcc_lo +// GFX12: encoding: [0x02,0x6a,0x80,0x94] + +s_bfe_i64 s[0:1], s[2:3], 0 +// GFX12: encoding: [0x02,0x80,0x80,0x94] + +s_bfe_i64 s[0:1], s[2:3], -1 +// GFX12: encoding: [0x02,0xc1,0x80,0x94] + +s_bfe_i64 s[0:1], s[2:3], 0.5 +// GFX12: encoding: [0x02,0xf0,0x80,0x94] + +s_bfe_i64 s[0:1], s[2:3], -4.0 +// GFX12: encoding: [0x02,0xf7,0x80,0x94] + +s_bfe_i64 s[0:1], s[2:3], 0x3f717273 +// GFX12: encoding: [0x02,0xff,0x80,0x94,0x73,0x72,0x71,0x3f] + +s_bfe_i64 s[0:1], s[2:3], 0xaf123456 +// GFX12: encoding: [0x02,0xff,0x80,0x94,0x56,0x34,0x12,0xaf] + +s_absdiff_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x83] + +s_absdiff_i32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x83] + +s_absdiff_i32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x83] + +s_absdiff_i32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x83] + +s_absdiff_i32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x83] + +s_absdiff_i32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x83] + +s_absdiff_i32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x83] + +s_absdiff_i32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x83] + +s_absdiff_i32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x83] + +s_absdiff_i32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x83] + +s_absdiff_i32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x83] + +s_absdiff_i32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x83] + +s_absdiff_i32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x83] + +s_absdiff_i32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x83] + +s_absdiff_i32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x83] + +s_absdiff_i32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x83] + +s_absdiff_i32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x83] + +s_absdiff_i32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x83] + +s_absdiff_i32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x83] + +s_absdiff_i32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x83] + +s_absdiff_i32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x83] + +s_absdiff_i32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x83] + +s_absdiff_i32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x83,0x73,0x72,0x71,0x3f] + +s_absdiff_i32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x83,0x56,0x34,0x12,0xaf] + +s_absdiff_i32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x83] + +s_absdiff_i32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x83] + +s_absdiff_i32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x83] + +s_absdiff_i32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x83] + +s_absdiff_i32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x83] + +s_absdiff_i32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x83] + +s_absdiff_i32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x83] + +s_absdiff_i32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x83] + +s_absdiff_i32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x83] + +s_absdiff_i32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x83,0x73,0x72,0x71,0x3f] + +s_absdiff_i32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x83,0x56,0x34,0x12,0xaf] + +s_lshl1_add_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x87] + +s_lshl1_add_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x87] + +s_lshl1_add_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x87] + +s_lshl1_add_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x87] + +s_lshl1_add_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x87] + +s_lshl1_add_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x87] + +s_lshl1_add_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x87] + +s_lshl1_add_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x87] + +s_lshl1_add_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x87] + +s_lshl1_add_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x87] + +s_lshl1_add_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x87] + +s_lshl1_add_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x87] + +s_lshl1_add_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x87] + +s_lshl1_add_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x87,0x73,0x72,0x71,0x3f] + +s_lshl1_add_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x87,0x56,0x34,0x12,0xaf] + +s_lshl1_add_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x87] + +s_lshl1_add_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x87] + +s_lshl1_add_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x87] + +s_lshl1_add_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x87] + +s_lshl1_add_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x87] + +s_lshl1_add_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x87] + +s_lshl1_add_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x87] + +s_lshl1_add_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x87] + +s_lshl1_add_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x87] + +s_lshl1_add_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x87,0x73,0x72,0x71,0x3f] + +s_lshl1_add_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x87,0x56,0x34,0x12,0xaf] + +s_lshl2_add_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x87] + +s_lshl2_add_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x87] + +s_lshl2_add_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x87] + +s_lshl2_add_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x87] + +s_lshl2_add_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x87] + +s_lshl2_add_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x87] + +s_lshl2_add_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x87] + +s_lshl2_add_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x87] + +s_lshl2_add_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x87] + +s_lshl2_add_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x87] + +s_lshl2_add_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x87] + +s_lshl2_add_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x87] + +s_lshl2_add_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x87] + +s_lshl2_add_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x87,0x73,0x72,0x71,0x3f] + +s_lshl2_add_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x87,0x56,0x34,0x12,0xaf] + +s_lshl2_add_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x87] + +s_lshl2_add_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x87] + +s_lshl2_add_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x87] + +s_lshl2_add_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x87] + +s_lshl2_add_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x87] + +s_lshl2_add_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x87] + +s_lshl2_add_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x87] + +s_lshl2_add_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x87] + +s_lshl2_add_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x87] + +s_lshl2_add_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x87,0x73,0x72,0x71,0x3f] + +s_lshl2_add_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x87,0x56,0x34,0x12,0xaf] + +s_lshl3_add_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x88] + +s_lshl3_add_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x88] + +s_lshl3_add_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x88] + +s_lshl3_add_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x88] + +s_lshl3_add_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x88] + +s_lshl3_add_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x88] + +s_lshl3_add_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x88] + +s_lshl3_add_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x88] + +s_lshl3_add_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x88] + +s_lshl3_add_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x88] + +s_lshl3_add_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x88] + +s_lshl3_add_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x88] + +s_lshl3_add_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x88] + +s_lshl3_add_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x88,0x73,0x72,0x71,0x3f] + +s_lshl3_add_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x88,0x56,0x34,0x12,0xaf] + +s_lshl3_add_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x88] + +s_lshl3_add_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x88] + +s_lshl3_add_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x88] + +s_lshl3_add_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x88] + +s_lshl3_add_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x88] + +s_lshl3_add_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x88] + +s_lshl3_add_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x88] + +s_lshl3_add_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x88] + +s_lshl3_add_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x88] + +s_lshl3_add_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x88,0x73,0x72,0x71,0x3f] + +s_lshl3_add_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x88,0x56,0x34,0x12,0xaf] + +s_lshl4_add_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x88] + +s_lshl4_add_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x88] + +s_lshl4_add_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x88] + +s_lshl4_add_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x88] + +s_lshl4_add_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x88] + +s_lshl4_add_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x88] + +s_lshl4_add_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x88] + +s_lshl4_add_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x88] + +s_lshl4_add_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x88] + +s_lshl4_add_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x88] + +s_lshl4_add_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x88] + +s_lshl4_add_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x88] + +s_lshl4_add_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x88] + +s_lshl4_add_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x88,0x73,0x72,0x71,0x3f] + +s_lshl4_add_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x88,0x56,0x34,0x12,0xaf] + +s_lshl4_add_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x88] + +s_lshl4_add_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x88] + +s_lshl4_add_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x88] + +s_lshl4_add_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x88] + +s_lshl4_add_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x88] + +s_lshl4_add_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x88] + +s_lshl4_add_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x88] + +s_lshl4_add_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x88] + +s_lshl4_add_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x88] + +s_lshl4_add_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x88,0x73,0x72,0x71,0x3f] + +s_lshl4_add_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x88,0x56,0x34,0x12,0xaf] + +s_pack_ll_b32_b16 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x99] + +s_pack_ll_b32_b16 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x99] + +s_pack_ll_b32_b16 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x99] + +s_pack_ll_b32_b16 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x99] + +s_pack_ll_b32_b16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x99] + +s_pack_ll_b32_b16 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x99] + +s_pack_ll_b32_b16 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x99] + +s_pack_ll_b32_b16 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x99] + +s_pack_ll_b32_b16 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x99] + +s_pack_ll_b32_b16 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x99] + +s_pack_ll_b32_b16 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x99] + +s_pack_ll_b32_b16 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x99] + +s_pack_ll_b32_b16 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x99,0x73,0x72,0x71,0x3f] + +s_pack_ll_b32_b16 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x99,0x56,0x34,0x12,0xaf] + +s_pack_ll_b32_b16 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x99] + +s_pack_ll_b32_b16 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x99,0x73,0x72,0x71,0x3f] + +s_pack_ll_b32_b16 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x99,0x56,0x34,0x12,0xaf] + +s_pack_lh_b32_b16 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x99] + +s_pack_lh_b32_b16 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x99] + +s_pack_lh_b32_b16 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x99] + +s_pack_lh_b32_b16 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x99] + +s_pack_lh_b32_b16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x99] + +s_pack_lh_b32_b16 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x99] + +s_pack_lh_b32_b16 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x99] + +s_pack_lh_b32_b16 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x99] + +s_pack_lh_b32_b16 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x99] + +s_pack_lh_b32_b16 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x99] + +s_pack_lh_b32_b16 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x99] + +s_pack_lh_b32_b16 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x99] + +s_pack_lh_b32_b16 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x99,0x73,0x72,0x71,0x3f] + +s_pack_lh_b32_b16 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x99,0x56,0x34,0x12,0xaf] + +s_pack_lh_b32_b16 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x99] + +s_pack_lh_b32_b16 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x99,0x73,0x72,0x71,0x3f] + +s_pack_lh_b32_b16 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x99,0x56,0x34,0x12,0xaf] + +s_pack_hh_b32_b16 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x9a] + +s_pack_hh_b32_b16 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x9a] + +s_pack_hh_b32_b16 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x9a] + +s_pack_hh_b32_b16 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x9a] + +s_pack_hh_b32_b16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x9a] + +s_pack_hh_b32_b16 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x9a] + +s_pack_hh_b32_b16 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x9a] + +s_pack_hh_b32_b16 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x9a] + +s_pack_hh_b32_b16 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x9a] + +s_pack_hh_b32_b16 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x9a] + +s_pack_hh_b32_b16 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x9a] + +s_pack_hh_b32_b16 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x9a] + +s_pack_hh_b32_b16 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x9a,0x73,0x72,0x71,0x3f] + +s_pack_hh_b32_b16 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x9a,0x56,0x34,0x12,0xaf] + +s_pack_hh_b32_b16 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x9a] + +s_pack_hh_b32_b16 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x9a,0x73,0x72,0x71,0x3f] + +s_pack_hh_b32_b16 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x9a,0x56,0x34,0x12,0xaf] + +s_mul_hi_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x96] + +s_mul_hi_u32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0xe9,0x96] + +s_mul_hi_u32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x80,0x96] + +s_mul_hi_u32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0xe9,0x96] + +s_mul_hi_u32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0xe9,0x96] + +s_mul_hi_u32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0x96] + +s_mul_hi_u32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x80,0x96] + +s_mul_hi_u32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x80,0x96] + +s_mul_hi_u32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfe,0x96] + +s_mul_hi_u32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xff,0x96] + +s_mul_hi_u32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0xea,0x96] + +s_mul_hi_u32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0xeb,0x96] + +s_mul_hi_u32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0xfd,0x96] + +s_mul_hi_u32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x80,0x96] + +s_mul_hi_u32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x80,0x96] + +s_mul_hi_u32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x80,0x96] + +s_mul_hi_u32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x80,0x96] + +s_mul_hi_u32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x80,0x96] + +s_mul_hi_u32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x80,0x96] + +s_mul_hi_u32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x80,0x96] + +s_mul_hi_u32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x80,0x96] + +s_mul_hi_u32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x80,0x96] + +s_mul_hi_u32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x96,0x73,0x72,0x71,0x3f] + +s_mul_hi_u32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x80,0x96,0x56,0x34,0x12,0xaf] + +s_mul_hi_u32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x80,0x96] + +s_mul_hi_u32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x80,0x96] + +s_mul_hi_u32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x80,0x96] + +s_mul_hi_u32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x80,0x96] + +s_mul_hi_u32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x80,0x96] + +s_mul_hi_u32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x80,0x96] + +s_mul_hi_u32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x80,0x96] + +s_mul_hi_u32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x80,0x96] + +s_mul_hi_u32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x80,0x96] + +s_mul_hi_u32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x80,0x96,0x73,0x72,0x71,0x3f] + +s_mul_hi_u32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x80,0x96,0x56,0x34,0x12,0xaf] + +s_mul_hi_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x97] + +s_mul_hi_i32 s105, s104, s103 +// GFX12: encoding: [0x68,0x67,0x69,0x97] + +s_mul_hi_i32 s0, s104, s103 +// GFX12: encoding: [0x68,0x67,0x00,0x97] + +s_mul_hi_i32 s105, s1, s103 +// GFX12: encoding: [0x01,0x67,0x69,0x97] + +s_mul_hi_i32 s105, s104, s2 +// GFX12: encoding: [0x68,0x02,0x69,0x97] + +s_mul_hi_i32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0x97] + +s_mul_hi_i32 s0, s104, s2 +// GFX12: encoding: [0x68,0x02,0x00,0x97] + +s_mul_hi_i32 s0, s1, s103 +// GFX12: encoding: [0x01,0x67,0x00,0x97] + +s_mul_hi_i32 exec_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7e,0x97] + +s_mul_hi_i32 exec_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7f,0x97] + +s_mul_hi_i32 vcc_lo, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6a,0x97] + +s_mul_hi_i32 vcc_hi, s1, s2 +// GFX12: encoding: [0x01,0x02,0x6b,0x97] + +s_mul_hi_i32 m0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x7d,0x97] + +s_mul_hi_i32 s0, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x00,0x97] + +s_mul_hi_i32 s0, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x00,0x97] + +s_mul_hi_i32 s0, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x00,0x97] + +s_mul_hi_i32 s0, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x00,0x97] + +s_mul_hi_i32 s0, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x00,0x97] + +s_mul_hi_i32 s0, 0, s2 +// GFX12: encoding: [0x80,0x02,0x00,0x97] + +s_mul_hi_i32 s0, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x00,0x97] + +s_mul_hi_i32 s0, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x00,0x97] + +s_mul_hi_i32 s0, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x00,0x97] + +s_mul_hi_i32 s0, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x97,0x73,0x72,0x71,0x3f] + +s_mul_hi_i32 s0, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x00,0x97,0x56,0x34,0x12,0xaf] + +s_mul_hi_i32 s0, s1, exec_lo +// GFX12: encoding: [0x01,0x7e,0x00,0x97] + +s_mul_hi_i32 s0, s1, exec_hi +// GFX12: encoding: [0x01,0x7f,0x00,0x97] + +s_mul_hi_i32 s0, s1, vcc_lo +// GFX12: encoding: [0x01,0x6a,0x00,0x97] + +s_mul_hi_i32 s0, s1, vcc_hi +// GFX12: encoding: [0x01,0x6b,0x00,0x97] + +s_mul_hi_i32 s0, s1, m0 +// GFX12: encoding: [0x01,0x7d,0x00,0x97] + +s_mul_hi_i32 s0, s1, 0 +// GFX12: encoding: [0x01,0x80,0x00,0x97] + +s_mul_hi_i32 s0, s1, -1 +// GFX12: encoding: [0x01,0xc1,0x00,0x97] + +s_mul_hi_i32 s0, s1, 0.5 +// GFX12: encoding: [0x01,0xf0,0x00,0x97] + +s_mul_hi_i32 s0, s1, -4.0 +// GFX12: encoding: [0x01,0xf7,0x00,0x97] + +s_mul_hi_i32 s0, s1, 0x3f717273 +// GFX12: encoding: [0x01,0xff,0x00,0x97,0x73,0x72,0x71,0x3f] + +s_mul_hi_i32 s0, s1, 0xaf123456 +// GFX12: encoding: [0x01,0xff,0x00,0x97,0x56,0x34,0x12,0xaf] + +s_or_not1_b32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0x92] + +s_or_not1_b32 s5, s105, s105 +// GFX12: encoding: [0x69,0x69,0x05,0x92] + +s_or_not1_b32 s5, vcc_lo, ttmp15 +// GFX12: encoding: [0x6a,0x7b,0x05,0x92] + +s_or_not1_b32 s5, vcc_hi, 0xaf123456 +// GFX12: encoding: [0x6b,0xff,0x05,0x92,0x56,0x34,0x12,0xaf] + +s_or_not1_b32 s5, ttmp15, src_scc +// GFX12: encoding: [0x7b,0xfd,0x05,0x92] + +s_or_not1_b32 s105, m0, 0.5 +// GFX12: encoding: [0x7d,0xf0,0x69,0x92] + +s_or_not1_b32 vcc_lo, exec_lo, -1 +// GFX12: encoding: [0x7e,0xc1,0x6a,0x92] + +s_or_not1_b32 vcc_hi, exec_hi, null +// GFX12: encoding: [0x7f,0x7c,0x6b,0x92] + +s_or_not1_b32 ttmp15, null, exec_lo +// GFX12: encoding: [0x7c,0x7e,0x7b,0x92] + +s_or_not1_b32 m0, -1, exec_hi +// GFX12: encoding: [0xc1,0x7f,0x7d,0x92] + +s_or_not1_b32 exec_lo, 0.5, m0 +// GFX12: encoding: [0xf0,0x7d,0x7e,0x92] + +s_or_not1_b32 exec_hi, src_scc, vcc_lo +// GFX12: encoding: [0xfd,0x6a,0x7f,0x92] + +s_or_not1_b32 null, 0xaf123456, vcc_hi +// GFX12: encoding: [0xff,0x6b,0x7c,0x92,0x56,0x34,0x12,0xaf] + +s_pack_hl_b32_b16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0x9a] + +s_pack_hl_b32_b16 s5, s105, s105 +// GFX12: encoding: [0x69,0x69,0x85,0x9a] + +s_pack_hl_b32_b16 s5, vcc_lo, ttmp15 +// GFX12: encoding: [0x6a,0x7b,0x85,0x9a] + +s_pack_hl_b32_b16 s5, vcc_hi, 0xfe0b +// GFX12: encoding: [0x6b,0xff,0x85,0x9a,0x0b,0xfe,0x00,0x00] + +s_pack_hl_b32_b16 s5, ttmp15, src_scc +// GFX12: encoding: [0x7b,0xfd,0x85,0x9a] + +s_pack_hl_b32_b16 s105, m0, 0.5 +// GFX12: encoding: [0x7d,0xf0,0xe9,0x9a] + +s_pack_hl_b32_b16 vcc_lo, exec_lo, -1 +// GFX12: encoding: [0x7e,0xc1,0xea,0x9a] + +s_pack_hl_b32_b16 vcc_hi, exec_hi, null +// GFX12: encoding: [0x7f,0x7c,0xeb,0x9a] + +s_pack_hl_b32_b16 ttmp15, null, exec_lo +// GFX12: encoding: [0x7c,0x7e,0xfb,0x9a] + +s_pack_hl_b32_b16 m0, -1, exec_hi +// GFX12: encoding: [0xc1,0x7f,0xfd,0x9a] + +s_pack_hl_b32_b16 exec_lo, 0.5, m0 +// GFX12: encoding: [0xf0,0x7d,0xfe,0x9a] + +s_pack_hl_b32_b16 exec_hi, src_scc, vcc_lo +// GFX12: encoding: [0xfd,0x6a,0xff,0x9a] + +s_pack_hl_b32_b16 null, 0xaf123456, vcc_hi +// GFX12: encoding: [0xff,0x6b,0xfc,0x9a,0x56,0x34,0x12,0xaf] + +s_and_not1_b32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0x91] + +s_and_not1_b32 s5, s105, s105 +// GFX12: encoding: [0x69,0x69,0x05,0x91] + +s_and_not1_b32 s5, vcc_lo, ttmp15 +// GFX12: encoding: [0x6a,0x7b,0x05,0x91] + +s_and_not1_b32 s5, vcc_hi, 0xaf123456 +// GFX12: encoding: [0x6b,0xff,0x05,0x91,0x56,0x34,0x12,0xaf] + +s_and_not1_b32 s5, ttmp15, src_scc +// GFX12: encoding: [0x7b,0xfd,0x05,0x91] + +s_and_not1_b32 s105, m0, 0.5 +// GFX12: encoding: [0x7d,0xf0,0x69,0x91] + +s_and_not1_b32 vcc_lo, exec_lo, -1 +// GFX12: encoding: [0x7e,0xc1,0x6a,0x91] + +s_and_not1_b32 vcc_hi, exec_hi, null +// GFX12: encoding: [0x7f,0x7c,0x6b,0x91] + +s_and_not1_b32 ttmp15, null, exec_lo +// GFX12: encoding: [0x7c,0x7e,0x7b,0x91] + +s_and_not1_b32 m0, -1, exec_hi +// GFX12: encoding: [0xc1,0x7f,0x7d,0x91] + +s_and_not1_b32 exec_lo, 0.5, m0 +// GFX12: encoding: [0xf0,0x7d,0x7e,0x91] + +s_and_not1_b32 exec_hi, src_scc, vcc_lo +// GFX12: encoding: [0xfd,0x6a,0x7f,0x91] + +s_and_not1_b32 null, 0xaf123456, vcc_hi +// GFX12: encoding: [0xff,0x6b,0x7c,0x91,0x56,0x34,0x12,0xaf] + +s_and_not1_b64 s[10:11], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x8a,0x91] + +s_and_not1_b64 s[10:11], s[104:105], s[104:105] +// GFX12: encoding: [0x68,0x68,0x8a,0x91] + +s_and_not1_b64 s[10:11], vcc, ttmp[14:15] +// GFX12: encoding: [0x6a,0x7a,0x8a,0x91] + +s_and_not1_b64 s[10:11], ttmp[14:15], 0xaf123456 +// GFX12: encoding: [0x7a,0xff,0x8a,0x91,0x56,0x34,0x12,0xaf] + +s_and_not1_b64 s[10:11], exec, src_scc +// GFX12: encoding: [0x7e,0xfd,0x8a,0x91] + +s_and_not1_b64 s[104:105], null, 0.5 +// GFX12: encoding: [0x7c,0xf0,0xe8,0x91] + +s_and_not1_b64 vcc, -1, -1 +// GFX12: encoding: [0xc1,0xc1,0xea,0x91] + +s_and_not1_b64 ttmp[14:15], 0.5, null +// GFX12: encoding: [0xf0,0x7c,0xfa,0x91] + +s_and_not1_b64 exec, src_scc, exec +// GFX12: encoding: [0xfd,0x7e,0xfe,0x91] + +s_and_not1_b64 null, 0xaf123456, vcc +// GFX12: encoding: [0xff,0x6a,0xfc,0x91,0x56,0x34,0x12,0xaf] + +s_or_not1_b64 s[10:11], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x8a,0x92] + +s_or_not1_b64 s[10:11], s[104:105], s[104:105] +// GFX12: encoding: [0x68,0x68,0x8a,0x92] + +s_or_not1_b64 s[10:11], vcc, ttmp[14:15] +// GFX12: encoding: [0x6a,0x7a,0x8a,0x92] + +s_or_not1_b64 s[10:11], ttmp[14:15], 0xaf123456 +// GFX12: encoding: [0x7a,0xff,0x8a,0x92,0x56,0x34,0x12,0xaf] + +s_or_not1_b64 s[10:11], exec, src_scc +// GFX12: encoding: [0x7e,0xfd,0x8a,0x92] + +s_or_not1_b64 s[104:105], null, 0.5 +// GFX12: encoding: [0x7c,0xf0,0xe8,0x92] + +s_or_not1_b64 vcc, -1, -1 +// GFX12: encoding: [0xc1,0xc1,0xea,0x92] + +s_or_not1_b64 ttmp[14:15], 0.5, null +// GFX12: encoding: [0xf0,0x7c,0xfa,0x92] + +s_or_not1_b64 exec, src_scc, exec +// GFX12: encoding: [0xfd,0x7e,0xfe,0x92] + +s_or_not1_b64 null, 0xaf123456, vcc +// GFX12: encoding: [0xff,0x6a,0xfc,0x92,0x56,0x34,0x12,0xaf] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sop2_alias.s b/llvm/test/MC/AMDGPU/gfx12_asm_sop2_alias.s new file mode 100644 index 000000000000..86c3bdbaf830 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sop2_alias.s @@ -0,0 +1,223 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s + +s_add_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x81] + +s_add_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x80] + +s_add_u64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x80,0xa9] + +s_addc_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x00,0x82] + +s_sub_i32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x81] + +s_sub_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x80] + +s_sub_u64 s[0:1], s[2:3], s[4:5] +// GFX12: encoding: [0x02,0x04,0x00,0xaa] + +s_subb_u32 s0, s1, s2 +// GFX12: encoding: [0x01,0x02,0x80,0x82] + +s_min_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa1] + +s_min_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa1] + +s_min_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa1] + +s_min_f32 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x05,0xa1] + +s_min_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa1] + +s_min_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa1] + +s_min_f32 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x05,0xa1] + +s_min_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa1] + +s_min_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa1] + +s_min_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa1] + +s_min_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa1] + +s_min_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa1] + +s_min_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa1] + +s_min_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa1] + +s_min_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa1,0x56,0x34,0x12,0xaf] + +s_min_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa1,0x73,0x72,0x71,0x3f] + +s_min_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa1] + +s_max_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa1] + +s_max_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa1] + +s_max_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa1] + +s_max_f32 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x85,0xa1] + +s_max_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa1] + +s_max_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa1] + +s_max_f32 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x85,0xa1] + +s_max_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa1] + +s_max_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa1] + +s_max_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa1] + +s_max_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa1] + +s_max_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa1] + +s_max_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa1] + +s_max_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa1] + +s_max_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa1,0x56,0x34,0x12,0xaf] + +s_max_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa1,0x73,0x72,0x71,0x3f] + +s_max_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa1] + +s_max_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa6] + +s_max_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa6] + +s_max_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa6] + +s_max_f16 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x05,0xa6] + +s_max_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa6] + +s_max_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa6] + +s_max_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa6] + +s_max_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa6] + +s_max_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa6] + +s_max_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa6] + +s_max_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa6] + +s_max_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa6] + +s_max_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa6] + +s_max_f16 s5, 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa6,0x0b,0xfe,0x00,0x00] + +s_max_f16 s5, 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa6,0x56,0x34,0x00,0x00] + +s_max_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa6] + +s_min_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa5] + +s_min_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa5] + +s_min_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa5] + +s_min_f16 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x85,0xa5] + +s_min_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa5] + +s_min_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa5] + +s_min_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa5] + +s_min_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa5] + +s_min_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa5] + +s_min_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa5] + +s_min_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa5] + +s_min_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa5] + +s_min_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa5] + +s_min_f16 s5, 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa5,0x0b,0xfe,0x00,0x00] + +s_min_f16 s5, 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa5,0x56,0x34,0x00,0x00] + +s_min_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa5] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx12_asm_sopc.s new file mode 100644 index 000000000000..6887ec318851 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sopc.s @@ -0,0 +1,2161 @@ +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s + +s_cmp_lt_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x41,0xbf] + +s_cmp_lt_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x41,0xbf] + +s_cmp_lt_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x41,0xbf] + +s_cmp_lt_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x41,0xbf] + +s_cmp_lt_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x41,0xbf] + +s_cmp_lt_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x41,0xbf] + +s_cmp_lt_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x41,0xbf] + +s_cmp_lt_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x41,0xbf] + +s_cmp_lt_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x41,0xbf] + +s_cmp_lt_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x41,0xbf] + +s_cmp_lt_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x41,0xbf] + +s_cmp_lt_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x41,0xbf] + +s_cmp_lt_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x41,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_lt_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x41,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_lt_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x41,0xbf] + +s_cmp_eq_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x42,0xbf] + +s_cmp_eq_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x42,0xbf] + +s_cmp_eq_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x42,0xbf] + +s_cmp_eq_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x42,0xbf] + +s_cmp_eq_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x42,0xbf] + +s_cmp_eq_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x42,0xbf] + +s_cmp_eq_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x42,0xbf] + +s_cmp_eq_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x42,0xbf] + +s_cmp_eq_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x42,0xbf] + +s_cmp_eq_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x42,0xbf] + +s_cmp_eq_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x42,0xbf] + +s_cmp_eq_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x42,0xbf] + +s_cmp_eq_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x42,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_eq_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x42,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_eq_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x42,0xbf] + +s_cmp_le_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x43,0xbf] + +s_cmp_le_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x43,0xbf] + +s_cmp_le_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x43,0xbf] + +s_cmp_le_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x43,0xbf] + +s_cmp_le_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x43,0xbf] + +s_cmp_le_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x43,0xbf] + +s_cmp_le_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x43,0xbf] + +s_cmp_le_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x43,0xbf] + +s_cmp_le_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x43,0xbf] + +s_cmp_le_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x43,0xbf] + +s_cmp_le_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x43,0xbf] + +s_cmp_le_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x43,0xbf] + +s_cmp_le_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x43,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_le_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x43,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_le_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x43,0xbf] + +s_cmp_gt_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x44,0xbf] + +s_cmp_gt_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x44,0xbf] + +s_cmp_gt_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x44,0xbf] + +s_cmp_gt_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x44,0xbf] + +s_cmp_gt_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x44,0xbf] + +s_cmp_gt_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x44,0xbf] + +s_cmp_gt_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x44,0xbf] + +s_cmp_gt_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x44,0xbf] + +s_cmp_gt_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x44,0xbf] + +s_cmp_gt_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x44,0xbf] + +s_cmp_gt_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x44,0xbf] + +s_cmp_gt_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x44,0xbf] + +s_cmp_gt_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x44,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_gt_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x44,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_gt_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x44,0xbf] + +s_cmp_lg_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x45,0xbf] + +s_cmp_lg_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x45,0xbf] + +s_cmp_lg_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x45,0xbf] + +s_cmp_lg_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x45,0xbf] + +s_cmp_lg_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x45,0xbf] + +s_cmp_lg_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x45,0xbf] + +s_cmp_lg_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x45,0xbf] + +s_cmp_lg_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x45,0xbf] + +s_cmp_lg_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x45,0xbf] + +s_cmp_lg_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x45,0xbf] + +s_cmp_lg_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x45,0xbf] + +s_cmp_lg_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x45,0xbf] + +s_cmp_lg_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x45,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_lg_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x45,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_lg_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x45,0xbf] + +s_cmp_ge_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x46,0xbf] + +s_cmp_ge_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x46,0xbf] + +s_cmp_ge_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x46,0xbf] + +s_cmp_ge_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x46,0xbf] + +s_cmp_ge_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x46,0xbf] + +s_cmp_ge_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x46,0xbf] + +s_cmp_ge_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x46,0xbf] + +s_cmp_ge_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x46,0xbf] + +s_cmp_ge_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x46,0xbf] + +s_cmp_ge_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x46,0xbf] + +s_cmp_ge_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x46,0xbf] + +s_cmp_ge_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x46,0xbf] + +s_cmp_ge_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x46,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_ge_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x46,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_ge_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x46,0xbf] + +s_cmp_o_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x47,0xbf] + +s_cmp_o_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x47,0xbf] + +s_cmp_o_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x47,0xbf] + +s_cmp_o_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x47,0xbf] + +s_cmp_o_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x47,0xbf] + +s_cmp_o_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x47,0xbf] + +s_cmp_o_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x47,0xbf] + +s_cmp_o_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x47,0xbf] + +s_cmp_o_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x47,0xbf] + +s_cmp_o_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x47,0xbf] + +s_cmp_o_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x47,0xbf] + +s_cmp_o_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x47,0xbf] + +s_cmp_o_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x47,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_o_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x47,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_o_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x47,0xbf] + +s_cmp_u_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x48,0xbf] + +s_cmp_u_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x48,0xbf] + +s_cmp_u_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x48,0xbf] + +s_cmp_u_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x48,0xbf] + +s_cmp_u_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x48,0xbf] + +s_cmp_u_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x48,0xbf] + +s_cmp_u_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x48,0xbf] + +s_cmp_u_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x48,0xbf] + +s_cmp_u_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x48,0xbf] + +s_cmp_u_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x48,0xbf] + +s_cmp_u_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x48,0xbf] + +s_cmp_u_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x48,0xbf] + +s_cmp_u_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x48,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_u_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x48,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_u_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x48,0xbf] + +s_cmp_nge_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x49,0xbf] + +s_cmp_nge_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x49,0xbf] + +s_cmp_nge_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x49,0xbf] + +s_cmp_nge_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x49,0xbf] + +s_cmp_nge_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x49,0xbf] + +s_cmp_nge_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x49,0xbf] + +s_cmp_nge_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x49,0xbf] + +s_cmp_nge_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x49,0xbf] + +s_cmp_nge_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x49,0xbf] + +s_cmp_nge_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x49,0xbf] + +s_cmp_nge_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x49,0xbf] + +s_cmp_nge_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x49,0xbf] + +s_cmp_nge_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x49,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_nge_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x49,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_nge_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x49,0xbf] + +s_cmp_nlg_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x4a,0xbf] + +s_cmp_nlg_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x4a,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_nlg_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x4a,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_nlg_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x4a,0xbf] + +s_cmp_ngt_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x4b,0xbf] + +s_cmp_ngt_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x4b,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_ngt_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x4b,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_ngt_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x4b,0xbf] + +s_cmp_nle_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x4c,0xbf] + +s_cmp_nle_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x4c,0xbf] + +s_cmp_nle_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x4c,0xbf] + +s_cmp_nle_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x4c,0xbf] + +s_cmp_nle_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x4c,0xbf] + +s_cmp_nle_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x4c,0xbf] + +s_cmp_nle_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x4c,0xbf] + +s_cmp_nle_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x4c,0xbf] + +s_cmp_nle_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x4c,0xbf] + +s_cmp_nle_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x4c,0xbf] + +s_cmp_nle_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x4c,0xbf] + +s_cmp_nle_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x4c,0xbf] + +s_cmp_nle_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x4c,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_nle_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x4c,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_nle_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x4c,0xbf] + +s_cmp_neq_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x4d,0xbf] + +s_cmp_neq_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x4d,0xbf] + +s_cmp_neq_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x4d,0xbf] + +s_cmp_neq_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x4d,0xbf] + +s_cmp_neq_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x4d,0xbf] + +s_cmp_neq_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x4d,0xbf] + +s_cmp_neq_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x4d,0xbf] + +s_cmp_neq_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x4d,0xbf] + +s_cmp_neq_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x4d,0xbf] + +s_cmp_neq_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x4d,0xbf] + +s_cmp_neq_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x4d,0xbf] + +s_cmp_neq_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x4d,0xbf] + +s_cmp_neq_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x4d,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_neq_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x4d,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_neq_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x4d,0xbf] + +s_cmp_nlt_f32 s1, s2 +// GFX12: encoding: [0x01,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 s105, s2 +// GFX12: encoding: [0x69,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 s101, s2 +// GFX12: encoding: [0x65,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 0, s2 +// GFX12: encoding: [0x80,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x4e,0xbf] + +s_cmp_nlt_f32 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x4e,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_nlt_f32 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x4e,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_nlt_f32 s1, s105 +// GFX12: encoding: [0x01,0x69,0x4e,0xbf] + +s_cmp_lt_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x51,0xbf] + +s_cmp_lt_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x51,0xbf] + +s_cmp_lt_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x51,0xbf] + +s_cmp_lt_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x51,0xbf] + +s_cmp_lt_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x51,0xbf] + +s_cmp_lt_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x51,0xbf] + +s_cmp_lt_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x51,0xbf] + +s_cmp_lt_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x51,0xbf] + +s_cmp_lt_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x51,0xbf] + +s_cmp_lt_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x51,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_lt_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x51,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_lt_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x51,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_eq_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x52,0xbf] + +s_cmp_eq_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x52,0xbf] + +s_cmp_eq_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x52,0xbf] + +s_cmp_eq_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x52,0xbf] + +s_cmp_eq_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x52,0xbf] + +s_cmp_eq_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x52,0xbf] + +s_cmp_eq_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x52,0xbf] + +s_cmp_eq_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x52,0xbf] + +s_cmp_eq_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x52,0xbf] + +s_cmp_eq_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x52,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_eq_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x52,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_eq_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x52,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_le_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x53,0xbf] + +s_cmp_le_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x53,0xbf] + +s_cmp_le_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x53,0xbf] + +s_cmp_le_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x53,0xbf] + +s_cmp_le_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x53,0xbf] + +s_cmp_le_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x53,0xbf] + +s_cmp_le_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x53,0xbf] + +s_cmp_le_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x53,0xbf] + +s_cmp_le_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x53,0xbf] + +s_cmp_le_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x53,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_le_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x53,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_le_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x53,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_gt_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x54,0xbf] + +s_cmp_gt_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x54,0xbf] + +s_cmp_gt_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x54,0xbf] + +s_cmp_gt_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x54,0xbf] + +s_cmp_gt_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x54,0xbf] + +s_cmp_gt_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x54,0xbf] + +s_cmp_gt_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x54,0xbf] + +s_cmp_gt_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x54,0xbf] + +s_cmp_gt_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x54,0xbf] + +s_cmp_gt_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x54,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_gt_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x54,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_gt_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x54,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_lg_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x55,0xbf] + +s_cmp_lg_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x55,0xbf] + +s_cmp_lg_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x55,0xbf] + +s_cmp_lg_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x55,0xbf] + +s_cmp_lg_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x55,0xbf] + +s_cmp_lg_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x55,0xbf] + +s_cmp_lg_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x55,0xbf] + +s_cmp_lg_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x55,0xbf] + +s_cmp_lg_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x55,0xbf] + +s_cmp_lg_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x55,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_lg_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x55,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_lg_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x55,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_ge_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x56,0xbf] + +s_cmp_ge_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x56,0xbf] + +s_cmp_ge_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x56,0xbf] + +s_cmp_ge_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x56,0xbf] + +s_cmp_ge_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x56,0xbf] + +s_cmp_ge_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x56,0xbf] + +s_cmp_ge_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x56,0xbf] + +s_cmp_ge_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x56,0xbf] + +s_cmp_ge_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x56,0xbf] + +s_cmp_ge_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x56,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_ge_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x56,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_ge_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x56,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_o_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x57,0xbf] + +s_cmp_o_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x57,0xbf] + +s_cmp_o_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x57,0xbf] + +s_cmp_o_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x57,0xbf] + +s_cmp_o_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x57,0xbf] + +s_cmp_o_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x57,0xbf] + +s_cmp_o_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x57,0xbf] + +s_cmp_o_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x57,0xbf] + +s_cmp_o_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x57,0xbf] + +s_cmp_o_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x57,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_o_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x57,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_o_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x57,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_u_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x58,0xbf] + +s_cmp_u_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x58,0xbf] + +s_cmp_u_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x58,0xbf] + +s_cmp_u_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x58,0xbf] + +s_cmp_u_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x58,0xbf] + +s_cmp_u_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x58,0xbf] + +s_cmp_u_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x58,0xbf] + +s_cmp_u_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x58,0xbf] + +s_cmp_u_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x58,0xbf] + +s_cmp_u_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x58,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_u_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x58,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_u_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x58,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_nge_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x59,0xbf] + +s_cmp_nge_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x59,0xbf] + +s_cmp_nge_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x59,0xbf] + +s_cmp_nge_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x59,0xbf] + +s_cmp_nge_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x59,0xbf] + +s_cmp_nge_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x59,0xbf] + +s_cmp_nge_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x59,0xbf] + +s_cmp_nge_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x59,0xbf] + +s_cmp_nge_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x59,0xbf] + +s_cmp_nge_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x59,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nge_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x59,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_nge_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x59,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_nlg_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x5a,0xbf] + +s_cmp_nlg_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x5a,0xbf] + +s_cmp_nlg_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x5a,0xbf] + +s_cmp_nlg_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x5a,0xbf] + +s_cmp_nlg_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x5a,0xbf] + +s_cmp_nlg_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x5a,0xbf] + +s_cmp_nlg_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x5a,0xbf] + +s_cmp_nlg_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x5a,0xbf] + +s_cmp_nlg_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x5a,0xbf] + +s_cmp_nlg_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x5a,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nlg_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x5a,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_nlg_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x5a,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_ngt_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x5b,0xbf] + +s_cmp_ngt_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x5b,0xbf] + +s_cmp_ngt_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x5b,0xbf] + +s_cmp_ngt_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x5b,0xbf] + +s_cmp_ngt_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x5b,0xbf] + +s_cmp_ngt_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x5b,0xbf] + +s_cmp_ngt_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x5b,0xbf] + +s_cmp_ngt_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x5b,0xbf] + +s_cmp_ngt_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x5b,0xbf] + +s_cmp_ngt_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x5b,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_ngt_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x5b,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_ngt_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x5b,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_nle_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x5c,0xbf] + +s_cmp_nle_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x5c,0xbf] + +s_cmp_nle_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x5c,0xbf] + +s_cmp_nle_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x5c,0xbf] + +s_cmp_nle_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x5c,0xbf] + +s_cmp_nle_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x5c,0xbf] + +s_cmp_nle_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x5c,0xbf] + +s_cmp_nle_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x5c,0xbf] + +s_cmp_nle_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x5c,0xbf] + +s_cmp_nle_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x5c,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nle_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x5c,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_nle_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x5c,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_neq_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x5d,0xbf] + +s_cmp_neq_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x5d,0xbf] + +s_cmp_neq_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x5d,0xbf] + +s_cmp_neq_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x5d,0xbf] + +s_cmp_neq_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x5d,0xbf] + +s_cmp_neq_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x5d,0xbf] + +s_cmp_neq_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x5d,0xbf] + +s_cmp_neq_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x5d,0xbf] + +s_cmp_neq_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x5d,0xbf] + +s_cmp_neq_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x5d,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_neq_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x5d,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_neq_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x5d,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_nlt_f16 s1, s2 +// GFX12: encoding: [0x01,0x02,0x5e,0xbf] + +s_cmp_nlt_f16 s101, s2 +// GFX12: encoding: [0x65,0x02,0x5e,0xbf] + +s_cmp_nlt_f16 vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x5e,0xbf] + +s_cmp_nlt_f16 vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x5e,0xbf] + +s_cmp_nlt_f16 m0, s2 +// GFX12: encoding: [0x7d,0x02,0x5e,0xbf] + +s_cmp_nlt_f16 exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x5e,0xbf] + +s_cmp_nlt_f16 exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x5e,0xbf] + +s_cmp_nlt_f16 0, s2 +// GFX12: encoding: [0x80,0x02,0x5e,0xbf] + +s_cmp_nlt_f16 -1, s2 +// GFX12: encoding: [0xc1,0x02,0x5e,0xbf] + +s_cmp_nlt_f16 0x3800, s2 +// GFX12: encoding: [0xff,0x02,0x5e,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nlt_f16 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x5e,0xbf,0x0b,0xfe,0x00,0x00] + +s_cmp_nlt_f16 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x5e,0xbf,0x56,0x34,0x00,0x00] + +s_cmp_eq_i32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x00,0xbf] + +s_cmp_eq_i32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x00,0xbf] + +s_cmp_eq_i32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x00,0xbf] + +s_cmp_eq_i32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x00,0xbf] + +s_cmp_eq_i32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x00,0xbf] + +s_cmp_eq_i32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x00,0xbf] + +s_cmp_eq_i32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x00,0xbf] + +s_cmp_eq_i32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x00,0xbf] + +s_cmp_eq_i32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x00,0xbf] + +s_cmp_eq_i32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x00,0xbf] + +s_cmp_eq_i32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x00,0xbf] + +s_cmp_eq_i32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x00,0xbf] + +s_cmp_eq_i32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x00,0xbf] + +s_cmp_eq_i32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x00,0xbf] + +s_cmp_eq_i32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x00,0xbf] + +s_cmp_eq_i32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x00,0xbf] + +s_cmp_eq_i32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x00,0xbf] + +s_cmp_eq_i32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x00,0xbf] + +s_cmp_eq_i32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_eq_i32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_lg_i32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x01,0xbf] + +s_cmp_lg_i32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x01,0xbf] + +s_cmp_lg_i32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x01,0xbf] + +s_cmp_lg_i32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x01,0xbf] + +s_cmp_lg_i32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x01,0xbf] + +s_cmp_lg_i32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x01,0xbf] + +s_cmp_lg_i32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x01,0xbf] + +s_cmp_lg_i32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x01,0xbf] + +s_cmp_lg_i32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x01,0xbf] + +s_cmp_lg_i32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x01,0xbf] + +s_cmp_lg_i32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x01,0xbf] + +s_cmp_lg_i32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x01,0xbf] + +s_cmp_lg_i32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x01,0xbf] + +s_cmp_lg_i32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x01,0xbf] + +s_cmp_lg_i32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x01,0xbf] + +s_cmp_lg_i32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x01,0xbf] + +s_cmp_lg_i32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x01,0xbf] + +s_cmp_lg_i32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x01,0xbf] + +s_cmp_lg_i32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_lg_i32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_gt_i32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x02,0xbf] + +s_cmp_gt_i32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x02,0xbf] + +s_cmp_gt_i32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x02,0xbf] + +s_cmp_gt_i32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x02,0xbf] + +s_cmp_gt_i32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x02,0xbf] + +s_cmp_gt_i32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x02,0xbf] + +s_cmp_gt_i32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x02,0xbf] + +s_cmp_gt_i32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x02,0xbf] + +s_cmp_gt_i32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x02,0xbf] + +s_cmp_gt_i32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x02,0xbf] + +s_cmp_gt_i32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x02,0xbf] + +s_cmp_gt_i32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x02,0xbf] + +s_cmp_gt_i32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x02,0xbf] + +s_cmp_gt_i32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x02,0xbf] + +s_cmp_gt_i32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x02,0xbf] + +s_cmp_gt_i32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x02,0xbf] + +s_cmp_gt_i32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x02,0xbf] + +s_cmp_gt_i32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x02,0xbf] + +s_cmp_gt_i32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_gt_i32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_ge_i32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x03,0xbf] + +s_cmp_ge_i32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x03,0xbf] + +s_cmp_ge_i32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x03,0xbf] + +s_cmp_ge_i32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x03,0xbf] + +s_cmp_ge_i32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x03,0xbf] + +s_cmp_ge_i32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x03,0xbf] + +s_cmp_ge_i32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x03,0xbf] + +s_cmp_ge_i32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x03,0xbf] + +s_cmp_ge_i32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x03,0xbf] + +s_cmp_ge_i32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x03,0xbf] + +s_cmp_ge_i32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x03,0xbf] + +s_cmp_ge_i32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x03,0xbf] + +s_cmp_ge_i32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x03,0xbf] + +s_cmp_ge_i32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x03,0xbf] + +s_cmp_ge_i32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x03,0xbf] + +s_cmp_ge_i32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x03,0xbf] + +s_cmp_ge_i32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x03,0xbf] + +s_cmp_ge_i32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x03,0xbf] + +s_cmp_ge_i32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_ge_i32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_lt_i32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x04,0xbf] + +s_cmp_lt_i32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x04,0xbf] + +s_cmp_lt_i32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x04,0xbf] + +s_cmp_lt_i32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x04,0xbf] + +s_cmp_lt_i32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x04,0xbf] + +s_cmp_lt_i32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x04,0xbf] + +s_cmp_lt_i32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x04,0xbf] + +s_cmp_lt_i32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x04,0xbf] + +s_cmp_lt_i32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x04,0xbf] + +s_cmp_lt_i32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x04,0xbf] + +s_cmp_lt_i32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x04,0xbf] + +s_cmp_lt_i32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x04,0xbf] + +s_cmp_lt_i32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x04,0xbf] + +s_cmp_lt_i32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x04,0xbf] + +s_cmp_lt_i32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x04,0xbf] + +s_cmp_lt_i32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x04,0xbf] + +s_cmp_lt_i32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x04,0xbf] + +s_cmp_lt_i32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x04,0xbf] + +s_cmp_lt_i32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_lt_i32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_le_i32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x05,0xbf] + +s_cmp_le_i32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x05,0xbf] + +s_cmp_le_i32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x05,0xbf] + +s_cmp_le_i32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x05,0xbf] + +s_cmp_le_i32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x05,0xbf] + +s_cmp_le_i32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x05,0xbf] + +s_cmp_le_i32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x05,0xbf] + +s_cmp_le_i32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x05,0xbf] + +s_cmp_le_i32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x05,0xbf] + +s_cmp_le_i32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x05,0xbf] + +s_cmp_le_i32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x05,0xbf] + +s_cmp_le_i32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x05,0xbf] + +s_cmp_le_i32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x05,0xbf] + +s_cmp_le_i32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x05,0xbf] + +s_cmp_le_i32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x05,0xbf] + +s_cmp_le_i32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x05,0xbf] + +s_cmp_le_i32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x05,0xbf] + +s_cmp_le_i32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x05,0xbf] + +s_cmp_le_i32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_le_i32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_eq_u32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x06,0xbf] + +s_cmp_eq_u32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x06,0xbf] + +s_cmp_eq_u32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x06,0xbf] + +s_cmp_eq_u32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x06,0xbf] + +s_cmp_eq_u32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x06,0xbf] + +s_cmp_eq_u32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x06,0xbf] + +s_cmp_eq_u32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x06,0xbf] + +s_cmp_eq_u32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x06,0xbf] + +s_cmp_eq_u32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x06,0xbf] + +s_cmp_eq_u32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x06,0xbf] + +s_cmp_eq_u32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x06,0xbf] + +s_cmp_eq_u32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x06,0xbf] + +s_cmp_eq_u32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x06,0xbf] + +s_cmp_eq_u32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x06,0xbf] + +s_cmp_eq_u32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x06,0xbf] + +s_cmp_eq_u32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x06,0xbf] + +s_cmp_eq_u32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x06,0xbf] + +s_cmp_eq_u32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x06,0xbf] + +s_cmp_eq_u32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_eq_u32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_lg_u32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x07,0xbf] + +s_cmp_lg_u32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x07,0xbf] + +s_cmp_lg_u32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x07,0xbf] + +s_cmp_lg_u32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x07,0xbf] + +s_cmp_lg_u32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x07,0xbf] + +s_cmp_lg_u32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x07,0xbf] + +s_cmp_lg_u32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x07,0xbf] + +s_cmp_lg_u32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x07,0xbf] + +s_cmp_lg_u32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x07,0xbf] + +s_cmp_lg_u32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x07,0xbf] + +s_cmp_lg_u32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x07,0xbf] + +s_cmp_lg_u32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x07,0xbf] + +s_cmp_lg_u32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x07,0xbf] + +s_cmp_lg_u32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x07,0xbf] + +s_cmp_lg_u32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x07,0xbf] + +s_cmp_lg_u32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x07,0xbf] + +s_cmp_lg_u32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x07,0xbf] + +s_cmp_lg_u32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x07,0xbf] + +s_cmp_lg_u32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_lg_u32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_gt_u32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x08,0xbf] + +s_cmp_gt_u32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x08,0xbf] + +s_cmp_gt_u32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x08,0xbf] + +s_cmp_gt_u32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x08,0xbf] + +s_cmp_gt_u32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x08,0xbf] + +s_cmp_gt_u32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x08,0xbf] + +s_cmp_gt_u32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x08,0xbf] + +s_cmp_gt_u32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x08,0xbf] + +s_cmp_gt_u32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x08,0xbf] + +s_cmp_gt_u32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x08,0xbf] + +s_cmp_gt_u32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x08,0xbf] + +s_cmp_gt_u32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x08,0xbf] + +s_cmp_gt_u32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x08,0xbf] + +s_cmp_gt_u32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x08,0xbf] + +s_cmp_gt_u32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x08,0xbf] + +s_cmp_gt_u32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x08,0xbf] + +s_cmp_gt_u32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x08,0xbf] + +s_cmp_gt_u32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x08,0xbf] + +s_cmp_gt_u32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_gt_u32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_ge_u32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x09,0xbf] + +s_cmp_ge_u32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x09,0xbf] + +s_cmp_ge_u32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x09,0xbf] + +s_cmp_ge_u32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x09,0xbf] + +s_cmp_ge_u32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x09,0xbf] + +s_cmp_ge_u32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x09,0xbf] + +s_cmp_ge_u32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x09,0xbf] + +s_cmp_ge_u32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x09,0xbf] + +s_cmp_ge_u32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x09,0xbf] + +s_cmp_ge_u32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x09,0xbf] + +s_cmp_ge_u32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x09,0xbf] + +s_cmp_ge_u32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x09,0xbf] + +s_cmp_ge_u32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x09,0xbf] + +s_cmp_ge_u32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x09,0xbf] + +s_cmp_ge_u32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x09,0xbf] + +s_cmp_ge_u32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x09,0xbf] + +s_cmp_ge_u32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x09,0xbf] + +s_cmp_ge_u32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x09,0xbf] + +s_cmp_ge_u32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_ge_u32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_lt_u32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x0a,0xbf] + +s_cmp_lt_u32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x0a,0xbf] + +s_cmp_lt_u32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x0a,0xbf] + +s_cmp_lt_u32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x0a,0xbf] + +s_cmp_lt_u32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x0a,0xbf] + +s_cmp_lt_u32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x0a,0xbf] + +s_cmp_lt_u32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x0a,0xbf] + +s_cmp_lt_u32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x0a,0xbf] + +s_cmp_lt_u32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x0a,0xbf] + +s_cmp_lt_u32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x0a,0xbf] + +s_cmp_lt_u32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x0a,0xbf] + +s_cmp_lt_u32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x0a,0xbf] + +s_cmp_lt_u32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x0a,0xbf] + +s_cmp_lt_u32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x0a,0xbf] + +s_cmp_lt_u32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x0a,0xbf] + +s_cmp_lt_u32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x0a,0xbf] + +s_cmp_lt_u32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x0a,0xbf] + +s_cmp_lt_u32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x0a,0xbf] + +s_cmp_lt_u32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_lt_u32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_le_u32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x0b,0xbf] + +s_cmp_le_u32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x0b,0xbf] + +s_cmp_le_u32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x0b,0xbf] + +s_cmp_le_u32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x0b,0xbf] + +s_cmp_le_u32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x0b,0xbf] + +s_cmp_le_u32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x0b,0xbf] + +s_cmp_le_u32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x0b,0xbf] + +s_cmp_le_u32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x0b,0xbf] + +s_cmp_le_u32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x0b,0xbf] + +s_cmp_le_u32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x0b,0xbf] + +s_cmp_le_u32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x0b,0xbf] + +s_cmp_le_u32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x0b,0xbf] + +s_cmp_le_u32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x0b,0xbf] + +s_cmp_le_u32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x0b,0xbf] + +s_cmp_le_u32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x0b,0xbf] + +s_cmp_le_u32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x0b,0xbf] + +s_cmp_le_u32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x0b,0xbf] + +s_cmp_le_u32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x0b,0xbf] + +s_cmp_le_u32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_le_u32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf] + +s_bitcmp0_b32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x0c,0xbf] + +s_bitcmp0_b32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x0c,0xbf] + +s_bitcmp0_b32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x0c,0xbf] + +s_bitcmp0_b32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x0c,0xbf] + +s_bitcmp0_b32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x0c,0xbf] + +s_bitcmp0_b32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x0c,0xbf] + +s_bitcmp0_b32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x0c,0xbf] + +s_bitcmp0_b32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x0c,0xbf] + +s_bitcmp0_b32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x0c,0xbf] + +s_bitcmp0_b32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x0c,0xbf] + +s_bitcmp0_b32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x0c,0xbf] + +s_bitcmp0_b32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x0c,0xbf] + +s_bitcmp0_b32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x0c,0xbf] + +s_bitcmp0_b32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x0c,0xbf] + +s_bitcmp0_b32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x0c,0xbf] + +s_bitcmp0_b32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x0c,0xbf] + +s_bitcmp0_b32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x0c,0xbf] + +s_bitcmp0_b32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x0c,0xbf] + +s_bitcmp0_b32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f] + +s_bitcmp0_b32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf] + +s_bitcmp1_b32 s0, s1 +// GFX12: encoding: [0x00,0x01,0x0d,0xbf] + +s_bitcmp1_b32 s105, s104 +// GFX12: encoding: [0x69,0x68,0x0d,0xbf] + +s_bitcmp1_b32 s0, s104 +// GFX12: encoding: [0x00,0x68,0x0d,0xbf] + +s_bitcmp1_b32 s105, s1 +// GFX12: encoding: [0x69,0x01,0x0d,0xbf] + +s_bitcmp1_b32 exec_lo, s1 +// GFX12: encoding: [0x7e,0x01,0x0d,0xbf] + +s_bitcmp1_b32 exec_hi, s1 +// GFX12: encoding: [0x7f,0x01,0x0d,0xbf] + +s_bitcmp1_b32 vcc_lo, s1 +// GFX12: encoding: [0x6a,0x01,0x0d,0xbf] + +s_bitcmp1_b32 vcc_hi, s1 +// GFX12: encoding: [0x6b,0x01,0x0d,0xbf] + +s_bitcmp1_b32 m0, s1 +// GFX12: encoding: [0x7d,0x01,0x0d,0xbf] + +s_bitcmp1_b32 s0, exec_lo +// GFX12: encoding: [0x00,0x7e,0x0d,0xbf] + +s_bitcmp1_b32 s0, exec_hi +// GFX12: encoding: [0x00,0x7f,0x0d,0xbf] + +s_bitcmp1_b32 s0, vcc_lo +// GFX12: encoding: [0x00,0x6a,0x0d,0xbf] + +s_bitcmp1_b32 s0, vcc_hi +// GFX12: encoding: [0x00,0x6b,0x0d,0xbf] + +s_bitcmp1_b32 s0, m0 +// GFX12: encoding: [0x00,0x7d,0x0d,0xbf] + +s_bitcmp1_b32 s0, 0 +// GFX12: encoding: [0x00,0x80,0x0d,0xbf] + +s_bitcmp1_b32 s0, -1 +// GFX12: encoding: [0x00,0xc1,0x0d,0xbf] + +s_bitcmp1_b32 s0, 0.5 +// GFX12: encoding: [0x00,0xf0,0x0d,0xbf] + +s_bitcmp1_b32 s0, -4.0 +// GFX12: encoding: [0x00,0xf7,0x0d,0xbf] + +s_bitcmp1_b32 s0, 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f] + +s_bitcmp1_b32 s0, 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf] + +s_bitcmp0_b64 s[0:1], s2 +// GFX12: encoding: [0x00,0x02,0x0e,0xbf] + +s_bitcmp0_b64 s[104:105], s102 +// GFX12: encoding: [0x68,0x66,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], s102 +// GFX12: encoding: [0x00,0x66,0x0e,0xbf] + +s_bitcmp0_b64 s[104:105], s2 +// GFX12: encoding: [0x68,0x02,0x0e,0xbf] + +s_bitcmp0_b64 exec, s2 +// GFX12: encoding: [0x7e,0x02,0x0e,0xbf] + +s_bitcmp0_b64 vcc, s2 +// GFX12: encoding: [0x6a,0x02,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], exec_lo +// GFX12: encoding: [0x00,0x7e,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], exec_hi +// GFX12: encoding: [0x00,0x7f,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], vcc_lo +// GFX12: encoding: [0x00,0x6a,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], vcc_hi +// GFX12: encoding: [0x00,0x6b,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], m0 +// GFX12: encoding: [0x00,0x7d,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], 0 +// GFX12: encoding: [0x00,0x80,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], -1 +// GFX12: encoding: [0x00,0xc1,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], 0.5 +// GFX12: encoding: [0x00,0xf0,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], -4.0 +// GFX12: encoding: [0x00,0xf7,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f] + +s_bitcmp0_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf] + +s_bitcmp1_b64 s[0:1], s2 +// GFX12: encoding: [0x00,0x02,0x0f,0xbf] + +s_bitcmp1_b64 s[104:105], s102 +// GFX12: encoding: [0x68,0x66,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], s102 +// GFX12: encoding: [0x00,0x66,0x0f,0xbf] + +s_bitcmp1_b64 s[104:105], s2 +// GFX12: encoding: [0x68,0x02,0x0f,0xbf] + +s_bitcmp1_b64 exec, s2 +// GFX12: encoding: [0x7e,0x02,0x0f,0xbf] + +s_bitcmp1_b64 vcc, s2 +// GFX12: encoding: [0x6a,0x02,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], exec_lo +// GFX12: encoding: [0x00,0x7e,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], exec_hi +// GFX12: encoding: [0x00,0x7f,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], vcc_lo +// GFX12: encoding: [0x00,0x6a,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], vcc_hi +// GFX12: encoding: [0x00,0x6b,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], m0 +// GFX12: encoding: [0x00,0x7d,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], 0 +// GFX12: encoding: [0x00,0x80,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], -1 +// GFX12: encoding: [0x00,0xc1,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], 0.5 +// GFX12: encoding: [0x00,0xf0,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], -4.0 +// GFX12: encoding: [0x00,0xf7,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f] + +s_bitcmp1_b64 s[0:1], 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_eq_u64 s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0x10,0xbf] + +s_cmp_eq_u64 s[104:105], s[102:103] +// GFX12: encoding: [0x68,0x66,0x10,0xbf] + +s_cmp_eq_u64 s[0:1], s[102:103] +// GFX12: encoding: [0x00,0x66,0x10,0xbf] + +s_cmp_eq_u64 s[104:105], s[2:3] +// GFX12: encoding: [0x68,0x02,0x10,0xbf] + +s_cmp_eq_u64 exec, s[2:3] +// GFX12: encoding: [0x7e,0x02,0x10,0xbf] + +s_cmp_eq_u64 vcc, s[2:3] +// GFX12: encoding: [0x6a,0x02,0x10,0xbf] + +s_cmp_eq_u64 s[0:1], exec +// GFX12: encoding: [0x00,0x7e,0x10,0xbf] + +s_cmp_eq_u64 s[0:1], vcc +// GFX12: encoding: [0x00,0x6a,0x10,0xbf] + +s_cmp_eq_u64 s[0:1], 0 +// GFX12: encoding: [0x00,0x80,0x10,0xbf] + +s_cmp_eq_u64 s[0:1], -1 +// GFX12: encoding: [0x00,0xc1,0x10,0xbf] + +s_cmp_eq_u64 s[0:1], 0.5 +// GFX12: encoding: [0x00,0xf0,0x10,0xbf] + +s_cmp_eq_u64 s[0:1], -4.0 +// GFX12: encoding: [0x00,0xf7,0x10,0xbf] + +s_cmp_eq_u64 s[0:1], 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x10,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_eq_u64 s[0:1], 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf] + +s_cmp_lg_u64 s[0:1], s[2:3] +// GFX12: encoding: [0x00,0x02,0x11,0xbf] + +s_cmp_lg_u64 s[104:105], s[102:103] +// GFX12: encoding: [0x68,0x66,0x11,0xbf] + +s_cmp_lg_u64 s[0:1], s[102:103] +// GFX12: encoding: [0x00,0x66,0x11,0xbf] + +s_cmp_lg_u64 s[104:105], s[2:3] +// GFX12: encoding: [0x68,0x02,0x11,0xbf] + +s_cmp_lg_u64 exec, s[2:3] +// GFX12: encoding: [0x7e,0x02,0x11,0xbf] + +s_cmp_lg_u64 vcc, s[2:3] +// GFX12: encoding: [0x6a,0x02,0x11,0xbf] + +s_cmp_lg_u64 s[0:1], exec +// GFX12: encoding: [0x00,0x7e,0x11,0xbf] + +s_cmp_lg_u64 s[0:1], vcc +// GFX12: encoding: [0x00,0x6a,0x11,0xbf] + +s_cmp_lg_u64 s[0:1], 0 +// GFX12: encoding: [0x00,0x80,0x11,0xbf] + +s_cmp_lg_u64 s[0:1], -1 +// GFX12: encoding: [0x00,0xc1,0x11,0xbf] + +s_cmp_lg_u64 s[0:1], 0.5 +// GFX12: encoding: [0x00,0xf0,0x11,0xbf] + +s_cmp_lg_u64 s[0:1], -4.0 +// GFX12: encoding: [0x00,0xf7,0x11,0xbf] + +s_cmp_lg_u64 s[0:1], 0x3f717273 +// GFX12: encoding: [0x00,0xff,0x11,0xbf,0x73,0x72,0x71,0x3f] + +s_cmp_lg_u64 s[0:1], 0xaf123456 +// GFX12: encoding: [0x00,0xff,0x11,0xbf,0x56,0x34,0x12,0xaf] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx12_asm_sopk.s new file mode 100644 index 000000000000..3d8d59cfada3 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sopk.s @@ -0,0 +1,244 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s + +s_movk_i32 s0, 0x1234 +// GFX12: encoding: [0x34,0x12,0x00,0xb0] + +s_movk_i32 s0, 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0x00,0xb0] + +s_movk_i32 s105, 0x1234 +// GFX12: encoding: [0x34,0x12,0x69,0xb0] + +s_movk_i32 exec_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7e,0xb0] + +s_movk_i32 exec_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7f,0xb0] + +s_movk_i32 vcc_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0x6a,0xb0] + +s_movk_i32 vcc_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0x6b,0xb0] + +s_movk_i32 m0, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7d,0xb0] + +s_version 0x1234 +// GFX12: encoding: [0x34,0x12,0x80,0xb0] + +s_version 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0x80,0xb0] + +s_cmovk_i32 s0, 0x1234 +// GFX12: encoding: [0x34,0x12,0x00,0xb1] + +s_cmovk_i32 s0, 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0x00,0xb1] + +s_cmovk_i32 s105, 0x1234 +// GFX12: encoding: [0x34,0x12,0x69,0xb1] + +s_cmovk_i32 exec_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7e,0xb1] + +s_cmovk_i32 exec_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7f,0xb1] + +s_cmovk_i32 vcc_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0x6a,0xb1] + +s_cmovk_i32 vcc_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0x6b,0xb1] + +s_cmovk_i32 m0, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7d,0xb1] + +s_addk_co_i32 s0, 0x1234 +// GFX12: encoding: [0x34,0x12,0x80,0xb7] + +s_addk_co_i32 s0, 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0x80,0xb7] + +s_addk_co_i32 s105, 0x1234 +// GFX12: encoding: [0x34,0x12,0xe9,0xb7] + +s_addk_co_i32 exec_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0xfe,0xb7] + +s_addk_co_i32 exec_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0xff,0xb7] + +s_addk_co_i32 vcc_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0xea,0xb7] + +s_addk_co_i32 vcc_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0xeb,0xb7] + +s_addk_co_i32 m0, 0x1234 +// GFX12: encoding: [0x34,0x12,0xfd,0xb7] + +s_mulk_i32 s0, 0x1234 +// GFX12: encoding: [0x34,0x12,0x00,0xb8] + +s_mulk_i32 s0, 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0x00,0xb8] + +s_mulk_i32 s105, 0x1234 +// GFX12: encoding: [0x34,0x12,0x69,0xb8] + +s_mulk_i32 exec_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7e,0xb8] + +s_mulk_i32 exec_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7f,0xb8] + +s_mulk_i32 vcc_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0x6a,0xb8] + +s_mulk_i32 vcc_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0x6b,0xb8] + +s_mulk_i32 m0, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7d,0xb8] + +s_getreg_b32 s0, 0x1234 +// GFX12: encoding: [0x34,0x12,0x80,0xb8] + +s_getreg_b32 s0, 0xc1d1 +// GFX12: encoding: [0xd1,0xc1,0x80,0xb8] + +s_getreg_b32 s105, 0x1234 +// GFX12: encoding: [0x34,0x12,0xe9,0xb8] + +s_getreg_b32 exec_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0xfe,0xb8] + +s_getreg_b32 exec_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0xff,0xb8] + +s_getreg_b32 vcc_lo, 0x1234 +// GFX12: encoding: [0x34,0x12,0xea,0xb8] + +s_getreg_b32 vcc_hi, 0x1234 +// GFX12: encoding: [0x34,0x12,0xeb,0xb8] + +s_getreg_b32 m0, 0x1234 +// GFX12: encoding: [0x34,0x12,0xfd,0xb8] + +s_setreg_b32 0x1234, s0 +// GFX12: encoding: [0x34,0x12,0x00,0xb9] + +s_setreg_b32 0xc1d1, s0 +// GFX12: encoding: [0xd1,0xc1,0x00,0xb9] + +s_setreg_b32 0x1234, s105 +// GFX12: encoding: [0x34,0x12,0x69,0xb9] + +s_setreg_b32 0x1234, exec_lo +// GFX12: encoding: [0x34,0x12,0x7e,0xb9] + +s_setreg_b32 0x1234, exec_hi +// GFX12: encoding: [0x34,0x12,0x7f,0xb9] + +s_setreg_b32 0x1234, vcc_lo +// GFX12: encoding: [0x34,0x12,0x6a,0xb9] + +s_setreg_b32 0x1234, vcc_hi +// GFX12: encoding: [0x34,0x12,0x6b,0xb9] + +s_setreg_b32 0x1234, m0 +// GFX12: encoding: [0x34,0x12,0x7d,0xb9] + +s_setreg_imm32_b32 0x1234, 0x11213141 +// GFX12: encoding: [0x34,0x12,0x80,0xb9,0x41,0x31,0x21,0x11] + +s_setreg_imm32_b32 0xc1d1, 0x11213141 +// GFX12: encoding: [0xd1,0xc1,0x80,0xb9,0x41,0x31,0x21,0x11] + +s_setreg_imm32_b32 0x1234, 0xa1b1c1d1 +// GFX12: encoding: [0x34,0x12,0x80,0xb9,0xd1,0xc1,0xb1,0xa1] + +s_setreg_imm32_b32 0xc1d1, 0xa1b1c1d1 +// GFX12: encoding: [0xd1,0xc1,0x80,0xb9,0xd1,0xc1,0xb1,0xa1] + +s_call_b64 s[0:1], 0x1234 +// GFX12: encoding: [0x34,0x12,0x00,0xba] + +s_call_b64 s[104:105], 0x1234 +// GFX12: encoding: [0x34,0x12,0x68,0xba] + +s_call_b64 exec, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7e,0xba] + +s_call_b64 vcc, 0x1234 +// GFX12: encoding: [0x34,0x12,0x6a,0xba] + +s_call_b64 null, 0x1234 +// GFX12: encoding: [0x34,0x12,0x7c,0xba] + +s_getreg_b32 s0, hwreg(HW_REG_MODE) +// GFX12: encoding: [0x01,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_STATUS) +// GFX12: encoding: [0x02,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_STATE_PRIV) +// GFX12: encoding: [0x04,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_GPR_ALLOC) +// GFX12: encoding: [0x05,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_LDS_ALLOC) +// GFX12: encoding: [0x06,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_IB_STS) +// GFX12: encoding: [0x07,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA) +// GFX12: encoding: [0x0a,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_LO) +// GFX12: encoding: [0x0b,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_HI) +// GFX12: encoding: [0x0c,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA1) +// GFX12: encoding: [0x0f,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA2) +// GFX12: encoding: [0x10,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_PRIV) +// GFX12: encoding: [0x11,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_USER) +// GFX12: encoding: [0x12,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_TRAP_CTRL) +// GFX12: encoding: [0x13,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_LO) +// GFX12: encoding: [0x14,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_HI) +// GFX12: encoding: [0x15,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_HW_ID1) +// GFX12: encoding: [0x17,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_HW_ID2) +// GFX12: encoding: [0x18,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_LO) +// GFX12: encoding: [0x1f,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_HI) +// GFX12: encoding: [0x20,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_LO) +// GFX12: encoding: [0x1d,0xf8,0x80,0xb8] + +s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_HI) +// GFX12: encoding: [0x1e,0xf8,0x80,0xb8] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sopk_alias.s b/llvm/test/MC/AMDGPU/gfx12_asm_sopk_alias.s new file mode 100644 index 000000000000..283890be82ac --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sopk_alias.s @@ -0,0 +1,4 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s + +s_addk_i32 s0, 0x1234 +// GFX12: encoding: [0x34,0x12,0x80,0xb7] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s new file mode 100644 index 000000000000..2e9df11d6f5a --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s @@ -0,0 +1,346 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s + +s_wait_alu 0xfffe +// GFX12: encoding: [0xfe,0xff,0x88,0xbf] + +s_wait_alu 0 +// GFX12: encoding: [0x00,0x00,0x88,0xbf] + +s_wait_alu depctr_va_sdst(0) +// GFX12: encoding: [0x9f,0xf1,0x88,0xbf] + +s_wait_alu depctr_va_sdst(3) +// GFX12: encoding: [0x9f,0xf7,0x88,0xbf] + +s_wait_alu depctr_va_vdst(14) depctr_va_sdst(6) depctr_vm_vsrc(6) +// GFX12: encoding: [0x9b,0xed,0x88,0xbf] + +s_inst_prefetch 0x1234 +// GFX12: s_set_inst_prefetch_distance 0x1234 ; encoding: [0x34,0x12,0x84,0xbf] + +s_set_inst_prefetch_distance 0x1234 +// GFX12: s_set_inst_prefetch_distance 0x1234 ; encoding: [0x34,0x12,0x84,0xbf] + +s_set_inst_prefetch_distance 0xc1d1 +// GFX12: s_set_inst_prefetch_distance 0xc1d1 ; encoding: [0xd1,0xc1,0x84,0xbf] + +s_singleuse_vdst 0x0000 +// GFX12: encoding: [0x00,0x00,0x93,0xbf] + +s_singleuse_vdst 0xffff +// GFX12: encoding: [0xff,0xff,0x93,0xbf] + +s_singleuse_vdst 0x1234 +// GFX12: encoding: [0x34,0x12,0x93,0xbf] + +//===----------------------------------------------------------------------===// +// s_waitcnt +//===----------------------------------------------------------------------===// + +s_waitcnt 0 +// GFX12: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf] + +s_waitcnt 0x1234 +// GFX12: s_waitcnt vmcnt(4) expcnt(4) lgkmcnt(35) ; encoding: [0x34,0x12,0x89,0xbf] + +s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0) +// GFX12: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf] + +s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +// GFX12: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf] + +s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0) +// GFX12: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x89,0xbf] + +s_waitcnt vmcnt(1) +// GFX12: s_waitcnt vmcnt(1) ; encoding: [0xf7,0x07,0x89,0xbf] + +s_waitcnt vmcnt(9) +// GFX12: s_waitcnt vmcnt(9) ; encoding: [0xf7,0x27,0x89,0xbf] + +s_waitcnt expcnt(2) +// GFX12: s_waitcnt expcnt(2) ; encoding: [0xf2,0xff,0x89,0xbf] + +s_waitcnt lgkmcnt(3) +// GFX12: s_waitcnt lgkmcnt(3) ; encoding: [0x37,0xfc,0x89,0xbf] + +s_waitcnt lgkmcnt(9) +// GFX12: s_waitcnt lgkmcnt(9) ; encoding: [0x97,0xfc,0x89,0xbf] + +s_waitcnt vmcnt(0), expcnt(0) +// GFX12: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0xf0,0x03,0x89,0xbf] + +s_waitcnt vmcnt(15) +// GFX12: s_waitcnt vmcnt(15) ; encoding: [0xf7,0x3f,0x89,0xbf] + +s_waitcnt vmcnt(15) expcnt(6) +// GFX12: s_waitcnt vmcnt(15) expcnt(6) ; encoding: [0xf6,0x3f,0x89,0xbf] + +s_waitcnt vmcnt(15) lgkmcnt(14) +// GFX12: s_waitcnt vmcnt(15) lgkmcnt(14) ; encoding: [0xe7,0x3c,0x89,0xbf] + +s_waitcnt vmcnt(15) expcnt(6) lgkmcnt(14) +// GFX12: s_waitcnt vmcnt(15) expcnt(6) lgkmcnt(14) ; encoding: [0xe6,0x3c,0x89,0xbf] + +s_waitcnt vmcnt(31) +// GFX12: s_waitcnt vmcnt(31) ; encoding: [0xf7,0x7f,0x89,0xbf] + +s_waitcnt vmcnt(31) expcnt(6) +// GFX12: s_waitcnt vmcnt(31) expcnt(6) ; encoding: [0xf6,0x7f,0x89,0xbf] + +s_waitcnt vmcnt(31) lgkmcnt(14) +// GFX12: s_waitcnt vmcnt(31) lgkmcnt(14) ; encoding: [0xe7,0x7c,0x89,0xbf] + +s_waitcnt vmcnt(31) expcnt(6) lgkmcnt(14) +// GFX12: s_waitcnt vmcnt(31) expcnt(6) lgkmcnt(14) ; encoding: [0xe6,0x7c,0x89,0xbf] + +s_waitcnt vmcnt(62) +// GFX12: s_waitcnt vmcnt(62) ; encoding: [0xf7,0xfb,0x89,0xbf] + +s_waitcnt vmcnt(62) expcnt(6) +// GFX12: s_waitcnt vmcnt(62) expcnt(6) ; encoding: [0xf6,0xfb,0x89,0xbf] + +s_waitcnt vmcnt(62) lgkmcnt(14) +// GFX12: s_waitcnt vmcnt(62) lgkmcnt(14) ; encoding: [0xe7,0xf8,0x89,0xbf] + +s_waitcnt vmcnt(62) expcnt(6) lgkmcnt(14) +// GFX12: s_waitcnt vmcnt(62) expcnt(6) lgkmcnt(14) ; encoding: [0xe6,0xf8,0x89,0xbf] + +//===----------------------------------------------------------------------===// +// s_sendmsg +//===----------------------------------------------------------------------===// + +s_sendmsg 2 +// GFX12: s_sendmsg sendmsg(MSG_HS_TESSFACTOR) ; encoding: [0x02,0x00,0xb6,0xbf] + +s_sendmsg 0xc1d1 +// GFX12: s_sendmsg 49617 ; encoding: [0xd1,0xc1,0xb6,0xbf] + +s_sendmsg sendmsg(MSG_HS_TESSFACTOR) +// GFX12: s_sendmsg sendmsg(MSG_HS_TESSFACTOR) ; encoding: [0x02,0x00,0xb6,0xbf] + +s_sendmsg 3 +// GFX12: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; encoding: [0x03,0x00,0xb6,0xbf] + +s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +// GFX12: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; encoding: [0x03,0x00,0xb6,0xbf] + +//===----------------------------------------------------------------------===// +// s_delay_alu +//===----------------------------------------------------------------------===// + +s_delay_alu 0 +// GFX12: s_delay_alu 0 ; encoding: [0x00,0x00,0x87,0xbf] + +s_delay_alu 0x91 +// GFX12: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; encoding: [0x91,0x00,0x87,0xbf] + +s_delay_alu instid0(VALU_DEP_1) +// GFX12: s_delay_alu instid0(VALU_DEP_1) ; encoding: [0x01,0x00,0x87,0xbf] + +s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +// GFX12: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; encoding: [0x81,0x04,0x87,0xbf] + +s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) +// GFX12: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; encoding: [0x91,0x01,0x87,0xbf] + +s_delay_alu instid1(SALU_CYCLE_2) +// GFX12: s_delay_alu instid1(SALU_CYCLE_2) ; encoding: [0x00,0x05,0x87,0xbf] + +s_delay_alu instid1(SALU_CYCLE_3) +// GFX12: s_delay_alu instid1(SALU_CYCLE_3) ; encoding: [0x80,0x05,0x87,0xbf] + +s_wait_idle +// GFX12: s_wait_idle ; encoding: [0x00,0x00,0x8a,0xbf] + +s_nop 0x0 +// GFX12: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf] + +s_nop 0x1234 +// GFX12: s_nop 0x1234 ; encoding: [0x34,0x12,0x80,0xbf] + +s_nop 0xc1d1 +// GFX12: s_nop 0xc1d1 ; encoding: [0xd1,0xc1,0x80,0xbf] + +s_endpgm +// GFX12: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] + +s_endpgm 1 +// GFX12: s_endpgm 1 ; encoding: [0x01,0x00,0xb0,0xbf] + +s_endpgm 65535 +// GFX12: s_endpgm 65535 ; encoding: [0xff,0xff,0xb0,0xbf] + +s_branch 0x0 +// GFX12: s_branch 0 ; encoding: [0x00,0x00,0xa0,0xbf] + +s_branch 0x1234 +// GFX12: s_branch 4660 ; encoding: [0x34,0x12,0xa0,0xbf] + +s_wakeup +// GFX12: s_wakeup ; encoding: [0x00,0x00,0xb4,0xbf] + +s_cbranch_scc0 0x0 +// GFX12: s_cbranch_scc0 0 ; encoding: [0x00,0x00,0xa1,0xbf] + +s_cbranch_scc0 0x1234 +// GFX12: s_cbranch_scc0 4660 ; encoding: [0x34,0x12,0xa1,0xbf] + +s_cbranch_scc1 0x0 +// GFX12: s_cbranch_scc1 0 ; encoding: [0x00,0x00,0xa2,0xbf] + +s_cbranch_scc1 0x1234 +// GFX12: s_cbranch_scc1 4660 ; encoding: [0x34,0x12,0xa2,0xbf] + +s_cbranch_vccz 0x0 +// GFX12: s_cbranch_vccz 0 ; encoding: [0x00,0x00,0xa3,0xbf] + +s_cbranch_vccz 0x1234 +// GFX12: s_cbranch_vccz 4660 ; encoding: [0x34,0x12,0xa3,0xbf] + +s_cbranch_vccnz 0x0 +// GFX12: s_cbranch_vccnz 0 ; encoding: [0x00,0x00,0xa4,0xbf] + +s_cbranch_vccnz 0x1234 +// GFX12: s_cbranch_vccnz 4660 ; encoding: [0x34,0x12,0xa4,0xbf] + +s_cbranch_execz 0x0 +// GFX12: s_cbranch_execz 0 ; encoding: [0x00,0x00,0xa5,0xbf] + +s_cbranch_execz 0x1234 +// GFX12: s_cbranch_execz 4660 ; encoding: [0x34,0x12,0xa5,0xbf] + +s_cbranch_execnz 0x0 +// GFX12: s_cbranch_execnz 0 ; encoding: [0x00,0x00,0xa6,0xbf] + +s_cbranch_execnz 0x1234 +// GFX12: s_cbranch_execnz 4660 ; encoding: [0x34,0x12,0xa6,0xbf] + +s_barrier +// GFX12: s_barrier ; encoding: [0x00,0x00,0xbd,0xbf] + +s_setkill 0x0 +// GFX12: s_setkill 0 ; encoding: [0x00,0x00,0x81,0xbf] + +s_setkill 0x1234 +// GFX12: s_setkill 0x1234 ; encoding: [0x34,0x12,0x81,0xbf] + +s_setkill 0xc1d1 +// GFX12: s_setkill 0xc1d1 ; encoding: [0xd1,0xc1,0x81,0xbf] + +s_sethalt 0x0 +// GFX12: s_sethalt 0 ; encoding: [0x00,0x00,0x82,0xbf] + +s_sethalt 0x1234 +// GFX12: s_sethalt 0x1234 ; encoding: [0x34,0x12,0x82,0xbf] + +s_sethalt 0xc1d1 +// GFX12: s_sethalt 0xc1d1 ; encoding: [0xd1,0xc1,0x82,0xbf] + +s_sleep 0x0 +// GFX12: s_sleep 0 ; encoding: [0x00,0x00,0x83,0xbf] + +s_sleep 0x1234 +// GFX12: s_sleep 0x1234 ; encoding: [0x34,0x12,0x83,0xbf] + +s_sleep 0xc1d1 +// GFX12: s_sleep 0xc1d1 ; encoding: [0xd1,0xc1,0x83,0xbf] + +s_setprio 0x0 +// GFX12: s_setprio 0 ; encoding: [0x00,0x00,0xb5,0xbf] + +s_setprio 0x1234 +// GFX12: s_setprio 0x1234 ; encoding: [0x34,0x12,0xb5,0xbf] + +s_setprio 0xc1d1 +// GFX12: s_setprio 0xc1d1 ; encoding: [0xd1,0xc1,0xb5,0xbf] + +s_sendmsghalt 0x0 +// GFX12: s_sendmsghalt sendmsg(0, 0, 0) ; encoding: [0x00,0x00,0xb7,0xbf] + +s_sendmsghalt 0x1234 +// GFX12: s_sendmsghalt 4660 ; encoding: [0x34,0x12,0xb7,0xbf] + +s_sendmsghalt 0xc1d1 +// GFX12: s_sendmsghalt 49617 ; encoding: [0xd1,0xc1,0xb7,0xbf] + +s_trap 0x0 +// GFX12: s_trap 0 ; encoding: [0x00,0x00,0x90,0xbf] + +s_trap 0x1234 +// GFX12: s_trap 0x1234 ; encoding: [0x34,0x12,0x90,0xbf] + +s_trap 0xc1d1 +// GFX12: s_trap 0xc1d1 ; encoding: [0xd1,0xc1,0x90,0xbf] + +s_icache_inv +// GFX12: s_icache_inv ; encoding: [0x00,0x00,0xbc,0xbf] + +s_incperflevel 0x0 +// GFX12: s_incperflevel 0 ; encoding: [0x00,0x00,0xb8,0xbf] + +s_incperflevel 0x1234 +// GFX12: s_incperflevel 0x1234 ; encoding: [0x34,0x12,0xb8,0xbf] + +s_incperflevel 0xc1d1 +// GFX12: s_incperflevel 0xc1d1 ; encoding: [0xd1,0xc1,0xb8,0xbf] + +s_decperflevel 0x0 +// GFX12: s_decperflevel 0 ; encoding: [0x00,0x00,0xb9,0xbf] + +s_decperflevel 0x1234 +// GFX12: s_decperflevel 0x1234 ; encoding: [0x34,0x12,0xb9,0xbf] + +s_decperflevel 0xc1d1 +// GFX12: s_decperflevel 0xc1d1 ; encoding: [0xd1,0xc1,0xb9,0xbf] + +s_ttracedata +// GFX12: s_ttracedata ; encoding: [0x00,0x00,0xba,0xbf] + +s_endpgm_saved +// GFX12: s_endpgm_saved ; encoding: [0x00,0x00,0xb1,0xbf] + +s_code_end +// GFX12: s_code_end ; encoding: [0x00,0x00,0x9f,0xbf] + +s_clause 0x0 +// GFX12: s_clause 0x0 ; encoding: [0x00,0x00,0x85,0xbf] + +s_clause 0x1234 +// GFX12: s_clause 0x1234 ; encoding: [0x34,0x12,0x85,0xbf] + +s_clause 0xc1d1 +// GFX12: s_clause 0xc1d1 ; encoding: [0xd1,0xc1,0x85,0xbf] + +s_round_mode 0x0 +// GFX12: s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf] + +s_round_mode 0x1234 +// GFX12: s_round_mode 0x1234 ; encoding: [0x34,0x12,0x91,0xbf] + +s_round_mode 0xc1d1 +// GFX12: s_round_mode 0xc1d1 ; encoding: [0xd1,0xc1,0x91,0xbf] + +s_denorm_mode 0x0 +// GFX12: s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf] + +s_denorm_mode 0x1234 +// GFX12: s_denorm_mode 0x1234 ; encoding: [0x34,0x12,0x92,0xbf] + +s_denorm_mode 0xc1d1 +// GFX12: s_denorm_mode 0xc1d1 ; encoding: [0xd1,0xc1,0x92,0xbf] + +s_ttracedata_imm 0x0 +// GFX12: s_ttracedata_imm 0x0 ; encoding: [0x00,0x00,0xbb,0xbf] + +s_ttracedata_imm 0x1234 +// GFX12: s_ttracedata_imm 0x1234 ; encoding: [0x34,0x12,0xbb,0xbf] + +s_ttracedata_imm 0xc1d1 +// GFX12: s_ttracedata_imm 0xc1d1 ; encoding: [0xd1,0xc1,0xbb,0xbf] + +s_wait_event 0x3141 +// GFX12: s_wait_event 0x3141 ; encoding: [0x41,0x31,0x8b,0xbf] + +s_wait_event 0xc1d1 +// GFX12: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf] diff --git a/llvm/test/MC/AMDGPU/gfx12_err.s b/llvm/test/MC/AMDGPU/gfx12_err.s index 93e3cc1498d2..b23e60082ffe 100644 --- a/llvm/test/MC/AMDGPU/gfx12_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_err.s @@ -41,3 +41,8 @@ image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_HT scope:SCOPE image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_SE th:TH_LOAD_HT scope:SCOPE_SE // GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand + +s_prefetch_inst s[14:15], 0xffffff, m0, 7 +// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 24-bit signed offset +// GFX12-ERR: s_prefetch_inst s[14:15], 0xffffff, m0, 7 +// GFX12-ERR: ^ diff --git a/llvm/test/MC/AMDGPU/gfx12_unsupported.s b/llvm/test/MC/AMDGPU/gfx12_unsupported.s new file mode 100644 index 000000000000..c9eb29c18a1a --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_unsupported.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 %s 2>&1 | FileCheck --implicit-check-not=error: %s + +//===----------------------------------------------------------------------===// +// Unsupported instructions. +//===----------------------------------------------------------------------===// + +s_subvector_loop_begin s0, 0x1234 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +s_subvector_loop_end s0, 0x1234 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_smem.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_smem.txt new file mode 100644 index 000000000000..7843905797a6 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_smem.txt @@ -0,0 +1,31 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s + +# GFX12: s_prefetch_inst s[12:13], 0x10, s4, 2 ; encoding: [0x86,0x80,0x04,0xf4,0x10,0x00,0x00,0x08] +0x86,0x80,0x04,0xf4,0x10,0x00,0x00,0x08 + +# GFX12: s_prefetch_inst s[14:15], 0x0, m0, 7 ; encoding: [0xc7,0x81,0x04,0xf4,0x00,0x00,0x00,0xfa] +0xc7,0x81,0x04,0xf4,0x00,0x00,0x00,0xfa + +# GFX12: s_prefetch_inst s[14:15], 0x7fffff, m0, 7 ; encoding: [0xc7,0x81,0x04,0xf4,0xff,0xff,0x7f,0xfa] +0xc7,0x81,0x04,0xf4,0xff,0xff,0x7f,0xfa + +# GFX12: s_prefetch_inst s[14:15], -0x1, m0, 7 ; encoding: [0xc7,0x81,0x04,0xf4,0xff,0xff,0xff,0xfa] +0xc7,0x81,0x04,0xf4,0xff,0xff,0xff,0xfa + +# GFX12: s_prefetch_inst s[14:15], 0x64, m0, 31 ; encoding: [0xc7,0x87,0x04,0xf4,0x64,0x00,0x00,0xfa] +0xc7,0x87,0x04,0xf4,0x64,0x00,0x00,0xfa + +# GFX12: s_prefetch_inst_pc_rel 0x64, s10, 7 ; encoding: [0xc0,0xa1,0x04,0xf4,0x64,0x00,0x00,0x14] +0xc0,0xa1,0x04,0xf4,0x64,0x00,0x00,0x14 + +# GFX12: s_prefetch_data s[18:19], 0x64, s10, 7 ; encoding: [0xc9,0xc1,0x04,0xf4,0x64,0x00,0x00,0x14] +0xc9,0xc1,0x04,0xf4,0x64,0x00,0x00,0x14 + +# GFX12: s_prefetch_data_pc_rel 0x64, s10, 7 ; encoding: [0xc0,0x01,0x05,0xf4,0x64,0x00,0x00,0x14] +0xc0,0x01,0x05,0xf4,0x64,0x00,0x00,0x14 + +# GFX12: s_buffer_prefetch_data s[20:23], 0x64, s10, 7 ; encoding: [0xca,0xe1,0x04,0xf4,0x64,0x00,0x00,0x14] +0xca,0xe1,0x04,0xf4,0x64,0x00,0x00,0x14 + +# GFX12: s_buffer_prefetch_data s[20:23], 0x64, null, 7 ; encoding: [0xca,0xe1,0x04,0xf4,0x64,0x00,0x00,0xf8] +0xca,0xe1,0x04,0xf4,0x64,0x00,0x00,0xf8 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt new file mode 100644 index 000000000000..7029f090faa4 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt @@ -0,0 +1,3649 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s + +# GFX12: s_cvt_f32_i32 s5, s1 ; encoding: [0x01,0x64,0x85,0xbe] +0x01,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s105, s1 ; encoding: [0x01,0x64,0xe9,0xbe] +0x01,0x64,0xe9,0xbe + +# GFX12: s_cvt_f32_i32 s5, s105 ; encoding: [0x69,0x64,0x85,0xbe] +0x69,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, s103 ; encoding: [0x67,0x64,0x85,0xbe] +0x67,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, vcc_lo ; encoding: [0x6a,0x64,0x85,0xbe] +0x6a,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, vcc_hi ; encoding: [0x6b,0x64,0x85,0xbe] +0x6b,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, ttmp11 ; encoding: [0x77,0x64,0x85,0xbe] +0x77,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, m0 ; encoding: [0x7d,0x64,0x85,0xbe] +0x7d,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, exec_lo ; encoding: [0x7e,0x64,0x85,0xbe] +0x7e,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, exec_hi ; encoding: [0x7f,0x64,0x85,0xbe] +0x7f,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, 0 ; encoding: [0x80,0x64,0x85,0xbe] +0x80,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, -1 ; encoding: [0xc1,0x64,0x85,0xbe] +0xc1,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, 0.5 ; encoding: [0xf0,0x64,0x85,0xbe] +0xf0,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, -4.0 ; encoding: [0xf7,0x64,0x85,0xbe] +0xf7,0x64,0x85,0xbe + +# GFX12: s_cvt_f32_i32 s5, 0xaf123456 ; encoding: [0xff,0x64,0x85,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x64,0x85,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_cvt_f32_i32 s5, 0x3f717273 ; encoding: [0xff,0x64,0x85,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x64,0x85,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_cvt_f32_u32 s5, s1 ; encoding: [0x01,0x65,0x85,0xbe] +0x01,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s105, s1 ; encoding: [0x01,0x65,0xe9,0xbe] +0x01,0x65,0xe9,0xbe + +# GFX12: s_cvt_f32_u32 s5, s105 ; encoding: [0x69,0x65,0x85,0xbe] +0x69,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, s103 ; encoding: [0x67,0x65,0x85,0xbe] +0x67,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, vcc_lo ; encoding: [0x6a,0x65,0x85,0xbe] +0x6a,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, vcc_hi ; encoding: [0x6b,0x65,0x85,0xbe] +0x6b,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, ttmp11 ; encoding: [0x77,0x65,0x85,0xbe] +0x77,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, m0 ; encoding: [0x7d,0x65,0x85,0xbe] +0x7d,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, exec_lo ; encoding: [0x7e,0x65,0x85,0xbe] +0x7e,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, exec_hi ; encoding: [0x7f,0x65,0x85,0xbe] +0x7f,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, 0 ; encoding: [0x80,0x65,0x85,0xbe] +0x80,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, -1 ; encoding: [0xc1,0x65,0x85,0xbe] +0xc1,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, 0.5 ; encoding: [0xf0,0x65,0x85,0xbe] +0xf0,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, -4.0 ; encoding: [0xf7,0x65,0x85,0xbe] +0xf7,0x65,0x85,0xbe + +# GFX12: s_cvt_f32_u32 s5, 0xaf123456 ; encoding: [0xff,0x65,0x85,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x65,0x85,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_cvt_f32_u32 s5, 0x3f717273 ; encoding: [0xff,0x65,0x85,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x65,0x85,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_cvt_u32_f32 s5, s1 ; encoding: [0x01,0x67,0x85,0xbe] +0x01,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s105, s1 ; encoding: [0x01,0x67,0xe9,0xbe] +0x01,0x67,0xe9,0xbe + +# GFX12: s_cvt_u32_f32 s5, s105 ; encoding: [0x69,0x67,0x85,0xbe] +0x69,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, s103 ; encoding: [0x67,0x67,0x85,0xbe] +0x67,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, vcc_lo ; encoding: [0x6a,0x67,0x85,0xbe] +0x6a,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, vcc_hi ; encoding: [0x6b,0x67,0x85,0xbe] +0x6b,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, ttmp11 ; encoding: [0x77,0x67,0x85,0xbe] +0x77,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, m0 ; encoding: [0x7d,0x67,0x85,0xbe] +0x7d,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, exec_lo ; encoding: [0x7e,0x67,0x85,0xbe] +0x7e,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, exec_hi ; encoding: [0x7f,0x67,0x85,0xbe] +0x7f,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, 0 ; encoding: [0x80,0x67,0x85,0xbe] +0x80,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, -1 ; encoding: [0xc1,0x67,0x85,0xbe] +0xc1,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, 0.5 ; encoding: [0xf0,0x67,0x85,0xbe] +0xf0,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, -4.0 ; encoding: [0xf7,0x67,0x85,0xbe] +0xf7,0x67,0x85,0xbe + +# GFX12: s_cvt_u32_f32 s5, 0xaf123456 ; encoding: [0xff,0x67,0x85,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x67,0x85,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_cvt_u32_f32 s5, 0x3f717273 ; encoding: [0xff,0x67,0x85,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x67,0x85,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_cvt_i32_f32 s5, s1 ; encoding: [0x01,0x66,0x85,0xbe] +0x01,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s105, s1 ; encoding: [0x01,0x66,0xe9,0xbe] +0x01,0x66,0xe9,0xbe + +# GFX12: s_cvt_i32_f32 s5, s105 ; encoding: [0x69,0x66,0x85,0xbe] +0x69,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, s103 ; encoding: [0x67,0x66,0x85,0xbe] +0x67,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, vcc_lo ; encoding: [0x6a,0x66,0x85,0xbe] +0x6a,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, vcc_hi ; encoding: [0x6b,0x66,0x85,0xbe] +0x6b,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, ttmp11 ; encoding: [0x77,0x66,0x85,0xbe] +0x77,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, m0 ; encoding: [0x7d,0x66,0x85,0xbe] +0x7d,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, exec_lo ; encoding: [0x7e,0x66,0x85,0xbe] +0x7e,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, exec_hi ; encoding: [0x7f,0x66,0x85,0xbe] +0x7f,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, 0 ; encoding: [0x80,0x66,0x85,0xbe] +0x80,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, -1 ; encoding: [0xc1,0x66,0x85,0xbe] +0xc1,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, 0.5 ; encoding: [0xf0,0x66,0x85,0xbe] +0xf0,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, -4.0 ; encoding: [0xf7,0x66,0x85,0xbe] +0xf7,0x66,0x85,0xbe + +# GFX12: s_cvt_i32_f32 s5, 0xaf123456 ; encoding: [0xff,0x66,0x85,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x66,0x85,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_cvt_i32_f32 s5, 0x3f717273 ; encoding: [0xff,0x66,0x85,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x66,0x85,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_cvt_f16_f32 s5, s1 ; encoding: [0x01,0x68,0x85,0xbe] +0x01,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s105, s1 ; encoding: [0x01,0x68,0xe9,0xbe] +0x01,0x68,0xe9,0xbe + +# GFX12: s_cvt_f16_f32 s5, s105 ; encoding: [0x69,0x68,0x85,0xbe] +0x69,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, s103 ; encoding: [0x67,0x68,0x85,0xbe] +0x67,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, vcc_lo ; encoding: [0x6a,0x68,0x85,0xbe] +0x6a,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, vcc_hi ; encoding: [0x6b,0x68,0x85,0xbe] +0x6b,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, ttmp11 ; encoding: [0x77,0x68,0x85,0xbe] +0x77,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, m0 ; encoding: [0x7d,0x68,0x85,0xbe] +0x7d,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, exec_lo ; encoding: [0x7e,0x68,0x85,0xbe] +0x7e,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, exec_hi ; encoding: [0x7f,0x68,0x85,0xbe] +0x7f,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, 0 ; encoding: [0x80,0x68,0x85,0xbe] +0x80,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, -1 ; encoding: [0xc1,0x68,0x85,0xbe] +0xc1,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, 0.5 ; encoding: [0xf0,0x68,0x85,0xbe] +0xf0,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, -4.0 ; encoding: [0xf7,0x68,0x85,0xbe] +0xf7,0x68,0x85,0xbe + +# GFX12: s_cvt_f16_f32 s5, 0xaf123456 ; encoding: [0xff,0x68,0x85,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x68,0x85,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_cvt_f16_f32 s5, 0x3f717273 ; encoding: [0xff,0x68,0x85,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x68,0x85,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_cvt_f32_f16 s5, s1 ; encoding: [0x01,0x69,0x85,0xbe] +0x01,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s105, s1 ; encoding: [0x01,0x69,0xe9,0xbe] +0x01,0x69,0xe9,0xbe + +# GFX12: s_cvt_f32_f16 s5, s105 ; encoding: [0x69,0x69,0x85,0xbe] +0x69,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s5, s103 ; encoding: [0x67,0x69,0x85,0xbe] +0x67,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s5, vcc_lo ; encoding: [0x6a,0x69,0x85,0xbe] +0x6a,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s5, vcc_hi ; encoding: [0x6b,0x69,0x85,0xbe] +0x6b,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s5, ttmp11 ; encoding: [0x77,0x69,0x85,0xbe] +0x77,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s5, m0 ; encoding: [0x7d,0x69,0x85,0xbe] +0x7d,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s5, exec_lo ; encoding: [0x7e,0x69,0x85,0xbe] +0x7e,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s5, exec_hi ; encoding: [0x7f,0x69,0x85,0xbe] +0x7f,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s5, 0 ; encoding: [0x80,0x69,0x85,0xbe] +0x80,0x69,0x85,0xbe + +# GFX12: s_cvt_f32_f16 s5, -1 ; encoding: [0xc1,0x69,0x85,0xbe] +0xc1,0x69,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, s1 ; encoding: [0x01,0x6a,0x85,0xbe] +0x01,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s105, s1 ; encoding: [0x01,0x6a,0xe9,0xbe] +0x01,0x6a,0xe9,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, s105 ; encoding: [0x69,0x6a,0x85,0xbe] +0x69,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, s103 ; encoding: [0x67,0x6a,0x85,0xbe] +0x67,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, vcc_lo ; encoding: [0x6a,0x6a,0x85,0xbe] +0x6a,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, vcc_hi ; encoding: [0x6b,0x6a,0x85,0xbe] +0x6b,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, ttmp11 ; encoding: [0x77,0x6a,0x85,0xbe] +0x77,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, m0 ; encoding: [0x7d,0x6a,0x85,0xbe] +0x7d,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, exec_lo ; encoding: [0x7e,0x6a,0x85,0xbe] +0x7e,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, exec_hi ; encoding: [0x7f,0x6a,0x85,0xbe] +0x7f,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, 0 ; encoding: [0x80,0x6a,0x85,0xbe] +0x80,0x6a,0x85,0xbe + +# GFX12: s_cvt_hi_f32_f16 s5, -1 ; encoding: [0xc1,0x6a,0x85,0xbe] +0xc1,0x6a,0x85,0xbe + +# GFX12: s_trunc_f32 s5, s1 ; encoding: [0x01,0x62,0x85,0xbe] +0x01,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s105, s1 ; encoding: [0x01,0x62,0xe9,0xbe] +0x01,0x62,0xe9,0xbe + +# GFX12: s_trunc_f32 s5, s105 ; encoding: [0x69,0x62,0x85,0xbe] +0x69,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, s103 ; encoding: [0x67,0x62,0x85,0xbe] +0x67,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, vcc_lo ; encoding: [0x6a,0x62,0x85,0xbe] +0x6a,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, vcc_hi ; encoding: [0x6b,0x62,0x85,0xbe] +0x6b,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, ttmp11 ; encoding: [0x77,0x62,0x85,0xbe] +0x77,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, m0 ; encoding: [0x7d,0x62,0x85,0xbe] +0x7d,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, exec_lo ; encoding: [0x7e,0x62,0x85,0xbe] +0x7e,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, exec_hi ; encoding: [0x7f,0x62,0x85,0xbe] +0x7f,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, 0 ; encoding: [0x80,0x62,0x85,0xbe] +0x80,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, -1 ; encoding: [0xc1,0x62,0x85,0xbe] +0xc1,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, 0.5 ; encoding: [0xf0,0x62,0x85,0xbe] +0xf0,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, -4.0 ; encoding: [0xf7,0x62,0x85,0xbe] +0xf7,0x62,0x85,0xbe + +# GFX12: s_trunc_f32 s5, 0xaf123456 ; encoding: [0xff,0x62,0x85,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x62,0x85,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_trunc_f32 s5, 0x3f717273 ; encoding: [0xff,0x62,0x85,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x62,0x85,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_ceil_f32 s5, s1 ; encoding: [0x01,0x60,0x85,0xbe] +0x01,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s105, s1 ; encoding: [0x01,0x60,0xe9,0xbe] +0x01,0x60,0xe9,0xbe + +# GFX12: s_ceil_f32 s5, s105 ; encoding: [0x69,0x60,0x85,0xbe] +0x69,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, s103 ; encoding: [0x67,0x60,0x85,0xbe] +0x67,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, vcc_lo ; encoding: [0x6a,0x60,0x85,0xbe] +0x6a,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, vcc_hi ; encoding: [0x6b,0x60,0x85,0xbe] +0x6b,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, ttmp11 ; encoding: [0x77,0x60,0x85,0xbe] +0x77,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, m0 ; encoding: [0x7d,0x60,0x85,0xbe] +0x7d,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, exec_lo ; encoding: [0x7e,0x60,0x85,0xbe] +0x7e,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, exec_hi ; encoding: [0x7f,0x60,0x85,0xbe] +0x7f,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, 0 ; encoding: [0x80,0x60,0x85,0xbe] +0x80,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, -1 ; encoding: [0xc1,0x60,0x85,0xbe] +0xc1,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, 0.5 ; encoding: [0xf0,0x60,0x85,0xbe] +0xf0,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, -4.0 ; encoding: [0xf7,0x60,0x85,0xbe] +0xf7,0x60,0x85,0xbe + +# GFX12: s_ceil_f32 s5, 0xaf123456 ; encoding: [0xff,0x60,0x85,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x60,0x85,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_ceil_f32 s5, 0x3f717273 ; encoding: [0xff,0x60,0x85,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x60,0x85,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_rndne_f32 s5, s1 ; encoding: [0x01,0x63,0x85,0xbe] +0x01,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s105, s1 ; encoding: [0x01,0x63,0xe9,0xbe] +0x01,0x63,0xe9,0xbe + +# GFX12: s_rndne_f32 s5, s105 ; encoding: [0x69,0x63,0x85,0xbe] +0x69,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, s103 ; encoding: [0x67,0x63,0x85,0xbe] +0x67,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, vcc_lo ; encoding: [0x6a,0x63,0x85,0xbe] +0x6a,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, vcc_hi ; encoding: [0x6b,0x63,0x85,0xbe] +0x6b,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, ttmp11 ; encoding: [0x77,0x63,0x85,0xbe] +0x77,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, m0 ; encoding: [0x7d,0x63,0x85,0xbe] +0x7d,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, exec_lo ; encoding: [0x7e,0x63,0x85,0xbe] +0x7e,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, exec_hi ; encoding: [0x7f,0x63,0x85,0xbe] +0x7f,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, 0 ; encoding: [0x80,0x63,0x85,0xbe] +0x80,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, -1 ; encoding: [0xc1,0x63,0x85,0xbe] +0xc1,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, 0.5 ; encoding: [0xf0,0x63,0x85,0xbe] +0xf0,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, -4.0 ; encoding: [0xf7,0x63,0x85,0xbe] +0xf7,0x63,0x85,0xbe + +# GFX12: s_rndne_f32 s5, 0xaf123456 ; encoding: [0xff,0x63,0x85,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x63,0x85,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_rndne_f32 s5, 0x3f717273 ; encoding: [0xff,0x63,0x85,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x63,0x85,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_floor_f32 s5, s1 ; encoding: [0x01,0x61,0x85,0xbe] +0x01,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s105, s1 ; encoding: [0x01,0x61,0xe9,0xbe] +0x01,0x61,0xe9,0xbe + +# GFX12: s_floor_f32 s5, s105 ; encoding: [0x69,0x61,0x85,0xbe] +0x69,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, s103 ; encoding: [0x67,0x61,0x85,0xbe] +0x67,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, vcc_lo ; encoding: [0x6a,0x61,0x85,0xbe] +0x6a,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, vcc_hi ; encoding: [0x6b,0x61,0x85,0xbe] +0x6b,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, ttmp11 ; encoding: [0x77,0x61,0x85,0xbe] +0x77,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, m0 ; encoding: [0x7d,0x61,0x85,0xbe] +0x7d,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, exec_lo ; encoding: [0x7e,0x61,0x85,0xbe] +0x7e,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, exec_hi ; encoding: [0x7f,0x61,0x85,0xbe] +0x7f,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, 0 ; encoding: [0x80,0x61,0x85,0xbe] +0x80,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, -1 ; encoding: [0xc1,0x61,0x85,0xbe] +0xc1,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, 0.5 ; encoding: [0xf0,0x61,0x85,0xbe] +0xf0,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, -4.0 ; encoding: [0xf7,0x61,0x85,0xbe] +0xf7,0x61,0x85,0xbe + +# GFX12: s_floor_f32 s5, 0xaf123456 ; encoding: [0xff,0x61,0x85,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x61,0x85,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_floor_f32 s5, 0x3f717273 ; encoding: [0xff,0x61,0x85,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x61,0x85,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_floor_f16 s5, s1 ; encoding: [0x01,0x6c,0x85,0xbe] +0x01,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s105, s1 ; encoding: [0x01,0x6c,0xe9,0xbe] +0x01,0x6c,0xe9,0xbe + +# GFX12: s_floor_f16 s5, s105 ; encoding: [0x69,0x6c,0x85,0xbe] +0x69,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, s101 ; encoding: [0x65,0x6c,0x85,0xbe] +0x65,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, vcc_lo ; encoding: [0x6a,0x6c,0x85,0xbe] +0x6a,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, vcc_hi ; encoding: [0x6b,0x6c,0x85,0xbe] +0x6b,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, m0 ; encoding: [0x7d,0x6c,0x85,0xbe] +0x7d,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, exec_lo ; encoding: [0x7e,0x6c,0x85,0xbe] +0x7e,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, exec_hi ; encoding: [0x7f,0x6c,0x85,0xbe] +0x7f,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, 0 ; encoding: [0x80,0x6c,0x85,0xbe] +0x80,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, -1 ; encoding: [0xc1,0x6c,0x85,0xbe] +0xc1,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, 0.5 ; encoding: [0xf0,0x6c,0x85,0xbe] +0xf0,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, -4.0 ; encoding: [0xf7,0x6c,0x85,0xbe] +0xf7,0x6c,0x85,0xbe + +# GFX12: s_floor_f16 s5, 0xfe0b ; encoding: [0xff,0x6c,0x85,0xbe,0x0b,0xfe,0x00,0x00] +0xff,0x6c,0x85,0xbe,0x0b,0xfe,0x00,0x00 + +# GFX12: s_floor_f16 s5, 0x3456 ; encoding: [0xff,0x6c,0x85,0xbe,0x56,0x34,0x00,0x00] +0xff,0x6c,0x85,0xbe,0x56,0x34,0x00,0x00 + +# GFX12: s_ceil_f16 s5, s1 ; encoding: [0x01,0x6b,0x85,0xbe] +0x01,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s105, s1 ; encoding: [0x01,0x6b,0xe9,0xbe] +0x01,0x6b,0xe9,0xbe + +# GFX12: s_ceil_f16 s5, s105 ; encoding: [0x69,0x6b,0x85,0xbe] +0x69,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, s101 ; encoding: [0x65,0x6b,0x85,0xbe] +0x65,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, vcc_lo ; encoding: [0x6a,0x6b,0x85,0xbe] +0x6a,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, vcc_hi ; encoding: [0x6b,0x6b,0x85,0xbe] +0x6b,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, m0 ; encoding: [0x7d,0x6b,0x85,0xbe] +0x7d,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, exec_lo ; encoding: [0x7e,0x6b,0x85,0xbe] +0x7e,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, exec_hi ; encoding: [0x7f,0x6b,0x85,0xbe] +0x7f,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, 0 ; encoding: [0x80,0x6b,0x85,0xbe] +0x80,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, -1 ; encoding: [0xc1,0x6b,0x85,0xbe] +0xc1,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, 0.5 ; encoding: [0xf0,0x6b,0x85,0xbe] +0xf0,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, -4.0 ; encoding: [0xf7,0x6b,0x85,0xbe] +0xf7,0x6b,0x85,0xbe + +# GFX12: s_ceil_f16 s5, 0xfe0b ; encoding: [0xff,0x6b,0x85,0xbe,0x0b,0xfe,0x00,0x00] +0xff,0x6b,0x85,0xbe,0x0b,0xfe,0x00,0x00 + +# GFX12: s_ceil_f16 s5, 0x3456 ; encoding: [0xff,0x6b,0x85,0xbe,0x56,0x34,0x00,0x00] +0xff,0x6b,0x85,0xbe,0x56,0x34,0x00,0x00 + +# GFX12: s_trunc_f16 s5, s1 ; encoding: [0x01,0x6d,0x85,0xbe] +0x01,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s105, s1 ; encoding: [0x01,0x6d,0xe9,0xbe] +0x01,0x6d,0xe9,0xbe + +# GFX12: s_trunc_f16 s5, s105 ; encoding: [0x69,0x6d,0x85,0xbe] +0x69,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, s101 ; encoding: [0x65,0x6d,0x85,0xbe] +0x65,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, vcc_lo ; encoding: [0x6a,0x6d,0x85,0xbe] +0x6a,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, vcc_hi ; encoding: [0x6b,0x6d,0x85,0xbe] +0x6b,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, m0 ; encoding: [0x7d,0x6d,0x85,0xbe] +0x7d,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, exec_lo ; encoding: [0x7e,0x6d,0x85,0xbe] +0x7e,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, exec_hi ; encoding: [0x7f,0x6d,0x85,0xbe] +0x7f,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, 0 ; encoding: [0x80,0x6d,0x85,0xbe] +0x80,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, -1 ; encoding: [0xc1,0x6d,0x85,0xbe] +0xc1,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, 0.5 ; encoding: [0xf0,0x6d,0x85,0xbe] +0xf0,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, -4.0 ; encoding: [0xf7,0x6d,0x85,0xbe] +0xf7,0x6d,0x85,0xbe + +# GFX12: s_trunc_f16 s5, 0xfe0b ; encoding: [0xff,0x6d,0x85,0xbe,0x0b,0xfe,0x00,0x00] +0xff,0x6d,0x85,0xbe,0x0b,0xfe,0x00,0x00 + +# GFX12: s_trunc_f16 s5, 0x3456 ; encoding: [0xff,0x6d,0x85,0xbe,0x56,0x34,0x00,0x00] +0xff,0x6d,0x85,0xbe,0x56,0x34,0x00,0x00 + +# GFX12: s_rndne_f16 s5, s1 ; encoding: [0x01,0x6e,0x85,0xbe] +0x01,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s105, s1 ; encoding: [0x01,0x6e,0xe9,0xbe] +0x01,0x6e,0xe9,0xbe + +# GFX12: s_rndne_f16 s5, s105 ; encoding: [0x69,0x6e,0x85,0xbe] +0x69,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, s101 ; encoding: [0x65,0x6e,0x85,0xbe] +0x65,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, vcc_lo ; encoding: [0x6a,0x6e,0x85,0xbe] +0x6a,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, vcc_hi ; encoding: [0x6b,0x6e,0x85,0xbe] +0x6b,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, m0 ; encoding: [0x7d,0x6e,0x85,0xbe] +0x7d,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, exec_lo ; encoding: [0x7e,0x6e,0x85,0xbe] +0x7e,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, exec_hi ; encoding: [0x7f,0x6e,0x85,0xbe] +0x7f,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, 0 ; encoding: [0x80,0x6e,0x85,0xbe] +0x80,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, -1 ; encoding: [0xc1,0x6e,0x85,0xbe] +0xc1,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, 0.5 ; encoding: [0xf0,0x6e,0x85,0xbe] +0xf0,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, -4.0 ; encoding: [0xf7,0x6e,0x85,0xbe] +0xf7,0x6e,0x85,0xbe + +# GFX12: s_rndne_f16 s5, 0xfe0b ; encoding: [0xff,0x6e,0x85,0xbe,0x0b,0xfe,0x00,0x00] +0xff,0x6e,0x85,0xbe,0x0b,0xfe,0x00,0x00 + +# GFX12: s_rndne_f16 s5, 0x3456 ; encoding: [0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00] +0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00 + +# GFX12: s_abs_i32 exec_hi, s1 ; encoding: [0x01,0x15,0xff,0xbe] +0x01,0x15,0xff,0xbe + +# GFX12: s_abs_i32 exec_lo, s1 ; encoding: [0x01,0x15,0xfe,0xbe] +0x01,0x15,0xfe,0xbe + +# GFX12: s_abs_i32 m0, s1 ; encoding: [0x01,0x15,0xfd,0xbe] +0x01,0x15,0xfd,0xbe + +# GFX12: s_abs_i32 s0, 0.5 ; encoding: [0xf0,0x15,0x80,0xbe] +0xf0,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, 0 ; encoding: [0x80,0x15,0x80,0xbe] +0x80,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, 0x3f717273 ; encoding: [0xff,0x15,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x15,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_abs_i32 s0, 0xaf123456 ; encoding: [0xff,0x15,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x15,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_abs_i32 s0, -1 ; encoding: [0xc1,0x15,0x80,0xbe] +0xc1,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, -4.0 ; encoding: [0xf7,0x15,0x80,0xbe] +0xf7,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, exec_hi ; encoding: [0x7f,0x15,0x80,0xbe] +0x7f,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, exec_lo ; encoding: [0x7e,0x15,0x80,0xbe] +0x7e,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, m0 ; encoding: [0x7d,0x15,0x80,0xbe] +0x7d,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, s104 ; encoding: [0x68,0x15,0x80,0xbe] +0x68,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, s1 ; encoding: [0x01,0x15,0x80,0xbe] +0x01,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, vcc_hi ; encoding: [0x6b,0x15,0x80,0xbe] +0x6b,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s0, vcc_lo ; encoding: [0x6a,0x15,0x80,0xbe] +0x6a,0x15,0x80,0xbe + +# GFX12: s_abs_i32 s105, s104 ; encoding: [0x68,0x15,0xe9,0xbe] +0x68,0x15,0xe9,0xbe + +# GFX12: s_abs_i32 s105, s1 ; encoding: [0x01,0x15,0xe9,0xbe] +0x01,0x15,0xe9,0xbe + +# GFX12: s_abs_i32 vcc_hi, s1 ; encoding: [0x01,0x15,0xeb,0xbe] +0x01,0x15,0xeb,0xbe + +# GFX12: s_abs_i32 vcc_lo, s1 ; encoding: [0x01,0x15,0xea,0xbe] +0x01,0x15,0xea,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x2c,0x80,0xbe] +0xf0,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, 0 ; encoding: [0x80,0x2c,0x80,0xbe] +0x80,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x2c,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x2c,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not0_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x2c,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x2c,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not0_saveexec_b32 s0, -1 ; encoding: [0xc1,0x2c,0x80,0xbe] +0xc1,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x2c,0x80,0xbe] +0xf7,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x2c,0x80,0xbe] +0x7f,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x2c,0x80,0xbe] +0x7e,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, m0 ; encoding: [0x7d,0x2c,0x80,0xbe] +0x7d,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, s104 ; encoding: [0x68,0x2c,0x80,0xbe] +0x68,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, s1 ; encoding: [0x01,0x2c,0x80,0xbe] +0x01,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x2c,0x80,0xbe] +0x6b,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x2c,0x80,0xbe] +0x6a,0x2c,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b32 s105, s104 ; encoding: [0x68,0x2c,0xe9,0xbe] +0x68,0x2c,0xe9,0xbe + +# GFX12: s_and_not0_saveexec_b32 s105, s1 ; encoding: [0x01,0x2c,0xe9,0xbe] +0x01,0x2c,0xe9,0xbe + +# GFX12: s_and_not0_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x2c,0xeb,0xbe] +0x01,0x2c,0xeb,0xbe + +# GFX12: s_and_not0_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x2c,0xea,0xbe] +0x01,0x2c,0xea,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x2d,0x80,0xbe] +0xf0,0x2d,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x2d,0x80,0xbe] +0x80,0x2d,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x2d,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x2d,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not0_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x2d,0x80,0xbe] +0xc1,0x2d,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x2d,0x80,0xbe] +0xf7,0x2d,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x2d,0x80,0xbe] +0x7e,0x2d,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x2d,0x80,0xbe] +0x66,0x2d,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x2d,0x80,0xbe] +0x02,0x2d,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x2d,0x80,0xbe] +0x6a,0x2d,0x80,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x2d,0xe8,0xbe] +0x66,0x2d,0xe8,0xbe + +# GFX12: s_and_not0_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x2d,0xe8,0xbe] +0x02,0x2d,0xe8,0xbe + +# GFX12: s_and_not0_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x2d,0xea,0xbe] +0x02,0x2d,0xea,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, 0.5 ; encoding: [0xf0,0x34,0x80,0xbe] +0xf0,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, 0 ; encoding: [0x80,0x34,0x80,0xbe] +0x80,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x34,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x34,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not0_wrexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x34,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x34,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not0_wrexec_b32 s0, -1 ; encoding: [0xc1,0x34,0x80,0xbe] +0xc1,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, -4.0 ; encoding: [0xf7,0x34,0x80,0xbe] +0xf7,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, exec_hi ; encoding: [0x7f,0x34,0x80,0xbe] +0x7f,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, exec_lo ; encoding: [0x7e,0x34,0x80,0xbe] +0x7e,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, m0 ; encoding: [0x7d,0x34,0x80,0xbe] +0x7d,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, s104 ; encoding: [0x68,0x34,0x80,0xbe] +0x68,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, s1 ; encoding: [0x01,0x34,0x80,0xbe] +0x01,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, vcc_hi ; encoding: [0x6b,0x34,0x80,0xbe] +0x6b,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s0, vcc_lo ; encoding: [0x6a,0x34,0x80,0xbe] +0x6a,0x34,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b32 s105, s104 ; encoding: [0x68,0x34,0xe9,0xbe] +0x68,0x34,0xe9,0xbe + +# GFX12: s_and_not0_wrexec_b32 s105, s1 ; encoding: [0x01,0x34,0xe9,0xbe] +0x01,0x34,0xe9,0xbe + +# GFX12: s_and_not0_wrexec_b32 vcc_hi, s1 ; encoding: [0x01,0x34,0xeb,0xbe] +0x01,0x34,0xeb,0xbe + +# GFX12: s_and_not0_wrexec_b32 vcc_lo, s1 ; encoding: [0x01,0x34,0xea,0xbe] +0x01,0x34,0xea,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x35,0x80,0xbe] +0xf0,0x35,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[0:1], 0 ; encoding: [0x80,0x35,0x80,0xbe] +0x80,0x35,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x35,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x35,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not0_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not0_wrexec_b64 s[0:1], -1 ; encoding: [0xc1,0x35,0x80,0xbe] +0xc1,0x35,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x35,0x80,0xbe] +0xf7,0x35,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[0:1], exec ; encoding: [0x7e,0x35,0x80,0xbe] +0x7e,0x35,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x35,0x80,0xbe] +0x66,0x35,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x35,0x80,0xbe] +0x02,0x35,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[0:1], vcc ; encoding: [0x6a,0x35,0x80,0xbe] +0x6a,0x35,0x80,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x35,0xe8,0xbe] +0x66,0x35,0xe8,0xbe + +# GFX12: s_and_not0_wrexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x35,0xe8,0xbe] +0x02,0x35,0xe8,0xbe + +# GFX12: s_and_not0_wrexec_b64 vcc, s[2:3] ; encoding: [0x02,0x35,0xea,0xbe] +0x02,0x35,0xea,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x30,0x80,0xbe] +0xf0,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, 0 ; encoding: [0x80,0x30,0x80,0xbe] +0x80,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x30,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x30,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not1_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x30,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x30,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not1_saveexec_b32 s0, -1 ; encoding: [0xc1,0x30,0x80,0xbe] +0xc1,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x30,0x80,0xbe] +0xf7,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x30,0x80,0xbe] +0x7f,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x30,0x80,0xbe] +0x7e,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, m0 ; encoding: [0x7d,0x30,0x80,0xbe] +0x7d,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, s104 ; encoding: [0x68,0x30,0x80,0xbe] +0x68,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, s1 ; encoding: [0x01,0x30,0x80,0xbe] +0x01,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x30,0x80,0xbe] +0x6b,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x30,0x80,0xbe] +0x6a,0x30,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b32 s105, s104 ; encoding: [0x68,0x30,0xe9,0xbe] +0x68,0x30,0xe9,0xbe + +# GFX12: s_and_not1_saveexec_b32 s105, s1 ; encoding: [0x01,0x30,0xe9,0xbe] +0x01,0x30,0xe9,0xbe + +# GFX12: s_and_not1_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x30,0xeb,0xbe] +0x01,0x30,0xeb,0xbe + +# GFX12: s_and_not1_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x30,0xea,0xbe] +0x01,0x30,0xea,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x31,0x80,0xbe] +0xf0,0x31,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x31,0x80,0xbe] +0x80,0x31,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x31,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x31,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not1_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x31,0x80,0xbe] +0xc1,0x31,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x31,0x80,0xbe] +0xf7,0x31,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x31,0x80,0xbe] +0x7e,0x31,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x31,0x80,0xbe] +0x66,0x31,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x31,0x80,0xbe] +0x02,0x31,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x31,0x80,0xbe] +0x6a,0x31,0x80,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x31,0xe8,0xbe] +0x66,0x31,0xe8,0xbe + +# GFX12: s_and_not1_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x31,0xe8,0xbe] +0x02,0x31,0xe8,0xbe + +# GFX12: s_and_not1_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x31,0xea,0xbe] +0x02,0x31,0xea,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, 0.5 ; encoding: [0xf0,0x36,0x80,0xbe] +0xf0,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, 0 ; encoding: [0x80,0x36,0x80,0xbe] +0x80,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x36,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x36,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not1_wrexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x36,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x36,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not1_wrexec_b32 s0, -1 ; encoding: [0xc1,0x36,0x80,0xbe] +0xc1,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, -4.0 ; encoding: [0xf7,0x36,0x80,0xbe] +0xf7,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, exec_hi ; encoding: [0x7f,0x36,0x80,0xbe] +0x7f,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, exec_lo ; encoding: [0x7e,0x36,0x80,0xbe] +0x7e,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, m0 ; encoding: [0x7d,0x36,0x80,0xbe] +0x7d,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, s104 ; encoding: [0x68,0x36,0x80,0xbe] +0x68,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, s1 ; encoding: [0x01,0x36,0x80,0xbe] +0x01,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, vcc_hi ; encoding: [0x6b,0x36,0x80,0xbe] +0x6b,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s0, vcc_lo ; encoding: [0x6a,0x36,0x80,0xbe] +0x6a,0x36,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b32 s105, s104 ; encoding: [0x68,0x36,0xe9,0xbe] +0x68,0x36,0xe9,0xbe + +# GFX12: s_and_not1_wrexec_b32 s105, s1 ; encoding: [0x01,0x36,0xe9,0xbe] +0x01,0x36,0xe9,0xbe + +# GFX12: s_and_not1_wrexec_b32 vcc_hi, s1 ; encoding: [0x01,0x36,0xeb,0xbe] +0x01,0x36,0xeb,0xbe + +# GFX12: s_and_not1_wrexec_b32 vcc_lo, s1 ; encoding: [0x01,0x36,0xea,0xbe] +0x01,0x36,0xea,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x37,0x80,0xbe] +0xf0,0x37,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[0:1], 0 ; encoding: [0x80,0x37,0x80,0xbe] +0x80,0x37,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x37,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x37,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not1_wrexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not1_wrexec_b64 s[0:1], -1 ; encoding: [0xc1,0x37,0x80,0xbe] +0xc1,0x37,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x37,0x80,0xbe] +0xf7,0x37,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[0:1], exec ; encoding: [0x7e,0x37,0x80,0xbe] +0x7e,0x37,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x37,0x80,0xbe] +0x66,0x37,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x37,0x80,0xbe] +0x02,0x37,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[0:1], vcc ; encoding: [0x6a,0x37,0x80,0xbe] +0x6a,0x37,0x80,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x37,0xe8,0xbe] +0x66,0x37,0xe8,0xbe + +# GFX12: s_and_not1_wrexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x37,0xe8,0xbe] +0x02,0x37,0xe8,0xbe + +# GFX12: s_and_not1_wrexec_b64 vcc, s[2:3] ; encoding: [0x02,0x37,0xea,0xbe] +0x02,0x37,0xea,0xbe + +# GFX12: s_and_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x20,0x80,0xbe] +0xf0,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, 0 ; encoding: [0x80,0x20,0x80,0xbe] +0x80,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x20,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x20,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x20,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x20,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_saveexec_b32 s0, -1 ; encoding: [0xc1,0x20,0x80,0xbe] +0xc1,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x20,0x80,0xbe] +0xf7,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x20,0x80,0xbe] +0x7f,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x20,0x80,0xbe] +0x7e,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, m0 ; encoding: [0x7d,0x20,0x80,0xbe] +0x7d,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, s104 ; encoding: [0x68,0x20,0x80,0xbe] +0x68,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, s1 ; encoding: [0x01,0x20,0x80,0xbe] +0x01,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x20,0x80,0xbe] +0x6b,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x20,0x80,0xbe] +0x6a,0x20,0x80,0xbe + +# GFX12: s_and_saveexec_b32 s105, s104 ; encoding: [0x68,0x20,0xe9,0xbe] +0x68,0x20,0xe9,0xbe + +# GFX12: s_and_saveexec_b32 s105, s1 ; encoding: [0x01,0x20,0xe9,0xbe] +0x01,0x20,0xe9,0xbe + +# GFX12: s_and_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x20,0xeb,0xbe] +0x01,0x20,0xeb,0xbe + +# GFX12: s_and_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x20,0xea,0xbe] +0x01,0x20,0xea,0xbe + +# GFX12: s_and_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x21,0x80,0xbe] +0xf0,0x21,0x80,0xbe + +# GFX12: s_and_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x21,0x80,0xbe] +0x80,0x21,0x80,0xbe + +# GFX12: s_and_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x21,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x21,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_and_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x21,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_and_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x21,0x80,0xbe] +0xc1,0x21,0x80,0xbe + +# GFX12: s_and_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x21,0x80,0xbe] +0xf7,0x21,0x80,0xbe + +# GFX12: s_and_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x21,0x80,0xbe] +0x7e,0x21,0x80,0xbe + +# GFX12: s_and_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x21,0x80,0xbe] +0x66,0x21,0x80,0xbe + +# GFX12: s_and_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x21,0x80,0xbe] +0x02,0x21,0x80,0xbe + +# GFX12: s_and_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x21,0x80,0xbe] +0x6a,0x21,0x80,0xbe + +# GFX12: s_and_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x21,0xe8,0xbe] +0x66,0x21,0xe8,0xbe + +# GFX12: s_and_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x21,0xe8,0xbe] +0x02,0x21,0xe8,0xbe + +# GFX12: s_and_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x21,0xea,0xbe] +0x02,0x21,0xea,0xbe + +# GFX12: s_bcnt0_i32_b32 exec_hi, s1 ; encoding: [0x01,0x16,0xff,0xbe] +0x01,0x16,0xff,0xbe + +# GFX12: s_bcnt0_i32_b32 exec_lo, s1 ; encoding: [0x01,0x16,0xfe,0xbe] +0x01,0x16,0xfe,0xbe + +# GFX12: s_bcnt0_i32_b32 m0, s1 ; encoding: [0x01,0x16,0xfd,0xbe] +0x01,0x16,0xfd,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, 0.5 ; encoding: [0xf0,0x16,0x80,0xbe] +0xf0,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, 0 ; encoding: [0x80,0x16,0x80,0xbe] +0x80,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, 0x3f717273 ; encoding: [0xff,0x16,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x16,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_bcnt0_i32_b32 s0, 0xaf123456 ; encoding: [0xff,0x16,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x16,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_bcnt0_i32_b32 s0, -1 ; encoding: [0xc1,0x16,0x80,0xbe] +0xc1,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, -4.0 ; encoding: [0xf7,0x16,0x80,0xbe] +0xf7,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, exec_hi ; encoding: [0x7f,0x16,0x80,0xbe] +0x7f,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, exec_lo ; encoding: [0x7e,0x16,0x80,0xbe] +0x7e,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, m0 ; encoding: [0x7d,0x16,0x80,0xbe] +0x7d,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, s104 ; encoding: [0x68,0x16,0x80,0xbe] +0x68,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, s1 ; encoding: [0x01,0x16,0x80,0xbe] +0x01,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, vcc_hi ; encoding: [0x6b,0x16,0x80,0xbe] +0x6b,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s0, vcc_lo ; encoding: [0x6a,0x16,0x80,0xbe] +0x6a,0x16,0x80,0xbe + +# GFX12: s_bcnt0_i32_b32 s105, s104 ; encoding: [0x68,0x16,0xe9,0xbe] +0x68,0x16,0xe9,0xbe + +# GFX12: s_bcnt0_i32_b32 s105, s1 ; encoding: [0x01,0x16,0xe9,0xbe] +0x01,0x16,0xe9,0xbe + +# GFX12: s_bcnt0_i32_b32 vcc_hi, s1 ; encoding: [0x01,0x16,0xeb,0xbe] +0x01,0x16,0xeb,0xbe + +# GFX12: s_bcnt0_i32_b32 vcc_lo, s1 ; encoding: [0x01,0x16,0xea,0xbe] +0x01,0x16,0xea,0xbe + +# GFX12: s_bcnt0_i32_b64 exec_hi, s[2:3] ; encoding: [0x02,0x17,0xff,0xbe] +0x02,0x17,0xff,0xbe + +# GFX12: s_bcnt0_i32_b64 exec_lo, s[2:3] ; encoding: [0x02,0x17,0xfe,0xbe] +0x02,0x17,0xfe,0xbe + +# GFX12: s_bcnt0_i32_b64 m0, s[2:3] ; encoding: [0x02,0x17,0xfd,0xbe] +0x02,0x17,0xfd,0xbe + +# GFX12: s_bcnt0_i32_b64 s0, 0.5 ; encoding: [0xf0,0x17,0x80,0xbe] +0xf0,0x17,0x80,0xbe + +# GFX12: s_bcnt0_i32_b64 s0, 0 ; encoding: [0x80,0x17,0x80,0xbe] +0x80,0x17,0x80,0xbe + +# GFX12: s_bcnt0_i32_b64 s0, 0x3f717273 ; encoding: [0xff,0x17,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x17,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_bcnt0_i32_b64 s0, 0xaf123456 ; encoding: [0xff,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_bcnt0_i32_b64 s0, -1 ; encoding: [0xc1,0x17,0x80,0xbe] +0xc1,0x17,0x80,0xbe + +# GFX12: s_bcnt0_i32_b64 s0, -4.0 ; encoding: [0xf7,0x17,0x80,0xbe] +0xf7,0x17,0x80,0xbe + +# GFX12: s_bcnt0_i32_b64 s0, exec ; encoding: [0x7e,0x17,0x80,0xbe] +0x7e,0x17,0x80,0xbe + +# GFX12: s_bcnt0_i32_b64 s0, s[102:103] ; encoding: [0x66,0x17,0x80,0xbe] +0x66,0x17,0x80,0xbe + +# GFX12: s_bcnt0_i32_b64 s0, s[2:3] ; encoding: [0x02,0x17,0x80,0xbe] +0x02,0x17,0x80,0xbe + +# GFX12: s_bcnt0_i32_b64 s0, vcc ; encoding: [0x6a,0x17,0x80,0xbe] +0x6a,0x17,0x80,0xbe + +# GFX12: s_bcnt0_i32_b64 s105, s[102:103] ; encoding: [0x66,0x17,0xe9,0xbe] +0x66,0x17,0xe9,0xbe + +# GFX12: s_bcnt0_i32_b64 s105, s[2:3] ; encoding: [0x02,0x17,0xe9,0xbe] +0x02,0x17,0xe9,0xbe + +# GFX12: s_bcnt0_i32_b64 vcc_hi, s[2:3] ; encoding: [0x02,0x17,0xeb,0xbe] +0x02,0x17,0xeb,0xbe + +# GFX12: s_bcnt0_i32_b64 vcc_lo, s[2:3] ; encoding: [0x02,0x17,0xea,0xbe] +0x02,0x17,0xea,0xbe + +# GFX12: s_bcnt1_i32_b32 exec_hi, s1 ; encoding: [0x01,0x18,0xff,0xbe] +0x01,0x18,0xff,0xbe + +# GFX12: s_bcnt1_i32_b32 exec_lo, s1 ; encoding: [0x01,0x18,0xfe,0xbe] +0x01,0x18,0xfe,0xbe + +# GFX12: s_bcnt1_i32_b32 m0, s1 ; encoding: [0x01,0x18,0xfd,0xbe] +0x01,0x18,0xfd,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, 0.5 ; encoding: [0xf0,0x18,0x80,0xbe] +0xf0,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, 0 ; encoding: [0x80,0x18,0x80,0xbe] +0x80,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, 0x3f717273 ; encoding: [0xff,0x18,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x18,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_bcnt1_i32_b32 s0, 0xaf123456 ; encoding: [0xff,0x18,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x18,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_bcnt1_i32_b32 s0, -1 ; encoding: [0xc1,0x18,0x80,0xbe] +0xc1,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, -4.0 ; encoding: [0xf7,0x18,0x80,0xbe] +0xf7,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, exec_hi ; encoding: [0x7f,0x18,0x80,0xbe] +0x7f,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, exec_lo ; encoding: [0x7e,0x18,0x80,0xbe] +0x7e,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, m0 ; encoding: [0x7d,0x18,0x80,0xbe] +0x7d,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, s104 ; encoding: [0x68,0x18,0x80,0xbe] +0x68,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, s1 ; encoding: [0x01,0x18,0x80,0xbe] +0x01,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, vcc_hi ; encoding: [0x6b,0x18,0x80,0xbe] +0x6b,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s0, vcc_lo ; encoding: [0x6a,0x18,0x80,0xbe] +0x6a,0x18,0x80,0xbe + +# GFX12: s_bcnt1_i32_b32 s105, s104 ; encoding: [0x68,0x18,0xe9,0xbe] +0x68,0x18,0xe9,0xbe + +# GFX12: s_bcnt1_i32_b32 s105, s1 ; encoding: [0x01,0x18,0xe9,0xbe] +0x01,0x18,0xe9,0xbe + +# GFX12: s_bcnt1_i32_b32 vcc_hi, s1 ; encoding: [0x01,0x18,0xeb,0xbe] +0x01,0x18,0xeb,0xbe + +# GFX12: s_bcnt1_i32_b32 vcc_lo, s1 ; encoding: [0x01,0x18,0xea,0xbe] +0x01,0x18,0xea,0xbe + +# GFX12: s_bcnt1_i32_b64 exec_hi, s[2:3] ; encoding: [0x02,0x19,0xff,0xbe] +0x02,0x19,0xff,0xbe + +# GFX12: s_bcnt1_i32_b64 exec_lo, s[2:3] ; encoding: [0x02,0x19,0xfe,0xbe] +0x02,0x19,0xfe,0xbe + +# GFX12: s_bcnt1_i32_b64 m0, s[2:3] ; encoding: [0x02,0x19,0xfd,0xbe] +0x02,0x19,0xfd,0xbe + +# GFX12: s_bcnt1_i32_b64 s0, 0.5 ; encoding: [0xf0,0x19,0x80,0xbe] +0xf0,0x19,0x80,0xbe + +# GFX12: s_bcnt1_i32_b64 s0, 0 ; encoding: [0x80,0x19,0x80,0xbe] +0x80,0x19,0x80,0xbe + +# GFX12: s_bcnt1_i32_b64 s0, 0x3f717273 ; encoding: [0xff,0x19,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x19,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_bcnt1_i32_b64 s0, 0xaf123456 ; encoding: [0xff,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_bcnt1_i32_b64 s0, -1 ; encoding: [0xc1,0x19,0x80,0xbe] +0xc1,0x19,0x80,0xbe + +# GFX12: s_bcnt1_i32_b64 s0, -4.0 ; encoding: [0xf7,0x19,0x80,0xbe] +0xf7,0x19,0x80,0xbe + +# GFX12: s_bcnt1_i32_b64 s0, exec ; encoding: [0x7e,0x19,0x80,0xbe] +0x7e,0x19,0x80,0xbe + +# GFX12: s_bcnt1_i32_b64 s0, s[102:103] ; encoding: [0x66,0x19,0x80,0xbe] +0x66,0x19,0x80,0xbe + +# GFX12: s_bcnt1_i32_b64 s0, s[2:3] ; encoding: [0x02,0x19,0x80,0xbe] +0x02,0x19,0x80,0xbe + +# GFX12: s_bcnt1_i32_b64 s0, vcc ; encoding: [0x6a,0x19,0x80,0xbe] +0x6a,0x19,0x80,0xbe + +# GFX12: s_bcnt1_i32_b64 s105, s[102:103] ; encoding: [0x66,0x19,0xe9,0xbe] +0x66,0x19,0xe9,0xbe + +# GFX12: s_bcnt1_i32_b64 s105, s[2:3] ; encoding: [0x02,0x19,0xe9,0xbe] +0x02,0x19,0xe9,0xbe + +# GFX12: s_bcnt1_i32_b64 vcc_hi, s[2:3] ; encoding: [0x02,0x19,0xeb,0xbe] +0x02,0x19,0xeb,0xbe + +# GFX12: s_bcnt1_i32_b64 vcc_lo, s[2:3] ; encoding: [0x02,0x19,0xea,0xbe] +0x02,0x19,0xea,0xbe + +# GFX12: s_bitreplicate_b64_b32 exec, s2 ; encoding: [0x02,0x14,0xfe,0xbe] +0x02,0x14,0xfe,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], 0.5 ; encoding: [0xf0,0x14,0x80,0xbe] +0xf0,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], 0 ; encoding: [0x80,0x14,0x80,0xbe] +0x80,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], 0x3f717273 ; encoding: [0xff,0x14,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x14,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_bitreplicate_b64_b32 s[0:1], 0xaf123456 ; encoding: [0xff,0x14,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x14,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_bitreplicate_b64_b32 s[0:1], -1 ; encoding: [0xc1,0x14,0x80,0xbe] +0xc1,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], -4.0 ; encoding: [0xf7,0x14,0x80,0xbe] +0xf7,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], exec_hi ; encoding: [0x7f,0x14,0x80,0xbe] +0x7f,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], exec_lo ; encoding: [0x7e,0x14,0x80,0xbe] +0x7e,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], m0 ; encoding: [0x7d,0x14,0x80,0xbe] +0x7d,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], s102 ; encoding: [0x66,0x14,0x80,0xbe] +0x66,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], s2 ; encoding: [0x02,0x14,0x80,0xbe] +0x02,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], vcc_hi ; encoding: [0x6b,0x14,0x80,0xbe] +0x6b,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[0:1], vcc_lo ; encoding: [0x6a,0x14,0x80,0xbe] +0x6a,0x14,0x80,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[104:105], s102 ; encoding: [0x66,0x14,0xe8,0xbe] +0x66,0x14,0xe8,0xbe + +# GFX12: s_bitreplicate_b64_b32 s[104:105], s2 ; encoding: [0x02,0x14,0xe8,0xbe] +0x02,0x14,0xe8,0xbe + +# GFX12: s_bitreplicate_b64_b32 vcc, s2 ; encoding: [0x02,0x14,0xea,0xbe] +0x02,0x14,0xea,0xbe + +# GFX12: s_bitset0_b32 exec_hi, s1 ; encoding: [0x01,0x10,0xff,0xbe] +0x01,0x10,0xff,0xbe + +# GFX12: s_bitset0_b32 exec_lo, s1 ; encoding: [0x01,0x10,0xfe,0xbe] +0x01,0x10,0xfe,0xbe + +# GFX12: s_bitset0_b32 m0, s1 ; encoding: [0x01,0x10,0xfd,0xbe] +0x01,0x10,0xfd,0xbe + +# GFX12: s_bitset0_b32 s0, 0.5 ; encoding: [0xf0,0x10,0x80,0xbe] +0xf0,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, 0 ; encoding: [0x80,0x10,0x80,0xbe] +0x80,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, 0x3f717273 ; encoding: [0xff,0x10,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x10,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_bitset0_b32 s0, 0xaf123456 ; encoding: [0xff,0x10,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x10,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_bitset0_b32 s0, -1 ; encoding: [0xc1,0x10,0x80,0xbe] +0xc1,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, -4.0 ; encoding: [0xf7,0x10,0x80,0xbe] +0xf7,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, exec_hi ; encoding: [0x7f,0x10,0x80,0xbe] +0x7f,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, exec_lo ; encoding: [0x7e,0x10,0x80,0xbe] +0x7e,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, m0 ; encoding: [0x7d,0x10,0x80,0xbe] +0x7d,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, s104 ; encoding: [0x68,0x10,0x80,0xbe] +0x68,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, s1 ; encoding: [0x01,0x10,0x80,0xbe] +0x01,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, vcc_hi ; encoding: [0x6b,0x10,0x80,0xbe] +0x6b,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s0, vcc_lo ; encoding: [0x6a,0x10,0x80,0xbe] +0x6a,0x10,0x80,0xbe + +# GFX12: s_bitset0_b32 s105, s104 ; encoding: [0x68,0x10,0xe9,0xbe] +0x68,0x10,0xe9,0xbe + +# GFX12: s_bitset0_b32 s105, s1 ; encoding: [0x01,0x10,0xe9,0xbe] +0x01,0x10,0xe9,0xbe + +# GFX12: s_bitset0_b32 vcc_hi, s1 ; encoding: [0x01,0x10,0xeb,0xbe] +0x01,0x10,0xeb,0xbe + +# GFX12: s_bitset0_b32 vcc_lo, s1 ; encoding: [0x01,0x10,0xea,0xbe] +0x01,0x10,0xea,0xbe + +# GFX12: s_bitset0_b64 exec, s2 ; encoding: [0x02,0x11,0xfe,0xbe] +0x02,0x11,0xfe,0xbe + +# GFX12: s_bitset0_b64 s[0:1], 0.5 ; encoding: [0xf0,0x11,0x80,0xbe] +0xf0,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], 0 ; encoding: [0x80,0x11,0x80,0xbe] +0x80,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x11,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x11,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_bitset0_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x11,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x11,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_bitset0_b64 s[0:1], -1 ; encoding: [0xc1,0x11,0x80,0xbe] +0xc1,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], -4.0 ; encoding: [0xf7,0x11,0x80,0xbe] +0xf7,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], exec_hi ; encoding: [0x7f,0x11,0x80,0xbe] +0x7f,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], exec_lo ; encoding: [0x7e,0x11,0x80,0xbe] +0x7e,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], m0 ; encoding: [0x7d,0x11,0x80,0xbe] +0x7d,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], s102 ; encoding: [0x66,0x11,0x80,0xbe] +0x66,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], s2 ; encoding: [0x02,0x11,0x80,0xbe] +0x02,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], vcc_hi ; encoding: [0x6b,0x11,0x80,0xbe] +0x6b,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[0:1], vcc_lo ; encoding: [0x6a,0x11,0x80,0xbe] +0x6a,0x11,0x80,0xbe + +# GFX12: s_bitset0_b64 s[104:105], s102 ; encoding: [0x66,0x11,0xe8,0xbe] +0x66,0x11,0xe8,0xbe + +# GFX12: s_bitset0_b64 s[104:105], s2 ; encoding: [0x02,0x11,0xe8,0xbe] +0x02,0x11,0xe8,0xbe + +# GFX12: s_bitset0_b64 vcc, s2 ; encoding: [0x02,0x11,0xea,0xbe] +0x02,0x11,0xea,0xbe + +# GFX12: s_bitset1_b32 exec_hi, s1 ; encoding: [0x01,0x12,0xff,0xbe] +0x01,0x12,0xff,0xbe + +# GFX12: s_bitset1_b32 exec_lo, s1 ; encoding: [0x01,0x12,0xfe,0xbe] +0x01,0x12,0xfe,0xbe + +# GFX12: s_bitset1_b32 m0, s1 ; encoding: [0x01,0x12,0xfd,0xbe] +0x01,0x12,0xfd,0xbe + +# GFX12: s_bitset1_b32 s0, 0.5 ; encoding: [0xf0,0x12,0x80,0xbe] +0xf0,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, 0 ; encoding: [0x80,0x12,0x80,0xbe] +0x80,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, 0x3f717273 ; encoding: [0xff,0x12,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x12,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_bitset1_b32 s0, 0xaf123456 ; encoding: [0xff,0x12,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x12,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_bitset1_b32 s0, -1 ; encoding: [0xc1,0x12,0x80,0xbe] +0xc1,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, -4.0 ; encoding: [0xf7,0x12,0x80,0xbe] +0xf7,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, exec_hi ; encoding: [0x7f,0x12,0x80,0xbe] +0x7f,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, exec_lo ; encoding: [0x7e,0x12,0x80,0xbe] +0x7e,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, m0 ; encoding: [0x7d,0x12,0x80,0xbe] +0x7d,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, s104 ; encoding: [0x68,0x12,0x80,0xbe] +0x68,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, s1 ; encoding: [0x01,0x12,0x80,0xbe] +0x01,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, vcc_hi ; encoding: [0x6b,0x12,0x80,0xbe] +0x6b,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s0, vcc_lo ; encoding: [0x6a,0x12,0x80,0xbe] +0x6a,0x12,0x80,0xbe + +# GFX12: s_bitset1_b32 s105, s104 ; encoding: [0x68,0x12,0xe9,0xbe] +0x68,0x12,0xe9,0xbe + +# GFX12: s_bitset1_b32 s105, s1 ; encoding: [0x01,0x12,0xe9,0xbe] +0x01,0x12,0xe9,0xbe + +# GFX12: s_bitset1_b32 vcc_hi, s1 ; encoding: [0x01,0x12,0xeb,0xbe] +0x01,0x12,0xeb,0xbe + +# GFX12: s_bitset1_b32 vcc_lo, s1 ; encoding: [0x01,0x12,0xea,0xbe] +0x01,0x12,0xea,0xbe + +# GFX12: s_bitset1_b64 exec, s2 ; encoding: [0x02,0x13,0xfe,0xbe] +0x02,0x13,0xfe,0xbe + +# GFX12: s_bitset1_b64 s[0:1], 0.5 ; encoding: [0xf0,0x13,0x80,0xbe] +0xf0,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], 0 ; encoding: [0x80,0x13,0x80,0xbe] +0x80,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x13,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x13,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_bitset1_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x13,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x13,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_bitset1_b64 s[0:1], -1 ; encoding: [0xc1,0x13,0x80,0xbe] +0xc1,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], -4.0 ; encoding: [0xf7,0x13,0x80,0xbe] +0xf7,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], exec_hi ; encoding: [0x7f,0x13,0x80,0xbe] +0x7f,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], exec_lo ; encoding: [0x7e,0x13,0x80,0xbe] +0x7e,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], m0 ; encoding: [0x7d,0x13,0x80,0xbe] +0x7d,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], s102 ; encoding: [0x66,0x13,0x80,0xbe] +0x66,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], s2 ; encoding: [0x02,0x13,0x80,0xbe] +0x02,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], vcc_hi ; encoding: [0x6b,0x13,0x80,0xbe] +0x6b,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[0:1], vcc_lo ; encoding: [0x6a,0x13,0x80,0xbe] +0x6a,0x13,0x80,0xbe + +# GFX12: s_bitset1_b64 s[104:105], s102 ; encoding: [0x66,0x13,0xe8,0xbe] +0x66,0x13,0xe8,0xbe + +# GFX12: s_bitset1_b64 s[104:105], s2 ; encoding: [0x02,0x13,0xe8,0xbe] +0x02,0x13,0xe8,0xbe + +# GFX12: s_bitset1_b64 vcc, s2 ; encoding: [0x02,0x13,0xea,0xbe] +0x02,0x13,0xea,0xbe + +# GFX12: s_brev_b32 exec_hi, s1 ; encoding: [0x01,0x04,0xff,0xbe] +0x01,0x04,0xff,0xbe + +# GFX12: s_brev_b32 exec_lo, s1 ; encoding: [0x01,0x04,0xfe,0xbe] +0x01,0x04,0xfe,0xbe + +# GFX12: s_brev_b32 m0, s1 ; encoding: [0x01,0x04,0xfd,0xbe] +0x01,0x04,0xfd,0xbe + +# GFX12: s_brev_b32 s0, 0.5 ; encoding: [0xf0,0x04,0x80,0xbe] +0xf0,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, 0 ; encoding: [0x80,0x04,0x80,0xbe] +0x80,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, 0x3f717273 ; encoding: [0xff,0x04,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_brev_b32 s0, 0xaf123456 ; encoding: [0xff,0x04,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_brev_b32 s0, -1 ; encoding: [0xc1,0x04,0x80,0xbe] +0xc1,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, -4.0 ; encoding: [0xf7,0x04,0x80,0xbe] +0xf7,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, exec_hi ; encoding: [0x7f,0x04,0x80,0xbe] +0x7f,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, exec_lo ; encoding: [0x7e,0x04,0x80,0xbe] +0x7e,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, m0 ; encoding: [0x7d,0x04,0x80,0xbe] +0x7d,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, s104 ; encoding: [0x68,0x04,0x80,0xbe] +0x68,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, s1 ; encoding: [0x01,0x04,0x80,0xbe] +0x01,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, vcc_hi ; encoding: [0x6b,0x04,0x80,0xbe] +0x6b,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s0, vcc_lo ; encoding: [0x6a,0x04,0x80,0xbe] +0x6a,0x04,0x80,0xbe + +# GFX12: s_brev_b32 s105, s104 ; encoding: [0x68,0x04,0xe9,0xbe] +0x68,0x04,0xe9,0xbe + +# GFX12: s_brev_b32 s105, s1 ; encoding: [0x01,0x04,0xe9,0xbe] +0x01,0x04,0xe9,0xbe + +# GFX12: s_brev_b32 vcc_hi, s1 ; encoding: [0x01,0x04,0xeb,0xbe] +0x01,0x04,0xeb,0xbe + +# GFX12: s_brev_b32 vcc_lo, s1 ; encoding: [0x01,0x04,0xea,0xbe] +0x01,0x04,0xea,0xbe + +# GFX12: s_brev_b64 exec, s[2:3] ; encoding: [0x02,0x05,0xfe,0xbe] +0x02,0x05,0xfe,0xbe + +# GFX12: s_brev_b64 s[0:1], 0.5 ; encoding: [0xf0,0x05,0x80,0xbe] +0xf0,0x05,0x80,0xbe + +# GFX12: s_brev_b64 s[0:1], 0 ; encoding: [0x80,0x05,0x80,0xbe] +0x80,0x05,0x80,0xbe + +# GFX12: s_brev_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x05,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x05,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_brev_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_brev_b64 s[0:1], -1 ; encoding: [0xc1,0x05,0x80,0xbe] +0xc1,0x05,0x80,0xbe + +# GFX12: s_brev_b64 s[0:1], -4.0 ; encoding: [0xf7,0x05,0x80,0xbe] +0xf7,0x05,0x80,0xbe + +# GFX12: s_brev_b64 s[0:1], exec ; encoding: [0x7e,0x05,0x80,0xbe] +0x7e,0x05,0x80,0xbe + +# GFX12: s_brev_b64 s[0:1], s[102:103] ; encoding: [0x66,0x05,0x80,0xbe] +0x66,0x05,0x80,0xbe + +# GFX12: s_brev_b64 s[0:1], s[2:3] ; encoding: [0x02,0x05,0x80,0xbe] +0x02,0x05,0x80,0xbe + +# GFX12: s_brev_b64 s[0:1], vcc ; encoding: [0x6a,0x05,0x80,0xbe] +0x6a,0x05,0x80,0xbe + +# GFX12: s_brev_b64 s[104:105], s[102:103] ; encoding: [0x66,0x05,0xe8,0xbe] +0x66,0x05,0xe8,0xbe + +# GFX12: s_brev_b64 s[104:105], s[2:3] ; encoding: [0x02,0x05,0xe8,0xbe] +0x02,0x05,0xe8,0xbe + +# GFX12: s_brev_b64 vcc, s[2:3] ; encoding: [0x02,0x05,0xea,0xbe] +0x02,0x05,0xea,0xbe + +# GFX12: s_cls_i32 exec_hi, s1 ; encoding: [0x01,0x0c,0xff,0xbe] +0x01,0x0c,0xff,0xbe + +# GFX12: s_cls_i32 exec_lo, s1 ; encoding: [0x01,0x0c,0xfe,0xbe] +0x01,0x0c,0xfe,0xbe + +# GFX12: s_cls_i32_i64 exec_hi, s[2:3] ; encoding: [0x02,0x0d,0xff,0xbe] +0x02,0x0d,0xff,0xbe + +# GFX12: s_cls_i32_i64 exec_lo, s[2:3] ; encoding: [0x02,0x0d,0xfe,0xbe] +0x02,0x0d,0xfe,0xbe + +# GFX12: s_cls_i32_i64 m0, s[2:3] ; encoding: [0x02,0x0d,0xfd,0xbe] +0x02,0x0d,0xfd,0xbe + +# GFX12: s_cls_i32_i64 s0, 0.5 ; encoding: [0xf0,0x0d,0x80,0xbe] +0xf0,0x0d,0x80,0xbe + +# GFX12: s_cls_i32_i64 s0, 0 ; encoding: [0x80,0x0d,0x80,0xbe] +0x80,0x0d,0x80,0xbe + +# GFX12: s_cls_i32_i64 s0, 0x3f717273 ; encoding: [0xff,0x0d,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x0d,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_cls_i32_i64 s0, 0xaf123456 ; encoding: [0xff,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_cls_i32_i64 s0, -1 ; encoding: [0xc1,0x0d,0x80,0xbe] +0xc1,0x0d,0x80,0xbe + +# GFX12: s_cls_i32_i64 s0, -4.0 ; encoding: [0xf7,0x0d,0x80,0xbe] +0xf7,0x0d,0x80,0xbe + +# GFX12: s_cls_i32_i64 s0, exec ; encoding: [0x7e,0x0d,0x80,0xbe] +0x7e,0x0d,0x80,0xbe + +# GFX12: s_cls_i32_i64 s0, s[102:103] ; encoding: [0x66,0x0d,0x80,0xbe] +0x66,0x0d,0x80,0xbe + +# GFX12: s_cls_i32_i64 s0, s[2:3] ; encoding: [0x02,0x0d,0x80,0xbe] +0x02,0x0d,0x80,0xbe + +# GFX12: s_cls_i32_i64 s0, vcc ; encoding: [0x6a,0x0d,0x80,0xbe] +0x6a,0x0d,0x80,0xbe + +# GFX12: s_cls_i32_i64 s105, s[102:103] ; encoding: [0x66,0x0d,0xe9,0xbe] +0x66,0x0d,0xe9,0xbe + +# GFX12: s_cls_i32_i64 s105, s[2:3] ; encoding: [0x02,0x0d,0xe9,0xbe] +0x02,0x0d,0xe9,0xbe + +# GFX12: s_cls_i32_i64 vcc_hi, s[2:3] ; encoding: [0x02,0x0d,0xeb,0xbe] +0x02,0x0d,0xeb,0xbe + +# GFX12: s_cls_i32_i64 vcc_lo, s[2:3] ; encoding: [0x02,0x0d,0xea,0xbe] +0x02,0x0d,0xea,0xbe + +# GFX12: s_cls_i32 m0, s1 ; encoding: [0x01,0x0c,0xfd,0xbe] +0x01,0x0c,0xfd,0xbe + +# GFX12: s_cls_i32 s0, 0.5 ; encoding: [0xf0,0x0c,0x80,0xbe] +0xf0,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, 0 ; encoding: [0x80,0x0c,0x80,0xbe] +0x80,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, 0x3f717273 ; encoding: [0xff,0x0c,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x0c,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_cls_i32 s0, 0xaf123456 ; encoding: [0xff,0x0c,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x0c,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_cls_i32 s0, -1 ; encoding: [0xc1,0x0c,0x80,0xbe] +0xc1,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, -4.0 ; encoding: [0xf7,0x0c,0x80,0xbe] +0xf7,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, exec_hi ; encoding: [0x7f,0x0c,0x80,0xbe] +0x7f,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, exec_lo ; encoding: [0x7e,0x0c,0x80,0xbe] +0x7e,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, m0 ; encoding: [0x7d,0x0c,0x80,0xbe] +0x7d,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, s104 ; encoding: [0x68,0x0c,0x80,0xbe] +0x68,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, s1 ; encoding: [0x01,0x0c,0x80,0xbe] +0x01,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, vcc_hi ; encoding: [0x6b,0x0c,0x80,0xbe] +0x6b,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s0, vcc_lo ; encoding: [0x6a,0x0c,0x80,0xbe] +0x6a,0x0c,0x80,0xbe + +# GFX12: s_cls_i32 s105, s104 ; encoding: [0x68,0x0c,0xe9,0xbe] +0x68,0x0c,0xe9,0xbe + +# GFX12: s_cls_i32 s105, s1 ; encoding: [0x01,0x0c,0xe9,0xbe] +0x01,0x0c,0xe9,0xbe + +# GFX12: s_cls_i32 vcc_hi, s1 ; encoding: [0x01,0x0c,0xeb,0xbe] +0x01,0x0c,0xeb,0xbe + +# GFX12: s_cls_i32 vcc_lo, s1 ; encoding: [0x01,0x0c,0xea,0xbe] +0x01,0x0c,0xea,0xbe + +# GFX12: s_clz_i32_u32 exec_hi, s1 ; encoding: [0x01,0x0a,0xff,0xbe] +0x01,0x0a,0xff,0xbe + +# GFX12: s_clz_i32_u32 exec_lo, s1 ; encoding: [0x01,0x0a,0xfe,0xbe] +0x01,0x0a,0xfe,0xbe + +# GFX12: s_clz_i32_u32 m0, s1 ; encoding: [0x01,0x0a,0xfd,0xbe] +0x01,0x0a,0xfd,0xbe + +# GFX12: s_clz_i32_u32 s0, 0.5 ; encoding: [0xf0,0x0a,0x80,0xbe] +0xf0,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, 0 ; encoding: [0x80,0x0a,0x80,0xbe] +0x80,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, 0x3f717273 ; encoding: [0xff,0x0a,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x0a,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_clz_i32_u32 s0, 0xaf123456 ; encoding: [0xff,0x0a,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x0a,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_clz_i32_u32 s0, -1 ; encoding: [0xc1,0x0a,0x80,0xbe] +0xc1,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, -4.0 ; encoding: [0xf7,0x0a,0x80,0xbe] +0xf7,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, exec_hi ; encoding: [0x7f,0x0a,0x80,0xbe] +0x7f,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, exec_lo ; encoding: [0x7e,0x0a,0x80,0xbe] +0x7e,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, m0 ; encoding: [0x7d,0x0a,0x80,0xbe] +0x7d,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, s104 ; encoding: [0x68,0x0a,0x80,0xbe] +0x68,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, s1 ; encoding: [0x01,0x0a,0x80,0xbe] +0x01,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, vcc_hi ; encoding: [0x6b,0x0a,0x80,0xbe] +0x6b,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s0, vcc_lo ; encoding: [0x6a,0x0a,0x80,0xbe] +0x6a,0x0a,0x80,0xbe + +# GFX12: s_clz_i32_u32 s105, s104 ; encoding: [0x68,0x0a,0xe9,0xbe] +0x68,0x0a,0xe9,0xbe + +# GFX12: s_clz_i32_u32 s105, s1 ; encoding: [0x01,0x0a,0xe9,0xbe] +0x01,0x0a,0xe9,0xbe + +# GFX12: s_clz_i32_u32 vcc_hi, s1 ; encoding: [0x01,0x0a,0xeb,0xbe] +0x01,0x0a,0xeb,0xbe + +# GFX12: s_clz_i32_u32 vcc_lo, s1 ; encoding: [0x01,0x0a,0xea,0xbe] +0x01,0x0a,0xea,0xbe + +# GFX12: s_clz_i32_u64 exec_hi, s[2:3] ; encoding: [0x02,0x0b,0xff,0xbe] +0x02,0x0b,0xff,0xbe + +# GFX12: s_clz_i32_u64 exec_lo, s[2:3] ; encoding: [0x02,0x0b,0xfe,0xbe] +0x02,0x0b,0xfe,0xbe + +# GFX12: s_clz_i32_u64 m0, s[2:3] ; encoding: [0x02,0x0b,0xfd,0xbe] +0x02,0x0b,0xfd,0xbe + +# GFX12: s_clz_i32_u64 s0, 0.5 ; encoding: [0xf0,0x0b,0x80,0xbe] +0xf0,0x0b,0x80,0xbe + +# GFX12: s_clz_i32_u64 s0, 0 ; encoding: [0x80,0x0b,0x80,0xbe] +0x80,0x0b,0x80,0xbe + +# GFX12: s_clz_i32_u64 s0, 0x3f717273 ; encoding: [0xff,0x0b,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x0b,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_clz_i32_u64 s0, 0xaf123456 ; encoding: [0xff,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_clz_i32_u64 s0, -1 ; encoding: [0xc1,0x0b,0x80,0xbe] +0xc1,0x0b,0x80,0xbe + +# GFX12: s_clz_i32_u64 s0, -4.0 ; encoding: [0xf7,0x0b,0x80,0xbe] +0xf7,0x0b,0x80,0xbe + +# GFX12: s_clz_i32_u64 s0, exec ; encoding: [0x7e,0x0b,0x80,0xbe] +0x7e,0x0b,0x80,0xbe + +# GFX12: s_clz_i32_u64 s0, s[102:103] ; encoding: [0x66,0x0b,0x80,0xbe] +0x66,0x0b,0x80,0xbe + +# GFX12: s_clz_i32_u64 s0, s[2:3] ; encoding: [0x02,0x0b,0x80,0xbe] +0x02,0x0b,0x80,0xbe + +# GFX12: s_clz_i32_u64 s0, vcc ; encoding: [0x6a,0x0b,0x80,0xbe] +0x6a,0x0b,0x80,0xbe + +# GFX12: s_clz_i32_u64 s105, s[102:103] ; encoding: [0x66,0x0b,0xe9,0xbe] +0x66,0x0b,0xe9,0xbe + +# GFX12: s_clz_i32_u64 s105, s[2:3] ; encoding: [0x02,0x0b,0xe9,0xbe] +0x02,0x0b,0xe9,0xbe + +# GFX12: s_clz_i32_u64 vcc_hi, s[2:3] ; encoding: [0x02,0x0b,0xeb,0xbe] +0x02,0x0b,0xeb,0xbe + +# GFX12: s_clz_i32_u64 vcc_lo, s[2:3] ; encoding: [0x02,0x0b,0xea,0xbe] +0x02,0x0b,0xea,0xbe + +# GFX12: s_cmov_b32 exec_hi, s1 ; encoding: [0x01,0x02,0xff,0xbe] +0x01,0x02,0xff,0xbe + +# GFX12: s_cmov_b32 exec_lo, s1 ; encoding: [0x01,0x02,0xfe,0xbe] +0x01,0x02,0xfe,0xbe + +# GFX12: s_cmov_b32 m0, s1 ; encoding: [0x01,0x02,0xfd,0xbe] +0x01,0x02,0xfd,0xbe + +# GFX12: s_cmov_b32 s0, 0.5 ; encoding: [0xf0,0x02,0x80,0xbe] +0xf0,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, 0 ; encoding: [0x80,0x02,0x80,0xbe] +0x80,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, 0x3f717273 ; encoding: [0xff,0x02,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_cmov_b32 s0, 0xaf123456 ; encoding: [0xff,0x02,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_cmov_b32 s0, -1 ; encoding: [0xc1,0x02,0x80,0xbe] +0xc1,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, -4.0 ; encoding: [0xf7,0x02,0x80,0xbe] +0xf7,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, exec_hi ; encoding: [0x7f,0x02,0x80,0xbe] +0x7f,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, exec_lo ; encoding: [0x7e,0x02,0x80,0xbe] +0x7e,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, m0 ; encoding: [0x7d,0x02,0x80,0xbe] +0x7d,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, s104 ; encoding: [0x68,0x02,0x80,0xbe] +0x68,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, s1 ; encoding: [0x01,0x02,0x80,0xbe] +0x01,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, vcc_hi ; encoding: [0x6b,0x02,0x80,0xbe] +0x6b,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s0, vcc_lo ; encoding: [0x6a,0x02,0x80,0xbe] +0x6a,0x02,0x80,0xbe + +# GFX12: s_cmov_b32 s105, s104 ; encoding: [0x68,0x02,0xe9,0xbe] +0x68,0x02,0xe9,0xbe + +# GFX12: s_cmov_b32 s105, s1 ; encoding: [0x01,0x02,0xe9,0xbe] +0x01,0x02,0xe9,0xbe + +# GFX12: s_cmov_b32 vcc_hi, s1 ; encoding: [0x01,0x02,0xeb,0xbe] +0x01,0x02,0xeb,0xbe + +# GFX12: s_cmov_b32 vcc_lo, s1 ; encoding: [0x01,0x02,0xea,0xbe] +0x01,0x02,0xea,0xbe + +# GFX12: s_cmov_b64 exec, s[2:3] ; encoding: [0x02,0x03,0xfe,0xbe] +0x02,0x03,0xfe,0xbe + +# GFX12: s_cmov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x03,0x80,0xbe] +0xf0,0x03,0x80,0xbe + +# GFX12: s_cmov_b64 s[0:1], 0 ; encoding: [0x80,0x03,0x80,0xbe] +0x80,0x03,0x80,0xbe + +# GFX12: s_cmov_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x03,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x03,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_cmov_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_cmov_b64 s[0:1], -1 ; encoding: [0xc1,0x03,0x80,0xbe] +0xc1,0x03,0x80,0xbe + +# GFX12: s_cmov_b64 s[0:1], -4.0 ; encoding: [0xf7,0x03,0x80,0xbe] +0xf7,0x03,0x80,0xbe + +# GFX12: s_cmov_b64 s[0:1], exec ; encoding: [0x7e,0x03,0x80,0xbe] +0x7e,0x03,0x80,0xbe + +# GFX12: s_cmov_b64 s[0:1], s[102:103] ; encoding: [0x66,0x03,0x80,0xbe] +0x66,0x03,0x80,0xbe + +# GFX12: s_cmov_b64 s[0:1], s[2:3] ; encoding: [0x02,0x03,0x80,0xbe] +0x02,0x03,0x80,0xbe + +# GFX12: s_cmov_b64 s[0:1], vcc ; encoding: [0x6a,0x03,0x80,0xbe] +0x6a,0x03,0x80,0xbe + +# GFX12: s_cmov_b64 s[104:105], s[102:103] ; encoding: [0x66,0x03,0xe8,0xbe] +0x66,0x03,0xe8,0xbe + +# GFX12: s_cmov_b64 s[104:105], s[2:3] ; encoding: [0x02,0x03,0xe8,0xbe] +0x02,0x03,0xe8,0xbe + +# GFX12: s_cmov_b64 vcc, s[2:3] ; encoding: [0x02,0x03,0xea,0xbe] +0x02,0x03,0xea,0xbe + +# GFX12: s_ctz_i32_b32 exec_hi, s1 ; encoding: [0x01,0x08,0xff,0xbe] +0x01,0x08,0xff,0xbe + +# GFX12: s_ctz_i32_b32 exec_lo, s1 ; encoding: [0x01,0x08,0xfe,0xbe] +0x01,0x08,0xfe,0xbe + +# GFX12: s_ctz_i32_b32 m0, s1 ; encoding: [0x01,0x08,0xfd,0xbe] +0x01,0x08,0xfd,0xbe + +# GFX12: s_ctz_i32_b32 s0, 0.5 ; encoding: [0xf0,0x08,0x80,0xbe] +0xf0,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, 0 ; encoding: [0x80,0x08,0x80,0xbe] +0x80,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, 0x3f717273 ; encoding: [0xff,0x08,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x08,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_ctz_i32_b32 s0, 0xaf123456 ; encoding: [0xff,0x08,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x08,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_ctz_i32_b32 s0, -1 ; encoding: [0xc1,0x08,0x80,0xbe] +0xc1,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, -4.0 ; encoding: [0xf7,0x08,0x80,0xbe] +0xf7,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, exec_hi ; encoding: [0x7f,0x08,0x80,0xbe] +0x7f,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, exec_lo ; encoding: [0x7e,0x08,0x80,0xbe] +0x7e,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, m0 ; encoding: [0x7d,0x08,0x80,0xbe] +0x7d,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, s104 ; encoding: [0x68,0x08,0x80,0xbe] +0x68,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, s1 ; encoding: [0x01,0x08,0x80,0xbe] +0x01,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, vcc_hi ; encoding: [0x6b,0x08,0x80,0xbe] +0x6b,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s0, vcc_lo ; encoding: [0x6a,0x08,0x80,0xbe] +0x6a,0x08,0x80,0xbe + +# GFX12: s_ctz_i32_b32 s105, s104 ; encoding: [0x68,0x08,0xe9,0xbe] +0x68,0x08,0xe9,0xbe + +# GFX12: s_ctz_i32_b32 s105, s1 ; encoding: [0x01,0x08,0xe9,0xbe] +0x01,0x08,0xe9,0xbe + +# GFX12: s_ctz_i32_b32 vcc_hi, s1 ; encoding: [0x01,0x08,0xeb,0xbe] +0x01,0x08,0xeb,0xbe + +# GFX12: s_ctz_i32_b32 vcc_lo, s1 ; encoding: [0x01,0x08,0xea,0xbe] +0x01,0x08,0xea,0xbe + +# GFX12: s_ctz_i32_b64 exec_hi, s[2:3] ; encoding: [0x02,0x09,0xff,0xbe] +0x02,0x09,0xff,0xbe + +# GFX12: s_ctz_i32_b64 exec_lo, s[2:3] ; encoding: [0x02,0x09,0xfe,0xbe] +0x02,0x09,0xfe,0xbe + +# GFX12: s_ctz_i32_b64 m0, s[2:3] ; encoding: [0x02,0x09,0xfd,0xbe] +0x02,0x09,0xfd,0xbe + +# GFX12: s_ctz_i32_b64 s0, 0.5 ; encoding: [0xf0,0x09,0x80,0xbe] +0xf0,0x09,0x80,0xbe + +# GFX12: s_ctz_i32_b64 s0, 0 ; encoding: [0x80,0x09,0x80,0xbe] +0x80,0x09,0x80,0xbe + +# GFX12: s_ctz_i32_b64 s0, 0x3f717273 ; encoding: [0xff,0x09,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x09,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_ctz_i32_b64 s0, 0xaf123456 ; encoding: [0xff,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_ctz_i32_b64 s0, -1 ; encoding: [0xc1,0x09,0x80,0xbe] +0xc1,0x09,0x80,0xbe + +# GFX12: s_ctz_i32_b64 s0, -4.0 ; encoding: [0xf7,0x09,0x80,0xbe] +0xf7,0x09,0x80,0xbe + +# GFX12: s_ctz_i32_b64 s0, exec ; encoding: [0x7e,0x09,0x80,0xbe] +0x7e,0x09,0x80,0xbe + +# GFX12: s_ctz_i32_b64 s0, s[102:103] ; encoding: [0x66,0x09,0x80,0xbe] +0x66,0x09,0x80,0xbe + +# GFX12: s_ctz_i32_b64 s0, s[2:3] ; encoding: [0x02,0x09,0x80,0xbe] +0x02,0x09,0x80,0xbe + +# GFX12: s_ctz_i32_b64 s0, vcc ; encoding: [0x6a,0x09,0x80,0xbe] +0x6a,0x09,0x80,0xbe + +# GFX12: s_ctz_i32_b64 s105, s[102:103] ; encoding: [0x66,0x09,0xe9,0xbe] +0x66,0x09,0xe9,0xbe + +# GFX12: s_ctz_i32_b64 s105, s[2:3] ; encoding: [0x02,0x09,0xe9,0xbe] +0x02,0x09,0xe9,0xbe + +# GFX12: s_ctz_i32_b64 vcc_hi, s[2:3] ; encoding: [0x02,0x09,0xeb,0xbe] +0x02,0x09,0xeb,0xbe + +# GFX12: s_ctz_i32_b64 vcc_lo, s[2:3] ; encoding: [0x02,0x09,0xea,0xbe] +0x02,0x09,0xea,0xbe + +# GFX12: s_getpc_b64 exec ; encoding: [0x00,0x47,0xfe,0xbe] +0x00,0x47,0xfe,0xbe + +# GFX12: s_getpc_b64 s[0:1] ; encoding: [0x00,0x47,0x80,0xbe] +0x00,0x47,0x80,0xbe + +# GFX12: s_getpc_b64 s[104:105] ; encoding: [0x00,0x47,0xe8,0xbe] +0x00,0x47,0xe8,0xbe + +# GFX12: s_getpc_b64 vcc ; encoding: [0x00,0x47,0xea,0xbe] +0x00,0x47,0xea,0xbe + +# GFX12: s_mov_b32 exec_hi, s1 ; encoding: [0x01,0x00,0xff,0xbe] +0x01,0x00,0xff,0xbe + +# GFX12: s_mov_b32 exec_lo, s1 ; encoding: [0x01,0x00,0xfe,0xbe] +0x01,0x00,0xfe,0xbe + +# GFX12: s_mov_b32 m0, s1 ; encoding: [0x01,0x00,0xfd,0xbe] +0x01,0x00,0xfd,0xbe + +# GFX12: s_mov_b32 s0, 0.5 ; encoding: [0xf0,0x00,0x80,0xbe] +0xf0,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, 0 ; encoding: [0x80,0x00,0x80,0xbe] +0x80,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, 0x3f717273 ; encoding: [0xff,0x00,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x00,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_mov_b32 s0, 0xaf123456 ; encoding: [0xff,0x00,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x00,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_mov_b32 s0, -1 ; encoding: [0xc1,0x00,0x80,0xbe] +0xc1,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, -4.0 ; encoding: [0xf7,0x00,0x80,0xbe] +0xf7,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, exec_hi ; encoding: [0x7f,0x00,0x80,0xbe] +0x7f,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, exec_lo ; encoding: [0x7e,0x00,0x80,0xbe] +0x7e,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, m0 ; encoding: [0x7d,0x00,0x80,0xbe] +0x7d,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, s104 ; encoding: [0x68,0x00,0x80,0xbe] +0x68,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, s1 ; encoding: [0x01,0x00,0x80,0xbe] +0x01,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, vcc_hi ; encoding: [0x6b,0x00,0x80,0xbe] +0x6b,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s0, vcc_lo ; encoding: [0x6a,0x00,0x80,0xbe] +0x6a,0x00,0x80,0xbe + +# GFX12: s_mov_b32 s105, s104 ; encoding: [0x68,0x00,0xe9,0xbe] +0x68,0x00,0xe9,0xbe + +# GFX12: s_mov_b32 s105, s1 ; encoding: [0x01,0x00,0xe9,0xbe] +0x01,0x00,0xe9,0xbe + +# GFX12: s_mov_b32 vcc_hi, s1 ; encoding: [0x01,0x00,0xeb,0xbe] +0x01,0x00,0xeb,0xbe + +# GFX12: s_mov_b32 vcc_lo, s1 ; encoding: [0x01,0x00,0xea,0xbe] +0x01,0x00,0xea,0xbe + +# GFX12: s_mov_b32 s0, null ; encoding: [0x7c,0x00,0x80,0xbe] +0x7c,0x00,0x80,0xbe + +# GFX12: s_mov_b32 null, s1 ; encoding: [0x01,0x00,0xfc,0xbe] +0x01,0x00,0xfc,0xbe + +# GFX12: s_mov_b64 exec, s[2:3] ; encoding: [0x02,0x01,0xfe,0xbe] +0x02,0x01,0xfe,0xbe + +# GFX12: s_mov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x01,0x80,0xbe] +0xf0,0x01,0x80,0xbe + +# GFX12: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x01,0x80,0xbe] +0x80,0x01,0x80,0xbe + +# GFX12: s_mov_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x01,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x01,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_mov_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x01,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_mov_b64 s[0:1], -1 ; encoding: [0xc1,0x01,0x80,0xbe] +0xc1,0x01,0x80,0xbe + +# GFX12: s_mov_b64 s[0:1], -4.0 ; encoding: [0xf7,0x01,0x80,0xbe] +0xf7,0x01,0x80,0xbe + +# GFX12: s_mov_b64 s[0:1], exec ; encoding: [0x7e,0x01,0x80,0xbe] +0x7e,0x01,0x80,0xbe + +# GFX12: s_mov_b64 s[0:1], s[102:103] ; encoding: [0x66,0x01,0x80,0xbe] +0x66,0x01,0x80,0xbe + +# GFX12: s_mov_b64 s[0:1], s[2:3] ; encoding: [0x02,0x01,0x80,0xbe] +0x02,0x01,0x80,0xbe + +# GFX12: s_mov_b64 s[0:1], vcc ; encoding: [0x6a,0x01,0x80,0xbe] +0x6a,0x01,0x80,0xbe + +# GFX12: s_mov_b64 s[104:105], s[102:103] ; encoding: [0x66,0x01,0xe8,0xbe] +0x66,0x01,0xe8,0xbe + +# GFX12: s_mov_b64 s[104:105], s[2:3] ; encoding: [0x02,0x01,0xe8,0xbe] +0x02,0x01,0xe8,0xbe + +# GFX12: s_mov_b64 vcc, s[2:3] ; encoding: [0x02,0x01,0xea,0xbe] +0x02,0x01,0xea,0xbe + +# GFX12: s_mov_b64 s[0:1], null ; encoding: [0x7c,0x01,0x80,0xbe] +0x7c,0x01,0x80,0xbe + +# GFX12: s_mov_b64 null, s[2:3] ; encoding: [0x02,0x01,0xfc,0xbe] +0x02,0x01,0xfc,0xbe + +# GFX12: s_movreld_b32 s0, 0.5 ; encoding: [0xf0,0x42,0x80,0xbe] +0xf0,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, 0 ; encoding: [0x80,0x42,0x80,0xbe] +0x80,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, 0x3f717273 ; encoding: [0xff,0x42,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x42,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_movreld_b32 s0, 0xaf123456 ; encoding: [0xff,0x42,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x42,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_movreld_b32 s0, -1 ; encoding: [0xc1,0x42,0x80,0xbe] +0xc1,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, -4.0 ; encoding: [0xf7,0x42,0x80,0xbe] +0xf7,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, exec_hi ; encoding: [0x7f,0x42,0x80,0xbe] +0x7f,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, exec_lo ; encoding: [0x7e,0x42,0x80,0xbe] +0x7e,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, m0 ; encoding: [0x7d,0x42,0x80,0xbe] +0x7d,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, s104 ; encoding: [0x68,0x42,0x80,0xbe] +0x68,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, s1 ; encoding: [0x01,0x42,0x80,0xbe] +0x01,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, vcc_hi ; encoding: [0x6b,0x42,0x80,0xbe] +0x6b,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s0, vcc_lo ; encoding: [0x6a,0x42,0x80,0xbe] +0x6a,0x42,0x80,0xbe + +# GFX12: s_movreld_b32 s105, s104 ; encoding: [0x68,0x42,0xe9,0xbe] +0x68,0x42,0xe9,0xbe + +# GFX12: s_movreld_b32 s105, s1 ; encoding: [0x01,0x42,0xe9,0xbe] +0x01,0x42,0xe9,0xbe + +# GFX12: s_movreld_b32 vcc_hi, s1 ; encoding: [0x01,0x42,0xeb,0xbe] +0x01,0x42,0xeb,0xbe + +# GFX12: s_movreld_b32 vcc_lo, s1 ; encoding: [0x01,0x42,0xea,0xbe] +0x01,0x42,0xea,0xbe + +# GFX12: s_movreld_b64 s[0:1], 0.5 ; encoding: [0xf0,0x43,0x80,0xbe] +0xf0,0x43,0x80,0xbe + +# GFX12: s_movreld_b64 s[0:1], 0 ; encoding: [0x80,0x43,0x80,0xbe] +0x80,0x43,0x80,0xbe + +# GFX12: s_movreld_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x43,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x43,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_movreld_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_movreld_b64 s[0:1], -1 ; encoding: [0xc1,0x43,0x80,0xbe] +0xc1,0x43,0x80,0xbe + +# GFX12: s_movreld_b64 s[0:1], -4.0 ; encoding: [0xf7,0x43,0x80,0xbe] +0xf7,0x43,0x80,0xbe + +# GFX12: s_movreld_b64 s[0:1], exec ; encoding: [0x7e,0x43,0x80,0xbe] +0x7e,0x43,0x80,0xbe + +# GFX12: s_movreld_b64 s[0:1], s[102:103] ; encoding: [0x66,0x43,0x80,0xbe] +0x66,0x43,0x80,0xbe + +# GFX12: s_movreld_b64 s[0:1], s[2:3] ; encoding: [0x02,0x43,0x80,0xbe] +0x02,0x43,0x80,0xbe + +# GFX12: s_movreld_b64 s[0:1], vcc ; encoding: [0x6a,0x43,0x80,0xbe] +0x6a,0x43,0x80,0xbe + +# GFX12: s_movreld_b64 s[104:105], s[102:103] ; encoding: [0x66,0x43,0xe8,0xbe] +0x66,0x43,0xe8,0xbe + +# GFX12: s_movreld_b64 s[104:105], s[2:3] ; encoding: [0x02,0x43,0xe8,0xbe] +0x02,0x43,0xe8,0xbe + +# GFX12: s_movreld_b64 vcc, s[2:3] ; encoding: [0x02,0x43,0xea,0xbe] +0x02,0x43,0xea,0xbe + +# GFX12: s_movrels_b32 exec_hi, s1 ; encoding: [0x01,0x40,0xff,0xbe] +0x01,0x40,0xff,0xbe + +# GFX12: s_movrels_b32 exec_lo, s1 ; encoding: [0x01,0x40,0xfe,0xbe] +0x01,0x40,0xfe,0xbe + +# GFX12: s_movrels_b32 m0, s1 ; encoding: [0x01,0x40,0xfd,0xbe] +0x01,0x40,0xfd,0xbe + +# GFX12: s_movrels_b32 s0, s104 ; encoding: [0x68,0x40,0x80,0xbe] +0x68,0x40,0x80,0xbe + +# GFX12: s_movrels_b32 s0, s1 ; encoding: [0x01,0x40,0x80,0xbe] +0x01,0x40,0x80,0xbe + +# GFX12: s_movrels_b32 s0, vcc_hi ; encoding: [0x6b,0x40,0x80,0xbe] +0x6b,0x40,0x80,0xbe + +# GFX12: s_movrels_b32 s0, vcc_lo ; encoding: [0x6a,0x40,0x80,0xbe] +0x6a,0x40,0x80,0xbe + +# GFX12: s_movrels_b32 s105, s104 ; encoding: [0x68,0x40,0xe9,0xbe] +0x68,0x40,0xe9,0xbe + +# GFX12: s_movrels_b32 s105, s1 ; encoding: [0x01,0x40,0xe9,0xbe] +0x01,0x40,0xe9,0xbe + +# GFX12: s_movrels_b32 vcc_hi, s1 ; encoding: [0x01,0x40,0xeb,0xbe] +0x01,0x40,0xeb,0xbe + +# GFX12: s_movrels_b32 vcc_lo, s1 ; encoding: [0x01,0x40,0xea,0xbe] +0x01,0x40,0xea,0xbe + +# GFX12: s_movrels_b64 exec, s[2:3] ; encoding: [0x02,0x41,0xfe,0xbe] +0x02,0x41,0xfe,0xbe + +# GFX12: s_movrels_b64 s[0:1], s[102:103] ; encoding: [0x66,0x41,0x80,0xbe] +0x66,0x41,0x80,0xbe + +# GFX12: s_movrels_b64 s[0:1], s[2:3] ; encoding: [0x02,0x41,0x80,0xbe] +0x02,0x41,0x80,0xbe + +# GFX12: s_movrels_b64 s[0:1], vcc ; encoding: [0x6a,0x41,0x80,0xbe] +0x6a,0x41,0x80,0xbe + +# GFX12: s_movrels_b64 s[104:105], s[102:103] ; encoding: [0x66,0x41,0xe8,0xbe] +0x66,0x41,0xe8,0xbe + +# GFX12: s_movrels_b64 s[104:105], s[2:3] ; encoding: [0x02,0x41,0xe8,0xbe] +0x02,0x41,0xe8,0xbe + +# GFX12: s_movrels_b64 vcc, s[2:3] ; encoding: [0x02,0x41,0xea,0xbe] +0x02,0x41,0xea,0xbe + +# GFX12: s_movrelsd_2_b32 s0, s104 ; encoding: [0x68,0x44,0x80,0xbe] +0x68,0x44,0x80,0xbe + +# GFX12: s_movrelsd_2_b32 s0, s1 ; encoding: [0x01,0x44,0x80,0xbe] +0x01,0x44,0x80,0xbe + +# GFX12: s_movrelsd_2_b32 s0, vcc_hi ; encoding: [0x6b,0x44,0x80,0xbe] +0x6b,0x44,0x80,0xbe + +# GFX12: s_movrelsd_2_b32 s0, vcc_lo ; encoding: [0x6a,0x44,0x80,0xbe] +0x6a,0x44,0x80,0xbe + +# GFX12: s_movrelsd_2_b32 s105, s104 ; encoding: [0x68,0x44,0xe9,0xbe] +0x68,0x44,0xe9,0xbe + +# GFX12: s_movrelsd_2_b32 s105, s1 ; encoding: [0x01,0x44,0xe9,0xbe] +0x01,0x44,0xe9,0xbe + +# GFX12: s_movrelsd_2_b32 vcc_hi, s1 ; encoding: [0x01,0x44,0xeb,0xbe] +0x01,0x44,0xeb,0xbe + +# GFX12: s_movrelsd_2_b32 vcc_lo, s1 ; encoding: [0x01,0x44,0xea,0xbe] +0x01,0x44,0xea,0xbe + +# GFX12: s_nand_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x26,0x80,0xbe] +0xf0,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, 0 ; encoding: [0x80,0x26,0x80,0xbe] +0x80,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x26,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x26,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_nand_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x26,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x26,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_nand_saveexec_b32 s0, -1 ; encoding: [0xc1,0x26,0x80,0xbe] +0xc1,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x26,0x80,0xbe] +0xf7,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x26,0x80,0xbe] +0x7f,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x26,0x80,0xbe] +0x7e,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, m0 ; encoding: [0x7d,0x26,0x80,0xbe] +0x7d,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, s104 ; encoding: [0x68,0x26,0x80,0xbe] +0x68,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, s1 ; encoding: [0x01,0x26,0x80,0xbe] +0x01,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x26,0x80,0xbe] +0x6b,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x26,0x80,0xbe] +0x6a,0x26,0x80,0xbe + +# GFX12: s_nand_saveexec_b32 s105, s104 ; encoding: [0x68,0x26,0xe9,0xbe] +0x68,0x26,0xe9,0xbe + +# GFX12: s_nand_saveexec_b32 s105, s1 ; encoding: [0x01,0x26,0xe9,0xbe] +0x01,0x26,0xe9,0xbe + +# GFX12: s_nand_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x26,0xeb,0xbe] +0x01,0x26,0xeb,0xbe + +# GFX12: s_nand_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x26,0xea,0xbe] +0x01,0x26,0xea,0xbe + +# GFX12: s_nand_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x27,0x80,0xbe] +0xf0,0x27,0x80,0xbe + +# GFX12: s_nand_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x27,0x80,0xbe] +0x80,0x27,0x80,0xbe + +# GFX12: s_nand_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x27,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x27,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_nand_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_nand_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x27,0x80,0xbe] +0xc1,0x27,0x80,0xbe + +# GFX12: s_nand_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x27,0x80,0xbe] +0xf7,0x27,0x80,0xbe + +# GFX12: s_nand_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x27,0x80,0xbe] +0x7e,0x27,0x80,0xbe + +# GFX12: s_nand_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x27,0x80,0xbe] +0x66,0x27,0x80,0xbe + +# GFX12: s_nand_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x27,0x80,0xbe] +0x02,0x27,0x80,0xbe + +# GFX12: s_nand_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x27,0x80,0xbe] +0x6a,0x27,0x80,0xbe + +# GFX12: s_nand_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x27,0xe8,0xbe] +0x66,0x27,0xe8,0xbe + +# GFX12: s_nand_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x27,0xe8,0xbe] +0x02,0x27,0xe8,0xbe + +# GFX12: s_nand_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x27,0xea,0xbe] +0x02,0x27,0xea,0xbe + +# GFX12: s_nor_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x28,0x80,0xbe] +0xf0,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, 0 ; encoding: [0x80,0x28,0x80,0xbe] +0x80,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x28,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x28,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_nor_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x28,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x28,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_nor_saveexec_b32 s0, -1 ; encoding: [0xc1,0x28,0x80,0xbe] +0xc1,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x28,0x80,0xbe] +0xf7,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x28,0x80,0xbe] +0x7f,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x28,0x80,0xbe] +0x7e,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, m0 ; encoding: [0x7d,0x28,0x80,0xbe] +0x7d,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, s104 ; encoding: [0x68,0x28,0x80,0xbe] +0x68,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, s1 ; encoding: [0x01,0x28,0x80,0xbe] +0x01,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x28,0x80,0xbe] +0x6b,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x28,0x80,0xbe] +0x6a,0x28,0x80,0xbe + +# GFX12: s_nor_saveexec_b32 s105, s104 ; encoding: [0x68,0x28,0xe9,0xbe] +0x68,0x28,0xe9,0xbe + +# GFX12: s_nor_saveexec_b32 s105, s1 ; encoding: [0x01,0x28,0xe9,0xbe] +0x01,0x28,0xe9,0xbe + +# GFX12: s_nor_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x28,0xeb,0xbe] +0x01,0x28,0xeb,0xbe + +# GFX12: s_nor_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x28,0xea,0xbe] +0x01,0x28,0xea,0xbe + +# GFX12: s_nor_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x29,0x80,0xbe] +0xf0,0x29,0x80,0xbe + +# GFX12: s_nor_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x29,0x80,0xbe] +0x80,0x29,0x80,0xbe + +# GFX12: s_nor_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x29,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x29,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_nor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_nor_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x29,0x80,0xbe] +0xc1,0x29,0x80,0xbe + +# GFX12: s_nor_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x29,0x80,0xbe] +0xf7,0x29,0x80,0xbe + +# GFX12: s_nor_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x29,0x80,0xbe] +0x7e,0x29,0x80,0xbe + +# GFX12: s_nor_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x29,0x80,0xbe] +0x66,0x29,0x80,0xbe + +# GFX12: s_nor_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x29,0x80,0xbe] +0x02,0x29,0x80,0xbe + +# GFX12: s_nor_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x29,0x80,0xbe] +0x6a,0x29,0x80,0xbe + +# GFX12: s_nor_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x29,0xe8,0xbe] +0x66,0x29,0xe8,0xbe + +# GFX12: s_nor_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x29,0xe8,0xbe] +0x02,0x29,0xe8,0xbe + +# GFX12: s_nor_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x29,0xea,0xbe] +0x02,0x29,0xea,0xbe + +# GFX12: s_not_b32 exec_hi, s1 ; encoding: [0x01,0x1e,0xff,0xbe] +0x01,0x1e,0xff,0xbe + +# GFX12: s_not_b32 exec_lo, s1 ; encoding: [0x01,0x1e,0xfe,0xbe] +0x01,0x1e,0xfe,0xbe + +# GFX12: s_not_b32 m0, s1 ; encoding: [0x01,0x1e,0xfd,0xbe] +0x01,0x1e,0xfd,0xbe + +# GFX12: s_not_b32 s0, 0.5 ; encoding: [0xf0,0x1e,0x80,0xbe] +0xf0,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, 0 ; encoding: [0x80,0x1e,0x80,0xbe] +0x80,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, 0x3f717273 ; encoding: [0xff,0x1e,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x1e,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_not_b32 s0, 0xaf123456 ; encoding: [0xff,0x1e,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x1e,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_not_b32 s0, -1 ; encoding: [0xc1,0x1e,0x80,0xbe] +0xc1,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, -4.0 ; encoding: [0xf7,0x1e,0x80,0xbe] +0xf7,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, exec_hi ; encoding: [0x7f,0x1e,0x80,0xbe] +0x7f,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, exec_lo ; encoding: [0x7e,0x1e,0x80,0xbe] +0x7e,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, m0 ; encoding: [0x7d,0x1e,0x80,0xbe] +0x7d,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, s104 ; encoding: [0x68,0x1e,0x80,0xbe] +0x68,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, s1 ; encoding: [0x01,0x1e,0x80,0xbe] +0x01,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, vcc_hi ; encoding: [0x6b,0x1e,0x80,0xbe] +0x6b,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s0, vcc_lo ; encoding: [0x6a,0x1e,0x80,0xbe] +0x6a,0x1e,0x80,0xbe + +# GFX12: s_not_b32 s105, s104 ; encoding: [0x68,0x1e,0xe9,0xbe] +0x68,0x1e,0xe9,0xbe + +# GFX12: s_not_b32 s105, s1 ; encoding: [0x01,0x1e,0xe9,0xbe] +0x01,0x1e,0xe9,0xbe + +# GFX12: s_not_b32 vcc_hi, s1 ; encoding: [0x01,0x1e,0xeb,0xbe] +0x01,0x1e,0xeb,0xbe + +# GFX12: s_not_b32 vcc_lo, s1 ; encoding: [0x01,0x1e,0xea,0xbe] +0x01,0x1e,0xea,0xbe + +# GFX12: s_not_b64 exec, s[2:3] ; encoding: [0x02,0x1f,0xfe,0xbe] +0x02,0x1f,0xfe,0xbe + +# GFX12: s_not_b64 s[0:1], 0.5 ; encoding: [0xf0,0x1f,0x80,0xbe] +0xf0,0x1f,0x80,0xbe + +# GFX12: s_not_b64 s[0:1], 0 ; encoding: [0x80,0x1f,0x80,0xbe] +0x80,0x1f,0x80,0xbe + +# GFX12: s_not_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x1f,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x1f,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_not_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x1f,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_not_b64 s[0:1], -1 ; encoding: [0xc1,0x1f,0x80,0xbe] +0xc1,0x1f,0x80,0xbe + +# GFX12: s_not_b64 s[0:1], -4.0 ; encoding: [0xf7,0x1f,0x80,0xbe] +0xf7,0x1f,0x80,0xbe + +# GFX12: s_not_b64 s[0:1], exec ; encoding: [0x7e,0x1f,0x80,0xbe] +0x7e,0x1f,0x80,0xbe + +# GFX12: s_not_b64 s[0:1], s[102:103] ; encoding: [0x66,0x1f,0x80,0xbe] +0x66,0x1f,0x80,0xbe + +# GFX12: s_not_b64 s[0:1], s[2:3] ; encoding: [0x02,0x1f,0x80,0xbe] +0x02,0x1f,0x80,0xbe + +# GFX12: s_not_b64 s[0:1], vcc ; encoding: [0x6a,0x1f,0x80,0xbe] +0x6a,0x1f,0x80,0xbe + +# GFX12: s_not_b64 s[104:105], s[102:103] ; encoding: [0x66,0x1f,0xe8,0xbe] +0x66,0x1f,0xe8,0xbe + +# GFX12: s_not_b64 s[104:105], s[2:3] ; encoding: [0x02,0x1f,0xe8,0xbe] +0x02,0x1f,0xe8,0xbe + +# GFX12: s_not_b64 vcc, s[2:3] ; encoding: [0x02,0x1f,0xea,0xbe] +0x02,0x1f,0xea,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x2e,0x80,0xbe] +0xf0,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, 0 ; encoding: [0x80,0x2e,0x80,0xbe] +0x80,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x2e,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x2e,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_or_not0_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x2e,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x2e,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_or_not0_saveexec_b32 s0, -1 ; encoding: [0xc1,0x2e,0x80,0xbe] +0xc1,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x2e,0x80,0xbe] +0xf7,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x2e,0x80,0xbe] +0x7f,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x2e,0x80,0xbe] +0x7e,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, m0 ; encoding: [0x7d,0x2e,0x80,0xbe] +0x7d,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, s104 ; encoding: [0x68,0x2e,0x80,0xbe] +0x68,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, s1 ; encoding: [0x01,0x2e,0x80,0xbe] +0x01,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x2e,0x80,0xbe] +0x6b,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x2e,0x80,0xbe] +0x6a,0x2e,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b32 s105, s104 ; encoding: [0x68,0x2e,0xe9,0xbe] +0x68,0x2e,0xe9,0xbe + +# GFX12: s_or_not0_saveexec_b32 s105, s1 ; encoding: [0x01,0x2e,0xe9,0xbe] +0x01,0x2e,0xe9,0xbe + +# GFX12: s_or_not0_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x2e,0xeb,0xbe] +0x01,0x2e,0xeb,0xbe + +# GFX12: s_or_not0_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x2e,0xea,0xbe] +0x01,0x2e,0xea,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x2f,0x80,0xbe] +0xf0,0x2f,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x2f,0x80,0xbe] +0x80,0x2f,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x2f,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x2f,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_or_not0_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x2f,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_or_not0_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x2f,0x80,0xbe] +0xc1,0x2f,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x2f,0x80,0xbe] +0xf7,0x2f,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x2f,0x80,0xbe] +0x7e,0x2f,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x2f,0x80,0xbe] +0x66,0x2f,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x2f,0x80,0xbe] +0x02,0x2f,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x2f,0x80,0xbe] +0x6a,0x2f,0x80,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x2f,0xe8,0xbe] +0x66,0x2f,0xe8,0xbe + +# GFX12: s_or_not0_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x2f,0xe8,0xbe] +0x02,0x2f,0xe8,0xbe + +# GFX12: s_or_not0_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x2f,0xea,0xbe] +0x02,0x2f,0xea,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x32,0x80,0xbe] +0xf0,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, 0 ; encoding: [0x80,0x32,0x80,0xbe] +0x80,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x32,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x32,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_or_not1_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x32,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x32,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_or_not1_saveexec_b32 s0, -1 ; encoding: [0xc1,0x32,0x80,0xbe] +0xc1,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x32,0x80,0xbe] +0xf7,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x32,0x80,0xbe] +0x7f,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x32,0x80,0xbe] +0x7e,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, m0 ; encoding: [0x7d,0x32,0x80,0xbe] +0x7d,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, s104 ; encoding: [0x68,0x32,0x80,0xbe] +0x68,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, s1 ; encoding: [0x01,0x32,0x80,0xbe] +0x01,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x32,0x80,0xbe] +0x6b,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x32,0x80,0xbe] +0x6a,0x32,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b32 s105, s104 ; encoding: [0x68,0x32,0xe9,0xbe] +0x68,0x32,0xe9,0xbe + +# GFX12: s_or_not1_saveexec_b32 s105, s1 ; encoding: [0x01,0x32,0xe9,0xbe] +0x01,0x32,0xe9,0xbe + +# GFX12: s_or_not1_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x32,0xeb,0xbe] +0x01,0x32,0xeb,0xbe + +# GFX12: s_or_not1_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x32,0xea,0xbe] +0x01,0x32,0xea,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x33,0x80,0xbe] +0xf0,0x33,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x33,0x80,0xbe] +0x80,0x33,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x33,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x33,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_or_not1_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x33,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_or_not1_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x33,0x80,0xbe] +0xc1,0x33,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x33,0x80,0xbe] +0xf7,0x33,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x33,0x80,0xbe] +0x7e,0x33,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x33,0x80,0xbe] +0x66,0x33,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x33,0x80,0xbe] +0x02,0x33,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x33,0x80,0xbe] +0x6a,0x33,0x80,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x33,0xe8,0xbe] +0x66,0x33,0xe8,0xbe + +# GFX12: s_or_not1_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x33,0xe8,0xbe] +0x02,0x33,0xe8,0xbe + +# GFX12: s_or_not1_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x33,0xea,0xbe] +0x02,0x33,0xea,0xbe + +# GFX12: s_or_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x22,0x80,0xbe] +0xf0,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, 0 ; encoding: [0x80,0x22,0x80,0xbe] +0x80,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x22,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x22,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_or_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x22,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x22,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_or_saveexec_b32 s0, -1 ; encoding: [0xc1,0x22,0x80,0xbe] +0xc1,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x22,0x80,0xbe] +0xf7,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x22,0x80,0xbe] +0x7f,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x22,0x80,0xbe] +0x7e,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, m0 ; encoding: [0x7d,0x22,0x80,0xbe] +0x7d,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, s104 ; encoding: [0x68,0x22,0x80,0xbe] +0x68,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, s1 ; encoding: [0x01,0x22,0x80,0xbe] +0x01,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x22,0x80,0xbe] +0x6b,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x22,0x80,0xbe] +0x6a,0x22,0x80,0xbe + +# GFX12: s_or_saveexec_b32 s105, s104 ; encoding: [0x68,0x22,0xe9,0xbe] +0x68,0x22,0xe9,0xbe + +# GFX12: s_or_saveexec_b32 s105, s1 ; encoding: [0x01,0x22,0xe9,0xbe] +0x01,0x22,0xe9,0xbe + +# GFX12: s_or_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x22,0xeb,0xbe] +0x01,0x22,0xeb,0xbe + +# GFX12: s_or_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x22,0xea,0xbe] +0x01,0x22,0xea,0xbe + +# GFX12: s_or_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x23,0x80,0xbe] +0xf0,0x23,0x80,0xbe + +# GFX12: s_or_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x23,0x80,0xbe] +0x80,0x23,0x80,0xbe + +# GFX12: s_or_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x23,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x23,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_or_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x23,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_or_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x23,0x80,0xbe] +0xc1,0x23,0x80,0xbe + +# GFX12: s_or_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x23,0x80,0xbe] +0xf7,0x23,0x80,0xbe + +# GFX12: s_or_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x23,0x80,0xbe] +0x7e,0x23,0x80,0xbe + +# GFX12: s_or_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x23,0x80,0xbe] +0x66,0x23,0x80,0xbe + +# GFX12: s_or_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x23,0x80,0xbe] +0x02,0x23,0x80,0xbe + +# GFX12: s_or_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x23,0x80,0xbe] +0x6a,0x23,0x80,0xbe + +# GFX12: s_or_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x23,0xe8,0xbe] +0x66,0x23,0xe8,0xbe + +# GFX12: s_or_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x23,0xe8,0xbe] +0x02,0x23,0xe8,0xbe + +# GFX12: s_or_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x23,0xea,0xbe] +0x02,0x23,0xea,0xbe + +# GFX12: s_quadmask_b32 exec_hi, s1 ; encoding: [0x01,0x1a,0xff,0xbe] +0x01,0x1a,0xff,0xbe + +# GFX12: s_quadmask_b32 exec_lo, s1 ; encoding: [0x01,0x1a,0xfe,0xbe] +0x01,0x1a,0xfe,0xbe + +# GFX12: s_quadmask_b32 m0, s1 ; encoding: [0x01,0x1a,0xfd,0xbe] +0x01,0x1a,0xfd,0xbe + +# GFX12: s_quadmask_b32 s0, 0.5 ; encoding: [0xf0,0x1a,0x80,0xbe] +0xf0,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, 0 ; encoding: [0x80,0x1a,0x80,0xbe] +0x80,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, 0x3f717273 ; encoding: [0xff,0x1a,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x1a,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_quadmask_b32 s0, 0xaf123456 ; encoding: [0xff,0x1a,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x1a,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_quadmask_b32 s0, -1 ; encoding: [0xc1,0x1a,0x80,0xbe] +0xc1,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, -4.0 ; encoding: [0xf7,0x1a,0x80,0xbe] +0xf7,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, exec_hi ; encoding: [0x7f,0x1a,0x80,0xbe] +0x7f,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, exec_lo ; encoding: [0x7e,0x1a,0x80,0xbe] +0x7e,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, m0 ; encoding: [0x7d,0x1a,0x80,0xbe] +0x7d,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, s104 ; encoding: [0x68,0x1a,0x80,0xbe] +0x68,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, s1 ; encoding: [0x01,0x1a,0x80,0xbe] +0x01,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, vcc_hi ; encoding: [0x6b,0x1a,0x80,0xbe] +0x6b,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s0, vcc_lo ; encoding: [0x6a,0x1a,0x80,0xbe] +0x6a,0x1a,0x80,0xbe + +# GFX12: s_quadmask_b32 s105, s104 ; encoding: [0x68,0x1a,0xe9,0xbe] +0x68,0x1a,0xe9,0xbe + +# GFX12: s_quadmask_b32 s105, s1 ; encoding: [0x01,0x1a,0xe9,0xbe] +0x01,0x1a,0xe9,0xbe + +# GFX12: s_quadmask_b32 vcc_hi, s1 ; encoding: [0x01,0x1a,0xeb,0xbe] +0x01,0x1a,0xeb,0xbe + +# GFX12: s_quadmask_b32 vcc_lo, s1 ; encoding: [0x01,0x1a,0xea,0xbe] +0x01,0x1a,0xea,0xbe + +# GFX12: s_quadmask_b64 exec, s[2:3] ; encoding: [0x02,0x1b,0xfe,0xbe] +0x02,0x1b,0xfe,0xbe + +# GFX12: s_quadmask_b64 s[0:1], 0.5 ; encoding: [0xf0,0x1b,0x80,0xbe] +0xf0,0x1b,0x80,0xbe + +# GFX12: s_quadmask_b64 s[0:1], 0 ; encoding: [0x80,0x1b,0x80,0xbe] +0x80,0x1b,0x80,0xbe + +# GFX12: s_quadmask_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x1b,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x1b,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_quadmask_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_quadmask_b64 s[0:1], -1 ; encoding: [0xc1,0x1b,0x80,0xbe] +0xc1,0x1b,0x80,0xbe + +# GFX12: s_quadmask_b64 s[0:1], -4.0 ; encoding: [0xf7,0x1b,0x80,0xbe] +0xf7,0x1b,0x80,0xbe + +# GFX12: s_quadmask_b64 s[0:1], exec ; encoding: [0x7e,0x1b,0x80,0xbe] +0x7e,0x1b,0x80,0xbe + +# GFX12: s_quadmask_b64 s[0:1], s[102:103] ; encoding: [0x66,0x1b,0x80,0xbe] +0x66,0x1b,0x80,0xbe + +# GFX12: s_quadmask_b64 s[0:1], s[2:3] ; encoding: [0x02,0x1b,0x80,0xbe] +0x02,0x1b,0x80,0xbe + +# GFX12: s_quadmask_b64 s[0:1], vcc ; encoding: [0x6a,0x1b,0x80,0xbe] +0x6a,0x1b,0x80,0xbe + +# GFX12: s_quadmask_b64 s[104:105], s[102:103] ; encoding: [0x66,0x1b,0xe8,0xbe] +0x66,0x1b,0xe8,0xbe + +# GFX12: s_quadmask_b64 s[104:105], s[2:3] ; encoding: [0x02,0x1b,0xe8,0xbe] +0x02,0x1b,0xe8,0xbe + +# GFX12: s_quadmask_b64 vcc, s[2:3] ; encoding: [0x02,0x1b,0xea,0xbe] +0x02,0x1b,0xea,0xbe + +# GFX12: s_rfe_b64 s[0:1] ; encoding: [0x00,0x4a,0x80,0xbe] +0x00,0x4a,0x80,0xbe + +# GFX12: s_rfe_b64 s[104:105] ; encoding: [0x68,0x4a,0x80,0xbe] +0x68,0x4a,0x80,0xbe + +# GFX12: s_rfe_b64 vcc ; encoding: [0x6a,0x4a,0x80,0xbe] +0x6a,0x4a,0x80,0xbe + +# GFX12: s_sendmsg_rtn_b32 s1, sendmsg(0, 0, 0) ; encoding: [0x00,0x4c,0x81,0xbe] +0x00,0x4c,0x81,0xbe + +# GFX12: s_sendmsg_rtn_b32 s2, sendmsg(18, 0, 0) ; encoding: [0x12,0x4c,0x82,0xbe] +0x12,0x4c,0x82,0xbe + +# GFX12: s_sendmsg_rtn_b32 s3, sendmsg(255, 0, 0) ; encoding: [0xff,0x4c,0x83,0xbe] +0xff,0x4c,0x83,0xbe + +# GFX12: s_sendmsg_rtn_b64 s[0:1], sendmsg(0, 0, 0) ; encoding: [0x00,0x4d,0x80,0xbe] +0x00,0x4d,0x80,0xbe + +# GFX12: s_sendmsg_rtn_b64 s[2:3], sendmsg(18, 0, 0) ; encoding: [0x12,0x4d,0x82,0xbe] +0x12,0x4d,0x82,0xbe + +# GFX12: s_sendmsg_rtn_b64 s[4:5], sendmsg(255, 0, 0) ; encoding: [0xff,0x4d,0x84,0xbe] +0xff,0x4d,0x84,0xbe + +# GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL) ; encoding: [0x80,0x4c,0x80,0xbe] +0x80,0x4c,0x80,0xbe + +# GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DDID) ; encoding: [0x81,0x4c,0x80,0xbe] +0x81,0x4c,0x80,0xbe + +# GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_TMA) ; encoding: [0x82,0x4c,0x80,0xbe] +0x82,0x4c,0x80,0xbe + +# GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_REALTIME) ; encoding: [0x83,0x4c,0x80,0xbe] +0x83,0x4c,0x80,0xbe + +# GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_SAVE_WAVE) ; encoding: [0x84,0x4c,0x80,0xbe] +0x84,0x4c,0x80,0xbe + +# GFX12: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_TBA) ; encoding: [0x85,0x4c,0x80,0xbe] +0x85,0x4c,0x80,0xbe + +# GFX12: s_setpc_b64 s[0:1] ; encoding: [0x00,0x48,0x80,0xbe] +0x00,0x48,0x80,0xbe + +# GFX12: s_setpc_b64 s[104:105] ; encoding: [0x68,0x48,0x80,0xbe] +0x68,0x48,0x80,0xbe + +# GFX12: s_setpc_b64 vcc ; encoding: [0x6a,0x48,0x80,0xbe] +0x6a,0x48,0x80,0xbe + +# GFX12: s_sext_i32_i16 exec_hi, s1 ; encoding: [0x01,0x0f,0xff,0xbe] +0x01,0x0f,0xff,0xbe + +# GFX12: s_sext_i32_i16 exec_lo, s1 ; encoding: [0x01,0x0f,0xfe,0xbe] +0x01,0x0f,0xfe,0xbe + +# GFX12: s_sext_i32_i16 m0, s1 ; encoding: [0x01,0x0f,0xfd,0xbe] +0x01,0x0f,0xfd,0xbe + +# GFX12: s_sext_i32_i16 s0, 0.5 ; encoding: [0xf0,0x0f,0x80,0xbe] +0xf0,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, 0 ; encoding: [0x80,0x0f,0x80,0xbe] +0x80,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, 0x3f717273 ; encoding: [0xff,0x0f,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x0f,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_sext_i32_i16 s0, 0xaf123456 ; encoding: [0xff,0x0f,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x0f,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_sext_i32_i16 s0, -1 ; encoding: [0xc1,0x0f,0x80,0xbe] +0xc1,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, -4.0 ; encoding: [0xf7,0x0f,0x80,0xbe] +0xf7,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, exec_hi ; encoding: [0x7f,0x0f,0x80,0xbe] +0x7f,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, exec_lo ; encoding: [0x7e,0x0f,0x80,0xbe] +0x7e,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, m0 ; encoding: [0x7d,0x0f,0x80,0xbe] +0x7d,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, s104 ; encoding: [0x68,0x0f,0x80,0xbe] +0x68,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, s1 ; encoding: [0x01,0x0f,0x80,0xbe] +0x01,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, vcc_hi ; encoding: [0x6b,0x0f,0x80,0xbe] +0x6b,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s0, vcc_lo ; encoding: [0x6a,0x0f,0x80,0xbe] +0x6a,0x0f,0x80,0xbe + +# GFX12: s_sext_i32_i16 s105, s104 ; encoding: [0x68,0x0f,0xe9,0xbe] +0x68,0x0f,0xe9,0xbe + +# GFX12: s_sext_i32_i16 s105, s1 ; encoding: [0x01,0x0f,0xe9,0xbe] +0x01,0x0f,0xe9,0xbe + +# GFX12: s_sext_i32_i16 vcc_hi, s1 ; encoding: [0x01,0x0f,0xeb,0xbe] +0x01,0x0f,0xeb,0xbe + +# GFX12: s_sext_i32_i16 vcc_lo, s1 ; encoding: [0x01,0x0f,0xea,0xbe] +0x01,0x0f,0xea,0xbe + +# GFX12: s_sext_i32_i8 exec_hi, s1 ; encoding: [0x01,0x0e,0xff,0xbe] +0x01,0x0e,0xff,0xbe + +# GFX12: s_sext_i32_i8 exec_lo, s1 ; encoding: [0x01,0x0e,0xfe,0xbe] +0x01,0x0e,0xfe,0xbe + +# GFX12: s_sext_i32_i8 m0, s1 ; encoding: [0x01,0x0e,0xfd,0xbe] +0x01,0x0e,0xfd,0xbe + +# GFX12: s_sext_i32_i8 s0, 0.5 ; encoding: [0xf0,0x0e,0x80,0xbe] +0xf0,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, 0 ; encoding: [0x80,0x0e,0x80,0xbe] +0x80,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, 0x3f717273 ; encoding: [0xff,0x0e,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x0e,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_sext_i32_i8 s0, 0xaf123456 ; encoding: [0xff,0x0e,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x0e,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_sext_i32_i8 s0, -1 ; encoding: [0xc1,0x0e,0x80,0xbe] +0xc1,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, -4.0 ; encoding: [0xf7,0x0e,0x80,0xbe] +0xf7,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, exec_hi ; encoding: [0x7f,0x0e,0x80,0xbe] +0x7f,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, exec_lo ; encoding: [0x7e,0x0e,0x80,0xbe] +0x7e,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, m0 ; encoding: [0x7d,0x0e,0x80,0xbe] +0x7d,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, s104 ; encoding: [0x68,0x0e,0x80,0xbe] +0x68,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, s1 ; encoding: [0x01,0x0e,0x80,0xbe] +0x01,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, vcc_hi ; encoding: [0x6b,0x0e,0x80,0xbe] +0x6b,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s0, vcc_lo ; encoding: [0x6a,0x0e,0x80,0xbe] +0x6a,0x0e,0x80,0xbe + +# GFX12: s_sext_i32_i8 s105, s104 ; encoding: [0x68,0x0e,0xe9,0xbe] +0x68,0x0e,0xe9,0xbe + +# GFX12: s_sext_i32_i8 s105, s1 ; encoding: [0x01,0x0e,0xe9,0xbe] +0x01,0x0e,0xe9,0xbe + +# GFX12: s_sext_i32_i8 vcc_hi, s1 ; encoding: [0x01,0x0e,0xeb,0xbe] +0x01,0x0e,0xeb,0xbe + +# GFX12: s_sext_i32_i8 vcc_lo, s1 ; encoding: [0x01,0x0e,0xea,0xbe] +0x01,0x0e,0xea,0xbe + +# GFX12: s_swappc_b64 s[0:1], s[102:103] ; encoding: [0x66,0x49,0x80,0xbe] +0x66,0x49,0x80,0xbe + +# GFX12: s_swappc_b64 s[0:1], s[2:3] ; encoding: [0x02,0x49,0x80,0xbe] +0x02,0x49,0x80,0xbe + +# GFX12: s_swappc_b64 s[0:1], vcc ; encoding: [0x6a,0x49,0x80,0xbe] +0x6a,0x49,0x80,0xbe + +# GFX12: s_swappc_b64 s[104:105], s[102:103] ; encoding: [0x66,0x49,0xe8,0xbe] +0x66,0x49,0xe8,0xbe + +# GFX12: s_swappc_b64 s[104:105], s[2:3] ; encoding: [0x02,0x49,0xe8,0xbe] +0x02,0x49,0xe8,0xbe + +# GFX12: s_swappc_b64 vcc, s[2:3] ; encoding: [0x02,0x49,0xea,0xbe] +0x02,0x49,0xea,0xbe + +# GFX12: s_wqm_b32 exec_hi, s1 ; encoding: [0x01,0x1c,0xff,0xbe] +0x01,0x1c,0xff,0xbe + +# GFX12: s_wqm_b32 exec_lo, s1 ; encoding: [0x01,0x1c,0xfe,0xbe] +0x01,0x1c,0xfe,0xbe + +# GFX12: s_wqm_b32 m0, s1 ; encoding: [0x01,0x1c,0xfd,0xbe] +0x01,0x1c,0xfd,0xbe + +# GFX12: s_wqm_b32 s0, 0.5 ; encoding: [0xf0,0x1c,0x80,0xbe] +0xf0,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, 0 ; encoding: [0x80,0x1c,0x80,0xbe] +0x80,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, 0x3f717273 ; encoding: [0xff,0x1c,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x1c,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_wqm_b32 s0, 0xaf123456 ; encoding: [0xff,0x1c,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x1c,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_wqm_b32 s0, -1 ; encoding: [0xc1,0x1c,0x80,0xbe] +0xc1,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, -4.0 ; encoding: [0xf7,0x1c,0x80,0xbe] +0xf7,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, exec_hi ; encoding: [0x7f,0x1c,0x80,0xbe] +0x7f,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, exec_lo ; encoding: [0x7e,0x1c,0x80,0xbe] +0x7e,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, m0 ; encoding: [0x7d,0x1c,0x80,0xbe] +0x7d,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, s104 ; encoding: [0x68,0x1c,0x80,0xbe] +0x68,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, s1 ; encoding: [0x01,0x1c,0x80,0xbe] +0x01,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, vcc_hi ; encoding: [0x6b,0x1c,0x80,0xbe] +0x6b,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s0, vcc_lo ; encoding: [0x6a,0x1c,0x80,0xbe] +0x6a,0x1c,0x80,0xbe + +# GFX12: s_wqm_b32 s105, s104 ; encoding: [0x68,0x1c,0xe9,0xbe] +0x68,0x1c,0xe9,0xbe + +# GFX12: s_wqm_b32 s105, s1 ; encoding: [0x01,0x1c,0xe9,0xbe] +0x01,0x1c,0xe9,0xbe + +# GFX12: s_wqm_b32 vcc_hi, s1 ; encoding: [0x01,0x1c,0xeb,0xbe] +0x01,0x1c,0xeb,0xbe + +# GFX12: s_wqm_b32 vcc_lo, s1 ; encoding: [0x01,0x1c,0xea,0xbe] +0x01,0x1c,0xea,0xbe + +# GFX12: s_wqm_b64 exec, s[2:3] ; encoding: [0x02,0x1d,0xfe,0xbe] +0x02,0x1d,0xfe,0xbe + +# GFX12: s_wqm_b64 s[0:1], 0.5 ; encoding: [0xf0,0x1d,0x80,0xbe] +0xf0,0x1d,0x80,0xbe + +# GFX12: s_wqm_b64 s[0:1], 0 ; encoding: [0x80,0x1d,0x80,0xbe] +0x80,0x1d,0x80,0xbe + +# GFX12: s_wqm_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x1d,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x1d,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_wqm_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_wqm_b64 s[0:1], -1 ; encoding: [0xc1,0x1d,0x80,0xbe] +0xc1,0x1d,0x80,0xbe + +# GFX12: s_wqm_b64 s[0:1], -4.0 ; encoding: [0xf7,0x1d,0x80,0xbe] +0xf7,0x1d,0x80,0xbe + +# GFX12: s_wqm_b64 s[0:1], exec ; encoding: [0x7e,0x1d,0x80,0xbe] +0x7e,0x1d,0x80,0xbe + +# GFX12: s_wqm_b64 s[0:1], s[102:103] ; encoding: [0x66,0x1d,0x80,0xbe] +0x66,0x1d,0x80,0xbe + +# GFX12: s_wqm_b64 s[0:1], s[2:3] ; encoding: [0x02,0x1d,0x80,0xbe] +0x02,0x1d,0x80,0xbe + +# GFX12: s_wqm_b64 s[0:1], vcc ; encoding: [0x6a,0x1d,0x80,0xbe] +0x6a,0x1d,0x80,0xbe + +# GFX12: s_wqm_b64 s[104:105], s[102:103] ; encoding: [0x66,0x1d,0xe8,0xbe] +0x66,0x1d,0xe8,0xbe + +# GFX12: s_wqm_b64 s[104:105], s[2:3] ; encoding: [0x02,0x1d,0xe8,0xbe] +0x02,0x1d,0xe8,0xbe + +# GFX12: s_wqm_b64 vcc, s[2:3] ; encoding: [0x02,0x1d,0xea,0xbe] +0x02,0x1d,0xea,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x2a,0x80,0xbe] +0xf0,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, 0 ; encoding: [0x80,0x2a,0x80,0xbe] +0x80,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x2a,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x2a,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_xnor_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x2a,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x2a,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_xnor_saveexec_b32 s0, -1 ; encoding: [0xc1,0x2a,0x80,0xbe] +0xc1,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x2a,0x80,0xbe] +0xf7,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x2a,0x80,0xbe] +0x7f,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x2a,0x80,0xbe] +0x7e,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, m0 ; encoding: [0x7d,0x2a,0x80,0xbe] +0x7d,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, s104 ; encoding: [0x68,0x2a,0x80,0xbe] +0x68,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, s1 ; encoding: [0x01,0x2a,0x80,0xbe] +0x01,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x2a,0x80,0xbe] +0x6b,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x2a,0x80,0xbe] +0x6a,0x2a,0x80,0xbe + +# GFX12: s_xnor_saveexec_b32 s105, s104 ; encoding: [0x68,0x2a,0xe9,0xbe] +0x68,0x2a,0xe9,0xbe + +# GFX12: s_xnor_saveexec_b32 s105, s1 ; encoding: [0x01,0x2a,0xe9,0xbe] +0x01,0x2a,0xe9,0xbe + +# GFX12: s_xnor_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x2a,0xeb,0xbe] +0x01,0x2a,0xeb,0xbe + +# GFX12: s_xnor_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x2a,0xea,0xbe] +0x01,0x2a,0xea,0xbe + +# GFX12: s_xnor_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x2b,0x80,0xbe] +0xf0,0x2b,0x80,0xbe + +# GFX12: s_xnor_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x2b,0x80,0xbe] +0x80,0x2b,0x80,0xbe + +# GFX12: s_xnor_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x2b,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x2b,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_xnor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_xnor_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x2b,0x80,0xbe] +0xc1,0x2b,0x80,0xbe + +# GFX12: s_xnor_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x2b,0x80,0xbe] +0xf7,0x2b,0x80,0xbe + +# GFX12: s_xnor_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x2b,0x80,0xbe] +0x7e,0x2b,0x80,0xbe + +# GFX12: s_xnor_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x2b,0x80,0xbe] +0x66,0x2b,0x80,0xbe + +# GFX12: s_xnor_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x2b,0x80,0xbe] +0x02,0x2b,0x80,0xbe + +# GFX12: s_xnor_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x2b,0x80,0xbe] +0x6a,0x2b,0x80,0xbe + +# GFX12: s_xnor_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x2b,0xe8,0xbe] +0x66,0x2b,0xe8,0xbe + +# GFX12: s_xnor_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x2b,0xe8,0xbe] +0x02,0x2b,0xe8,0xbe + +# GFX12: s_xnor_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x2b,0xea,0xbe] +0x02,0x2b,0xea,0xbe + +# GFX12: s_xor_saveexec_b32 s0, 0.5 ; encoding: [0xf0,0x24,0x80,0xbe] +0xf0,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, 0 ; encoding: [0x80,0x24,0x80,0xbe] +0x80,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, 0x3f717273 ; encoding: [0xff,0x24,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x24,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_xor_saveexec_b32 s0, 0xaf123456 ; encoding: [0xff,0x24,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x24,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_xor_saveexec_b32 s0, -1 ; encoding: [0xc1,0x24,0x80,0xbe] +0xc1,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, -4.0 ; encoding: [0xf7,0x24,0x80,0xbe] +0xf7,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, exec_hi ; encoding: [0x7f,0x24,0x80,0xbe] +0x7f,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, exec_lo ; encoding: [0x7e,0x24,0x80,0xbe] +0x7e,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, m0 ; encoding: [0x7d,0x24,0x80,0xbe] +0x7d,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, s104 ; encoding: [0x68,0x24,0x80,0xbe] +0x68,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, s1 ; encoding: [0x01,0x24,0x80,0xbe] +0x01,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, vcc_hi ; encoding: [0x6b,0x24,0x80,0xbe] +0x6b,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s0, vcc_lo ; encoding: [0x6a,0x24,0x80,0xbe] +0x6a,0x24,0x80,0xbe + +# GFX12: s_xor_saveexec_b32 s105, s104 ; encoding: [0x68,0x24,0xe9,0xbe] +0x68,0x24,0xe9,0xbe + +# GFX12: s_xor_saveexec_b32 s105, s1 ; encoding: [0x01,0x24,0xe9,0xbe] +0x01,0x24,0xe9,0xbe + +# GFX12: s_xor_saveexec_b32 vcc_hi, s1 ; encoding: [0x01,0x24,0xeb,0xbe] +0x01,0x24,0xeb,0xbe + +# GFX12: s_xor_saveexec_b32 vcc_lo, s1 ; encoding: [0x01,0x24,0xea,0xbe] +0x01,0x24,0xea,0xbe + +# GFX12: s_xor_saveexec_b64 s[0:1], 0.5 ; encoding: [0xf0,0x25,0x80,0xbe] +0xf0,0x25,0x80,0xbe + +# GFX12: s_xor_saveexec_b64 s[0:1], 0 ; encoding: [0x80,0x25,0x80,0xbe] +0x80,0x25,0x80,0xbe + +# GFX12: s_xor_saveexec_b64 s[0:1], 0x3f717273 ; encoding: [0xff,0x25,0x80,0xbe,0x73,0x72,0x71,0x3f] +0xff,0x25,0x80,0xbe,0x73,0x72,0x71,0x3f + +# GFX12: s_xor_saveexec_b64 s[0:1], 0xaf123456 ; encoding: [0xff,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf] +0xff,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf + +# GFX12: s_xor_saveexec_b64 s[0:1], -1 ; encoding: [0xc1,0x25,0x80,0xbe] +0xc1,0x25,0x80,0xbe + +# GFX12: s_xor_saveexec_b64 s[0:1], -4.0 ; encoding: [0xf7,0x25,0x80,0xbe] +0xf7,0x25,0x80,0xbe + +# GFX12: s_xor_saveexec_b64 s[0:1], exec ; encoding: [0x7e,0x25,0x80,0xbe] +0x7e,0x25,0x80,0xbe + +# GFX12: s_xor_saveexec_b64 s[0:1], s[102:103] ; encoding: [0x66,0x25,0x80,0xbe] +0x66,0x25,0x80,0xbe + +# GFX12: s_xor_saveexec_b64 s[0:1], s[2:3] ; encoding: [0x02,0x25,0x80,0xbe] +0x02,0x25,0x80,0xbe + +# GFX12: s_xor_saveexec_b64 s[0:1], vcc ; encoding: [0x6a,0x25,0x80,0xbe] +0x6a,0x25,0x80,0xbe + +# GFX12: s_xor_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x25,0xe8,0xbe] +0x66,0x25,0xe8,0xbe + +# GFX12: s_xor_saveexec_b64 s[104:105], s[2:3] ; encoding: [0x02,0x25,0xe8,0xbe] +0x02,0x25,0xe8,0xbe + +# GFX12: s_xor_saveexec_b64 vcc, s[2:3] ; encoding: [0x02,0x25,0xea,0xbe] +0x02,0x25,0xea,0xbe diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt new file mode 100644 index 000000000000..c177af7a6e50 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt @@ -0,0 +1,5960 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0xa9] +0x02,0x04,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[100:101], s[102:103], s[104:105] ; encoding: [0x66,0x68,0xe4,0xa9] +0x66,0x68,0xe4,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], s[104:105], s[102:103] ; encoding: [0x68,0x66,0x80,0xa9] +0x68,0x66,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[104:105], s[0:1], s[102:103] ; encoding: [0x00,0x66,0xe8,0xa9] +0x00,0x66,0xe8,0xa9 + +# GFX12: s_add_nc_u64 s[104:105], s[102:103], s[2:3] ; encoding: [0x66,0x02,0xe8,0xa9] +0x66,0x02,0xe8,0xa9 + +# GFX12: s_add_nc_u64 s[104:105], s[0:1], s[2:3] ; encoding: [0x00,0x02,0xe8,0xa9] +0x00,0x02,0xe8,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], s[102:103], s[2:3] ; encoding: [0x66,0x02,0x80,0xa9] +0x66,0x02,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], s[102:103] ; encoding: [0x02,0x66,0x80,0xa9] +0x02,0x66,0x80,0xa9 + +# GFX12: s_add_nc_u64 exec, s[0:1], s[2:3] ; encoding: [0x00,0x02,0xfe,0xa9] +0x00,0x02,0xfe,0xa9 + +# GFX12: s_add_nc_u64 vcc, s[0:1], s[2:3] ; encoding: [0x00,0x02,0xea,0xa9] +0x00,0x02,0xea,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], exec, s[2:3] ; encoding: [0x7e,0x02,0x80,0xa9] +0x7e,0x02,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], vcc, s[2:3] ; encoding: [0x6a,0x02,0x80,0xa9] +0x6a,0x02,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], 0, s[2:3] ; encoding: [0x80,0x02,0x80,0xa9] +0x80,0x02,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], -1, s[2:3] ; encoding: [0xc1,0x02,0x80,0xa9] +0xc1,0x02,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], 0.5, s[2:3] ; encoding: [0xf0,0x02,0x80,0xa9] +0xf0,0x02,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], -4.0, s[2:3] ; encoding: [0xf7,0x02,0x80,0xa9] +0xf7,0x02,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], 0x3f717273, s[2:3] ; encoding: [0xff,0x02,0x80,0xa9,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0xa9,0x73,0x72,0x71,0x3f + +# GFX12: s_add_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xff,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0xa9,0x56,0x34,0x12,0xaf + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0xa9] +0x02,0x7e,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0xa9] +0x02,0x6a,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0xa9] +0x02,0x80,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0xa9] +0x02,0xc1,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0xa9] +0x02,0xf0,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0xa9] +0x02,0xf7,0x80,0xa9 + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0xa9,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0xa9,0x73,0x72,0x71,0x3f + +# GFX12: s_add_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0xa9,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0xa9,0x56,0x34,0x12,0xaf + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x00,0xaa] +0x02,0x04,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[100:101], s[102:103], s[104:105] ; encoding: [0x66,0x68,0x64,0xaa] +0x66,0x68,0x64,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], s[104:105], s[102:103] ; encoding: [0x68,0x66,0x00,0xaa] +0x68,0x66,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[104:105], s[0:1], s[102:103] ; encoding: [0x00,0x66,0x68,0xaa] +0x00,0x66,0x68,0xaa + +# GFX12: s_sub_nc_u64 s[104:105], s[102:103], s[2:3] ; encoding: [0x66,0x02,0x68,0xaa] +0x66,0x02,0x68,0xaa + +# GFX12: s_sub_nc_u64 s[104:105], s[0:1], s[2:3] ; encoding: [0x00,0x02,0x68,0xaa] +0x00,0x02,0x68,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], s[102:103], s[2:3] ; encoding: [0x66,0x02,0x00,0xaa] +0x66,0x02,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], s[102:103] ; encoding: [0x02,0x66,0x00,0xaa] +0x02,0x66,0x00,0xaa + +# GFX12: s_sub_nc_u64 exec, s[0:1], s[2:3] ; encoding: [0x00,0x02,0x7e,0xaa] +0x00,0x02,0x7e,0xaa + +# GFX12: s_sub_nc_u64 vcc, s[0:1], s[2:3] ; encoding: [0x00,0x02,0x6a,0xaa] +0x00,0x02,0x6a,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], exec, s[2:3] ; encoding: [0x7e,0x02,0x00,0xaa] +0x7e,0x02,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], vcc, s[2:3] ; encoding: [0x6a,0x02,0x00,0xaa] +0x6a,0x02,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], 0, s[2:3] ; encoding: [0x80,0x02,0x00,0xaa] +0x80,0x02,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], -1, s[2:3] ; encoding: [0xc1,0x02,0x00,0xaa] +0xc1,0x02,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], 0.5, s[2:3] ; encoding: [0xf0,0x02,0x00,0xaa] +0xf0,0x02,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], -4.0, s[2:3] ; encoding: [0xf7,0x02,0x00,0xaa] +0xf7,0x02,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], 0x3f717273, s[2:3] ; encoding: [0xff,0x02,0x00,0xaa,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0xaa,0x73,0x72,0x71,0x3f + +# GFX12: s_sub_nc_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xff,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0xaa,0x56,0x34,0x12,0xaf + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x00,0xaa] +0x02,0x7e,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x00,0xaa +0x02,0x6a,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x00,0xaa] +0x02,0x80,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x00,0xaa] +0x02,0xc1,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x00,0xaa] +0x02,0xf0,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x00,0xaa] +0x02,0xf7,0x00,0xaa + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x00,0xaa,0x73,0x72,0x71,0x3f] +0x02,0xff,0x00,0xaa,0x73,0x72,0x71,0x3f + +# GFX12: s_sub_nc_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x00,0xaa,0x56,0x34,0x12,0xaf] +0x02,0xff,0x00,0xaa,0x56,0x34,0x12,0xaf + +# GFX12: s_mul_u64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0xaa] +0x02,0x04,0x80,0xaa + +# GFX12: s_mul_u64 s[100:101], s[102:103], s[104:105] ; encoding: [0x66,0x68,0xe4,0xaa] +0x66,0x68,0xe4,0xaa + +# GFX12: s_mul_u64 s[0:1], s[104:105], s[102:103] ; encoding: [0x68,0x66,0x80,0xaa] +0x68,0x66,0x80,0xaa + +# GFX12: s_mul_u64 s[104:105], s[0:1], s[102:103] ; encoding: [0x00,0x66,0xe8,0xaa] +0x00,0x66,0xe8,0xaa + +# GFX12: s_mul_u64 s[104:105], s[102:103], s[2:3] ; encoding: [0x66,0x02,0xe8,0xaa] +0x66,0x02,0xe8,0xaa + +# GFX12: s_mul_u64 s[104:105], s[0:1], s[2:3] ; encoding: [0x00,0x02,0xe8,0xaa] +0x00,0x02,0xe8,0xaa + +# GFX12: s_mul_u64 s[0:1], s[102:103], s[2:3] ; encoding: [0x66,0x02,0x80,0xaa] +0x66,0x02,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], s[2:3], s[102:103] ; encoding: [0x02,0x66,0x80,0xaa] +0x02,0x66,0x80,0xaa + +# GFX12: s_mul_u64 exec, s[0:1], s[2:3] ; encoding: [0x00,0x02,0xfe,0xaa] +0x00,0x02,0xfe,0xaa + +# GFX12: s_mul_u64 vcc, s[0:1], s[2:3] ; encoding: [0x00,0x02,0xea,0xaa] +0x00,0x02,0xea,0xaa + +# GFX12: s_mul_u64 s[0:1], exec, s[2:3] ; encoding: [0x7e,0x02,0x80,0xaa] +0x7e,0x02,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], vcc, s[2:3] ; encoding: [0x6a,0x02,0x80,0xaa] +0x6a,0x02,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], 0, s[2:3] ; encoding: [0x80,0x02,0x80,0xaa] +0x80,0x02,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], -1, s[2:3] ; encoding: [0xc1,0x02,0x80,0xaa] +0xc1,0x02,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], 0.5, s[2:3] ; encoding: [0xf0,0x02,0x80,0xaa] +0xf0,0x02,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], -4.0, s[2:3] ; encoding: [0xf7,0x02,0x80,0xaa] +0xf7,0x02,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], 0x3f717273, s[2:3] ; encoding: [0xff,0x02,0x80,0xaa,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0xaa,0x73,0x72,0x71,0x3f + +# GFX12: s_mul_u64 s[0:1], 0xaf123456, s[2:3] ; encoding: [0xff,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0xaa,0x56,0x34,0x12,0xaf + +# GFX12: s_mul_u64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0xaa] +0x02,0x7e,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0xaa] +0x02,0x6a,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0xaa] +0x02,0x80,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0xaa] +0x02,0xc1,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0xaa] +0x02,0xf0,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0xaa] +0x02,0xf7,0x80,0xaa + +# GFX12: s_mul_u64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0xaa,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0xaa,0x73,0x72,0x71,0x3f + +# GFX12: s_mul_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0xaa,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0xaa,0x56,0x34,0x12,0xaf + +# GFX12: s_add_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa0] +0x01,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa0] +0x01,0x02,0x69,0xa0 + +# GFX12: s_add_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa0] +0x69,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, s101, s2 ; encoding: [0x65,0x02,0x05,0xa0] +0x65,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa0] +0x6a,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa0] +0x6b,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa0] +0x7d,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa0] +0x7e,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa0] +0x7f,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa0] +0x80,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, -1, s2 ; encoding: [0xc1,0x02,0x05,0xa0] +0xc1,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x05,0xa0] +0xf0,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x05,0xa0] +0xf7,0x02,0x05,0xa0 + +# GFX12: s_add_f32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x05,0xa0,0x56,0x34,0x12,0xaf] +0xff,0x02,0x05,0xa0,0x56,0x34,0x12,0xaf + +# GFX12: s_add_f32 s5, 0x3f717273, s2 ; encoding: [0xff,0x02,0x05,0xa0,0x73,0x72,0x71,0x3f] +0xff,0x02,0x05,0xa0,0x73,0x72,0x71,0x3f + +# GFX12: s_add_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x05,0xa0] +0x01,0x69,0x05,0xa0 + +# GFX12: s_sub_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0xa0] +0x01,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0xa0] +0x01,0x02,0xe9,0xa0 + +# GFX12: s_sub_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x85,0xa0] +0x69,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, s101, s2 ; encoding: [0x65,0x02,0x85,0xa0] +0x65,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x85,0xa0] +0x6a,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x85,0xa0] +0x6b,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x85,0xa0] +0x7d,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x85,0xa0] +0x7e,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x85,0xa0] +0x7f,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x85,0xa0] +0x80,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, -1, s2 ; encoding: [0xc1,0x02,0x85,0xa0] +0xc1,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x85,0xa0] +0xf0,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x85,0xa0] +0xf7,0x02,0x85,0xa0 + +# GFX12: s_sub_f32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x85,0xa0,0x56,0x34,0x12,0xaf] +0xff,0x02,0x85,0xa0,0x56,0x34,0x12,0xaf + +# GFX12: s_sub_f32 s5, 0x3f717273, s2 ; encoding: [0xff,0x02,0x85,0xa0,0x73,0x72,0x71,0x3f] +0xff,0x02,0x85,0xa0,0x73,0x72,0x71,0x3f + +# GFX12: s_sub_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa0] +0x01,0x69,0x85,0xa0 + +# GFX12: s_mul_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa2] +0x01,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa2] +0x01,0x02,0x69,0xa2 + +# GFX12: s_mul_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa2] +0x69,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, s103, s2 ; encoding: [0x67,0x02,0x05,0xa2] +0x67,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa2] +0x6a,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa2] +0x6b,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, ttmp11, s2 ; encoding: [0x77,0x02,0x05,0xa2] +0x77,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa2] +0x7d,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa2] +0x7e,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa2] +0x7f,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa2] +0x80,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, -1, s2 ; encoding: [0xc1,0x02,0x05,0xa2] +0xc1,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x05,0xa2] +0xf0,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x05,0xa2] +0xf7,0x02,0x05,0xa2 + +# GFX12: s_mul_f32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x05,0xa2,0x56,0x34,0x12,0xaf] +0xff,0x02,0x05,0xa2,0x56,0x34,0x12,0xaf + +# GFX12: s_mul_f32 s5, 0x3f717273, s2 ; encoding: [0xff,0x02,0x05,0xa2,0x73,0x72,0x71,0x3f] +0xff,0x02,0x05,0xa2,0x73,0x72,0x71,0x3f + +# GFX12: s_mul_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x05,0xa2] +0x01,0x69,0x05,0xa2 + +# GFX12: s_min_num_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa1] +0x01,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa1] +0x01,0x02,0x69,0xa1 + +# GFX12: s_min_num_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa1] +0x69,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, s103, s2 ; encoding: [0x67,0x02,0x05,0xa1] +0x67,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa1] +0x6a,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa1] +0x6b,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, ttmp11, s2 ; encoding: [0x77,0x02,0x05,0xa1] +0x77,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa1] +0x7d,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa1] +0x7e,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa1] +0x7f,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa1] +0x80,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, -1, s2 ; encoding: [0xc1,0x02,0x05,0xa1] +0xc1,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x05,0xa1] +0xf0,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x05,0xa1] +0xf7,0x02,0x05,0xa1 + +# GFX12: s_min_num_f32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x05,0xa1,0x56,0x34,0x12,0xaf] +0xff,0x02,0x05,0xa1,0x56,0x34,0x12,0xaf + +# GFX12: s_min_num_f32 s5, 0x3f717273, s2 ; encoding: [0xff,0x02,0x05,0xa1,0x73,0x72,0x71,0x3f] +0xff,0x02,0x05,0xa1,0x73,0x72,0x71,0x3f + +# GFX12: s_min_num_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x05,0xa1] +0x01,0x69,0x05,0xa1 + +# GFX12: s_max_num_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0xa1] +0x01,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0xa1] +0x01,0x02,0xe9,0xa1 + +# GFX12: s_max_num_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x85,0xa1] +0x69,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, s103, s2 ; encoding: [0x67,0x02,0x85,0xa1] +0x67,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x85,0xa1] +0x6a,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x85,0xa1] +0x6b,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, ttmp11, s2 ; encoding: [0x77,0x02,0x85,0xa1] +0x77,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x85,0xa1] +0x7d,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x85,0xa1] +0x7e,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x85,0xa1] +0x7f,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x85,0xa1] +0x80,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, -1, s2 ; encoding: [0xc1,0x02,0x85,0xa1] +0xc1,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x85,0xa1] +0xf0,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x85,0xa1] +0xf7,0x02,0x85,0xa1 + +# GFX12: s_max_num_f32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x85,0xa1,0x56,0x34,0x12,0xaf] +0xff,0x02,0x85,0xa1,0x56,0x34,0x12,0xaf + +# GFX12: s_max_num_f32 s5, 0x3f717273, s2 ; encoding: [0xff,0x02,0x85,0xa1,0x73,0x72,0x71,0x3f] +0xff,0x02,0x85,0xa1,0x73,0x72,0x71,0x3f + +# GFX12: s_max_num_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa1] +0x01,0x69,0x85,0xa1 + +# GFX12: s_fmac_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0xa3] +0x01,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0xa3] +0x01,0x02,0xe9,0xa3 + +# GFX12: s_fmac_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x85,0xa3] +0x69,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, s103, s2 ; encoding: [0x67,0x02,0x85,0xa3] +0x67,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x85,0xa3] +0x6a,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x85,0xa3] +0x6b,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, ttmp11, s2 ; encoding: [0x77,0x02,0x85,0xa3] +0x77,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x85,0xa3] +0x7d,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x85,0xa3] +0x7e,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x85,0xa3] +0x7f,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x85,0xa3] +0x80,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, -1, s2 ; encoding: [0xc1,0x02,0x85,0xa3] +0xc1,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x85,0xa3] +0xf0,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x85,0xa3] +0xf7,0x02,0x85,0xa3 + +# GFX12: s_fmac_f32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x85,0xa3,0x56,0x34,0x12,0xaf] +0xff,0x02,0x85,0xa3,0x56,0x34,0x12,0xaf + +# GFX12: s_fmac_f32 s5, 0x3f717273, s2 ; encoding: [0xff,0x02,0x85,0xa3,0x73,0x72,0x71,0x3f] +0xff,0x02,0x85,0xa3,0x73,0x72,0x71,0x3f + +# GFX12: s_fmac_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa3] +0x01,0x69,0x85,0xa3 + +# GFX12: s_fmamk_f32 s5, s1, 0x11213141, s3 ; encoding: [0x01,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] +0x01,0x03,0x05,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmamk_f32 s105, s1, 0x11213141, s3 ; encoding: [0x01,0x03,0x69,0xa3,0x41,0x31,0x21,0x11] +0x01,0x03,0x69,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmamk_f32 s5, s105, 0x11213141, s3 ; encoding: [0x69,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] +0x69,0x03,0x05,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmamk_f32 s5, 0, 0x11213141, s3 ; encoding: [0x80,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] +0x80,0x03,0x05,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmamk_f32 s5, -1, 0x11213141, s3 ; encoding: [0xc1,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] +0xc1,0x03,0x05,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmamk_f32 s5, 0.5, 0x11213141, s3 ; encoding: [0xf0,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] +0xf0,0x03,0x05,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmamk_f32 s5, -4.0, 0x11213141, s3 ; encoding: [0xf7,0x03,0x05,0xa3,0x41,0x31,0x21,0x11] +0xf7,0x03,0x05,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmamk_f32 s5, s1, 0xa1b1c1d1, s3 ; encoding: [0x01,0x03,0x05,0xa3,0xd1,0xc1,0xb1,0xa1] +0x01,0x03,0x05,0xa3,0xd1,0xc1,0xb1,0xa1 + +# GFX12: s_fmamk_f32 s5, s1, 0x11213141, s105 ; encoding: [0x01,0x69,0x05,0xa3,0x41,0x31,0x21,0x11] +0x01,0x69,0x05,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmamk_f32 s5, 0x11213141, 0x11213141, s105 ; encoding: [0xff,0x69,0x05,0xa3,0x41,0x31,0x21,0x11] +0xff,0x69,0x05,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmamk_f32 s5, s105, 0x11213141, 0x11213141 ; encoding: [0x69,0xff,0x05,0xa3,0x41,0x31,0x21,0x11] +0x69,0xff,0x05,0xa3,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, 0x11213141, 0x11213141, 0x11213141 ; encoding: [0xff,0xff,0x85,0xa2,0x41,0x31,0x21,0x11] +0xff,0xff,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, s1, s2, 0x11213141 ; encoding: [0x01,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] +0x01,0x02,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s105, s1, s2, 0x11213141 ; encoding: [0x01,0x02,0xe9,0xa2,0x41,0x31,0x21,0x11] +0x01,0x02,0xe9,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, s105, s2, 0x11213141 ; encoding: [0x69,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] +0x69,0x02,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, 0, s2, 0x11213141 ; encoding: [0x80,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] +0x80,0x02,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, -1, s2, 0x11213141 ; encoding: [0xc1,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] +0xc1,0x02,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, 0.5, s2, 0x11213141 ; encoding: [0xf0,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] +0xf0,0x02,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, -4.0, s2, 0x11213141 ; encoding: [0xf7,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] +0xf7,0x02,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, s1, s105, 0x11213141 ; encoding: [0x01,0x69,0x85,0xa2,0x41,0x31,0x21,0x11] +0x01,0x69,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, s1, s2, 0xa1b1c1d1 ; encoding: [0x01,0x02,0x85,0xa2,0xd1,0xc1,0xb1,0xa1] +0x01,0x02,0x85,0xa2,0xd1,0xc1,0xb1,0xa1 + +# GFX12: s_fmaak_f32 s5, 0x11213141, s2, 0x11213141 ; encoding: [0xff,0x02,0x85,0xa2,0x41,0x31,0x21,0x11] +0xff,0x02,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_fmaak_f32 s5, s105, 0x11213141, 0x11213141 ; encoding: [0x69,0xff,0x85,0xa2,0x41,0x31,0x21,0x11] +0x69,0xff,0x85,0xa2,0x41,0x31,0x21,0x11 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa4] +0x01,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa4] +0x01,0x02,0x69,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa4] +0x69,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, s103, s2 ; encoding: [0x67,0x02,0x05,0xa4] +0x67,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa4] +0x6a,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa4] +0x6b,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, ttmp11, s2 ; encoding: [0x77,0x02,0x05,0xa4] +0x77,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa4] +0x7d,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa4] +0x7e,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa4] +0x7f,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa4] +0x80,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, -1, s2 ; encoding: [0xc1,0x02,0x05,0xa4] +0xc1,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x05,0xa4] +0xf0,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x05,0xa4] +0xf7,0x02,0x05,0xa4 + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x05,0xa4,0x56,0x34,0x12,0xaf] +0xff,0x02,0x05,0xa4,0x56,0x34,0x12,0xaf + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, 0x3f717273, s2 ; encoding: [0xff,0x02,0x05,0xa4,0x73,0x72,0x71,0x3f] +0xff,0x02,0x05,0xa4,0x73,0x72,0x71,0x3f + +# GFX12: s_cvt_pk_rtz_f16_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x05,0xa4] +0x01,0x69,0x05,0xa4 + +# GFX12: s_add_f16 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0xa4] +0x01,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0xa4] +0x01,0x02,0xe9,0xa4 + +# GFX12: s_add_f16 s5, s105, s2 ; encoding: [0x69,0x02,0x85,0xa4] +0x69,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, s101, s2 ; encoding: [0x65,0x02,0x85,0xa4] +0x65,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x85,0xa4] +0x6a,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x85,0xa4] +0x6b,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, m0, s2 ; encoding: [0x7d,0x02,0x85,0xa4] +0x7d,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x85,0xa4] +0x7e,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x85,0xa4] +0x7f,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, 0, s2 ; encoding: [0x80,0x02,0x85,0xa4] +0x80,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, -1, s2 ; encoding: [0xc1,0x02,0x85,0xa4] +0xc1,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x85,0xa4] +0xf0,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x85,0xa4] +0xf7,0x02,0x85,0xa4 + +# GFX12: s_add_f16 s5, 0xfe0b, s2 ; encoding: [0xff,0x02,0x85,0xa4,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x85,0xa4,0x0b,0xfe,0x00,0x00 + +# GFX12: s_add_f16 s5, 0x3456, s2 ; encoding: [0xff,0x02,0x85,0xa4,0x56,0x34,0x00,0x00] +0xff,0x02,0x85,0xa4,0x56,0x34,0x00,0x00 + +# GFX12: s_add_f16 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa4] +0x01,0x69,0x85,0xa4 + +# GFX12: s_sub_f16 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa5] +0x01,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa5] +0x01,0x02,0x69,0xa5 + +# GFX12: s_sub_f16 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa5] +0x69,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, s101, s2 ; encoding: [0x65,0x02,0x05,0xa5] +0x65,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa5] +0x6a,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa5] +0x6b,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa5] +0x7d,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa5] +0x7e,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa5] +0x7f,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa5] +0x80,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, -1, s2 ; encoding: [0xc1,0x02,0x05,0xa5] +0xc1,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x05,0xa5] +0xf0,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x05,0xa5] +0xf7,0x02,0x05,0xa5 + +# GFX12: s_sub_f16 s5, 0xfe0b, s2 ; encoding: [0xff,0x02,0x05,0xa5,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x05,0xa5,0x0b,0xfe,0x00,0x00 + +# GFX12: s_sub_f16 s5, 0x3456, s2 ; encoding: [0xff,0x02,0x05,0xa5,0x56,0x34,0x00,0x00] +0xff,0x02,0x05,0xa5,0x56,0x34,0x00,0x00 + +# GFX12: s_sub_f16 s5, s1, s105 ; encoding: [0x01,0x69,0x05,0xa5] +0x01,0x69,0x05,0xa5 + +# GFX12: s_mul_f16 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0xa6] +0x01,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0xa6] +0x01,0x02,0xe9,0xa6 + +# GFX12: s_mul_f16 s5, s105, s2 ; encoding: [0x69,0x02,0x85,0xa6] +0x69,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, s101, s2 ; encoding: [0x65,0x02,0x85,0xa6] +0x65,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x85,0xa6] +0x6a,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x85,0xa6] +0x6b,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, m0, s2 ; encoding: [0x7d,0x02,0x85,0xa6] +0x7d,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x85,0xa6] +0x7e,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x85,0xa6] +0x7f,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, 0, s2 ; encoding: [0x80,0x02,0x85,0xa6] +0x80,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, -1, s2 ; encoding: [0xc1,0x02,0x85,0xa6] +0xc1,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x85,0xa6] +0xf0,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x85,0xa6] +0xf7,0x02,0x85,0xa6 + +# GFX12: s_mul_f16 s5, 0xfe0b, s2 ; encoding: [0xff,0x02,0x85,0xa6,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x85,0xa6,0x0b,0xfe,0x00,0x00 + +# GFX12: s_mul_f16 s5, 0x3456, s2 ; encoding: [0xff,0x02,0x85,0xa6,0x56,0x34,0x00,0x00] +0xff,0x02,0x85,0xa6,0x56,0x34,0x00,0x00 + +# GFX12: s_mul_f16 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa6] +0x01,0x69,0x85,0xa6 + +# GFX12: s_fmac_f16 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa7] +0x01,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa7] +0x01,0x02,0x69,0xa7 + +# GFX12: s_fmac_f16 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa7] +0x69,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, s103, s2 ; encoding: [0x67,0x02,0x05,0xa7] +0x67,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa7] +0x6a,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa7] +0x6b,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, ttmp11, s2 ; encoding: [0x77,0x02,0x05,0xa7] +0x77,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa7] +0x7d,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa7] +0x7e,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa7] +0x7f,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa7] +0x80,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, -1, s2 ; encoding: [0xc1,0x02,0x05,0xa7] +0xc1,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x05,0xa7] +0xf0,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x05,0xa7] +0xf7,0x02,0x05,0xa7 + +# GFX12: s_fmac_f16 s5, 0x1234, s2 ; encoding: [0xff,0x02,0x05,0xa7,0x34,0x12,0x00,0x00] +0xff,0x02,0x05,0xa7,0x34,0x12,0x00,0x00 + +# GFX12: s_fmac_f16 s5, s1, s105 ; encoding: [0x01,0x69,0x05,0xa7] +0x01,0x69,0x05,0xa7 + +# GFX12: s_max_num_f16 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa6] +0x01,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa6] +0x01,0x02,0x69,0xa6 + +# GFX12: s_max_num_f16 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa6] +0x69,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, s101, s2 ; encoding: [0x65,0x02,0x05,0xa6] +0x65,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa6] +0x6a,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa6] +0x6b,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa6] +0x7d,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa6] +0x7e,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa6] +0x7f,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa6] +0x80,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, -1, s2 ; encoding: [0xc1,0x02,0x05,0xa6] +0xc1,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x05,0xa6] +0xf0,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x05,0xa6] +0xf7,0x02,0x05,0xa6 + +# GFX12: s_max_num_f16 s5, 0xfe0b, s2 ; encoding: [0xff,0x02,0x05,0xa6,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x05,0xa6,0x0b,0xfe,0x00,0x00 + +# GFX12: s_max_num_f16 s5, 0x3456, s2 ; encoding: [0xff,0x02,0x05,0xa6,0x56,0x34,0x00,0x00] +0xff,0x02,0x05,0xa6,0x56,0x34,0x00,0x00 + +# GFX12: s_max_num_f16 s5, s1, s105 ; encoding: [0x01,0x69,0x05,0xa6] +0x01,0x69,0x05,0xa6 + +# GFX12: s_min_num_f16 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0xa5] +0x01,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0xa5] +0x01,0x02,0xe9,0xa5 + +# GFX12: s_min_num_f16 s5, s105, s2 ; encoding: [0x69,0x02,0x85,0xa5] +0x69,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, s101, s2 ; encoding: [0x65,0x02,0x85,0xa5] +0x65,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x85,0xa5] +0x6a,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x85,0xa5] +0x6b,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, m0, s2 ; encoding: [0x7d,0x02,0x85,0xa5] +0x7d,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x85,0xa5] +0x7e,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x85,0xa5] +0x7f,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, 0, s2 ; encoding: [0x80,0x02,0x85,0xa5] +0x80,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, -1, s2 ; encoding: [0xc1,0x02,0x85,0xa5] +0xc1,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x85,0xa5] +0xf0,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x85,0xa5] +0xf7,0x02,0x85,0xa5 + +# GFX12: s_min_num_f16 s5, 0xfe0b, s2 ; encoding: [0xff,0x02,0x85,0xa5,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x85,0xa5,0x0b,0xfe,0x00,0x00 + +# GFX12: s_min_num_f16 s5, 0x3456, s2 ; encoding: [0xff,0x02,0x85,0xa5,0x56,0x34,0x00,0x00] +0xff,0x02,0x85,0xa5,0x56,0x34,0x00,0x00 + +# GFX12: s_min_num_f16 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa5] +0x01,0x69,0x85,0xa5 + +# GFX12: s_absdiff_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x83] +0x01,0x02,0x7f,0x83 + +# GFX12: s_absdiff_i32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x83] +0x01,0x02,0x7e,0x83 + +# GFX12: s_absdiff_i32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x83] +0x01,0x02,0x7d,0x83 + +# GFX12: s_absdiff_i32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x83] +0xf0,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x83] +0x80,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x83,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x83,0x73,0x72,0x71,0x3f + +# GFX12: s_absdiff_i32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x83,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x83,0x56,0x34,0x12,0xaf + +# GFX12: s_absdiff_i32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x83] +0xc1,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x83] +0xf7,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x83] +0x7f,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x83] +0x7e,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x83] +0x7d,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x83] +0x68,0x67,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x83] +0x68,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x83] +0x01,0xf0,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x83] +0x01,0x80,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x83,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x83,0x73,0x72,0x71,0x3f + +# GFX12: s_absdiff_i32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x83,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x83,0x56,0x34,0x12,0xaf + +# GFX12: s_absdiff_i32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x83] +0x01,0xc1,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x83] +0x01,0xf7,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x83] +0x01,0x7f,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x83] +0x01,0x7e,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x83] +0x01,0x7d,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x83] +0x01,0x67,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x83] +0x01,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x83] +0x01,0x6b,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x83] +0x01,0x6a,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x83] +0x6b,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x83] +0x6a,0x02,0x00,0x83 + +# GFX12: s_absdiff_i32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x83] +0x68,0x67,0x69,0x83 + +# GFX12: s_absdiff_i32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x83] +0x68,0x02,0x69,0x83 + +# GFX12: s_absdiff_i32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x83] +0x01,0x67,0x69,0x83 + +# GFX12: s_absdiff_i32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x83] +0x01,0x02,0x69,0x83 + +# GFX12: s_absdiff_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x83] +0x01,0x02,0x6b,0x83 + +# GFX12: s_absdiff_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x83] +0x01,0x02,0x6a,0x83 + +# GFX12: s_add_co_ci_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x82] +0x01,0x02,0x7f,0x82 + +# GFX12: s_add_co_ci_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x82] +0x01,0x02,0x7e,0x82 + +# GFX12: s_add_co_ci_u32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x82] +0x01,0x02,0x7d,0x82 + +# GFX12: s_add_co_ci_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x82] +0xf0,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x82] +0x80,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x82,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x82,0x73,0x72,0x71,0x3f + +# GFX12: s_add_co_ci_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x82,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x82,0x56,0x34,0x12,0xaf + +# GFX12: s_add_co_ci_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x82] +0xc1,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x82] +0xf7,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x82] +0x7f,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x82] +0x7e,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x82] +0x7d,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x82] +0x68,0x67,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x82] +0x68,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x82] +0x01,0xf0,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x82] +0x01,0x80,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x82,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x82,0x73,0x72,0x71,0x3f + +# GFX12: s_add_co_ci_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x82,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x82,0x56,0x34,0x12,0xaf + +# GFX12: s_add_co_ci_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x82] +0x01,0xc1,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x82] +0x01,0xf7,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x82] +0x01,0x7f,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x82] +0x01,0x7e,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x82] +0x01,0x7d,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x82] +0x01,0x67,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x82] +0x01,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x82] +0x01,0x6b,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x82] +0x01,0x6a,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x82] +0x6b,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x82] +0x6a,0x02,0x00,0x82 + +# GFX12: s_add_co_ci_u32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x82] +0x68,0x67,0x69,0x82 + +# GFX12: s_add_co_ci_u32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x82] +0x68,0x02,0x69,0x82 + +# GFX12: s_add_co_ci_u32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x82] +0x01,0x67,0x69,0x82 + +# GFX12: s_add_co_ci_u32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x82] +0x01,0x02,0x69,0x82 + +# GFX12: s_add_co_ci_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x82] +0x01,0x02,0x6b,0x82 + +# GFX12: s_add_co_ci_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x82] +0x01,0x02,0x6a,0x82 + +# GFX12: s_add_co_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x81] +0x01,0x02,0x7f,0x81 + +# GFX12: s_add_co_i32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x81] +0x01,0x02,0x7e,0x81 + +# GFX12: s_add_co_i32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x81] +0x01,0x02,0x7d,0x81 + +# GFX12: s_add_co_i32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x81] +0xf0,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x81] +0x80,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x81,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x81,0x73,0x72,0x71,0x3f + +# GFX12: s_add_co_i32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x81,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x81,0x56,0x34,0x12,0xaf + +# GFX12: s_add_co_i32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x81] +0xc1,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x81] +0xf7,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x81] +0x7f,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x81] +0x7e,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x81] +0x7d,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x81] +0x68,0x67,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x81] +0x68,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x81] +0x01,0xf0,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x81] +0x01,0x80,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x81,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x81,0x73,0x72,0x71,0x3f + +# GFX12: s_add_co_i32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x81,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x81,0x56,0x34,0x12,0xaf + +# GFX12: s_add_co_i32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x81] +0x01,0xc1,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x81] +0x01,0xf7,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x81] +0x01,0x7f,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x81] +0x01,0x7e,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x81] +0x01,0x7d,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x81] +0x01,0x67,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x81] +0x01,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x81] +0x01,0x6b,0x00,0x81 + +# GFX12: s_add_co_i32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x81] +0x01,0x6a,0x00,0x81 + +# GFX12: s_add_co_i32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x81] +0x6b,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x81] +0x6a,0x02,0x00,0x81 + +# GFX12: s_add_co_i32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x81] +0x68,0x67,0x69,0x81 + +# GFX12: s_add_co_i32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x81] +0x68,0x02,0x69,0x81 + +# GFX12: s_add_co_i32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x81] +0x01,0x67,0x69,0x81 + +# GFX12: s_add_co_i32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x81] +0x01,0x02,0x69,0x81 + +# GFX12: s_add_co_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x81] +0x01,0x02,0x6b,0x81 + +# GFX12: s_add_co_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x81] +0x01,0x02,0x6a,0x81 + +# GFX12: s_add_co_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x80] +0x01,0x02,0x7f,0x80 + +# GFX12: s_add_co_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x80] +0x01,0x02,0x7e,0x80 + +# GFX12: s_add_co_u32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x80] +0x01,0x02,0x7d,0x80 + +# GFX12: s_add_co_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x80] +0xf0,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x80] +0x80,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x80,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x80,0x73,0x72,0x71,0x3f + +# GFX12: s_add_co_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x80,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x80,0x56,0x34,0x12,0xaf + +# GFX12: s_add_co_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x80] +0xc1,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x80] +0xf7,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x80] +0x7f,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x80] +0x7e,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x80] +0x7d,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x80] +0x68,0x67,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x80] +0x68,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x80] +0x01,0xf0,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x80] +0x01,0x80,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x80,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x80,0x73,0x72,0x71,0x3f + +# GFX12: s_add_co_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x80,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x80,0x56,0x34,0x12,0xaf + +# GFX12: s_add_co_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x80] +0x01,0xc1,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x80] +0x01,0xf7,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x80] +0x01,0x7f,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x80] +0x01,0x7e,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x80] +0x01,0x7d,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x80] +0x01,0x67,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x80] +0x01,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x80] +0x01,0x6b,0x00,0x80 + +# GFX12: s_add_co_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x80] +0x01,0x6a,0x00,0x80 + +# GFX12: s_add_co_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x80] +0x6b,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x80] +0x6a,0x02,0x00,0x80 + +# GFX12: s_add_co_u32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x80] +0x68,0x67,0x69,0x80 + +# GFX12: s_add_co_u32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x80] +0x68,0x02,0x69,0x80 + +# GFX12: s_add_co_u32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x80] +0x01,0x67,0x69,0x80 + +# GFX12: s_add_co_u32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x80] +0x01,0x02,0x69,0x80 + +# GFX12: s_add_co_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x80] +0x01,0x02,0x6b,0x80 + +# GFX12: s_add_co_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x80] +0x01,0x02,0x6a,0x80 + +# GFX12: s_and_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x8b] +0x01,0x02,0x7f,0x8b + +# GFX12: s_and_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x8b] +0x01,0x02,0x7e,0x8b + +# GFX12: s_and_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x8b] +0x01,0x02,0x7d,0x8b + +# GFX12: s_and_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x8b] +0xf0,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x8b] +0x80,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x8b,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x8b,0x73,0x72,0x71,0x3f + +# GFX12: s_and_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x8b,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x8b,0x56,0x34,0x12,0xaf + +# GFX12: s_and_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x8b] +0xc1,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x8b] +0xf7,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x8b] +0x7f,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x8b] +0x7e,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x8b] +0x7d,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x8b] +0x68,0x67,0x00,0x8b + +# GFX12: s_and_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x8b] +0x68,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x8b] +0x01,0xf0,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x8b] +0x01,0x80,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x8b,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x8b,0x73,0x72,0x71,0x3f + +# GFX12: s_and_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x8b,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x8b,0x56,0x34,0x12,0xaf + +# GFX12: s_and_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x8b] +0x01,0xc1,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x8b] +0x01,0xf7,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x8b] +0x01,0x7f,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x8b] +0x01,0x7e,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x8b] +0x01,0x7d,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x8b] +0x01,0x67,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8b] +0x01,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x8b] +0x01,0x6b,0x00,0x8b + +# GFX12: s_and_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x8b] +0x01,0x6a,0x00,0x8b + +# GFX12: s_and_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x8b] +0x6b,0x02,0x00,0x8b + +# GFX12: s_and_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x8b] +0x6a,0x02,0x00,0x8b + +# GFX12: s_and_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x8b] +0x68,0x67,0x69,0x8b + +# GFX12: s_and_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x8b] +0x68,0x02,0x69,0x8b + +# GFX12: s_and_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x8b] +0x01,0x67,0x69,0x8b + +# GFX12: s_and_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x8b] +0x01,0x02,0x69,0x8b + +# GFX12: s_and_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x8b] +0x01,0x02,0x6b,0x8b + +# GFX12: s_and_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x8b] +0x01,0x02,0x6a,0x8b + +# GFX12: s_and_b32 s0, s1, null ; encoding: [0x01,0x7c,0x00,0x8b] +0x01,0x7c,0x00,0x8b + +# GFX12: s_and_b32 s0, null, s2 ; encoding: [0x7c,0x02,0x00,0x8b] +0x7c,0x02,0x00,0x8b + +# GFX12: s_and_b32 null, s1, s2 ; encoding: [0x01,0x02,0x7c,0x8b] +0x01,0x02,0x7c,0x8b + +# GFX12: s_and_b64 exec, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xfe,0x8b] +0x02,0x04,0xfe,0x8b + +# GFX12: s_and_b64 s[0:1], 0.5, s[4:5] ; encoding: [0xf0,0x04,0x80,0x8b] +0xf0,0x04,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], 0, s[4:5] ; encoding: [0x80,0x04,0x80,0x8b] +0x80,0x04,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], 0x3f717273, s[4:5] ; encoding: [0xff,0x04,0x80,0x8b,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x8b,0x73,0x72,0x71,0x3f + +# GFX12: s_and_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf + +# GFX12: s_and_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8b] +0xc1,0x04,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], -4.0, s[4:5] ; encoding: [0xf7,0x04,0x80,0x8b] +0xf7,0x04,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], exec, s[4:5] ; encoding: [0x7e,0x04,0x80,0x8b] +0x7e,0x04,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[102:103], s[100:101] ; encoding: [0x66,0x64,0x80,0x8b] +0x66,0x64,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[102:103], s[4:5] ; encoding: [0x66,0x04,0x80,0x8b] +0x66,0x04,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x8b] +0x02,0xf0,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x8b] +0x02,0x80,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x8b,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x8b,0x73,0x72,0x71,0x3f + +# GFX12: s_and_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8b,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x8b,0x56,0x34,0x12,0xaf + +# GFX12: s_and_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8b] +0x02,0xc1,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x8b] +0x02,0xf7,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8b] +0x02,0x7e,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[2:3], s[100:101] ; encoding: [0x02,0x64,0x80,0x8b] +0x02,0x64,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0x8b] +0x02,0x04,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0x8b] +0x02,0x6a,0x80,0x8b + +# GFX12: s_and_b64 s[0:1], vcc, s[4:5] ; encoding: [0x6a,0x04,0x80,0x8b] +0x6a,0x04,0x80,0x8b + +# GFX12: s_and_b64 s[104:105], s[102:103], s[100:101] ; encoding: [0x66,0x64,0xe8,0x8b] +0x66,0x64,0xe8,0x8b + +# GFX12: s_and_b64 s[104:105], s[102:103], s[4:5] ; encoding: [0x66,0x04,0xe8,0x8b] +0x66,0x04,0xe8,0x8b + +# GFX12: s_and_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x8b] +0x02,0x64,0xe8,0x8b + +# GFX12: s_and_b64 s[104:105], s[2:3], s[4:5] ; encoding: [0x02,0x04,0xe8,0x8b] +0x02,0x04,0xe8,0x8b + +# GFX12: s_and_b64 vcc, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xea,0x8b] +0x02,0x04,0xea,0x8b + +# GFX12: s_and_not1_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x91] +0x01,0x02,0x7f,0x91 + +# GFX12: s_and_not1_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x91] +0x01,0x02,0x7e,0x91 + +# GFX12: s_and_not1_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x91] +0x01,0x02,0x7d,0x91 + +# GFX12: s_and_not1_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x91] +0xf0,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x91] +0x80,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x91,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x91,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not1_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x91,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x91,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not1_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x91] +0xc1,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x91] +0xf7,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x91] +0x7f,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x91] +0x7e,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x91] +0x7d,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x91] +0x68,0x67,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x91] +0x68,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x91] +0x01,0xf0,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x91] +0x01,0x80,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x91,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x91,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not1_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x91,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x91,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not1_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x91] +0x01,0xc1,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x91] +0x01,0xf7,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x91] +0x01,0x7f,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x91] +0x01,0x7e,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x91] +0x01,0x7d,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x91] +0x01,0x67,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x91] +0x01,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x91] +0x01,0x6b,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x91] +0x01,0x6a,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x91] +0x6b,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x91] +0x6a,0x02,0x00,0x91 + +# GFX12: s_and_not1_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x91] +0x68,0x67,0x69,0x91 + +# GFX12: s_and_not1_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x91] +0x68,0x02,0x69,0x91 + +# GFX12: s_and_not1_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x91] +0x01,0x67,0x69,0x91 + +# GFX12: s_and_not1_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x91] +0x01,0x02,0x69,0x91 + +# GFX12: s_and_not1_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x91] +0x01,0x02,0x6b,0x91 + +# GFX12: s_and_not1_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x91] +0x01,0x02,0x6a,0x91 + +# GFX12: s_and_not1_b64 exec, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xfe,0x91] +0x02,0x04,0xfe,0x91 + +# GFX12: s_and_not1_b64 s[0:1], 0.5, s[4:5] ; encoding: [0xf0,0x04,0x80,0x91] +0xf0,0x04,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], 0, s[4:5] ; encoding: [0x80,0x04,0x80,0x91] +0x80,0x04,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], 0x3f717273, s[4:5] ; encoding: [0xff,0x04,0x80,0x91,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x91,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x91,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x91,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not1_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x91] +0xc1,0x04,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], -4.0, s[4:5] ; encoding: [0xf7,0x04,0x80,0x91] +0xf7,0x04,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], exec, s[4:5] ; encoding: [0x7e,0x04,0x80,0x91] +0x7e,0x04,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[102:103], s[100:101] ; encoding: [0x66,0x64,0x80,0x91] +0x66,0x64,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[102:103], s[4:5] ; encoding: [0x66,0x04,0x80,0x91] +0x66,0x04,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x91] +0x02,0xf0,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x91] +0x02,0x80,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x91,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x91,0x73,0x72,0x71,0x3f + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x91,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x91,0x56,0x34,0x12,0xaf + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x91] +0x02,0xc1,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x91] +0x02,0xf7,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x91] +0x02,0x7e,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], s[100:101] ; encoding: [0x02,0x64,0x80,0x91] +0x02,0x64,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0x91] +0x02,0x04,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0x91] +0x02,0x6a,0x80,0x91 + +# GFX12: s_and_not1_b64 s[0:1], vcc, s[4:5] ; encoding: [0x6a,0x04,0x80,0x91] +0x6a,0x04,0x80,0x91 + +# GFX12: s_and_not1_b64 s[104:105], s[102:103], s[100:101] ; encoding: [0x66,0x64,0xe8,0x91] +0x66,0x64,0xe8,0x91 + +# GFX12: s_and_not1_b64 s[104:105], s[102:103], s[4:5] ; encoding: [0x66,0x04,0xe8,0x91] +0x66,0x04,0xe8,0x91 + +# GFX12: s_and_not1_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x91] +0x02,0x64,0xe8,0x91 + +# GFX12: s_and_not1_b64 s[104:105], s[2:3], s[4:5] ; encoding: [0x02,0x04,0xe8,0x91] +0x02,0x04,0xe8,0x91 + +# GFX12: s_and_not1_b64 vcc, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xea,0x91] +0x02,0x04,0xea,0x91 + +# GFX12: s_ashr_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x86] +0x01,0x02,0x7f,0x86 + +# GFX12: s_ashr_i32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x86] +0x01,0x02,0x7e,0x86 + +# GFX12: s_ashr_i32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x86] +0x01,0x02,0x7d,0x86 + +# GFX12: s_ashr_i32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x86] +0xf0,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x86] +0x80,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x86,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x86,0x73,0x72,0x71,0x3f + +# GFX12: s_ashr_i32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x86,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x86,0x56,0x34,0x12,0xaf + +# GFX12: s_ashr_i32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x86] +0xc1,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x86] +0xf7,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x86] +0x7f,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x86] +0x7e,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x86] +0x7d,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x86] +0x68,0x67,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x86] +0x68,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x86] +0x01,0xf0,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x86] +0x01,0x80,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x86,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x86,0x73,0x72,0x71,0x3f + +# GFX12: s_ashr_i32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x86,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x86,0x56,0x34,0x12,0xaf + +# GFX12: s_ashr_i32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x86] +0x01,0xc1,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x86] +0x01,0xf7,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x86] +0x01,0x7f,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x86] +0x01,0x7e,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x86] +0x01,0x7d,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x86] +0x01,0x67,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x86] +0x01,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x86] +0x01,0x6b,0x00,0x86 + +# GFX12: s_ashr_i32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x86] +0x01,0x6a,0x00,0x86 + +# GFX12: s_ashr_i32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x86] +0x6b,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x86] +0x6a,0x02,0x00,0x86 + +# GFX12: s_ashr_i32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x86] +0x68,0x67,0x69,0x86 + +# GFX12: s_ashr_i32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x86] +0x68,0x02,0x69,0x86 + +# GFX12: s_ashr_i32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x86] +0x01,0x67,0x69,0x86 + +# GFX12: s_ashr_i32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x86] +0x01,0x02,0x69,0x86 + +# GFX12: s_ashr_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x86] +0x01,0x02,0x6b,0x86 + +# GFX12: s_ashr_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x86] +0x01,0x02,0x6a,0x86 + +# GFX12: s_ashr_i64 exec, s[2:3], s4 ; encoding: [0x02,0x04,0xfe,0x86] +0x02,0x04,0xfe,0x86 + +# GFX12: s_ashr_i64 s[0:1], 0.5, s4 ; encoding: [0xf0,0x04,0x80,0x86] +0xf0,0x04,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], 0, s4 ; encoding: [0x80,0x04,0x80,0x86] +0x80,0x04,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], 0x3f717273, s4 ; encoding: [0xff,0x04,0x80,0x86,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x86,0x73,0x72,0x71,0x3f + +# GFX12: s_ashr_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x86,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x86,0x56,0x34,0x12,0xaf + +# GFX12: s_ashr_i64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x80,0x86] +0xc1,0x04,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], -4.0, s4 ; encoding: [0xf7,0x04,0x80,0x86] +0xf7,0x04,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], exec, s4 ; encoding: [0x7e,0x04,0x80,0x86] +0x7e,0x04,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[102:103], s100 ; encoding: [0x66,0x64,0x80,0x86] +0x66,0x64,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[102:103], s4 ; encoding: [0x66,0x04,0x80,0x86] +0x66,0x04,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x86] +0x02,0xf0,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x86] +0x02,0x80,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x86,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x86,0x73,0x72,0x71,0x3f + +# GFX12: s_ashr_i64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x86,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x86,0x56,0x34,0x12,0xaf + +# GFX12: s_ashr_i64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x86] +0x02,0xc1,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x86] +0x02,0xf7,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x80,0x86] +0x02,0x7e,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[2:3], s100 ; encoding: [0x02,0x64,0x80,0x86] +0x02,0x64,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[2:3], s4 ; encoding: [0x02,0x04,0x80,0x86] +0x02,0x04,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], s[2:3], vcc_lo ; encoding: [0x02,0x6a,0x80,0x86] +0x02,0x6a,0x80,0x86 + +# GFX12: s_ashr_i64 s[0:1], vcc, s4 ; encoding: [0x6a,0x04,0x80,0x86] +0x6a,0x04,0x80,0x86 + +# GFX12: s_ashr_i64 s[104:105], s[102:103], s100 ; encoding: [0x66,0x64,0xe8,0x86] +0x66,0x64,0xe8,0x86 + +# GFX12: s_ashr_i64 s[104:105], s[102:103], s4 ; encoding: [0x66,0x04,0xe8,0x86] +0x66,0x04,0xe8,0x86 + +# GFX12: s_ashr_i64 s[104:105], s[2:3], s100 ; encoding: [0x02,0x64,0xe8,0x86] +0x02,0x64,0xe8,0x86 + +# GFX12: s_ashr_i64 s[104:105], s[2:3], s4 ; encoding: [0x02,0x04,0xe8,0x86] +0x02,0x04,0xe8,0x86 + +# GFX12: s_ashr_i64 vcc, s[2:3], s4 ; encoding: [0x02,0x04,0xea,0x86] +0x02,0x04,0xea,0x86 + +# GFX12: s_bfe_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x93] +0x01,0x02,0xff,0x93 + +# GFX12: s_bfe_i32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x93] +0x01,0x02,0xfe,0x93 + +# GFX12: s_bfe_i32 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x93] +0x01,0x02,0xfd,0x93 + +# GFX12: s_bfe_i32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x93] +0xf0,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x93] +0x80,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x93,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x93,0x73,0x72,0x71,0x3f + +# GFX12: s_bfe_i32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x93,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x93,0x56,0x34,0x12,0xaf + +# GFX12: s_bfe_i32 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x93] +0xc1,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x93] +0xf7,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x93] +0x7f,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x93] +0x7e,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x93] +0x7d,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x93] +0x68,0x67,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x93] +0x68,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x93] +0x01,0xf0,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x93] +0x01,0x80,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x93,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x93,0x73,0x72,0x71,0x3f + +# GFX12: s_bfe_i32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x93,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x93,0x56,0x34,0x12,0xaf + +# GFX12: s_bfe_i32 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x93] +0x01,0xc1,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x93] +0x01,0xf7,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x93] +0x01,0x7f,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x93] +0x01,0x7e,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x93] +0x01,0x7d,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x93] +0x01,0x67,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x93] +0x01,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x93] +0x01,0x6b,0x80,0x93 + +# GFX12: s_bfe_i32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x93] +0x01,0x6a,0x80,0x93 + +# GFX12: s_bfe_i32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x93] +0x6b,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x93] +0x6a,0x02,0x80,0x93 + +# GFX12: s_bfe_i32 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x93] +0x68,0x67,0xe9,0x93 + +# GFX12: s_bfe_i32 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x93] +0x68,0x02,0xe9,0x93 + +# GFX12: s_bfe_i32 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x93] +0x01,0x67,0xe9,0x93 + +# GFX12: s_bfe_i32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x93] +0x01,0x02,0xe9,0x93 + +# GFX12: s_bfe_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x93] +0x01,0x02,0xeb,0x93 + +# GFX12: s_bfe_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x93] +0x01,0x02,0xea,0x93 + +# GFX12: s_bfe_i64 exec, s[2:3], s4 ; encoding: [0x02,0x04,0xfe,0x94] +0x02,0x04,0xfe,0x94 + +# GFX12: s_bfe_i64 s[0:1], 0.5, s4 ; encoding: [0xf0,0x04,0x80,0x94] +0xf0,0x04,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], 0, s4 ; encoding: [0x80,0x04,0x80,0x94] +0x80,0x04,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], 0x3f717273, s4 ; encoding: [0xff,0x04,0x80,0x94,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x94,0x73,0x72,0x71,0x3f + +# GFX12: s_bfe_i64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x94,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x94,0x56,0x34,0x12,0xaf + +# GFX12: s_bfe_i64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x80,0x94] +0xc1,0x04,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], -4.0, s4 ; encoding: [0xf7,0x04,0x80,0x94] +0xf7,0x04,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], exec, s4 ; encoding: [0x7e,0x04,0x80,0x94] +0x7e,0x04,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[102:103], s100 ; encoding: [0x66,0x64,0x80,0x94] +0x66,0x64,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[102:103], s4 ; encoding: [0x66,0x04,0x80,0x94] +0x66,0x04,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x94] +0x02,0xf0,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x94] +0x02,0x80,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x94,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x94,0x73,0x72,0x71,0x3f + +# GFX12: s_bfe_i64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x94,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x94,0x56,0x34,0x12,0xaf + +# GFX12: s_bfe_i64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x94] +0x02,0xc1,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x94] +0x02,0xf7,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x80,0x94] +0x02,0x7e,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[2:3], s100 ; encoding: [0x02,0x64,0x80,0x94] +0x02,0x64,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[2:3], s4 ; encoding: [0x02,0x04,0x80,0x94] +0x02,0x04,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], s[2:3], vcc_lo ; encoding: [0x02,0x6a,0x80,0x94] +0x02,0x6a,0x80,0x94 + +# GFX12: s_bfe_i64 s[0:1], vcc, s4 ; encoding: [0x6a,0x04,0x80,0x94] +0x6a,0x04,0x80,0x94 + +# GFX12: s_bfe_i64 s[104:105], s[102:103], s100 ; encoding: [0x66,0x64,0xe8,0x94] +0x66,0x64,0xe8,0x94 + +# GFX12: s_bfe_i64 s[104:105], s[102:103], s4 ; encoding: [0x66,0x04,0xe8,0x94] +0x66,0x04,0xe8,0x94 + +# GFX12: s_bfe_i64 s[104:105], s[2:3], s100 ; encoding: [0x02,0x64,0xe8,0x94] +0x02,0x64,0xe8,0x94 + +# GFX12: s_bfe_i64 s[104:105], s[2:3], s4 ; encoding: [0x02,0x04,0xe8,0x94] +0x02,0x04,0xe8,0x94 + +# GFX12: s_bfe_i64 vcc, s[2:3], s4 ; encoding: [0x02,0x04,0xea,0x94] +0x02,0x04,0xea,0x94 + +# GFX12: s_bfe_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x93] +0x01,0x02,0x7f,0x93 + +# GFX12: s_bfe_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x93] +0x01,0x02,0x7e,0x93 + +# GFX12: s_bfe_u32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x93] +0x01,0x02,0x7d,0x93 + +# GFX12: s_bfe_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x93] +0xf0,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x93] +0x80,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x93,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x93,0x73,0x72,0x71,0x3f + +# GFX12: s_bfe_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x93,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x93,0x56,0x34,0x12,0xaf + +# GFX12: s_bfe_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x93] +0xc1,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x93] +0xf7,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x93] +0x7f,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x93] +0x7e,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x93] +0x7d,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x93] +0x68,0x67,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x93] +0x68,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x93] +0x01,0xf0,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x93] +0x01,0x80,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x93,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x93,0x73,0x72,0x71,0x3f + +# GFX12: s_bfe_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x93,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x93,0x56,0x34,0x12,0xaf + +# GFX12: s_bfe_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x93] +0x01,0xc1,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x93] +0x01,0xf7,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x93] +0x01,0x7f,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x93] +0x01,0x7e,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x93] +0x01,0x7d,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x93] +0x01,0x67,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x93] +0x01,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x93] +0x01,0x6b,0x00,0x93 + +# GFX12: s_bfe_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x93] +0x01,0x6a,0x00,0x93 + +# GFX12: s_bfe_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x93] +0x6b,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x93] +0x6a,0x02,0x00,0x93 + +# GFX12: s_bfe_u32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x93] +0x68,0x67,0x69,0x93 + +# GFX12: s_bfe_u32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x93] +0x68,0x02,0x69,0x93 + +# GFX12: s_bfe_u32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x93] +0x01,0x67,0x69,0x93 + +# GFX12: s_bfe_u32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x93] +0x01,0x02,0x69,0x93 + +# GFX12: s_bfe_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x93] +0x01,0x02,0x6b,0x93 + +# GFX12: s_bfe_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x93] +0x01,0x02,0x6a,0x93 + +# GFX12: s_bfe_u64 exec, s[2:3], s4 ; encoding: [0x02,0x04,0x7e,0x94] +0x02,0x04,0x7e,0x94 + +# GFX12: s_bfe_u64 s[0:1], 0.5, s4 ; encoding: [0xf0,0x04,0x00,0x94] +0xf0,0x04,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], 0, s4 ; encoding: [0x80,0x04,0x00,0x94] +0x80,0x04,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], 0x3f717273, s4 ; encoding: [0xff,0x04,0x00,0x94,0x73,0x72,0x71,0x3f] +0xff,0x04,0x00,0x94,0x73,0x72,0x71,0x3f + +# GFX12: s_bfe_u64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x00,0x94,0x56,0x34,0x12,0xaf] +0xff,0x04,0x00,0x94,0x56,0x34,0x12,0xaf + +# GFX12: s_bfe_u64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x00,0x94] +0xc1,0x04,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], -4.0, s4 ; encoding: [0xf7,0x04,0x00,0x94] +0xf7,0x04,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], exec, s4 ; encoding: [0x7e,0x04,0x00,0x94] +0x7e,0x04,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[102:103], s100 ; encoding: [0x66,0x64,0x00,0x94] +0x66,0x64,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[102:103], s4 ; encoding: [0x66,0x04,0x00,0x94] +0x66,0x04,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x00,0x94] +0x02,0xf0,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x00,0x94] +0x02,0x80,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x00,0x94,0x73,0x72,0x71,0x3f] +0x02,0xff,0x00,0x94,0x73,0x72,0x71,0x3f + +# GFX12: s_bfe_u64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x00,0x94,0x56,0x34,0x12,0xaf] +0x02,0xff,0x00,0x94,0x56,0x34,0x12,0xaf + +# GFX12: s_bfe_u64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x00,0x94] +0x02,0xc1,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x00,0x94] +0x02,0xf7,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x00,0x94] +0x02,0x7e,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[2:3], s100 ; encoding: [0x02,0x64,0x00,0x94] +0x02,0x64,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[2:3], s4 ; encoding: [0x02,0x04,0x00,0x94] +0x02,0x04,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], s[2:3], vcc_lo ; encoding: [0x02,0x6a,0x00,0x94] +0x02,0x6a,0x00,0x94 + +# GFX12: s_bfe_u64 s[0:1], vcc, s4 ; encoding: [0x6a,0x04,0x00,0x94] +0x6a,0x04,0x00,0x94 + +# GFX12: s_bfe_u64 s[104:105], s[102:103], s100 ; encoding: [0x66,0x64,0x68,0x94] +0x66,0x64,0x68,0x94 + +# GFX12: s_bfe_u64 s[104:105], s[102:103], s4 ; encoding: [0x66,0x04,0x68,0x94] +0x66,0x04,0x68,0x94 + +# GFX12: s_bfe_u64 s[104:105], s[2:3], s100 ; encoding: [0x02,0x64,0x68,0x94] +0x02,0x64,0x68,0x94 + +# GFX12: s_bfe_u64 s[104:105], s[2:3], s4 ; encoding: [0x02,0x04,0x68,0x94] +0x02,0x04,0x68,0x94 + +# GFX12: s_bfe_u64 vcc, s[2:3], s4 ; encoding: [0x02,0x04,0x6a,0x94] +0x02,0x04,0x6a,0x94 + +# GFX12: s_bfm_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x95] +0x01,0x02,0x7f,0x95 + +# GFX12: s_bfm_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x95] +0x01,0x02,0x7e,0x95 + +# GFX12: s_bfm_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x95] +0x01,0x02,0x7d,0x95 + +# GFX12: s_bfm_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x95] +0xf0,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x95] +0x80,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x95,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x95,0x73,0x72,0x71,0x3f + +# GFX12: s_bfm_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x95,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x95,0x56,0x34,0x12,0xaf + +# GFX12: s_bfm_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x95] +0xc1,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x95] +0xf7,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x95] +0x7f,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x95] +0x7e,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x95] +0x7d,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x95] +0x68,0x67,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x95] +0x68,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x95] +0x01,0xf0,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x95] +0x01,0x80,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x95,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x95,0x73,0x72,0x71,0x3f + +# GFX12: s_bfm_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x95,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x95,0x56,0x34,0x12,0xaf + +# GFX12: s_bfm_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x95] +0x01,0xc1,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x95] +0x01,0xf7,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x95] +0x01,0x7f,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x95] +0x01,0x7e,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x95] +0x01,0x7d,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x95] +0x01,0x67,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x95] +0x01,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x95] +0x01,0x6b,0x00,0x95 + +# GFX12: s_bfm_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x95] +0x01,0x6a,0x00,0x95 + +# GFX12: s_bfm_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x95] +0x6b,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x95] +0x6a,0x02,0x00,0x95 + +# GFX12: s_bfm_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x95] +0x68,0x67,0x69,0x95 + +# GFX12: s_bfm_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x95] +0x68,0x02,0x69,0x95 + +# GFX12: s_bfm_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x95] +0x01,0x67,0x69,0x95 + +# GFX12: s_bfm_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x95] +0x01,0x02,0x69,0x95 + +# GFX12: s_bfm_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x95] +0x01,0x02,0x6b,0x95 + +# GFX12: s_bfm_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x95] +0x01,0x02,0x6a,0x95 + +# GFX12: s_bfm_b64 exec, s2, s3 ; encoding: [0x02,0x03,0xfe,0x95] +0x02,0x03,0xfe,0x95 + +# GFX12: s_bfm_b64 s[0:1], 0.5, s3 ; encoding: [0xf0,0x03,0x80,0x95] +0xf0,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], 0, s3 ; encoding: [0x80,0x03,0x80,0x95] +0x80,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], 0x3f717273, s3 ; encoding: [0xff,0x03,0x80,0x95,0x73,0x72,0x71,0x3f] +0xff,0x03,0x80,0x95,0x73,0x72,0x71,0x3f + +# GFX12: s_bfm_b64 s[0:1], 0xaf123456, s3 ; encoding: [0xff,0x03,0x80,0x95,0x56,0x34,0x12,0xaf] +0xff,0x03,0x80,0x95,0x56,0x34,0x12,0xaf + +# GFX12: s_bfm_b64 s[0:1], -1, s3 ; encoding: [0xc1,0x03,0x80,0x95] +0xc1,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], -4.0, s3 ; encoding: [0xf7,0x03,0x80,0x95] +0xf7,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], exec_hi, s3 ; encoding: [0x7f,0x03,0x80,0x95] +0x7f,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], exec_lo, s3 ; encoding: [0x7e,0x03,0x80,0x95] +0x7e,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], m0, s3 ; encoding: [0x7d,0x03,0x80,0x95] +0x7d,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s104, s103 ; encoding: [0x68,0x67,0x80,0x95] +0x68,0x67,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s104, s3 ; encoding: [0x68,0x03,0x80,0x95] +0x68,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, 0.5 ; encoding: [0x02,0xf0,0x80,0x95] +0x02,0xf0,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, 0 ; encoding: [0x02,0x80,0x80,0x95] +0x02,0x80,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, 0x3f717273 ; encoding: [0x02,0xff,0x80,0x95,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x95,0x73,0x72,0x71,0x3f + +# GFX12: s_bfm_b64 s[0:1], s2, 0xaf123456 ; encoding: [0x02,0xff,0x80,0x95,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x95,0x56,0x34,0x12,0xaf + +# GFX12: s_bfm_b64 s[0:1], s2, -1 ; encoding: [0x02,0xc1,0x80,0x95] +0x02,0xc1,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, -4.0 ; encoding: [0x02,0xf7,0x80,0x95] +0x02,0xf7,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, exec_hi ; encoding: [0x02,0x7f,0x80,0x95] +0x02,0x7f,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, exec_lo ; encoding: [0x02,0x7e,0x80,0x95] +0x02,0x7e,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, m0 ; encoding: [0x02,0x7d,0x80,0x95] +0x02,0x7d,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, s103 ; encoding: [0x02,0x67,0x80,0x95] +0x02,0x67,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, s3 ; encoding: [0x02,0x03,0x80,0x95] +0x02,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, vcc_hi ; encoding: [0x02,0x6b,0x80,0x95] +0x02,0x6b,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], s2, vcc_lo ; encoding: [0x02,0x6a,0x80,0x95] +0x02,0x6a,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], vcc_hi, s3 ; encoding: [0x6b,0x03,0x80,0x95] +0x6b,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[0:1], vcc_lo, s3 ; encoding: [0x6a,0x03,0x80,0x95] +0x6a,0x03,0x80,0x95 + +# GFX12: s_bfm_b64 s[104:105], s103, s102 ; encoding: [0x67,0x66,0xe8,0x95] +0x67,0x66,0xe8,0x95 + +# GFX12: s_bfm_b64 s[104:105], s104, s3 ; encoding: [0x68,0x03,0xe8,0x95] +0x68,0x03,0xe8,0x95 + +# GFX12: s_bfm_b64 s[104:105], s2, s103 ; encoding: [0x02,0x67,0xe8,0x95] +0x02,0x67,0xe8,0x95 + +# GFX12: s_bfm_b64 s[104:105], s2, s3 ; encoding: [0x02,0x03,0xe8,0x95] +0x02,0x03,0xe8,0x95 + +# GFX12: s_bfm_b64 vcc, s2, s3 ; encoding: [0x02,0x03,0xea,0x95] +0x02,0x03,0xea,0x95 + +# GFX12: s_cselect_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x98] +0x01,0x02,0x7f,0x98 + +# GFX12: s_cselect_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x98] +0x01,0x02,0x7e,0x98 + +# GFX12: s_cselect_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x98] +0x01,0x02,0x7d,0x98 + +# GFX12: s_cselect_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x98] +0xf0,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x98] +0x80,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x98,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x98,0x73,0x72,0x71,0x3f + +# GFX12: s_cselect_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x98,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x98,0x56,0x34,0x12,0xaf + +# GFX12: s_cselect_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x98] +0xc1,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x98] +0xf7,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x98] +0x7f,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x98] +0x7e,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x98] +0x7d,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x98] +0x68,0x67,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x98] +0x68,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x98] +0x01,0xf0,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x98] +0x01,0x80,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x98,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x98,0x73,0x72,0x71,0x3f + +# GFX12: s_cselect_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x98,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x98,0x56,0x34,0x12,0xaf + +# GFX12: s_cselect_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x98] +0x01,0xc1,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x98] +0x01,0xf7,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x98] +0x01,0x7f,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x98] +0x01,0x7e,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x98] +0x01,0x7d,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x98] +0x01,0x67,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x98] +0x01,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x98] +0x01,0x6b,0x00,0x98 + +# GFX12: s_cselect_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x98] +0x01,0x6a,0x00,0x98 + +# GFX12: s_cselect_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x98] +0x6b,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x98] +0x6a,0x02,0x00,0x98 + +# GFX12: s_cselect_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x98] +0x68,0x67,0x69,0x98 + +# GFX12: s_cselect_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x98] +0x68,0x02,0x69,0x98 + +# GFX12: s_cselect_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x98] +0x01,0x67,0x69,0x98 + +# GFX12: s_cselect_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x98] +0x01,0x02,0x69,0x98 + +# GFX12: s_cselect_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x98] +0x01,0x02,0x6b,0x98 + +# GFX12: s_cselect_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x98] +0x01,0x02,0x6a,0x98 + +# GFX12: s_cselect_b64 exec, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xfe,0x98] +0x02,0x04,0xfe,0x98 + +# GFX12: s_cselect_b64 s[0:1], 0.5, s[4:5] ; encoding: [0xf0,0x04,0x80,0x98] +0xf0,0x04,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], 0, s[4:5] ; encoding: [0x80,0x04,0x80,0x98] +0x80,0x04,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], 0x3f717273, s[4:5] ; encoding: [0xff,0x04,0x80,0x98,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x98,0x73,0x72,0x71,0x3f + +# GFX12: s_cselect_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x98,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x98,0x56,0x34,0x12,0xaf + +# GFX12: s_cselect_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x98] +0xc1,0x04,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], -4.0, s[4:5] ; encoding: [0xf7,0x04,0x80,0x98] +0xf7,0x04,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], exec, s[4:5] ; encoding: [0x7e,0x04,0x80,0x98] +0x7e,0x04,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[102:103], s[100:101] ; encoding: [0x66,0x64,0x80,0x98] +0x66,0x64,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[102:103], s[4:5] ; encoding: [0x66,0x04,0x80,0x98] +0x66,0x04,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x98] +0x02,0xf0,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x98] +0x02,0x80,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x98,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x98,0x73,0x72,0x71,0x3f + +# GFX12: s_cselect_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x98,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x98,0x56,0x34,0x12,0xaf + +# GFX12: s_cselect_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x98] +0x02,0xc1,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x98] +0x02,0xf7,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x98] +0x02,0x7e,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[2:3], s[100:101] ; encoding: [0x02,0x64,0x80,0x98] +0x02,0x64,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0x98] +0x02,0x04,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0x98] +0x02,0x6a,0x80,0x98 + +# GFX12: s_cselect_b64 s[0:1], vcc, s[4:5] ; encoding: [0x6a,0x04,0x80,0x98] +0x6a,0x04,0x80,0x98 + +# GFX12: s_cselect_b64 s[104:105], s[102:103], s[100:101] ; encoding: [0x66,0x64,0xe8,0x98] +0x66,0x64,0xe8,0x98 + +# GFX12: s_cselect_b64 s[104:105], s[102:103], s[4:5] ; encoding: [0x66,0x04,0xe8,0x98] +0x66,0x04,0xe8,0x98 + +# GFX12: s_cselect_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x98] +0x02,0x64,0xe8,0x98 + +# GFX12: s_cselect_b64 s[104:105], s[2:3], s[4:5] ; encoding: [0x02,0x04,0xe8,0x98] +0x02,0x04,0xe8,0x98 + +# GFX12: s_cselect_b64 vcc, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xea,0x98] +0x02,0x04,0xea,0x98 + +# GFX12: s_lshl1_add_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x87] +0x01,0x02,0x7f,0x87 + +# GFX12: s_lshl1_add_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x87] +0x01,0x02,0x7e,0x87 + +# GFX12: s_lshl1_add_u32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x87] +0x01,0x02,0x7d,0x87 + +# GFX12: s_lshl1_add_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x87] +0xf0,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x87] +0x80,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x87,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x87,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl1_add_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x87,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x87,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl1_add_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x87] +0xc1,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x87] +0xf7,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x87] +0x7f,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x87] +0x7e,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x87] +0x7d,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x87] +0x68,0x67,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x87] +0x68,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x87] +0x01,0xf0,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x87] +0x01,0x80,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x87,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x87,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl1_add_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x87,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x87,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl1_add_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x87] +0x01,0xc1,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x87] +0x01,0xf7,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x87] +0x01,0x7f,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x87] +0x01,0x7e,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x87] +0x01,0x7d,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x87] +0x01,0x67,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x87] +0x01,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x87] +0x01,0x6b,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x87] +0x01,0x6a,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x87] +0x6b,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x87] +0x6a,0x02,0x00,0x87 + +# GFX12: s_lshl1_add_u32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x87] +0x68,0x67,0x69,0x87 + +# GFX12: s_lshl1_add_u32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x87] +0x68,0x02,0x69,0x87 + +# GFX12: s_lshl1_add_u32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x87] +0x01,0x67,0x69,0x87 + +# GFX12: s_lshl1_add_u32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x87] +0x01,0x02,0x69,0x87 + +# GFX12: s_lshl1_add_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x87] +0x01,0x02,0x6b,0x87 + +# GFX12: s_lshl1_add_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x87] +0x01,0x02,0x6a,0x87 + +# GFX12: s_lshl2_add_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x87] +0x01,0x02,0xff,0x87 + +# GFX12: s_lshl2_add_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x87] +0x01,0x02,0xfe,0x87 + +# GFX12: s_lshl2_add_u32 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x87] +0x01,0x02,0xfd,0x87 + +# GFX12: s_lshl2_add_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x87] +0xf0,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x87] +0x80,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x87,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x87,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl2_add_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x87,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x87,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl2_add_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x87] +0xc1,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x87] +0xf7,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x87] +0x7f,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x87] +0x7e,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x87] +0x7d,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x87] +0x68,0x67,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x87] +0x68,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x87] +0x01,0xf0,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x87] +0x01,0x80,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x87,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x87,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl2_add_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x87,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x87,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl2_add_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x87] +0x01,0xc1,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x87] +0x01,0xf7,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x87] +0x01,0x7f,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x87] +0x01,0x7e,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x87] +0x01,0x7d,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x87] +0x01,0x67,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x87] +0x01,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x87] +0x01,0x6b,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x87] +0x01,0x6a,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x87] +0x6b,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x87] +0x6a,0x02,0x80,0x87 + +# GFX12: s_lshl2_add_u32 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x87] +0x68,0x67,0xe9,0x87 + +# GFX12: s_lshl2_add_u32 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x87] +0x68,0x02,0xe9,0x87 + +# GFX12: s_lshl2_add_u32 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x87] +0x01,0x67,0xe9,0x87 + +# GFX12: s_lshl2_add_u32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x87] +0x01,0x02,0xe9,0x87 + +# GFX12: s_lshl2_add_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x87] +0x01,0x02,0xeb,0x87 + +# GFX12: s_lshl2_add_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x87] +0x01,0x02,0xea,0x87 + +# GFX12: s_lshl3_add_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x88] +0x01,0x02,0x7f,0x88 + +# GFX12: s_lshl3_add_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x88] +0x01,0x02,0x7e,0x88 + +# GFX12: s_lshl3_add_u32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x88] +0x01,0x02,0x7d,0x88 + +# GFX12: s_lshl3_add_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x88] +0xf0,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x88] +0x80,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x88,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x88,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl3_add_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x88,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x88,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl3_add_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x88] +0xc1,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x88] +0xf7,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x88] +0x7f,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x88] +0x7e,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x88] +0x7d,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x88] +0x68,0x67,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x88] +0x68,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x88] +0x01,0xf0,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x88] +0x01,0x80,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x88,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x88,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl3_add_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x88,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x88,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl3_add_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x88] +0x01,0xc1,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x88] +0x01,0xf7,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x88] +0x01,0x7f,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x88] +0x01,0x7e,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x88] +0x01,0x7d,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x88] +0x01,0x67,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x88] +0x01,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x88] +0x01,0x6b,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x88] +0x01,0x6a,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x88] +0x6b,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x88] +0x6a,0x02,0x00,0x88 + +# GFX12: s_lshl3_add_u32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x88] +0x68,0x67,0x69,0x88 + +# GFX12: s_lshl3_add_u32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x88] +0x68,0x02,0x69,0x88 + +# GFX12: s_lshl3_add_u32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x88] +0x01,0x67,0x69,0x88 + +# GFX12: s_lshl3_add_u32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x88] +0x01,0x02,0x69,0x88 + +# GFX12: s_lshl3_add_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x88] +0x01,0x02,0x6b,0x88 + +# GFX12: s_lshl3_add_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x88] +0x01,0x02,0x6a,0x88 + +# GFX12: s_lshl4_add_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x88] +0x01,0x02,0xff,0x88 + +# GFX12: s_lshl4_add_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x88] +0x01,0x02,0xfe,0x88 + +# GFX12: s_lshl4_add_u32 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x88] +0x01,0x02,0xfd,0x88 + +# GFX12: s_lshl4_add_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x88] +0xf0,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x88] +0x80,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x88,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x88,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl4_add_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x88,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x88,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl4_add_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x88] +0xc1,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x88] +0xf7,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x88] +0x7f,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x88] +0x7e,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x88] +0x7d,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x88] +0x68,0x67,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x88] +0x68,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x88] +0x01,0xf0,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x88] +0x01,0x80,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x88,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x88,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl4_add_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x88,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x88,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl4_add_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x88] +0x01,0xc1,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x88] +0x01,0xf7,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x88] +0x01,0x7f,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x88] +0x01,0x7e,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x88] +0x01,0x7d,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x88] +0x01,0x67,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x88] +0x01,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x88] +0x01,0x6b,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x88] +0x01,0x6a,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x88] +0x6b,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x88] +0x6a,0x02,0x80,0x88 + +# GFX12: s_lshl4_add_u32 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x88] +0x68,0x67,0xe9,0x88 + +# GFX12: s_lshl4_add_u32 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x88] +0x68,0x02,0xe9,0x88 + +# GFX12: s_lshl4_add_u32 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x88] +0x01,0x67,0xe9,0x88 + +# GFX12: s_lshl4_add_u32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x88] +0x01,0x02,0xe9,0x88 + +# GFX12: s_lshl4_add_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x88] +0x01,0x02,0xeb,0x88 + +# GFX12: s_lshl4_add_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x88] +0x01,0x02,0xea,0x88 + +# GFX12: s_lshl_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x84] +0x01,0x02,0x7f,0x84 + +# GFX12: s_lshl_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x84] +0x01,0x02,0x7e,0x84 + +# GFX12: s_lshl_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x84] +0x01,0x02,0x7d,0x84 + +# GFX12: s_lshl_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x84] +0xf0,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x84] +0x80,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x84,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x84,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x84,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x84,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x84] +0xc1,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x84] +0xf7,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x84] +0x7f,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x84] +0x7e,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x84] +0x7d,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x84] +0x68,0x67,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x84] +0x68,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x84] +0x01,0xf0,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x84] +0x01,0x80,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x84,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x84,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x84,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x84,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x84] +0x01,0xc1,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x84] +0x01,0xf7,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x84] +0x01,0x7f,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x84] +0x01,0x7e,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x84] +0x01,0x7d,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x84] +0x01,0x67,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x84] +0x01,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x84] +0x01,0x6b,0x00,0x84 + +# GFX12: s_lshl_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x84] +0x01,0x6a,0x00,0x84 + +# GFX12: s_lshl_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x84] +0x6b,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x84] +0x6a,0x02,0x00,0x84 + +# GFX12: s_lshl_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x84] +0x68,0x67,0x69,0x84 + +# GFX12: s_lshl_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x84] +0x68,0x02,0x69,0x84 + +# GFX12: s_lshl_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x84] +0x01,0x67,0x69,0x84 + +# GFX12: s_lshl_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x84] +0x01,0x02,0x69,0x84 + +# GFX12: s_lshl_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x84] +0x01,0x02,0x6b,0x84 + +# GFX12: s_lshl_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x84] +0x01,0x02,0x6a,0x84 + +# GFX12: s_lshl_b64 exec, s[2:3], s4 ; encoding: [0x02,0x04,0xfe,0x84] +0x02,0x04,0xfe,0x84 + +# GFX12: s_lshl_b64 s[0:1], 0.5, s4 ; encoding: [0xf0,0x04,0x80,0x84] +0xf0,0x04,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], 0, s4 ; encoding: [0x80,0x04,0x80,0x84] +0x80,0x04,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], 0x3f717273, s4 ; encoding: [0xff,0x04,0x80,0x84,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x84,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x84,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x84,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl_b64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x80,0x84] +0xc1,0x04,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], -4.0, s4 ; encoding: [0xf7,0x04,0x80,0x84] +0xf7,0x04,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], exec, s4 ; encoding: [0x7e,0x04,0x80,0x84] +0x7e,0x04,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[102:103], s100 ; encoding: [0x66,0x64,0x80,0x84] +0x66,0x64,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[102:103], s4 ; encoding: [0x66,0x04,0x80,0x84] +0x66,0x04,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x84] +0x02,0xf0,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x84] +0x02,0x80,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x84,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x84,0x73,0x72,0x71,0x3f + +# GFX12: s_lshl_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x84,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x84,0x56,0x34,0x12,0xaf + +# GFX12: s_lshl_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x84] +0x02,0xc1,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x84] +0x02,0xf7,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x80,0x84] +0x02,0x7e,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[2:3], s100 ; encoding: [0x02,0x64,0x80,0x84] +0x02,0x64,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[2:3], s4 ; encoding: [0x02,0x04,0x80,0x84] +0x02,0x04,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], s[2:3], vcc_lo ; encoding: [0x02,0x6a,0x80,0x84] +0x02,0x6a,0x80,0x84 + +# GFX12: s_lshl_b64 s[0:1], vcc, s4 ; encoding: [0x6a,0x04,0x80,0x84] +0x6a,0x04,0x80,0x84 + +# GFX12: s_lshl_b64 s[104:105], s[102:103], s100 ; encoding: [0x66,0x64,0xe8,0x84] +0x66,0x64,0xe8,0x84 + +# GFX12: s_lshl_b64 s[104:105], s[102:103], s4 ; encoding: [0x66,0x04,0xe8,0x84] +0x66,0x04,0xe8,0x84 + +# GFX12: s_lshl_b64 s[104:105], s[2:3], s100 ; encoding: [0x02,0x64,0xe8,0x84] +0x02,0x64,0xe8,0x84 + +# GFX12: s_lshl_b64 s[104:105], s[2:3], s4 ; encoding: [0x02,0x04,0xe8,0x84] +0x02,0x04,0xe8,0x84 + +# GFX12: s_lshl_b64 vcc, s[2:3], s4 ; encoding: [0x02,0x04,0xea,0x84] +0x02,0x04,0xea,0x84 + +# GFX12: s_lshr_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x85] +0x01,0x02,0x7f,0x85 + +# GFX12: s_lshr_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x85] +0x01,0x02,0x7e,0x85 + +# GFX12: s_lshr_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x85] +0x01,0x02,0x7d,0x85 + +# GFX12: s_lshr_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x85] +0xf0,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x85] +0x80,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x85,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x85,0x73,0x72,0x71,0x3f + +# GFX12: s_lshr_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x85,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x85,0x56,0x34,0x12,0xaf + +# GFX12: s_lshr_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x85] +0xc1,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x85] +0xf7,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x85] +0x7f,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x85] +0x7e,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x85] +0x7d,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x85] +0x68,0x67,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x85] +0x68,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x85] +0x01,0xf0,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x85] +0x01,0x80,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x85,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x85,0x73,0x72,0x71,0x3f + +# GFX12: s_lshr_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x85,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x85,0x56,0x34,0x12,0xaf + +# GFX12: s_lshr_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x85] +0x01,0xc1,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x85] +0x01,0xf7,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x85] +0x01,0x7f,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x85] +0x01,0x7e,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x85] +0x01,0x7d,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x85] +0x01,0x67,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x85] +0x01,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x85] +0x01,0x6b,0x00,0x85 + +# GFX12: s_lshr_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x85] +0x01,0x6a,0x00,0x85 + +# GFX12: s_lshr_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x85] +0x6b,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x85] +0x6a,0x02,0x00,0x85 + +# GFX12: s_lshr_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x85] +0x68,0x67,0x69,0x85 + +# GFX12: s_lshr_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x85] +0x68,0x02,0x69,0x85 + +# GFX12: s_lshr_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x85] +0x01,0x67,0x69,0x85 + +# GFX12: s_lshr_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x85] +0x01,0x02,0x69,0x85 + +# GFX12: s_lshr_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x85] +0x01,0x02,0x6b,0x85 + +# GFX12: s_lshr_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x85] +0x01,0x02,0x6a,0x85 + +# GFX12: s_lshr_b64 exec, s[2:3], s4 ; encoding: [0x02,0x04,0xfe,0x85] +0x02,0x04,0xfe,0x85 + +# GFX12: s_lshr_b64 s[0:1], 0.5, s4 ; encoding: [0xf0,0x04,0x80,0x85] +0xf0,0x04,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], 0, s4 ; encoding: [0x80,0x04,0x80,0x85] +0x80,0x04,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], 0x3f717273, s4 ; encoding: [0xff,0x04,0x80,0x85,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x85,0x73,0x72,0x71,0x3f + +# GFX12: s_lshr_b64 s[0:1], 0xaf123456, s4 ; encoding: [0xff,0x04,0x80,0x85,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x85,0x56,0x34,0x12,0xaf + +# GFX12: s_lshr_b64 s[0:1], -1, s4 ; encoding: [0xc1,0x04,0x80,0x85] +0xc1,0x04,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], -4.0, s4 ; encoding: [0xf7,0x04,0x80,0x85] +0xf7,0x04,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], exec, s4 ; encoding: [0x7e,0x04,0x80,0x85] +0x7e,0x04,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[102:103], s100 ; encoding: [0x66,0x64,0x80,0x85] +0x66,0x64,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[102:103], s4 ; encoding: [0x66,0x04,0x80,0x85] +0x66,0x04,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x85] +0x02,0xf0,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x85] +0x02,0x80,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x85,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x85,0x73,0x72,0x71,0x3f + +# GFX12: s_lshr_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x85,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x85,0x56,0x34,0x12,0xaf + +# GFX12: s_lshr_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x85] +0x02,0xc1,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x85] +0x02,0xf7,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[2:3], exec_lo ; encoding: [0x02,0x7e,0x80,0x85] +0x02,0x7e,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[2:3], s100 ; encoding: [0x02,0x64,0x80,0x85] +0x02,0x64,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[2:3], s4 ; encoding: [0x02,0x04,0x80,0x85] +0x02,0x04,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], s[2:3], vcc_lo ; encoding: [0x02,0x6a,0x80,0x85] +0x02,0x6a,0x80,0x85 + +# GFX12: s_lshr_b64 s[0:1], vcc, s4 ; encoding: [0x6a,0x04,0x80,0x85] +0x6a,0x04,0x80,0x85 + +# GFX12: s_lshr_b64 s[104:105], s[102:103], s100 ; encoding: [0x66,0x64,0xe8,0x85] +0x66,0x64,0xe8,0x85 + +# GFX12: s_lshr_b64 s[104:105], s[102:103], s4 ; encoding: [0x66,0x04,0xe8,0x85] +0x66,0x04,0xe8,0x85 + +# GFX12: s_lshr_b64 s[104:105], s[2:3], s100 ; encoding: [0x02,0x64,0xe8,0x85] +0x02,0x64,0xe8,0x85 + +# GFX12: s_lshr_b64 s[104:105], s[2:3], s4 ; encoding: [0x02,0x04,0xe8,0x85] +0x02,0x04,0xe8,0x85 + +# GFX12: s_lshr_b64 vcc, s[2:3], s4 ; encoding: [0x02,0x04,0xea,0x85] +0x02,0x04,0xea,0x85 + +# GFX12: s_max_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x8a] +0x01,0x02,0x7f,0x8a + +# GFX12: s_max_i32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x8a] +0x01,0x02,0x7e,0x8a + +# GFX12: s_max_i32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x8a] +0x01,0x02,0x7d,0x8a + +# GFX12: s_max_i32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x8a] +0xf0,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x8a] +0x80,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x8a,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x8a,0x73,0x72,0x71,0x3f + +# GFX12: s_max_i32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x8a,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x8a,0x56,0x34,0x12,0xaf + +# GFX12: s_max_i32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x8a] +0xc1,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x8a] +0xf7,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x8a] +0x7f,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x8a] +0x7e,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x8a] +0x7d,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x8a] +0x68,0x67,0x00,0x8a + +# GFX12: s_max_i32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x8a] +0x68,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x8a] +0x01,0xf0,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x8a] +0x01,0x80,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x8a,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x8a,0x73,0x72,0x71,0x3f + +# GFX12: s_max_i32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x8a,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x8a,0x56,0x34,0x12,0xaf + +# GFX12: s_max_i32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x8a] +0x01,0xc1,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x8a] +0x01,0xf7,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x8a] +0x01,0x7f,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x8a] +0x01,0x7e,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x8a] +0x01,0x7d,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x8a] +0x01,0x67,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8a] +0x01,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x8a] +0x01,0x6b,0x00,0x8a + +# GFX12: s_max_i32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x8a] +0x01,0x6a,0x00,0x8a + +# GFX12: s_max_i32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x8a] +0x6b,0x02,0x00,0x8a + +# GFX12: s_max_i32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x8a] +0x6a,0x02,0x00,0x8a + +# GFX12: s_max_i32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x8a] +0x68,0x67,0x69,0x8a + +# GFX12: s_max_i32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x8a] +0x68,0x02,0x69,0x8a + +# GFX12: s_max_i32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x8a] +0x01,0x67,0x69,0x8a + +# GFX12: s_max_i32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x8a] +0x01,0x02,0x69,0x8a + +# GFX12: s_max_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x8a] +0x01,0x02,0x6b,0x8a + +# GFX12: s_max_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x8a] +0x01,0x02,0x6a,0x8a + +# GFX12: s_max_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x8a] +0x01,0x02,0xff,0x8a + +# GFX12: s_max_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x8a] +0x01,0x02,0xfe,0x8a + +# GFX12: s_max_u32 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x8a] +0x01,0x02,0xfd,0x8a + +# GFX12: s_max_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x8a] +0xf0,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x8a] +0x80,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x8a,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x8a,0x73,0x72,0x71,0x3f + +# GFX12: s_max_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x8a,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x8a,0x56,0x34,0x12,0xaf + +# GFX12: s_max_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x8a] +0xc1,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x8a] +0xf7,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x8a] +0x7f,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x8a] +0x7e,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x8a] +0x7d,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x8a] +0x68,0x67,0x80,0x8a + +# GFX12: s_max_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x8a] +0x68,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x8a] +0x01,0xf0,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x8a] +0x01,0x80,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x8a,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x8a,0x73,0x72,0x71,0x3f + +# GFX12: s_max_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x8a,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x8a,0x56,0x34,0x12,0xaf + +# GFX12: s_max_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x8a] +0x01,0xc1,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x8a] +0x01,0xf7,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x8a] +0x01,0x7f,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x8a] +0x01,0x7e,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x8a] +0x01,0x7d,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x8a] +0x01,0x67,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x8a] +0x01,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x8a] +0x01,0x6b,0x80,0x8a + +# GFX12: s_max_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x8a] +0x01,0x6a,0x80,0x8a + +# GFX12: s_max_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x8a] +0x6b,0x02,0x80,0x8a + +# GFX12: s_max_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x8a] +0x6a,0x02,0x80,0x8a + +# GFX12: s_max_u32 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x8a] +0x68,0x67,0xe9,0x8a + +# GFX12: s_max_u32 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x8a] +0x68,0x02,0xe9,0x8a + +# GFX12: s_max_u32 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x8a] +0x01,0x67,0xe9,0x8a + +# GFX12: s_max_u32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x8a] +0x01,0x02,0xe9,0x8a + +# GFX12: s_max_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x8a] +0x01,0x02,0xeb,0x8a + +# GFX12: s_max_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x8a] +0x01,0x02,0xea,0x8a + +# GFX12: s_min_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x89] +0x01,0x02,0x7f,0x89 + +# GFX12: s_min_i32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x89] +0x01,0x02,0x7e,0x89 + +# GFX12: s_min_i32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x89] +0x01,0x02,0x7d,0x89 + +# GFX12: s_min_i32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x89] +0xf0,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x89] +0x80,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x89,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x89,0x73,0x72,0x71,0x3f + +# GFX12: s_min_i32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x89,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x89,0x56,0x34,0x12,0xaf + +# GFX12: s_min_i32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x89] +0xc1,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x89] +0xf7,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x89] +0x7f,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x89] +0x7e,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x89] +0x7d,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x89] +0x68,0x67,0x00,0x89 + +# GFX12: s_min_i32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x89] +0x68,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x89] +0x01,0xf0,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x89] +0x01,0x80,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x89,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x89,0x73,0x72,0x71,0x3f + +# GFX12: s_min_i32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x89,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x89,0x56,0x34,0x12,0xaf + +# GFX12: s_min_i32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x89] +0x01,0xc1,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x89] +0x01,0xf7,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x89] +0x01,0x7f,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x89] +0x01,0x7e,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x89] +0x01,0x7d,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x89] +0x01,0x67,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x89] +0x01,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x89] +0x01,0x6b,0x00,0x89 + +# GFX12: s_min_i32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x89] +0x01,0x6a,0x00,0x89 + +# GFX12: s_min_i32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x89] +0x6b,0x02,0x00,0x89 + +# GFX12: s_min_i32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x89] +0x6a,0x02,0x00,0x89 + +# GFX12: s_min_i32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x89] +0x68,0x67,0x69,0x89 + +# GFX12: s_min_i32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x89] +0x68,0x02,0x69,0x89 + +# GFX12: s_min_i32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x89] +0x01,0x67,0x69,0x89 + +# GFX12: s_min_i32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x89] +0x01,0x02,0x69,0x89 + +# GFX12: s_min_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x89] +0x01,0x02,0x6b,0x89 + +# GFX12: s_min_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x89] +0x01,0x02,0x6a,0x89 + +# GFX12: s_min_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x89] +0x01,0x02,0xff,0x89 + +# GFX12: s_min_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x89] +0x01,0x02,0xfe,0x89 + +# GFX12: s_min_u32 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x89] +0x01,0x02,0xfd,0x89 + +# GFX12: s_min_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x89] +0xf0,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x89] +0x80,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x89,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x89,0x73,0x72,0x71,0x3f + +# GFX12: s_min_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x89,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x89,0x56,0x34,0x12,0xaf + +# GFX12: s_min_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x89] +0xc1,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x89] +0xf7,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x89] +0x7f,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x89] +0x7e,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x89] +0x7d,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x89] +0x68,0x67,0x80,0x89 + +# GFX12: s_min_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x89] +0x68,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x89] +0x01,0xf0,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x89] +0x01,0x80,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x89,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x89,0x73,0x72,0x71,0x3f + +# GFX12: s_min_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x89,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x89,0x56,0x34,0x12,0xaf + +# GFX12: s_min_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x89] +0x01,0xc1,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x89] +0x01,0xf7,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x89] +0x01,0x7f,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x89] +0x01,0x7e,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x89] +0x01,0x7d,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x89] +0x01,0x67,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x89] +0x01,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x89] +0x01,0x6b,0x80,0x89 + +# GFX12: s_min_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x89] +0x01,0x6a,0x80,0x89 + +# GFX12: s_min_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x89] +0x6b,0x02,0x80,0x89 + +# GFX12: s_min_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x89] +0x6a,0x02,0x80,0x89 + +# GFX12: s_min_u32 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x89] +0x68,0x67,0xe9,0x89 + +# GFX12: s_min_u32 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x89] +0x68,0x02,0xe9,0x89 + +# GFX12: s_min_u32 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x89] +0x01,0x67,0xe9,0x89 + +# GFX12: s_min_u32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x89] +0x01,0x02,0xe9,0x89 + +# GFX12: s_min_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x89] +0x01,0x02,0xeb,0x89 + +# GFX12: s_min_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x89] +0x01,0x02,0xea,0x89 + +# GFX12: s_mul_hi_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x97] +0x01,0x02,0x7f,0x97 + +# GFX12: s_mul_hi_i32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x97] +0x01,0x02,0x7e,0x97 + +# GFX12: s_mul_hi_i32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x97] +0x01,0x02,0x7d,0x97 + +# GFX12: s_mul_hi_i32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x97] +0xf0,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x97] +0x80,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x97,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x97,0x73,0x72,0x71,0x3f + +# GFX12: s_mul_hi_i32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x97,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x97,0x56,0x34,0x12,0xaf + +# GFX12: s_mul_hi_i32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x97] +0xc1,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x97] +0xf7,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x97] +0x7f,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x97] +0x7e,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x97] +0x7d,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x97] +0x68,0x67,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x97] +0x68,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x97] +0x01,0xf0,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x97] +0x01,0x80,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x97,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x97,0x73,0x72,0x71,0x3f + +# GFX12: s_mul_hi_i32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x97,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x97,0x56,0x34,0x12,0xaf + +# GFX12: s_mul_hi_i32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x97] +0x01,0xc1,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x97] +0x01,0xf7,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x97] +0x01,0x7f,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x97] +0x01,0x7e,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x97] +0x01,0x7d,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x97] +0x01,0x67,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x97] +0x01,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x97] +0x01,0x6b,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x97] +0x01,0x6a,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x97] +0x6b,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x97] +0x6a,0x02,0x00,0x97 + +# GFX12: s_mul_hi_i32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x97] +0x68,0x67,0x69,0x97 + +# GFX12: s_mul_hi_i32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x97] +0x68,0x02,0x69,0x97 + +# GFX12: s_mul_hi_i32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x97] +0x01,0x67,0x69,0x97 + +# GFX12: s_mul_hi_i32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x97] +0x01,0x02,0x69,0x97 + +# GFX12: s_mul_hi_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x97] +0x01,0x02,0x6b,0x97 + +# GFX12: s_mul_hi_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x97] +0x01,0x02,0x6a,0x97 + +# GFX12: s_mul_hi_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x96] +0x01,0x02,0xff,0x96 + +# GFX12: s_mul_hi_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x96] +0x01,0x02,0xfe,0x96 + +# GFX12: s_mul_hi_u32 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x96] +0x01,0x02,0xfd,0x96 + +# GFX12: s_mul_hi_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x96] +0xf0,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x96] +0x80,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x96,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x96,0x73,0x72,0x71,0x3f + +# GFX12: s_mul_hi_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x96,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x96,0x56,0x34,0x12,0xaf + +# GFX12: s_mul_hi_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x96] +0xc1,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x96] +0xf7,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x96] +0x7f,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x96] +0x7e,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x96] +0x7d,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x96] +0x68,0x67,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x96] +0x68,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x96] +0x01,0xf0,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x96] +0x01,0x80,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x96,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x96,0x73,0x72,0x71,0x3f + +# GFX12: s_mul_hi_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x96,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x96,0x56,0x34,0x12,0xaf + +# GFX12: s_mul_hi_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x96] +0x01,0xc1,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x96] +0x01,0xf7,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x96] +0x01,0x7f,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x96] +0x01,0x7e,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x96] +0x01,0x7d,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x96] +0x01,0x67,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x96] +0x01,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x96] +0x01,0x6b,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x96] +0x01,0x6a,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x96] +0x6b,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x96] +0x6a,0x02,0x80,0x96 + +# GFX12: s_mul_hi_u32 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x96] +0x68,0x67,0xe9,0x96 + +# GFX12: s_mul_hi_u32 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x96] +0x68,0x02,0xe9,0x96 + +# GFX12: s_mul_hi_u32 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x96] +0x01,0x67,0xe9,0x96 + +# GFX12: s_mul_hi_u32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x96] +0x01,0x02,0xe9,0x96 + +# GFX12: s_mul_hi_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x96] +0x01,0x02,0xeb,0x96 + +# GFX12: s_mul_hi_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x96] +0x01,0x02,0xea,0x96 + +# GFX12: s_mul_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x96] +0x01,0x02,0x7f,0x96 + +# GFX12: s_mul_i32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x96] +0x01,0x02,0x7e,0x96 + +# GFX12: s_mul_i32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x96] +0x01,0x02,0x7d,0x96 + +# GFX12: s_mul_i32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x96] +0xf0,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x96] +0x80,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x96,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x96,0x73,0x72,0x71,0x3f + +# GFX12: s_mul_i32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x96,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x96,0x56,0x34,0x12,0xaf + +# GFX12: s_mul_i32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x96] +0xc1,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x96] +0xf7,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x96] +0x7f,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x96] +0x7e,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x96] +0x7d,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x96] +0x68,0x67,0x00,0x96 + +# GFX12: s_mul_i32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x96] +0x68,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x96] +0x01,0xf0,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x96] +0x01,0x80,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x96,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x96,0x73,0x72,0x71,0x3f + +# GFX12: s_mul_i32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x96,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x96,0x56,0x34,0x12,0xaf + +# GFX12: s_mul_i32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x96] +0x01,0xc1,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x96] +0x01,0xf7,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x96] +0x01,0x7f,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x96] +0x01,0x7e,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x96] +0x01,0x7d,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x96] +0x01,0x67,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x96] +0x01,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x96] +0x01,0x6b,0x00,0x96 + +# GFX12: s_mul_i32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x96] +0x01,0x6a,0x00,0x96 + +# GFX12: s_mul_i32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x96] +0x6b,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x96] +0x6a,0x02,0x00,0x96 + +# GFX12: s_mul_i32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x96] +0x68,0x67,0x69,0x96 + +# GFX12: s_mul_i32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x96] +0x68,0x02,0x69,0x96 + +# GFX12: s_mul_i32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x96] +0x01,0x67,0x69,0x96 + +# GFX12: s_mul_i32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x96] +0x01,0x02,0x69,0x96 + +# GFX12: s_mul_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x96] +0x01,0x02,0x6b,0x96 + +# GFX12: s_mul_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x96] +0x01,0x02,0x6a,0x96 + +# GFX12: s_nand_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x8e] +0x01,0x02,0x7f,0x8e + +# GFX12: s_nand_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x8e] +0x01,0x02,0x7e,0x8e + +# GFX12: s_nand_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x8e] +0x01,0x02,0x7d,0x8e + +# GFX12: s_nand_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x8e] +0xf0,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x8e] +0x80,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x8e,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x8e,0x73,0x72,0x71,0x3f + +# GFX12: s_nand_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x8e,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x8e,0x56,0x34,0x12,0xaf + +# GFX12: s_nand_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x8e] +0xc1,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x8e] +0xf7,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x8e] +0x7f,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x8e] +0x7e,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x8e] +0x7d,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x8e] +0x68,0x67,0x00,0x8e + +# GFX12: s_nand_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x8e] +0x68,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x8e] +0x01,0xf0,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x8e] +0x01,0x80,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x8e,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x8e,0x73,0x72,0x71,0x3f + +# GFX12: s_nand_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x8e,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x8e,0x56,0x34,0x12,0xaf + +# GFX12: s_nand_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x8e] +0x01,0xc1,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x8e] +0x01,0xf7,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x8e] +0x01,0x7f,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x8e] +0x01,0x7e,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x8e] +0x01,0x7d,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x8e] +0x01,0x67,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8e] +0x01,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x8e] +0x01,0x6b,0x00,0x8e + +# GFX12: s_nand_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x8e] +0x01,0x6a,0x00,0x8e + +# GFX12: s_nand_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x8e] +0x6b,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x8e] +0x6a,0x02,0x00,0x8e + +# GFX12: s_nand_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x8e] +0x68,0x67,0x69,0x8e + +# GFX12: s_nand_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x8e] +0x68,0x02,0x69,0x8e + +# GFX12: s_nand_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x8e] +0x01,0x67,0x69,0x8e + +# GFX12: s_nand_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x8e] +0x01,0x02,0x69,0x8e + +# GFX12: s_nand_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x8e] +0x01,0x02,0x6b,0x8e + +# GFX12: s_nand_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x8e] +0x01,0x02,0x6a,0x8e + +# GFX12: s_nand_b64 exec, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xfe,0x8e] +0x02,0x04,0xfe,0x8e + +# GFX12: s_nand_b64 s[0:1], 0.5, s[4:5] ; encoding: [0xf0,0x04,0x80,0x8e] +0xf0,0x04,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], 0, s[4:5] ; encoding: [0x80,0x04,0x80,0x8e] +0x80,0x04,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], 0x3f717273, s[4:5] ; encoding: [0xff,0x04,0x80,0x8e,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x8e,0x73,0x72,0x71,0x3f + +# GFX12: s_nand_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf + +# GFX12: s_nand_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8e] +0xc1,0x04,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], -4.0, s[4:5] ; encoding: [0xf7,0x04,0x80,0x8e] +0xf7,0x04,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], exec, s[4:5] ; encoding: [0x7e,0x04,0x80,0x8e] +0x7e,0x04,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[102:103], s[100:101] ; encoding: [0x66,0x64,0x80,0x8e] +0x66,0x64,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[102:103], s[4:5] ; encoding: [0x66,0x04,0x80,0x8e] +0x66,0x04,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x8e] +0x02,0xf0,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x8e] +0x02,0x80,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x8e,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x8e,0x73,0x72,0x71,0x3f + +# GFX12: s_nand_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8e,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x8e,0x56,0x34,0x12,0xaf + +# GFX12: s_nand_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8e] +0x02,0xc1,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x8e] +0x02,0xf7,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8e] +0x02,0x7e,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[2:3], s[100:101] ; encoding: [0x02,0x64,0x80,0x8e] +0x02,0x64,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0x8e] +0x02,0x04,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0x8e] +0x02,0x6a,0x80,0x8e + +# GFX12: s_nand_b64 s[0:1], vcc, s[4:5] ; encoding: [0x6a,0x04,0x80,0x8e] +0x6a,0x04,0x80,0x8e + +# GFX12: s_nand_b64 s[104:105], s[102:103], s[100:101] ; encoding: [0x66,0x64,0xe8,0x8e] +0x66,0x64,0xe8,0x8e + +# GFX12: s_nand_b64 s[104:105], s[102:103], s[4:5] ; encoding: [0x66,0x04,0xe8,0x8e] +0x66,0x04,0xe8,0x8e + +# GFX12: s_nand_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x8e] +0x02,0x64,0xe8,0x8e + +# GFX12: s_nand_b64 s[104:105], s[2:3], s[4:5] ; encoding: [0x02,0x04,0xe8,0x8e] +0x02,0x04,0xe8,0x8e + +# GFX12: s_nand_b64 vcc, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xea,0x8e] +0x02,0x04,0xea,0x8e + +# GFX12: s_nor_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x8f] +0x01,0x02,0x7f,0x8f + +# GFX12: s_nor_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x8f] +0x01,0x02,0x7e,0x8f + +# GFX12: s_nor_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x8f] +0x01,0x02,0x7d,0x8f + +# GFX12: s_nor_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x8f] +0xf0,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x8f] +0x80,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x8f,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x8f,0x73,0x72,0x71,0x3f + +# GFX12: s_nor_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x8f,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x8f,0x56,0x34,0x12,0xaf + +# GFX12: s_nor_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x8f] +0xc1,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x8f] +0xf7,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x8f] +0x7f,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x8f] +0x7e,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x8f] +0x7d,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x8f] +0x68,0x67,0x00,0x8f + +# GFX12: s_nor_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x8f] +0x68,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x8f] +0x01,0xf0,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x8f] +0x01,0x80,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x8f,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x8f,0x73,0x72,0x71,0x3f + +# GFX12: s_nor_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x8f,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x8f,0x56,0x34,0x12,0xaf + +# GFX12: s_nor_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x8f] +0x01,0xc1,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x8f] +0x01,0xf7,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x8f] +0x01,0x7f,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x8f] +0x01,0x7e,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x8f] +0x01,0x7d,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x8f] +0x01,0x67,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8f] +0x01,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x8f] +0x01,0x6b,0x00,0x8f + +# GFX12: s_nor_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x8f] +0x01,0x6a,0x00,0x8f + +# GFX12: s_nor_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x8f] +0x6b,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x8f] +0x6a,0x02,0x00,0x8f + +# GFX12: s_nor_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x8f] +0x68,0x67,0x69,0x8f + +# GFX12: s_nor_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x8f] +0x68,0x02,0x69,0x8f + +# GFX12: s_nor_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x8f] +0x01,0x67,0x69,0x8f + +# GFX12: s_nor_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x8f] +0x01,0x02,0x69,0x8f + +# GFX12: s_nor_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x8f] +0x01,0x02,0x6b,0x8f + +# GFX12: s_nor_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x8f] +0x01,0x02,0x6a,0x8f + +# GFX12: s_nor_b64 exec, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xfe,0x8f] +0x02,0x04,0xfe,0x8f + +# GFX12: s_nor_b64 s[0:1], 0.5, s[4:5] ; encoding: [0xf0,0x04,0x80,0x8f] +0xf0,0x04,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], 0, s[4:5] ; encoding: [0x80,0x04,0x80,0x8f] +0x80,0x04,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], 0x3f717273, s[4:5] ; encoding: [0xff,0x04,0x80,0x8f,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x8f,0x73,0x72,0x71,0x3f + +# GFX12: s_nor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf + +# GFX12: s_nor_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8f] +0xc1,0x04,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], -4.0, s[4:5] ; encoding: [0xf7,0x04,0x80,0x8f] +0xf7,0x04,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], exec, s[4:5] ; encoding: [0x7e,0x04,0x80,0x8f] +0x7e,0x04,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[102:103], s[100:101] ; encoding: [0x66,0x64,0x80,0x8f] +0x66,0x64,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[102:103], s[4:5] ; encoding: [0x66,0x04,0x80,0x8f] +0x66,0x04,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x8f] +0x02,0xf0,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x8f] +0x02,0x80,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x8f,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x8f,0x73,0x72,0x71,0x3f + +# GFX12: s_nor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8f,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x8f,0x56,0x34,0x12,0xaf + +# GFX12: s_nor_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8f] +0x02,0xc1,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x8f] +0x02,0xf7,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8f] +0x02,0x7e,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[2:3], s[100:101] ; encoding: [0x02,0x64,0x80,0x8f] +0x02,0x64,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0x8f] +0x02,0x04,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0x8f] +0x02,0x6a,0x80,0x8f + +# GFX12: s_nor_b64 s[0:1], vcc, s[4:5] ; encoding: [0x6a,0x04,0x80,0x8f] +0x6a,0x04,0x80,0x8f + +# GFX12: s_nor_b64 s[104:105], s[102:103], s[100:101] ; encoding: [0x66,0x64,0xe8,0x8f] +0x66,0x64,0xe8,0x8f + +# GFX12: s_nor_b64 s[104:105], s[102:103], s[4:5] ; encoding: [0x66,0x04,0xe8,0x8f] +0x66,0x04,0xe8,0x8f + +# GFX12: s_nor_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x8f] +0x02,0x64,0xe8,0x8f + +# GFX12: s_nor_b64 s[104:105], s[2:3], s[4:5] ; encoding: [0x02,0x04,0xe8,0x8f] +0x02,0x04,0xe8,0x8f + +# GFX12: s_nor_b64 vcc, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xea,0x8f] +0x02,0x04,0xea,0x8f + +# GFX12: s_or_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x8c] +0x01,0x02,0x7f,0x8c + +# GFX12: s_or_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x8c] +0x01,0x02,0x7e,0x8c + +# GFX12: s_or_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x8c] +0x01,0x02,0x7d,0x8c + +# GFX12: s_or_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x8c] +0xf0,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x8c] +0x80,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x8c,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x8c,0x73,0x72,0x71,0x3f + +# GFX12: s_or_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x8c,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x8c,0x56,0x34,0x12,0xaf + +# GFX12: s_or_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x8c] +0xc1,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x8c] +0xf7,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x8c] +0x7f,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x8c] +0x7e,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x8c] +0x7d,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x8c] +0x68,0x67,0x00,0x8c + +# GFX12: s_or_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x8c] +0x68,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x8c] +0x01,0xf0,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x8c] +0x01,0x80,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x8c,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x8c,0x73,0x72,0x71,0x3f + +# GFX12: s_or_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x8c,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x8c,0x56,0x34,0x12,0xaf + +# GFX12: s_or_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x8c] +0x01,0xc1,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x8c] +0x01,0xf7,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x8c] +0x01,0x7f,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x8c] +0x01,0x7e,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x8c] +0x01,0x7d,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x8c] +0x01,0x67,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8c] +0x01,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x8c] +0x01,0x6b,0x00,0x8c + +# GFX12: s_or_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x8c] +0x01,0x6a,0x00,0x8c + +# GFX12: s_or_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x8c] +0x6b,0x02,0x00,0x8c + +# GFX12: s_or_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x8c] +0x6a,0x02,0x00,0x8c + +# GFX12: s_or_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x8c] +0x68,0x67,0x69,0x8c + +# GFX12: s_or_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x8c] +0x68,0x02,0x69,0x8c + +# GFX12: s_or_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x8c] +0x01,0x67,0x69,0x8c + +# GFX12: s_or_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x8c] +0x01,0x02,0x69,0x8c + +# GFX12: s_or_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x8c] +0x01,0x02,0x6b,0x8c + +# GFX12: s_or_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x8c] +0x01,0x02,0x6a,0x8c + +# GFX12: s_or_b64 exec, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xfe,0x8c] +0x02,0x04,0xfe,0x8c + +# GFX12: s_or_b64 s[0:1], 0.5, s[4:5] ; encoding: [0xf0,0x04,0x80,0x8c] +0xf0,0x04,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], 0, s[4:5] ; encoding: [0x80,0x04,0x80,0x8c] +0x80,0x04,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], 0x3f717273, s[4:5] ; encoding: [0xff,0x04,0x80,0x8c,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x8c,0x73,0x72,0x71,0x3f + +# GFX12: s_or_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf + +# GFX12: s_or_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8c] +0xc1,0x04,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], -4.0, s[4:5] ; encoding: [0xf7,0x04,0x80,0x8c] +0xf7,0x04,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], exec, s[4:5] ; encoding: [0x7e,0x04,0x80,0x8c] +0x7e,0x04,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[102:103], s[100:101] ; encoding: [0x66,0x64,0x80,0x8c] +0x66,0x64,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[102:103], s[4:5] ; encoding: [0x66,0x04,0x80,0x8c] +0x66,0x04,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x8c] +0x02,0xf0,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x8c] +0x02,0x80,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x8c,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x8c,0x73,0x72,0x71,0x3f + +# GFX12: s_or_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8c,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x8c,0x56,0x34,0x12,0xaf + +# GFX12: s_or_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8c] +0x02,0xc1,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x8c] +0x02,0xf7,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8c] +0x02,0x7e,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[2:3], s[100:101] ; encoding: [0x02,0x64,0x80,0x8c] +0x02,0x64,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0x8c] +0x02,0x04,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0x8c] +0x02,0x6a,0x80,0x8c + +# GFX12: s_or_b64 s[0:1], vcc, s[4:5] ; encoding: [0x6a,0x04,0x80,0x8c] +0x6a,0x04,0x80,0x8c + +# GFX12: s_or_b64 s[104:105], s[102:103], s[100:101] ; encoding: [0x66,0x64,0xe8,0x8c] +0x66,0x64,0xe8,0x8c + +# GFX12: s_or_b64 s[104:105], s[102:103], s[4:5] ; encoding: [0x66,0x04,0xe8,0x8c] +0x66,0x04,0xe8,0x8c + +# GFX12: s_or_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x8c] +0x02,0x64,0xe8,0x8c + +# GFX12: s_or_b64 s[104:105], s[2:3], s[4:5] ; encoding: [0x02,0x04,0xe8,0x8c] +0x02,0x04,0xe8,0x8c + +# GFX12: s_or_b64 vcc, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xea,0x8c] +0x02,0x04,0xea,0x8c + +# GFX12: s_or_not1_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x92] +0x01,0x02,0x7f,0x92 + +# GFX12: s_or_not1_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x92] +0x01,0x02,0x7e,0x92 + +# GFX12: s_or_not1_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x92] +0x01,0x02,0x7d,0x92 + +# GFX12: s_or_not1_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x92] +0xf0,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x92] +0x80,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x92,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x92,0x73,0x72,0x71,0x3f + +# GFX12: s_or_not1_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x92,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x92,0x56,0x34,0x12,0xaf + +# GFX12: s_or_not1_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x92] +0xc1,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x92] +0xf7,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x92] +0x7f,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x92] +0x7e,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x92] +0x7d,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x92] +0x68,0x67,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x92] +0x68,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x92] +0x01,0xf0,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x92] +0x01,0x80,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x92,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x92,0x73,0x72,0x71,0x3f + +# GFX12: s_or_not1_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x92,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x92,0x56,0x34,0x12,0xaf + +# GFX12: s_or_not1_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x92] +0x01,0xc1,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x92] +0x01,0xf7,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x92] +0x01,0x7f,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x92] +0x01,0x7e,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x92] +0x01,0x7d,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x92] +0x01,0x67,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x92] +0x01,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x92] +0x01,0x6b,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x92] +0x01,0x6a,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x92] +0x6b,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x92] +0x6a,0x02,0x00,0x92 + +# GFX12: s_or_not1_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x92] +0x68,0x67,0x69,0x92 + +# GFX12: s_or_not1_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x92] +0x68,0x02,0x69,0x92 + +# GFX12: s_or_not1_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x92] +0x01,0x67,0x69,0x92 + +# GFX12: s_or_not1_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x92] +0x01,0x02,0x69,0x92 + +# GFX12: s_or_not1_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x92] +0x01,0x02,0x6b,0x92 + +# GFX12: s_or_not1_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x92] +0x01,0x02,0x6a,0x92 + +# GFX12: s_or_not1_b64 exec, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xfe,0x92] +0x02,0x04,0xfe,0x92 + +# GFX12: s_or_not1_b64 s[0:1], 0.5, s[4:5] ; encoding: [0xf0,0x04,0x80,0x92] +0xf0,0x04,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], 0, s[4:5] ; encoding: [0x80,0x04,0x80,0x92] +0x80,0x04,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], 0x3f717273, s[4:5] ; encoding: [0xff,0x04,0x80,0x92,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x92,0x73,0x72,0x71,0x3f + +# GFX12: s_or_not1_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x92,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x92,0x56,0x34,0x12,0xaf + +# GFX12: s_or_not1_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x92] +0xc1,0x04,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], -4.0, s[4:5] ; encoding: [0xf7,0x04,0x80,0x92] +0xf7,0x04,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], exec, s[4:5] ; encoding: [0x7e,0x04,0x80,0x92] +0x7e,0x04,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[102:103], s[100:101] ; encoding: [0x66,0x64,0x80,0x92] +0x66,0x64,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[102:103], s[4:5] ; encoding: [0x66,0x04,0x80,0x92] +0x66,0x04,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x92] +0x02,0xf0,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x92] +0x02,0x80,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x92,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x92,0x73,0x72,0x71,0x3f + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x92,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x92,0x56,0x34,0x12,0xaf + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x92] +0x02,0xc1,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x92] +0x02,0xf7,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x92] +0x02,0x7e,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], s[100:101] ; encoding: [0x02,0x64,0x80,0x92] +0x02,0x64,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0x92] +0x02,0x04,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0x92] +0x02,0x6a,0x80,0x92 + +# GFX12: s_or_not1_b64 s[0:1], vcc, s[4:5] ; encoding: [0x6a,0x04,0x80,0x92] +0x6a,0x04,0x80,0x92 + +# GFX12: s_or_not1_b64 s[104:105], s[102:103], s[100:101] ; encoding: [0x66,0x64,0xe8,0x92] +0x66,0x64,0xe8,0x92 + +# GFX12: s_or_not1_b64 s[104:105], s[102:103], s[4:5] ; encoding: [0x66,0x04,0xe8,0x92] +0x66,0x04,0xe8,0x92 + +# GFX12: s_or_not1_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x92] +0x02,0x64,0xe8,0x92 + +# GFX12: s_or_not1_b64 s[104:105], s[2:3], s[4:5] ; encoding: [0x02,0x04,0xe8,0x92] +0x02,0x04,0xe8,0x92 + +# GFX12: s_or_not1_b64 vcc, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xea,0x92] +0x02,0x04,0xea,0x92 + +# GFX12: s_pack_hh_b32_b16 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x9a] +0x01,0x02,0x7f,0x9a + +# GFX12: s_pack_hh_b32_b16 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x9a] +0x01,0x02,0x7e,0x9a + +# GFX12: s_pack_hh_b32_b16 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x9a] +0x01,0x02,0x7d,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x9a] +0xf0,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x9a] +0x80,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x9a,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x9a,0x73,0x72,0x71,0x3f + +# GFX12: s_pack_hh_b32_b16 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x9a,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x9a,0x56,0x34,0x12,0xaf + +# GFX12: s_pack_hh_b32_b16 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x9a] +0xc1,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x9a] +0xf7,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x9a] +0x7f,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x9a] +0x7e,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x9a] +0x7d,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x9a] +0x68,0x67,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x9a] +0x68,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x9a] +0x01,0xf0,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x9a] +0x01,0x80,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x9a,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x9a,0x73,0x72,0x71,0x3f + +# GFX12: s_pack_hh_b32_b16 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x9a,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x9a,0x56,0x34,0x12,0xaf + +# GFX12: s_pack_hh_b32_b16 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x9a] +0x01,0xc1,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x9a] +0x01,0xf7,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x9a] +0x01,0x7f,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x9a] +0x01,0x7e,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x9a] +0x01,0x7d,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x9a] +0x01,0x67,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x9a] +0x01,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x9a] +0x01,0x6b,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x9a] +0x01,0x6a,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x9a] +0x6b,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x9a] +0x6a,0x02,0x00,0x9a + +# GFX12: s_pack_hh_b32_b16 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x9a] +0x68,0x67,0x69,0x9a + +# GFX12: s_pack_hh_b32_b16 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x9a] +0x68,0x02,0x69,0x9a + +# GFX12: s_pack_hh_b32_b16 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x9a] +0x01,0x67,0x69,0x9a + +# GFX12: s_pack_hh_b32_b16 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x9a] +0x01,0x02,0x69,0x9a + +# GFX12: s_pack_hh_b32_b16 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x9a] +0x01,0x02,0x6b,0x9a + +# GFX12: s_pack_hh_b32_b16 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x9a] +0x01,0x02,0x6a,0x9a + +# GFX12: s_pack_lh_b32_b16 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x99] +0x01,0x02,0xff,0x99 + +# GFX12: s_pack_lh_b32_b16 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x99] +0x01,0x02,0xfe,0x99 + +# GFX12: s_pack_lh_b32_b16 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x99] +0x01,0x02,0xfd,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x99] +0xf0,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x99] +0x80,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x99,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x99,0x73,0x72,0x71,0x3f + +# GFX12: s_pack_lh_b32_b16 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x99,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x99,0x56,0x34,0x12,0xaf + +# GFX12: s_pack_lh_b32_b16 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x99] +0xc1,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x99] +0xf7,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x99] +0x7f,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x99] +0x7e,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x99] +0x7d,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x99] +0x68,0x67,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x99] +0x68,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x99] +0x01,0xf0,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x99] +0x01,0x80,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x99,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x99,0x73,0x72,0x71,0x3f + +# GFX12: s_pack_lh_b32_b16 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x99,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x99,0x56,0x34,0x12,0xaf + +# GFX12: s_pack_lh_b32_b16 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x99] +0x01,0xc1,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x99] +0x01,0xf7,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x99] +0x01,0x7f,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x99] +0x01,0x7e,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x99] +0x01,0x7d,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x99] +0x01,0x67,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x99] +0x01,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x99] +0x01,0x6b,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x99] +0x01,0x6a,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x99] +0x6b,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x99] +0x6a,0x02,0x80,0x99 + +# GFX12: s_pack_lh_b32_b16 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x99] +0x68,0x67,0xe9,0x99 + +# GFX12: s_pack_lh_b32_b16 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x99] +0x68,0x02,0xe9,0x99 + +# GFX12: s_pack_lh_b32_b16 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x99] +0x01,0x67,0xe9,0x99 + +# GFX12: s_pack_lh_b32_b16 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x99] +0x01,0x02,0xe9,0x99 + +# GFX12: s_pack_lh_b32_b16 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x99] +0x01,0x02,0xeb,0x99 + +# GFX12: s_pack_lh_b32_b16 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x99] +0x01,0x02,0xea,0x99 + +# GFX12: s_pack_ll_b32_b16 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x99] +0x01,0x02,0x7f,0x99 + +# GFX12: s_pack_ll_b32_b16 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x99] +0x01,0x02,0x7e,0x99 + +# GFX12: s_pack_ll_b32_b16 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x99] +0x01,0x02,0x7d,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x99] +0xf0,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x99] +0x80,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x99,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x99,0x73,0x72,0x71,0x3f + +# GFX12: s_pack_ll_b32_b16 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x99,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x99,0x56,0x34,0x12,0xaf + +# GFX12: s_pack_ll_b32_b16 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x99] +0xc1,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x99] +0xf7,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x99] +0x7f,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x99] +0x7e,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x99] +0x7d,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x99] +0x68,0x67,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x99] +0x68,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x99] +0x01,0xf0,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x99] +0x01,0x80,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x99,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x99,0x73,0x72,0x71,0x3f + +# GFX12: s_pack_ll_b32_b16 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x99,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x99,0x56,0x34,0x12,0xaf + +# GFX12: s_pack_ll_b32_b16 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x99] +0x01,0xc1,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x99] +0x01,0xf7,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x99] +0x01,0x7f,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x99] +0x01,0x7e,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x99] +0x01,0x7d,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x99] +0x01,0x67,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x99] +0x01,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x99] +0x01,0x6b,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x99] +0x01,0x6a,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x99] +0x6b,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x99] +0x6a,0x02,0x00,0x99 + +# GFX12: s_pack_ll_b32_b16 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x99] +0x68,0x67,0x69,0x99 + +# GFX12: s_pack_ll_b32_b16 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x99] +0x68,0x02,0x69,0x99 + +# GFX12: s_pack_ll_b32_b16 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x99] +0x01,0x67,0x69,0x99 + +# GFX12: s_pack_ll_b32_b16 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x99] +0x01,0x02,0x69,0x99 + +# GFX12: s_pack_ll_b32_b16 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x99] +0x01,0x02,0x6b,0x99 + +# GFX12: s_pack_ll_b32_b16 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x99] +0x01,0x02,0x6a,0x99 + +# GFX12: s_sub_co_ci_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x82] +0x01,0x02,0xff,0x82 + +# GFX12: s_sub_co_ci_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x82] +0x01,0x02,0xfe,0x82 + +# GFX12: s_sub_co_ci_u32 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x82] +0x01,0x02,0xfd,0x82 + +# GFX12: s_sub_co_ci_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x82] +0xf0,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x82] +0x80,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x82,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x82,0x73,0x72,0x71,0x3f + +# GFX12: s_sub_co_ci_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x82,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x82,0x56,0x34,0x12,0xaf + +# GFX12: s_sub_co_ci_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x82] +0xc1,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x82] +0xf7,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x82] +0x7f,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x82] +0x7e,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x82] +0x7d,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x82] +0x68,0x67,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x82] +0x68,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x82] +0x01,0xf0,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x82] +0x01,0x80,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x82,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x82,0x73,0x72,0x71,0x3f + +# GFX12: s_sub_co_ci_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x82,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x82,0x56,0x34,0x12,0xaf + +# GFX12: s_sub_co_ci_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x82] +0x01,0xc1,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x82] +0x01,0xf7,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x82] +0x01,0x7f,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x82] +0x01,0x7e,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x82] +0x01,0x7d,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x82] +0x01,0x67,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x82] +0x01,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x82] +0x01,0x6b,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x82] +0x01,0x6a,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x82] +0x6b,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x82] +0x6a,0x02,0x80,0x82 + +# GFX12: s_sub_co_ci_u32 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x82] +0x68,0x67,0xe9,0x82 + +# GFX12: s_sub_co_ci_u32 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x82] +0x68,0x02,0xe9,0x82 + +# GFX12: s_sub_co_ci_u32 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x82] +0x01,0x67,0xe9,0x82 + +# GFX12: s_sub_co_ci_u32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x82] +0x01,0x02,0xe9,0x82 + +# GFX12: s_sub_co_ci_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x82] +0x01,0x02,0xeb,0x82 + +# GFX12: s_sub_co_ci_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x82] +0x01,0x02,0xea,0x82 + +# GFX12: s_sub_co_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x81] +0x01,0x02,0xff,0x81 + +# GFX12: s_sub_co_i32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x81] +0x01,0x02,0xfe,0x81 + +# GFX12: s_sub_co_i32 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x81] +0x01,0x02,0xfd,0x81 + +# GFX12: s_sub_co_i32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x81] +0xf0,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x81] +0x80,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x81,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x81,0x73,0x72,0x71,0x3f + +# GFX12: s_sub_co_i32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x81,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x81,0x56,0x34,0x12,0xaf + +# GFX12: s_sub_co_i32 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x81] +0xc1,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x81] +0xf7,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x81] +0x7f,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x81] +0x7e,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x81] +0x7d,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x81] +0x68,0x67,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x81] +0x68,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x81] +0x01,0xf0,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x81] +0x01,0x80,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x81,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x81,0x73,0x72,0x71,0x3f + +# GFX12: s_sub_co_i32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x81,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x81,0x56,0x34,0x12,0xaf + +# GFX12: s_sub_co_i32 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x81] +0x01,0xc1,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x81] +0x01,0xf7,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x81] +0x01,0x7f,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x81] +0x01,0x7e,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x81] +0x01,0x7d,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x81] +0x01,0x67,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x81] +0x01,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x81] +0x01,0x6b,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x81] +0x01,0x6a,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x81] +0x6b,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x81] +0x6a,0x02,0x80,0x81 + +# GFX12: s_sub_co_i32 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x81] +0x68,0x67,0xe9,0x81 + +# GFX12: s_sub_co_i32 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x81] +0x68,0x02,0xe9,0x81 + +# GFX12: s_sub_co_i32 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x81] +0x01,0x67,0xe9,0x81 + +# GFX12: s_sub_co_i32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x81] +0x01,0x02,0xe9,0x81 + +# GFX12: s_sub_co_i32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x81] +0x01,0x02,0xeb,0x81 + +# GFX12: s_sub_co_i32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x81] +0x01,0x02,0xea,0x81 + +# GFX12: s_sub_co_u32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0xff,0x80] +0x01,0x02,0xff,0x80 + +# GFX12: s_sub_co_u32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0xfe,0x80] +0x01,0x02,0xfe,0x80 + +# GFX12: s_sub_co_u32 m0, s1, s2 ; encoding: [0x01,0x02,0xfd,0x80] +0x01,0x02,0xfd,0x80 + +# GFX12: s_sub_co_u32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x80,0x80] +0xf0,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, 0, s2 ; encoding: [0x80,0x02,0x80,0x80] +0x80,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x80,0x80,0x73,0x72,0x71,0x3f] +0xff,0x02,0x80,0x80,0x73,0x72,0x71,0x3f + +# GFX12: s_sub_co_u32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x80,0x80,0x56,0x34,0x12,0xaf] +0xff,0x02,0x80,0x80,0x56,0x34,0x12,0xaf + +# GFX12: s_sub_co_u32 s0, -1, s2 ; encoding: [0xc1,0x02,0x80,0x80] +0xc1,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x80,0x80] +0xf7,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x80,0x80] +0x7f,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x80,0x80] +0x7e,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, m0, s2 ; encoding: [0x7d,0x02,0x80,0x80] +0x7d,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s104, s103 ; encoding: [0x68,0x67,0x80,0x80] +0x68,0x67,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s104, s2 ; encoding: [0x68,0x02,0x80,0x80] +0x68,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x80,0x80] +0x01,0xf0,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, 0 ; encoding: [0x01,0x80,0x80,0x80] +0x01,0x80,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x80,0x80,0x73,0x72,0x71,0x3f] +0x01,0xff,0x80,0x80,0x73,0x72,0x71,0x3f + +# GFX12: s_sub_co_u32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x80,0x80,0x56,0x34,0x12,0xaf] +0x01,0xff,0x80,0x80,0x56,0x34,0x12,0xaf + +# GFX12: s_sub_co_u32 s0, s1, -1 ; encoding: [0x01,0xc1,0x80,0x80] +0x01,0xc1,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x80,0x80] +0x01,0xf7,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x80,0x80] +0x01,0x7f,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x80,0x80] +0x01,0x7e,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, m0 ; encoding: [0x01,0x7d,0x80,0x80] +0x01,0x7d,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, s103 ; encoding: [0x01,0x67,0x80,0x80] +0x01,0x67,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, s2 ; encoding: [0x01,0x02,0x80,0x80] +0x01,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x80,0x80] +0x01,0x6b,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x80,0x80] +0x01,0x6a,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x80,0x80] +0x6b,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x80,0x80] +0x6a,0x02,0x80,0x80 + +# GFX12: s_sub_co_u32 s105, s104, s103 ; encoding: [0x68,0x67,0xe9,0x80] +0x68,0x67,0xe9,0x80 + +# GFX12: s_sub_co_u32 s105, s104, s2 ; encoding: [0x68,0x02,0xe9,0x80] +0x68,0x02,0xe9,0x80 + +# GFX12: s_sub_co_u32 s105, s1, s103 ; encoding: [0x01,0x67,0xe9,0x80] +0x01,0x67,0xe9,0x80 + +# GFX12: s_sub_co_u32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0x80] +0x01,0x02,0xe9,0x80 + +# GFX12: s_sub_co_u32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0xeb,0x80] +0x01,0x02,0xeb,0x80 + +# GFX12: s_sub_co_u32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0xea,0x80] +0x01,0x02,0xea,0x80 + +# GFX12: s_xnor_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x90] +0x01,0x02,0x7f,0x90 + +# GFX12: s_xnor_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x90] +0x01,0x02,0x7e,0x90 + +# GFX12: s_xnor_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x90] +0x01,0x02,0x7d,0x90 + +# GFX12: s_xnor_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x90] +0xf0,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x90] +0x80,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x90,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x90,0x73,0x72,0x71,0x3f + +# GFX12: s_xnor_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x90,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x90,0x56,0x34,0x12,0xaf + +# GFX12: s_xnor_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x90] +0xc1,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x90] +0xf7,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x90] +0x7f,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x90] +0x7e,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x90] +0x7d,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x90] +0x68,0x67,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x90] +0x68,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x90] +0x01,0xf0,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x90] +0x01,0x80,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x90,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x90,0x73,0x72,0x71,0x3f + +# GFX12: s_xnor_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x90,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x90,0x56,0x34,0x12,0xaf + +# GFX12: s_xnor_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x90] +0x01,0xc1,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x90] +0x01,0xf7,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x90] +0x01,0x7f,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x90] +0x01,0x7e,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x90] +0x01,0x7d,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x90] +0x01,0x67,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x90] +0x01,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x90] +0x01,0x6b,0x00,0x90 + +# GFX12: s_xnor_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x90] +0x01,0x6a,0x00,0x90 + +# GFX12: s_xnor_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x90] +0x6b,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x90] +0x6a,0x02,0x00,0x90 + +# GFX12: s_xnor_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x90] +0x68,0x67,0x69,0x90 + +# GFX12: s_xnor_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x90] +0x68,0x02,0x69,0x90 + +# GFX12: s_xnor_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x90] +0x01,0x67,0x69,0x90 + +# GFX12: s_xnor_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x90] +0x01,0x02,0x69,0x90 + +# GFX12: s_xnor_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x90] +0x01,0x02,0x6b,0x90 + +# GFX12: s_xnor_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x90] +0x01,0x02,0x6a,0x90 + +# GFX12: s_xnor_b64 exec, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xfe,0x90] +0x02,0x04,0xfe,0x90 + +# GFX12: s_xnor_b64 s[0:1], 0.5, s[4:5] ; encoding: [0xf0,0x04,0x80,0x90] +0xf0,0x04,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], 0, s[4:5] ; encoding: [0x80,0x04,0x80,0x90] +0x80,0x04,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], 0x3f717273, s[4:5] ; encoding: [0xff,0x04,0x80,0x90,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x90,0x73,0x72,0x71,0x3f + +# GFX12: s_xnor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x90,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x90,0x56,0x34,0x12,0xaf + +# GFX12: s_xnor_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x90] +0xc1,0x04,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], -4.0, s[4:5] ; encoding: [0xf7,0x04,0x80,0x90] +0xf7,0x04,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], exec, s[4:5] ; encoding: [0x7e,0x04,0x80,0x90] +0x7e,0x04,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[102:103], s[100:101] ; encoding: [0x66,0x64,0x80,0x90] +0x66,0x64,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[102:103], s[4:5] ; encoding: [0x66,0x04,0x80,0x90] +0x66,0x04,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x90] +0x02,0xf0,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x90] +0x02,0x80,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x90,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x90,0x73,0x72,0x71,0x3f + +# GFX12: s_xnor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x90,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x90,0x56,0x34,0x12,0xaf + +# GFX12: s_xnor_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x90] +0x02,0xc1,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x90] +0x02,0xf7,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x90] +0x02,0x7e,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[2:3], s[100:101] ; encoding: [0x02,0x64,0x80,0x90] +0x02,0x64,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0x90] +0x02,0x04,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0x90] +0x02,0x6a,0x80,0x90 + +# GFX12: s_xnor_b64 s[0:1], vcc, s[4:5] ; encoding: [0x6a,0x04,0x80,0x90] +0x6a,0x04,0x80,0x90 + +# GFX12: s_xnor_b64 s[104:105], s[102:103], s[100:101] ; encoding: [0x66,0x64,0xe8,0x90] +0x66,0x64,0xe8,0x90 + +# GFX12: s_xnor_b64 s[104:105], s[102:103], s[4:5] ; encoding: [0x66,0x04,0xe8,0x90] +0x66,0x04,0xe8,0x90 + +# GFX12: s_xnor_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x90] +0x02,0x64,0xe8,0x90 + +# GFX12: s_xnor_b64 s[104:105], s[2:3], s[4:5] ; encoding: [0x02,0x04,0xe8,0x90] +0x02,0x04,0xe8,0x90 + +# GFX12: s_xnor_b64 vcc, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xea,0x90] +0x02,0x04,0xea,0x90 + +# GFX12: s_xor_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x8d] +0x01,0x02,0x7f,0x8d + +# GFX12: s_xor_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x8d] +0x01,0x02,0x7e,0x8d + +# GFX12: s_xor_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7d,0x8d] +0x01,0x02,0x7d,0x8d + +# GFX12: s_xor_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x8d] +0xf0,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x8d] +0x80,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x8d,0x73,0x72,0x71,0x3f] +0xff,0x02,0x00,0x8d,0x73,0x72,0x71,0x3f + +# GFX12: s_xor_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x8d,0x56,0x34,0x12,0xaf] +0xff,0x02,0x00,0x8d,0x56,0x34,0x12,0xaf + +# GFX12: s_xor_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x8d] +0xc1,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x8d] +0xf7,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x8d] +0x7f,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, exec_lo, s2 ; encoding: [0x7e,0x02,0x00,0x8d] +0x7e,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, m0, s2 ; encoding: [0x7d,0x02,0x00,0x8d] +0x7d,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, s104, s103 ; encoding: [0x68,0x67,0x00,0x8d] +0x68,0x67,0x00,0x8d + +# GFX12: s_xor_b32 s0, s104, s2 ; encoding: [0x68,0x02,0x00,0x8d] +0x68,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, 0.5 ; encoding: [0x01,0xf0,0x00,0x8d] +0x01,0xf0,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, 0 ; encoding: [0x01,0x80,0x00,0x8d] +0x01,0x80,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, 0x3f717273 ; encoding: [0x01,0xff,0x00,0x8d,0x73,0x72,0x71,0x3f] +0x01,0xff,0x00,0x8d,0x73,0x72,0x71,0x3f + +# GFX12: s_xor_b32 s0, s1, 0xaf123456 ; encoding: [0x01,0xff,0x00,0x8d,0x56,0x34,0x12,0xaf] +0x01,0xff,0x00,0x8d,0x56,0x34,0x12,0xaf + +# GFX12: s_xor_b32 s0, s1, -1 ; encoding: [0x01,0xc1,0x00,0x8d] +0x01,0xc1,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, -4.0 ; encoding: [0x01,0xf7,0x00,0x8d] +0x01,0xf7,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, exec_hi ; encoding: [0x01,0x7f,0x00,0x8d] +0x01,0x7f,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, exec_lo ; encoding: [0x01,0x7e,0x00,0x8d] +0x01,0x7e,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, m0 ; encoding: [0x01,0x7d,0x00,0x8d] +0x01,0x7d,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, s103 ; encoding: [0x01,0x67,0x00,0x8d] +0x01,0x67,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, s2 ; encoding: [0x01,0x02,0x00,0x8d] +0x01,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, vcc_hi ; encoding: [0x01,0x6b,0x00,0x8d] +0x01,0x6b,0x00,0x8d + +# GFX12: s_xor_b32 s0, s1, vcc_lo ; encoding: [0x01,0x6a,0x00,0x8d] +0x01,0x6a,0x00,0x8d + +# GFX12: s_xor_b32 s0, vcc_hi, s2 ; encoding: [0x6b,0x02,0x00,0x8d] +0x6b,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s0, vcc_lo, s2 ; encoding: [0x6a,0x02,0x00,0x8d] +0x6a,0x02,0x00,0x8d + +# GFX12: s_xor_b32 s105, s104, s103 ; encoding: [0x68,0x67,0x69,0x8d] +0x68,0x67,0x69,0x8d + +# GFX12: s_xor_b32 s105, s104, s2 ; encoding: [0x68,0x02,0x69,0x8d] +0x68,0x02,0x69,0x8d + +# GFX12: s_xor_b32 s105, s1, s103 ; encoding: [0x01,0x67,0x69,0x8d] +0x01,0x67,0x69,0x8d + +# GFX12: s_xor_b32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0x8d] +0x01,0x02,0x69,0x8d + +# GFX12: s_xor_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x8d] +0x01,0x02,0x6b,0x8d + +# GFX12: s_xor_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x8d] +0x01,0x02,0x6a,0x8d + +# GFX12: s_xor_b64 exec, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xfe,0x8d] +0x02,0x04,0xfe,0x8d + +# GFX12: s_xor_b64 s[0:1], 0.5, s[4:5] ; encoding: [0xf0,0x04,0x80,0x8d] +0xf0,0x04,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], 0, s[4:5] ; encoding: [0x80,0x04,0x80,0x8d] +0x80,0x04,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], 0x3f717273, s[4:5] ; encoding: [0xff,0x04,0x80,0x8d,0x73,0x72,0x71,0x3f] +0xff,0x04,0x80,0x8d,0x73,0x72,0x71,0x3f + +# GFX12: s_xor_b64 s[0:1], 0xaf123456, s[4:5] ; encoding: [0xff,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf] +0xff,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf + +# GFX12: s_xor_b64 s[0:1], -1, s[4:5] ; encoding: [0xc1,0x04,0x80,0x8d] +0xc1,0x04,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], -4.0, s[4:5] ; encoding: [0xf7,0x04,0x80,0x8d] +0xf7,0x04,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], exec, s[4:5] ; encoding: [0x7e,0x04,0x80,0x8d] +0x7e,0x04,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[102:103], s[100:101] ; encoding: [0x66,0x64,0x80,0x8d] +0x66,0x64,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[102:103], s[4:5] ; encoding: [0x66,0x04,0x80,0x8d] +0x66,0x04,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[2:3], 0.5 ; encoding: [0x02,0xf0,0x80,0x8d] +0x02,0xf0,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[2:3], 0 ; encoding: [0x02,0x80,0x80,0x8d] +0x02,0x80,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[2:3], 0x3f717273 ; encoding: [0x02,0xff,0x80,0x8d,0x73,0x72,0x71,0x3f] +0x02,0xff,0x80,0x8d,0x73,0x72,0x71,0x3f + +# GFX12: s_xor_b64 s[0:1], s[2:3], 0xaf123456 ; encoding: [0x02,0xff,0x80,0x8d,0x56,0x34,0x12,0xaf] +0x02,0xff,0x80,0x8d,0x56,0x34,0x12,0xaf + +# GFX12: s_xor_b64 s[0:1], s[2:3], -1 ; encoding: [0x02,0xc1,0x80,0x8d] +0x02,0xc1,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[2:3], -4.0 ; encoding: [0x02,0xf7,0x80,0x8d] +0x02,0xf7,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[2:3], exec ; encoding: [0x02,0x7e,0x80,0x8d] +0x02,0x7e,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[2:3], s[100:101] ; encoding: [0x02,0x64,0x80,0x8d] +0x02,0x64,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[2:3], s[4:5] ; encoding: [0x02,0x04,0x80,0x8d] +0x02,0x04,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], s[2:3], vcc ; encoding: [0x02,0x6a,0x80,0x8d] +0x02,0x6a,0x80,0x8d + +# GFX12: s_xor_b64 s[0:1], vcc, s[4:5] ; encoding: [0x6a,0x04,0x80,0x8d] +0x6a,0x04,0x80,0x8d + +# GFX12: s_xor_b64 s[104:105], s[102:103], s[100:101] ; encoding: [0x66,0x64,0xe8,0x8d] +0x66,0x64,0xe8,0x8d + +# GFX12: s_xor_b64 s[104:105], s[102:103], s[4:5] ; encoding: [0x66,0x04,0xe8,0x8d] +0x66,0x04,0xe8,0x8d + +# GFX12: s_xor_b64 s[104:105], s[2:3], s[100:101] ; encoding: [0x02,0x64,0xe8,0x8d] +0x02,0x64,0xe8,0x8d + +# GFX12: s_xor_b64 s[104:105], s[2:3], s[4:5] ; encoding: [0x02,0x04,0xe8,0x8d] +0x02,0x04,0xe8,0x8d + +# GFX12: s_xor_b64 vcc, s[2:3], s[4:5] ; encoding: [0x02,0x04,0xea,0x8d] +0x02,0x04,0xea,0x8d + +# GFX12: s_pack_hl_b32_b16 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0x9a] +0x01,0x02,0x85,0x9a + +# GFX12: s_pack_hl_b32_b16 s5, s105, s105 ; encoding: [0x69,0x69,0x85,0x9a] +0x69,0x69,0x85,0x9a + +# GFX12: s_pack_hl_b32_b16 s5, vcc_lo, ttmp15 ; encoding: [0x6a,0x7b,0x85,0x9a] +0x6a,0x7b,0x85,0x9a + +# GFX12: s_pack_hl_b32_b16 s5, vcc_hi, 0xfe0b ; encoding: [0x6b,0xff,0x85,0x9a,0x0b,0xfe,0x00,0x00] +0x6b,0xff,0x85,0x9a,0x0b,0xfe,0x00,0x00 + +# GFX12: s_pack_hl_b32_b16 s5, ttmp15, src_scc ; encoding: [0x7b,0xfd,0x85,0x9a] +0x7b,0xfd,0x85,0x9a + +# GFX12: s_pack_hl_b32_b16 s105, m0, 0.5 ; encoding: [0x7d,0xf0,0xe9,0x9a] +0x7d,0xf0,0xe9,0x9a + +# GFX12: s_pack_hl_b32_b16 vcc_lo, exec_lo, -1 ; encoding: [0x7e,0xc1,0xea,0x9a] +0x7e,0xc1,0xea,0x9a + +# GFX12: s_pack_hl_b32_b16 vcc_hi, exec_hi, null ; encoding: [0x7f,0x7c,0xeb,0x9a] +0x7f,0x7c,0xeb,0x9a + +# GFX12: s_pack_hl_b32_b16 ttmp15, null, exec_lo ; encoding: [0x7c,0x7e,0xfb,0x9a] +0x7c,0x7e,0xfb,0x9a + +# GFX12: s_pack_hl_b32_b16 m0, -1, exec_hi ; encoding: [0xc1,0x7f,0xfd,0x9a] +0xc1,0x7f,0xfd,0x9a + +# GFX12: s_pack_hl_b32_b16 exec_lo, 0.5, m0 ; encoding: [0xf0,0x7d,0xfe,0x9a] +0xf0,0x7d,0xfe,0x9a + +# GFX12: s_pack_hl_b32_b16 exec_hi, src_scc, vcc_lo ; encoding: [0xfd,0x6a,0xff,0x9a] +0xfd,0x6a,0xff,0x9a + +# GFX12: s_pack_hl_b32_b16 null, 0xaf123456, vcc_hi ; encoding: [0xff,0x6b,0xfc,0x9a,0x56,0x34,0x12,0xaf] +0xff,0x6b,0xfc,0x9a,0x56,0x34,0x12,0xaf diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt new file mode 100644 index 000000000000..ad418db854c8 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt @@ -0,0 +1,2161 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s + +# GFX12: s_cmp_lt_f32 s1, s2 ; encoding: [0x01,0x02,0x41,0xbf] +0x01,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 s105, s2 ; encoding: [0x69,0x02,0x41,0xbf] +0x69,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 s101, s2 ; encoding: [0x65,0x02,0x41,0xbf] +0x65,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x41,0xbf] +0x6a,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x41,0xbf] +0x6b,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 m0, s2 ; encoding: [0x7d,0x02,0x41,0xbf] +0x7d,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x41,0xbf] +0x7e,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x41,0xbf] +0x7f,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 0, s2 ; encoding: [0x80,0x02,0x41,0xbf] +0x80,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 -1, s2 ; encoding: [0xc1,0x02,0x41,0xbf] +0xc1,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 0.5, s2 ; encoding: [0xf0,0x02,0x41,0xbf] +0xf0,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x41,0xbf] +0xf7,0x02,0x41,0xbf + +# GFX12: s_cmp_lt_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x41,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x41,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_lt_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x41,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x41,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_lt_f32 s1, s105 ; encoding: [0x01,0x69,0x41,0xbf] +0x01,0x69,0x41,0xbf + +# GFX12: s_cmp_eq_f32 s1, s2 ; encoding: [0x01,0x02,0x42,0xbf] +0x01,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 s105, s2 ; encoding: [0x69,0x02,0x42,0xbf] +0x69,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 s101, s2 ; encoding: [0x65,0x02,0x42,0xbf] +0x65,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x42,0xbf] +0x6a,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x42,0xbf] +0x6b,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 m0, s2 ; encoding: [0x7d,0x02,0x42,0xbf] +0x7d,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x42,0xbf] +0x7e,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x42,0xbf] +0x7f,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 0, s2 ; encoding: [0x80,0x02,0x42,0xbf] +0x80,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 -1, s2 ; encoding: [0xc1,0x02,0x42,0xbf] +0xc1,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 0.5, s2 ; encoding: [0xf0,0x02,0x42,0xbf] +0xf0,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x42,0xbf] +0xf7,0x02,0x42,0xbf + +# GFX12: s_cmp_eq_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x42,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x42,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_eq_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x42,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x42,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_eq_f32 s1, s105 ; encoding: [0x01,0x69,0x42,0xbf] +0x01,0x69,0x42,0xbf + +# GFX12: s_cmp_le_f32 s1, s2 ; encoding: [0x01,0x02,0x43,0xbf] +0x01,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 s105, s2 ; encoding: [0x69,0x02,0x43,0xbf] +0x69,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 s101, s2 ; encoding: [0x65,0x02,0x43,0xbf] +0x65,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x43,0xbf] +0x6a,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x43,0xbf] +0x6b,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 m0, s2 ; encoding: [0x7d,0x02,0x43,0xbf] +0x7d,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x43,0xbf] +0x7e,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x43,0xbf] +0x7f,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 0, s2 ; encoding: [0x80,0x02,0x43,0xbf] +0x80,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 -1, s2 ; encoding: [0xc1,0x02,0x43,0xbf] +0xc1,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 0.5, s2 ; encoding: [0xf0,0x02,0x43,0xbf] +0xf0,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x43,0xbf] +0xf7,0x02,0x43,0xbf + +# GFX12: s_cmp_le_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x43,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x43,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_le_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x43,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x43,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_le_f32 s1, s105 ; encoding: [0x01,0x69,0x43,0xbf] +0x01,0x69,0x43,0xbf + +# GFX12: s_cmp_gt_f32 s1, s2 ; encoding: [0x01,0x02,0x44,0xbf] +0x01,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 s105, s2 ; encoding: [0x69,0x02,0x44,0xbf] +0x69,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 s101, s2 ; encoding: [0x65,0x02,0x44,0xbf] +0x65,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x44,0xbf] +0x6a,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x44,0xbf] +0x6b,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 m0, s2 ; encoding: [0x7d,0x02,0x44,0xbf] +0x7d,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x44,0xbf] +0x7e,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x44,0xbf] +0x7f,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 0, s2 ; encoding: [0x80,0x02,0x44,0xbf] +0x80,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 -1, s2 ; encoding: [0xc1,0x02,0x44,0xbf] +0xc1,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 0.5, s2 ; encoding: [0xf0,0x02,0x44,0xbf] +0xf0,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x44,0xbf] +0xf7,0x02,0x44,0xbf + +# GFX12: s_cmp_gt_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x44,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x44,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_gt_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x44,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x44,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_gt_f32 s1, s105 ; encoding: [0x01,0x69,0x44,0xbf] +0x01,0x69,0x44,0xbf + +# GFX12: s_cmp_lg_f32 s1, s2 ; encoding: [0x01,0x02,0x45,0xbf] +0x01,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 s105, s2 ; encoding: [0x69,0x02,0x45,0xbf] +0x69,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 s101, s2 ; encoding: [0x65,0x02,0x45,0xbf] +0x65,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x45,0xbf] +0x6a,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x45,0xbf] +0x6b,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 m0, s2 ; encoding: [0x7d,0x02,0x45,0xbf] +0x7d,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x45,0xbf] +0x7e,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x45,0xbf] +0x7f,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 0, s2 ; encoding: [0x80,0x02,0x45,0xbf] +0x80,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 -1, s2 ; encoding: [0xc1,0x02,0x45,0xbf] +0xc1,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 0.5, s2 ; encoding: [0xf0,0x02,0x45,0xbf] +0xf0,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x45,0xbf] +0xf7,0x02,0x45,0xbf + +# GFX12: s_cmp_lg_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x45,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x45,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_lg_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x45,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x45,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_lg_f32 s1, s105 ; encoding: [0x01,0x69,0x45,0xbf] +0x01,0x69,0x45,0xbf + +# GFX12: s_cmp_ge_f32 s1, s2 ; encoding: [0x01,0x02,0x46,0xbf] +0x01,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 s105, s2 ; encoding: [0x69,0x02,0x46,0xbf] +0x69,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 s101, s2 ; encoding: [0x65,0x02,0x46,0xbf] +0x65,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x46,0xbf] +0x6a,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x46,0xbf] +0x6b,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 m0, s2 ; encoding: [0x7d,0x02,0x46,0xbf] +0x7d,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x46,0xbf] +0x7e,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x46,0xbf] +0x7f,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 0, s2 ; encoding: [0x80,0x02,0x46,0xbf] +0x80,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 -1, s2 ; encoding: [0xc1,0x02,0x46,0xbf] +0xc1,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 0.5, s2 ; encoding: [0xf0,0x02,0x46,0xbf] +0xf0,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x46,0xbf] +0xf7,0x02,0x46,0xbf + +# GFX12: s_cmp_ge_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x46,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x46,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_ge_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x46,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x46,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_ge_f32 s1, s105 ; encoding: [0x01,0x69,0x46,0xbf] +0x01,0x69,0x46,0xbf + +# GFX12: s_cmp_o_f32 s1, s2 ; encoding: [0x01,0x02,0x47,0xbf] +0x01,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 s105, s2 ; encoding: [0x69,0x02,0x47,0xbf] +0x69,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 s101, s2 ; encoding: [0x65,0x02,0x47,0xbf] +0x65,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x47,0xbf] +0x6a,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x47,0xbf] +0x6b,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 m0, s2 ; encoding: [0x7d,0x02,0x47,0xbf] +0x7d,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x47,0xbf] +0x7e,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x47,0xbf] +0x7f,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 0, s2 ; encoding: [0x80,0x02,0x47,0xbf] +0x80,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 -1, s2 ; encoding: [0xc1,0x02,0x47,0xbf] +0xc1,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 0.5, s2 ; encoding: [0xf0,0x02,0x47,0xbf] +0xf0,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x47,0xbf] +0xf7,0x02,0x47,0xbf + +# GFX12: s_cmp_o_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x47,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x47,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_o_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x47,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x47,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_o_f32 s1, s105 ; encoding: [0x01,0x69,0x47,0xbf] +0x01,0x69,0x47,0xbf + +# GFX12: s_cmp_u_f32 s1, s2 ; encoding: [0x01,0x02,0x48,0xbf] +0x01,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 s105, s2 ; encoding: [0x69,0x02,0x48,0xbf] +0x69,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 s101, s2 ; encoding: [0x65,0x02,0x48,0xbf] +0x65,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x48,0xbf] +0x6a,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x48,0xbf] +0x6b,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 m0, s2 ; encoding: [0x7d,0x02,0x48,0xbf] +0x7d,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x48,0xbf] +0x7e,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x48,0xbf] +0x7f,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 0, s2 ; encoding: [0x80,0x02,0x48,0xbf] +0x80,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 -1, s2 ; encoding: [0xc1,0x02,0x48,0xbf] +0xc1,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 0.5, s2 ; encoding: [0xf0,0x02,0x48,0xbf] +0xf0,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x48,0xbf] +0xf7,0x02,0x48,0xbf + +# GFX12: s_cmp_u_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x48,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x48,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_u_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x48,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x48,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_u_f32 s1, s105 ; encoding: [0x01,0x69,0x48,0xbf] +0x01,0x69,0x48,0xbf + +# GFX12: s_cmp_nge_f32 s1, s2 ; encoding: [0x01,0x02,0x49,0xbf] +0x01,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 s105, s2 ; encoding: [0x69,0x02,0x49,0xbf] +0x69,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 s101, s2 ; encoding: [0x65,0x02,0x49,0xbf] +0x65,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x49,0xbf] +0x6a,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x49,0xbf] +0x6b,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 m0, s2 ; encoding: [0x7d,0x02,0x49,0xbf] +0x7d,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x49,0xbf] +0x7e,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x49,0xbf] +0x7f,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 0, s2 ; encoding: [0x80,0x02,0x49,0xbf] +0x80,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 -1, s2 ; encoding: [0xc1,0x02,0x49,0xbf] +0xc1,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 0.5, s2 ; encoding: [0xf0,0x02,0x49,0xbf] +0xf0,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x49,0xbf] +0xf7,0x02,0x49,0xbf + +# GFX12: s_cmp_nge_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x49,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x49,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_nge_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x49,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x49,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_nge_f32 s1, s105 ; encoding: [0x01,0x69,0x49,0xbf] +0x01,0x69,0x49,0xbf + +# GFX12: s_cmp_nlg_f32 s1, s2 ; encoding: [0x01,0x02,0x4a,0xbf] +0x01,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 s105, s2 ; encoding: [0x69,0x02,0x4a,0xbf] +0x69,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 s101, s2 ; encoding: [0x65,0x02,0x4a,0xbf] +0x65,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x4a,0xbf] +0x6a,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x4a,0xbf] +0x6b,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 m0, s2 ; encoding: [0x7d,0x02,0x4a,0xbf] +0x7d,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x4a,0xbf] +0x7e,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x4a,0xbf] +0x7f,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 0, s2 ; encoding: [0x80,0x02,0x4a,0xbf] +0x80,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 -1, s2 ; encoding: [0xc1,0x02,0x4a,0xbf] +0xc1,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 0.5, s2 ; encoding: [0xf0,0x02,0x4a,0xbf] +0xf0,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x4a,0xbf] +0xf7,0x02,0x4a,0xbf + +# GFX12: s_cmp_nlg_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x4a,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x4a,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_nlg_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x4a,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x4a,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_nlg_f32 s1, s105 ; encoding: [0x01,0x69,0x4a,0xbf] +0x01,0x69,0x4a,0xbf + +# GFX12: s_cmp_ngt_f32 s1, s2 ; encoding: [0x01,0x02,0x4b,0xbf] +0x01,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 s105, s2 ; encoding: [0x69,0x02,0x4b,0xbf] +0x69,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 s101, s2 ; encoding: [0x65,0x02,0x4b,0xbf] +0x65,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x4b,0xbf] +0x6a,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x4b,0xbf] +0x6b,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 m0, s2 ; encoding: [0x7d,0x02,0x4b,0xbf] +0x7d,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x4b,0xbf] +0x7e,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x4b,0xbf] +0x7f,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 0, s2 ; encoding: [0x80,0x02,0x4b,0xbf] +0x80,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 -1, s2 ; encoding: [0xc1,0x02,0x4b,0xbf] +0xc1,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 0.5, s2 ; encoding: [0xf0,0x02,0x4b,0xbf] +0xf0,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x4b,0xbf] +0xf7,0x02,0x4b,0xbf + +# GFX12: s_cmp_ngt_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x4b,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x4b,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_ngt_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x4b,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x4b,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_ngt_f32 s1, s105 ; encoding: [0x01,0x69,0x4b,0xbf] +0x01,0x69,0x4b,0xbf + +# GFX12: s_cmp_nle_f32 s1, s2 ; encoding: [0x01,0x02,0x4c,0xbf] +0x01,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 s105, s2 ; encoding: [0x69,0x02,0x4c,0xbf] +0x69,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 s101, s2 ; encoding: [0x65,0x02,0x4c,0xbf] +0x65,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x4c,0xbf] +0x6a,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x4c,0xbf] +0x6b,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 m0, s2 ; encoding: [0x7d,0x02,0x4c,0xbf] +0x7d,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x4c,0xbf] +0x7e,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x4c,0xbf] +0x7f,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 0, s2 ; encoding: [0x80,0x02,0x4c,0xbf] +0x80,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 -1, s2 ; encoding: [0xc1,0x02,0x4c,0xbf] +0xc1,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 0.5, s2 ; encoding: [0xf0,0x02,0x4c,0xbf] +0xf0,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x4c,0xbf] +0xf7,0x02,0x4c,0xbf + +# GFX12: s_cmp_nle_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x4c,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x4c,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_nle_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x4c,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x4c,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_nle_f32 s1, s105 ; encoding: [0x01,0x69,0x4c,0xbf] +0x01,0x69,0x4c,0xbf + +# GFX12: s_cmp_neq_f32 s1, s2 ; encoding: [0x01,0x02,0x4d,0xbf] +0x01,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 s105, s2 ; encoding: [0x69,0x02,0x4d,0xbf] +0x69,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 s101, s2 ; encoding: [0x65,0x02,0x4d,0xbf] +0x65,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x4d,0xbf] +0x6a,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x4d,0xbf] +0x6b,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 m0, s2 ; encoding: [0x7d,0x02,0x4d,0xbf] +0x7d,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x4d,0xbf] +0x7e,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x4d,0xbf] +0x7f,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 0, s2 ; encoding: [0x80,0x02,0x4d,0xbf] +0x80,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 -1, s2 ; encoding: [0xc1,0x02,0x4d,0xbf] +0xc1,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 0.5, s2 ; encoding: [0xf0,0x02,0x4d,0xbf] +0xf0,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x4d,0xbf] +0xf7,0x02,0x4d,0xbf + +# GFX12: s_cmp_neq_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x4d,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x4d,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_neq_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x4d,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x4d,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_neq_f32 s1, s105 ; encoding: [0x01,0x69,0x4d,0xbf] +0x01,0x69,0x4d,0xbf + +# GFX12: s_cmp_nlt_f32 s1, s2 ; encoding: [0x01,0x02,0x4e,0xbf] +0x01,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 s105, s2 ; encoding: [0x69,0x02,0x4e,0xbf] +0x69,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 s101, s2 ; encoding: [0x65,0x02,0x4e,0xbf] +0x65,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 vcc_lo, s2 ; encoding: [0x6a,0x02,0x4e,0xbf] +0x6a,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 vcc_hi, s2 ; encoding: [0x6b,0x02,0x4e,0xbf] +0x6b,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 m0, s2 ; encoding: [0x7d,0x02,0x4e,0xbf] +0x7d,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 exec_lo, s2 ; encoding: [0x7e,0x02,0x4e,0xbf] +0x7e,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 exec_hi, s2 ; encoding: [0x7f,0x02,0x4e,0xbf] +0x7f,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 0, s2 ; encoding: [0x80,0x02,0x4e,0xbf] +0x80,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 -1, s2 ; encoding: [0xc1,0x02,0x4e,0xbf] +0xc1,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 0.5, s2 ; encoding: [0xf0,0x02,0x4e,0xbf] +0xf0,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 -4.0, s2 ; encoding: [0xf7,0x02,0x4e,0xbf] +0xf7,0x02,0x4e,0xbf + +# GFX12: s_cmp_nlt_f32 0xaf123456, s2 ; encoding: [0xff,0x02,0x4e,0xbf,0x56,0x34,0x12,0xaf] +0xff,0x02,0x4e,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_nlt_f32 0x3f717273, s2 ; encoding: [0xff,0x02,0x4e,0xbf,0x73,0x72,0x71,0x3f] +0xff,0x02,0x4e,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_nlt_f32 s1, s105 ; encoding: [0x01,0x69,0x4e,0xbf] +0x01,0x69,0x4e,0xbf + +# GFX12: s_cmp_lt_f16 s1, s2 ; encoding: [0x01,0x02,0x51,0xbf] +0x01,0x02,0x51,0xbf + +# GFX12: s_cmp_lt_f16 s101, s2 ; encoding: [0x65,0x02,0x51,0xbf] +0x65,0x02,0x51,0xbf + +# GFX12: s_cmp_lt_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x51,0xbf] +0x6a,0x02,0x51,0xbf + +# GFX12: s_cmp_lt_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x51,0xbf] +0x6b,0x02,0x51,0xbf + +# GFX12: s_cmp_lt_f16 m0, s2 ; encoding: [0x7d,0x02,0x51,0xbf] +0x7d,0x02,0x51,0xbf + +# GFX12: s_cmp_lt_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x51,0xbf] +0x7e,0x02,0x51,0xbf + +# GFX12: s_cmp_lt_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x51,0xbf] +0x7f,0x02,0x51,0xbf + +# GFX12: s_cmp_lt_f16 0, s2 ; encoding: [0x80,0x02,0x51,0xbf] +0x80,0x02,0x51,0xbf + +# GFX12: s_cmp_lt_f16 -1, s2 ; encoding: [0xc1,0x02,0x51,0xbf] +0xc1,0x02,0x51,0xbf + +# GFX12: s_cmp_lt_f16 0x3800, s2 ; encoding: [0xff,0x02,0x51,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x51,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_lt_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x51,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x51,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_lt_f16 0x3456, s2 ; encoding: [0xff,0x02,0x51,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x51,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_eq_f16 s1, s2 ; encoding: [0x01,0x02,0x52,0xbf] +0x01,0x02,0x52,0xbf + +# GFX12: s_cmp_eq_f16 s101, s2 ; encoding: [0x65,0x02,0x52,0xbf] +0x65,0x02,0x52,0xbf + +# GFX12: s_cmp_eq_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x52,0xbf] +0x6a,0x02,0x52,0xbf + +# GFX12: s_cmp_eq_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x52,0xbf] +0x6b,0x02,0x52,0xbf + +# GFX12: s_cmp_eq_f16 m0, s2 ; encoding: [0x7d,0x02,0x52,0xbf] +0x7d,0x02,0x52,0xbf + +# GFX12: s_cmp_eq_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x52,0xbf] +0x7e,0x02,0x52,0xbf + +# GFX12: s_cmp_eq_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x52,0xbf] +0x7f,0x02,0x52,0xbf + +# GFX12: s_cmp_eq_f16 0, s2 ; encoding: [0x80,0x02,0x52,0xbf] +0x80,0x02,0x52,0xbf + +# GFX12: s_cmp_eq_f16 -1, s2 ; encoding: [0xc1,0x02,0x52,0xbf] +0xc1,0x02,0x52,0xbf + +# GFX12: s_cmp_eq_f16 0x3800, s2 ; encoding: [0xff,0x02,0x52,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x52,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_eq_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x52,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x52,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_eq_f16 0x3456, s2 ; encoding: [0xff,0x02,0x52,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x52,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_le_f16 s1, s2 ; encoding: [0x01,0x02,0x53,0xbf] +0x01,0x02,0x53,0xbf + +# GFX12: s_cmp_le_f16 s101, s2 ; encoding: [0x65,0x02,0x53,0xbf] +0x65,0x02,0x53,0xbf + +# GFX12: s_cmp_le_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x53,0xbf] +0x6a,0x02,0x53,0xbf + +# GFX12: s_cmp_le_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x53,0xbf] +0x6b,0x02,0x53,0xbf + +# GFX12: s_cmp_le_f16 m0, s2 ; encoding: [0x7d,0x02,0x53,0xbf] +0x7d,0x02,0x53,0xbf + +# GFX12: s_cmp_le_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x53,0xbf] +0x7e,0x02,0x53,0xbf + +# GFX12: s_cmp_le_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x53,0xbf] +0x7f,0x02,0x53,0xbf + +# GFX12: s_cmp_le_f16 0, s2 ; encoding: [0x80,0x02,0x53,0xbf] +0x80,0x02,0x53,0xbf + +# GFX12: s_cmp_le_f16 -1, s2 ; encoding: [0xc1,0x02,0x53,0xbf] +0xc1,0x02,0x53,0xbf + +# GFX12: s_cmp_le_f16 0x3800, s2 ; encoding: [0xff,0x02,0x53,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x53,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_le_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x53,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x53,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_le_f16 0x3456, s2 ; encoding: [0xff,0x02,0x53,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x53,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_gt_f16 s1, s2 ; encoding: [0x01,0x02,0x54,0xbf] +0x01,0x02,0x54,0xbf + +# GFX12: s_cmp_gt_f16 s101, s2 ; encoding: [0x65,0x02,0x54,0xbf] +0x65,0x02,0x54,0xbf + +# GFX12: s_cmp_gt_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x54,0xbf] +0x6a,0x02,0x54,0xbf + +# GFX12: s_cmp_gt_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x54,0xbf] +0x6b,0x02,0x54,0xbf + +# GFX12: s_cmp_gt_f16 m0, s2 ; encoding: [0x7d,0x02,0x54,0xbf] +0x7d,0x02,0x54,0xbf + +# GFX12: s_cmp_gt_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x54,0xbf] +0x7e,0x02,0x54,0xbf + +# GFX12: s_cmp_gt_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x54,0xbf] +0x7f,0x02,0x54,0xbf + +# GFX12: s_cmp_gt_f16 0, s2 ; encoding: [0x80,0x02,0x54,0xbf] +0x80,0x02,0x54,0xbf + +# GFX12: s_cmp_gt_f16 -1, s2 ; encoding: [0xc1,0x02,0x54,0xbf] +0xc1,0x02,0x54,0xbf + +# GFX12: s_cmp_gt_f16 0x3800, s2 ; encoding: [0xff,0x02,0x54,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x54,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_gt_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x54,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x54,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_gt_f16 0x3456, s2 ; encoding: [0xff,0x02,0x54,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x54,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_lg_f16 s1, s2 ; encoding: [0x01,0x02,0x55,0xbf] +0x01,0x02,0x55,0xbf + +# GFX12: s_cmp_lg_f16 s101, s2 ; encoding: [0x65,0x02,0x55,0xbf] +0x65,0x02,0x55,0xbf + +# GFX12: s_cmp_lg_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x55,0xbf] +0x6a,0x02,0x55,0xbf + +# GFX12: s_cmp_lg_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x55,0xbf] +0x6b,0x02,0x55,0xbf + +# GFX12: s_cmp_lg_f16 m0, s2 ; encoding: [0x7d,0x02,0x55,0xbf] +0x7d,0x02,0x55,0xbf + +# GFX12: s_cmp_lg_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x55,0xbf] +0x7e,0x02,0x55,0xbf + +# GFX12: s_cmp_lg_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x55,0xbf] +0x7f,0x02,0x55,0xbf + +# GFX12: s_cmp_lg_f16 0, s2 ; encoding: [0x80,0x02,0x55,0xbf] +0x80,0x02,0x55,0xbf + +# GFX12: s_cmp_lg_f16 -1, s2 ; encoding: [0xc1,0x02,0x55,0xbf] +0xc1,0x02,0x55,0xbf + +# GFX12: s_cmp_lg_f16 0x3800, s2 ; encoding: [0xff,0x02,0x55,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x55,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_lg_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x55,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x55,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_lg_f16 0x3456, s2 ; encoding: [0xff,0x02,0x55,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x55,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_ge_f16 s1, s2 ; encoding: [0x01,0x02,0x56,0xbf] +0x01,0x02,0x56,0xbf + +# GFX12: s_cmp_ge_f16 s101, s2 ; encoding: [0x65,0x02,0x56,0xbf] +0x65,0x02,0x56,0xbf + +# GFX12: s_cmp_ge_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x56,0xbf] +0x6a,0x02,0x56,0xbf + +# GFX12: s_cmp_ge_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x56,0xbf] +0x6b,0x02,0x56,0xbf + +# GFX12: s_cmp_ge_f16 m0, s2 ; encoding: [0x7d,0x02,0x56,0xbf] +0x7d,0x02,0x56,0xbf + +# GFX12: s_cmp_ge_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x56,0xbf] +0x7e,0x02,0x56,0xbf + +# GFX12: s_cmp_ge_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x56,0xbf] +0x7f,0x02,0x56,0xbf + +# GFX12: s_cmp_ge_f16 0, s2 ; encoding: [0x80,0x02,0x56,0xbf] +0x80,0x02,0x56,0xbf + +# GFX12: s_cmp_ge_f16 -1, s2 ; encoding: [0xc1,0x02,0x56,0xbf] +0xc1,0x02,0x56,0xbf + +# GFX12: s_cmp_ge_f16 0x3800, s2 ; encoding: [0xff,0x02,0x56,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x56,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_ge_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x56,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x56,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_ge_f16 0x3456, s2 ; encoding: [0xff,0x02,0x56,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x56,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_o_f16 s1, s2 ; encoding: [0x01,0x02,0x57,0xbf] +0x01,0x02,0x57,0xbf + +# GFX12: s_cmp_o_f16 s101, s2 ; encoding: [0x65,0x02,0x57,0xbf] +0x65,0x02,0x57,0xbf + +# GFX12: s_cmp_o_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x57,0xbf] +0x6a,0x02,0x57,0xbf + +# GFX12: s_cmp_o_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x57,0xbf] +0x6b,0x02,0x57,0xbf + +# GFX12: s_cmp_o_f16 m0, s2 ; encoding: [0x7d,0x02,0x57,0xbf] +0x7d,0x02,0x57,0xbf + +# GFX12: s_cmp_o_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x57,0xbf] +0x7e,0x02,0x57,0xbf + +# GFX12: s_cmp_o_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x57,0xbf] +0x7f,0x02,0x57,0xbf + +# GFX12: s_cmp_o_f16 0, s2 ; encoding: [0x80,0x02,0x57,0xbf] +0x80,0x02,0x57,0xbf + +# GFX12: s_cmp_o_f16 -1, s2 ; encoding: [0xc1,0x02,0x57,0xbf] +0xc1,0x02,0x57,0xbf + +# GFX12: s_cmp_o_f16 0x3800, s2 ; encoding: [0xff,0x02,0x57,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x57,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_o_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x57,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x57,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_o_f16 0x3456, s2 ; encoding: [0xff,0x02,0x57,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x57,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_u_f16 s1, s2 ; encoding: [0x01,0x02,0x58,0xbf] +0x01,0x02,0x58,0xbf + +# GFX12: s_cmp_u_f16 s101, s2 ; encoding: [0x65,0x02,0x58,0xbf] +0x65,0x02,0x58,0xbf + +# GFX12: s_cmp_u_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x58,0xbf] +0x6a,0x02,0x58,0xbf + +# GFX12: s_cmp_u_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x58,0xbf] +0x6b,0x02,0x58,0xbf + +# GFX12: s_cmp_u_f16 m0, s2 ; encoding: [0x7d,0x02,0x58,0xbf] +0x7d,0x02,0x58,0xbf + +# GFX12: s_cmp_u_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x58,0xbf] +0x7e,0x02,0x58,0xbf + +# GFX12: s_cmp_u_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x58,0xbf] +0x7f,0x02,0x58,0xbf + +# GFX12: s_cmp_u_f16 0, s2 ; encoding: [0x80,0x02,0x58,0xbf] +0x80,0x02,0x58,0xbf + +# GFX12: s_cmp_u_f16 -1, s2 ; encoding: [0xc1,0x02,0x58,0xbf] +0xc1,0x02,0x58,0xbf + +# GFX12: s_cmp_u_f16 0x3800, s2 ; encoding: [0xff,0x02,0x58,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x58,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_u_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x58,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x58,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_u_f16 0x3456, s2 ; encoding: [0xff,0x02,0x58,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x58,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_nge_f16 s1, s2 ; encoding: [0x01,0x02,0x59,0xbf] +0x01,0x02,0x59,0xbf + +# GFX12: s_cmp_nge_f16 s101, s2 ; encoding: [0x65,0x02,0x59,0xbf] +0x65,0x02,0x59,0xbf + +# GFX12: s_cmp_nge_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x59,0xbf] +0x6a,0x02,0x59,0xbf + +# GFX12: s_cmp_nge_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x59,0xbf] +0x6b,0x02,0x59,0xbf + +# GFX12: s_cmp_nge_f16 m0, s2 ; encoding: [0x7d,0x02,0x59,0xbf] +0x7d,0x02,0x59,0xbf + +# GFX12: s_cmp_nge_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x59,0xbf] +0x7e,0x02,0x59,0xbf + +# GFX12: s_cmp_nge_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x59,0xbf] +0x7f,0x02,0x59,0xbf + +# GFX12: s_cmp_nge_f16 0, s2 ; encoding: [0x80,0x02,0x59,0xbf] +0x80,0x02,0x59,0xbf + +# GFX12: s_cmp_nge_f16 -1, s2 ; encoding: [0xc1,0x02,0x59,0xbf] +0xc1,0x02,0x59,0xbf + +# GFX12: s_cmp_nge_f16 0x3800, s2 ; encoding: [0xff,0x02,0x59,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x59,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_nge_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x59,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x59,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_nge_f16 0x3456, s2 ; encoding: [0xff,0x02,0x59,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x59,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_nlg_f16 s1, s2 ; encoding: [0x01,0x02,0x5a,0xbf] +0x01,0x02,0x5a,0xbf + +# GFX12: s_cmp_nlg_f16 s101, s2 ; encoding: [0x65,0x02,0x5a,0xbf] +0x65,0x02,0x5a,0xbf + +# GFX12: s_cmp_nlg_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x5a,0xbf] +0x6a,0x02,0x5a,0xbf + +# GFX12: s_cmp_nlg_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x5a,0xbf] +0x6b,0x02,0x5a,0xbf + +# GFX12: s_cmp_nlg_f16 m0, s2 ; encoding: [0x7d,0x02,0x5a,0xbf] +0x7d,0x02,0x5a,0xbf + +# GFX12: s_cmp_nlg_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x5a,0xbf] +0x7e,0x02,0x5a,0xbf + +# GFX12: s_cmp_nlg_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x5a,0xbf] +0x7f,0x02,0x5a,0xbf + +# GFX12: s_cmp_nlg_f16 0, s2 ; encoding: [0x80,0x02,0x5a,0xbf] +0x80,0x02,0x5a,0xbf + +# GFX12: s_cmp_nlg_f16 -1, s2 ; encoding: [0xc1,0x02,0x5a,0xbf] +0xc1,0x02,0x5a,0xbf + +# GFX12: s_cmp_nlg_f16 0x3800, s2 ; encoding: [0xff,0x02,0x5a,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x5a,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_nlg_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x5a,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x5a,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_nlg_f16 0x3456, s2 ; encoding: [0xff,0x02,0x5a,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x5a,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_ngt_f16 s1, s2 ; encoding: [0x01,0x02,0x5b,0xbf] +0x01,0x02,0x5b,0xbf + +# GFX12: s_cmp_ngt_f16 s101, s2 ; encoding: [0x65,0x02,0x5b,0xbf] +0x65,0x02,0x5b,0xbf + +# GFX12: s_cmp_ngt_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x5b,0xbf] +0x6a,0x02,0x5b,0xbf + +# GFX12: s_cmp_ngt_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x5b,0xbf] +0x6b,0x02,0x5b,0xbf + +# GFX12: s_cmp_ngt_f16 m0, s2 ; encoding: [0x7d,0x02,0x5b,0xbf] +0x7d,0x02,0x5b,0xbf + +# GFX12: s_cmp_ngt_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x5b,0xbf] +0x7e,0x02,0x5b,0xbf + +# GFX12: s_cmp_ngt_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x5b,0xbf] +0x7f,0x02,0x5b,0xbf + +# GFX12: s_cmp_ngt_f16 0, s2 ; encoding: [0x80,0x02,0x5b,0xbf] +0x80,0x02,0x5b,0xbf + +# GFX12: s_cmp_ngt_f16 -1, s2 ; encoding: [0xc1,0x02,0x5b,0xbf] +0xc1,0x02,0x5b,0xbf + +# GFX12: s_cmp_ngt_f16 0x3800, s2 ; encoding: [0xff,0x02,0x5b,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x5b,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_ngt_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x5b,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x5b,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_ngt_f16 0x3456, s2 ; encoding: [0xff,0x02,0x5b,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x5b,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_nle_f16 s1, s2 ; encoding: [0x01,0x02,0x5c,0xbf] +0x01,0x02,0x5c,0xbf + +# GFX12: s_cmp_nle_f16 s101, s2 ; encoding: [0x65,0x02,0x5c,0xbf] +0x65,0x02,0x5c,0xbf + +# GFX12: s_cmp_nle_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x5c,0xbf] +0x6a,0x02,0x5c,0xbf + +# GFX12: s_cmp_nle_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x5c,0xbf] +0x6b,0x02,0x5c,0xbf + +# GFX12: s_cmp_nle_f16 m0, s2 ; encoding: [0x7d,0x02,0x5c,0xbf] +0x7d,0x02,0x5c,0xbf + +# GFX12: s_cmp_nle_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x5c,0xbf] +0x7e,0x02,0x5c,0xbf + +# GFX12: s_cmp_nle_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x5c,0xbf] +0x7f,0x02,0x5c,0xbf + +# GFX12: s_cmp_nle_f16 0, s2 ; encoding: [0x80,0x02,0x5c,0xbf] +0x80,0x02,0x5c,0xbf + +# GFX12: s_cmp_nle_f16 -1, s2 ; encoding: [0xc1,0x02,0x5c,0xbf] +0xc1,0x02,0x5c,0xbf + +# GFX12: s_cmp_nle_f16 0x3800, s2 ; encoding: [0xff,0x02,0x5c,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x5c,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_nle_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x5c,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x5c,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_nle_f16 0x3456, s2 ; encoding: [0xff,0x02,0x5c,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x5c,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_neq_f16 s1, s2 ; encoding: [0x01,0x02,0x5d,0xbf] +0x01,0x02,0x5d,0xbf + +# GFX12: s_cmp_neq_f16 s101, s2 ; encoding: [0x65,0x02,0x5d,0xbf] +0x65,0x02,0x5d,0xbf + +# GFX12: s_cmp_neq_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x5d,0xbf] +0x6a,0x02,0x5d,0xbf + +# GFX12: s_cmp_neq_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x5d,0xbf] +0x6b,0x02,0x5d,0xbf + +# GFX12: s_cmp_neq_f16 m0, s2 ; encoding: [0x7d,0x02,0x5d,0xbf] +0x7d,0x02,0x5d,0xbf + +# GFX12: s_cmp_neq_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x5d,0xbf] +0x7e,0x02,0x5d,0xbf + +# GFX12: s_cmp_neq_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x5d,0xbf] +0x7f,0x02,0x5d,0xbf + +# GFX12: s_cmp_neq_f16 0, s2 ; encoding: [0x80,0x02,0x5d,0xbf] +0x80,0x02,0x5d,0xbf + +# GFX12: s_cmp_neq_f16 -1, s2 ; encoding: [0xc1,0x02,0x5d,0xbf] +0xc1,0x02,0x5d,0xbf + +# GFX12: s_cmp_neq_f16 0x3800, s2 ; encoding: [0xff,0x02,0x5d,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x5d,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_neq_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x5d,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x5d,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_neq_f16 0x3456, s2 ; encoding: [0xff,0x02,0x5d,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x5d,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_cmp_nlt_f16 s1, s2 ; encoding: [0x01,0x02,0x5e,0xbf] +0x01,0x02,0x5e,0xbf + +# GFX12: s_cmp_nlt_f16 s101, s2 ; encoding: [0x65,0x02,0x5e,0xbf] +0x65,0x02,0x5e,0xbf + +# GFX12: s_cmp_nlt_f16 vcc_lo, s2 ; encoding: [0x6a,0x02,0x5e,0xbf] +0x6a,0x02,0x5e,0xbf + +# GFX12: s_cmp_nlt_f16 vcc_hi, s2 ; encoding: [0x6b,0x02,0x5e,0xbf] +0x6b,0x02,0x5e,0xbf + +# GFX12: s_cmp_nlt_f16 m0, s2 ; encoding: [0x7d,0x02,0x5e,0xbf] +0x7d,0x02,0x5e,0xbf + +# GFX12: s_cmp_nlt_f16 exec_lo, s2 ; encoding: [0x7e,0x02,0x5e,0xbf] +0x7e,0x02,0x5e,0xbf + +# GFX12: s_cmp_nlt_f16 exec_hi, s2 ; encoding: [0x7f,0x02,0x5e,0xbf] +0x7f,0x02,0x5e,0xbf + +# GFX12: s_cmp_nlt_f16 0, s2 ; encoding: [0x80,0x02,0x5e,0xbf] +0x80,0x02,0x5e,0xbf + +# GFX12: s_cmp_nlt_f16 -1, s2 ; encoding: [0xc1,0x02,0x5e,0xbf] +0xc1,0x02,0x5e,0xbf + +# GFX12: s_cmp_nlt_f16 0x3800, s2 ; encoding: [0xff,0x02,0x5e,0xbf,0x00,0x38,0x00,0x00] +0xff,0x02,0x5e,0xbf,0x00,0x38,0x00,0x00 + +# GFX12: s_cmp_nlt_f16 0xfe0b, s2 ; encoding: [0xff,0x02,0x5e,0xbf,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x5e,0xbf,0x0b,0xfe,0x00,0x00 + +# GFX12: s_cmp_nlt_f16 0x3456, s2 ; encoding: [0xff,0x02,0x5e,0xbf,0x56,0x34,0x00,0x00] +0xff,0x02,0x5e,0xbf,0x56,0x34,0x00,0x00 + +# GFX12: s_bitcmp0_b32 exec_hi, s1 ; encoding: [0x7f,0x01,0x0c,0xbf] +0x7f,0x01,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 exec_lo, s1 ; encoding: [0x7e,0x01,0x0c,0xbf] +0x7e,0x01,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 m0, s1 ; encoding: [0x7d,0x01,0x0c,0xbf] +0x7d,0x01,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, 0.5 ; encoding: [0x00,0xf0,0x0c,0xbf] +0x00,0xf0,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, 0 ; encoding: [0x00,0x80,0x0c,0xbf] +0x00,0x80,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_bitcmp0_b32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_bitcmp0_b32 s0, -1 ; encoding: [0x00,0xc1,0x0c,0xbf] +0x00,0xc1,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, -4.0 ; encoding: [0x00,0xf7,0x0c,0xbf] +0x00,0xf7,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, exec_hi ; encoding: [0x00,0x7f,0x0c,0xbf] +0x00,0x7f,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, exec_lo ; encoding: [0x00,0x7e,0x0c,0xbf] +0x00,0x7e,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, m0 ; encoding: [0x00,0x7d,0x0c,0xbf] +0x00,0x7d,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, s104 ; encoding: [0x00,0x68,0x0c,0xbf] +0x00,0x68,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, s1 ; encoding: [0x00,0x01,0x0c,0xbf] +0x00,0x01,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, vcc_hi ; encoding: [0x00,0x6b,0x0c,0xbf] +0x00,0x6b,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s0, vcc_lo ; encoding: [0x00,0x6a,0x0c,0xbf] +0x00,0x6a,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s105, s104 ; encoding: [0x69,0x68,0x0c,0xbf] +0x69,0x68,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 s105, s1 ; encoding: [0x69,0x01,0x0c,0xbf] +0x69,0x01,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x0c,0xbf] +0x6b,0x01,0x0c,0xbf + +# GFX12: s_bitcmp0_b32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x0c,0xbf] +0x6a,0x01,0x0c,0xbf + +# GFX12: s_bitcmp0_b64 exec, s2 ; encoding: [0x7e,0x02,0x0e,0xbf] +0x7e,0x02,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], 0.5 ; encoding: [0x00,0xf0,0x0e,0xbf] +0x00,0xf0,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], 0 ; encoding: [0x00,0x80,0x0e,0xbf] +0x00,0x80,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], 0x3f717273 ; encoding: [0x00,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_bitcmp0_b64 s[0:1], 0xaf123456 ; encoding: [0x00,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_bitcmp0_b64 s[0:1], -1 ; encoding: [0x00,0xc1,0x0e,0xbf] +0x00,0xc1,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], -4.0 ; encoding: [0x00,0xf7,0x0e,0xbf] +0x00,0xf7,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], exec_hi ; encoding: [0x00,0x7f,0x0e,0xbf] +0x00,0x7f,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], exec_lo ; encoding: [0x00,0x7e,0x0e,0xbf] +0x00,0x7e,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], m0 ; encoding: [0x00,0x7d,0x0e,0xbf] +0x00,0x7d,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], s102 ; encoding: [0x00,0x66,0x0e,0xbf] +0x00,0x66,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], s2 ; encoding: [0x00,0x02,0x0e,0xbf] +0x00,0x02,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], vcc_hi ; encoding: [0x00,0x6b,0x0e,0xbf] +0x00,0x6b,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[0:1], vcc_lo ; encoding: [0x00,0x6a,0x0e,0xbf] +0x00,0x6a,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[104:105], s102 ; encoding: [0x68,0x66,0x0e,0xbf] +0x68,0x66,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 s[104:105], s2 ; encoding: [0x68,0x02,0x0e,0xbf] +0x68,0x02,0x0e,0xbf + +# GFX12: s_bitcmp0_b64 vcc, s2 ; encoding: [0x6a,0x02,0x0e,0xbf] +0x6a,0x02,0x0e,0xbf + +# GFX12: s_bitcmp1_b32 exec_hi, s1 ; encoding: [0x7f,0x01,0x0d,0xbf] +0x7f,0x01,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 exec_lo, s1 ; encoding: [0x7e,0x01,0x0d,0xbf] +0x7e,0x01,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 m0, s1 ; encoding: [0x7d,0x01,0x0d,0xbf] +0x7d,0x01,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, 0.5 ; encoding: [0x00,0xf0,0x0d,0xbf] +0x00,0xf0,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, 0 ; encoding: [0x00,0x80,0x0d,0xbf] +0x00,0x80,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_bitcmp1_b32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_bitcmp1_b32 s0, -1 ; encoding: [0x00,0xc1,0x0d,0xbf] +0x00,0xc1,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, -4.0 ; encoding: [0x00,0xf7,0x0d,0xbf] +0x00,0xf7,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, exec_hi ; encoding: [0x00,0x7f,0x0d,0xbf] +0x00,0x7f,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, exec_lo ; encoding: [0x00,0x7e,0x0d,0xbf] +0x00,0x7e,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, m0 ; encoding: [0x00,0x7d,0x0d,0xbf] +0x00,0x7d,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, s104 ; encoding: [0x00,0x68,0x0d,0xbf] +0x00,0x68,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, s1 ; encoding: [0x00,0x01,0x0d,0xbf] +0x00,0x01,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, vcc_hi ; encoding: [0x00,0x6b,0x0d,0xbf] +0x00,0x6b,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s0, vcc_lo ; encoding: [0x00,0x6a,0x0d,0xbf] +0x00,0x6a,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s105, s104 ; encoding: [0x69,0x68,0x0d,0xbf] +0x69,0x68,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 s105, s1 ; encoding: [0x69,0x01,0x0d,0xbf] +0x69,0x01,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x0d,0xbf] +0x6b,0x01,0x0d,0xbf + +# GFX12: s_bitcmp1_b32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x0d,0xbf] +0x6a,0x01,0x0d,0xbf + +# GFX12: s_bitcmp1_b64 exec, s2 ; encoding: [0x7e,0x02,0x0f,0xbf] +0x7e,0x02,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], 0.5 ; encoding: [0x00,0xf0,0x0f,0xbf] +0x00,0xf0,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], 0 ; encoding: [0x00,0x80,0x0f,0xbf] +0x00,0x80,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], 0x3f717273 ; encoding: [0x00,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_bitcmp1_b64 s[0:1], 0xaf123456 ; encoding: [0x00,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_bitcmp1_b64 s[0:1], -1 ; encoding: [0x00,0xc1,0x0f,0xbf] +0x00,0xc1,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], -4.0 ; encoding: [0x00,0xf7,0x0f,0xbf] +0x00,0xf7,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], exec_hi ; encoding: [0x00,0x7f,0x0f,0xbf] +0x00,0x7f,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], exec_lo ; encoding: [0x00,0x7e,0x0f,0xbf] +0x00,0x7e,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], m0 ; encoding: [0x00,0x7d,0x0f,0xbf] +0x00,0x7d,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], s102 ; encoding: [0x00,0x66,0x0f,0xbf] +0x00,0x66,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], s2 ; encoding: [0x00,0x02,0x0f,0xbf] +0x00,0x02,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], vcc_hi ; encoding: [0x00,0x6b,0x0f,0xbf] +0x00,0x6b,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[0:1], vcc_lo ; encoding: [0x00,0x6a,0x0f,0xbf] +0x00,0x6a,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[104:105], s102 ; encoding: [0x68,0x66,0x0f,0xbf] +0x68,0x66,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 s[104:105], s2 ; encoding: [0x68,0x02,0x0f,0xbf] +0x68,0x02,0x0f,0xbf + +# GFX12: s_bitcmp1_b64 vcc, s2 ; encoding: [0x6a,0x02,0x0f,0xbf] +0x6a,0x02,0x0f,0xbf + +# GFX12: s_cmp_eq_i32 exec_hi, s1 ; encoding: [0x7f,0x01,0x00,0xbf] +0x7f,0x01,0x00,0xbf + +# GFX12: s_cmp_eq_i32 exec_lo, s1 ; encoding: [0x7e,0x01,0x00,0xbf] +0x7e,0x01,0x00,0xbf + +# GFX12: s_cmp_eq_i32 m0, s1 ; encoding: [0x7d,0x01,0x00,0xbf] +0x7d,0x01,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x00,0xbf] +0x00,0xf0,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, 0 ; encoding: [0x00,0x80,0x00,0xbf] +0x00,0x80,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_eq_i32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_eq_i32 s0, -1 ; encoding: [0x00,0xc1,0x00,0xbf] +0x00,0xc1,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, -4.0 ; encoding: [0x00,0xf7,0x00,0xbf] +0x00,0xf7,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, exec_hi ; encoding: [0x00,0x7f,0x00,0xbf] +0x00,0x7f,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x00,0xbf] +0x00,0x7e,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, m0 ; encoding: [0x00,0x7d,0x00,0xbf] +0x00,0x7d,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, s104 ; encoding: [0x00,0x68,0x00,0xbf] +0x00,0x68,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, s1 ; encoding: [0x00,0x01,0x00,0xbf] +0x00,0x01,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, vcc_hi ; encoding: [0x00,0x6b,0x00,0xbf] +0x00,0x6b,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x00,0xbf] +0x00,0x6a,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s105, s104 ; encoding: [0x69,0x68,0x00,0xbf] +0x69,0x68,0x00,0xbf + +# GFX12: s_cmp_eq_i32 s105, s1 ; encoding: [0x69,0x01,0x00,0xbf] +0x69,0x01,0x00,0xbf + +# GFX12: s_cmp_eq_i32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x00,0xbf] +0x6b,0x01,0x00,0xbf + +# GFX12: s_cmp_eq_i32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x00,0xbf] +0x6a,0x01,0x00,0xbf + +# GFX12: s_cmp_eq_u32 exec_hi, s1 ; encoding: [0x7f,0x01,0x06,0xbf] +0x7f,0x01,0x06,0xbf + +# GFX12: s_cmp_eq_u32 exec_lo, s1 ; encoding: [0x7e,0x01,0x06,0xbf] +0x7e,0x01,0x06,0xbf + +# GFX12: s_cmp_eq_u32 m0, s1 ; encoding: [0x7d,0x01,0x06,0xbf] +0x7d,0x01,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x06,0xbf] +0x00,0xf0,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, 0 ; encoding: [0x00,0x80,0x06,0xbf] +0x00,0x80,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_eq_u32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_eq_u32 s0, -1 ; encoding: [0x00,0xc1,0x06,0xbf] +0x00,0xc1,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, -4.0 ; encoding: [0x00,0xf7,0x06,0xbf] +0x00,0xf7,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, exec_hi ; encoding: [0x00,0x7f,0x06,0xbf] +0x00,0x7f,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x06,0xbf] +0x00,0x7e,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, m0 ; encoding: [0x00,0x7d,0x06,0xbf] +0x00,0x7d,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, s104 ; encoding: [0x00,0x68,0x06,0xbf] +0x00,0x68,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, s1 ; encoding: [0x00,0x01,0x06,0xbf] +0x00,0x01,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, vcc_hi ; encoding: [0x00,0x6b,0x06,0xbf] +0x00,0x6b,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x06,0xbf] +0x00,0x6a,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s105, s104 ; encoding: [0x69,0x68,0x06,0xbf] +0x69,0x68,0x06,0xbf + +# GFX12: s_cmp_eq_u32 s105, s1 ; encoding: [0x69,0x01,0x06,0xbf] +0x69,0x01,0x06,0xbf + +# GFX12: s_cmp_eq_u32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x06,0xbf] +0x6b,0x01,0x06,0xbf + +# GFX12: s_cmp_eq_u32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x06,0xbf] +0x6a,0x01,0x06,0xbf + +# GFX12: s_cmp_eq_u64 exec, s[2:3] ; encoding: [0x7e,0x02,0x10,0xbf] +0x7e,0x02,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[0:1], 0.5 ; encoding: [0x00,0xf0,0x10,0xbf] +0x00,0xf0,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[0:1], 0 ; encoding: [0x00,0x80,0x10,0xbf] +0x00,0x80,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[0:1], 0x3f717273 ; encoding: [0x00,0xff,0x10,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x10,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_eq_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_eq_u64 s[0:1], -1 ; encoding: [0x00,0xc1,0x10,0xbf] +0x00,0xc1,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[0:1], -4.0 ; encoding: [0x00,0xf7,0x10,0xbf] +0x00,0xf7,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[0:1], exec ; encoding: [0x00,0x7e,0x10,0xbf] +0x00,0x7e,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[0:1], s[102:103] ; encoding: [0x00,0x66,0x10,0xbf] +0x00,0x66,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x10,0xbf] +0x00,0x02,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[0:1], vcc ; encoding: [0x00,0x6a,0x10,0xbf] +0x00,0x6a,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[104:105], s[102:103] ; encoding: [0x68,0x66,0x10,0xbf] +0x68,0x66,0x10,0xbf + +# GFX12: s_cmp_eq_u64 s[104:105], s[2:3] ; encoding: [0x68,0x02,0x10,0xbf] +0x68,0x02,0x10,0xbf + +# GFX12: s_cmp_eq_u64 vcc, s[2:3] ; encoding: [0x6a,0x02,0x10,0xbf] +0x6a,0x02,0x10,0xbf + +# GFX12: s_cmp_ge_i32 exec_hi, s1 ; encoding: [0x7f,0x01,0x03,0xbf] +0x7f,0x01,0x03,0xbf + +# GFX12: s_cmp_ge_i32 exec_lo, s1 ; encoding: [0x7e,0x01,0x03,0xbf] +0x7e,0x01,0x03,0xbf + +# GFX12: s_cmp_ge_i32 m0, s1 ; encoding: [0x7d,0x01,0x03,0xbf] +0x7d,0x01,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x03,0xbf] +0x00,0xf0,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, 0 ; encoding: [0x00,0x80,0x03,0xbf] +0x00,0x80,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_ge_i32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_ge_i32 s0, -1 ; encoding: [0x00,0xc1,0x03,0xbf] +0x00,0xc1,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, -4.0 ; encoding: [0x00,0xf7,0x03,0xbf] +0x00,0xf7,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, exec_hi ; encoding: [0x00,0x7f,0x03,0xbf] +0x00,0x7f,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x03,0xbf] +0x00,0x7e,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, m0 ; encoding: [0x00,0x7d,0x03,0xbf] +0x00,0x7d,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, s104 ; encoding: [0x00,0x68,0x03,0xbf] +0x00,0x68,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, s1 ; encoding: [0x00,0x01,0x03,0xbf] +0x00,0x01,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, vcc_hi ; encoding: [0x00,0x6b,0x03,0xbf] +0x00,0x6b,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x03,0xbf] +0x00,0x6a,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s105, s104 ; encoding: [0x69,0x68,0x03,0xbf] +0x69,0x68,0x03,0xbf + +# GFX12: s_cmp_ge_i32 s105, s1 ; encoding: [0x69,0x01,0x03,0xbf] +0x69,0x01,0x03,0xbf + +# GFX12: s_cmp_ge_i32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x03,0xbf] +0x6b,0x01,0x03,0xbf + +# GFX12: s_cmp_ge_i32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x03,0xbf] +0x6a,0x01,0x03,0xbf + +# GFX12: s_cmp_ge_u32 exec_hi, s1 ; encoding: [0x7f,0x01,0x09,0xbf] +0x7f,0x01,0x09,0xbf + +# GFX12: s_cmp_ge_u32 exec_lo, s1 ; encoding: [0x7e,0x01,0x09,0xbf] +0x7e,0x01,0x09,0xbf + +# GFX12: s_cmp_ge_u32 m0, s1 ; encoding: [0x7d,0x01,0x09,0xbf] +0x7d,0x01,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x09,0xbf] +0x00,0xf0,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, 0 ; encoding: [0x00,0x80,0x09,0xbf] +0x00,0x80,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_ge_u32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_ge_u32 s0, -1 ; encoding: [0x00,0xc1,0x09,0xbf] +0x00,0xc1,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, -4.0 ; encoding: [0x00,0xf7,0x09,0xbf] +0x00,0xf7,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, exec_hi ; encoding: [0x00,0x7f,0x09,0xbf] +0x00,0x7f,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x09,0xbf] +0x00,0x7e,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, m0 ; encoding: [0x00,0x7d,0x09,0xbf] +0x00,0x7d,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, s104 ; encoding: [0x00,0x68,0x09,0xbf] +0x00,0x68,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, s1 ; encoding: [0x00,0x01,0x09,0xbf] +0x00,0x01,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, vcc_hi ; encoding: [0x00,0x6b,0x09,0xbf] +0x00,0x6b,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x09,0xbf] +0x00,0x6a,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s105, s104 ; encoding: [0x69,0x68,0x09,0xbf] +0x69,0x68,0x09,0xbf + +# GFX12: s_cmp_ge_u32 s105, s1 ; encoding: [0x69,0x01,0x09,0xbf] +0x69,0x01,0x09,0xbf + +# GFX12: s_cmp_ge_u32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x09,0xbf] +0x6b,0x01,0x09,0xbf + +# GFX12: s_cmp_ge_u32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x09,0xbf] +0x6a,0x01,0x09,0xbf + +# GFX12: s_cmp_gt_i32 exec_hi, s1 ; encoding: [0x7f,0x01,0x02,0xbf] +0x7f,0x01,0x02,0xbf + +# GFX12: s_cmp_gt_i32 exec_lo, s1 ; encoding: [0x7e,0x01,0x02,0xbf] +0x7e,0x01,0x02,0xbf + +# GFX12: s_cmp_gt_i32 m0, s1 ; encoding: [0x7d,0x01,0x02,0xbf] +0x7d,0x01,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x02,0xbf] +0x00,0xf0,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, 0 ; encoding: [0x00,0x80,0x02,0xbf] +0x00,0x80,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_gt_i32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_gt_i32 s0, -1 ; encoding: [0x00,0xc1,0x02,0xbf] +0x00,0xc1,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, -4.0 ; encoding: [0x00,0xf7,0x02,0xbf] +0x00,0xf7,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, exec_hi ; encoding: [0x00,0x7f,0x02,0xbf] +0x00,0x7f,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x02,0xbf] +0x00,0x7e,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, m0 ; encoding: [0x00,0x7d,0x02,0xbf] +0x00,0x7d,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, s104 ; encoding: [0x00,0x68,0x02,0xbf] +0x00,0x68,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, s1 ; encoding: [0x00,0x01,0x02,0xbf] +0x00,0x01,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, vcc_hi ; encoding: [0x00,0x6b,0x02,0xbf] +0x00,0x6b,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x02,0xbf] +0x00,0x6a,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s105, s104 ; encoding: [0x69,0x68,0x02,0xbf] +0x69,0x68,0x02,0xbf + +# GFX12: s_cmp_gt_i32 s105, s1 ; encoding: [0x69,0x01,0x02,0xbf] +0x69,0x01,0x02,0xbf + +# GFX12: s_cmp_gt_i32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x02,0xbf] +0x6b,0x01,0x02,0xbf + +# GFX12: s_cmp_gt_i32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x02,0xbf] +0x6a,0x01,0x02,0xbf + +# GFX12: s_cmp_gt_u32 exec_hi, s1 ; encoding: [0x7f,0x01,0x08,0xbf] +0x7f,0x01,0x08,0xbf + +# GFX12: s_cmp_gt_u32 exec_lo, s1 ; encoding: [0x7e,0x01,0x08,0xbf] +0x7e,0x01,0x08,0xbf + +# GFX12: s_cmp_gt_u32 m0, s1 ; encoding: [0x7d,0x01,0x08,0xbf] +0x7d,0x01,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x08,0xbf] +0x00,0xf0,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, 0 ; encoding: [0x00,0x80,0x08,0xbf] +0x00,0x80,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_gt_u32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_gt_u32 s0, -1 ; encoding: [0x00,0xc1,0x08,0xbf] +0x00,0xc1,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, -4.0 ; encoding: [0x00,0xf7,0x08,0xbf] +0x00,0xf7,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, exec_hi ; encoding: [0x00,0x7f,0x08,0xbf] +0x00,0x7f,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x08,0xbf] +0x00,0x7e,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, m0 ; encoding: [0x00,0x7d,0x08,0xbf] +0x00,0x7d,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, s104 ; encoding: [0x00,0x68,0x08,0xbf] +0x00,0x68,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, s1 ; encoding: [0x00,0x01,0x08,0xbf] +0x00,0x01,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, vcc_hi ; encoding: [0x00,0x6b,0x08,0xbf] +0x00,0x6b,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x08,0xbf] +0x00,0x6a,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s105, s104 ; encoding: [0x69,0x68,0x08,0xbf] +0x69,0x68,0x08,0xbf + +# GFX12: s_cmp_gt_u32 s105, s1 ; encoding: [0x69,0x01,0x08,0xbf] +0x69,0x01,0x08,0xbf + +# GFX12: s_cmp_gt_u32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x08,0xbf] +0x6b,0x01,0x08,0xbf + +# GFX12: s_cmp_gt_u32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x08,0xbf] +0x6a,0x01,0x08,0xbf + +# GFX12: s_cmp_le_i32 exec_hi, s1 ; encoding: [0x7f,0x01,0x05,0xbf] +0x7f,0x01,0x05,0xbf + +# GFX12: s_cmp_le_i32 exec_lo, s1 ; encoding: [0x7e,0x01,0x05,0xbf] +0x7e,0x01,0x05,0xbf + +# GFX12: s_cmp_le_i32 m0, s1 ; encoding: [0x7d,0x01,0x05,0xbf] +0x7d,0x01,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x05,0xbf] +0x00,0xf0,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, 0 ; encoding: [0x00,0x80,0x05,0xbf] +0x00,0x80,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_le_i32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_le_i32 s0, -1 ; encoding: [0x00,0xc1,0x05,0xbf] +0x00,0xc1,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, -4.0 ; encoding: [0x00,0xf7,0x05,0xbf] +0x00,0xf7,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, exec_hi ; encoding: [0x00,0x7f,0x05,0xbf] +0x00,0x7f,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x05,0xbf] +0x00,0x7e,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, m0 ; encoding: [0x00,0x7d,0x05,0xbf] +0x00,0x7d,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, s104 ; encoding: [0x00,0x68,0x05,0xbf] +0x00,0x68,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, s1 ; encoding: [0x00,0x01,0x05,0xbf] +0x00,0x01,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, vcc_hi ; encoding: [0x00,0x6b,0x05,0xbf] +0x00,0x6b,0x05,0xbf + +# GFX12: s_cmp_le_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x05,0xbf] +0x00,0x6a,0x05,0xbf + +# GFX12: s_cmp_le_i32 s105, s104 ; encoding: [0x69,0x68,0x05,0xbf] +0x69,0x68,0x05,0xbf + +# GFX12: s_cmp_le_i32 s105, s1 ; encoding: [0x69,0x01,0x05,0xbf] +0x69,0x01,0x05,0xbf + +# GFX12: s_cmp_le_i32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x05,0xbf] +0x6b,0x01,0x05,0xbf + +# GFX12: s_cmp_le_i32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x05,0xbf] +0x6a,0x01,0x05,0xbf + +# GFX12: s_cmp_le_u32 exec_hi, s1 ; encoding: [0x7f,0x01,0x0b,0xbf] +0x7f,0x01,0x0b,0xbf + +# GFX12: s_cmp_le_u32 exec_lo, s1 ; encoding: [0x7e,0x01,0x0b,0xbf] +0x7e,0x01,0x0b,0xbf + +# GFX12: s_cmp_le_u32 m0, s1 ; encoding: [0x7d,0x01,0x0b,0xbf] +0x7d,0x01,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x0b,0xbf] +0x00,0xf0,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, 0 ; encoding: [0x00,0x80,0x0b,0xbf] +0x00,0x80,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_le_u32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_le_u32 s0, -1 ; encoding: [0x00,0xc1,0x0b,0xbf] +0x00,0xc1,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, -4.0 ; encoding: [0x00,0xf7,0x0b,0xbf] +0x00,0xf7,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, exec_hi ; encoding: [0x00,0x7f,0x0b,0xbf] +0x00,0x7f,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x0b,0xbf] +0x00,0x7e,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, m0 ; encoding: [0x00,0x7d,0x0b,0xbf] +0x00,0x7d,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, s104 ; encoding: [0x00,0x68,0x0b,0xbf] +0x00,0x68,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, s1 ; encoding: [0x00,0x01,0x0b,0xbf] +0x00,0x01,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, vcc_hi ; encoding: [0x00,0x6b,0x0b,0xbf] +0x00,0x6b,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x0b,0xbf] +0x00,0x6a,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s105, s104 ; encoding: [0x69,0x68,0x0b,0xbf] +0x69,0x68,0x0b,0xbf + +# GFX12: s_cmp_le_u32 s105, s1 ; encoding: [0x69,0x01,0x0b,0xbf] +0x69,0x01,0x0b,0xbf + +# GFX12: s_cmp_le_u32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x0b,0xbf] +0x6b,0x01,0x0b,0xbf + +# GFX12: s_cmp_le_u32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x0b,0xbf] +0x6a,0x01,0x0b,0xbf + +# GFX12: s_cmp_lg_i32 exec_hi, s1 ; encoding: [0x7f,0x01,0x01,0xbf] +0x7f,0x01,0x01,0xbf + +# GFX12: s_cmp_lg_i32 exec_lo, s1 ; encoding: [0x7e,0x01,0x01,0xbf] +0x7e,0x01,0x01,0xbf + +# GFX12: s_cmp_lg_i32 m0, s1 ; encoding: [0x7d,0x01,0x01,0xbf] +0x7d,0x01,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x01,0xbf] +0x00,0xf0,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, 0 ; encoding: [0x00,0x80,0x01,0xbf] +0x00,0x80,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_lg_i32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_lg_i32 s0, -1 ; encoding: [0x00,0xc1,0x01,0xbf] +0x00,0xc1,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, -4.0 ; encoding: [0x00,0xf7,0x01,0xbf] +0x00,0xf7,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, exec_hi ; encoding: [0x00,0x7f,0x01,0xbf] +0x00,0x7f,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x01,0xbf] +0x00,0x7e,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, m0 ; encoding: [0x00,0x7d,0x01,0xbf] +0x00,0x7d,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, s104 ; encoding: [0x00,0x68,0x01,0xbf] +0x00,0x68,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, s1 ; encoding: [0x00,0x01,0x01,0xbf] +0x00,0x01,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, vcc_hi ; encoding: [0x00,0x6b,0x01,0xbf] +0x00,0x6b,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x01,0xbf] +0x00,0x6a,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s105, s104 ; encoding: [0x69,0x68,0x01,0xbf] +0x69,0x68,0x01,0xbf + +# GFX12: s_cmp_lg_i32 s105, s1 ; encoding: [0x69,0x01,0x01,0xbf] +0x69,0x01,0x01,0xbf + +# GFX12: s_cmp_lg_i32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x01,0xbf] +0x6b,0x01,0x01,0xbf + +# GFX12: s_cmp_lg_i32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x01,0xbf] +0x6a,0x01,0x01,0xbf + +# GFX12: s_cmp_lg_u32 exec_hi, s1 ; encoding: [0x7f,0x01,0x07,0xbf] +0x7f,0x01,0x07,0xbf + +# GFX12: s_cmp_lg_u32 exec_lo, s1 ; encoding: [0x7e,0x01,0x07,0xbf] +0x7e,0x01,0x07,0xbf + +# GFX12: s_cmp_lg_u32 m0, s1 ; encoding: [0x7d,0x01,0x07,0xbf] +0x7d,0x01,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x07,0xbf] +0x00,0xf0,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, 0 ; encoding: [0x00,0x80,0x07,0xbf] +0x00,0x80,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_lg_u32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_lg_u32 s0, -1 ; encoding: [0x00,0xc1,0x07,0xbf] +0x00,0xc1,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, -4.0 ; encoding: [0x00,0xf7,0x07,0xbf] +0x00,0xf7,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, exec_hi ; encoding: [0x00,0x7f,0x07,0xbf] +0x00,0x7f,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x07,0xbf] +0x00,0x7e,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, m0 ; encoding: [0x00,0x7d,0x07,0xbf] +0x00,0x7d,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, s104 ; encoding: [0x00,0x68,0x07,0xbf] +0x00,0x68,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, s1 ; encoding: [0x00,0x01,0x07,0xbf] +0x00,0x01,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, vcc_hi ; encoding: [0x00,0x6b,0x07,0xbf] +0x00,0x6b,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x07,0xbf] +0x00,0x6a,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s105, s104 ; encoding: [0x69,0x68,0x07,0xbf] +0x69,0x68,0x07,0xbf + +# GFX12: s_cmp_lg_u32 s105, s1 ; encoding: [0x69,0x01,0x07,0xbf] +0x69,0x01,0x07,0xbf + +# GFX12: s_cmp_lg_u32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x07,0xbf] +0x6b,0x01,0x07,0xbf + +# GFX12: s_cmp_lg_u32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x07,0xbf] +0x6a,0x01,0x07,0xbf + +# GFX12: s_cmp_lg_u64 exec, s[2:3] ; encoding: [0x7e,0x02,0x11,0xbf] +0x7e,0x02,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[0:1], 0.5 ; encoding: [0x00,0xf0,0x11,0xbf] +0x00,0xf0,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[0:1], 0 ; encoding: [0x00,0x80,0x11,0xbf] +0x00,0x80,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[0:1], 0x3f717273 ; encoding: [0x00,0xff,0x11,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x11,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_lg_u64 s[0:1], 0xaf123456 ; encoding: [0x00,0xff,0x11,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x11,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_lg_u64 s[0:1], -1 ; encoding: [0x00,0xc1,0x11,0xbf] +0x00,0xc1,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[0:1], -4.0 ; encoding: [0x00,0xf7,0x11,0xbf] +0x00,0xf7,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[0:1], exec ; encoding: [0x00,0x7e,0x11,0xbf] +0x00,0x7e,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[0:1], s[102:103] ; encoding: [0x00,0x66,0x11,0xbf] +0x00,0x66,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x11,0xbf] +0x00,0x02,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[0:1], vcc ; encoding: [0x00,0x6a,0x11,0xbf] +0x00,0x6a,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[104:105], s[102:103] ; encoding: [0x68,0x66,0x11,0xbf] +0x68,0x66,0x11,0xbf + +# GFX12: s_cmp_lg_u64 s[104:105], s[2:3] ; encoding: [0x68,0x02,0x11,0xbf] +0x68,0x02,0x11,0xbf + +# GFX12: s_cmp_lg_u64 vcc, s[2:3] ; encoding: [0x6a,0x02,0x11,0xbf] +0x6a,0x02,0x11,0xbf + +# GFX12: s_cmp_lt_i32 exec_hi, s1 ; encoding: [0x7f,0x01,0x04,0xbf] +0x7f,0x01,0x04,0xbf + +# GFX12: s_cmp_lt_i32 exec_lo, s1 ; encoding: [0x7e,0x01,0x04,0xbf] +0x7e,0x01,0x04,0xbf + +# GFX12: s_cmp_lt_i32 m0, s1 ; encoding: [0x7d,0x01,0x04,0xbf] +0x7d,0x01,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x04,0xbf] +0x00,0xf0,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, 0 ; encoding: [0x00,0x80,0x04,0xbf] +0x00,0x80,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_lt_i32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_lt_i32 s0, -1 ; encoding: [0x00,0xc1,0x04,0xbf] +0x00,0xc1,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, -4.0 ; encoding: [0x00,0xf7,0x04,0xbf] +0x00,0xf7,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, exec_hi ; encoding: [0x00,0x7f,0x04,0xbf] +0x00,0x7f,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x04,0xbf] +0x00,0x7e,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, m0 ; encoding: [0x00,0x7d,0x04,0xbf] +0x00,0x7d,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, s104 ; encoding: [0x00,0x68,0x04,0xbf] +0x00,0x68,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, s1 ; encoding: [0x00,0x01,0x04,0xbf] +0x00,0x01,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, vcc_hi ; encoding: [0x00,0x6b,0x04,0xbf] +0x00,0x6b,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x04,0xbf] +0x00,0x6a,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s105, s104 ; encoding: [0x69,0x68,0x04,0xbf] +0x69,0x68,0x04,0xbf + +# GFX12: s_cmp_lt_i32 s105, s1 ; encoding: [0x69,0x01,0x04,0xbf] +0x69,0x01,0x04,0xbf + +# GFX12: s_cmp_lt_i32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x04,0xbf] +0x6b,0x01,0x04,0xbf + +# GFX12: s_cmp_lt_i32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x04,0xbf] +0x6a,0x01,0x04,0xbf + +# GFX12: s_cmp_lt_u32 exec_hi, s1 ; encoding: [0x7f,0x01,0x0a,0xbf] +0x7f,0x01,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 exec_lo, s1 ; encoding: [0x7e,0x01,0x0a,0xbf] +0x7e,0x01,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 m0, s1 ; encoding: [0x7d,0x01,0x0a,0xbf] +0x7d,0x01,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x0a,0xbf] +0x00,0xf0,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, 0 ; encoding: [0x00,0x80,0x0a,0xbf] +0x00,0x80,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, 0x3f717273 ; encoding: [0x00,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f] +0x00,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f + +# GFX12: s_cmp_lt_u32 s0, 0xaf123456 ; encoding: [0x00,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf] +0x00,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf + +# GFX12: s_cmp_lt_u32 s0, -1 ; encoding: [0x00,0xc1,0x0a,0xbf] +0x00,0xc1,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, -4.0 ; encoding: [0x00,0xf7,0x0a,0xbf] +0x00,0xf7,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, exec_hi ; encoding: [0x00,0x7f,0x0a,0xbf] +0x00,0x7f,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x0a,0xbf] +0x00,0x7e,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, m0 ; encoding: [0x00,0x7d,0x0a,0xbf] +0x00,0x7d,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, s104 ; encoding: [0x00,0x68,0x0a,0xbf] +0x00,0x68,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, s1 ; encoding: [0x00,0x01,0x0a,0xbf] +0x00,0x01,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, vcc_hi ; encoding: [0x00,0x6b,0x0a,0xbf] +0x00,0x6b,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x0a,0xbf] +0x00,0x6a,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s105, s104 ; encoding: [0x69,0x68,0x0a,0xbf] +0x69,0x68,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 s105, s1 ; encoding: [0x69,0x01,0x0a,0xbf] +0x69,0x01,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 vcc_hi, s1 ; encoding: [0x6b,0x01,0x0a,0xbf] +0x6b,0x01,0x0a,0xbf + +# GFX12: s_cmp_lt_u32 vcc_lo, s1 ; encoding: [0x6a,0x01,0x0a,0xbf] +0x6a,0x01,0x0a,0xbf diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt new file mode 100644 index 000000000000..ebf65a45d176 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt @@ -0,0 +1,257 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefix=GFX12 %s + +# GFX12: s_addk_co_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0xff,0xb7] +0x34,0x12,0xff,0xb7 + +# GFX12: s_addk_co_i32 exec_lo, 0x1234 ; encoding: [0x34,0x12,0xfe,0xb7] +0x34,0x12,0xfe,0xb7 + +# GFX12: s_addk_co_i32 m0, 0x1234 ; encoding: [0x34,0x12,0xfd,0xb7] +0x34,0x12,0xfd,0xb7 + +# GFX12: s_addk_co_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x80,0xb7] +0x34,0x12,0x80,0xb7 + +# GFX12: s_addk_co_i32 s0, 0xc1d1 ; encoding: [0xd1,0xc1,0x80,0xb7] +0xd1,0xc1,0x80,0xb7 + +# GFX12: s_addk_co_i32 s105, 0x1234 ; encoding: [0x34,0x12,0xe9,0xb7] +0x34,0x12,0xe9,0xb7 + +# GFX12: s_addk_co_i32 vcc_hi, 0x1234 ; encoding: [0x34,0x12,0xeb,0xb7] +0x34,0x12,0xeb,0xb7 + +# GFX12: s_addk_co_i32 vcc_lo, 0x1234 ; encoding: [0x34,0x12,0xea,0xb7] +0x34,0x12,0xea,0xb7 + +# GFX12: s_call_b64 exec, 4660 ; encoding: [0x34,0x12,0x7e,0xba] +0x34,0x12,0x7e,0xba + +# GFX12: s_call_b64 s[0:1], 4660 ; encoding: [0x34,0x12,0x00,0xba] +0x34,0x12,0x00,0xba + +# GFX12: s_call_b64 s[104:105], 4660 ; encoding: [0x34,0x12,0x68,0xba] +0x34,0x12,0x68,0xba + +# GFX12: s_call_b64 vcc, 4660 ; encoding: [0x34,0x12,0x6a,0xba] +0x34,0x12,0x6a,0xba + +# GFX12: s_call_b64 null, 4660 ; encoding: [0x34,0x12,0x7c,0xba] +0x34,0x12,0x7c,0xba + +# GFX12: s_cmovk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0x7f,0xb1] +0x34,0x12,0x7f,0xb1 + +# GFX12: s_cmovk_i32 exec_lo, 0x1234 ; encoding: [0x34,0x12,0x7e,0xb1] +0x34,0x12,0x7e,0xb1 + +# GFX12: s_cmovk_i32 m0, 0x1234 ; encoding: [0x34,0x12,0x7d,0xb1] +0x34,0x12,0x7d,0xb1 + +# GFX12: s_cmovk_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x00,0xb1] +0x34,0x12,0x00,0xb1 + +# GFX12: s_cmovk_i32 s0, 0xc1d1 ; encoding: [0xd1,0xc1,0x00,0xb1] +0xd1,0xc1,0x00,0xb1 + +# GFX12: s_cmovk_i32 s105, 0x1234 ; encoding: [0x34,0x12,0x69,0xb1] +0x34,0x12,0x69,0xb1 + +# GFX12: s_cmovk_i32 vcc_hi, 0x1234 ; encoding: [0x34,0x12,0x6b,0xb1] +0x34,0x12,0x6b,0xb1 + +# GFX12: s_cmovk_i32 vcc_lo, 0x1234 ; encoding: [0x34,0x12,0x6a,0xb1] +0x34,0x12,0x6a,0xb1 + +# GFX12: s_getreg_b32 exec_hi, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xff,0xb8] +0x34,0x12,0xff,0xb8 + +# GFX12: s_getreg_b32 exec_lo, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xfe,0xb8] +0x34,0x12,0xfe,0xb8 + +# GFX12: s_getreg_b32 m0, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xfd,0xb8] +0x34,0x12,0xfd,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0x80,0xb8] +0x34,0x12,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_PRIV, 7, 25) ; encoding: [0xd1,0xc1,0x80,0xb8] +0xd1,0xc1,0x80,0xb8 + +# GFX12: s_getreg_b32 s105, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xe9,0xb8] +0x34,0x12,0xe9,0xb8 + +# GFX12: s_getreg_b32 vcc_hi, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xeb,0xb8] +0x34,0x12,0xeb,0xb8 + +# GFX12: s_getreg_b32 vcc_lo, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0xea,0xb8] +0x34,0x12,0xea,0xb8 + +# GFX12: s_movk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0x7f,0xb0] +0x34,0x12,0x7f,0xb0 + +# GFX12: s_movk_i32 exec_lo, 0x1234 ; encoding: [0x34,0x12,0x7e,0xb0] +0x34,0x12,0x7e,0xb0 + +# GFX12: s_movk_i32 m0, 0x1234 ; encoding: [0x34,0x12,0x7d,0xb0] +0x34,0x12,0x7d,0xb0 + +# GFX12: s_movk_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x00,0xb0] +0x34,0x12,0x00,0xb0 + +# GFX12: s_movk_i32 s0, 0xc1d1 ; encoding: [0xd1,0xc1,0x00,0xb0] +0xd1,0xc1,0x00,0xb0 + +# GFX12: s_movk_i32 s105, 0x1234 ; encoding: [0x34,0x12,0x69,0xb0] +0x34,0x12,0x69,0xb0 + +# GFX12: s_movk_i32 vcc_hi, 0x1234 ; encoding: [0x34,0x12,0x6b,0xb0] +0x34,0x12,0x6b,0xb0 + +# GFX12: s_movk_i32 vcc_lo, 0x1234 ; encoding: [0x34,0x12,0x6a,0xb0] +0x34,0x12,0x6a,0xb0 + +# GFX12: s_mulk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0x7f,0xb8] +0x34,0x12,0x7f,0xb8 + +# GFX12: s_mulk_i32 exec_lo, 0x1234 ; encoding: [0x34,0x12,0x7e,0xb8] +0x34,0x12,0x7e,0xb8 + +# GFX12: s_mulk_i32 m0, 0x1234 ; encoding: [0x34,0x12,0x7d,0xb8] +0x34,0x12,0x7d,0xb8 + +# GFX12: s_mulk_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x00,0xb8] +0x34,0x12,0x00,0xb8 + +# GFX12: s_mulk_i32 s0, 0xc1d1 ; encoding: [0xd1,0xc1,0x00,0xb8] +0xd1,0xc1,0x00,0xb8 + +# GFX12: s_mulk_i32 s105, 0x1234 ; encoding: [0x34,0x12,0x69,0xb8] +0x34,0x12,0x69,0xb8 + +# GFX12: s_mulk_i32 vcc_hi, 0x1234 ; encoding: [0x34,0x12,0x6b,0xb8] +0x34,0x12,0x6b,0xb8 + +# GFX12: s_mulk_i32 vcc_lo, 0x1234 ; encoding: [0x34,0x12,0x6a,0xb8] +0x34,0x12,0x6a,0xb8 + +# GFX12: s_setreg_b32 hwreg(52, 8, 3), exec_hi ; encoding: [0x34,0x12,0x7f,0xb9] +0x34,0x12,0x7f,0xb9 + +# GFX12: s_setreg_b32 hwreg(52, 8, 3), exec_lo ; encoding: [0x34,0x12,0x7e,0xb9] +0x34,0x12,0x7e,0xb9 + +# GFX12: s_setreg_b32 hwreg(52, 8, 3), m0 ; encoding: [0x34,0x12,0x7d,0xb9] +0x34,0x12,0x7d,0xb9 + +# GFX12: s_setreg_b32 hwreg(52, 8, 3), s0 ; encoding: [0x34,0x12,0x00,0xb9] +0x34,0x12,0x00,0xb9 + +# GFX12: s_setreg_b32 hwreg(52, 8, 3), s105 ; encoding: [0x34,0x12,0x69,0xb9] +0x34,0x12,0x69,0xb9 + +# GFX12: s_setreg_b32 hwreg(52, 8, 3), vcc_hi ; encoding: [0x34,0x12,0x6b,0xb9] +0x34,0x12,0x6b,0xb9 + +# GFX12: s_setreg_b32 hwreg(52, 8, 3), vcc_lo ; encoding: [0x34,0x12,0x6a,0xb9] +0x34,0x12,0x6a,0xb9 + +# GFX12: s_setreg_b32 hwreg(HW_REG_EXCP_FLAG_PRIV, 7, 25), s0 ; encoding: [0xd1,0xc1,0x00,0xb9] +0xd1,0xc1,0x00,0xb9 + +# GFX12: s_version 0x1234 ; encoding: [0x34,0x12,0x80,0xb0] +0x34,0x12,0x80,0xb0 + +# GFX12: s_version 0xc1d1 ; encoding: [0xd1,0xc1,0x80,0xb0] +0xd1,0xc1,0x80,0xb0 + +# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_MODE), 0xaf123456 ; encoding: [0x01,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] +0x01,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf + +# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 31, 1), 0xaf123456 ; encoding: [0xc1,0x07,0x80,0xb9,0x56,0x34,0x12,0xaf] +0xc1,0x07,0x80,0xb9,0x56,0x34,0x12,0xaf + +# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_STATUS), 0xaf123456 ; encoding: [0x02,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] +0x02,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf + +# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC), 0xaf123456 ; encoding: [0x05,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] +0x05,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf + +# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC), 0xaf123456 ; encoding: [0x06,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] +0x06,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf + +# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_IB_STS), 0xaf123456 ; encoding: [0x07,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] +0x07,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf + +# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID1), 0xaf123456 ; encoding: [0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] +0x17,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf + +# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_HW_ID2), 0xaf123456 ; encoding: [0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf] +0x18,0xf8,0x80,0xb9,0x56,0x34,0x12,0xaf + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_MODE) ; encoding: [0x01,0xf8,0x80,0xb8] +0x01,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_STATUS) ; encoding: [0x02,0xf8,0x80,0xb8] +0x02,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_STATE_PRIV) ; encoding: [0x04,0xf8,0x80,0xb8] +0x04,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_GPR_ALLOC) ; encoding: [0x05,0xf8,0x80,0xb8] +0x05,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x80,0xb8] +0x06,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_IB_STS) ; encoding: [0x07,0xf8,0x80,0xb8] +0x07,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA) ; encoding: [0x0a,0xf8,0x80,0xb8] +0x0a,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_LO) ; encoding: [0x0b,0xf8,0x80,0xb8] +0x0b,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_HI) ; encoding: [0x0c,0xf8,0x80,0xb8] +0x0c,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA1) ; encoding: [0x0f,0xf8,0x80,0xb8] +0x0f,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA2) ; encoding: [0x10,0xf8,0x80,0xb8] +0x10,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_PRIV) ; encoding: [0x11,0xf8,0x80,0xb8] +0x11,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_USER) ; encoding: [0x12,0xf8,0x80,0xb8] +0x12,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_TRAP_CTRL) ; encoding: [0x13,0xf8,0x80,0xb8] +0x13,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_LO) ; encoding: [0x14,0xf8,0x80,0xb8] +0x14,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_HI) ; encoding: [0x15,0xf8,0x80,0xb8] +0x15,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_HW_ID1) ; encoding: [0x17,0xf8,0x80,0xb8] +0x17,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_HW_ID2) ; encoding: [0x18,0xf8,0x80,0xb8] +0x18,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_LO) ; encoding: [0x1f,0xf8,0x80,0xb8] +0x1f,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_HI) ; encoding: [0x20,0xf8,0x80,0xb8] +0x20,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_LO) ; encoding: [0x1d,0xf8,0x80,0xb8] +0x1d,0xf8,0x80,0xb8 + +# GFX12: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_HI) ; encoding: [0x1e,0xf8,0x80,0xb8] +0x1e,0xf8,0x80,0xb8 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt new file mode 100644 index 000000000000..fe74ff08a8e5 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt @@ -0,0 +1,268 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX12 %s + +# GFX12: s_wait_alu depctr_hold_cnt(0) depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0x88,0xbf] +0x00,0x00,0x88,0xbf + +# GFX12: s_wait_alu 0xfffe ; encoding: [0xfe,0xff,0x88,0xbf] +0xfe,0xff,0x88,0xbf + +# GFX12: s_singleuse_vdst 0x0 ; encoding: [0x00,0x00,0x93,0xbf] +0x00,0x00,0x93,0xbf + +# GFX12: s_singleuse_vdst 0xffff ; encoding: [0xff,0xff,0x93,0xbf] +0xff,0xff,0x93,0xbf + +# GFX12: s_singleuse_vdst 0x1234 ; encoding: [0x34,0x12,0x93,0xbf] +0x34,0x12,0x93,0xbf + +# GFX12: s_branch 0 ; encoding: [0x00,0x00,0xa0,0xbf] +0x00,0x00,0xa0,0xbf + +# GFX12: s_branch 4660 ; encoding: [0x34,0x12,0xa0,0xbf] +0x34,0x12,0xa0,0xbf + +# GFX12: s_cbranch_execnz 0 ; encoding: [0x00,0x00,0xa6,0xbf] +0x00,0x00,0xa6,0xbf + +# GFX12: s_cbranch_execnz 4660 ; encoding: [0x34,0x12,0xa6,0xbf] +0x34,0x12,0xa6,0xbf + +# GFX12: s_cbranch_execz 0 ; encoding: [0x00,0x00,0xa5,0xbf] +0x00,0x00,0xa5,0xbf + +# GFX12: s_cbranch_execz 4660 ; encoding: [0x34,0x12,0xa5,0xbf] +0x34,0x12,0xa5,0xbf + +# GFX12: s_cbranch_scc0 0 ; encoding: [0x00,0x00,0xa1,0xbf] +0x00,0x00,0xa1,0xbf + +# GFX12: s_cbranch_scc0 4660 ; encoding: [0x34,0x12,0xa1,0xbf] +0x34,0x12,0xa1,0xbf + +# GFX12: s_cbranch_scc1 0 ; encoding: [0x00,0x00,0xa2,0xbf] +0x00,0x00,0xa2,0xbf + +# GFX12: s_cbranch_scc1 4660 ; encoding: [0x34,0x12,0xa2,0xbf] +0x34,0x12,0xa2,0xbf + +# GFX12: s_cbranch_vccnz 0 ; encoding: [0x00,0x00,0xa4,0xbf] +0x00,0x00,0xa4,0xbf + +# GFX12: s_cbranch_vccnz 4660 ; encoding: [0x34,0x12,0xa4,0xbf] +0x34,0x12,0xa4,0xbf + +# GFX12: s_cbranch_vccz 0 ; encoding: [0x00,0x00,0xa3,0xbf] +0x00,0x00,0xa3,0xbf + +# GFX12: s_cbranch_vccz 4660 ; encoding: [0x34,0x12,0xa3,0xbf] +0x34,0x12,0xa3,0xbf + +# GFX12: s_clause 0x0 ; encoding: [0x00,0x00,0x85,0xbf] +0x00,0x00,0x85,0xbf + +# GFX12: s_clause 0x1234 ; encoding: [0x34,0x12,0x85,0xbf] +0x34,0x12,0x85,0xbf + +# GFX12: s_clause 0xc1d1 ; encoding: [0xd1,0xc1,0x85,0xbf] +0xd1,0xc1,0x85,0xbf + +# GFX12: s_code_end ; encoding: [0x00,0x00,0x9f,0xbf] +0x00,0x00,0x9f,0xbf + +# GFX12: s_decperflevel 0 ; encoding: [0x00,0x00,0xb9,0xbf] +0x00,0x00,0xb9,0xbf + +# GFX12: s_decperflevel 0x1234 ; encoding: [0x34,0x12,0xb9,0xbf] +0x34,0x12,0xb9,0xbf + +# GFX12: s_decperflevel 0xc1d1 ; encoding: [0xd1,0xc1,0xb9,0xbf] +0xd1,0xc1,0xb9,0xbf + +# GFX12: s_delay_alu 0 ; encoding: [0x00,0x00,0x87,0xbf] +0x00,0x00,0x87,0xbf + +# GFX12: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; encoding: [0x91,0x00,0x87,0xbf] +0x91,0x00,0x87,0xbf + +# GFX12: s_delay_alu instid0(VALU_DEP_1) ; encoding: [0x01,0x00,0x87,0xbf] +0x01,0x00,0x87,0xbf + +# GFX12: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; encoding: [0x81,0x04,0x87,0xbf] +0x81,0x04,0x87,0xbf + +# GFX12: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; encoding: [0x91,0x01,0x87,0xbf] +0x91,0x01,0x87,0xbf + +# GFX12: s_delay_alu instid1(SALU_CYCLE_2) ; encoding: [0x00,0x05,0x87,0xbf] +0x00,0x05,0x87,0xbf + +# GFX12: s_delay_alu instid1(SALU_CYCLE_3) ; encoding: [0x80,0x05,0x87,0xbf] +0x80,0x05,0x87,0xbf + +# GFX12: s_delay_alu instid0(/* invalid instid value */) | instskip(/* invalid instskip value */) | instid1(/* invalid instid value */) ; encoding: [0xff,0x07,0x87,0xbf] +0xff,0x07,0x87,0xbf + +# GFX12: s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf] +0x00,0x00,0x92,0xbf + +# GFX12: s_denorm_mode 0x1234 ; encoding: [0x34,0x12,0x92,0xbf] +0x34,0x12,0x92,0xbf + +# GFX12: s_denorm_mode 0xc1d1 ; encoding: [0xd1,0xc1,0x92,0xbf] +0xd1,0xc1,0x92,0xbf + +# GFX12: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +0x00,0x00,0xb0,0xbf + +# GFX12: s_endpgm 1 ; encoding: [0x01,0x00,0xb0,0xbf] +0x01,0x00,0xb0,0xbf + +# GFX12: s_endpgm 65535 ; encoding: [0xff,0xff,0xb0,0xbf] +0xff,0xff,0xb0,0xbf + +# GFX12: s_endpgm_saved ; encoding: [0x00,0x00,0xb1,0xbf] +0x00,0x00,0xb1,0xbf + +# GFX12: s_icache_inv ; encoding: [0x00,0x00,0xbc,0xbf] +0x00,0x00,0xbc,0xbf + +# GFX12: s_incperflevel 0 ; encoding: [0x00,0x00,0xb8,0xbf] +0x00,0x00,0xb8,0xbf + +# GFX12: s_incperflevel 0x1234 ; encoding: [0x34,0x12,0xb8,0xbf] +0x34,0x12,0xb8,0xbf + +# GFX12: s_incperflevel 0xc1d1 ; encoding: [0xd1,0xc1,0xb8,0xbf] +0xd1,0xc1,0xb8,0xbf + +# GFX12: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf] +0x00,0x00,0x80,0xbf + +# GFX12: s_nop 0x1234 ; encoding: [0x34,0x12,0x80,0xbf] +0x34,0x12,0x80,0xbf + +# GFX12: s_nop 0xc1d1 ; encoding: [0xd1,0xc1,0x80,0xbf] +0xd1,0xc1,0x80,0xbf + +# GFX12: s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf] +0x00,0x00,0x91,0xbf + +# GFX12: s_round_mode 0x1234 ; encoding: [0x34,0x12,0x91,0xbf] +0x34,0x12,0x91,0xbf + +# GFX12: s_round_mode 0xc1d1 ; encoding: [0xd1,0xc1,0x91,0xbf] +0xd1,0xc1,0x91,0xbf + +# GFX12: s_sendmsg 4660 ; encoding: [0x34,0x12,0xb6,0xbf] +0x34,0x12,0xb6,0xbf + +# GFX12: s_sendmsg 49617 ; encoding: [0xd1,0xc1,0xb6,0xbf] +0xd1,0xc1,0xb6,0xbf + +# GFX12: s_sendmsghalt 4660 ; encoding: [0x34,0x12,0xb7,0xbf] +0x34,0x12,0xb7,0xbf + +# GFX12: s_sendmsghalt 49617 ; encoding: [0xd1,0xc1,0xb7,0xbf] +0xd1,0xc1,0xb7,0xbf + +# GFX12: s_sendmsghalt sendmsg(0, 0, 0) ; encoding: [0x00,0x00,0xb7,0xbf] +0x00,0x00,0xb7,0xbf + +# GFX12: s_sendmsg sendmsg(0, 0, 0) ; encoding: [0x00,0x00,0xb6,0xbf] +0x00,0x00,0xb6,0xbf + +# GFX12: s_sendmsg sendmsg(MSG_RTN_GET_DOORBELL) ; encoding: [0x80,0x00,0xb6,0xbf] +0x80,0x00,0xb6,0xbf + +# GFX12: s_sendmsg sendmsg(MSG_RTN_GET_DDID) ; encoding: [0x81,0x00,0xb6,0xbf] +0x81,0x00,0xb6,0xbf + +# GFX12: s_sendmsg sendmsg(MSG_RTN_GET_TMA) ; encoding: [0x82,0x00,0xb6,0xbf] +0x82,0x00,0xb6,0xbf + +# GFX12: s_sendmsg sendmsg(MSG_RTN_GET_REALTIME) ; encoding: [0x83,0x00,0xb6,0xbf] +0x83,0x00,0xb6,0xbf + +# GFX12: s_sendmsg sendmsg(MSG_RTN_SAVE_WAVE) ; encoding: [0x84,0x00,0xb6,0xbf] +0x84,0x00,0xb6,0xbf + +# GFX12: s_sendmsg sendmsg(MSG_RTN_GET_TBA) ; encoding: [0x85,0x00,0xb6,0xbf] +0x85,0x00,0xb6,0xbf + +# GFX12: s_sethalt 0 ; encoding: [0x00,0x00,0x82,0xbf] +0x00,0x00,0x82,0xbf + +# GFX12: s_sethalt 0x1234 ; encoding: [0x34,0x12,0x82,0xbf] +0x34,0x12,0x82,0xbf + +# GFX12: s_sethalt 0xc1d1 ; encoding: [0xd1,0xc1,0x82,0xbf] +0xd1,0xc1,0x82,0xbf + +# GFX12: s_set_inst_prefetch_distance 0x0 ; encoding: [0x00,0x00,0x84,0xbf] +0x00,0x00,0x84,0xbf + +# GFX12: s_set_inst_prefetch_distance 0x1234 ; encoding: [0x34,0x12,0x84,0xbf] +0x34,0x12,0x84,0xbf + +# GFX12: s_set_inst_prefetch_distance 0xc1d1 ; encoding: [0xd1,0xc1,0x84,0xbf] +0xd1,0xc1,0x84,0xbf + +# GFX12: s_setkill 0 ; encoding: [0x00,0x00,0x81,0xbf] +0x00,0x00,0x81,0xbf + +# GFX12: s_setkill 0x1234 ; encoding: [0x34,0x12,0x81,0xbf] +0x34,0x12,0x81,0xbf + +# GFX12: s_setkill 0xc1d1 ; encoding: [0xd1,0xc1,0x81,0xbf] +0xd1,0xc1,0x81,0xbf + +# GFX12: s_setprio 0 ; encoding: [0x00,0x00,0xb5,0xbf] +0x00,0x00,0xb5,0xbf + +# GFX12: s_setprio 0x1234 ; encoding: [0x34,0x12,0xb5,0xbf] +0x34,0x12,0xb5,0xbf + +# GFX12: s_setprio 0xc1d1 ; encoding: [0xd1,0xc1,0xb5,0xbf] +0xd1,0xc1,0xb5,0xbf + +# GFX12: s_sleep 0 ; encoding: [0x00,0x00,0x83,0xbf] +0x00,0x00,0x83,0xbf + +# GFX12: s_sleep 0x1234 ; encoding: [0x34,0x12,0x83,0xbf] +0x34,0x12,0x83,0xbf + +# GFX12: s_sleep 0xc1d1 ; encoding: [0xd1,0xc1,0x83,0xbf] +0xd1,0xc1,0x83,0xbf + +# GFX12: s_trap 0 ; encoding: [0x00,0x00,0x90,0xbf] +0x00,0x00,0x90,0xbf + +# GFX12: s_trap 0x1234 ; encoding: [0x34,0x12,0x90,0xbf] +0x34,0x12,0x90,0xbf + +# GFX12: s_trap 0xc1d1 ; encoding: [0xd1,0xc1,0x90,0xbf] +0xd1,0xc1,0x90,0xbf + +# GFX12: s_ttracedata ; encoding: [0x00,0x00,0xba,0xbf] +0x00,0x00,0xba,0xbf + +# GFX12: s_ttracedata_imm 0x0 ; encoding: [0x00,0x00,0xbb,0xbf] +0x00,0x00,0xbb,0xbf + +# GFX12: s_ttracedata_imm 0x1234 ; encoding: [0x34,0x12,0xbb,0xbf] +0x34,0x12,0xbb,0xbf + +# GFX12: s_ttracedata_imm 0xc1d1 ; encoding: [0xd1,0xc1,0xbb,0xbf] +0xd1,0xc1,0xbb,0xbf + +# GFX12: s_wait_idle ; encoding: [0x00,0x00,0x8a,0xbf] +0x00,0x00,0x8a,0xbf + +# GFX12: s_wakeup ; encoding: [0x00,0x00,0xb4,0xbf] +0x00,0x00,0xb4,0xbf + +# GFX12: s_wait_event 0x3141 ; encoding: [0x41,0x31,0x8b,0xbf] +0x41,0x31,0x8b,0xbf + +# GFX12: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf] +0xd1,0xc1,0x8b,0xbf diff --git a/llvm/test/MC/Disassembler/X86/apx/invept.txt b/llvm/test/MC/Disassembler/X86/apx/invept.txt new file mode 100644 index 000000000000..dc6bcbbb05cc --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/invept.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: invept 123(%r28,%r29,4), %r19 +# INTEL: invept r19, xmmword ptr [r28 + 4*r29 + 123] +0x62,0x8c,0x7a,0x08,0xf0,0x5c,0xac,0x7b diff --git a/llvm/test/MC/Disassembler/X86/apx/invvpid.txt b/llvm/test/MC/Disassembler/X86/apx/invvpid.txt new file mode 100644 index 000000000000..05abc29b9b46 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/invvpid.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: invvpid 291(%r28,%r29,4), %r19 +# INTEL: invvpid r19, xmmword ptr [r28 + 4*r29 + 291] +0x62,0x8c,0x7a,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00 diff --git a/llvm/test/MC/X86/apx/invept-att.s b/llvm/test/MC/X86/apx/invept-att.s new file mode 100644 index 000000000000..42840bf0b730 --- /dev/null +++ b/llvm/test/MC/X86/apx/invept-att.s @@ -0,0 +1,8 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-1: error: +# ERROR-NOT: error: +# CHECK: invept 123(%r28,%r29,4), %r19 +# CHECK: encoding: [0x62,0x8c,0x7a,0x08,0xf0,0x5c,0xac,0x7b] + invept 123(%r28,%r29,4), %r19 diff --git a/llvm/test/MC/X86/apx/invept-intel.s b/llvm/test/MC/X86/apx/invept-intel.s new file mode 100644 index 000000000000..1c5fac234570 --- /dev/null +++ b/llvm/test/MC/X86/apx/invept-intel.s @@ -0,0 +1,5 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: invept r19, xmmword ptr [r28 + 4*r29 + 123] +# CHECK: encoding: [0x62,0x8c,0x7a,0x08,0xf0,0x5c,0xac,0x7b] + invept r19, xmmword ptr [r28 + 4*r29 + 123] diff --git a/llvm/test/MC/X86/apx/invvpid-att.s b/llvm/test/MC/X86/apx/invvpid-att.s new file mode 100644 index 000000000000..a07489121460 --- /dev/null +++ b/llvm/test/MC/X86/apx/invvpid-att.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-1: error: +# ERROR-NOT: error: +# CHECK: invvpid 291(%r28,%r29,4), %r19 +# CHECK: encoding: [0x62,0x8c,0x7a,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00] + invvpid 291(%r28,%r29,4), %r19 + diff --git a/llvm/test/MC/X86/apx/invvpid-intel.s b/llvm/test/MC/X86/apx/invvpid-intel.s new file mode 100644 index 000000000000..cc4e3e9a618d --- /dev/null +++ b/llvm/test/MC/X86/apx/invvpid-intel.s @@ -0,0 +1,5 @@ +# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +# CHECK: invvpid r19, xmmword ptr [r28 + 4*r29 + 291] +# CHECK: encoding: [0x62,0x8c,0x7a,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00] + invvpid r19, xmmword ptr [r28 + 4*r29 + 291] diff --git a/llvm/test/ThinLTO/X86/deadstrip.ll b/llvm/test/ThinLTO/X86/deadstrip.ll index 4e97cc3317fb..2a3e15f87097 100644 --- a/llvm/test/ThinLTO/X86/deadstrip.ll +++ b/llvm/test/ThinLTO/X86/deadstrip.ll @@ -37,23 +37,23 @@ ; RUN: llvm-bcanalyzer -dump %t.out.index.bc | FileCheck %s --check-prefix=COMBINED ; Live, NotEligibleForImport, dso_local, Internal -; COMBINED-DAG: This Inner Loop Header: Depth=1 -; CHECK-NEXT: str w8, [x9, #4] -; CHECK-NEXT: add w8, w8, #1 -; CHECK-NEXT: str w8, [x9] -; CHECK-NEXT: cmp w8, w1 +; CHECK-NEXT: str w9, [x8, #3140] +; CHECK-NEXT: add w9, w9, #1 +; CHECK-NEXT: str w9, [x8, #3136] +; CHECK-NEXT: cmp w9, w1 ; CHECK-NEXT: b.lt .LBB0_1 ; CHECK-NEXT: .LBB0_2: // %while_end ; CHECK-NEXT: ret @@ -47,16 +46,15 @@ define void @test2(ptr %struct, i32 %n) { ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: cbz x0, .LBB1_3 ; CHECK-NEXT: // %bb.1: // %while_cond.preheader -; CHECK-NEXT: mov w8, #40000 // =0x9c40 ; CHECK-NEXT: mov w9, wzr -; CHECK-NEXT: add x8, x0, x8 +; CHECK-NEXT: add x8, x0, #9, lsl #12 // =36864 ; CHECK-NEXT: cmp w9, w1 ; CHECK-NEXT: b.ge .LBB1_3 ; CHECK-NEXT: .LBB1_2: // %while_body ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: str w9, [x8, #4] +; CHECK-NEXT: str w9, [x8, #3140] ; CHECK-NEXT: add w9, w9, #1 -; CHECK-NEXT: str w9, [x8] +; CHECK-NEXT: str w9, [x8, #3136] ; CHECK-NEXT: cmp w9, w1 ; CHECK-NEXT: b.lt .LBB1_2 ; CHECK-NEXT: .LBB1_3: // %while_end @@ -89,16 +87,15 @@ define void @test3(ptr %s1, ptr %s2, i1 %cond, i32 %n) { ; CHECK-NEXT: csel x8, x1, x0, ne ; CHECK-NEXT: cbz x8, .LBB2_3 ; CHECK-NEXT: // %bb.1: // %while_cond.preheader -; CHECK-NEXT: mov w10, #40000 // =0x9c40 ; CHECK-NEXT: mov w9, wzr -; CHECK-NEXT: add x8, x8, x10 +; CHECK-NEXT: add x8, x8, #9, lsl #12 // =36864 ; CHECK-NEXT: cmp w9, w3 ; CHECK-NEXT: b.ge .LBB2_3 ; CHECK-NEXT: .LBB2_2: // %while_body ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: str w9, [x8, #4] +; CHECK-NEXT: str w9, [x8, #3140] ; CHECK-NEXT: add w9, w9, #1 -; CHECK-NEXT: str w9, [x8] +; CHECK-NEXT: str w9, [x8, #3136] ; CHECK-NEXT: cmp w9, w3 ; CHECK-NEXT: b.lt .LBB2_2 ; CHECK-NEXT: .LBB2_3: // %while_end @@ -141,17 +138,15 @@ define void @test4(i32 %n) uwtable personality ptr @__FrameHandler { ; CHECK-NEXT: .cfi_personality 156, DW.ref.__FrameHandler ; CHECK-NEXT: .cfi_lsda 28, .Lexception0 ; CHECK-NEXT: // %bb.0: // %entry -; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill +; CHECK-NEXT: str x30, [sp, #-32]! // 8-byte Folded Spill ; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: .cfi_offset w19, -8 ; CHECK-NEXT: .cfi_offset w20, -16 -; CHECK-NEXT: .cfi_offset w21, -24 ; CHECK-NEXT: .cfi_offset w30, -32 ; CHECK-NEXT: .cfi_remember_state ; CHECK-NEXT: mov w19, w0 -; CHECK-NEXT: mov w21, wzr -; CHECK-NEXT: mov w20, #40000 // =0x9c40 +; CHECK-NEXT: mov w20, wzr ; CHECK-NEXT: .LBB3_1: // %while_cond ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: .Ltmp0: @@ -159,23 +154,22 @@ define void @test4(i32 %n) uwtable personality ptr @__FrameHandler { ; CHECK-NEXT: .Ltmp1: ; CHECK-NEXT: // %bb.2: // %while_cond_x.split ; CHECK-NEXT: // in Loop: Header=BB3_1 Depth=1 -; CHECK-NEXT: add x8, x0, x20 -; CHECK-NEXT: cmp w21, w19 -; CHECK-NEXT: str wzr, [x8] +; CHECK-NEXT: add x8, x0, #9, lsl #12 // =36864 +; CHECK-NEXT: cmp w20, w19 +; CHECK-NEXT: str wzr, [x8, #3136] ; CHECK-NEXT: b.ge .LBB3_4 ; CHECK-NEXT: // %bb.3: // %while_body ; CHECK-NEXT: // in Loop: Header=BB3_1 Depth=1 -; CHECK-NEXT: str w21, [x8, #4] -; CHECK-NEXT: add w21, w21, #1 -; CHECK-NEXT: str w21, [x8] +; CHECK-NEXT: str w20, [x8, #3140] +; CHECK-NEXT: add w20, w20, #1 +; CHECK-NEXT: str w20, [x8, #3136] ; CHECK-NEXT: b .LBB3_1 ; CHECK-NEXT: .LBB3_4: // %while_end ; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload -; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload +; CHECK-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload ; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: .cfi_restore w19 ; CHECK-NEXT: .cfi_restore w20 -; CHECK-NEXT: .cfi_restore w21 ; CHECK-NEXT: .cfi_restore w30 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB3_5: // %cleanup @@ -223,14 +217,13 @@ define void @test5(ptr %s, i32 %n) { ; CHECK-NEXT: ldr x8, [x0] ; CHECK-NEXT: mov w9, wzr ; CHECK-NEXT: add x8, x8, #19, lsl #12 // =77824 -; CHECK-NEXT: add x8, x8, #2176 ; CHECK-NEXT: cmp w9, w1 ; CHECK-NEXT: b.ge .LBB4_2 ; CHECK-NEXT: .LBB4_1: // %while_body ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: str w9, [x8, #4] +; CHECK-NEXT: str w9, [x8, #2180] ; CHECK-NEXT: add w9, w9, #1 -; CHECK-NEXT: str w9, [x8] +; CHECK-NEXT: str w9, [x8, #2176] ; CHECK-NEXT: cmp w9, w1 ; CHECK-NEXT: b.lt .LBB4_1 ; CHECK-NEXT: .LBB4_2: // %while_end diff --git a/llvm/test/Transforms/CodeGenPrepare/debug-info-on-skipped-selects.ll b/llvm/test/Transforms/CodeGenPrepare/debug-info-on-skipped-selects.ll new file mode 100644 index 000000000000..ffd4a0170ac9 --- /dev/null +++ b/llvm/test/Transforms/CodeGenPrepare/debug-info-on-skipped-selects.ll @@ -0,0 +1,68 @@ +; RUN: llc %s -stop-after=codegenprepare -o - | FileCheck %s +; RUN: llc %s -stop-after=codegenprepare -o - --try-experimental-debuginfo-iterators | FileCheck %s +; REQUIRES: x86-registered-target +; +; Test that when we skip over multiple selects in CGP, that the debug-info +; attached to those selects is still fixed up. + +; CHECK: declare void @llvm.dbg.value(metadata, +; CHECK: call void @llvm.dbg.value(metadata ptr %sunkaddr, + +source_filename = "reduced.ll" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +%"class.(anonymous namespace)::CFIInstrInserter" = type { ptr, ptr, ptr, ptr } + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) #0 + +define i1 @_ZN12_GLOBAL__N_116CFIInstrInserter20runOnMachineFunctionERN4llvm15MachineFunctionE(ptr %this, i1 %or.cond.i) !dbg !5 { +entry: + %CSRLocMap.i = getelementptr %"class.(anonymous namespace)::CFIInstrInserter", ptr %this, i64 0, i32 2, !dbg !16 + %bf.load.i.i.i.i = load i32, ptr %CSRLocMap.i, align 8, !dbg !17 + br i1 %or.cond.i, label %_ZN4llvm12DenseMapBaseINS_13SmallDenseMapIjN12_GLOBAL__N_116CFIInstrInserter16CSRSavedLocationELj16ENS_12DenseMapInfoIjvEENS_6detail12DenseMapPairIjS4_EEEEjS4_S6_S9_E5clearEv.exit.i, label %if.end.i.i, !dbg !18 + +if.end.i.i: ; preds = %entry + store ptr null, ptr null, align 8, !dbg !19 + %bf.load.i.i.i.pre.i.i.i.i.i = load i32, ptr %CSRLocMap.i, align 8, !dbg !20 + %cond.i.i.i.i.i.i.i.i.i = select i1 false, ptr null, ptr null, !dbg !21 + tail call void @llvm.dbg.value(metadata ptr %CSRLocMap.i, metadata !14, metadata !DIExpression()), !dbg !21 + %cond.i.i.i7.i.i.i.i.i.i = select i1 false, i32 0, i32 0, !dbg !22 + br label %_ZN4llvm12DenseMapBaseINS_13SmallDenseMapIjN12_GLOBAL__N_116CFIInstrInserter16CSRSavedLocationELj16ENS_12DenseMapInfoIjvEENS_6detail12DenseMapPairIjS4_EEEEjS4_S6_S9_E5clearEv.exit.i, !dbg !23 + +_ZN4llvm12DenseMapBaseINS_13SmallDenseMapIjN12_GLOBAL__N_116CFIInstrInserter16CSRSavedLocationELj16ENS_12DenseMapInfoIjvEENS_6detail12DenseMapPairIjS4_EEEEjS4_S6_S9_E5clearEv.exit.i: ; preds = %if.end.i.i, %entry + ret i1 false, !dbg !24 +} + +attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + +!llvm.module.flags = !{!0} +!llvm.dbg.cu = !{!1} +!llvm.debugify = !{!3, !4} + +!0 = !{i32 2, !"Debug Info Version", i32 3} +!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +!2 = !DIFile(filename: "reduced.ll", directory: "/") +!3 = !{i32 9} +!4 = !{i32 5} +!5 = distinct !DISubprogram(name: "_ZN12_GLOBAL__N_116CFIInstrInserter20runOnMachineFunctionERN4llvm15MachineFunctionE", linkageName: "_ZN12_GLOBAL__N_116CFIInstrInserter20runOnMachineFunctionERN4llvm15MachineFunctionE", scope: null, file: !2, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !1, retainedNodes: !8) +!6 = !DISubroutineType(types: !7) +!7 = !{} +!8 = !{!9, !11, !13, !14, !15} +!9 = !DILocalVariable(name: "1", scope: !5, file: !2, line: 1, type: !10) +!10 = !DIBasicType(name: "ty64", size: 64, encoding: DW_ATE_unsigned) +!11 = !DILocalVariable(name: "2", scope: !5, file: !2, line: 2, type: !12) +!12 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) +!13 = !DILocalVariable(name: "3", scope: !5, file: !2, line: 5, type: !12) +!14 = !DILocalVariable(name: "4", scope: !5, file: !2, line: 6, type: !10) +!15 = !DILocalVariable(name: "5", scope: !5, file: !2, line: 7, type: !12) +!16 = !DILocation(line: 1, column: 1, scope: !5) +!17 = !DILocation(line: 2, column: 1, scope: !5) +!18 = !DILocation(line: 3, column: 1, scope: !5) +!19 = !DILocation(line: 4, column: 1, scope: !5) +!20 = !DILocation(line: 5, column: 1, scope: !5) +!21 = !DILocation(line: 6, column: 1, scope: !5) +!22 = !DILocation(line: 7, column: 1, scope: !5) +!23 = !DILocation(line: 8, column: 1, scope: !5) +!24 = !DILocation(line: 9, column: 1, scope: !5) diff --git a/llvm/test/Transforms/ConstraintElimination/or.ll b/llvm/test/Transforms/ConstraintElimination/or.ll index 4f46f546bd32..2f24519ddd1d 100644 --- a/llvm/test/Transforms/ConstraintElimination/or.ll +++ b/llvm/test/Transforms/ConstraintElimination/or.ll @@ -414,20 +414,20 @@ define void @test_or_as_add_ult(i8 %init_val, i8 %high) { ; CHECK: then: ; CHECK-NEXT: [[F_0:%.*]] = icmp ult i8 [[START]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[F_0]]) -; CHECK-NEXT: [[I_1:%.*]] = or i8 [[START]], 1 +; CHECK-NEXT: [[I_1:%.*]] = or disjoint i8 [[START]], 1 ; CHECK-NEXT: [[F_1:%.*]] = icmp ult i8 [[I_1]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[F_1]]) -; CHECK-NEXT: [[I_2:%.*]] = or i8 [[START]], 2 +; CHECK-NEXT: [[I_2:%.*]] = or disjoint i8 [[START]], 2 ; CHECK-NEXT: [[F_2:%.*]] = icmp ult i8 [[I_2]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[F_2]]) ; CHECK-NEXT: ret void ; CHECK: end: ; CHECK-NEXT: call void @use(i1 true) -; CHECK-NEXT: [[START_1:%.*]] = or i8 [[START]], 1 +; CHECK-NEXT: [[START_1:%.*]] = or disjoint i8 [[START]], 1 ; CHECK-NEXT: call void @use(i1 true) -; CHECK-NEXT: [[START_2:%.*]] = or i8 [[START]], 2 +; CHECK-NEXT: [[START_2:%.*]] = or disjoint i8 [[START]], 2 ; CHECK-NEXT: call void @use(i1 true) -; CHECK-NEXT: [[START_3:%.*]] = or i8 [[START]], 3 +; CHECK-NEXT: [[START_3:%.*]] = or disjoint i8 [[START]], 3 ; CHECK-NEXT: call void @use(i1 true) ; CHECK-NEXT: [[START_4:%.*]] = or i8 [[START]], 4 ; CHECK-NEXT: [[C_4:%.*]] = icmp ult i8 [[START_4]], [[HIGH]] @@ -443,10 +443,10 @@ entry: then: ; preds = %entry %f.0 = icmp ult i8 %start, %high call void @use(i1 %f.0) - %i.1 = or i8 %start, 1 + %i.1 = or disjoint i8 %start, 1 %f.1 = icmp ult i8 %i.1, %high call void @use(i1 %f.1) - %i.2 = or i8 %start, 2 + %i.2 = or disjoint i8 %start, 2 %f.2 = icmp ult i8 %i.2, %high call void @use(i1 %f.2) ret void @@ -454,13 +454,13 @@ then: ; preds = %entry end: ; preds = %entry %t.0 = icmp ult i8 %start, %high call void @use(i1 %t.0) - %start.1 = or i8 %start, 1 + %start.1 = or disjoint i8 %start, 1 %t.1 = icmp ult i8 %start.1, %high call void @use(i1 %t.1) - %start.2 = or i8 %start, 2 + %start.2 = or disjoint i8 %start, 2 %t.2 = icmp ult i8 %start.2, %high call void @use(i1 %t.2) - %start.3 = or i8 %start, 3 + %start.3 = or disjoint i8 %start, 3 %t.3 = icmp ult i8 %start.3, %high call void @use(i1 %t.3) %start.4 = or i8 %start, 4 @@ -479,20 +479,20 @@ define void @test_or_as_add_ule(i8 %init_val, i8 %high) { ; CHECK: then: ; CHECK-NEXT: [[F_0:%.*]] = icmp ule i8 [[START]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[F_0]]) -; CHECK-NEXT: [[I_1:%.*]] = or i8 [[START]], 1 +; CHECK-NEXT: [[I_1:%.*]] = or disjoint i8 [[START]], 1 ; CHECK-NEXT: [[F_1:%.*]] = icmp ule i8 [[I_1]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[F_1]]) -; CHECK-NEXT: [[I_2:%.*]] = or i8 [[START]], 2 +; CHECK-NEXT: [[I_2:%.*]] = or disjoint i8 [[START]], 2 ; CHECK-NEXT: [[F_2:%.*]] = icmp ule i8 [[I_2]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[F_2]]) ; CHECK-NEXT: ret void ; CHECK: end: ; CHECK-NEXT: call void @use(i1 true) -; CHECK-NEXT: [[START_1:%.*]] = or i8 [[START]], 1 +; CHECK-NEXT: [[START_1:%.*]] = or disjoint i8 [[START]], 1 ; CHECK-NEXT: call void @use(i1 true) -; CHECK-NEXT: [[START_2:%.*]] = or i8 [[START]], 2 +; CHECK-NEXT: [[START_2:%.*]] = or disjoint i8 [[START]], 2 ; CHECK-NEXT: call void @use(i1 true) -; CHECK-NEXT: [[START_3:%.*]] = or i8 [[START]], 3 +; CHECK-NEXT: [[START_3:%.*]] = or disjoint i8 [[START]], 3 ; CHECK-NEXT: call void @use(i1 true) ; CHECK-NEXT: [[START_4:%.*]] = or i8 [[START]], 4 ; CHECK-NEXT: [[T_4:%.*]] = icmp ule i8 [[START_4]], [[HIGH]] @@ -511,10 +511,10 @@ entry: then: ; preds = %entry %f.0 = icmp ule i8 %start, %high call void @use(i1 %f.0) - %i.1 = or i8 %start, 1 + %i.1 = or disjoint i8 %start, 1 %f.1 = icmp ule i8 %i.1, %high call void @use(i1 %f.1) - %i.2 = or i8 %start, 2 + %i.2 = or disjoint i8 %start, 2 %f.2 = icmp ule i8 %i.2, %high call void @use(i1 %f.2) ret void @@ -522,13 +522,13 @@ then: ; preds = %entry end: ; preds = %entry %t.0 = icmp ule i8 %start, %high call void @use(i1 %t.0) - %start.1 = or i8 %start, 1 + %start.1 = or disjoint i8 %start, 1 %t.1 = icmp ule i8 %start.1, %high call void @use(i1 %t.1) - %start.2 = or i8 %start, 2 + %start.2 = or disjoint i8 %start, 2 %t.2 = icmp ule i8 %start.2, %high call void @use(i1 %t.2) - %start.3 = or i8 %start, 3 + %start.3 = or disjoint i8 %start, 3 %t.3 = icmp ule i8 %start.3, %high call void @use(i1 %t.3) %start.4 = or i8 %start, 4 @@ -551,20 +551,20 @@ define void @test_or_as_add_ugt(i8 %init_val, i8 %high) { ; CHECK: then: ; CHECK-NEXT: [[T_0:%.*]] = icmp ugt i8 [[START]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[T_0]]) -; CHECK-NEXT: [[I_1:%.*]] = or i8 [[START]], 1 +; CHECK-NEXT: [[I_1:%.*]] = or disjoint i8 [[START]], 1 ; CHECK-NEXT: [[T_1:%.*]] = icmp ugt i8 [[I_1]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[T_1]]) -; CHECK-NEXT: [[I_2:%.*]] = or i8 [[START]], 2 +; CHECK-NEXT: [[I_2:%.*]] = or disjoint i8 [[START]], 2 ; CHECK-NEXT: [[T_2:%.*]] = icmp ugt i8 [[I_2]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[T_2]]) ; CHECK-NEXT: ret void ; CHECK: end: ; CHECK-NEXT: call void @use(i1 false) -; CHECK-NEXT: [[START_1:%.*]] = or i8 [[START]], 1 +; CHECK-NEXT: [[START_1:%.*]] = or disjoint i8 [[START]], 1 ; CHECK-NEXT: call void @use(i1 false) -; CHECK-NEXT: [[START_2:%.*]] = or i8 [[START]], 2 +; CHECK-NEXT: [[START_2:%.*]] = or disjoint i8 [[START]], 2 ; CHECK-NEXT: call void @use(i1 false) -; CHECK-NEXT: [[START_3:%.*]] = or i8 [[START]], 3 +; CHECK-NEXT: [[START_3:%.*]] = or disjoint i8 [[START]], 3 ; CHECK-NEXT: call void @use(i1 false) ; CHECK-NEXT: [[START_4:%.*]] = or i8 [[START]], 4 ; CHECK-NEXT: [[F_4:%.*]] = icmp ugt i8 [[START_4]], [[HIGH]] @@ -583,10 +583,10 @@ entry: then: ; preds = %entry %t.0 = icmp ugt i8 %start, %high call void @use(i1 %t.0) - %i.1 = or i8 %start, 1 + %i.1 = or disjoint i8 %start, 1 %t.1 = icmp ugt i8 %i.1, %high call void @use(i1 %t.1) - %i.2 = or i8 %start, 2 + %i.2 = or disjoint i8 %start, 2 %t.2 = icmp ugt i8 %i.2, %high call void @use(i1 %t.2) ret void @@ -594,13 +594,13 @@ then: ; preds = %entry end: ; preds = %entry %f.0 = icmp ugt i8 %start, %high call void @use(i1 %f.0) - %start.1 = or i8 %start, 1 + %start.1 = or disjoint i8 %start, 1 %f.1 = icmp ugt i8 %start.1, %high call void @use(i1 %f.1) - %start.2 = or i8 %start, 2 + %start.2 = or disjoint i8 %start, 2 %f.2 = icmp ugt i8 %start.2, %high call void @use(i1 %f.2) - %start.3 = or i8 %start, 3 + %start.3 = or disjoint i8 %start, 3 %f.3 = icmp ugt i8 %start.3, %high call void @use(i1 %f.3) %start.4 = or i8 %start, 4 @@ -622,20 +622,20 @@ define void @test_or_as_add_uge(i8 %init_val, i8 %high) { ; CHECK: then: ; CHECK-NEXT: [[T_0:%.*]] = icmp ugt i8 [[START]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[T_0]]) -; CHECK-NEXT: [[I_1:%.*]] = or i8 [[START]], 1 +; CHECK-NEXT: [[I_1:%.*]] = or disjoint i8 [[START]], 1 ; CHECK-NEXT: [[T_1:%.*]] = icmp uge i8 [[I_1]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[T_1]]) -; CHECK-NEXT: [[I_2:%.*]] = or i8 [[START]], 2 +; CHECK-NEXT: [[I_2:%.*]] = or disjoint i8 [[START]], 2 ; CHECK-NEXT: [[T_2:%.*]] = icmp uge i8 [[I_2]], [[HIGH]] ; CHECK-NEXT: call void @use(i1 [[T_2]]) ; CHECK-NEXT: ret void ; CHECK: end: ; CHECK-NEXT: call void @use(i1 false) -; CHECK-NEXT: [[START_1:%.*]] = or i8 [[START]], 1 +; CHECK-NEXT: [[START_1:%.*]] = or disjoint i8 [[START]], 1 ; CHECK-NEXT: call void @use(i1 false) -; CHECK-NEXT: [[START_2:%.*]] = or i8 [[START]], 2 +; CHECK-NEXT: [[START_2:%.*]] = or disjoint i8 [[START]], 2 ; CHECK-NEXT: call void @use(i1 false) -; CHECK-NEXT: [[START_3:%.*]] = or i8 [[START]], 3 +; CHECK-NEXT: [[START_3:%.*]] = or disjoint i8 [[START]], 3 ; CHECK-NEXT: call void @use(i1 false) ; CHECK-NEXT: [[START_4:%.*]] = or i8 [[START]], 4 ; CHECK-NEXT: [[C_4:%.*]] = icmp uge i8 [[START_4]], [[HIGH]] @@ -654,10 +654,10 @@ entry: then: ; preds = %entry %t.0 = icmp ugt i8 %start, %high call void @use(i1 %t.0) - %i.1 = or i8 %start, 1 + %i.1 = or disjoint i8 %start, 1 %t.1 = icmp uge i8 %i.1, %high call void @use(i1 %t.1) - %i.2 = or i8 %start, 2 + %i.2 = or disjoint i8 %start, 2 %t.2 = icmp uge i8 %i.2, %high call void @use(i1 %t.2) ret void @@ -665,13 +665,13 @@ then: ; preds = %entry end: ; preds = %entry %f.0 = icmp ugt i8 %start, %high call void @use(i1 %f.0) - %start.1 = or i8 %start, 1 + %start.1 = or disjoint i8 %start, 1 %f.1 = icmp uge i8 %start.1, %high call void @use(i1 %f.1) - %start.2 = or i8 %start, 2 + %start.2 = or disjoint i8 %start, 2 %f.2 = icmp uge i8 %start.2, %high call void @use(i1 %f.2) - %start.3 = or i8 %start, 3 + %start.3 = or disjoint i8 %start, 3 %f.3 = icmp uge i8 %start.3, %high call void @use(i1 %f.3) %start.4 = or i8 %start, 4 @@ -748,3 +748,68 @@ end: ; preds = %entry ret void } + +; Nothing in the IR implies the disjoint flag, but we can still use it +; to decompose into an add. +define void @test_decompose_explicit_disjoint(i8 %start, i8 %high) { +; CHECK-LABEL: @test_decompose_explicit_disjoint( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[START_PLUS_3:%.*]] = add nuw i8 [[START:%.*]], 3 +; CHECK-NEXT: [[C_1:%.*]] = icmp uge i8 [[START_PLUS_3]], [[HIGH:%.*]] +; CHECK-NEXT: br i1 [[C_1]], label [[THEN:%.*]], label [[END:%.*]] +; CHECK: then: +; CHECK-NEXT: [[I_1:%.*]] = or disjoint i8 [[START]], 1 +; CHECK-NEXT: [[T_1:%.*]] = icmp uge i8 [[I_1]], [[HIGH]] +; CHECK-NEXT: call void @use(i1 [[T_1]]) +; CHECK-NEXT: [[I_2:%.*]] = or disjoint i8 [[START]], 2 +; CHECK-NEXT: [[T_2:%.*]] = icmp uge i8 [[I_2]], [[HIGH]] +; CHECK-NEXT: call void @use(i1 [[T_2]]) +; CHECK-NEXT: ret void +; CHECK: end: +; CHECK-NEXT: [[START_1:%.*]] = or disjoint i8 [[START]], 1 +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: [[START_2:%.*]] = or disjoint i8 [[START]], 2 +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: [[START_3:%.*]] = or disjoint i8 [[START]], 3 +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: [[START_4:%.*]] = or disjoint i8 [[START]], 4 +; CHECK-NEXT: [[C_4:%.*]] = icmp uge i8 [[START_4]], [[HIGH]] +; CHECK-NEXT: call void @use(i1 [[C_4]]) +; CHECK-NEXT: [[START_5:%.*]] = or disjoint i8 [[START]], 5 +; CHECK-NEXT: [[C_5:%.*]] = icmp uge i8 [[START_5]], [[HIGH]] +; CHECK-NEXT: call void @use(i1 [[C_5]]) +; CHECK-NEXT: ret void +; +entry: + %start.plus.3 = add nuw i8 %start, 3 + %c.1 = icmp uge i8 %start.plus.3, %high + br i1 %c.1, label %then, label %end + +then: ; preds = %entry + %i.1 = or disjoint i8 %start, 1 + %t.1 = icmp uge i8 %i.1, %high + call void @use(i1 %t.1) + %i.2 = or disjoint i8 %start, 2 + %t.2 = icmp uge i8 %i.2, %high + call void @use(i1 %t.2) + ret void + +end: ; preds = %entry + %start.1 = or disjoint i8 %start, 1 + %f.1 = icmp uge i8 %start.1, %high + call void @use(i1 %f.1) + %start.2 = or disjoint i8 %start, 2 + %f.2 = icmp uge i8 %start.2, %high + call void @use(i1 %f.2) + %start.3 = or disjoint i8 %start, 3 + %f.3 = icmp uge i8 %start.3, %high + call void @use(i1 %f.3) + %start.4 = or disjoint i8 %start, 4 + %c.4 = icmp uge i8 %start.4, %high + call void @use(i1 %c.4) + %start.5 = or disjoint i8 %start, 5 + %c.5 = icmp uge i8 %start.5, %high + call void @use(i1 %c.5) + + ret void +} diff --git a/llvm/test/Transforms/GVN/captured-before.ll b/llvm/test/Transforms/GVN/captured-before.ll index 62529b8c1cf6..0977f6e577b5 100644 --- a/llvm/test/Transforms/GVN/captured-before.ll +++ b/llvm/test/Transforms/GVN/captured-before.ll @@ -132,3 +132,21 @@ loop: call void @use(i32 %v) memory(none) br label %loop } + +define i32 @test_splat_gep_capture(<1 x i32> %index) { +; CHECK-LABEL: define i32 @test_splat_gep_capture( +; CHECK-SAME: <1 x i32> [[INDEX:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 +; CHECK-NEXT: store i32 123, ptr [[A]], align 4 +; CHECK-NEXT: [[PTRS:%.*]] = getelementptr inbounds i32, ptr [[A]], <1 x i32> [[INDEX]] +; CHECK-NEXT: call void @some_call(<1 x ptr> [[PTRS]]) +; CHECK-NEXT: [[RELOAD:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: ret i32 [[RELOAD]] +; + %a = alloca i32 + store i32 123, ptr %a + %ptrs = getelementptr inbounds i32, ptr %a, <1 x i32> %index + call void @some_call(<1 x ptr> %ptrs) + %reload = load i32, ptr %a + ret i32 %reload +} diff --git a/llvm/test/Transforms/GlobalOpt/globalvar-code-model.ll b/llvm/test/Transforms/GlobalOpt/globalvar-code-model.ll new file mode 100644 index 000000000000..276a49474f73 --- /dev/null +++ b/llvm/test/Transforms/GlobalOpt/globalvar-code-model.ll @@ -0,0 +1,11 @@ +; RUN: opt -passes=globalopt -S < %s | FileCheck %s + +@G = internal global i32 5, code_model "large" + +define i32 @test() norecurse { + %a = load i32, ptr @G + store i32 4, ptr @G + ret i32 %a +} + +; CHECK: @G = internal unnamed_addr global i1 false, code_model "large" diff --git a/llvm/test/Transforms/IRCE/stride_more_than_1.ll b/llvm/test/Transforms/IRCE/stride_more_than_1.ll index 92cd410b12f6..749c17d11820 100644 --- a/llvm/test/Transforms/IRCE/stride_more_than_1.ll +++ b/llvm/test/Transforms/IRCE/stride_more_than_1.ll @@ -917,7 +917,7 @@ define i32 @binop_or_is_iv_base(ptr %p, i32 %end) { ; CHECK-NEXT: br i1 true, label [[GUARDED]], label [[DEOPT_LOOPEXIT2:%.*]] ; CHECK: guarded: ; CHECK-NEXT: [[IV_ADD]] = add i32 [[IV]], 8 -; CHECK-NEXT: [[IV_OR:%.*]] = or i32 [[IV_ADD]], 7 +; CHECK-NEXT: [[IV_OR:%.*]] = or disjoint i32 [[IV_ADD]], 7 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[IV_OR]], [[END]] ; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[IV_OR]], [[EXIT_MAINLOOP_AT]] ; CHECK-NEXT: br i1 [[TMP2]], label [[LOOP_HEADER]], label [[MAIN_EXIT_SELECTOR:%.*]] @@ -951,7 +951,7 @@ define i32 @binop_or_is_iv_base(ptr %p, i32 %end) { ; CHECK-NEXT: br i1 [[CHECK_POSTLOOP]], label [[GUARDED_POSTLOOP]], label [[DEOPT_LOOPEXIT:%.*]] ; CHECK: guarded.postloop: ; CHECK-NEXT: [[IV_ADD_POSTLOOP]] = add i32 [[IV_POSTLOOP]], 8 -; CHECK-NEXT: [[IV_OR_POSTLOOP:%.*]] = or i32 [[IV_ADD_POSTLOOP]], 7 +; CHECK-NEXT: [[IV_OR_POSTLOOP:%.*]] = or disjoint i32 [[IV_ADD_POSTLOOP]], 7 ; CHECK-NEXT: [[CMP_POSTLOOP:%.*]] = icmp slt i32 [[IV_OR_POSTLOOP]], [[END]] ; CHECK-NEXT: br i1 [[CMP_POSTLOOP]], label [[LOOP_HEADER_POSTLOOP]], label [[COMMON_RET_LOOPEXIT_LOOPEXIT:%.*]], !llvm.loop [[LOOP21:![0-9]+]], !loop_constrainer.loop.clone !6 ; @@ -967,7 +967,7 @@ loop.header: guarded: %iv.add = add i32 %iv, 8 - %iv.or = or i32 %iv.add, 7 + %iv.or = or disjoint i32 %iv.add, 7 %cmp = icmp slt i32 %iv.or, %end br i1 %cmp, label %loop.header, label %common.ret diff --git a/llvm/test/Transforms/IndVarSimplify/ashr-tripcount.ll b/llvm/test/Transforms/IndVarSimplify/ashr-tripcount.ll index 4dedf7c6b633..54421f1a5bae 100644 --- a/llvm/test/Transforms/IndVarSimplify/ashr-tripcount.ll +++ b/llvm/test/Transforms/IndVarSimplify/ashr-tripcount.ll @@ -53,21 +53,21 @@ bb3: ; preds = %bb4, %bb.nph %t9 = zext i32 %t8 to i64 ; [#uses=1] %t10 = getelementptr float, ptr %pow4_3_tab_ptr, i64 %t9 ; [#uses=1] %t11 = load float, ptr %t10, align 4 ; [#uses=1] - %t12 = or i32 %i.05, 1 ; [#uses=1] + %t12 = or disjoint i32 %i.05, 1 ; [#uses=1] %t13 = sext i32 %t12 to i64 ; [#uses=1] %t14 = getelementptr i32, ptr %quaSpectrum, i64 %t13 ; [#uses=1] %t15 = load i32, ptr %t14, align 4 ; [#uses=1] %t16 = zext i32 %t15 to i64 ; [#uses=1] %t17 = getelementptr float, ptr %pow4_3_tab_ptr, i64 %t16 ; [#uses=1] %t18 = load float, ptr %t17, align 4 ; [#uses=1] - %t19 = or i32 %i.05, 2 ; [#uses=1] + %t19 = or disjoint i32 %i.05, 2 ; [#uses=1] %t20 = sext i32 %t19 to i64 ; [#uses=1] %t21 = getelementptr i32, ptr %quaSpectrum, i64 %t20 ; [#uses=1] %t22 = load i32, ptr %t21, align 4 ; [#uses=1] %t23 = zext i32 %t22 to i64 ; [#uses=1] %t24 = getelementptr float, ptr %pow4_3_tab_ptr, i64 %t23 ; [#uses=1] %t25 = load float, ptr %t24, align 4 ; [#uses=1] - %t26 = or i32 %i.05, 3 ; [#uses=1] + %t26 = or disjoint i32 %i.05, 3 ; [#uses=1] %t27 = sext i32 %t26 to i64 ; [#uses=1] %t28 = getelementptr i32, ptr %quaSpectrum, i64 %t27 ; [#uses=1] %t29 = load i32, ptr %t28, align 4 ; [#uses=1] @@ -78,17 +78,17 @@ bb3: ; preds = %bb4, %bb.nph %t34 = sext i32 %i.05 to i64 ; [#uses=1] %t35 = getelementptr float, ptr %iquaSpectrum, i64 %t34 ; [#uses=1] store float %t33, ptr %t35, align 4 - %t36 = or i32 %i.05, 1 ; [#uses=1] + %t36 = or disjoint i32 %i.05, 1 ; [#uses=1] %t37 = fmul float %t18, %invQuantizer.0 ; [#uses=1] %t38 = sext i32 %t36 to i64 ; [#uses=1] %t39 = getelementptr float, ptr %iquaSpectrum, i64 %t38 ; [#uses=1] store float %t37, ptr %t39, align 4 - %t40 = or i32 %i.05, 2 ; [#uses=1] + %t40 = or disjoint i32 %i.05, 2 ; [#uses=1] %t41 = fmul float %t25, %invQuantizer.0 ; [#uses=1] %t42 = sext i32 %t40 to i64 ; [#uses=1] %t43 = getelementptr float, ptr %iquaSpectrum, i64 %t42 ; [#uses=1] store float %t41, ptr %t43, align 4 - %t44 = or i32 %i.05, 3 ; [#uses=1] + %t44 = or disjoint i32 %i.05, 3 ; [#uses=1] %t45 = fmul float %t32, %invQuantizer.0 ; [#uses=1] %t46 = sext i32 %t44 to i64 ; [#uses=1] %t47 = getelementptr float, ptr %iquaSpectrum, i64 %t46 ; [#uses=1] diff --git a/llvm/test/Transforms/IndVarSimplify/lcssa-preservation.ll b/llvm/test/Transforms/IndVarSimplify/lcssa-preservation.ll index a372fa900ddb..f00a111aa6a6 100644 --- a/llvm/test/Transforms/IndVarSimplify/lcssa-preservation.ll +++ b/llvm/test/Transforms/IndVarSimplify/lcssa-preservation.ll @@ -109,9 +109,9 @@ define void @pr57000(i64 %a) { ; CHECK-NEXT: br label [[LOOP_2_HEADER:%.*]] ; CHECK: loop.2.header: ; CHECK-NEXT: switch i8 [[CMP_EXT_LCSSA]], label [[LOOP_1_LOOPEXIT:%.*]] [ -; CHECK-NEXT: i8 -1, label [[LOOP_2_LATCH:%.*]] -; CHECK-NEXT: i8 1, label [[LOOP_2_LATCH]] -; CHECK-NEXT: i8 4, label [[LOOP_2_HEADER]] +; CHECK-NEXT: i8 -1, label [[LOOP_2_LATCH:%.*]] +; CHECK-NEXT: i8 1, label [[LOOP_2_LATCH]] +; CHECK-NEXT: i8 4, label [[LOOP_2_HEADER]] ; CHECK-NEXT: ] ; CHECK: loop.2.latch: ; CHECK-NEXT: [[CMP_TRUNC_LCSSA1:%.*]] = phi i1 [ [[CMP_LCSSA2]], [[LOOP_2_HEADER]] ], [ [[CMP_LCSSA2]], [[LOOP_2_HEADER]] ] @@ -147,7 +147,7 @@ define void @D149435(i16 %arg) { ; CHECK: loop1: ; CHECK-NEXT: [[FR:%.*]] = freeze i16 [[ARG:%.*]] ; CHECK-NEXT: [[ARRAYIDX_IDX:%.*]] = shl i16 [[FR]], 1 -; CHECK-NEXT: [[OR:%.*]] = or i16 [[ARRAYIDX_IDX]], 1 +; CHECK-NEXT: [[OR:%.*]] = or disjoint i16 [[ARRAYIDX_IDX]], 1 ; CHECK-NEXT: br i1 false, label [[LOOP1]], label [[LOOP2_PREHEADER:%.*]] ; CHECK: loop2.preheader: ; CHECK-NEXT: [[FR_LCSSA:%.*]] = phi i16 [ [[FR]], [[LOOP1]] ] @@ -175,7 +175,7 @@ define void @D149435(i16 %arg) { loop1: %fr = freeze i16 %arg %arrayidx.idx = shl i16 %fr, 1 - %or = or i16 %arrayidx.idx, 1 + %or = or disjoint i16 %arrayidx.idx, 1 br i1 false, label %loop1, label %loop2.preheader loop2.preheader: diff --git a/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll b/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll index 355c927b0acc..c35c5bacf68c 100644 --- a/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll +++ b/llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll @@ -299,7 +299,7 @@ define i64 @cloneOr(i32 %limit, ptr %base) nounwind { ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[ADR:%.*]] = getelementptr i64, ptr [[BASE:%.*]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[VAL:%.*]] = load i64, ptr [[ADR]], align 8 -; CHECK-NEXT: [[TMP1:%.*]] = or i64 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 2 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT]], [[TMP0]] ; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]] @@ -319,7 +319,7 @@ loop: %t1 = sext i32 %iv to i64 %adr = getelementptr i64, ptr %base, i64 %t1 %val = load i64, ptr %adr - %t2 = or i32 %iv, 1 + %t2 = or disjoint i32 %iv, 1 %t3 = sext i32 %t2 to i64 %iv.next = add i32 %iv, 2 %cmp = icmp slt i32 %iv.next, %halfLim diff --git a/llvm/test/Transforms/IndVarSimplify/pr58702-invalidate-scev-when-replacing-congruent-phis.ll b/llvm/test/Transforms/IndVarSimplify/pr58702-invalidate-scev-when-replacing-congruent-phis.ll index d3013655ae5d..e7025d75dd99 100644 --- a/llvm/test/Transforms/IndVarSimplify/pr58702-invalidate-scev-when-replacing-congruent-phis.ll +++ b/llvm/test/Transforms/IndVarSimplify/pr58702-invalidate-scev-when-replacing-congruent-phis.ll @@ -5,9 +5,9 @@ define i32 @test(i32 %p_16, i1 %c) { ; CHECK-LABEL: @test( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[P_16:%.*]], 6 -; CHECK-NEXT: [[OR_1:%.*]] = or i32 [[XOR]], [[P_16]] +; CHECK-NEXT: [[OR_1:%.*]] = or disjoint i32 [[XOR]], [[P_16]] ; CHECK-NEXT: [[XOR_1:%.*]] = xor i32 [[OR_1]], 6 -; CHECK-NEXT: [[OR_2:%.*]] = or i32 [[XOR_1]], [[P_16]] +; CHECK-NEXT: [[OR_2:%.*]] = or disjoint i32 [[XOR_1]], [[P_16]] ; CHECK-NEXT: [[XOR_2:%.*]] = xor i32 [[OR_2]], 6 ; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] ; CHECK: outer.header: @@ -22,7 +22,7 @@ define i32 @test(i32 %p_16, i1 %c) { ; CHECK-NEXT: br i1 [[C]], label [[OUTER_LATCH]], label [[INNER_LATCH_3:%.*]] ; CHECK: inner.latch.3: ; CHECK-NEXT: [[XOR_2_LCSSA:%.*]] = phi i32 [ [[XOR_2]], [[INNER_LATCH_2]] ] -; CHECK-NEXT: [[OR_3:%.*]] = or i32 [[XOR_2_LCSSA]], [[P_16]] +; CHECK-NEXT: [[OR_3:%.*]] = or disjoint i32 [[XOR_2_LCSSA]], [[P_16]] ; CHECK-NEXT: [[XOR_3:%.*]] = xor i32 [[OR_3]], 6 ; CHECK-NEXT: ret i32 [[XOR_3]] ; CHECK: outer.latch: @@ -41,7 +41,7 @@ inner.header: br i1 %c, label %outer.latch, label %inner.latch inner.latch: - %or = or i32 %p.2, %p_16 + %or = or disjoint i32 %p.2, %p_16 %xor = xor i32 %or, 6 %add = add nuw nsw i32 %p.3, 1 %cmp = icmp ult i32 %p.3, 3 diff --git a/llvm/test/Transforms/IndVarSimplify/pr64891.ll b/llvm/test/Transforms/IndVarSimplify/pr64891.ll index 69b22bc373a6..465b4605ea9c 100644 --- a/llvm/test/Transforms/IndVarSimplify/pr64891.ll +++ b/llvm/test/Transforms/IndVarSimplify/pr64891.ll @@ -20,7 +20,7 @@ entry: loop: %phi = phi i16 [ 0, %entry ], [ %or, %loop ] - %or = or i16 %phi, %trunc + %or = or disjoint i16 %phi, %trunc %phi.ext = sext i16 %phi to i64 %add.ptr = getelementptr i8, ptr null, i64 %phi.ext br label %loop diff --git a/llvm/test/Transforms/InstCombine/2007-10-31-RangeCrash.ll b/llvm/test/Transforms/InstCombine/2007-10-31-RangeCrash.ll index f2548f6f8c8c..8b472aa5af09 100644 --- a/llvm/test/Transforms/InstCombine/2007-10-31-RangeCrash.ll +++ b/llvm/test/Transforms/InstCombine/2007-10-31-RangeCrash.ll @@ -1,5 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt < %s -S -passes=instcombine | FileCheck %s +; RUN: opt < %s -S -passes='instcombine' | FileCheck %s + +; We do not reach a fixpoint, because we first have to infer nsw on the IV add, +; and could eliminate the icmp slt afterwards, but don't revisit it. target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" @@ -10,7 +13,7 @@ define i32 @test() { ; CHECK: bb.i: ; CHECK-NEXT: br label [[BB51_I_I:%.*]] ; CHECK: bb27.i.i: -; CHECK-NEXT: [[TMP50_I_I:%.*]] = add i32 [[X_0_I_I:%.*]], 2 +; CHECK-NEXT: [[TMP50_I_I:%.*]] = add nsw i32 [[X_0_I_I:%.*]], 2 ; CHECK-NEXT: br label [[BB51_I_I]] ; CHECK: bb51.i.i: ; CHECK-NEXT: [[X_0_I_I]] = phi i32 [ [[TMP50_I_I]], [[BB27_I_I:%.*]] ], [ 0, [[BB_I]] ] diff --git a/llvm/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll b/llvm/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll index 13eca92f5535..9f69d67f61e1 100644 --- a/llvm/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll +++ b/llvm/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll @@ -80,7 +80,7 @@ define ptr @_Z3fooRSt6vectorIiSaIiEE(ptr %X) { ; IC-NEXT: [[TMP31:%.*]] = load ptr, ptr [[__FIRST_ADDR_I_I]], align 4 ; IC-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[TMP31]], i32 1 ; IC-NEXT: store ptr [[TMP32]], ptr [[__FIRST_ADDR_I_I]], align 4 -; IC-NEXT: [[TMP33:%.*]] = add i32 [[__TRIP_COUNT_0_I_I:%.*]], -1 +; IC-NEXT: [[TMP33:%.*]] = add nsw i32 [[__TRIP_COUNT_0_I_I:%.*]], -1 ; IC-NEXT: br label [[BB12_I_I]] ; IC: bb12.i.i: ; IC-NEXT: [[__TRIP_COUNT_0_I_I]] = phi i32 [ [[TMP7]], [[ENTRY:%.*]] ], [ [[TMP33]], [[BB11_I_I]] ] @@ -188,7 +188,7 @@ define ptr @_Z3fooRSt6vectorIiSaIiEE(ptr %X) { ; IC_SROA-NEXT: br label [[_ZST4FINDIN9__GNU_CXX17__NORMAL_ITERATORIPIST6VECTORIISAIIEEEEIET_S7_S7_RKT0__EXIT]] ; IC_SROA: bb11.i.i: ; IC_SROA-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP15]], i32 1 -; IC_SROA-NEXT: [[TMP19:%.*]] = add i32 [[__TRIP_COUNT_0_I_I:%.*]], -1 +; IC_SROA-NEXT: [[TMP19:%.*]] = add nsw i32 [[__TRIP_COUNT_0_I_I:%.*]], -1 ; IC_SROA-NEXT: br label [[BB12_I_I]] ; IC_SROA: bb12.i.i: ; IC_SROA-NEXT: [[__FIRST_ADDR_I_I_SROA_0_0]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[TMP18]], [[BB11_I_I]] ] diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll index db9eafe998eb..6242fc6f528a 100644 --- a/llvm/test/Transforms/InstCombine/add.ll +++ b/llvm/test/Transforms/InstCombine/add.ll @@ -657,8 +657,8 @@ define <2 x i1> @test21vec(<2 x i32> %x) { define i32 @test22(i32 %V) { ; CHECK-LABEL: @test22( ; CHECK-NEXT: switch i32 [[V:%.*]], label [[DEFAULT:%.*]] [ -; CHECK-NEXT: i32 10, label [[LAB1:%.*]] -; CHECK-NEXT: i32 20, label [[LAB2:%.*]] +; CHECK-NEXT: i32 10, label [[LAB1:%.*]] +; CHECK-NEXT: i32 20, label [[LAB2:%.*]] ; CHECK-NEXT: ] ; CHECK: Default: ; CHECK-NEXT: ret i32 123 @@ -1511,7 +1511,17 @@ define i8 @add_like_or_t2_extrause(i8 %x) { ret i8 %r } -define i8 @add_and_xor(i8 %x, i8 %y) { +define i8 @add_like_or_disjoint(i8 %x) { +; CHECK-LABEL: @add_like_or_disjoint( +; CHECK-NEXT: [[R:%.*]] = add i8 [[X:%.*]], 57 +; CHECK-NEXT: ret i8 [[R]] +; + %i1 = or disjoint i8 %x, 15 + %r = add i8 %i1, 42 + ret i8 %r +} + +define i8 @add_and_xor(i8 noundef %x, i8 %y) { ; CHECK-LABEL: @add_and_xor( ; CHECK-NEXT: [[ADD:%.*]] = or i8 [[Y:%.*]], [[X:%.*]] ; CHECK-NEXT: ret i8 [[ADD]] @@ -1548,7 +1558,7 @@ define i8 @add_and_xor_wrong_op(i8 %x, i8 %y, i8 %z) { ret i8 %add } -define i8 @add_and_xor_commuted1(i8 %x, i8 %_y) { +define i8 @add_and_xor_commuted1(i8 noundef %x, i8 %_y) { ; CHECK-LABEL: @add_and_xor_commuted1( ; CHECK-NEXT: [[Y:%.*]] = udiv i8 42, [[_Y:%.*]] ; CHECK-NEXT: [[ADD:%.*]] = or i8 [[Y]], [[X:%.*]] @@ -1561,7 +1571,7 @@ define i8 @add_and_xor_commuted1(i8 %x, i8 %_y) { ret i8 %add } -define i8 @add_and_xor_commuted2(i8 %_x, i8 %y) { +define i8 @add_and_xor_commuted2(i8 noundef %_x, i8 %y) { ; CHECK-LABEL: @add_and_xor_commuted2( ; CHECK-NEXT: [[X:%.*]] = udiv i8 42, [[_X:%.*]] ; CHECK-NEXT: [[ADD:%.*]] = or i8 [[X]], [[Y:%.*]] @@ -1574,7 +1584,7 @@ define i8 @add_and_xor_commuted2(i8 %_x, i8 %y) { ret i8 %add } -define i8 @add_and_xor_commuted3(i8 %_x, i8 %_y) { +define i8 @add_and_xor_commuted3(i8 noundef %_x, i8 %_y) { ; CHECK-LABEL: @add_and_xor_commuted3( ; CHECK-NEXT: [[X:%.*]] = udiv i8 42, [[_X:%.*]] ; CHECK-NEXT: [[Y:%.*]] = udiv i8 42, [[_Y:%.*]] @@ -1589,7 +1599,7 @@ define i8 @add_and_xor_commuted3(i8 %_x, i8 %_y) { ret i8 %add } -define i8 @add_and_xor_extra_use(i8 %x, i8 %y) { +define i8 @add_and_xor_extra_use(i8 noundef %x, i8 %y) { ; CHECK-LABEL: @add_and_xor_extra_use( ; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[X:%.*]], -1 ; CHECK-NEXT: call void @use(i8 [[XOR]]) @@ -1606,7 +1616,7 @@ define i8 @add_and_xor_extra_use(i8 %x, i8 %y) { ret i8 %add } -define i8 @add_xor_and_const(i8 %x) { +define i8 @add_xor_and_const(i8 noundef %x) { ; CHECK-LABEL: @add_xor_and_const( ; CHECK-NEXT: [[ADD:%.*]] = or i8 [[X:%.*]], 42 ; CHECK-NEXT: ret i8 [[ADD]] @@ -1630,7 +1640,7 @@ define i8 @add_xor_and_const_wrong_const(i8 %x) { ret i8 %add } -define i8 @add_xor_and_var(i8 %x, i8 %y) { +define i8 @add_xor_and_var(i8 noundef %x, i8 noundef %y) { ; CHECK-LABEL: @add_xor_and_var( ; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: call void @use(i8 [[AND]]) @@ -1674,7 +1684,7 @@ define i8 @add_xor_and_var_wrong_op2(i8 %x, i8 %y, i8 %z) { ret i8 %add } -define i8 @add_xor_and_var_commuted1(i8 %x, i8 %y) { +define i8 @add_xor_and_var_commuted1(i8 noundef %x, i8 noundef %y) { ; CHECK-LABEL: @add_xor_and_var_commuted1( ; CHECK-NEXT: [[AND:%.*]] = and i8 [[Y:%.*]], [[X:%.*]] ; CHECK-NEXT: call void @use(i8 [[AND]]) @@ -1688,7 +1698,7 @@ define i8 @add_xor_and_var_commuted1(i8 %x, i8 %y) { ret i8 %add } -define i8 @add_xor_and_var_commuted2(i8 %_x, i8 %_y) { +define i8 @add_xor_and_var_commuted2(i8 noundef %_x, i8 noundef %_y) { ; CHECK-LABEL: @add_xor_and_var_commuted2( ; CHECK-NEXT: [[X:%.*]] = udiv i8 42, [[_X:%.*]] ; CHECK-NEXT: [[Y:%.*]] = udiv i8 42, [[_Y:%.*]] @@ -1706,7 +1716,7 @@ define i8 @add_xor_and_var_commuted2(i8 %_x, i8 %_y) { ret i8 %add } -define i8 @add_xor_and_var_commuted3(i8 %x, i8 %_y) { +define i8 @add_xor_and_var_commuted3(i8 noundef %x, i8 noundef %_y) { ; CHECK-LABEL: @add_xor_and_var_commuted3( ; CHECK-NEXT: [[Y:%.*]] = udiv i8 42, [[_Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i8 [[Y]], [[X:%.*]] @@ -1722,7 +1732,7 @@ define i8 @add_xor_and_var_commuted3(i8 %x, i8 %_y) { ret i8 %add } -define i8 @add_xor_and_var_commuted4(i8 %_x, i8 %y) { +define i8 @add_xor_and_var_commuted4(i8 noundef %_x, i8 noundef %y) { ; CHECK-LABEL: @add_xor_and_var_commuted4( ; CHECK-NEXT: [[X:%.*]] = udiv i8 42, [[_X:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i8 [[X]], [[Y:%.*]] @@ -1738,7 +1748,7 @@ define i8 @add_xor_and_var_commuted4(i8 %_x, i8 %y) { ret i8 %add } -define i8 @add_xor_and_var_commuted5(i8 %_x, i8 %_y) { +define i8 @add_xor_and_var_commuted5(i8 noundef %_x, i8 noundef %_y) { ; CHECK-LABEL: @add_xor_and_var_commuted5( ; CHECK-NEXT: [[X:%.*]] = udiv i8 42, [[_X:%.*]] ; CHECK-NEXT: [[Y:%.*]] = udiv i8 42, [[_Y:%.*]] @@ -1756,7 +1766,7 @@ define i8 @add_xor_and_var_commuted5(i8 %_x, i8 %_y) { ret i8 %add } -define i8 @add_xor_and_var_commuted6(i8 %_x, i8 %_y) { +define i8 @add_xor_and_var_commuted6(i8 noundef %_x, i8 noundef %_y) { ; CHECK-LABEL: @add_xor_and_var_commuted6( ; CHECK-NEXT: [[X:%.*]] = udiv i8 42, [[_X:%.*]] ; CHECK-NEXT: [[Y:%.*]] = udiv i8 42, [[_Y:%.*]] @@ -1774,7 +1784,7 @@ define i8 @add_xor_and_var_commuted6(i8 %_x, i8 %_y) { ret i8 %add } -define i8 @add_xor_and_var_commuted7(i8 %_x, i8 %_y) { +define i8 @add_xor_and_var_commuted7(i8 noundef %_x, i8 noundef %_y) { ; CHECK-LABEL: @add_xor_and_var_commuted7( ; CHECK-NEXT: [[X:%.*]] = udiv i8 42, [[_X:%.*]] ; CHECK-NEXT: [[Y:%.*]] = udiv i8 42, [[_Y:%.*]] @@ -1792,7 +1802,7 @@ define i8 @add_xor_and_var_commuted7(i8 %_x, i8 %_y) { ret i8 %add } -define i8 @add_xor_and_var_extra_use(i8 %x, i8 %y) { +define i8 @add_xor_and_var_extra_use(i8 noundef %x, i8 noundef %y) { ; CHECK-LABEL: @add_xor_and_var_extra_use( ; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: call void @use(i8 [[AND]]) @@ -2573,7 +2583,7 @@ define @add_to_or_scalable( %in) { ret %add } -define i5 @zext_zext_not(i3 %x) { +define i5 @zext_zext_not(i3 noundef %x) { ; CHECK-LABEL: @zext_zext_not( ; CHECK-NEXT: ret i5 7 ; @@ -2584,7 +2594,7 @@ define i5 @zext_zext_not(i3 %x) { ret i5 %r } -define <2 x i5> @zext_zext_not_commute(<2 x i3> %x) { +define <2 x i5> @zext_zext_not_commute(<2 x i3> noundef %x) { ; CHECK-LABEL: @zext_zext_not_commute( ; CHECK-NEXT: ret <2 x i5> ; @@ -2595,7 +2605,7 @@ define <2 x i5> @zext_zext_not_commute(<2 x i3> %x) { ret <2 x i5> %r } -define i9 @sext_sext_not(i3 %x) { +define i9 @sext_sext_not(i3 noundef %x) { ; CHECK-LABEL: @sext_sext_not( ; CHECK-NEXT: ret i9 -1 ; @@ -2606,7 +2616,7 @@ define i9 @sext_sext_not(i3 %x) { ret i9 %r } -define i8 @sext_sext_not_commute(i3 %x) { +define i8 @sext_sext_not_commute(i3 noundef %x) { ; CHECK-LABEL: @sext_sext_not_commute( ; CHECK-NEXT: [[SX:%.*]] = sext i3 [[X:%.*]] to i8 ; CHECK-NEXT: call void @use(i8 [[SX]]) @@ -2621,7 +2631,7 @@ define i8 @sext_sext_not_commute(i3 %x) { ret i8 %r } -define i5 @zext_sext_not(i4 %x) { +define i5 @zext_sext_not(i4 noundef %x) { ; CHECK-LABEL: @zext_sext_not( ; CHECK-NEXT: [[ZX:%.*]] = zext i4 [[X:%.*]] to i5 ; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1 @@ -2636,7 +2646,7 @@ define i5 @zext_sext_not(i4 %x) { ret i5 %r } -define i8 @zext_sext_not_commute(i4 %x) { +define i8 @zext_sext_not_commute(i4 noundef %x) { ; CHECK-LABEL: @zext_sext_not_commute( ; CHECK-NEXT: [[ZX:%.*]] = zext i4 [[X:%.*]] to i8 ; CHECK-NEXT: call void @use(i8 [[ZX]]) @@ -2655,7 +2665,7 @@ define i8 @zext_sext_not_commute(i4 %x) { ret i8 %r } -define i9 @sext_zext_not(i4 %x) { +define i9 @sext_zext_not(i4 noundef %x) { ; CHECK-LABEL: @sext_zext_not( ; CHECK-NEXT: [[SX:%.*]] = sext i4 [[X:%.*]] to i9 ; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1 @@ -2670,7 +2680,7 @@ define i9 @sext_zext_not(i4 %x) { ret i9 %r } -define i9 @sext_zext_not_commute(i4 %x) { +define i9 @sext_zext_not_commute(i4 noundef %x) { ; CHECK-LABEL: @sext_zext_not_commute( ; CHECK-NEXT: [[SX:%.*]] = sext i4 [[X:%.*]] to i9 ; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1 diff --git a/llvm/test/Transforms/InstCombine/and-or-not.ll b/llvm/test/Transforms/InstCombine/and-or-not.ll index c896c8f10038..ca093eba1b56 100644 --- a/llvm/test/Transforms/InstCombine/and-or-not.ll +++ b/llvm/test/Transforms/InstCombine/and-or-not.ll @@ -548,7 +548,7 @@ define i32 @and_to_nxor_multiuse(float %fa, float %fb) { ; (a & b) | ~(a | b) --> ~(a ^ b) ; TODO: this increases instruction count if the pieces have additional users -define i32 @or_to_nxor_multiuse(i32 %a, i32 %b) { +define i32 @or_to_nxor_multiuse(i32 noundef %a, i32 noundef %b) { ; CHECK-LABEL: @or_to_nxor_multiuse( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[OR:%.*]] = or i32 [[A]], [[B]] diff --git a/llvm/test/Transforms/InstCombine/cast_phi.ll b/llvm/test/Transforms/InstCombine/cast_phi.ll index feeee16e27f2..5b4425b4d830 100644 --- a/llvm/test/Transforms/InstCombine/cast_phi.ll +++ b/llvm/test/Transforms/InstCombine/cast_phi.ll @@ -319,7 +319,7 @@ define i8 @trunc_in_loop_exit_block() { ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IV]], 100 ; CHECK-NEXT: br i1 [[CMP]], label [[LOOP_LATCH]], label [[EXIT:%.*]] ; CHECK: loop.latch: -; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 +; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1 ; CHECK-NEXT: br label [[LOOP]] ; CHECK: exit: ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[PHI]] to i8 diff --git a/llvm/test/Transforms/InstCombine/icmp-binop.ll b/llvm/test/Transforms/InstCombine/icmp-binop.ll index 60a12411ee91..878f39bb7c9a 100644 --- a/llvm/test/Transforms/InstCombine/icmp-binop.ll +++ b/llvm/test/Transforms/InstCombine/icmp-binop.ll @@ -132,8 +132,7 @@ define i1 @mul_broddV_unkV_eq(i16 %v, i16 %v2) { ; CHECK-NEXT: [[ODD_NOT:%.*]] = icmp eq i16 [[LB]], 0 ; CHECK-NEXT: br i1 [[ODD_NOT]], label [[FALSE:%.*]], label [[TRUE:%.*]] ; CHECK: true: -; CHECK-NEXT: [[MUL:%.*]] = mul i16 [[V:%.*]], [[V2]] -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[MUL]], 0 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[V:%.*]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; CHECK: false: ; CHECK-NEXT: call void @use64(i16 [[V]]) diff --git a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll index 095ac5b27f59..adf78723b130 100644 --- a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll +++ b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll @@ -17,8 +17,7 @@ define i32 @sterix(i32, i8, i64) { ; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]] ; CHECK: lor.rhs: ; CHECK-NEXT: [[AND:%.*]] = and i64 [[MUL3]], [[TMP2]] -; CHECK-NEXT: [[CONV4:%.*]] = trunc i64 [[AND]] to i32 -; CHECK-NEXT: [[TOBOOL7_NOT:%.*]] = icmp eq i32 [[CONV4]], 0 +; CHECK-NEXT: [[TOBOOL7_NOT:%.*]] = icmp eq i64 [[AND]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TOBOOL7_NOT]] to i32 ; CHECK-NEXT: br label [[LOR_END]] ; CHECK: lor.end: diff --git a/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll b/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll index 224ea3cd76cc..70a2b33d17dd 100644 --- a/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll +++ b/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll @@ -125,8 +125,7 @@ define i32 @pow2_32_br(i32 %x) { ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0 ; CHECK-NEXT: br i1 [[CMP_NOT]], label [[FALSE:%.*]], label [[TRUE:%.*]] ; CHECK: True: -; CHECK-NEXT: [[OR:%.*]] = or i32 [[X]], 4 -; CHECK-NEXT: ret i32 [[OR]] +; CHECK-NEXT: ret i32 [[X]] ; CHECK: False: ; CHECK-NEXT: ret i32 0 ; @@ -167,8 +166,7 @@ define i64 @pow2_64_br(i64 %x) { ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[AND]], 0 ; CHECK-NEXT: br i1 [[CMP_NOT]], label [[FALSE:%.*]], label [[TRUE:%.*]] ; CHECK: True: -; CHECK-NEXT: [[AND2:%.*]] = and i64 [[X]], 1 -; CHECK-NEXT: ret i64 [[AND2]] +; CHECK-NEXT: ret i64 1 ; CHECK: False: ; CHECK-NEXT: ret i64 0 ; @@ -209,8 +207,7 @@ define i16 @pow2_16_br(i16 %x) { ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i16 [[AND]], 0 ; CHECK-NEXT: br i1 [[CMP_NOT]], label [[FALSE:%.*]], label [[TRUE:%.*]] ; CHECK: True: -; CHECK-NEXT: [[OR:%.*]] = or i16 [[X]], 16384 -; CHECK-NEXT: ret i16 [[OR]] +; CHECK-NEXT: ret i16 [[X]] ; CHECK: False: ; CHECK-NEXT: ret i16 0 ; @@ -250,8 +247,7 @@ define i8 @pow2_8_br(i8 %x) { ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp sgt i8 [[X:%.*]], -1 ; CHECK-NEXT: br i1 [[CMP_NOT]], label [[FALSE:%.*]], label [[TRUE:%.*]] ; CHECK: True: -; CHECK-NEXT: [[AND2:%.*]] = and i8 [[X]], -128 -; CHECK-NEXT: ret i8 [[AND2]] +; CHECK-NEXT: ret i8 -128 ; CHECK: False: ; CHECK-NEXT: ret i8 0 ; diff --git a/llvm/test/Transforms/InstCombine/icmp-of-or-x.ll b/llvm/test/Transforms/InstCombine/icmp-of-or-x.ll index 4b8df439b846..26f53cb4807e 100644 --- a/llvm/test/Transforms/InstCombine/icmp-of-or-x.ll +++ b/llvm/test/Transforms/InstCombine/icmp-of-or-x.ll @@ -207,10 +207,8 @@ define i1 @or_sle_intmin_indirect_2(i8 %xx, i8 %C, i8 %z) { ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[C:%.*]], -128 ; CHECK-NEXT: br i1 [[CMP]], label [[NEG:%.*]], label [[POS:%.*]] ; CHECK: neg: -; CHECK-NEXT: [[NC:%.*]] = sub i8 0, [[C]] -; CHECK-NEXT: [[CP2:%.*]] = and i8 [[NC]], [[C]] ; CHECK-NEXT: [[X:%.*]] = add i8 [[XX:%.*]], [[Z:%.*]] -; CHECK-NEXT: [[XN1:%.*]] = or i8 [[X]], [[CP2]] +; CHECK-NEXT: [[XN1:%.*]] = or i8 [[X]], -128 ; CHECK-NEXT: [[R:%.*]] = icmp sle i8 [[X]], [[XN1]] ; CHECK-NEXT: ret i1 [[R]] ; CHECK: pos: @@ -247,9 +245,7 @@ define i1 @or_sgt_intmin_indirect(i8 %x, i8 %C) { ; CHECK-NEXT: [[C_NOT:%.*]] = icmp eq i8 [[C:%.*]], -128 ; CHECK-NEXT: br i1 [[C_NOT]], label [[NEG:%.*]], label [[POS:%.*]] ; CHECK: neg: -; CHECK-NEXT: [[NC:%.*]] = sub i8 0, [[C]] -; CHECK-NEXT: [[CP2:%.*]] = and i8 [[NC]], [[C]] -; CHECK-NEXT: [[XN1:%.*]] = or i8 [[CP2]], [[X:%.*]] +; CHECK-NEXT: [[XN1:%.*]] = or i8 [[X:%.*]], -128 ; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[XN1]], [[X]] ; CHECK-NEXT: ret i1 [[R]] ; CHECK: pos: diff --git a/llvm/test/Transforms/InstCombine/idioms.ll b/llvm/test/Transforms/InstCombine/idioms.ll index 7eef4386f781..fbc8b8fe1e18 100644 --- a/llvm/test/Transforms/InstCombine/idioms.ll +++ b/llvm/test/Transforms/InstCombine/idioms.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt -passes=instcombine -S < %s | FileCheck %s +; RUN: opt -passes=instcombine,simplifycfg,instcombine -S < %s | FileCheck %s --check-prefix=EXTRA-PASSES ; Check that code corresponding to the following C function is ; simplified into a single ASR operation: @@ -16,13 +17,21 @@ define i32 @test_asr(i32 %a, i32 %b) { ; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[A]], 0 ; CHECK-NEXT: br i1 [[C]], label [[BB2:%.*]], label [[BB3:%.*]] ; CHECK: bb2: +; CHECK-NEXT: [[NOT2:%.*]] = ashr i32 [[A]], [[B]] ; CHECK-NEXT: br label [[BB4:%.*]] ; CHECK: bb3: +; CHECK-NEXT: [[E:%.*]] = lshr i32 [[A]], [[B]] ; CHECK-NEXT: br label [[BB4]] ; CHECK: bb4: -; CHECK-NEXT: [[F:%.*]] = ashr i32 [[A]], [[B]] +; CHECK-NEXT: [[F:%.*]] = phi i32 [ [[NOT2]], [[BB2]] ], [ [[E]], [[BB3]] ] ; CHECK-NEXT: ret i32 [[F]] ; +; EXTRA-PASSES-LABEL: define i32 @test_asr( +; EXTRA-PASSES-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; EXTRA-PASSES-NEXT: entry: +; EXTRA-PASSES-NEXT: [[C1:%.*]] = ashr i32 [[A]], [[B]] +; EXTRA-PASSES-NEXT: ret i32 [[C1]] +; entry: %c = icmp slt i32 %a, 0 br i1 %c, label %bb2, label %bb3 diff --git a/llvm/test/Transforms/InstCombine/known-non-zero.ll b/llvm/test/Transforms/InstCombine/known-non-zero.ll index b5755700e2a4..7965b47911c4 100644 --- a/llvm/test/Transforms/InstCombine/known-non-zero.ll +++ b/llvm/test/Transforms/InstCombine/known-non-zero.ll @@ -140,7 +140,7 @@ define i64 @test_sgt_zero(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp sgt i64 [[X:%.*]], 0 ; CHECK-NEXT: br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG1:![0-9]+]] ; CHECK-NEXT: ret i64 [[CTZ]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 @@ -163,8 +163,7 @@ define i64 @test_slt_neg_ten(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[X:%.*]], -10 ; CHECK-NEXT: br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]] -; CHECK-NEXT: ret i64 [[CTZ]] +; CHECK-NEXT: ret i64 0 ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 ; @@ -232,7 +231,7 @@ define i64 @test_sle_zero(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[X:%.*]], 1 ; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG1]] ; CHECK-NEXT: ret i64 [[CTZ]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 @@ -255,8 +254,7 @@ define i64 @test_sge_neg_ten(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp sgt i64 [[X:%.*]], -11 ; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]] -; CHECK-NEXT: ret i64 [[CTZ]] +; CHECK-NEXT: ret i64 0 ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 ; diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll index 31848bc91189..c3eec5eebf2e 100644 --- a/llvm/test/Transforms/InstCombine/logical-select.ll +++ b/llvm/test/Transforms/InstCombine/logical-select.ll @@ -762,7 +762,7 @@ define @bitcast_vec_cond_scalable( %cond, < ; Negative test - bitcast of condition from wide source element type cannot be converted to select. -define <8 x i3> @bitcast_vec_cond_commute1(<3 x i1> %cond, <8 x i3> %pc, <8 x i3> %d) { +define <8 x i3> @bitcast_vec_cond_commute1(<3 x i1> noundef %cond, <8 x i3> %pc, <8 x i3> %d) { ; CHECK-LABEL: @bitcast_vec_cond_commute1( ; CHECK-NEXT: [[C:%.*]] = mul <8 x i3> [[PC:%.*]], [[PC]] ; CHECK-NEXT: [[S:%.*]] = sext <3 x i1> [[COND:%.*]] to <3 x i8> @@ -830,7 +830,7 @@ define <2 x i16> @bitcast_vec_cond_commute3(<4 x i8> %cond, <2 x i16> %pc, <2 x ; Don't crash on invalid type for compute signbits. -define <2 x i64> @bitcast_fp_vec_cond(<2 x double> %s, <2 x i64> %c, <2 x i64> %d) { +define <2 x i64> @bitcast_fp_vec_cond(<2 x double> noundef %s, <2 x i64> %c, <2 x i64> %d) { ; CHECK-LABEL: @bitcast_fp_vec_cond( ; CHECK-NEXT: [[T9:%.*]] = bitcast <2 x double> [[S:%.*]] to <2 x i64> ; CHECK-NEXT: [[NOTT9:%.*]] = xor <2 x i64> [[T9]], @@ -849,7 +849,7 @@ define <2 x i64> @bitcast_fp_vec_cond(<2 x double> %s, <2 x i64> %c, <2 x i64> % ; Wider source type would be ok except poison could leak across elements. -define <2 x i64> @bitcast_int_vec_cond(i1 %b, <2 x i64> %c, <2 x i64> %d) { +define <2 x i64> @bitcast_int_vec_cond(i1 noundef %b, <2 x i64> %c, <2 x i64> %d) { ; CHECK-LABEL: @bitcast_int_vec_cond( ; CHECK-NEXT: [[S:%.*]] = sext i1 [[B:%.*]] to i128 ; CHECK-NEXT: [[T9:%.*]] = bitcast i128 [[S]] to <2 x i64> diff --git a/llvm/test/Transforms/InstCombine/masked-merge-add.ll b/llvm/test/Transforms/InstCombine/masked-merge-add.ll index c4265eb896b2..f655153108a4 100644 --- a/llvm/test/Transforms/InstCombine/masked-merge-add.ll +++ b/llvm/test/Transforms/InstCombine/masked-merge-add.ll @@ -16,7 +16,7 @@ ; Most basic positive tests ; ============================================================================ ; -define i32 @p(i32 %x, i32 %y, i32 %m) { +define i32 @p(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -31,7 +31,7 @@ define i32 @p(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %m) { +define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> noundef %m) { ; CHECK-LABEL: @p_splatvec( ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor <2 x i32> [[M]], @@ -46,7 +46,7 @@ define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %m) { ret <2 x i32> %ret } -define <3 x i32> @p_vec_undef(<3 x i32> %x, <3 x i32> %y, <3 x i32> %m) { +define <3 x i32> @p_vec_undef(<3 x i32> %x, <3 x i32> %y, <3 x i32> noundef %m) { ; CHECK-LABEL: @p_vec_undef( ; CHECK-NEXT: [[AND:%.*]] = and <3 x i32> [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor <3 x i32> [[M]], @@ -180,7 +180,7 @@ define <3 x i32> @p_constmask2_vec_undef(<3 x i32> %x, <3 x i32> %y) { ; Used to make sure that the IR complexity sorting does not interfere. declare i32 @gen32() -define i32 @p_commutative0(i32 %x, i32 %y, i32 %m) { +define i32 @p_commutative0(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p_commutative0( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -195,7 +195,7 @@ define i32 @p_commutative0(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define i32 @p_commutative1(i32 %x, i32 %m) { +define i32 @p_commutative1(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative1( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] @@ -212,7 +212,7 @@ define i32 @p_commutative1(i32 %x, i32 %m) { ret i32 %ret } -define i32 @p_commutative2(i32 %x, i32 %y, i32 %m) { +define i32 @p_commutative2(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p_commutative2( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -227,7 +227,7 @@ define i32 @p_commutative2(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define i32 @p_commutative3(i32 %x, i32 %m) { +define i32 @p_commutative3(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative3( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] @@ -244,7 +244,7 @@ define i32 @p_commutative3(i32 %x, i32 %m) { ret i32 %ret } -define i32 @p_commutative4(i32 %x, i32 %y, i32 %m) { +define i32 @p_commutative4(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p_commutative4( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -259,7 +259,7 @@ define i32 @p_commutative4(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define i32 @p_commutative5(i32 %x, i32 %m) { +define i32 @p_commutative5(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative5( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] @@ -276,7 +276,7 @@ define i32 @p_commutative5(i32 %x, i32 %m) { ret i32 %ret } -define i32 @p_commutative6(i32 %x, i32 %m) { +define i32 @p_commutative6(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative6( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] @@ -314,7 +314,7 @@ define i32 @p_constmask_commutative(i32 %x, i32 %y) { declare void @use32(i32) -define i32 @n0_oneuse(i32 %x, i32 %y, i32 %m) { +define i32 @n0_oneuse(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @n0_oneuse( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 diff --git a/llvm/test/Transforms/InstCombine/masked-merge-or.ll b/llvm/test/Transforms/InstCombine/masked-merge-or.ll index 7d67b2d49541..b49ec07706e2 100644 --- a/llvm/test/Transforms/InstCombine/masked-merge-or.ll +++ b/llvm/test/Transforms/InstCombine/masked-merge-or.ll @@ -16,7 +16,7 @@ ; Most basic positive tests ; ============================================================================ ; -define i32 @p(i32 %x, i32 %y, i32 %m) { +define i32 @p(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -31,7 +31,7 @@ define i32 @p(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %m) { +define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> noundef %m) { ; CHECK-LABEL: @p_splatvec( ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor <2 x i32> [[M]], @@ -46,7 +46,7 @@ define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %m) { ret <2 x i32> %ret } -define <3 x i32> @p_vec_undef(<3 x i32> %x, <3 x i32> %y, <3 x i32> %m) { +define <3 x i32> @p_vec_undef(<3 x i32> %x, <3 x i32> %y, <3 x i32> noundef %m) { ; CHECK-LABEL: @p_vec_undef( ; CHECK-NEXT: [[AND:%.*]] = and <3 x i32> [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor <3 x i32> [[M]], @@ -180,7 +180,7 @@ define <3 x i32> @p_constmask2_vec_undef(<3 x i32> %x, <3 x i32> %y) { ; Used to make sure that the IR complexity sorting does not interfere. declare i32 @gen32() -define i32 @p_commutative0(i32 %x, i32 %y, i32 %m) { +define i32 @p_commutative0(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p_commutative0( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -195,7 +195,7 @@ define i32 @p_commutative0(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define i32 @p_commutative1(i32 %x, i32 %m) { +define i32 @p_commutative1(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative1( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] @@ -212,7 +212,7 @@ define i32 @p_commutative1(i32 %x, i32 %m) { ret i32 %ret } -define i32 @p_commutative2(i32 %x, i32 %y, i32 %m) { +define i32 @p_commutative2(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p_commutative2( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -227,7 +227,7 @@ define i32 @p_commutative2(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define i32 @p_commutative3(i32 %x, i32 %m) { +define i32 @p_commutative3(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative3( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] @@ -244,7 +244,7 @@ define i32 @p_commutative3(i32 %x, i32 %m) { ret i32 %ret } -define i32 @p_commutative4(i32 %x, i32 %y, i32 %m) { +define i32 @p_commutative4(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p_commutative4( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -259,7 +259,7 @@ define i32 @p_commutative4(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define i32 @p_commutative5(i32 %x, i32 %m) { +define i32 @p_commutative5(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative5( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] @@ -276,7 +276,7 @@ define i32 @p_commutative5(i32 %x, i32 %m) { ret i32 %ret } -define i32 @p_commutative6(i32 %x, i32 %m) { +define i32 @p_commutative6(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative6( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] @@ -314,7 +314,7 @@ define i32 @p_constmask_commutative(i32 %x, i32 %y) { declare void @use32(i32) -define i32 @n0_oneuse(i32 %x, i32 %y, i32 %m) { +define i32 @n0_oneuse(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @n0_oneuse( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 diff --git a/llvm/test/Transforms/InstCombine/masked-merge-xor.ll b/llvm/test/Transforms/InstCombine/masked-merge-xor.ll index 4f0845c8c8f4..a6d201be68ce 100644 --- a/llvm/test/Transforms/InstCombine/masked-merge-xor.ll +++ b/llvm/test/Transforms/InstCombine/masked-merge-xor.ll @@ -16,7 +16,7 @@ ; Most basic positive tests ; ============================================================================ ; -define i32 @p(i32 %x, i32 %y, i32 %m) { +define i32 @p(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -31,7 +31,7 @@ define i32 @p(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %m) { +define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> noundef %m) { ; CHECK-LABEL: @p_splatvec( ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor <2 x i32> [[M]], @@ -46,7 +46,7 @@ define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %m) { ret <2 x i32> %ret } -define <3 x i32> @p_vec_undef(<3 x i32> %x, <3 x i32> %y, <3 x i32> %m) { +define <3 x i32> @p_vec_undef(<3 x i32> %x, <3 x i32> %y, <3 x i32> noundef %m) { ; CHECK-LABEL: @p_vec_undef( ; CHECK-NEXT: [[AND:%.*]] = and <3 x i32> [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor <3 x i32> [[M]], @@ -180,7 +180,7 @@ define <3 x i32> @p_constmask2_vec_undef(<3 x i32> %x, <3 x i32> %y) { ; Used to make sure that the IR complexity sorting does not interfere. declare i32 @gen32() -define i32 @p_commutative0(i32 %x, i32 %y, i32 %m) { +define i32 @p_commutative0(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p_commutative0( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -195,7 +195,7 @@ define i32 @p_commutative0(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define i32 @p_commutative1(i32 %x, i32 %m) { +define i32 @p_commutative1(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative1( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] @@ -212,7 +212,7 @@ define i32 @p_commutative1(i32 %x, i32 %m) { ret i32 %ret } -define i32 @p_commutative2(i32 %x, i32 %y, i32 %m) { +define i32 @p_commutative2(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p_commutative2( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -227,7 +227,7 @@ define i32 @p_commutative2(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define i32 @p_commutative3(i32 %x, i32 %m) { +define i32 @p_commutative3(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative3( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] @@ -244,7 +244,7 @@ define i32 @p_commutative3(i32 %x, i32 %m) { ret i32 %ret } -define i32 @p_commutative4(i32 %x, i32 %y, i32 %m) { +define i32 @p_commutative4(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @p_commutative4( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 @@ -259,7 +259,7 @@ define i32 @p_commutative4(i32 %x, i32 %y, i32 %m) { ret i32 %ret } -define i32 @p_commutative5(i32 %x, i32 %m) { +define i32 @p_commutative5(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative5( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] @@ -276,7 +276,7 @@ define i32 @p_commutative5(i32 %x, i32 %m) { ret i32 %ret } -define i32 @p_commutative6(i32 %x, i32 %m) { +define i32 @p_commutative6(i32 %x, i32 noundef %m) { ; CHECK-LABEL: @p_commutative6( ; CHECK-NEXT: [[Y:%.*]] = call i32 @gen32() ; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]] @@ -314,7 +314,7 @@ define i32 @p_constmask_commutative(i32 %x, i32 %y) { declare void @use32(i32) -define i32 @n0_oneuse(i32 %x, i32 %y, i32 %m) { +define i32 @n0_oneuse(i32 %x, i32 %y, i32 noundef %m) { ; CHECK-LABEL: @n0_oneuse( ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]] ; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1 diff --git a/llvm/test/Transforms/InstCombine/minmax-of-xor-x.ll b/llvm/test/Transforms/InstCombine/minmax-of-xor-x.ll index daf58a3b5200..b8430da451f9 100644 --- a/llvm/test/Transforms/InstCombine/minmax-of-xor-x.ll +++ b/llvm/test/Transforms/InstCombine/minmax-of-xor-x.ll @@ -137,10 +137,7 @@ define i8 @smax_xor_pow2_neg(i8 %x, i8 %y) { ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[Y:%.*]], -128 ; CHECK-NEXT: br i1 [[CMP]], label [[NEG:%.*]], label [[POS:%.*]] ; CHECK: neg: -; CHECK-NEXT: [[NY:%.*]] = sub i8 0, [[Y]] -; CHECK-NEXT: [[YP2:%.*]] = and i8 [[NY]], [[Y]] -; CHECK-NEXT: [[X_XOR:%.*]] = xor i8 [[YP2]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.smax.i8(i8 [[X]], i8 [[X_XOR]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[X:%.*]], 127 ; CHECK-NEXT: ret i8 [[R]] ; CHECK: pos: ; CHECK-NEXT: call void @barrier() diff --git a/llvm/test/Transforms/InstCombine/mul.ll b/llvm/test/Transforms/InstCombine/mul.ll index 42698b5102bc..9fe8462c5d31 100644 --- a/llvm/test/Transforms/InstCombine/mul.ll +++ b/llvm/test/Transforms/InstCombine/mul.ll @@ -964,6 +964,28 @@ define i32 @PR57278_mul_assume(i32 %a) { declare void @llvm.assume(i1) +define i32 @PR57278_or_disjoint_nuw(i32 %a) { +; CHECK-LABEL: @PR57278_or_disjoint_nuw( +; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i32 [[A:%.*]], 3 +; CHECK-NEXT: [[MUL:%.*]] = add nuw i32 [[TMP1]], 9 +; CHECK-NEXT: ret i32 [[MUL]] +; + %add = or disjoint i32 %a, 3 + %mul = mul nuw i32 %add, 3 + ret i32 %mul +} + +define i32 @PR57278_or_disjoint_nsw(i32 %a) { +; CHECK-LABEL: @PR57278_or_disjoint_nsw( +; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[A:%.*]], 3 +; CHECK-NEXT: [[MUL:%.*]] = add i32 [[TMP1]], 9 +; CHECK-NEXT: ret i32 [[MUL]] +; + %add = or disjoint i32 %a, 3 + %mul = mul nsw i32 %add, 3 + ret i32 %mul +} + ; https://alive2.llvm.org/ce/z/XYpv9q define <2 x i32> @PR57278_shl_vec(<2 x i32> %v1) { ; CHECK-LABEL: @PR57278_shl_vec( diff --git a/llvm/test/Transforms/InstCombine/pr53357.ll b/llvm/test/Transforms/InstCombine/pr53357.ll index bdb63068fd4a..0a6d2993ce46 100644 --- a/llvm/test/Transforms/InstCombine/pr53357.ll +++ b/llvm/test/Transforms/InstCombine/pr53357.ll @@ -3,7 +3,7 @@ ; RUN: opt < %s -passes=instcombine -S | FileCheck %s ; (x & y) + ~(x | y) -define i32 @src(i32 %0, i32 %1) { +define i32 @src(i32 noundef %0, i32 noundef %1) { ; CHECK-LABEL: @src( ; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1:%.*]], [[TMP0:%.*]] ; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], -1 @@ -17,7 +17,7 @@ define i32 @src(i32 %0, i32 %1) { } ; vector version of src -define <2 x i32> @src_vec(<2 x i32> %0, <2 x i32> %1) { +define <2 x i32> @src_vec(<2 x i32> noundef %0, <2 x i32> noundef %1) { ; CHECK-LABEL: @src_vec( ; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i32> [[TMP1:%.*]], [[TMP0:%.*]] ; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i32> [[TMP3]], @@ -31,7 +31,7 @@ define <2 x i32> @src_vec(<2 x i32> %0, <2 x i32> %1) { } ; vector version of src with undef values -define <2 x i32> @src_vec_undef(<2 x i32> %0, <2 x i32> %1) { +define <2 x i32> @src_vec_undef(<2 x i32> noundef %0, <2 x i32> noundef %1) { ; CHECK-LABEL: @src_vec_undef( ; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i32> [[TMP1:%.*]], [[TMP0:%.*]] ; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i32> [[TMP3]], @@ -45,7 +45,7 @@ define <2 x i32> @src_vec_undef(<2 x i32> %0, <2 x i32> %1) { } ; (x & y) + ~(y | x) -define i32 @src2(i32 %0, i32 %1) { +define i32 @src2(i32 noundef %0, i32 noundef %1) { ; CHECK-LABEL: @src2( ; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1:%.*]], [[TMP0:%.*]] ; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], -1 @@ -59,7 +59,7 @@ define i32 @src2(i32 %0, i32 %1) { } ; (x & y) + (~x & ~y) -define i32 @src3(i32 %0, i32 %1) { +define i32 @src3(i32 noundef %0, i32 noundef %1) { ; CHECK-LABEL: @src3( ; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1:%.*]], [[TMP0:%.*]] ; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], -1 @@ -74,7 +74,7 @@ define i32 @src3(i32 %0, i32 %1) { } ; ~(x | y) + (y & x) -define i32 @src4(i32 %0, i32 %1) { +define i32 @src4(i32 noundef %0, i32 noundef %1) { ; CHECK-LABEL: @src4( ; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP0:%.*]], [[TMP1:%.*]] ; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], -1 @@ -88,7 +88,7 @@ define i32 @src4(i32 %0, i32 %1) { } ; ~(x | y) + (x & y) -define i32 @src5(i32 %0, i32 %1) { +define i32 @src5(i32 noundef %0, i32 noundef %1) { ; CHECK-LABEL: @src5( ; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1:%.*]], [[TMP0:%.*]] ; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], -1 diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll index 54ff690eb85b..6f9ce1544cc0 100644 --- a/llvm/test/Transforms/InstCombine/shift.ll +++ b/llvm/test/Transforms/InstCombine/shift.ll @@ -400,14 +400,12 @@ define <2 x i1> @test28vec(<2 x i8> %x) { define i8 @test28a(i8 %x, i8 %y) { ; CHECK-LABEL: @test28a( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[I1:%.*]] = lshr i8 [[X:%.*]], 7 -; CHECK-NEXT: [[COND1_NOT:%.*]] = icmp sgt i8 [[X]], -1 +; CHECK-NEXT: [[COND1_NOT:%.*]] = icmp sgt i8 [[X:%.*]], -1 ; CHECK-NEXT: br i1 [[COND1_NOT]], label [[BB2:%.*]], label [[BB1:%.*]] ; CHECK: bb1: -; CHECK-NEXT: ret i8 [[I1]] +; CHECK-NEXT: ret i8 1 ; CHECK: bb2: -; CHECK-NEXT: [[I2:%.*]] = add i8 [[I1]], [[Y:%.*]] -; CHECK-NEXT: ret i8 [[I2]] +; CHECK-NEXT: ret i8 [[Y:%.*]] ; entry: ; This shouldn't be transformed. diff --git a/llvm/test/Transforms/InstCombine/sink_instruction.ll b/llvm/test/Transforms/InstCombine/sink_instruction.ll index 37a72b92d2db..c938002788bc 100644 --- a/llvm/test/Transforms/InstCombine/sink_instruction.ll +++ b/llvm/test/Transforms/InstCombine/sink_instruction.ll @@ -1,5 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -passes=instcombine -S < %s | FileCheck %s +; RUN: opt -passes='instcombine' -S < %s | FileCheck %s + +; We fail to reach a fixpoint, because sunk instructions get revisited too +; early. In @test2 the sunk add is revisited before the dominating condition +; is visited and added to the DomConditionCache. ;; This tests that the instructions in the entry blocks are sunk into each ;; arm of the 'if'. diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll index fd2236860add..76a172302999 100644 --- a/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll @@ -865,7 +865,7 @@ define i16 @negation_of_zeroext_of_nonnegative(i8 %x) { ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1 ; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]] ; CHECK: nonneg_bb: -; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16 +; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16 ; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] ; CHECK-NEXT: ret i16 [[T3]] ; CHECK: neg_bb: @@ -889,7 +889,7 @@ define i16 @negation_of_zeroext_of_positive(i8 %x) { ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], 0 ; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]] ; CHECK: nonneg_bb: -; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16 +; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16 ; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] ; CHECK-NEXT: ret i16 [[T3]] ; CHECK: neg_bb: @@ -961,7 +961,7 @@ define i16 @negation_of_signext_of_nonnegative__wrong_cast(i8 %x) { ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1 ; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]] ; CHECK: nonneg_bb: -; CHECK-NEXT: [[T2:%.*]] = sext i8 [[T0]] to i16 +; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16 ; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] ; CHECK-NEXT: ret i16 [[T3]] ; CHECK: neg_bb: diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll index 64cb647ae3f7..66105f4add18 100644 --- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll +++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll @@ -889,7 +889,7 @@ define i16 @negation_of_zeroext_of_nonnegative(i8 %x) { ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1 ; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]] ; CHECK: nonneg_bb: -; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16 +; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16 ; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] ; CHECK-NEXT: ret i16 [[T3]] ; CHECK: neg_bb: @@ -913,7 +913,7 @@ define i16 @negation_of_zeroext_of_positive(i8 %x) { ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], 0 ; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]] ; CHECK: nonneg_bb: -; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16 +; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16 ; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] ; CHECK-NEXT: ret i16 [[T3]] ; CHECK: neg_bb: @@ -985,7 +985,7 @@ define i16 @negation_of_signext_of_nonnegative__wrong_cast(i8 %x) { ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1 ; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]] ; CHECK: nonneg_bb: -; CHECK-NEXT: [[T2:%.*]] = sext i8 [[T0]] to i16 +; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16 ; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] ; CHECK-NEXT: ret i16 [[T3]] ; CHECK: neg_bb: @@ -1068,6 +1068,17 @@ define i8 @negation_of_increment_via_or_common_bits_set(i8 %x, i8 %y) { ret i8 %t2 } +define i8 @negation_of_increment_via_or_disjoint(i8 %x, i8 %y) { +; CHECK-LABEL: @negation_of_increment_via_or_disjoint( +; CHECK-NEXT: [[T1_NEG:%.*]] = xor i8 [[Y:%.*]], -1 +; CHECK-NEXT: [[T2:%.*]] = add i8 [[T1_NEG]], [[X:%.*]] +; CHECK-NEXT: ret i8 [[T2]] +; + %t1 = or disjoint i8 %y, 1 + %t2 = sub i8 %x, %t1 + ret i8 %t2 +} + ; 'or' of operands with no common bits set is 'add' define i8 @add_via_or_with_no_common_bits_set(i8 %x, i8 %y) { ; CHECK-LABEL: @add_via_or_with_no_common_bits_set( diff --git a/llvm/test/Transforms/InstCombine/udiv-simplify.ll b/llvm/test/Transforms/InstCombine/udiv-simplify.ll index cb813e87249e..41a4e642b4e8 100644 --- a/llvm/test/Transforms/InstCombine/udiv-simplify.ll +++ b/llvm/test/Transforms/InstCombine/udiv-simplify.ll @@ -172,11 +172,9 @@ define i32 @div_by_zero_or_one_from_dom_cond(i32 %a, i32 %b) { ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[A:%.*]], 1 ; CHECK-NEXT: br i1 [[CMP]], label [[JOIN:%.*]], label [[ZERO_OR_ONE:%.*]] ; CHECK: zero_or_one: -; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[B:%.*]], [[A]] ; CHECK-NEXT: br label [[JOIN]] ; CHECK: join: -; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[DIV]], [[ZERO_OR_ONE]] ], [ [[B]], [[ENTRY:%.*]] ] -; CHECK-NEXT: ret i32 [[RES]] +; CHECK-NEXT: ret i32 [[B:%.*]] ; entry: %cmp = icmp ugt i32 %a, 1 diff --git a/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll b/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll index 8d5ac063108c..7970f3ce6bf0 100644 --- a/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll +++ b/llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll @@ -17,7 +17,8 @@ define i1 @assume_olt_neg1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -30,7 +31,8 @@ define i1 @assume_olt_neg1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -43,7 +45,8 @@ define i1 @assume_olt_neg1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -56,7 +59,8 @@ define i1 @assume_olt_neg1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -69,7 +73,8 @@ define i1 @assume_olt_neg1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -82,7 +87,8 @@ define i1 @assume_olt_neg1__one_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -95,7 +101,8 @@ define i1 @assume_olt_neg1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -108,7 +115,8 @@ define i1 @assume_olt_neg1__ueq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -121,7 +129,8 @@ define i1 @assume_olt_neg1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -134,7 +143,8 @@ define i1 @assume_olt_neg1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -147,7 +157,8 @@ define i1 @assume_olt_neg1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -160,7 +171,8 @@ define i1 @assume_olt_neg1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -173,7 +185,8 @@ define i1 @assume_olt_neg1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -186,7 +199,8 @@ define i1 @assume_olt_neg1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -203,7 +217,8 @@ define i1 @assume_ole_neg1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -216,7 +231,8 @@ define i1 @assume_ole_neg1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -229,7 +245,8 @@ define i1 @assume_ole_neg1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -242,7 +259,8 @@ define i1 @assume_ole_neg1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -255,7 +273,8 @@ define i1 @assume_ole_neg1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -268,7 +287,8 @@ define i1 @assume_ole_neg1__one_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -281,7 +301,8 @@ define i1 @assume_ole_neg1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -294,7 +315,8 @@ define i1 @assume_ole_neg1__ueq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -307,7 +329,8 @@ define i1 @assume_ole_neg1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -320,7 +343,8 @@ define i1 @assume_ole_neg1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -333,7 +357,8 @@ define i1 @assume_ole_neg1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -346,7 +371,8 @@ define i1 @assume_ole_neg1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -359,7 +385,8 @@ define i1 @assume_ole_neg1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -372,7 +399,8 @@ define i1 @assume_ole_neg1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_NEG1:%.*]] = fcmp ole float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.neg1 = fcmp ole float %arg, -1.0 call void @llvm.assume(i1 %ole.neg1) @@ -473,7 +501,8 @@ define i1 @assume_ogt_neg1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_NEG1:%.*]] = fcmp ogt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.neg1 = fcmp ogt float %arg, -1.0 call void @llvm.assume(i1 %ogt.neg1) @@ -570,7 +599,8 @@ define i1 @assume_ogt_neg1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_NEG1:%.*]] = fcmp ogt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.neg1 = fcmp ogt float %arg, -1.0 call void @llvm.assume(i1 %ogt.neg1) @@ -671,7 +701,8 @@ define i1 @assume_oge_neg1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_NEG1:%.*]] = fcmp oge float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.neg1 = fcmp oge float %arg, -1.0 call void @llvm.assume(i1 %oge.neg1) @@ -768,7 +799,8 @@ define i1 @assume_oge_neg1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_NEG1:%.*]] = fcmp oge float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.neg1 = fcmp oge float %arg, -1.0 call void @llvm.assume(i1 %oge.neg1) @@ -1185,7 +1217,8 @@ define i1 @assume_ule_neg1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1198,7 +1231,8 @@ define i1 @assume_ule_neg1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1211,7 +1245,8 @@ define i1 @assume_ule_neg1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1322,7 +1357,8 @@ define i1 @assume_ule_neg1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1335,7 +1371,8 @@ define i1 @assume_ule_neg1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1348,7 +1385,8 @@ define i1 @assume_ule_neg1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULE_NEG1:%.*]] = fcmp ule float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULE_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ule.neg1 = fcmp ule float %arg, -1.0 call void @llvm.assume(i1 %ule.neg1) @@ -1379,7 +1417,8 @@ define i1 @assume_ult_neg1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1392,7 +1431,8 @@ define i1 @assume_ult_neg1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1405,7 +1445,8 @@ define i1 @assume_ult_neg1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1516,7 +1557,8 @@ define i1 @assume_ult_neg1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1529,7 +1571,8 @@ define i1 @assume_ult_neg1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1542,7 +1585,8 @@ define i1 @assume_ult_neg1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[ULT_NEG1:%.*]] = fcmp ult float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[ULT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ult.neg1 = fcmp ult float %arg, -1.0 call void @llvm.assume(i1 %ult.neg1) @@ -1780,7 +1824,8 @@ define i1 @assume_olt_pos1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_POS1:%.*]] = fcmp olt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.pos1 = fcmp olt float %arg, 1.0 call void @llvm.assume(i1 %olt.pos1) @@ -1877,7 +1922,8 @@ define i1 @assume_olt_pos1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_POS1:%.*]] = fcmp olt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.pos1 = fcmp olt float %arg, 1.0 call void @llvm.assume(i1 %olt.pos1) @@ -1978,7 +2024,8 @@ define i1 @assume_ole_pos1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_POS1:%.*]] = fcmp ole float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.pos1 = fcmp ole float %arg, 1.0 call void @llvm.assume(i1 %ole.pos1) @@ -2075,7 +2122,8 @@ define i1 @assume_ole_pos1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLE_POS1:%.*]] = fcmp ole float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ole.pos1 = fcmp ole float %arg, 1.0 call void @llvm.assume(i1 %ole.pos1) @@ -2092,7 +2140,8 @@ define i1 @assume_ogt_pos1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2105,7 +2154,8 @@ define i1 @assume_ogt_pos1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2118,7 +2168,8 @@ define i1 @assume_ogt_pos1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2131,7 +2182,8 @@ define i1 @assume_ogt_pos1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2144,7 +2196,8 @@ define i1 @assume_ogt_pos1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2157,7 +2210,8 @@ define i1 @assume_ogt_pos1__one_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2170,7 +2224,8 @@ define i1 @assume_ogt_pos1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2183,7 +2238,8 @@ define i1 @assume_ogt_pos1__ueq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2196,7 +2252,8 @@ define i1 @assume_ogt_pos1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2209,7 +2266,8 @@ define i1 @assume_ogt_pos1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2222,7 +2280,8 @@ define i1 @assume_ogt_pos1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2235,7 +2294,8 @@ define i1 @assume_ogt_pos1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2248,7 +2308,8 @@ define i1 @assume_ogt_pos1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2261,7 +2322,8 @@ define i1 @assume_ogt_pos1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGT_POS1:%.*]] = fcmp ogt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ogt.pos1 = fcmp ogt float %arg, 1.0 call void @llvm.assume(i1 %ogt.pos1) @@ -2278,7 +2340,8 @@ define i1 @assume_oge_pos1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2291,7 +2354,8 @@ define i1 @assume_oge_pos1__ogt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2304,7 +2368,8 @@ define i1 @assume_oge_pos1__oge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2317,7 +2382,8 @@ define i1 @assume_oge_pos1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2330,7 +2396,8 @@ define i1 @assume_oge_pos1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2343,7 +2410,8 @@ define i1 @assume_oge_pos1__one_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2356,7 +2424,8 @@ define i1 @assume_oge_pos1__ord_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ord float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2369,7 +2438,8 @@ define i1 @assume_oge_pos1__ueq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2382,7 +2452,8 @@ define i1 @assume_oge_pos1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2395,7 +2466,8 @@ define i1 @assume_oge_pos1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2408,7 +2480,8 @@ define i1 @assume_oge_pos1__ult_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ult float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2421,7 +2494,8 @@ define i1 @assume_oge_pos1__ule_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2434,7 +2508,8 @@ define i1 @assume_oge_pos1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2447,7 +2522,8 @@ define i1 @assume_oge_pos1__uno_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OGE_POS1:%.*]] = fcmp oge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %oge.pos1 = fcmp oge float %arg, 1.0 call void @llvm.assume(i1 %oge.pos1) @@ -2464,7 +2540,8 @@ define i1 @assume_ugt_pos1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2505,7 +2582,8 @@ define i1 @assume_ugt_pos1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2518,7 +2596,8 @@ define i1 @assume_ugt_pos1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2573,7 +2652,8 @@ define i1 @assume_ugt_pos1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2586,7 +2666,8 @@ define i1 @assume_ugt_pos1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2627,7 +2708,8 @@ define i1 @assume_ugt_pos1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGT_POS1:%.*]] = fcmp ugt float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGT_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %ugt.pos1 = fcmp ugt float %arg, 1.0 call void @llvm.assume(i1 %ugt.pos1) @@ -2658,7 +2740,8 @@ define i1 @assume_uge_pos1__oeq_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2699,7 +2782,8 @@ define i1 @assume_uge_pos1__olt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2712,7 +2796,8 @@ define i1 @assume_uge_pos1__ole_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2767,7 +2852,8 @@ define i1 @assume_uge_pos1__ugt_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp ugt float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2780,7 +2866,8 @@ define i1 @assume_uge_pos1__uge_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp uge float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2821,7 +2908,8 @@ define i1 @assume_uge_pos1__une_0(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[UGE_POS1:%.*]] = fcmp uge float [[ARG]], 1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[UGE_POS1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[ARG]], 0.000000e+00 +; CHECK-NEXT: ret i1 [[CMP]] ; %uge.pos1 = fcmp uge float %arg, 1.0 call void @llvm.assume(i1 %uge.pos1) @@ -2852,7 +2940,8 @@ define i1 @assume_olt_neg1__oeq_inf(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[ARG]], 0x7FF0000000000000 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) @@ -2865,7 +2954,8 @@ define i1 @assume_olt_neg1__one_inf(float %arg) { ; CHECK-SAME: float [[ARG:%.*]]) { ; CHECK-NEXT: [[OLT_NEG1:%.*]] = fcmp olt float [[ARG]], -1.000000e+00 ; CHECK-NEXT: call void @llvm.assume(i1 [[OLT_NEG1]]) -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[CMP:%.*]] = fcmp one float [[ARG]], 0x7FF0000000000000 +; CHECK-NEXT: ret i1 [[CMP]] ; %olt.neg1 = fcmp olt float %arg, -1.0 call void @llvm.assume(i1 %olt.neg1) diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll index 067bbdf43922..d78537ca83ed 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll @@ -38,7 +38,7 @@ entry: %cstoreval1 = fptrunc double %storeval1 to float store float %cstoreval1, ptr addrspace(1) %arrayidx, align 4 - %add23 = or i64 %add10, 1 + %add23 = or disjoint i64 %add10, 1 %arrayidx24 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %add23 %load2 = load float, ptr addrspace(1) %arrayidx24, align 4 %conv25 = fpext float %load2 to double diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll index 6df55ffba863..9d686e9837f3 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll @@ -63,7 +63,7 @@ entry: %a.0 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %zext.id.x %c.0 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %zext.id.x - %id.x.1 = or i32 %shl, 1 + %id.x.1 = or disjoint i32 %shl, 1 %id.x.1.ext = zext i32 %id.x.1 to i64 %a.1 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %id.x.1.ext @@ -90,7 +90,7 @@ entry: %a.0 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %zext.id.x %c.0 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %zext.id.x - %id.x.1 = or i32 %shl, 1 + %id.x.1 = or disjoint i32 %shl, 1 %id.x.1.ext = sext i32 %id.x.1 to i64 %a.1 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %id.x.1.ext @@ -127,7 +127,7 @@ loop: %c.0 = getelementptr inbounds i32, ptr addrspace(1) %c, i64 %idx.ext %a.0 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %idx.ext - %idx.1 = or i32 %idx, 1 + %idx.1 = or disjoint i32 %idx, 1 %idx.1.ext = zext i32 %idx.1 to i64 %c.1 = getelementptr inbounds i32, ptr addrspace(1) %c, i64 %idx.1.ext %a.1 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %idx.1.ext diff --git a/llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll b/llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll index f6f3267aba48..ac50c8716c73 100644 --- a/llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll +++ b/llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll @@ -28,7 +28,7 @@ define void @test(ptr %f, i32 %n) nounwind ssp { ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[F]], i32 [[INDVARS_IV]] -; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = or disjoint i32 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[F]], i32 [[TMP5]] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[INDVARS_IV]], 2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[INDVARS_IV_NEXT]], [[TMP0]] @@ -50,7 +50,7 @@ for.body: ; preds = %for.body.preheader, %indvars.iv = phi i32 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32, ptr %f, i32 %indvars.iv store i32 0, ptr %arrayidx, align 4 - %1 = or i32 %indvars.iv, 1 + %1 = or disjoint i32 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds i32, ptr %f, i32 %1 store i32 0, ptr %arrayidx2, align 4 %indvars.iv.next = add nuw nsw i32 %indvars.iv, 2 @@ -86,7 +86,7 @@ define void @test_pattern(ptr %f, i32 %n) nounwind ssp { ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[F]], i32 [[INDVARS_IV]] -; CHECK-NEXT: [[X1:%.*]] = or i32 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[X1:%.*]] = or disjoint i32 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[F]], i32 [[X1]] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[INDVARS_IV]], 2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[INDVARS_IV_NEXT]], [[MUL]] @@ -108,7 +108,7 @@ for.body: ; preds = %for.body.preheader, %indvars.iv = phi i32 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32, ptr %f, i32 %indvars.iv store i32 2, ptr %arrayidx, align 4 - %x1 = or i32 %indvars.iv, 1 + %x1 = or disjoint i32 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds i32, ptr %f, i32 %x1 store i32 2, ptr %arrayidx2, align 4 %indvars.iv.next = add nuw nsw i32 %indvars.iv, 2 diff --git a/llvm/test/Transforms/LoopIdiom/unroll.ll b/llvm/test/Transforms/LoopIdiom/unroll.ll index 8dce77da033f..7c41310abdfd 100644 --- a/llvm/test/Transforms/LoopIdiom/unroll.ll +++ b/llvm/test/Transforms/LoopIdiom/unroll.ll @@ -29,7 +29,7 @@ define void @test(ptr %f, i32 %n) nounwind ssp { ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[F]], i64 [[INDVARS_IV]] -; CHECK-NEXT: [[TMP5:%.*]] = or i64 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = or disjoint i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[F]], i64 [[TMP5]] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT]], [[TMP0]] @@ -52,7 +52,7 @@ for.body: ; preds = %for.body.preheader, %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32, ptr %f, i64 %indvars.iv store i32 0, ptr %arrayidx, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds i32, ptr %f, i64 %1 store i32 0, ptr %arrayidx2, align 4 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 2 @@ -89,7 +89,7 @@ define void @test_pattern(ptr %f, i32 %n) nounwind ssp { ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[F]], i64 [[INDVARS_IV]] -; CHECK-NEXT: [[TMP5:%.*]] = or i64 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = or disjoint i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[F]], i64 [[TMP5]] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT]], [[TMP0]] @@ -112,7 +112,7 @@ for.body: ; preds = %for.body.preheader, %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32, ptr %f, i64 %indvars.iv store i32 2, ptr %arrayidx, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds i32, ptr %f, i64 %1 store i32 2, ptr %arrayidx2, align 4 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 2 diff --git a/llvm/test/Transforms/LoopInterchange/pr57148.ll b/llvm/test/Transforms/LoopInterchange/pr57148.ll index 4bdc41db559e..f2b8a93a780b 100644 --- a/llvm/test/Transforms/LoopInterchange/pr57148.ll +++ b/llvm/test/Transforms/LoopInterchange/pr57148.ll @@ -116,7 +116,7 @@ define void @test2() { ; CHECK-NEXT: [[INDEX86:%.*]] = phi i16 [ 0, [[FOR_COND37_PREHEADER_SPLIT]] ], [ [[TMP3:%.*]], [[VECTOR_BODY85_SPLIT:%.*]] ] ; CHECK-NEXT: br label [[FOR_COND33_PREHEADER_PREHEADER]] ; CHECK: vector.body85.split1: -; CHECK-NEXT: [[TMP0:%.*]] = or i16 [[INDEX86]], 2 +; CHECK-NEXT: [[TMP0:%.*]] = or disjoint i16 [[INDEX86]], 2 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [512 x [4 x i32]], ptr @b, i16 0, i16 [[TMP0]], i16 [[J_165]] ; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 1 ; CHECK-NEXT: [[INDEX_NEXT87:%.*]] = add nuw i16 [[INDEX86]], 4 @@ -148,7 +148,7 @@ for.cond37.preheader: ; preds = %middle.block80, %fo vector.body85: ; preds = %vector.body85, %for.cond37.preheader %index86 = phi i16 [ 0, %for.cond37.preheader ], [ %index.next87, %vector.body85 ] - %0 = or i16 %index86, 2 + %0 = or disjoint i16 %index86, 2 %1 = getelementptr inbounds [512 x [4 x i32]], ptr @b, i16 0, i16 %0, i16 %j.165 %2 = load i32, ptr %1, align 1 %index.next87 = add nuw i16 %index86, 4 diff --git a/llvm/test/Transforms/LoopReroll/basic32iters.ll b/llvm/test/Transforms/LoopReroll/basic32iters.ll index 6c313c1febab..edf38cb3eb18 100644 --- a/llvm/test/Transforms/LoopReroll/basic32iters.ll +++ b/llvm/test/Transforms/LoopReroll/basic32iters.ll @@ -53,7 +53,7 @@ for.body: ; preds = %entry, %for.body %1 = load float, ptr %arrayidx2, align 4 %add = fadd float %1, %mul store float %add, ptr %arrayidx2, align 4 - %2 = or i64 %indvars.iv, 1 + %2 = or disjoint i64 %indvars.iv, 1 %arrayidx5 = getelementptr inbounds float, ptr %b, i64 %2 %3 = load float, ptr %arrayidx5, align 4 %mul6 = fmul float %3, %alpha @@ -61,7 +61,7 @@ for.body: ; preds = %entry, %for.body %4 = load float, ptr %arrayidx9, align 4 %add10 = fadd float %4, %mul6 store float %add10, ptr %arrayidx9, align 4 - %5 = or i64 %indvars.iv, 2 + %5 = or disjoint i64 %indvars.iv, 2 %arrayidx13 = getelementptr inbounds float, ptr %b, i64 %5 %6 = load float, ptr %arrayidx13, align 4 %mul14 = fmul float %6, %alpha @@ -69,7 +69,7 @@ for.body: ; preds = %entry, %for.body %7 = load float, ptr %arrayidx17, align 4 %add18 = fadd float %7, %mul14 store float %add18, ptr %arrayidx17, align 4 - %8 = or i64 %indvars.iv, 3 + %8 = or disjoint i64 %indvars.iv, 3 %arrayidx21 = getelementptr inbounds float, ptr %b, i64 %8 %9 = load float, ptr %arrayidx21, align 4 %mul22 = fmul float %9, %alpha @@ -77,7 +77,7 @@ for.body: ; preds = %entry, %for.body %10 = load float, ptr %arrayidx25, align 4 %add26 = fadd float %10, %mul22 store float %add26, ptr %arrayidx25, align 4 - %11 = or i64 %indvars.iv, 4 + %11 = or disjoint i64 %indvars.iv, 4 %arrayidx29 = getelementptr inbounds float, ptr %b, i64 %11 %12 = load float, ptr %arrayidx29, align 4 %mul30 = fmul float %12, %alpha @@ -85,7 +85,7 @@ for.body: ; preds = %entry, %for.body %13 = load float, ptr %arrayidx33, align 4 %add34 = fadd float %13, %mul30 store float %add34, ptr %arrayidx33, align 4 - %14 = or i64 %indvars.iv, 5 + %14 = or disjoint i64 %indvars.iv, 5 %arrayidx37 = getelementptr inbounds float, ptr %b, i64 %14 %15 = load float, ptr %arrayidx37, align 4 %mul38 = fmul float %15, %alpha @@ -93,7 +93,7 @@ for.body: ; preds = %entry, %for.body %16 = load float, ptr %arrayidx41, align 4 %add42 = fadd float %16, %mul38 store float %add42, ptr %arrayidx41, align 4 - %17 = or i64 %indvars.iv, 6 + %17 = or disjoint i64 %indvars.iv, 6 %arrayidx45 = getelementptr inbounds float, ptr %b, i64 %17 %18 = load float, ptr %arrayidx45, align 4 %mul46 = fmul float %18, %alpha @@ -101,7 +101,7 @@ for.body: ; preds = %entry, %for.body %19 = load float, ptr %arrayidx49, align 4 %add50 = fadd float %19, %mul46 store float %add50, ptr %arrayidx49, align 4 - %20 = or i64 %indvars.iv, 7 + %20 = or disjoint i64 %indvars.iv, 7 %arrayidx53 = getelementptr inbounds float, ptr %b, i64 %20 %21 = load float, ptr %arrayidx53, align 4 %mul54 = fmul float %21, %alpha @@ -109,7 +109,7 @@ for.body: ; preds = %entry, %for.body %22 = load float, ptr %arrayidx57, align 4 %add58 = fadd float %22, %mul54 store float %add58, ptr %arrayidx57, align 4 - %23 = or i64 %indvars.iv, 8 + %23 = or disjoint i64 %indvars.iv, 8 %arrayidx61 = getelementptr inbounds float, ptr %b, i64 %23 %24 = load float, ptr %arrayidx61, align 4 %mul62 = fmul float %24, %alpha @@ -117,7 +117,7 @@ for.body: ; preds = %entry, %for.body %25 = load float, ptr %arrayidx65, align 4 %add66 = fadd float %25, %mul62 store float %add66, ptr %arrayidx65, align 4 - %26 = or i64 %indvars.iv, 9 + %26 = or disjoint i64 %indvars.iv, 9 %arrayidx69 = getelementptr inbounds float, ptr %b, i64 %26 %27 = load float, ptr %arrayidx69, align 4 %mul70 = fmul float %27, %alpha @@ -125,7 +125,7 @@ for.body: ; preds = %entry, %for.body %28 = load float, ptr %arrayidx73, align 4 %add74 = fadd float %28, %mul70 store float %add74, ptr %arrayidx73, align 4 - %29 = or i64 %indvars.iv, 10 + %29 = or disjoint i64 %indvars.iv, 10 %arrayidx77 = getelementptr inbounds float, ptr %b, i64 %29 %30 = load float, ptr %arrayidx77, align 4 %mul78 = fmul float %30, %alpha @@ -133,7 +133,7 @@ for.body: ; preds = %entry, %for.body %31 = load float, ptr %arrayidx81, align 4 %add82 = fadd float %31, %mul78 store float %add82, ptr %arrayidx81, align 4 - %32 = or i64 %indvars.iv, 11 + %32 = or disjoint i64 %indvars.iv, 11 %arrayidx85 = getelementptr inbounds float, ptr %b, i64 %32 %33 = load float, ptr %arrayidx85, align 4 %mul86 = fmul float %33, %alpha @@ -141,7 +141,7 @@ for.body: ; preds = %entry, %for.body %34 = load float, ptr %arrayidx89, align 4 %add90 = fadd float %34, %mul86 store float %add90, ptr %arrayidx89, align 4 - %35 = or i64 %indvars.iv, 12 + %35 = or disjoint i64 %indvars.iv, 12 %arrayidx93 = getelementptr inbounds float, ptr %b, i64 %35 %36 = load float, ptr %arrayidx93, align 4 %mul94 = fmul float %36, %alpha @@ -149,7 +149,7 @@ for.body: ; preds = %entry, %for.body %37 = load float, ptr %arrayidx97, align 4 %add98 = fadd float %37, %mul94 store float %add98, ptr %arrayidx97, align 4 - %38 = or i64 %indvars.iv, 13 + %38 = or disjoint i64 %indvars.iv, 13 %arrayidx101 = getelementptr inbounds float, ptr %b, i64 %38 %39 = load float, ptr %arrayidx101, align 4 %mul102 = fmul float %39, %alpha @@ -157,7 +157,7 @@ for.body: ; preds = %entry, %for.body %40 = load float, ptr %arrayidx105, align 4 %add106 = fadd float %40, %mul102 store float %add106, ptr %arrayidx105, align 4 - %41 = or i64 %indvars.iv, 14 + %41 = or disjoint i64 %indvars.iv, 14 %arrayidx109 = getelementptr inbounds float, ptr %b, i64 %41 %42 = load float, ptr %arrayidx109, align 4 %mul110 = fmul float %42, %alpha @@ -165,7 +165,7 @@ for.body: ; preds = %entry, %for.body %43 = load float, ptr %arrayidx113, align 4 %add114 = fadd float %43, %mul110 store float %add114, ptr %arrayidx113, align 4 - %44 = or i64 %indvars.iv, 15 + %44 = or disjoint i64 %indvars.iv, 15 %arrayidx117 = getelementptr inbounds float, ptr %b, i64 %44 %45 = load float, ptr %arrayidx117, align 4 %mul118 = fmul float %45, %alpha @@ -173,7 +173,7 @@ for.body: ; preds = %entry, %for.body %46 = load float, ptr %arrayidx121, align 4 %add122 = fadd float %46, %mul118 store float %add122, ptr %arrayidx121, align 4 - %47 = or i64 %indvars.iv, 16 + %47 = or disjoint i64 %indvars.iv, 16 %arrayidx125 = getelementptr inbounds float, ptr %b, i64 %47 %48 = load float, ptr %arrayidx125, align 4 %mul126 = fmul float %48, %alpha @@ -181,7 +181,7 @@ for.body: ; preds = %entry, %for.body %49 = load float, ptr %arrayidx129, align 4 %add130 = fadd float %49, %mul126 store float %add130, ptr %arrayidx129, align 4 - %50 = or i64 %indvars.iv, 17 + %50 = or disjoint i64 %indvars.iv, 17 %arrayidx133 = getelementptr inbounds float, ptr %b, i64 %50 %51 = load float, ptr %arrayidx133, align 4 %mul134 = fmul float %51, %alpha @@ -189,7 +189,7 @@ for.body: ; preds = %entry, %for.body %52 = load float, ptr %arrayidx137, align 4 %add138 = fadd float %52, %mul134 store float %add138, ptr %arrayidx137, align 4 - %53 = or i64 %indvars.iv, 18 + %53 = or disjoint i64 %indvars.iv, 18 %arrayidx141 = getelementptr inbounds float, ptr %b, i64 %53 %54 = load float, ptr %arrayidx141, align 4 %mul142 = fmul float %54, %alpha @@ -197,7 +197,7 @@ for.body: ; preds = %entry, %for.body %55 = load float, ptr %arrayidx145, align 4 %add146 = fadd float %55, %mul142 store float %add146, ptr %arrayidx145, align 4 - %56 = or i64 %indvars.iv, 19 + %56 = or disjoint i64 %indvars.iv, 19 %arrayidx149 = getelementptr inbounds float, ptr %b, i64 %56 %57 = load float, ptr %arrayidx149, align 4 %mul150 = fmul float %57, %alpha @@ -205,7 +205,7 @@ for.body: ; preds = %entry, %for.body %58 = load float, ptr %arrayidx153, align 4 %add154 = fadd float %58, %mul150 store float %add154, ptr %arrayidx153, align 4 - %59 = or i64 %indvars.iv, 20 + %59 = or disjoint i64 %indvars.iv, 20 %arrayidx157 = getelementptr inbounds float, ptr %b, i64 %59 %60 = load float, ptr %arrayidx157, align 4 %mul158 = fmul float %60, %alpha @@ -213,7 +213,7 @@ for.body: ; preds = %entry, %for.body %61 = load float, ptr %arrayidx161, align 4 %add162 = fadd float %61, %mul158 store float %add162, ptr %arrayidx161, align 4 - %62 = or i64 %indvars.iv, 21 + %62 = or disjoint i64 %indvars.iv, 21 %arrayidx165 = getelementptr inbounds float, ptr %b, i64 %62 %63 = load float, ptr %arrayidx165, align 4 %mul166 = fmul float %63, %alpha @@ -221,7 +221,7 @@ for.body: ; preds = %entry, %for.body %64 = load float, ptr %arrayidx169, align 4 %add170 = fadd float %64, %mul166 store float %add170, ptr %arrayidx169, align 4 - %65 = or i64 %indvars.iv, 22 + %65 = or disjoint i64 %indvars.iv, 22 %arrayidx173 = getelementptr inbounds float, ptr %b, i64 %65 %66 = load float, ptr %arrayidx173, align 4 %mul174 = fmul float %66, %alpha @@ -229,7 +229,7 @@ for.body: ; preds = %entry, %for.body %67 = load float, ptr %arrayidx177, align 4 %add178 = fadd float %67, %mul174 store float %add178, ptr %arrayidx177, align 4 - %68 = or i64 %indvars.iv, 23 + %68 = or disjoint i64 %indvars.iv, 23 %arrayidx181 = getelementptr inbounds float, ptr %b, i64 %68 %69 = load float, ptr %arrayidx181, align 4 %mul182 = fmul float %69, %alpha @@ -237,7 +237,7 @@ for.body: ; preds = %entry, %for.body %70 = load float, ptr %arrayidx185, align 4 %add186 = fadd float %70, %mul182 store float %add186, ptr %arrayidx185, align 4 - %71 = or i64 %indvars.iv, 24 + %71 = or disjoint i64 %indvars.iv, 24 %arrayidx189 = getelementptr inbounds float, ptr %b, i64 %71 %72 = load float, ptr %arrayidx189, align 4 %mul190 = fmul float %72, %alpha @@ -245,7 +245,7 @@ for.body: ; preds = %entry, %for.body %73 = load float, ptr %arrayidx193, align 4 %add194 = fadd float %73, %mul190 store float %add194, ptr %arrayidx193, align 4 - %74 = or i64 %indvars.iv, 25 + %74 = or disjoint i64 %indvars.iv, 25 %arrayidx197 = getelementptr inbounds float, ptr %b, i64 %74 %75 = load float, ptr %arrayidx197, align 4 %mul198 = fmul float %75, %alpha @@ -253,7 +253,7 @@ for.body: ; preds = %entry, %for.body %76 = load float, ptr %arrayidx201, align 4 %add202 = fadd float %76, %mul198 store float %add202, ptr %arrayidx201, align 4 - %77 = or i64 %indvars.iv, 26 + %77 = or disjoint i64 %indvars.iv, 26 %arrayidx205 = getelementptr inbounds float, ptr %b, i64 %77 %78 = load float, ptr %arrayidx205, align 4 %mul206 = fmul float %78, %alpha @@ -261,7 +261,7 @@ for.body: ; preds = %entry, %for.body %79 = load float, ptr %arrayidx209, align 4 %add210 = fadd float %79, %mul206 store float %add210, ptr %arrayidx209, align 4 - %80 = or i64 %indvars.iv, 27 + %80 = or disjoint i64 %indvars.iv, 27 %arrayidx213 = getelementptr inbounds float, ptr %b, i64 %80 %81 = load float, ptr %arrayidx213, align 4 %mul214 = fmul float %81, %alpha @@ -269,7 +269,7 @@ for.body: ; preds = %entry, %for.body %82 = load float, ptr %arrayidx217, align 4 %add218 = fadd float %82, %mul214 store float %add218, ptr %arrayidx217, align 4 - %83 = or i64 %indvars.iv, 28 + %83 = or disjoint i64 %indvars.iv, 28 %arrayidx221 = getelementptr inbounds float, ptr %b, i64 %83 %84 = load float, ptr %arrayidx221, align 4 %mul222 = fmul float %84, %alpha @@ -277,7 +277,7 @@ for.body: ; preds = %entry, %for.body %85 = load float, ptr %arrayidx225, align 4 %add226 = fadd float %85, %mul222 store float %add226, ptr %arrayidx225, align 4 - %86 = or i64 %indvars.iv, 29 + %86 = or disjoint i64 %indvars.iv, 29 %arrayidx229 = getelementptr inbounds float, ptr %b, i64 %86 %87 = load float, ptr %arrayidx229, align 4 %mul230 = fmul float %87, %alpha @@ -285,7 +285,7 @@ for.body: ; preds = %entry, %for.body %88 = load float, ptr %arrayidx233, align 4 %add234 = fadd float %88, %mul230 store float %add234, ptr %arrayidx233, align 4 - %89 = or i64 %indvars.iv, 30 + %89 = or disjoint i64 %indvars.iv, 30 %arrayidx237 = getelementptr inbounds float, ptr %b, i64 %89 %90 = load float, ptr %arrayidx237, align 4 %mul238 = fmul float %90, %alpha @@ -293,7 +293,7 @@ for.body: ; preds = %entry, %for.body %91 = load float, ptr %arrayidx241, align 4 %add242 = fadd float %91, %mul238 store float %add242, ptr %arrayidx241, align 4 - %92 = or i64 %indvars.iv, 31 + %92 = or disjoint i64 %indvars.iv, 31 %arrayidx245 = getelementptr inbounds float, ptr %b, i64 %92 %93 = load float, ptr %arrayidx245, align 4 %mul246 = fmul float %93, %alpha diff --git a/llvm/test/Transforms/LoopReroll/indvar_with_ext.ll b/llvm/test/Transforms/LoopReroll/indvar_with_ext.ll index e867972050a1..3fcd43f1866a 100644 --- a/llvm/test/Transforms/LoopReroll/indvar_with_ext.ll +++ b/llvm/test/Transforms/LoopReroll/indvar_with_ext.ll @@ -82,7 +82,7 @@ for.body: ; preds = %for.body.preheader, %0 = load i32, ptr %arrayidx, align 4 %arrayidx3 = getelementptr inbounds i32, ptr %x, i64 %indvars.iv store i32 %0, ptr %arrayidx3, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx5 = getelementptr inbounds i32, ptr %y, i64 %1 %2 = load i32, ptr %arrayidx5, align 4 %arrayidx8 = getelementptr inbounds i32, ptr %x, i64 %1 @@ -122,7 +122,7 @@ for.body: ; preds = %for.body.preheader, %0 = load i32, ptr %arrayidx, align 4 %arrayidx3 = getelementptr inbounds i32, ptr %x, i64 %idxprom store i32 %0, ptr %arrayidx3, align 4 - %add = or i32 %conv23, 1 + %add = or disjoint i32 %conv23, 1 %idxprom5 = sext i32 %add to i64 %arrayidx6 = getelementptr inbounds i32, ptr %y, i64 %idxprom5 %1 = load i32, ptr %arrayidx6, align 4 @@ -166,7 +166,7 @@ for.body: ; preds = %for.body.preheader, %0 = load i32, ptr %arrayidx, align 4 %arrayidx3 = getelementptr inbounds i32, ptr %x, i64 %indvars.iv store i32 %0, ptr %arrayidx3, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx5 = getelementptr inbounds i32, ptr %y, i64 %1 %2 = load i32, ptr %arrayidx5, align 4 %arrayidx8 = getelementptr inbounds i32, ptr %x, i64 %1 diff --git a/llvm/test/Transforms/LoopReroll/reduction.ll b/llvm/test/Transforms/LoopReroll/reduction.ll index 4125716bfb5a..94f4d53bfbf6 100644 --- a/llvm/test/Transforms/LoopReroll/reduction.ll +++ b/llvm/test/Transforms/LoopReroll/reduction.ll @@ -12,15 +12,15 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds i32, ptr %x, i64 %indvars.iv %0 = load i32, ptr %arrayidx, align 4 %add = add nsw i32 %0, %r.029 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx3 = getelementptr inbounds i32, ptr %x, i64 %1 %2 = load i32, ptr %arrayidx3, align 4 %add4 = add nsw i32 %add, %2 - %3 = or i64 %indvars.iv, 2 + %3 = or disjoint i64 %indvars.iv, 2 %arrayidx7 = getelementptr inbounds i32, ptr %x, i64 %3 %4 = load i32, ptr %arrayidx7, align 4 %add8 = add nsw i32 %add4, %4 - %5 = or i64 %indvars.iv, 3 + %5 = or disjoint i64 %indvars.iv, 3 %arrayidx11 = getelementptr inbounds i32, ptr %x, i64 %5 %6 = load i32, ptr %arrayidx11, align 4 %add12 = add nsw i32 %add8, %6 @@ -57,15 +57,15 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds float, ptr %x, i64 %indvars.iv %0 = load float, ptr %arrayidx, align 4 %add = fadd float %0, %r.029 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx3 = getelementptr inbounds float, ptr %x, i64 %1 %2 = load float, ptr %arrayidx3, align 4 %add4 = fadd float %add, %2 - %3 = or i64 %indvars.iv, 2 + %3 = or disjoint i64 %indvars.iv, 2 %arrayidx7 = getelementptr inbounds float, ptr %x, i64 %3 %4 = load float, ptr %arrayidx7, align 4 %add8 = fadd float %add4, %4 - %5 = or i64 %indvars.iv, 3 + %5 = or disjoint i64 %indvars.iv, 3 %arrayidx11 = getelementptr inbounds float, ptr %x, i64 %5 %6 = load float, ptr %arrayidx11, align 4 %add12 = fadd float %add8, %6 @@ -102,15 +102,15 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds i32, ptr %x, i64 %indvars.iv %0 = load i32, ptr %arrayidx, align 4 %add = add nsw i32 %0, %0 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx3 = getelementptr inbounds i32, ptr %x, i64 %1 %2 = load i32, ptr %arrayidx3, align 4 %add4 = add nsw i32 %add, %2 - %3 = or i64 %indvars.iv, 2 + %3 = or disjoint i64 %indvars.iv, 2 %arrayidx7 = getelementptr inbounds i32, ptr %x, i64 %3 %4 = load i32, ptr %arrayidx7, align 4 %add8 = add nsw i32 %add4, %4 - %5 = or i64 %indvars.iv, 3 + %5 = or disjoint i64 %indvars.iv, 3 %arrayidx11 = getelementptr inbounds i32, ptr %x, i64 %5 %6 = load i32, ptr %arrayidx11, align 4 %add12 = add nsw i32 %add8, %6 diff --git a/llvm/test/Transforms/LoopReroll/reroll_with_dbg.ll b/llvm/test/Transforms/LoopReroll/reroll_with_dbg.ll index 32f9d72c5f66..e720e761f4d6 100644 --- a/llvm/test/Transforms/LoopReroll/reroll_with_dbg.ll +++ b/llvm/test/Transforms/LoopReroll/reroll_with_dbg.ll @@ -46,17 +46,17 @@ for.body: ; preds = %for.body.preheader, %0 = load i32, ptr %arrayidx, align 4, !dbg !30, !tbaa !33 %arrayidx1 = getelementptr inbounds float, ptr %a, i32 %i.031, !dbg !37 store i32 %0, ptr %arrayidx1, align 4, !dbg !38, !tbaa !33 - %add = or i32 %i.031, 1, !dbg !39 + %add = or disjoint i32 %i.031, 1, !dbg !39 %arrayidx2 = getelementptr inbounds float, ptr %b, i32 %add, !dbg !40 %1 = load i32, ptr %arrayidx2, align 4, !dbg !40, !tbaa !33 %arrayidx4 = getelementptr inbounds float, ptr %a, i32 %add, !dbg !41 store i32 %1, ptr %arrayidx4, align 4, !dbg !42, !tbaa !33 - %add5 = or i32 %i.031, 2, !dbg !43 + %add5 = or disjoint i32 %i.031, 2, !dbg !43 %arrayidx6 = getelementptr inbounds float, ptr %b, i32 %add5, !dbg !44 %2 = load i32, ptr %arrayidx6, align 4, !dbg !44, !tbaa !33 %arrayidx8 = getelementptr inbounds float, ptr %a, i32 %add5, !dbg !45 store i32 %2, ptr %arrayidx8, align 4, !dbg !46, !tbaa !33 - %add9 = or i32 %i.031, 3, !dbg !47 + %add9 = or disjoint i32 %i.031, 3, !dbg !47 %arrayidx10 = getelementptr inbounds float, ptr %b, i32 %add9, !dbg !48 %3 = load i32, ptr %arrayidx10, align 4, !dbg !48, !tbaa !33 %arrayidx12 = getelementptr inbounds float, ptr %a, i32 %add9, !dbg !49 diff --git a/llvm/test/Transforms/LoopRotate/delete-dbg-values.ll b/llvm/test/Transforms/LoopRotate/delete-dbg-values.ll new file mode 100644 index 000000000000..bce5ed02b43b --- /dev/null +++ b/llvm/test/Transforms/LoopRotate/delete-dbg-values.ll @@ -0,0 +1,63 @@ +; RUN: opt --passes=loop-rotate -o - -S %s | FileCheck %s --implicit-check-not=dbg.value +; RUN: opt --passes=loop-rotate -o - -S %s --try-experimental-debuginfo-iterators | FileCheck %s --implicit-check-not=dbg.value +; +;; Test some fine-grained behaviour of loop-rotate's de-duplication of +;; dbg.values. The intrinsic on the first branch should be seen and +;; prevent the rotation of the dbg.value for "sink" into the entry block. +;; However the other dbg.value, for "source", should not be seen, and we'll +;; get a duplicate. +; +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; CHECK: declare void @llvm.dbg.value(metadata, + +; CHECK-LABEL: define void @_ZNK4llvm5APInt4sextEj(ptr +; CHECK-LABEL: entry: +; CHECK: call void @llvm.dbg.value(metadata i32 0, metadata ![[SRC:[0-9]+]], +; CHECK-NEXT: load +; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 0, metadata ![[SINK:[0-9]+]], +; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 0, metadata ![[SRC]], +; CHECK-LABEL: for.body: +; CHECK: call void @llvm.dbg.value(metadata i32 0, metadata ![[SINK]], +; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 0, metadata ![[SRC]], + +declare void @llvm.dbg.value(metadata, metadata, metadata) + +define void @_ZNK4llvm5APInt4sextEj(ptr %agg.result) !dbg !5 { +entry: + tail call void @llvm.dbg.value(metadata i32 0, metadata !4, metadata !DIExpression()), !dbg !10 + %.pre = load i32, ptr %agg.result, align 8 + tail call void @llvm.dbg.value(metadata i32 0, metadata !11, metadata !DIExpression()), !dbg !10 + br label %for.cond + +for.cond: ; preds = %for.body, %entry + %i.0 = phi i32 [ 0, %entry ], [ 1, %for.body ] + tail call void @llvm.dbg.value(metadata i32 0, metadata !11, metadata !DIExpression()), !dbg !10 + tail call void @llvm.dbg.value(metadata i32 0, metadata !4, metadata !DIExpression()), !dbg !10 + %cmp12.not = icmp eq i32 %i.0, %.pre, !dbg !10 + br i1 %cmp12.not, label %for.end, label %for.body + +for.body: ; preds = %for.cond + store i64 0, ptr %agg.result, align 8 + br label %for.cond + +for.end: ; preds = %for.cond + ret void +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "foo", directory: "bar") +!2 = !{} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !DILocalVariable(name: "source", scope: !5, file: !6, line: 170, type: !8) +!5 = distinct !DISubprogram(name: "ConvertUTF16toUTF32", scope: !6, file: !6, line: 166, type: !7, scopeLine: 168, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2) +!6 = !DIFile(filename: "fooo", directory: ".") +!7 = !DISubroutineType(types: !2) +!8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64) +!9 = !DIBasicType(name: "unsigned short", size: 16, encoding: DW_ATE_unsigned) +!10 = !DILocation(line: 0, scope: !5) +!11 = !DILocalVariable(name: "sink", scope: !5, file: !6, line: 170, type: !8) diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/complexity.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/complexity.ll index 9ad65439f5a4..1b64ade50f21 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/complexity.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/ARM/complexity.ll @@ -54,7 +54,7 @@ for.body12.us.us: ; preds = %for.body12.us.us, % %conv17.us.us = sext i16 %tmp10 to i32 %mul.us.us = mul nsw i32 %conv17.us.us, %conv.us.us %add18.us.us = add nsw i32 %mul.us.us, %result_element.152.us.us - %inc.us.us = or i32 %filter_x.053.us.us, 1 + %inc.us.us = or disjoint i32 %filter_x.053.us.us, 1 %add13.us.us.1 = add i32 %inc.us.us, %res_x.060.us %arrayidx14.us.us.1 = getelementptr inbounds i16, ptr %tmp5, i32 %inc.us.us %tmp11 = load i16, ptr %arrayidx14.us.us.1, align 2 @@ -64,7 +64,7 @@ for.body12.us.us: ; preds = %for.body12.us.us, % %conv17.us.us.1 = sext i16 %tmp12 to i32 %mul.us.us.1 = mul nsw i32 %conv17.us.us.1, %conv.us.us.1 %add18.us.us.1 = add nsw i32 %mul.us.us.1, %add18.us.us - %inc.us.us.1 = or i32 %filter_x.053.us.us, 2 + %inc.us.us.1 = or disjoint i32 %filter_x.053.us.us, 2 %add13.us.us.2 = add i32 %inc.us.us.1, %res_x.060.us %arrayidx14.us.us.2 = getelementptr inbounds i16, ptr %tmp5, i32 %inc.us.us.1 %tmp13 = load i16, ptr %arrayidx14.us.us.2, align 2 @@ -74,7 +74,7 @@ for.body12.us.us: ; preds = %for.body12.us.us, % %conv17.us.us.2 = sext i16 %tmp14 to i32 %mul.us.us.2 = mul nsw i32 %conv17.us.us.2, %conv.us.us.2 %add18.us.us.2 = add nsw i32 %mul.us.us.2, %add18.us.us.1 - %inc.us.us.2 = or i32 %filter_x.053.us.us, 3 + %inc.us.us.2 = or disjoint i32 %filter_x.053.us.us, 3 %add13.us.us.3 = add i32 %inc.us.us.2, %res_x.060.us %arrayidx14.us.us.3 = getelementptr inbounds i16, ptr %tmp5, i32 %inc.us.us.2 %tmp15 = load i16, ptr %arrayidx14.us.us.3, align 2 diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll index 07debadf34f5..1614de8dbf55 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll @@ -245,7 +245,7 @@ for.body: ; preds = %for.body, %entry %conv3 = trunc i32 %add to i8 %arrayidx4 = getelementptr inbounds i8, ptr %c, i32 %i.07 store i8 %conv3, ptr %arrayidx4, align 1 - %inc1 = or i32 %i.07, 1 + %inc1 = or disjoint i32 %i.07, 1 %arrayidx.1 = getelementptr inbounds i8, ptr %a, i32 %inc1 %2 = load i8, ptr %arrayidx.1, align 1 %conv5.1 = zext i8 %2 to i32 @@ -256,7 +256,7 @@ for.body: ; preds = %for.body, %entry %conv3.1 = trunc i32 %add.1 to i8 %arrayidx4.1 = getelementptr inbounds i8, ptr %c, i32 %inc1 store i8 %conv3.1, ptr %arrayidx4.1, align 1 - %inc.12 = or i32 %i.07, 2 + %inc.12 = or disjoint i32 %i.07, 2 %arrayidx.2 = getelementptr inbounds i8, ptr %a, i32 %inc.12 %4 = load i8, ptr %arrayidx.2, align 1 %conv5.2 = zext i8 %4 to i32 @@ -267,7 +267,7 @@ for.body: ; preds = %for.body, %entry %conv3.2 = trunc i32 %add.2 to i8 %arrayidx4.2 = getelementptr inbounds i8, ptr %c, i32 %inc.12 store i8 %conv3.2, ptr %arrayidx4.2, align 1 - %inc.23 = or i32 %i.07, 3 + %inc.23 = or disjoint i32 %i.07, 3 %arrayidx.3 = getelementptr inbounds i8, ptr %a, i32 %inc.23 %6 = load i8, ptr %arrayidx.3, align 1 %conv5.3 = zext i8 %6 to i32 diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll index d618b6365fac..39e2d6f1acca 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll @@ -385,7 +385,7 @@ for.body: ; preds = %for.body, %entry %conv3 = trunc i32 %add to i8 %arrayidx4 = getelementptr inbounds i8, ptr %c, i32 %i.07 store i8 %conv3, ptr %arrayidx4, align 1 - %inc1 = or i32 %i.07, 1 + %inc1 = or disjoint i32 %i.07, 1 %arrayidx.1 = getelementptr inbounds i8, ptr %a, i32 %inc1 %2 = load i8, ptr %arrayidx.1, align 1 %conv5.1 = zext i8 %2 to i32 @@ -396,7 +396,7 @@ for.body: ; preds = %for.body, %entry %conv3.1 = trunc i32 %add.1 to i8 %arrayidx4.1 = getelementptr inbounds i8, ptr %c, i32 %inc1 store i8 %conv3.1, ptr %arrayidx4.1, align 1 - %inc.12 = or i32 %i.07, 2 + %inc.12 = or disjoint i32 %i.07, 2 %arrayidx.2 = getelementptr inbounds i8, ptr %a, i32 %inc.12 %4 = load i8, ptr %arrayidx.2, align 1 %conv5.2 = zext i8 %4 to i32 @@ -407,7 +407,7 @@ for.body: ; preds = %for.body, %entry %conv3.2 = trunc i32 %add.2 to i8 %arrayidx4.2 = getelementptr inbounds i8, ptr %c, i32 %inc.12 store i8 %conv3.2, ptr %arrayidx4.2, align 1 - %inc.23 = or i32 %i.07, 3 + %inc.23 = or disjoint i32 %i.07, 3 %arrayidx.3 = getelementptr inbounds i8, ptr %a, i32 %inc.23 %6 = load i8, ptr %arrayidx.3, align 1 %conv5.3 = zext i8 %6 to i32 @@ -478,7 +478,7 @@ for.body: %p = phi ptr [ %p.next, %for.body ], [ %a, %entry ] %i = phi i32 [ %inc4, %for.body ], [ 0, %entry ] store i32 %i, ptr %p, align 4 - %inc1 = or i32 %i, 1 + %inc1 = or disjoint i32 %i, 1 %add.ptr.i1 = getelementptr inbounds i32, ptr %p, i32 1 store i32 %inc1, ptr %add.ptr.i1, align 4 %inc2 = add nsw i32 %i, 2 diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/missing-phi-operand-update.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/missing-phi-operand-update.ll index 83f30ad33431..b13503543d6e 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/X86/missing-phi-operand-update.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/X86/missing-phi-operand-update.ll @@ -13,8 +13,8 @@ target triple = "x86_64-unknown-linux-gnu" ; All the other PHI inputs besides %tmp1 go to a new phi node. ; This test checks that LSR is still able to rewrite %tmp2, %tmp3, %tmp4. define i32 @foo(ptr %A, i32 %t) { -; CHECK-LABEL: define i32 @foo -; CHECK-SAME: (ptr [[A:%.*]], i32 [[T:%.*]]) { +; CHECK-LABEL: define i32 @foo( +; CHECK-SAME: ptr [[A:%.*]], i32 [[T:%.*]]) { ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[LOOP_32:%.*]] ; CHECK: loop.exit.loopexitsplitsplitsplit: @@ -131,7 +131,7 @@ for.end: ; preds = %then.8.1, %ifmerge. loop.32: ; preds = %ifmerge.46, %entry %i1.i64.0 = phi i64 [ 0, %entry ], [ %nextivloop.32, %ifmerge.46 ] %tmp1 = shl i64 %i1.i64.0, 2 - %tmp2 = or i64 %tmp1, 1 + %tmp2 = or disjoint i64 %tmp1, 1 %arrayIdx = getelementptr inbounds i32, ptr %A, i64 %tmp2 %gepload = load i32, ptr %arrayIdx, align 4 %cmp.34 = icmp sgt i32 %gepload, %t @@ -144,7 +144,7 @@ then.34: ; preds = %loop.32 br i1 %cmp.35, label %loop.exit, label %ifmerge.34 ifmerge.34: ; preds = %then.34, %loop.32 - %tmp3 = or i64 %tmp1, 2 + %tmp3 = or disjoint i64 %tmp1, 2 %arrayIdx19 = getelementptr inbounds i32, ptr %A, i64 %tmp3 %gepload20 = load i32, ptr %arrayIdx19, align 4 %cmp.38 = icmp sgt i32 %gepload20, %t @@ -153,7 +153,7 @@ ifmerge.34: ; preds = %then.34, %loop.32 br i1 %or.cond, label %loop.exit, label %ifmerge.38 ifmerge.38: ; preds = %ifmerge.34 - %tmp4 = or i64 %tmp1, 3 + %tmp4 = or disjoint i64 %tmp1, 3 %arrayIdx23 = getelementptr inbounds i32, ptr %A, i64 %tmp4 %gepload24 = load i32, ptr %arrayIdx23, align 4 %cmp.42 = icmp sgt i32 %gepload24, %t diff --git a/llvm/test/Transforms/LoopUnroll/X86/high-cost-expansion.ll b/llvm/test/Transforms/LoopUnroll/X86/high-cost-expansion.ll index be7547c09741..d5d4319b041a 100644 --- a/llvm/test/Transforms/LoopUnroll/X86/high-cost-expansion.ll +++ b/llvm/test/Transforms/LoopUnroll/X86/high-cost-expansion.ll @@ -7,7 +7,7 @@ define void @mask-high(i64 %arg, ptr dereferenceable(4) %arg1) { ; CHECK-NEXT: [[I:%.*]] = load i32, ptr [[ARG1:%.*]], align 4 ; CHECK-NEXT: [[I2:%.*]] = sext i32 [[I]] to i64 ; CHECK-NEXT: [[I3:%.*]] = and i64 [[ARG:%.*]], -16 -; CHECK-NEXT: [[I4:%.*]] = or i64 1, [[I3]] +; CHECK-NEXT: [[I4:%.*]] = or disjoint i64 1, [[I3]] ; CHECK-NEXT: [[I5:%.*]] = icmp sgt i64 [[I4]], [[I2]] ; CHECK-NEXT: br i1 [[I5]], label [[BB10:%.*]], label [[BB6_PREHEADER:%.*]] ; CHECK: bb6.preheader: @@ -26,7 +26,7 @@ bb: %i = load i32, ptr %arg1, align 4 %i2 = sext i32 %i to i64 %i3 = and i64 %arg, -16 - %i4 = or i64 1, %i3 + %i4 = or disjoint i64 1, %i3 %i5 = icmp sgt i64 %i4, %i2 br i1 %i5, label %bb10, label %bb6 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll index f045f486eac2..2e994838ff24 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll @@ -556,7 +556,7 @@ define void @fadd_strict_interleave(ptr noalias nocapture readonly %a, ptr noali ; CHECK-NOT-VECTORIZED-NEXT: [[ARRAYIDXB1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]] ; CHECK-NOT-VECTORIZED-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDXB1]], align 4 ; CHECK-NOT-VECTORIZED-NEXT: [[ADD1]] = fadd float [[TMP0]], [[ADD_PHI2]] -; CHECK-NOT-VECTORIZED-NEXT: [[OR:%.*]] = or i64 [[IV]], 1 +; CHECK-NOT-VECTORIZED-NEXT: [[OR:%.*]] = or disjoint i64 [[IV]], 1 ; CHECK-NOT-VECTORIZED-NEXT: [[ARRAYIDXB2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[OR]] ; CHECK-NOT-VECTORIZED-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDXB2]], align 4 ; CHECK-NOT-VECTORIZED-NEXT: [[ADD2]] = fadd float [[TMP1]], [[ADD_PHI1]] @@ -628,7 +628,7 @@ define void @fadd_strict_interleave(ptr noalias nocapture readonly %a, ptr noali ; CHECK-UNORDERED-NEXT: [[ARRAYIDXB1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]] ; CHECK-UNORDERED-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDXB1]], align 4 ; CHECK-UNORDERED-NEXT: [[ADD1]] = fadd float [[TMP21]], [[ADD_PHI2]] -; CHECK-UNORDERED-NEXT: [[OR:%.*]] = or i64 [[IV]], 1 +; CHECK-UNORDERED-NEXT: [[OR:%.*]] = or disjoint i64 [[IV]], 1 ; CHECK-UNORDERED-NEXT: [[ARRAYIDXB2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[OR]] ; CHECK-UNORDERED-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDXB2]], align 4 ; CHECK-UNORDERED-NEXT: [[ADD2]] = fadd float [[TMP22]], [[ADD_PHI1]] @@ -696,7 +696,7 @@ define void @fadd_strict_interleave(ptr noalias nocapture readonly %a, ptr noali ; CHECK-ORDERED-NEXT: [[ARRAYIDXB1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]] ; CHECK-ORDERED-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDXB1]], align 4 ; CHECK-ORDERED-NEXT: [[ADD1]] = fadd float [[TMP17]], [[ADD_PHI2]] -; CHECK-ORDERED-NEXT: [[OR:%.*]] = or i64 [[IV]], 1 +; CHECK-ORDERED-NEXT: [[OR:%.*]] = or disjoint i64 [[IV]], 1 ; CHECK-ORDERED-NEXT: [[ARRAYIDXB2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[OR]] ; CHECK-ORDERED-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDXB2]], align 4 ; CHECK-ORDERED-NEXT: [[ADD2]] = fadd float [[TMP18]], [[ADD_PHI1]] @@ -776,7 +776,7 @@ define void @fadd_strict_interleave(ptr noalias nocapture readonly %a, ptr noali ; CHECK-ORDERED-TF-NEXT: [[ARRAYIDXB1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]] ; CHECK-ORDERED-TF-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDXB1]], align 4 ; CHECK-ORDERED-TF-NEXT: [[ADD1]] = fadd float [[TMP26]], [[ADD_PHI2]] -; CHECK-ORDERED-TF-NEXT: [[OR:%.*]] = or i64 [[IV]], 1 +; CHECK-ORDERED-TF-NEXT: [[OR:%.*]] = or disjoint i64 [[IV]], 1 ; CHECK-ORDERED-TF-NEXT: [[ARRAYIDXB2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[OR]] ; CHECK-ORDERED-TF-NEXT: [[TMP27:%.*]] = load float, ptr [[ARRAYIDXB2]], align 4 ; CHECK-ORDERED-TF-NEXT: [[ADD2]] = fadd float [[TMP27]], [[ADD_PHI1]] @@ -807,7 +807,7 @@ for.body: %arrayidxb1 = getelementptr inbounds float, ptr %b, i64 %iv %0 = load float, ptr %arrayidxb1, align 4 %add1 = fadd float %0, %add.phi2 - %or = or i64 %iv, 1 + %or = or disjoint i64 %iv, 1 %arrayidxb2 = getelementptr inbounds float, ptr %b, i64 %or %1 = load float, ptr %arrayidxb2, align 4 %add2 = fadd float %1, %add.phi1 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll index 852a5adf5d0e..33b5273217cd 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll @@ -315,7 +315,7 @@ for.body: %arrayidxb1 = getelementptr inbounds float, ptr %b, i64 %iv %0 = load float, ptr %arrayidxb1, align 4 %add1 = fadd float %0, %add.phi2 - %or = or i64 %iv, 1 + %or = or disjoint i64 %iv, 1 %arrayidxb2 = getelementptr inbounds float, ptr %b, i64 %or %1 = load float, ptr %arrayidxb2, align 4 %add2 = fadd float %1, %add.phi1 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll index 27b0c9587351..0b5058cff8d5 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll @@ -67,7 +67,7 @@ for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx0 = getelementptr inbounds [1024 x i32], [1024 x i32]* @AB, i64 0, i64 %indvars.iv %load1 = load i32, i32* %arrayidx0, align 4 - %or = or i64 %indvars.iv, 1 + %or = or disjoint i64 %indvars.iv, 1 %arrayidx1 = getelementptr inbounds [1024 x i32], [1024 x i32]* @AB, i64 0, i64 %or %load2 = load i32, i32* %arrayidx1, align 4 %add = add nsw i32 %load1, %C @@ -122,7 +122,7 @@ define void @test_array_load2_i16_store2(i32 %C, i32 %D) #1 { ; CHECK-NEXT: [[VEC_IND:%.*]] = phi [ [[TMP1]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1024 x i16], ptr @AB_i16, i64 0, [[VEC_IND]] ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call @llvm.masked.gather.nxv4i16.nxv4p0( [[TMP4]], i32 2, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison) -; CHECK-NEXT: [[TMP5:%.*]] = or [[VEC_IND]], shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) +; CHECK-NEXT: [[TMP5:%.*]] = or disjoint [[VEC_IND]], shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1024 x i16], ptr @AB_i16, i64 0, [[TMP5]] ; CHECK-NEXT: [[WIDE_MASKED_GATHER1:%.*]] = call @llvm.masked.gather.nxv4i16.nxv4p0( [[TMP6]], i32 2, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison) ; CHECK-NEXT: [[TMP7:%.*]] = sext [[WIDE_MASKED_GATHER]] to @@ -156,7 +156,7 @@ for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds [1024 x i16], [1024 x i16]* @AB_i16, i64 0, i64 %indvars.iv %0 = load i16, i16* %arrayidx, align 2 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds [1024 x i16], [1024 x i16]* @AB_i16, i64 0, i64 %1 %2 = load i16, i16* %arrayidx2, align 2 %conv = sext i16 %0 to i32 @@ -217,7 +217,7 @@ define void @test_array_load2_store2_i16(i32 noundef %C, i32 noundef %D) #1 { ; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 -; CHECK-NEXT: [[TMP7:%.*]] = or [[VEC_IND]], shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) +; CHECK-NEXT: [[TMP7:%.*]] = or disjoint [[VEC_IND]], shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP8:%.*]] = add nsw [[TMP5]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP9:%.*]] = trunc [[TMP8]] to ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1024 x i16], ptr @CD_i16, i64 0, [[VEC_IND]] @@ -248,7 +248,7 @@ for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* @AB, i64 0, i64 %indvars.iv %0 = load i32, i32* %arrayidx, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds [1024 x i32], [1024 x i32]* @AB, i64 0, i64 %1 %2 = load i32, i32* %arrayidx2, align 4 %add3 = add nsw i32 %0, %C @@ -752,7 +752,7 @@ for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv %load1 = load i32, i32* %arrayidx, align 4 - %or = or i64 %indvars.iv, 1 + %or = or disjoint i64 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %or %load2 = load i32, i32* %arrayidx2, align 4 %mul = mul nsw i32 %load2, %load1 @@ -1491,17 +1491,17 @@ define void @PR34743(i16* %a, i32* %b, i64 %n) #1 { ; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw [[VEC_IND]], shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP17:%.*]] = add nuw nsw [[VEC_IND]], shufflevector ( insertelement ( poison, i64 2, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i16, ptr [[A]], [[TMP16]] -; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call @llvm.masked.gather.nxv4i16.nxv4p0( [[TMP18]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison), !alias.scope !34 +; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call @llvm.masked.gather.nxv4i16.nxv4p0( [[TMP18]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison), !alias.scope [[META34:![0-9]+]] ; CHECK-NEXT: [[TMP19:%.*]] = sext [[WIDE_MASKED_GATHER]] to ; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i16, ptr [[A]], [[TMP17]] -; CHECK-NEXT: [[WIDE_MASKED_GATHER4]] = call @llvm.masked.gather.nxv4i16.nxv4p0( [[TMP20]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison), !alias.scope !34 +; CHECK-NEXT: [[WIDE_MASKED_GATHER4]] = call @llvm.masked.gather.nxv4i16.nxv4p0( [[TMP20]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison), !alias.scope [[META34]] ; CHECK-NEXT: [[TMP21:%.*]] = call @llvm.experimental.vector.splice.nxv4i16( [[VECTOR_RECUR]], [[WIDE_MASKED_GATHER4]], i32 -1) ; CHECK-NEXT: [[TMP22:%.*]] = sext [[TMP21]] to ; CHECK-NEXT: [[TMP23:%.*]] = sext [[WIDE_MASKED_GATHER4]] to ; CHECK-NEXT: [[TMP24:%.*]] = mul nsw [[TMP22]], [[TMP19]] ; CHECK-NEXT: [[TMP25:%.*]] = mul nsw [[TMP24]], [[TMP23]] ; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]] -; CHECK-NEXT: store [[TMP25]], ptr [[TMP26]], align 4, !alias.scope !37, !noalias !34 +; CHECK-NEXT: store [[TMP25]], ptr [[TMP26]], align 4, !alias.scope [[META37:![0-9]+]], !noalias [[META34]] ; CHECK-NEXT: [[TMP27:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP28:%.*]] = shl nuw nsw i64 [[TMP27]], 2 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP28]] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll index ae3abba27be5..56e2fe6e15b7 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll @@ -179,7 +179,7 @@ if.then: %mul = shl nuw nsw i32 %ix.024, 1 %arrayidx = getelementptr inbounds i8, ptr %p, i32 %mul %0 = load i8, ptr %arrayidx, align 1 - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx4 = getelementptr inbounds i8, ptr %p, i32 %add %1 = load i8, ptr %arrayidx4, align 1 %cmp.i = icmp slt i8 %0, %1 @@ -345,7 +345,7 @@ for.body: br i1 %cmp1, label %if.then, label %for.inc if.then: - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx3 = getelementptr inbounds i8, ptr %q, i32 %add store i8 2, ptr %arrayidx3, align 1 br label %for.inc @@ -532,7 +532,7 @@ if.end: br i1 %cmp4, label %if.then6, label %for.inc if.then6: - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx7 = getelementptr inbounds i8, ptr %q, i32 %add store i8 2, ptr %arrayidx7, align 1 br label %for.inc diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll index e3f7cd88848e..1dfa7f8fe18b 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll @@ -328,7 +328,7 @@ for.body: ; preds = %entry, %for.body %mul1 = mul nuw nsw i64 %i.021, 3 %arrayidx2 = getelementptr inbounds float, ptr %dst, i64 %mul1 store float %0, ptr %arrayidx2, align 4 - %add = or i64 %mul, 1 + %add = or disjoint i64 %mul, 1 %arrayidx4 = getelementptr inbounds float, ptr %src, i64 %add %1 = load float, ptr %arrayidx4, align 4 %add6 = add nuw nsw i64 %mul1, 1 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll index 136561dcacd1..b36a10b46734 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll @@ -22,7 +22,7 @@ define void @vector_reverse_f64(i64 %N, ptr noalias %a, ptr noalias %b) #0{ ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 4 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]] -; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] +; CHECK-NEXT: [[N_VEC:%.*]] = sub nsw i64 [[N]], [[N_MOD_VF]] ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -124,7 +124,7 @@ define void @vector_reverse_i64(i64 %N, ptr %a, ptr %b) #0 { ; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP5]], 4 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP6]] -; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] +; CHECK-NEXT: [[N_VEC:%.*]] = sub nsw i64 [[N]], [[N_MOD_VF]] ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args.ll b/llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args.ll new file mode 100644 index 000000000000..cd133371f66c --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args.ll @@ -0,0 +1,253 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter "call" --version 2 +; RUN: opt < %s -passes=loop-vectorize -force-vector-interleave=1 -S | FileCheck %s --check-prefixes=NEON +; RUN: opt < %s -mattr=+sve -passes=loop-vectorize -force-vector-interleave=1 -S | FileCheck %s --check-prefixes=SVE_OR_NEON +; RUN: opt < %s -mattr=+sve -passes=loop-vectorize -force-vector-interleave=1 -S -prefer-predicate-over-epilogue=predicate-dont-vectorize | FileCheck %s --check-prefixes=SVE_TF + +target triple = "aarch64-unknown-linux-gnu" + +; A call whose argument can remain a scalar because it's sequential and only the +; starting value is required. +define void @test_linear8(ptr noalias %a, ptr readnone %b, i64 %n) { +; NEON-LABEL: define void @test_linear8 +; NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], i64 [[N:%.*]]) { +; NEON: [[DATA:%.*]] = call i64 @foo(ptr [[GEPB:%.*]]) #[[ATTR0:[0-9]+]] +; +; SVE_OR_NEON-LABEL: define void @test_linear8 +; SVE_OR_NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; SVE_OR_NEON: [[DATA:%.*]] = call i64 @foo(ptr [[GEPB:%.*]]) #[[ATTR1:[0-9]+]] +; +; SVE_TF-LABEL: define void @test_linear8 +; SVE_TF-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; SVE_TF: [[DATA:%.*]] = call i64 @foo(ptr [[GEPB:%.*]]) #[[ATTR1:[0-9]+]] +; +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %gepb = getelementptr i64, ptr %b, i64 %indvars.iv + %data = call i64 @foo(ptr %gepb) #0 + %gepa = getelementptr inbounds i64, ptr %a, i64 %indvars.iv + store i64 %data, ptr %gepa + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, %n + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: + ret void +} + +define void @test_vector_linear4(ptr noalias %a, ptr readnone %b, ptr readonly %c, i64 %n) { +; NEON-LABEL: define void @test_vector_linear4 +; NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], ptr readonly [[C:%.*]], i64 [[N:%.*]]) { +; NEON: [[DATA:%.*]] = call i32 @baz(i32 [[INPUT:%.*]], ptr [[GEPB:%.*]]) #[[ATTR1:[0-9]+]] +; +; SVE_OR_NEON-LABEL: define void @test_vector_linear4 +; SVE_OR_NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], ptr readonly [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_OR_NEON: [[DATA:%.*]] = call i32 @baz(i32 [[INPUT:%.*]], ptr [[GEPB:%.*]]) #[[ATTR2:[0-9]+]] +; +; SVE_TF-LABEL: define void @test_vector_linear4 +; SVE_TF-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], ptr readonly [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_TF: [[DATA:%.*]] = call i32 @baz(i32 [[INPUT:%.*]], ptr [[GEPB:%.*]]) #[[ATTR2:[0-9]+]] +; +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %gepc = getelementptr i32, ptr %c, i64 %indvars.iv + %input = load i32, ptr %gepc, align 8 + %gepb = getelementptr i32, ptr %b, i64 %indvars.iv + %data = call i32 @baz(i32 %input, ptr %gepb) #1 + %gepa = getelementptr inbounds i32, ptr %a, i64 %indvars.iv + store i32 %data, ptr %gepa, align 8 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, %n + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: + ret void +} + +define void @test_linear8_bad_stride(ptr noalias %a, ptr readnone %b, i64 %n) { +; NEON-LABEL: define void @test_linear8_bad_stride +; NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], i64 [[N:%.*]]) { +; NEON: [[DATA:%.*]] = call i64 @foo(ptr [[GEPB:%.*]]) #[[ATTR2:[0-9]+]] +; +; SVE_OR_NEON-LABEL: define void @test_linear8_bad_stride +; SVE_OR_NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_OR_NEON: [[DATA:%.*]] = call i64 @foo(ptr [[GEPB:%.*]]) #[[ATTR3:[0-9]+]] +; +; SVE_TF-LABEL: define void @test_linear8_bad_stride +; SVE_TF-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_TF: [[DATA:%.*]] = call i64 @foo(ptr [[GEPB:%.*]]) #[[ATTR3:[0-9]+]] +; +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %gepb = getelementptr i64, ptr %b, i64 %indvars.iv + %data = call i64 @foo(ptr %gepb) #2 + %gepa = getelementptr inbounds i64, ptr %a, i64 %indvars.iv + store i64 %data, ptr %gepa + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, %n + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: + ret void +} + +define void @test_linear16_wide_stride(ptr noalias %a, ptr readnone %b, i64 %n) { +; NEON-LABEL: define void @test_linear16_wide_stride +; NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], i64 [[N:%.*]]) { +; NEON: [[DATA:%.*]] = call i64 @foo(ptr [[GEPB:%.*]]) #[[ATTR2]] +; +; SVE_OR_NEON-LABEL: define void @test_linear16_wide_stride +; SVE_OR_NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_OR_NEON: [[DATA:%.*]] = call i64 @foo(ptr [[GEPB:%.*]]) #[[ATTR3]] +; +; SVE_TF-LABEL: define void @test_linear16_wide_stride +; SVE_TF-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_TF: [[DATA:%.*]] = call i64 @foo(ptr [[GEPB:%.*]]) #[[ATTR3]] +; +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %double = mul i64 %indvars.iv, 2 + %gepb = getelementptr i64, ptr %b, i64 %double + %data = call i64 @foo(ptr %gepb) #2 + %gepa = getelementptr inbounds i64, ptr %a, i64 %indvars.iv + store i64 %data, ptr %gepa + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, %n + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: + ret void +} + +define void @test_linear4_linear8(ptr noalias %a, ptr readnone %b, ptr readonly %c, i64 %n) { +; NEON-LABEL: define void @test_linear4_linear8 +; NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], ptr readonly [[C:%.*]], i64 [[N:%.*]]) { +; NEON: [[DATA:%.*]] = call i32 @quux(ptr [[GEPC:%.*]], ptr [[GEPB:%.*]]) #[[ATTR3:[0-9]+]] +; +; SVE_OR_NEON-LABEL: define void @test_linear4_linear8 +; SVE_OR_NEON-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], ptr readonly [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_OR_NEON: [[DATA:%.*]] = call i32 @quux(ptr [[GEPC:%.*]], ptr [[GEPB:%.*]]) #[[ATTR4:[0-9]+]] +; +; SVE_TF-LABEL: define void @test_linear4_linear8 +; SVE_TF-SAME: (ptr noalias [[A:%.*]], ptr readnone [[B:%.*]], ptr readonly [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_TF: [[DATA:%.*]] = call i32 @quux(ptr [[GEPC:%.*]], ptr [[GEPB:%.*]]) #[[ATTR4:[0-9]+]] +; +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %gepc = getelementptr i32, ptr %c, i64 %indvars.iv + %gepb = getelementptr i64, ptr %b, i64 %indvars.iv + %data = call i32 @quux(ptr %gepc, ptr %gepb) #3 + %gepa = getelementptr inbounds i32, ptr %a, i64 %indvars.iv + store i32 %data, ptr %gepa, align 8 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, %n + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: + ret void +} + +define void @test_linear3_non_ptr(ptr noalias %a, i64 %n) { +; NEON-LABEL: define void @test_linear3_non_ptr +; NEON-SAME: (ptr noalias [[A:%.*]], i64 [[N:%.*]]) { +; NEON: [[DATA:%.*]] = call i32 @bar(i32 [[TREBLED:%.*]]) #[[ATTR4:[0-9]+]] +; +; SVE_OR_NEON-LABEL: define void @test_linear3_non_ptr +; SVE_OR_NEON-SAME: (ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_OR_NEON: [[DATA:%.*]] = call i32 @bar(i32 [[TREBLED:%.*]]) #[[ATTR5:[0-9]+]] +; +; SVE_TF-LABEL: define void @test_linear3_non_ptr +; SVE_TF-SAME: (ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_TF: [[DATA:%.*]] = call i32 @bar(i32 [[TREBLED:%.*]]) #[[ATTR5:[0-9]+]] +; +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %little.iv = trunc i64 %indvars.iv to i32 + %trebled = mul i32 %little.iv, 3 + %data = call i32 @bar(i32 %trebled) #4 + %gepa = getelementptr inbounds i32, ptr %a, i64 %indvars.iv + store i32 %data, ptr %gepa + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, %n + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: + ret void +} + +define void @test_linearn5_non_ptr_neg_stride(ptr noalias %a, i64 %n) { +; NEON-LABEL: define void @test_linearn5_non_ptr_neg_stride +; NEON-SAME: (ptr noalias [[A:%.*]], i64 [[N:%.*]]) { +; NEON: [[DATA:%.*]] = call i32 @bar(i32 [[NEGSTRIDE:%.*]]) #[[ATTR5:[0-9]+]] +; +; SVE_OR_NEON-LABEL: define void @test_linearn5_non_ptr_neg_stride +; SVE_OR_NEON-SAME: (ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_OR_NEON: [[DATA:%.*]] = call i32 @bar(i32 [[NEGSTRIDE:%.*]]) #[[ATTR6:[0-9]+]] +; +; SVE_TF-LABEL: define void @test_linearn5_non_ptr_neg_stride +; SVE_TF-SAME: (ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; SVE_TF: [[DATA:%.*]] = call i32 @bar(i32 [[NEGSTRIDE:%.*]]) #[[ATTR6:[0-9]+]] +; +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %little.iv = trunc i64 %indvars.iv to i32 + %negstride = mul i32 %little.iv, -5 + %data = call i32 @bar(i32 %negstride) #5 + %gepa = getelementptr inbounds i32, ptr %a, i64 %indvars.iv + store i32 %data, ptr %gepa + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, %n + br i1 %exitcond, label %for.cond.cleanup, label %for.body + +for.cond.cleanup: + ret void +} + +declare i64 @foo(ptr) +declare i32 @baz(i32, ptr) +declare i32 @quux(ptr, ptr) +declare i32 @bar(i32) + +; neon vector variants of foo +declare <2 x i64> @vec_foo_linear8_nomask_neon(ptr) +declare <2 x i64> @vec_foo_linear16_nomask_neon(ptr) +declare <4 x i32> @vec_baz_vector_linear4_nomask_neon(<4 x i32>, ptr) +declare <4 x i32> @vec_quux_linear4_linear8_nomask_neon(ptr, ptr) +declare <4 x i32> @vec_bar_linear3_nomask_neon(i32) +declare <4 x i32> @vec_bar_linearn5_nomask_neon(i32) + +; scalable vector variants of foo +declare @vec_foo_linear8_mask_sve(ptr, ) +declare @vec_foo_linear8_nomask_sve(ptr) +declare @vec_foo_linear16_nomask_sve(ptr) +declare @vec_baz_vector_linear4_nomask_sve(, ptr) +declare @vec_quux_linear4_linear8_mask_sve(ptr, ptr, ) +declare @vec_bar_linear3_nomask_sve(i32) +declare @vec_bar_linearn5_nomask_sve(i32) + +attributes #0 = { nounwind "vector-function-abi-variant"="_ZGVsNxl8_foo(vec_foo_linear8_nomask_sve),_ZGVsMxl8_foo(vec_foo_linear8_mask_sve),_ZGVnN2l8_foo(vec_foo_linear8_nomask_neon)" } +attributes #1 = { nounwind "vector-function-abi-variant"="_ZGVsNxvl4_baz(vec_baz_vector_linear4_nomask_sve),_ZGVnN4vl4_baz(vec_baz_vector_linear4_nomask_neon)" } +attributes #2 = { nounwind "vector-function-abi-variant"="_ZGVsNxl16_foo(vec_foo_linear16_nomask_sve),_ZGVnN2l16_foo(vec_foo_linear16_nomask_neon)" } +attributes #3 = { nounwind "vector-function-abi-variant"="_ZGVsMxl4l8_quux(vec_quux_linear4_linear8_mask_sve),_ZGVnN4l4l8_quux(vec_quux_linear4_linear8_nomask_neon)" } +attributes #4 = { nounwind "vector-function-abi-variant"="_ZGVsNxl3_bar(vec_bar_linear3_nomask_sve),_ZGVnN4l3_bar(vec_bar_linear3_nomask_neon)" } +attributes #5 = { nounwind "vector-function-abi-variant"="_ZGVsNxln5_bar(vec_bar_linearn5_nomask_sve),_ZGVnN4ln5_bar(vec_bar_linearn5_nomask_neon)" } diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll b/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll index 195826300e39..bf30e41d5573 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll @@ -26,7 +26,7 @@ define void @vector_reverse_mask_v4i1(ptr noalias %a, ptr noalias %cond, i64 %N) ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[N]], -8 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[N]], 9223372036854775800 ; CHECK-NEXT: [[IND_END:%.*]] = and i64 [[N]], 7 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll index 794c1364356c..1dd0347e4d28 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll @@ -53,7 +53,7 @@ define i64 @add_i32_i64(ptr nocapture readonly %x, i32 %n) #0 { ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], -4 +; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -118,7 +118,7 @@ define i64 @add_i16_i64(ptr nocapture readonly %x, i32 %n) #0 { ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], -4 +; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -183,7 +183,7 @@ define i64 @add_i8_i64(ptr nocapture readonly %x, i32 %n) #0 { ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], -4 +; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -244,7 +244,7 @@ define i32 @add_i32_i32(ptr nocapture readonly %x, i32 %n) #0 { ; CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP6]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 3 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 3 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -288,7 +288,7 @@ define i32 @add_i16_i32(ptr nocapture readonly %x, i32 %n) #0 { ; CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP6]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -335,7 +335,7 @@ define i32 @add_i8_i32(ptr nocapture readonly %x, i32 %n) #0 { ; CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP6]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 15 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 15 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -382,7 +382,7 @@ define signext i16 @add_i16_i16(ptr nocapture readonly %x, i32 %n) #0 { ; CHECK-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP8]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -426,7 +426,7 @@ define signext i16 @add_i8_i16(ptr nocapture readonly %x, i32 %n) #0 { ; CHECK-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP8]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 15 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 15 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -473,7 +473,7 @@ define zeroext i8 @add_i8_i8(ptr nocapture readonly %x, i32 %n) #0 { ; CHECK-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP7]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 15 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 15 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -565,7 +565,7 @@ define i64 @mla_i32_i64(ptr nocapture readonly %x, ptr nocapture readonly %y, i3 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], -4 +; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -639,7 +639,7 @@ define i64 @mla_i16_i64(ptr nocapture readonly %x, ptr nocapture readonly %y, i3 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], -8 +; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], 2147483640 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -719,7 +719,7 @@ define i64 @mla_i8_i64(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], -8 +; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N]], 2147483640 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -795,7 +795,7 @@ define i32 @mla_i32_i32(ptr nocapture readonly %x, ptr nocapture readonly %y, i3 ; CHECK-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP8]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 3 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 3 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -846,7 +846,7 @@ define i32 @mla_i16_i32(ptr nocapture readonly %x, ptr nocapture readonly %y, i3 ; CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -901,7 +901,7 @@ define i32 @mla_i8_i32(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 ; CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 15 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 15 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -956,7 +956,7 @@ define signext i16 @mla_i16_i16(ptr nocapture readonly %x, ptr nocapture readonl ; CHECK-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP11]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -1007,7 +1007,7 @@ define signext i16 @mla_i8_i16(ptr nocapture readonly %x, ptr nocapture readonly ; CHECK-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP11]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 15 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 15 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -1062,7 +1062,7 @@ define zeroext i8 @mla_i8_i8(ptr nocapture readonly %x, ptr nocapture readonly % ; CHECK-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP10]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 15 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 15 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -1323,7 +1323,7 @@ define i32 @reduction_interleave_group(i32 %n, ptr %arr) #0 { ; CHECK-NEXT: [[GUARD:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[GUARD]], label [[FOR_BODY_PREHEADER:%.*]], label [[EXIT:%.*]] ; CHECK: for.body.preheader: -; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1 +; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[N]], -1 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = add nuw i32 [[TMP1]], 1 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 7 @@ -1380,7 +1380,7 @@ entry: for.body: ; preds = %for.body.preheader, %for.body %iv = phi i32 [ %iv.next, %for.body ], [ 0, %entry ] %red.phi = phi i32 [ %red.2, %for.body ], [ 0, %entry ] - %add = or i32 %iv, 1 + %add = or disjoint i32 %iv, 1 %gep.0 = getelementptr inbounds i32, ptr %arr, i32 %add %l.0 = load i32, ptr %gep.0, align 4 %gep.1 = getelementptr inbounds i32, ptr %arr, i32 %iv @@ -1403,7 +1403,7 @@ define i32 @mla_i8_i32_multiuse(ptr nocapture readonly %x, ptr nocapture readonl ; CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 15 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 15 ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: diff --git a/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll index 5694367dd1f9..bc5f137564b3 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll @@ -268,6 +268,84 @@ loop.exit: ret void } +define void @drop_zext_nneg(ptr noalias %p, ptr noalias %p1) #0 { +; CHECK-LABEL: define void @drop_zext_nneg( +; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[P1:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; CHECK: vector.scevcheck: +; CHECK-NEXT: br i1 true, label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq <4 x i32> [[VEC_IND]], zeroinitializer +; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i32> [[VEC_IND]] to <4 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[TMP3]], i32 0 +; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr [[TMP4]], i32 8, <4 x i1> [[TMP0]], <4 x double> poison) +; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i1> [[TMP0]], +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP5]], <4 x double> zeroinitializer, <4 x double> [[WIDE_MASKED_LOAD]] +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[PREDPHI]], i32 3 +; CHECK-NEXT: store double [[TMP6]], ptr [[P1]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0 +; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 0, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: br label [[BODY:%.*]] +; CHECK: body: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[NEXT:%.*]], [[ELSE:%.*]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[IV]] to i32 +; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[TMP8]], 0 +; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE]] +; CHECK: then: +; CHECK-NEXT: [[ZEXT:%.*]] = zext nneg i32 [[TMP8]] to i64 +; CHECK-NEXT: [[IDX1:%.*]] = getelementptr double, ptr [[P]], i64 [[ZEXT]] +; CHECK-NEXT: [[IDX2:%.*]] = getelementptr double, ptr [[P]], i64 [[ZEXT]] +; CHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[IDX2]], align 8 +; CHECK-NEXT: br label [[ELSE]] +; CHECK: else: +; CHECK-NEXT: [[PHI:%.*]] = phi double [ [[TMP9]], [[THEN]] ], [ 0.000000e+00, [[BODY]] ] +; CHECK-NEXT: store double [[PHI]], ptr [[P1]], align 8 +; CHECK-NEXT: [[NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[NEXT]], 0 +; CHECK-NEXT: br i1 [[CMP]], label [[EXIT]], label [[BODY]], !llvm.loop [[LOOP18:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %body + +body: + %iv = phi i64 [ %next, %else ], [ 0, %entry ] + %0 = trunc i64 %iv to i32 + %c = icmp eq i32 %0, 0 + br i1 %c, label %then, label %else + +then: + %zext = zext nneg i32 %0 to i64 + %idx1 = getelementptr double, ptr %p, i64 %zext + %idx2 = getelementptr double, ptr %p, i64 %zext + %1 = load double, ptr %idx2, align 8 + br label %else + +else: + %phi = phi double [ %1, %then ], [ 0.000000e+00, %body ] + store double %phi, ptr %p1, align 8 + %next = add i64 %iv, 1 + %cmp = icmp eq i64 %next, 0 + br i1 %cmp, label %exit, label %body + +exit: + ret void +} + ; Preserve poison-generating flags from 'sdiv' and 'getelementptr' feeding a masked gather. define void @preserve_vector_exact_no_addr(ptr noalias nocapture readonly %input, ptr %output) local_unnamed_addr #0 { diff --git a/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll b/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll index 2467d3acbc6c..1e029ba15904 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll @@ -181,7 +181,7 @@ for.body: ; preds = %for.body, %entry %0 = shl nsw i64 %indvars.iv, 1 %arrayidx = getelementptr inbounds i32, ptr %b, i64 %0 %1 = load i32, ptr %arrayidx, align 4 - %2 = or i64 %0, 1 + %2 = or disjoint i64 %0, 1 %arrayidx3 = getelementptr inbounds i32, ptr %b, i64 %2 %3 = load i32, ptr %arrayidx3, align 4 %add4 = add nsw i32 %3, %1 diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr47437.ll b/llvm/test/Transforms/LoopVectorize/X86/pr47437.ll index 7ace7fd2c099..4fa65af14270 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/pr47437.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/pr47437.ll @@ -61,7 +61,7 @@ define void @test_muladd(ptr noalias nocapture %d1, ptr noalias nocapture readon ; SSE2-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2 ; SSE2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP18]] to i32 ; SSE2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[CONV5]], [[CONV]] -; SSE2-NEXT: [[TMP19:%.*]] = or i64 [[TMP16]], 1 +; SSE2-NEXT: [[TMP19:%.*]] = or disjoint i64 [[TMP16]], 1 ; SSE2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, ptr [[S1]], i64 [[TMP19]] ; SSE2-NEXT: [[TMP20:%.*]] = load i16, ptr [[ARRAYIDX10]], align 2 ; SSE2-NEXT: [[CONV11:%.*]] = sext i16 [[TMP20]] to i32 @@ -74,7 +74,7 @@ define void @test_muladd(ptr noalias nocapture %d1, ptr noalias nocapture readon ; SSE2-NEXT: store i32 [[ADD18]], ptr [[ARRAYIDX20]], align 4 ; SSE2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; SSE2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] -; SSE2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] +; SSE2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; SSE2: for.end.loopexit: ; SSE2-NEXT: br label [[FOR_END]] ; SSE2: for.end: @@ -157,7 +157,7 @@ define void @test_muladd(ptr noalias nocapture %d1, ptr noalias nocapture readon ; SSE41-NEXT: [[TMP33:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2 ; SSE41-NEXT: [[CONV5:%.*]] = sext i16 [[TMP33]] to i32 ; SSE41-NEXT: [[MUL6:%.*]] = mul nsw i32 [[CONV5]], [[CONV]] -; SSE41-NEXT: [[TMP34:%.*]] = or i64 [[TMP31]], 1 +; SSE41-NEXT: [[TMP34:%.*]] = or disjoint i64 [[TMP31]], 1 ; SSE41-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, ptr [[S1]], i64 [[TMP34]] ; SSE41-NEXT: [[TMP35:%.*]] = load i16, ptr [[ARRAYIDX10]], align 2 ; SSE41-NEXT: [[CONV11:%.*]] = sext i16 [[TMP35]] to i32 @@ -170,7 +170,7 @@ define void @test_muladd(ptr noalias nocapture %d1, ptr noalias nocapture readon ; SSE41-NEXT: store i32 [[ADD18]], ptr [[ARRAYIDX20]], align 4 ; SSE41-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; SSE41-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] -; SSE41-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] +; SSE41-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; SSE41: for.end.loopexit: ; SSE41-NEXT: br label [[FOR_END]] ; SSE41: for.end: @@ -297,7 +297,7 @@ define void @test_muladd(ptr noalias nocapture %d1, ptr noalias nocapture readon ; AVX1-NEXT: [[TMP63:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2 ; AVX1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP63]] to i32 ; AVX1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[CONV5]], [[CONV]] -; AVX1-NEXT: [[TMP64:%.*]] = or i64 [[TMP61]], 1 +; AVX1-NEXT: [[TMP64:%.*]] = or disjoint i64 [[TMP61]], 1 ; AVX1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, ptr [[S1]], i64 [[TMP64]] ; AVX1-NEXT: [[TMP65:%.*]] = load i16, ptr [[ARRAYIDX10]], align 2 ; AVX1-NEXT: [[CONV11:%.*]] = sext i16 [[TMP65]] to i32 @@ -310,7 +310,7 @@ define void @test_muladd(ptr noalias nocapture %d1, ptr noalias nocapture readon ; AVX1-NEXT: store i32 [[ADD18]], ptr [[ARRAYIDX20]], align 4 ; AVX1-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; AVX1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] -; AVX1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] +; AVX1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; AVX1: for.end.loopexit: ; AVX1-NEXT: br label [[FOR_END]] ; AVX1: for.end: @@ -371,7 +371,7 @@ define void @test_muladd(ptr noalias nocapture %d1, ptr noalias nocapture readon ; AVX2-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2 ; AVX2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP18]] to i32 ; AVX2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[CONV5]], [[CONV]] -; AVX2-NEXT: [[TMP19:%.*]] = or i64 [[TMP16]], 1 +; AVX2-NEXT: [[TMP19:%.*]] = or disjoint i64 [[TMP16]], 1 ; AVX2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, ptr [[S1]], i64 [[TMP19]] ; AVX2-NEXT: [[TMP20:%.*]] = load i16, ptr [[ARRAYIDX10]], align 2 ; AVX2-NEXT: [[CONV11:%.*]] = sext i16 [[TMP20]] to i32 @@ -384,7 +384,7 @@ define void @test_muladd(ptr noalias nocapture %d1, ptr noalias nocapture readon ; AVX2-NEXT: store i32 [[ADD18]], ptr [[ARRAYIDX20]], align 4 ; AVX2-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; AVX2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] -; AVX2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] +; AVX2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; AVX2: for.end.loopexit: ; AVX2-NEXT: br label [[FOR_END]] ; AVX2: for.end: @@ -408,7 +408,7 @@ for.body: %2 = load i16, ptr %arrayidx4, align 2 %conv5 = sext i16 %2 to i32 %mul6 = mul nsw i32 %conv5, %conv - %3 = or i64 %0, 1 + %3 = or disjoint i64 %0, 1 %arrayidx10 = getelementptr inbounds i16, ptr %s1, i64 %3 %4 = load i16, ptr %arrayidx10, align 2 %conv11 = sext i16 %4 to i32 diff --git a/llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll b/llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll index 631738b0bd67..bf2b9e2aef85 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll @@ -24,7 +24,7 @@ define void @_Z3fn1v() #0 { ; CHECK-NEXT: [[TMP12:%.*]] = add nsw <16 x i64> [[TMP10]], [[VEC_IND3]] ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [10 x i32], <16 x ptr> [[TMP11]], <16 x i64> [[TMP12]], i64 0 ; CHECK-NEXT: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> , <16 x ptr> [[TMP13]], i32 16, <16 x i1> ) -; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i64> [[VEC_IND3]], +; CHECK-NEXT: [[TMP14:%.*]] = or disjoint <16 x i64> [[VEC_IND3]], ; CHECK-NEXT: [[TMP15:%.*]] = add nsw <16 x i64> [[TMP10]], [[TMP14]] ; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [10 x i32], <16 x ptr> [[TMP11]], <16 x i64> [[TMP15]], i64 0 ; CHECK-NEXT: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> , <16 x ptr> [[TMP16]], i32 8, <16 x i1> ) @@ -64,7 +64,7 @@ for.body.us: ; preds = %for.body.us.prehead for.body5.us.us48.preheader: ; preds = %for.body.us store i32 8, ptr %arraydecay.us.us.us, align 16 - %indvars.iv.next66 = or i64 %indvars.iv70, 1 + %indvars.iv.next66 = or disjoint i64 %indvars.iv70, 1 %6 = add nsw i64 %4, %indvars.iv.next66 %arraydecay.us.us55.1 = getelementptr inbounds [10 x i32], ptr %add.ptr.us, i64 %6, i64 0 store i32 8, ptr %arraydecay.us.us55.1, align 8 @@ -72,7 +72,7 @@ for.body5.us.us48.preheader: ; preds = %for.body.us for.body5.us.us.us.preheader: ; preds = %for.body.us store i32 7, ptr %arraydecay.us.us.us, align 16 - %indvars.iv.next73 = or i64 %indvars.iv70, 1 + %indvars.iv.next73 = or disjoint i64 %indvars.iv70, 1 %7 = add nsw i64 %4, %indvars.iv.next73 %arraydecay.us.us.us.1 = getelementptr inbounds [10 x i32], ptr %add.ptr.us, i64 %7, i64 0 store i32 7, ptr %arraydecay.us.us.us.1, align 8 @@ -101,7 +101,7 @@ for.body: ; preds = %for.body.preheader, %9 = add nsw i64 %8, %indvars.iv87 %arraydecay.us31 = getelementptr inbounds [10 x i32], ptr %add.ptr, i64 %9, i64 0 store i32 8, ptr %arraydecay.us31, align 16 - %indvars.iv.next90 = or i64 %indvars.iv87, 1 + %indvars.iv.next90 = or disjoint i64 %indvars.iv87, 1 %10 = add nsw i64 %8, %indvars.iv.next90 %arraydecay.us31.1 = getelementptr inbounds [10 x i32], ptr %add.ptr, i64 %10, i64 0 store i32 8, ptr %arraydecay.us31.1, align 8 diff --git a/llvm/test/Transforms/LoopVectorize/X86/small-size.ll b/llvm/test/Transforms/LoopVectorize/X86/small-size.ll index 23b22b7a7ebf..fcd41fd188ce 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/small-size.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/small-size.ll @@ -75,9 +75,9 @@ define void @example2(i32 %n, i32 %x) optsize { ; CHECK: .lr.ph5.preheader: ; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[N_RND_UP:%.*]] = add nuw nsw i64 [[TMP2]], 3 -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[N_RND_UP]], 8589934588 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[N_RND_UP]], 4294967292 ; CHECK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i64 [[TMP2]], -1 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer @@ -126,7 +126,7 @@ define void @example2(i32 %n, i32 %x) optsize { ; CHECK: scalar.ph: ; CHECK-NEXT: br label [[DOTLR_PH5:%.*]] ; CHECK: ..preheader_crit_edge: -; CHECK-NEXT: [[PHITMP:%.*]] = sext i32 [[N]] to i64 +; CHECK-NEXT: [[PHITMP:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: br label [[DOTPREHEADER]] ; CHECK: .preheader: ; CHECK-NEXT: [[I_0_LCSSA:%.*]] = phi i64 [ [[PHITMP]], [[DOT_PREHEADER_CRIT_EDGE]] ], [ 0, [[TMP0:%.*]] ] diff --git a/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll b/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll index 95b337944853..8633d5e834cc 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll @@ -388,9 +388,9 @@ define dso_local void @masked_strided1_optsize_unknown_tc(ptr noalias nocapture ; DISABLED_MASKED_STRIDED-NEXT: br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; DISABLED_MASKED_STRIDED: vector.ph: ; DISABLED_MASKED_STRIDED-NEXT: [[CONV:%.*]] = zext i8 [[GUARD:%.*]] to i32 -; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; DISABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i32> poison, i32 [[CONV]], i64 0 @@ -498,9 +498,9 @@ define dso_local void @masked_strided1_optsize_unknown_tc(ptr noalias nocapture ; ENABLED_MASKED_STRIDED-NEXT: br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; ENABLED_MASKED_STRIDED: vector.ph: ; ENABLED_MASKED_STRIDED-NEXT: [[CONV:%.*]] = zext i8 [[GUARD:%.*]] to i32 -; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; ENABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i32> poison, i32 [[CONV]], i64 0 @@ -592,9 +592,9 @@ define dso_local void @masked_strided3_optsize_unknown_tc(ptr noalias nocapture ; DISABLED_MASKED_STRIDED-NEXT: br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; DISABLED_MASKED_STRIDED: vector.ph: ; DISABLED_MASKED_STRIDED-NEXT: [[CONV:%.*]] = zext i8 [[GUARD:%.*]] to i32 -; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; DISABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i32> poison, i32 [[CONV]], i64 0 @@ -702,9 +702,9 @@ define dso_local void @masked_strided3_optsize_unknown_tc(ptr noalias nocapture ; ENABLED_MASKED_STRIDED-NEXT: br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; ENABLED_MASKED_STRIDED: vector.ph: ; ENABLED_MASKED_STRIDED-NEXT: [[CONV:%.*]] = zext i8 [[GUARD:%.*]] to i32 -; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; ENABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i32> poison, i32 [[CONV]], i64 0 @@ -896,9 +896,9 @@ define dso_local void @unconditional_strided1_optsize_unknown_tc(ptr noalias noc ; DISABLED_MASKED_STRIDED-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; DISABLED_MASKED_STRIDED-NEXT: br i1 [[CMP6]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; DISABLED_MASKED_STRIDED: vector.ph: -; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; DISABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; DISABLED_MASKED_STRIDED-NEXT: br label [[VECTOR_BODY:%.*]] @@ -1001,9 +1001,9 @@ define dso_local void @unconditional_strided1_optsize_unknown_tc(ptr noalias noc ; ENABLED_MASKED_STRIDED-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; ENABLED_MASKED_STRIDED-NEXT: br i1 [[CMP6]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; ENABLED_MASKED_STRIDED: vector.ph: -; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; ENABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: br label [[VECTOR_BODY:%.*]] @@ -1446,7 +1446,7 @@ if.then: %mul = shl nuw nsw i32 %ix.024, 1 %arrayidx = getelementptr inbounds i8, ptr %p, i32 %mul %0 = load i8, ptr %arrayidx, align 1 - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx4 = getelementptr inbounds i8, ptr %p, i32 %add %1 = load i8, ptr %arrayidx4, align 1 %cmp.i = icmp slt i8 %0, %1 @@ -2148,7 +2148,7 @@ if.then: %mul = shl nuw nsw i32 %ix.024, 1 %arrayidx = getelementptr inbounds i8, ptr %p, i32 %mul %0 = load i8, ptr %arrayidx, align 1 - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx4 = getelementptr inbounds i8, ptr %p, i32 %add %1 = load i8, ptr %arrayidx4, align 1 %cmp.i = icmp slt i8 %0, %1 @@ -2201,9 +2201,9 @@ define dso_local void @masked_strided2_unknown_tc(ptr noalias nocapture readonly ; DISABLED_MASKED_STRIDED-NEXT: [[CMP22:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; DISABLED_MASKED_STRIDED-NEXT: br i1 [[CMP22]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; DISABLED_MASKED_STRIDED: vector.ph: -; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; DISABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i32> poison, i32 [[GUARD:%.*]], i64 0 @@ -2535,9 +2535,9 @@ define dso_local void @masked_strided2_unknown_tc(ptr noalias nocapture readonly ; ENABLED_MASKED_STRIDED-NEXT: [[CMP22:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; ENABLED_MASKED_STRIDED-NEXT: br i1 [[CMP22]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; ENABLED_MASKED_STRIDED: vector.ph: -; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; ENABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i32> poison, i32 [[GUARD:%.*]], i64 0 @@ -2585,7 +2585,7 @@ if.then: %mul = shl nuw nsw i32 %ix.023, 1 %arrayidx = getelementptr inbounds i8, ptr %p, i32 %mul %0 = load i8, ptr %arrayidx, align 1 - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx3 = getelementptr inbounds i8, ptr %p, i32 %add %1 = load i8, ptr %arrayidx3, align 1 %cmp.i = icmp slt i8 %0, %1 @@ -2641,9 +2641,9 @@ define dso_local void @unconditional_masked_strided2_unknown_tc(ptr noalias noca ; DISABLED_MASKED_STRIDED-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; DISABLED_MASKED_STRIDED-NEXT: br i1 [[CMP20]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; DISABLED_MASKED_STRIDED: vector.ph: -; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; DISABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; DISABLED_MASKED_STRIDED-NEXT: br label [[VECTOR_BODY:%.*]] @@ -2971,9 +2971,9 @@ define dso_local void @unconditional_masked_strided2_unknown_tc(ptr noalias noca ; ENABLED_MASKED_STRIDED-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; ENABLED_MASKED_STRIDED-NEXT: br i1 [[CMP20]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; ENABLED_MASKED_STRIDED: vector.ph: -; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 7 +; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw i32 [[N]], 7 ; ENABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8 -; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add i32 [[N]], -1 +; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i32 [[N]], -1 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i32> poison, i32 [[TRIP_COUNT_MINUS_1]], i64 0 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT]], <8 x i32> poison, <8 x i32> zeroinitializer ; ENABLED_MASKED_STRIDED-NEXT: br label [[VECTOR_BODY:%.*]] @@ -3014,7 +3014,7 @@ for.body: %mul = shl nuw nsw i32 %ix.021, 1 %arrayidx = getelementptr inbounds i8, ptr %p, i32 %mul %0 = load i8, ptr %arrayidx, align 1 - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx2 = getelementptr inbounds i8, ptr %p, i32 %add %1 = load i8, ptr %arrayidx2, align 1 %cmp.i = icmp slt i8 %0, %1 diff --git a/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll b/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll index 53eab9c649b4..ffe4e13b187a 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll @@ -103,7 +103,7 @@ for.body: store i16 %0, ptr %arrayidx2, align 2 %arrayidx4 = getelementptr inbounds i16, ptr %y, i64 %indvars.iv %2 = load i16, ptr %arrayidx4, align 2 - %3 = or i64 %1, 1 + %3 = or disjoint i64 %1, 1 %arrayidx7 = getelementptr inbounds i16, ptr %points, i64 %3 store i16 %2, ptr %arrayidx7, align 2 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 @@ -130,9 +130,9 @@ define dso_local void @test2(ptr noalias nocapture %points, i32 %numPoints, ptr ; DISABLED_MASKED_STRIDED-NEXT: [[CMP15:%.*]] = icmp sgt i32 [[NUMPOINTS:%.*]], 0 ; DISABLED_MASKED_STRIDED-NEXT: br i1 [[CMP15]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; DISABLED_MASKED_STRIDED: vector.ph: -; DISABLED_MASKED_STRIDED-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[NUMPOINTS]] to i64 +; DISABLED_MASKED_STRIDED-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[NUMPOINTS]] to i64 ; DISABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw nsw i64 [[WIDE_TRIP_COUNT]], 3 -; DISABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i64 [[N_RND_UP]], 8589934588 +; DISABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i64 [[N_RND_UP]], 4294967292 ; DISABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i64 [[WIDE_TRIP_COUNT]], -1 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0 ; DISABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer @@ -233,9 +233,9 @@ define dso_local void @test2(ptr noalias nocapture %points, i32 %numPoints, ptr ; ENABLED_MASKED_STRIDED-NEXT: [[CMP15:%.*]] = icmp sgt i32 [[NUMPOINTS:%.*]], 0 ; ENABLED_MASKED_STRIDED-NEXT: br i1 [[CMP15]], label [[VECTOR_PH:%.*]], label [[FOR_END:%.*]] ; ENABLED_MASKED_STRIDED: vector.ph: -; ENABLED_MASKED_STRIDED-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[NUMPOINTS]] to i64 +; ENABLED_MASKED_STRIDED-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[NUMPOINTS]] to i64 ; ENABLED_MASKED_STRIDED-NEXT: [[N_RND_UP:%.*]] = add nuw nsw i64 [[WIDE_TRIP_COUNT]], 3 -; ENABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i64 [[N_RND_UP]], 8589934588 +; ENABLED_MASKED_STRIDED-NEXT: [[N_VEC:%.*]] = and i64 [[N_RND_UP]], 4294967292 ; ENABLED_MASKED_STRIDED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = add nsw i64 [[WIDE_TRIP_COUNT]], -1 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0 ; ENABLED_MASKED_STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer @@ -283,7 +283,7 @@ for.body: store i16 %0, ptr %arrayidx2, align 2 %arrayidx4 = getelementptr inbounds i16, ptr %y, i64 %indvars.iv %2 = load i16, ptr %arrayidx4, align 2 - %3 = or i64 %1, 1 + %3 = or disjoint i64 %1, 1 %arrayidx7 = getelementptr inbounds i16, ptr %points, i64 %3 store i16 %2, ptr %arrayidx7, align 2 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 diff --git a/llvm/test/Transforms/LoopVectorize/float-induction.ll b/llvm/test/Transforms/LoopVectorize/float-induction.ll index 5769c9eac392..f232ac3aa698 100644 --- a/llvm/test/Transforms/LoopVectorize/float-induction.ll +++ b/llvm/test/Transforms/LoopVectorize/float-induction.ll @@ -24,11 +24,11 @@ define void @fp_iv_loop1_fast_FMF(float %init, ptr noalias nocapture %A, i32 %N) ; VEC4_INTERL1-NEXT: br i1 [[CMP4]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL1: for.body.lr.ph: ; VEC4_INTERL1-NEXT: [[FPINC:%.*]] = load float, ptr @fp_inc, align 4 -; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; VEC4_INTERL1-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL1: vector.ph: -; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; VEC4_INTERL1-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL1-NEXT: [[TMP1:%.*]] = fmul fast float [[FPINC]], [[DOTCAST]] ; VEC4_INTERL1-NEXT: [[IND_END:%.*]] = fsub fast float [[INIT:%.*]], [[TMP1]] @@ -79,11 +79,11 @@ define void @fp_iv_loop1_fast_FMF(float %init, ptr noalias nocapture %A, i32 %N) ; VEC4_INTERL2-NEXT: br i1 [[CMP4]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL2: for.body.lr.ph: ; VEC4_INTERL2-NEXT: [[FPINC:%.*]] = load float, ptr @fp_inc, align 4 -; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8 ; VEC4_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL2: vector.ph: -; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967288 +; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483640 ; VEC4_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL2-NEXT: [[TMP1:%.*]] = fmul fast float [[FPINC]], [[DOTCAST]] ; VEC4_INTERL2-NEXT: [[IND_END:%.*]] = fsub fast float [[INIT:%.*]], [[TMP1]] @@ -137,11 +137,11 @@ define void @fp_iv_loop1_fast_FMF(float %init, ptr noalias nocapture %A, i32 %N) ; VEC1_INTERL2-NEXT: br i1 [[CMP4]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC1_INTERL2: for.body.lr.ph: ; VEC1_INTERL2-NEXT: [[FPINC:%.*]] = load float, ptr @fp_inc, align 4 -; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC1_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC1_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC1_INTERL2: vector.ph: -; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967294 +; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483646 ; VEC1_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC1_INTERL2-NEXT: [[TMP1:%.*]] = fmul fast float [[FPINC]], [[DOTCAST]] ; VEC1_INTERL2-NEXT: [[IND_END:%.*]] = fsub fast float [[INIT:%.*]], [[TMP1]] @@ -188,11 +188,11 @@ define void @fp_iv_loop1_fast_FMF(float %init, ptr noalias nocapture %A, i32 %N) ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[CMP4]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC2_INTERL1_PRED_STORE: for.body.lr.ph: ; VEC2_INTERL1_PRED_STORE-NEXT: [[FPINC:%.*]] = load float, ptr @fp_inc, align 4 -; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC2_INTERL1_PRED_STORE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY:%.*]], label [[VECTOR_PH:%.*]] ; VEC2_INTERL1_PRED_STORE: vector.ph: -; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967294 +; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483646 ; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP1:%.*]] = fmul fast float [[FPINC]], [[DOTCAST]] ; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END:%.*]] = fsub fast float [[INIT:%.*]], [[TMP1]] @@ -271,11 +271,11 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, ptr noalias nocapture %A, i32 ; VEC4_INTERL1-NEXT: br i1 [[CMP4]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL1: for.body.lr.ph: ; VEC4_INTERL1-NEXT: [[FPINC:%.*]] = load float, ptr @fp_inc, align 4 -; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; VEC4_INTERL1-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL1: vector.ph: -; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; VEC4_INTERL1-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL1-NEXT: [[TMP1:%.*]] = fmul reassoc float [[FPINC]], [[DOTCAST]] ; VEC4_INTERL1-NEXT: [[IND_END:%.*]] = fsub reassoc float [[INIT:%.*]], [[TMP1]] @@ -326,11 +326,11 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, ptr noalias nocapture %A, i32 ; VEC4_INTERL2-NEXT: br i1 [[CMP4]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL2: for.body.lr.ph: ; VEC4_INTERL2-NEXT: [[FPINC:%.*]] = load float, ptr @fp_inc, align 4 -; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8 ; VEC4_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL2: vector.ph: -; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967288 +; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483640 ; VEC4_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL2-NEXT: [[TMP1:%.*]] = fmul reassoc float [[FPINC]], [[DOTCAST]] ; VEC4_INTERL2-NEXT: [[IND_END:%.*]] = fsub reassoc float [[INIT:%.*]], [[TMP1]] @@ -384,11 +384,11 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, ptr noalias nocapture %A, i32 ; VEC1_INTERL2-NEXT: br i1 [[CMP4]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC1_INTERL2: for.body.lr.ph: ; VEC1_INTERL2-NEXT: [[FPINC:%.*]] = load float, ptr @fp_inc, align 4 -; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC1_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC1_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC1_INTERL2: vector.ph: -; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967294 +; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483646 ; VEC1_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC1_INTERL2-NEXT: [[TMP1:%.*]] = fmul reassoc float [[FPINC]], [[DOTCAST]] ; VEC1_INTERL2-NEXT: [[IND_END:%.*]] = fsub reassoc float [[INIT:%.*]], [[TMP1]] @@ -437,11 +437,11 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, ptr noalias nocapture %A, i32 ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[CMP4]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC2_INTERL1_PRED_STORE: for.body.lr.ph: ; VEC2_INTERL1_PRED_STORE-NEXT: [[FPINC:%.*]] = load float, ptr @fp_inc, align 4 -; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC2_INTERL1_PRED_STORE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY:%.*]], label [[VECTOR_PH:%.*]] ; VEC2_INTERL1_PRED_STORE: vector.ph: -; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967294 +; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483646 ; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP1:%.*]] = fmul reassoc float [[FPINC]], [[DOTCAST]] ; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END:%.*]] = fsub reassoc float [[INIT:%.*]], [[TMP1]] @@ -521,11 +521,11 @@ define void @fp_iv_loop2(float %init, ptr noalias nocapture %A, i32 %N) #0 { ; VEC4_INTERL1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; VEC4_INTERL1-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL1: for.body.preheader: -; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; VEC4_INTERL1-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL1: vector.ph: -; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; VEC4_INTERL1-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL1-NEXT: [[TMP1:%.*]] = fmul fast float [[DOTCAST]], 5.000000e-01 ; VEC4_INTERL1-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP1]], [[INIT:%.*]] @@ -569,11 +569,11 @@ define void @fp_iv_loop2(float %init, ptr noalias nocapture %A, i32 %N) #0 { ; VEC4_INTERL2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; VEC4_INTERL2-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL2: for.body.preheader: -; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8 ; VEC4_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL2: vector.ph: -; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967288 +; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483640 ; VEC4_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL2-NEXT: [[TMP1:%.*]] = fmul fast float [[DOTCAST]], 5.000000e-01 ; VEC4_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP1]], [[INIT:%.*]] @@ -620,11 +620,11 @@ define void @fp_iv_loop2(float %init, ptr noalias nocapture %A, i32 %N) #0 { ; VEC1_INTERL2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; VEC1_INTERL2-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; VEC1_INTERL2: for.body.preheader: -; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC1_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC1_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC1_INTERL2: vector.ph: -; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967294 +; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483646 ; VEC1_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC1_INTERL2-NEXT: [[TMP1:%.*]] = fmul fast float [[DOTCAST]], 5.000000e-01 ; VEC1_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP1]], [[INIT:%.*]] @@ -670,11 +670,11 @@ define void @fp_iv_loop2(float %init, ptr noalias nocapture %A, i32 %N) #0 { ; VEC2_INTERL1_PRED_STORE-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; VEC2_INTERL1_PRED_STORE: for.body.preheader: -; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC2_INTERL1_PRED_STORE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY:%.*]], label [[VECTOR_PH:%.*]] ; VEC2_INTERL1_PRED_STORE: vector.ph: -; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967294 +; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483646 ; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP1:%.*]] = fmul fast float [[DOTCAST]], 5.000000e-01 ; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP1]], [[INIT:%.*]] @@ -753,11 +753,11 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca ; VEC4_INTERL1-NEXT: br i1 [[CMP9]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL1: for.body.lr.ph: ; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = load float, ptr @fp_inc, align 4 -; VEC4_INTERL1-NEXT: [[TMP1:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL1-NEXT: [[TMP1:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; VEC4_INTERL1-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL1: vector.ph: -; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 4294967292 +; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 2147483644 ; VEC4_INTERL1-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL1-NEXT: [[TMP2:%.*]] = fmul fast float [[DOTCAST]], -5.000000e-01 ; VEC4_INTERL1-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 0x3FB99999A0000000 @@ -830,11 +830,11 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca ; VEC4_INTERL2-NEXT: br i1 [[CMP9]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL2: for.body.lr.ph: ; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = load float, ptr @fp_inc, align 4 -; VEC4_INTERL2-NEXT: [[TMP1:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL2-NEXT: [[TMP1:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8 ; VEC4_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL2: vector.ph: -; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 4294967288 +; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 2147483640 ; VEC4_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL2-NEXT: [[TMP2:%.*]] = fmul fast float [[DOTCAST]], -5.000000e-01 ; VEC4_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 0x3FB99999A0000000 @@ -917,11 +917,11 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca ; VEC1_INTERL2-NEXT: br i1 [[CMP9]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC1_INTERL2: for.body.lr.ph: ; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = load float, ptr @fp_inc, align 4 -; VEC1_INTERL2-NEXT: [[TMP1:%.*]] = zext i32 [[N]] to i64 +; VEC1_INTERL2-NEXT: [[TMP1:%.*]] = zext nneg i32 [[N]] to i64 ; VEC1_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC1_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC1_INTERL2: vector.ph: -; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 4294967294 +; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 2147483646 ; VEC1_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC1_INTERL2-NEXT: [[TMP2:%.*]] = fmul fast float [[DOTCAST]], -5.000000e-01 ; VEC1_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 0x3FB99999A0000000 @@ -995,11 +995,11 @@ define void @fp_iv_loop3(float %init, ptr noalias nocapture %A, ptr noalias noca ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[CMP9]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; VEC2_INTERL1_PRED_STORE: for.body.lr.ph: ; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = load float, ptr @fp_inc, align 4 -; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP1:%.*]] = zext i32 [[N]] to i64 +; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP1:%.*]] = zext nneg i32 [[N]] to i64 ; VEC2_INTERL1_PRED_STORE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY:%.*]], label [[VECTOR_PH:%.*]] ; VEC2_INTERL1_PRED_STORE: vector.ph: -; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 4294967294 +; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP1]], 2147483646 ; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP2:%.*]] = fmul fast float [[DOTCAST]], -5.000000e-01 ; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP2]], 0x3FB99999A0000000 @@ -1108,11 +1108,11 @@ define void @fp_iv_loop4(ptr noalias nocapture %A, i32 %N) { ; VEC4_INTERL1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; VEC4_INTERL1-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL1: for.body.preheader: -; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL1-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; VEC4_INTERL1-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL1: vector.ph: -; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; VEC4_INTERL1-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL1-NEXT: [[TMP1:%.*]] = fmul fast float [[DOTCAST]], 5.000000e-01 ; VEC4_INTERL1-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP1]], 1.000000e+00 @@ -1153,11 +1153,11 @@ define void @fp_iv_loop4(ptr noalias nocapture %A, i32 %N) { ; VEC4_INTERL2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; VEC4_INTERL2-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; VEC4_INTERL2: for.body.preheader: -; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC4_INTERL2-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC4_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8 ; VEC4_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC4_INTERL2: vector.ph: -; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967288 +; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483640 ; VEC4_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC4_INTERL2-NEXT: [[TMP1:%.*]] = fmul fast float [[DOTCAST]], 5.000000e-01 ; VEC4_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP1]], 1.000000e+00 @@ -1201,11 +1201,11 @@ define void @fp_iv_loop4(ptr noalias nocapture %A, i32 %N) { ; VEC1_INTERL2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; VEC1_INTERL2-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; VEC1_INTERL2: for.body.preheader: -; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC1_INTERL2-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC1_INTERL2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC1_INTERL2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; VEC1_INTERL2: vector.ph: -; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967294 +; VEC1_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483646 ; VEC1_INTERL2-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC1_INTERL2-NEXT: [[TMP1:%.*]] = fmul fast float [[DOTCAST]], 5.000000e-01 ; VEC1_INTERL2-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP1]], 1.000000e+00 @@ -1251,11 +1251,11 @@ define void @fp_iv_loop4(ptr noalias nocapture %A, i32 %N) { ; VEC2_INTERL1_PRED_STORE-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; VEC2_INTERL1_PRED_STORE: for.body.preheader: -; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; VEC2_INTERL1_PRED_STORE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i32 [[N]], 1 ; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY:%.*]], label [[VECTOR_PH:%.*]] ; VEC2_INTERL1_PRED_STORE: vector.ph: -; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967294 +; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483646 ; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float ; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP1:%.*]] = fmul fast float [[DOTCAST]], 5.000000e-01 ; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP1]], 1.000000e+00 diff --git a/llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll b/llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll index fdbba5e02c49..107e9ea189bc 100644 --- a/llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll +++ b/llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll @@ -9,11 +9,11 @@ define i32 @foo(ptr nocapture %A, ptr nocapture %B, i32 %n) { ; CHECK-NEXT: [[CMP26:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP26]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.preheader: -; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] ; CHECK: vector.memcheck: -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[N]], -1 +; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[N]], -1 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i64 [[TMP2]], 2 ; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 4 @@ -24,7 +24,7 @@ define i32 @foo(ptr nocapture %A, ptr nocapture %B, i32 %n) { ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] ; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] diff --git a/llvm/test/Transforms/LoopVectorize/induction.ll b/llvm/test/Transforms/LoopVectorize/induction.ll index 0985253928d6..a8cfac64258e 100644 --- a/llvm/test/Transforms/LoopVectorize/induction.ll +++ b/llvm/test/Transforms/LoopVectorize/induction.ll @@ -4462,7 +4462,7 @@ define void @trunciv(ptr nocapture %a, i32 %start, i64 %k) { ; IND-NEXT: [[DOTNOT:%.*]] = icmp ult i64 [[K]], 2147483649 ; IND-NEXT: br i1 [[DOTNOT]], label [[VECTOR_PH:%.*]], label [[SCALAR_PH]] ; IND: vector.ph: -; IND-NEXT: [[N_VEC:%.*]] = and i64 [[K]], -2 +; IND-NEXT: [[N_VEC:%.*]] = and i64 [[K]], 4294967294 ; IND-NEXT: br label [[VECTOR_BODY:%.*]] ; IND: vector.body: ; IND-NEXT: [[OFFSET_IDX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -4502,7 +4502,7 @@ define void @trunciv(ptr nocapture %a, i32 %start, i64 %k) { ; UNROLL-NEXT: [[DOTNOT:%.*]] = icmp ult i64 [[K]], 2147483649 ; UNROLL-NEXT: br i1 [[DOTNOT]], label [[VECTOR_PH:%.*]], label [[SCALAR_PH]] ; UNROLL: vector.ph: -; UNROLL-NEXT: [[N_VEC:%.*]] = and i64 [[K]], -4 +; UNROLL-NEXT: [[N_VEC:%.*]] = and i64 [[K]], 4294967292 ; UNROLL-NEXT: br label [[VECTOR_BODY:%.*]] ; UNROLL: vector.body: ; UNROLL-NEXT: [[OFFSET_IDX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -4594,7 +4594,7 @@ define void @trunciv(ptr nocapture %a, i32 %start, i64 %k) { ; INTERLEAVE-NEXT: [[DOTNOT:%.*]] = icmp ult i64 [[K]], 2147483649 ; INTERLEAVE-NEXT: br i1 [[DOTNOT]], label [[VECTOR_PH:%.*]], label [[SCALAR_PH]] ; INTERLEAVE: vector.ph: -; INTERLEAVE-NEXT: [[N_VEC:%.*]] = and i64 [[K]], -8 +; INTERLEAVE-NEXT: [[N_VEC:%.*]] = and i64 [[K]], 4294967288 ; INTERLEAVE-NEXT: br label [[VECTOR_BODY:%.*]] ; INTERLEAVE: vector.body: ; INTERLEAVE-NEXT: [[OFFSET_IDX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] diff --git a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-masked-group.ll b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-masked-group.ll index 7d335a8d56f6..cd4d2d0055ed 100644 --- a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-masked-group.ll +++ b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-masked-group.ll @@ -127,7 +127,7 @@ if.then: %mul = shl nuw nsw i32 %ix.024, 1 %arrayidx = getelementptr inbounds i8, ptr %p, i32 %mul %0 = load i8, ptr %arrayidx, align 1 - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx4 = getelementptr inbounds i8, ptr %p, i32 %add %1 = load i8, ptr %arrayidx4, align 1 %cmp.i = icmp slt i8 %0, %1 @@ -163,7 +163,7 @@ for.body: br i1 %cmp1, label %if.then, label %for.inc if.then: - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx3 = getelementptr inbounds i8, ptr %q, i32 %add store i8 2, ptr %arrayidx3, align 1 br label %for.inc @@ -200,7 +200,7 @@ if.end: br i1 %cmp4, label %if.then6, label %for.inc if.then6: - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx7 = getelementptr inbounds i8, ptr %q, i32 %add store i8 2, ptr %arrayidx7, align 1 br label %for.inc diff --git a/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll b/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll index 71a1af78f7c8..187eefbe9b59 100644 --- a/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll +++ b/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll @@ -64,7 +64,7 @@ for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx0 = getelementptr inbounds [1024 x i32], ptr @AB, i64 0, i64 %indvars.iv %tmp = load i32, ptr %arrayidx0, align 4 - %tmp1 = or i64 %indvars.iv, 1 + %tmp1 = or disjoint i64 %indvars.iv, 1 %arrayidx1 = getelementptr inbounds [1024 x i32], ptr @AB, i64 0, i64 %tmp1 %tmp2 = load i32, ptr %arrayidx1, align 4 %add = add nsw i32 %tmp, %C @@ -700,7 +700,7 @@ for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv %tmp = load i32, ptr %arrayidx, align 4 - %tmp1 = or i64 %indvars.iv, 1 + %tmp1 = or disjoint i64 %indvars.iv, 1 %arrayidx2 = getelementptr inbounds i32, ptr %A, i64 %tmp1 %tmp2 = load i32, ptr %arrayidx2, align 4 %mul = mul nsw i32 %tmp2, %tmp @@ -1510,7 +1510,7 @@ define void @PR34743(ptr %a, ptr %b, i64 %n) { ; CHECK-NEXT: [[TMP12:%.*]] = mul nsw <4 x i32> [[TMP9]], [[TMP10]] ; CHECK-NEXT: [[TMP13:%.*]] = mul nsw <4 x i32> [[TMP12]], [[TMP11]] ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]] -; CHECK-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP14]], align 4, !alias.scope !36, !noalias !39 +; CHECK-NEXT: store <4 x i32> [[TMP13]], ptr [[TMP14]], align 4, !alias.scope [[META36:![0-9]+]], !noalias [[META39:![0-9]+]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP41:![0-9]+]] diff --git a/llvm/test/Transforms/LoopVectorize/pr39099.ll b/llvm/test/Transforms/LoopVectorize/pr39099.ll index 9c2eb3d1ebe4..ff1e46e35607 100644 --- a/llvm/test/Transforms/LoopVectorize/pr39099.ll +++ b/llvm/test/Transforms/LoopVectorize/pr39099.ll @@ -27,7 +27,7 @@ if.then: %arrayidx4 = getelementptr inbounds i8, ptr %q, i32 %mul store i8 %0, ptr %arrayidx4, align 1 %sub = sub i8 0, %0 - %add = or i32 %mul, 1 + %add = or disjoint i32 %mul, 1 %arrayidx8 = getelementptr inbounds i8, ptr %q, i32 %add store i8 %sub, ptr %arrayidx8, align 1 br label %for.inc diff --git a/llvm/test/Transforms/LoopVectorize/preserve-or-disjoint.ll b/llvm/test/Transforms/LoopVectorize/preserve-or-disjoint.ll new file mode 100644 index 000000000000..66509ffedd68 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/preserve-or-disjoint.ll @@ -0,0 +1,71 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s + +; TODO: Preserve disjoint flag on OR instruction. +define void @generate_disjoint_flags(i64 %n, ptr noalias %x) { +; CHECK-LABEL: define void @generate_disjoint_flags( +; CHECK-SAME: i64 [[N:%.*]], ptr noalias [[X:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = or disjoint <4 x i32> [[WIDE_LOAD]], +; CHECK-NEXT: [[TMP4:%.*]] = or <4 x i32> [[WIDE_LOAD]], +; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw <4 x i32> [[TMP3]], [[TMP4]] +; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP2]], align 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[GEP_X:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[IV]] +; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_X]], align 4 +; CHECK-NEXT: [[OR_1:%.*]] = or disjoint i32 [[LV]], 1 +; CHECK-NEXT: [[OR_2:%.*]] = or i32 [[LV]], 3 +; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[OR_1]], [[OR_2]] +; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP_X]], align 4 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] +; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.x = getelementptr inbounds i32, ptr %x, i64 %iv + %lv = load i32, ptr %gep.x, align 4 + %or.1 = or disjoint i32 %lv, 1 + %or.2 = or i32 %lv, 3 + %add = add nsw nuw i32 %or.1, %or.2 + store i32 %add, ptr %gep.x, align 4 + %iv.next = add i64 %iv, 1 + %exitcond = icmp eq i64 %iv.next, %n + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +;. diff --git a/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll b/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll index 1cbe9d70aec2..2a2d55fb75c5 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll @@ -195,7 +195,7 @@ for.end: ; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP10]], i32 2 ; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> [[TMP14]], i32 [[TMP11]], i32 3 ; CHECK-NEXT: [[TMP16:%.*]] = add <4 x i32> [[TMP15]], [[VEC_PHI]] -; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i64> [[VEC_IND]], +; CHECK-NEXT: [[TMP17:%.*]] = or disjoint <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i64> [[TMP17]], i32 0 ; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP18]] ; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i64> [[TMP17]], i32 1 @@ -233,7 +233,7 @@ for.body: %0 = load i32, ptr %gep.src, align 4 %sum.1 = add nsw i32 %0, %sum store i32 %sum.1, ptr %gep.dst, align 4 - %1 = or i64 %iv, 1 + %1 = or disjoint i64 %iv, 1 %gep.src.1 = getelementptr inbounds i32, ptr %src, i64 %1 %2 = load i32, ptr %gep.src.1, align 4 %sum.2 = add nsw i32 %2, %sum.1 @@ -302,7 +302,7 @@ for.body: %0 = load i32, ptr %arrayidx, align 4 %sum.1 = add nsw i32 %0, %sum store i32 %sum.1, ptr %gep.dst, align 4 - %1 = or i64 %iv, 1 + %1 = or disjoint i64 %iv, 1 %arrayidx4 = getelementptr inbounds i32, ptr %src, i64 %1 %2 = load i32, ptr %arrayidx4, align 4 %sum.2 = add nsw i32 %2, %sum.1 @@ -349,7 +349,7 @@ predicated: ; preds = %for.body br label %latch latch: ; preds = %predicated, %for.body - %1 = or i64 %iv, 1 + %1 = or disjoint i64 %iv, 1 %gep.src.1 = getelementptr inbounds i32, ptr %src, i64 %1 %2 = load i32, ptr %gep.src.1, align 4 %sum.2 = add nsw i32 %2, %sum.1 @@ -384,7 +384,7 @@ for.body: ; preds = %latch, %entry %0 = load i32, ptr %arrayidx, align 4 %sum.1 = add nsw i32 %0, %sum store i32 %sum.1, ptr %gep.dst, align 4 - %1 = or i64 %iv, 1 + %1 = or disjoint i64 %iv, 1 %gep.src.1 = getelementptr inbounds i32, ptr %src, i64 %1 %2 = load i32, ptr %gep.src.1, align 4 %sum.2 = add nsw i32 %2, %sum.1 diff --git a/llvm/test/Transforms/LoopVectorize/reduction.ll b/llvm/test/Transforms/LoopVectorize/reduction.ll index 8db07151a5f4..7c12eb1d4e59 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction.ll @@ -7,11 +7,11 @@ define i32 @reduction_sum(i32 %n, ptr %A, ptr %B) { ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label [[DOTLR_PH_PREHEADER:%.*]], label [[DOT_CRIT_EDGE:%.*]] ; CHECK: .lr.ph.preheader: -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -88,11 +88,11 @@ define i32 @reduction_prod(i32 %n, ptr %A, ptr %B) { ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label [[DOTLR_PH_PREHEADER:%.*]], label [[DOT_CRIT_EDGE:%.*]] ; CHECK: .lr.ph.preheader: -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -169,11 +169,11 @@ define i32 @reduction_mix(i32 %n, ptr %A, ptr %B) { ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label [[DOTLR_PH_PREHEADER:%.*]], label [[DOT_CRIT_EDGE:%.*]] ; CHECK: .lr.ph.preheader: -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -250,11 +250,11 @@ define i32 @reduction_mul(i32 %n, ptr %A, ptr %B) { ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label [[DOTLR_PH_PREHEADER:%.*]], label [[DOT_CRIT_EDGE:%.*]] ; CHECK: .lr.ph.preheader: -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -332,11 +332,11 @@ define i32 @start_at_non_zero(ptr %in, ptr %coeff, ptr %out, i32 %n) { ; CHECK-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[CMP7]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.preheader: -; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -408,11 +408,11 @@ define i32 @reduction_and(i32 %n, ptr %A, ptr %B) { ; CHECK-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[CMP7]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.preheader: -; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -484,11 +484,11 @@ define i32 @reduction_or(i32 %n, ptr %A, ptr %B) { ; CHECK-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[CMP7]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.preheader: -; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -560,11 +560,11 @@ define i32 @reduction_xor(i32 %n, ptr %A, ptr %B) { ; CHECK-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[CMP7]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.preheader: -; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -683,11 +683,11 @@ define i32 @reduction_sub_lhs(i32 %n, ptr %A) { ; CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.preheader: -; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -1041,11 +1041,11 @@ define i32 @reduction_sum_multiuse(i32 %n, ptr %A, ptr %B) { ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label [[DOTLR_PH_PREHEADER:%.*]], label [[END:%.*]] ; CHECK: .lr.ph.preheader: -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 4294967292 +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 2147483644 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] @@ -1135,8 +1135,8 @@ define void @reduction_reset(i32 %N, ptr %arrayA, ptr %arrayB) { ; CHECK-NEXT: [[C4:%.*]] = icmp sgt i32 [[N]], 0 ; CHECK-NEXT: br i1 [[C4]], label [[DOTLR_PH_PREHEADER:%.*]], label [[DOT_CRIT_EDGE:%.*]] ; CHECK: .lr.ph.preheader: -; CHECK-NEXT: [[C5:%.*]] = add i32 [[N]], -1 -; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[C5:%.*]] = add nsw i32 [[N]], -1 +; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: br label [[DOTLR_PH:%.*]] ; CHECK: .lr.ph: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[DOTLR_PH_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[DOTLR_PH]] ] diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check.ll b/llvm/test/Transforms/LoopVectorize/runtime-check.ll index 498c1a5f0a43..108580556f53 100644 --- a/llvm/test/Transforms/LoopVectorize/runtime-check.ll +++ b/llvm/test/Transforms/LoopVectorize/runtime-check.ll @@ -18,7 +18,7 @@ define i32 @foo(ptr nocapture %a, ptr nocapture %b, i32 %n) nounwind uwtable ssp ; CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0, !dbg [[DBG4]] ; CHECK-NEXT: br i1 [[CMP6]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]], !dbg [[DBG4]] ; CHECK: for.body.preheader: -; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64, !dbg [[DBG9:![0-9]+]] +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[N]] to i64, !dbg [[DBG9:![0-9]+]] ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4, !dbg [[DBG9]] ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]], !dbg [[DBG9]] ; CHECK: vector.memcheck: @@ -26,7 +26,7 @@ define i32 @foo(ptr nocapture %a, ptr nocapture %b, i32 %n) nounwind uwtable ssp ; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16, !dbg [[DBG9]] ; CHECK-NEXT: br i1 [[DIFF_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]], !dbg [[DBG9]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967292, !dbg [[DBG9]] +; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644, !dbg [[DBG9]] ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]], !dbg [[DBG9]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], !dbg [[DBG9]] diff --git a/llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll b/llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll index 989d25c0099c..6de52c09665c 100644 --- a/llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll +++ b/llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll @@ -2,7 +2,7 @@ ; RUN: opt -S -passes=loop-vectorize,instcombine -force-vector-interleave=2 -force-vector-width=4 -force-target-supports-scalable-vectors=true -scalable-vectorization=on < %s | FileCheck %s --check-prefix=CHECKUF2 ; CHECKUF1: for.body.preheader: -; CHECKUF1-DAG: %wide.trip.count = zext i32 %N to i64 +; CHECKUF1-DAG: %wide.trip.count = zext nneg i32 %N to i64 ; CHECKUF1-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64() ; CHECKUF1-DAG: %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2 ; CHECKUF1-DAG: %min.iters.check = icmp ugt i64 %[[VSCALEX4]], %wide.trip.count @@ -31,7 +31,7 @@ ; There is also the increment for the next iteration, e.g. instead of indexing IDXB, it indexes at IDXB + vscale * 4. ; CHECKUF2: for.body.preheader: -; CHECKUF2-DAG: %wide.trip.count = zext i32 %N to i64 +; CHECKUF2-DAG: %wide.trip.count = zext nneg i32 %N to i64 ; CHECKUF2-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64() ; CHECKUF2-DAG: %[[VSCALEX8:.*]] = shl i64 %[[VSCALE]], 3 ; CHECKUF2-DAG: %min.iters.check = icmp ugt i64 %[[VSCALEX8]], %wide.trip.count diff --git a/llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll b/llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll index ba02ddd1e5e2..b721d2184bcc 100644 --- a/llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll +++ b/llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll @@ -16,23 +16,23 @@ define void @test(ptr %data) { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0 -; CHECK-NEXT: [[INDUCTION1:%.*]] = add i64 [[INDEX]], 1 -; CHECK-NEXT: [[TMP0:%.*]] = shl nuw nsw i64 [[INDUCTION]], 1 -; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[INDUCTION1]], 1 -; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP0]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds double, ptr [[DATA:%.*]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = load double, ptr [[TMP4]], align 8 -; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP5]], align 8 -; CHECK-NEXT: [[TMP8:%.*]] = fneg double [[TMP6]] -; CHECK-NEXT: [[TMP9:%.*]] = fneg double [[TMP7]] -; CHECK-NEXT: store double [[TMP8]], ptr [[TMP4]], align 8 -; CHECK-NEXT: store double [[TMP9]], ptr [[TMP5]], align 8 +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i64 [[TMP0]], 1 +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i64 [[TMP1]], 1 +; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i64 [[TMP2]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = or disjoint i64 [[TMP3]], 1 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds double, ptr [[DATA:%.*]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP6]], align 8 +; CHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP7]], align 8 +; CHECK-NEXT: [[TMP10:%.*]] = fneg double [[TMP8]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg double [[TMP9]] +; CHECK-NEXT: store double [[TMP10]], ptr [[TMP6]], align 8 +; CHECK-NEXT: store double [[TMP11]], ptr [[TMP7]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 -; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1022 -; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1022 +; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: br label [[SCALAR_PH]] ; CHECK: scalar.ph: @@ -45,12 +45,12 @@ define void @test(ptr %data) { ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END:%.*]], label [[FOR_LATCH]] ; CHECK: for.latch: ; CHECK-NEXT: [[T15:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 1 -; CHECK-NEXT: [[T16:%.*]] = or i64 [[T15]], 1 +; CHECK-NEXT: [[T16:%.*]] = or disjoint i64 [[T15]], 1 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[T16]] ; CHECK-NEXT: [[T17:%.*]] = load double, ptr [[ARRAYIDX]], align 8 ; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[T17]] ; CHECK-NEXT: store double [[FNEG]], ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: br label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] +; CHECK-NEXT: br label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK: for.end: ; CHECK-NEXT: ret void ; @@ -65,7 +65,7 @@ for.body: for.latch: %t15 = shl nuw nsw i64 %indvars.iv, 1 - %t16 = or i64 %t15, 1 + %t16 = or disjoint i64 %t15, 1 %arrayidx = getelementptr inbounds double, ptr %data, i64 %t16 %t17 = load double, ptr %arrayidx, align 8 %fneg = fneg double %t17 diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll index 3626b8c9dce7..f129cf3e2a1a 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll @@ -757,6 +757,96 @@ end: ret void } +; FIXME: Preserve disjoint flag on OR recipe. +define void @print_disjoint_flags(i64 %n, ptr noalias %x) { +; CHECK-LABEL: Checking a loop in 'print_disjoint_flags' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> +; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> +; CHECK-NEXT: CLONE ir<%gep.x> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> +; CHECK-NEXT: WIDEN ir<%lv> = load ir<%gep.x> +; CHECK-NEXT: WIDEN ir<%or.1> = or disjoint ir<%lv>, ir<1> +; CHECK-NEXT: WIDEN ir<%or.2> = or ir<%lv>, ir<3> +; CHECK-NEXT: WIDEN ir<%add> = add nuw nsw ir<%or.1>, ir<%or.2> +; CHECK-NEXT: WIDEN store ir<%gep.x>, ir<%add> +; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = VF * UF + nuw vp<[[CAN_IV]]> +; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.x = getelementptr inbounds i32, ptr %x, i64 %iv + %lv = load i32, ptr %gep.x, align 4 + %or.1 = or disjoint i32 %lv, 1 + %or.2 = or i32 %lv, 3 + %add = add nsw nuw i32 %or.1, %or.2 + store i32 %add, ptr %gep.x, align 4 + %iv.next = add i64 %iv, 1 + %exitcond = icmp eq i64 %iv.next, %n + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} + +define void @zext_nneg(ptr noalias %p, ptr noalias %p1) { +; CHECK-LABEL: LV: Checking a loop in 'zext_nneg' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<%0> = vector-trip-count +; CHECK-NEXT: Live-in ir<0> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<%1> = CANONICAL-INDUCTION ir<0>, vp<%8> +; CHECK-NEXT: vp<%2> = DERIVED-IV ir<0> + vp<%1> * ir<1> (truncated to i32) +; CHECK-NEXT: vp<%3> = SCALAR-STEPS vp<%2>, ir<1> +; CHECK-NEXT: CLONE ir<%zext> = zext nneg vp<%3> +; CHECK-NEXT: CLONE ir<%idx2> = getelementptr ir<%p>, ir<%zext> +; CHECK-NEXT: WIDEN ir<%1> = load ir<%idx2> +; CHECK-NEXT: REPLICATE store ir<%1>, ir<%p1> +; CHECK-NEXT: EMIT vp<%8> = VF * UF + nuw vp<%1> +; CHECK-NEXT: EMIT branch-on-count vp<%8>, vp<%0> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; +entry: + br label %body + +body: + %iv = phi i64 [ %next, %body ], [ 0, %entry ] + %0 = trunc i64 %iv to i32 + %zext = zext nneg i32 %0 to i64 + %idx2 = getelementptr double, ptr %p, i64 %zext + %1 = load double, ptr %idx2, align 8 + store double %1, ptr %p1, align 8 + %next = add i64 %iv, 1 + %cmp = icmp eq i64 %next, 0 + br i1 %cmp, label %exit, label %body + +exit: + ret void +} + !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4} diff --git a/llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll b/llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll index 139df60a7b91..3464a748778b 100644 --- a/llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll +++ b/llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --include-generated-funcs --version 2 ; RUN: opt -S -passes=lowertypetests -mtriple=aarch64-unknown-linux-gnu %s | FileCheck --check-prefixes=AARCH64 %s ; Test for the jump table generation with branch protection on AArch64 @@ -6,7 +7,6 @@ target datalayout = "e-p:64:64" @0 = private unnamed_addr constant [2 x ptr] [ptr @f, ptr @g], align 16 -; AARCH64: @f = alias void (), ptr @[[JT:.*]] define void @f() !type !0 { ret void @@ -29,11 +29,30 @@ define i1 @foo(ptr %p) { !1 = !{i32 4, !"branch-target-enforcement", i32 1} -; AARCH64: define private void @[[JT]]() #[[ATTR:.*]] align 8 { -; AARCH64: bti c -; AARCH64-SAME: b $0 -; AARCH64-SAME: bti c -; AARCH64-SAME: b $1 - -; AARCH64: attributes #[[ATTR]] = { naked nounwind "branch-target-enforcement"="false" "sign-return-address"="none" +; AARCH64-LABEL: define hidden void @f.cfi() !type !1 { +; AARCH64-NEXT: ret void +; +; +; AARCH64-LABEL: define internal void @g.cfi() !type !1 { +; AARCH64-NEXT: ret void +; +; +; AARCH64-LABEL: define i1 @foo +; AARCH64-SAME: (ptr [[P:%.*]]) { +; AARCH64-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64 +; AARCH64-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @.cfi.jumptable to i64) +; AARCH64-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3 +; AARCH64-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 61 +; AARCH64-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]] +; AARCH64-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 1 +; AARCH64-NEXT: ret i1 [[TMP6]] +; +; +; AARCH64: Function Attrs: naked noinline +; AARCH64-LABEL: define private void @.cfi.jumptable +; AARCH64-SAME: () #[[ATTR1:[0-9]+]] align 8 { +; AARCH64-NEXT: entry: +; AARCH64-NEXT: call void asm sideeffect "bti c\0Ab $0\0Abti c\0Ab $1\0A", "s,s"(ptr @f.cfi, ptr @g.cfi) +; AARCH64-NEXT: unreachable +; diff --git a/llvm/test/Transforms/LowerTypeTests/cfi-nounwind-direct-call.ll b/llvm/test/Transforms/LowerTypeTests/cfi-nounwind-direct-call.ll new file mode 100644 index 000000000000..4c88f4acc12f --- /dev/null +++ b/llvm/test/Transforms/LowerTypeTests/cfi-nounwind-direct-call.ll @@ -0,0 +1,160 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --include-generated-funcs --version 2 +; RUN: opt < %s -passes='lowertypetests,default' -S | FileCheck %s + +; This IR is based of the following C++ +; which was compiled with: +; clang -cc1 -fexceptions -fcxx-exceptions \ +; -std=c++11 -internal-isystem llvm-project/build/lib/clang/17/include \ +; -nostdsysteminc -triple x86_64-unknown-linux -fsanitize=cfi-icall \ +; -fsanitize-cfi-cross-dso -fsanitize-trap=cfi-icall -Oz -S -emit-llvm +; int (*catch_ptr)(int); +; int nothrow_e (int num) noexcept { +; if (num) return 1; +; return 0; +; } +; int call_catch(int num) { +; catch_ptr = ¬hrow_e; +; return catch_ptr(num); +; } + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux" + +@catch_ptr = local_unnamed_addr global ptr null, align 8 +@llvm.used = appending global [1 x ptr] [ptr @__cfi_check_fail], section "llvm.metadata" + +; Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize willreturn memory(none) +define dso_local noundef i32 @_Z9nothrow_ei(i32 noundef %num) #0 !type !4 !type !5 !type !6 { +entry: + %tobool.not = icmp ne i32 %num, 0 + %. = zext i1 %tobool.not to i32 + ret i32 %. +} + +; Function Attrs: minsize mustprogress nounwind optsize +define dso_local noundef i32 @_Z10call_catchi(i32 noundef %num) local_unnamed_addr #1 !type !4 !type !5 !type !6 { +entry: + store ptr @_Z9nothrow_ei, ptr @catch_ptr, align 8, !tbaa !7 + %0 = tail call i1 @llvm.type.test(ptr nonnull @_Z9nothrow_ei, metadata !"_ZTSFiiE"), !nosanitize !11 + br i1 %0, label %cfi.cont, label %cfi.slowpath, !prof !12, !nosanitize !11 + +cfi.slowpath: ; preds = %entry + tail call void @__cfi_slowpath(i64 5174074510188755522, ptr nonnull @_Z9nothrow_ei) #5, !nosanitize !11 + br label %cfi.cont, !nosanitize !11 + +cfi.cont: ; preds = %cfi.slowpath, %entry + %tobool.not.i = icmp ne i32 %num, 0 + %..i = zext i1 %tobool.not.i to i32 + ret i32 %..i +} + +; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare i1 @llvm.type.test(ptr, metadata) #2 + +declare void @__cfi_slowpath(i64, ptr) local_unnamed_addr + +; Function Attrs: minsize optsize +define weak_odr hidden void @__cfi_check_fail(ptr noundef %0, ptr noundef %1) #3 { +entry: + %.not = icmp eq ptr %0, null, !nosanitize !11 + br i1 %.not, label %trap, label %cont, !nosanitize !11 + +trap: ; preds = %cont, %entry + tail call void @llvm.ubsantrap(i8 2) #6, !nosanitize !11 + unreachable, !nosanitize !11 + +cont: ; preds = %entry + %2 = load i8, ptr %0, align 4, !nosanitize !11 + %switch = icmp ult i8 %2, 5 + br i1 %switch, label %trap, label %cont6 + +cont6: ; preds = %cont + ret void, !nosanitize !11 +} + +; Function Attrs: cold noreturn nounwind +declare void @llvm.ubsantrap(i8 immarg) #4 + +define weak void @__cfi_check(i64 %0, ptr %1, ptr %2) local_unnamed_addr { +entry: + tail call void @llvm.trap() + unreachable +} + +; Function Attrs: cold noreturn nounwind +declare void @llvm.trap() #4 + +attributes #0 = { minsize mustprogress nofree norecurse nosync nounwind optsize willreturn memory(none) "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } +attributes #1 = { minsize mustprogress nounwind optsize "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } +attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #3 = { minsize optsize "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } +attributes #4 = { cold noreturn nounwind } +attributes #5 = { nounwind } +attributes #6 = { noreturn nounwind } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"Cross-DSO CFI", i32 1} +!2 = !{i32 4, !"CFI Canonical Jump Tables", i32 0} +!3 = !{!"clang version 17.0.2"} +!4 = !{i64 0, !"_ZTSFiiE"} +!5 = !{i64 0, !"_ZTSFiiE.generalized"} +!6 = !{i64 0, i64 5174074510188755522} +!7 = !{!8, !8, i64 0} +!8 = !{!"any pointer", !9, i64 0} +!9 = !{!"omnipotent char", !10, i64 0} +!10 = !{!"Simple C++ TBAA"} +!11 = !{} +!12 = !{!"branch_weights", i32 1048575, i32 1} +; CHECK: Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize willreturn memory(none) +; CHECK-LABEL: define dso_local noundef i32 @_Z9nothrow_ei +; CHECK-SAME: (i32 noundef [[NUM:%.*]]) #[[ATTR0:[0-9]+]] !type !4 !type !5 !type !6 { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp ne i32 [[NUM]], 0 +; CHECK-NEXT: [[DOT:%.*]] = zext i1 [[TOBOOL_NOT]] to i32 +; CHECK-NEXT: ret i32 [[DOT]] +; +; +; CHECK: Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize willreturn memory(write, argmem: none, inaccessiblemem: none) +; CHECK-LABEL: define dso_local noundef i32 @_Z10call_catchi +; CHECK-SAME: (i32 noundef [[NUM:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] !type !4 !type !5 !type !6 { +; CHECK-NEXT: entry: +; CHECK-NEXT: store ptr @_Z9nothrow_ei.cfi_jt, ptr @catch_ptr, align 8, !tbaa [[TBAA7:![0-9]+]] +; CHECK-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp ne i32 [[NUM]], 0 +; CHECK-NEXT: [[DOT_I:%.*]] = zext i1 [[TOBOOL_NOT_I]] to i32 +; CHECK-NEXT: ret i32 [[DOT_I]] +; +; +; CHECK: Function Attrs: minsize optsize +; CHECK-LABEL: define weak_odr hidden void @__cfi_check_fail +; CHECK-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq ptr [[TMP0]], null, !nosanitize !11 +; CHECK-NEXT: br i1 [[DOTNOT]], label [[TRAP:%.*]], label [[CONT:%.*]], !nosanitize !11 +; CHECK: trap: +; CHECK-NEXT: tail call void @llvm.ubsantrap(i8 2) #[[ATTR5:[0-9]+]], !nosanitize !11 +; CHECK-NEXT: unreachable, !nosanitize !11 +; CHECK: cont: +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP0]], align 4, !nosanitize !11 +; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i8 [[TMP2]], 5 +; CHECK-NEXT: br i1 [[SWITCH]], label [[TRAP]], label [[CONT6:%.*]] +; CHECK: cont6: +; CHECK-NEXT: ret void, !nosanitize !11 +; +; +; CHECK-LABEL: define weak void @__cfi_check +; CHECK-SAME: (i64 [[TMP0:%.*]], ptr [[TMP1:%.*]], ptr [[TMP2:%.*]]) local_unnamed_addr { +; CHECK-NEXT: entry: +; CHECK-NEXT: tail call void @llvm.trap() +; CHECK-NEXT: unreachable +; +; +; CHECK: Function Attrs: naked nocf_check noinline nounwind +; CHECK-LABEL: define internal void @_Z9nothrow_ei.cfi_jt +; CHECK-SAME: () #[[ATTR4:[0-9]+]] align 8 { +; CHECK-NEXT: entry: +; CHECK-NEXT: tail call void asm sideeffect "jmp ${0:c}@plt\0Aint3\0Aint3\0Aint3\0A", "s"(ptr nonnull @_Z9nothrow_ei) #[[ATTR6:[0-9]+]] +; CHECK-NEXT: unreachable +; diff --git a/llvm/test/Transforms/LowerTypeTests/cfi-unwind-direct-call.ll b/llvm/test/Transforms/LowerTypeTests/cfi-unwind-direct-call.ll new file mode 100644 index 000000000000..c56094083527 --- /dev/null +++ b/llvm/test/Transforms/LowerTypeTests/cfi-unwind-direct-call.ll @@ -0,0 +1,228 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --include-generated-funcs --version 2 +; RUN: opt < %s -passes='lowertypetests,default' -S | FileCheck %s + +; This IR is based of the following C++ +; which was compiled with: +; clang -cc1 -fexceptions -fcxx-exceptions \ +; -std=c++11 -internal-isystem llvm-project/build/lib/clang/17/include \ +; -nostdsysteminc -triple x86_64-unknown-linux -fsanitize=cfi-icall \ +; -fsanitize-cfi-cross-dso -fsanitize-trap=cfi-icall -Oz -S -emit-llvm +; void (*catch_ptr)(int); +; void throw_e (int num) { +; if (num) throw 20; +; } +; void call_catch(int num) { +; catch_ptr = &throw_e; +; try{ +; catch_ptr(num); +; } catch (int i) { +; } +; } + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux" + +@catch_ptr = local_unnamed_addr global ptr null, align 8 +@_ZTIi = external constant ptr +@llvm.used = appending global [1 x ptr] [ptr @__cfi_check_fail], section "llvm.metadata" + +; Function Attrs: minsize mustprogress optsize +define dso_local void @_Z7throw_ei(i32 noundef %num) #0 !type !4 !type !5 !type !6 { +entry: + %tobool.not = icmp eq i32 %num, 0 + br i1 %tobool.not, label %if.end, label %if.then + +if.then: ; preds = %entry + %exception = tail call ptr @__cxa_allocate_exception(i64 4) #5 + store i32 20, ptr %exception, align 16, !tbaa !7 + tail call void @__cxa_throw(ptr nonnull %exception, ptr nonnull @_ZTIi, ptr null) #6 + unreachable + +if.end: ; preds = %entry + ret void +} + +declare ptr @__cxa_allocate_exception(i64) local_unnamed_addr + +declare void @__cxa_throw(ptr, ptr, ptr) local_unnamed_addr + +; Function Attrs: minsize mustprogress optsize +define dso_local void @_Z10call_catchi(i32 noundef %num) local_unnamed_addr #0 personality ptr @__gxx_personality_v0 !type !4 !type !5 !type !6 { +entry: + store ptr @_Z7throw_ei, ptr @catch_ptr, align 8, !tbaa !11 + %0 = tail call i1 @llvm.type.test(ptr nonnull @_Z7throw_ei, metadata !"_ZTSFviE"), !nosanitize !13 + br i1 %0, label %cfi.cont, label %cfi.slowpath, !prof !14, !nosanitize !13 + +cfi.slowpath: ; preds = %entry + tail call void @__cfi_slowpath(i64 -8738933900360652027, ptr nonnull @_Z7throw_ei) #5, !nosanitize !13 + br label %cfi.cont, !nosanitize !13 + +cfi.cont: ; preds = %cfi.slowpath, %entry + invoke void @_Z7throw_ei(i32 noundef %num) #7 + to label %try.cont unwind label %lpad + +lpad: ; preds = %cfi.cont + %1 = landingpad { ptr, i32 } + catch ptr @_ZTIi + %2 = extractvalue { ptr, i32 } %1, 1 + %3 = tail call i32 @llvm.eh.typeid.for(ptr nonnull @_ZTIi) #5 + %matches = icmp eq i32 %2, %3 + br i1 %matches, label %catch, label %eh.resume + +catch: ; preds = %lpad + %4 = extractvalue { ptr, i32 } %1, 0 + %5 = tail call ptr @__cxa_begin_catch(ptr %4) #5 + tail call void @__cxa_end_catch() #5 + br label %try.cont + +try.cont: ; preds = %cfi.cont, %catch + ret void + +eh.resume: ; preds = %lpad + resume { ptr, i32 } %1 +} + +; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare i1 @llvm.type.test(ptr, metadata) #1 + +declare void @__cfi_slowpath(i64, ptr) local_unnamed_addr + +declare i32 @__gxx_personality_v0(...) + +; Function Attrs: nofree nosync nounwind memory(none) +declare i32 @llvm.eh.typeid.for(ptr) #2 + +declare ptr @__cxa_begin_catch(ptr) local_unnamed_addr + +declare void @__cxa_end_catch() local_unnamed_addr + +; Function Attrs: minsize optsize +define weak_odr hidden void @__cfi_check_fail(ptr noundef %0, ptr noundef %1) #3 { +entry: + %.not = icmp eq ptr %0, null, !nosanitize !13 + br i1 %.not, label %trap, label %cont, !nosanitize !13 + +trap: ; preds = %cont, %entry + tail call void @llvm.ubsantrap(i8 2) #8, !nosanitize !13 + unreachable, !nosanitize !13 + +cont: ; preds = %entry + %2 = load i8, ptr %0, align 4, !nosanitize !13 + %switch = icmp ult i8 %2, 5 + br i1 %switch, label %trap, label %cont6 + +cont6: ; preds = %cont + ret void, !nosanitize !13 +} + +; Function Attrs: cold noreturn nounwind +declare void @llvm.ubsantrap(i8 immarg) #4 + +define weak void @__cfi_check(i64 %0, ptr %1, ptr %2) local_unnamed_addr { +entry: + tail call void @llvm.trap() + unreachable +} + +; Function Attrs: cold noreturn nounwind +declare void @llvm.trap() #4 + +attributes #0 = { minsize mustprogress optsize "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } +attributes #1 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) } +attributes #2 = { nofree nosync nounwind memory(none) } +attributes #3 = { minsize optsize "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } +attributes #4 = { cold noreturn nounwind } +attributes #5 = { nounwind } +attributes #6 = { noreturn } +attributes #7 = { minsize optsize } +attributes #8 = { noreturn nounwind } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"Cross-DSO CFI", i32 1} +!2 = !{i32 4, !"CFI Canonical Jump Tables", i32 0} +!3 = !{!"clang version 17.0.2"} +!4 = !{i64 0, !"_ZTSFviE"} +!5 = !{i64 0, !"_ZTSFviE.generalized"} +!6 = !{i64 0, i64 -8738933900360652027} +!7 = !{!8, !8, i64 0} +!8 = !{!"int", !9, i64 0} +!9 = !{!"omnipotent char", !10, i64 0} +!10 = !{!"Simple C++ TBAA"} +!11 = !{!12, !12, i64 0} +!12 = !{!"any pointer", !9, i64 0} +!13 = !{} +!14 = !{!"branch_weights", i32 1048575, i32 1} +; CHECK: Function Attrs: minsize mustprogress optsize +; CHECK-LABEL: define dso_local void @_Z7throw_ei +; CHECK-SAME: (i32 noundef [[NUM:%.*]]) #[[ATTR0:[0-9]+]] !type !4 !type !5 !type !6 { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[NUM]], 0 +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] +; CHECK: if.then: +; CHECK-NEXT: [[EXCEPTION:%.*]] = tail call ptr @__cxa_allocate_exception(i64 4) #[[ATTR5:[0-9]+]] +; CHECK-NEXT: store i32 20, ptr [[EXCEPTION]], align 16, !tbaa [[TBAA7:![0-9]+]] +; CHECK-NEXT: tail call void @__cxa_throw(ptr nonnull [[EXCEPTION]], ptr nonnull @_ZTIi, ptr null) #[[ATTR6:[0-9]+]] +; CHECK-NEXT: unreachable +; CHECK: if.end: +; CHECK-NEXT: ret void +; +; +; CHECK: Function Attrs: minsize mustprogress optsize +; CHECK-LABEL: define dso_local void @_Z10call_catchi +; CHECK-SAME: (i32 noundef [[NUM:%.*]]) local_unnamed_addr #[[ATTR0]] personality ptr @__gxx_personality_v0 !type !4 !type !5 !type !6 { +; CHECK-NEXT: entry: +; CHECK-NEXT: store ptr @_Z7throw_ei.cfi_jt, ptr @catch_ptr, align 8, !tbaa [[TBAA11:![0-9]+]] +; CHECK-NEXT: invoke void @_Z7throw_ei.cfi_jt() #[[ATTR7:[0-9]+]] +; CHECK-NEXT: to label [[TRY_CONT:%.*]] unwind label [[LPAD:%.*]] +; CHECK: lpad: +; CHECK-NEXT: [[TMP0:%.*]] = landingpad { ptr, i32 } +; CHECK-NEXT: catch ptr @_ZTIi +; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { ptr, i32 } [[TMP0]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.eh.typeid.for(ptr nonnull @_ZTIi) #[[ATTR5]] +; CHECK-NEXT: [[MATCHES:%.*]] = icmp eq i32 [[TMP1]], [[TMP2]] +; CHECK-NEXT: br i1 [[MATCHES]], label [[CATCH:%.*]], label [[EH_RESUME:%.*]] +; CHECK: catch: +; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP0]], 0 +; CHECK-NEXT: [[TMP4:%.*]] = tail call ptr @__cxa_begin_catch(ptr [[TMP3]]) #[[ATTR5]] +; CHECK-NEXT: tail call void @__cxa_end_catch() #[[ATTR5]] +; CHECK-NEXT: br label [[TRY_CONT]] +; CHECK: try.cont: +; CHECK-NEXT: ret void +; CHECK: eh.resume: +; CHECK-NEXT: resume { ptr, i32 } [[TMP0]] +; +; +; CHECK: Function Attrs: minsize optsize +; CHECK-LABEL: define weak_odr hidden void @__cfi_check_fail +; CHECK-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq ptr [[TMP0]], null, !nosanitize !13 +; CHECK-NEXT: br i1 [[DOTNOT]], label [[TRAP:%.*]], label [[CONT:%.*]], !nosanitize !13 +; CHECK: trap: +; CHECK-NEXT: tail call void @llvm.ubsantrap(i8 2) #[[ATTR8:[0-9]+]], !nosanitize !13 +; CHECK-NEXT: unreachable, !nosanitize !13 +; CHECK: cont: +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP0]], align 4, !nosanitize !13 +; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i8 [[TMP2]], 5 +; CHECK-NEXT: br i1 [[SWITCH]], label [[TRAP]], label [[CONT6:%.*]] +; CHECK: cont6: +; CHECK-NEXT: ret void, !nosanitize !13 +; +; +; CHECK-LABEL: define weak void @__cfi_check +; CHECK-SAME: (i64 [[TMP0:%.*]], ptr [[TMP1:%.*]], ptr [[TMP2:%.*]]) local_unnamed_addr { +; CHECK-NEXT: entry: +; CHECK-NEXT: tail call void @llvm.trap() +; CHECK-NEXT: unreachable +; +; +; CHECK: Function Attrs: naked nocf_check noinline +; CHECK-LABEL: define internal void @_Z7throw_ei.cfi_jt +; CHECK-SAME: () #[[ATTR4:[0-9]+]] align 8 { +; CHECK-NEXT: entry: +; CHECK-NEXT: tail call void asm sideeffect "jmp ${0:c}@plt\0Aint3\0Aint3\0Aint3\0A", "s"(ptr nonnull @_Z7throw_ei) #[[ATTR5]] +; CHECK-NEXT: unreachable +; diff --git a/llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll b/llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll index 3406e70dd02b..c482a20f9513 100644 --- a/llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll +++ b/llvm/test/Transforms/LowerTypeTests/function-arm-thumb.ll @@ -45,5 +45,5 @@ define void @addrtaken() { ; CHECK-NEXT: unreachable ; CHECK-NEXT: } -; CHECK-DAG: attributes #[[AA]] = { naked nounwind "target-features"="-thumb-mode" } -; CHECK-DAG: attributes #[[AT]] = { naked nounwind "branch-target-enforcement"="false" "sign-return-address"="none" "target-cpu"="cortex-a8" "target-features"="+thumb-mode" } +; CHECK-DAG: attributes #[[AA]] = { naked noinline "target-features"="-thumb-mode" } +; CHECK-DAG: attributes #[[AT]] = { naked noinline "branch-target-enforcement"="false" "sign-return-address"="none" "target-cpu"="cortex-a8" "target-features"="+thumb-mode" } diff --git a/llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll b/llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll index 01bf81d0abd4..c1308931c781 100644 --- a/llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll +++ b/llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll @@ -43,5 +43,5 @@ define i1 @foo(ptr %p) { ; BTI: call void asm sideeffect "bti\0Ab.w $0\0Abti\0Ab.w $1\0A", "s,s"(ptr @f.cfi, ptr @g.cfi) ; NOBTI: call void asm sideeffect "b.w $0\0Ab.w $1\0A", "s,s"(ptr @f.cfi, ptr @g.cfi) -; BTI: attributes [[ATTRS]] = { naked nounwind "branch-target-enforcement"="false" "sign-return-address"="none" "target-features"="+thumb-mode,+pacbti" } -; NOBTI: attributes [[ATTRS]] = { naked nounwind "branch-target-enforcement"="false" "sign-return-address"="none" "target-cpu"="cortex-a8" "target-features"="+thumb-mode" } +; BTI: attributes [[ATTRS]] = { naked noinline "branch-target-enforcement"="false" "sign-return-address"="none" "target-features"="+thumb-mode,+pacbti" } +; NOBTI: attributes [[ATTRS]] = { naked noinline "branch-target-enforcement"="false" "sign-return-address"="none" "target-cpu"="cortex-a8" "target-features"="+thumb-mode" } diff --git a/llvm/test/Transforms/LowerTypeTests/function.ll b/llvm/test/Transforms/LowerTypeTests/function.ll index 5ba69e236e41..a858aace834d 100644 --- a/llvm/test/Transforms/LowerTypeTests/function.ll +++ b/llvm/test/Transforms/LowerTypeTests/function.ll @@ -51,7 +51,7 @@ define internal void @g() !type !0 { !0 = !{i32 0, !"typeid1"} -declare i1 @llvm.type.test(ptr %ptr, metadata %bitset) nounwind readnone +declare i1 @llvm.type.test(ptr %ptr, metadata %bitset) noinline readnone define i1 @foo(ptr %p) { ; NATIVE: sub i64 {{.*}}, ptrtoint (ptr @[[JT]] to i64) @@ -109,13 +109,13 @@ define i1 @foo(ptr %p) { ; NATIVE-SAME: "s,s"(ptr @f.cfi, ptr @g.cfi) -; X86-LINUX: attributes #[[ATTR]] = { naked nocf_check nounwind } -; X86-WIN32: attributes #[[ATTR]] = { nocf_check nounwind } -; ARM: attributes #[[ATTR]] = { naked nounwind -; THUMB: attributes #[[ATTR]] = { naked nounwind "branch-target-enforcement"="false" "sign-return-address"="none" "target-cpu"="cortex-a8" "target-features"="+thumb-mode" } -; THUMBV6M: attributes #[[ATTR]] = { naked nounwind "branch-target-enforcement"="false" "sign-return-address"="none" "target-features"="+thumb-mode" } -; RISCV: attributes #[[ATTR]] = { naked nounwind "target-features"="-c,-relax" } -; LOONGARCH64: attributes #[[ATTR]] = { naked nounwind } +; X86-LINUX: attributes #[[ATTR]] = { naked nocf_check noinline } +; X86-WIN32: attributes #[[ATTR]] = { nocf_check noinline } +; ARM: attributes #[[ATTR]] = { naked noinline +; THUMB: attributes #[[ATTR]] = { naked noinline "branch-target-enforcement"="false" "sign-return-address"="none" "target-cpu"="cortex-a8" "target-features"="+thumb-mode" } +; THUMBV6M: attributes #[[ATTR]] = { naked noinline "branch-target-enforcement"="false" "sign-return-address"="none" "target-features"="+thumb-mode" } +; RISCV: attributes #[[ATTR]] = { naked noinline "target-features"="-c,-relax" } +; LOONGARCH64: attributes #[[ATTR]] = { naked noinline } ; WASM32: ![[I0]] = !{i64 1} ; WASM32: ![[I1]] = !{i64 2} diff --git a/llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll b/llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll index a88a45a65d59..f56d30be3795 100644 --- a/llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll +++ b/llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll @@ -28,4 +28,4 @@ define i1 @foo(ptr %p) { ; X86_32-NEXT: call void asm sideeffect "endbr32\0Ajmp ${0:c}@plt\0A.balign 16, 0xcc\0Aendbr32\0Ajmp ${1:c}@plt\0A.balign 16, 0xcc\0A", "s,s"(ptr @f.cfi, ptr @g.cfi) ; X86_64-NEXT: call void asm sideeffect "endbr64\0Ajmp ${0:c}@plt\0A.balign 16, 0xcc\0Aendbr64\0Ajmp ${1:c}@plt\0A.balign 16, 0xcc\0A", "s,s"(ptr @f.cfi, ptr @g.cfi) -; X86_64: attributes #[[#ATTR]] = { naked nocf_check nounwind } +; X86_64: attributes #[[#ATTR]] = { naked nocf_check noinline } diff --git a/llvm/test/Transforms/PGOProfile/chr.ll b/llvm/test/Transforms/PGOProfile/chr.ll index c4030af943a9..0551a171091c 100644 --- a/llvm/test/Transforms/PGOProfile/chr.ll +++ b/llvm/test/Transforms/PGOProfile/chr.ll @@ -1583,7 +1583,7 @@ define i32 @test_chr_17(i32 %i, i1 %j) !prof !14 { ; CHECK-NEXT: br i1 [[TMP1]], label [[BB1]], label [[BB0:%.*]], !prof [[PROF16]] ; CHECK: bb0: ; CHECK-NEXT: call void @foo() -; CHECK-NEXT: [[S:%.*]] = add i32 [[TMP0]], [[I]] +; CHECK-NEXT: [[S:%.*]] = add nuw nsw i32 [[TMP0]], [[I]] ; CHECK-NEXT: br label [[BB1]] ; CHECK: bb1: ; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[I]], [[BBQ]] ], [ [[TMP0]], [[BBE]] ], [ [[S]], [[BB0]] ] @@ -1942,8 +1942,8 @@ define i32 @test_chr_21(i64 %i, i64 %k, i64 %j) !prof !14 { ; CHECK: bb1: ; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i64 [[I_FR]], 2 ; CHECK-NEXT: switch i64 [[I_FR]], label [[BB2:%.*]] [ -; CHECK-NEXT: i64 2, label [[BB3_NONCHR2:%.*]] -; CHECK-NEXT: i64 86, label [[BB2_NONCHR1:%.*]] +; CHECK-NEXT: i64 2, label [[BB3_NONCHR2:%.*]] +; CHECK-NEXT: i64 86, label [[BB2_NONCHR1:%.*]] ; CHECK-NEXT: ], !prof [[PROF19:![0-9]+]] ; CHECK: bb2: ; CHECK-NEXT: call void @foo() diff --git a/llvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll b/llvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll index 02ca48effbff..10193df6f179 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll @@ -13,7 +13,7 @@ define i32 @f(i32 %c) { ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK: switch.lookup: -; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[SWITCH_TABLEIDX]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[SWITCH_TABLEIDX]] to i64 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], ptr @switch.table.f, i64 0, i64 [[TMP1]] ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4 ; CHECK-NEXT: br label [[RETURN]] diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll b/llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll index 246bb0095e1a..e5582548447a 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll @@ -19,7 +19,7 @@ define void @vdiv(ptr %x, ptr %y, double %a, i32 %N) #0 { ; CHECK: for.body.preheader: ; CHECK-NEXT: [[X4:%.*]] = ptrtoint ptr [[X:%.*]] to i64 ; CHECK-NEXT: [[Y5:%.*]] = ptrtoint ptr [[Y:%.*]] to i64 -; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 16 ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[X4]], [[Y5]] ; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 128 diff --git a/llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll b/llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll index b5bba73e05f8..bae3e269b6f0 100644 --- a/llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll +++ b/llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll @@ -72,7 +72,7 @@ define void @_Z4loopi(i32 %width) { ; ROTATE-NEXT: [[CMP13_NOT:%.*]] = icmp eq i32 [[WIDTH]], 1 ; ROTATE-NEXT: br i1 [[CMP13_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] ; ROTATE: for.body.preheader: -; ROTATE-NEXT: [[TMP0:%.*]] = add i32 [[WIDTH]], -2 +; ROTATE-NEXT: [[TMP0:%.*]] = add nsw i32 [[WIDTH]], -2 ; ROTATE-NEXT: br label [[FOR_BODY:%.*]] ; ROTATE: for.cond.cleanup: ; ROTATE-NEXT: tail call void @f0() diff --git a/llvm/test/Transforms/Reassociate/add-like-or.ll b/llvm/test/Transforms/Reassociate/add-like-or.ll index 514b10b5a76b..d88458f630bc 100644 --- a/llvm/test/Transforms/Reassociate/add-like-or.ll +++ b/llvm/test/Transforms/Reassociate/add-like-or.ll @@ -59,6 +59,18 @@ define i32 @test3(i32 %x, i32 %bit) { ret i32 %res } +; Test that disjoint allow reassociation. +define i32 @test4(i32 %a, i32 %b) { +; CHECK-LABEL: @test4( +; CHECK-NEXT: [[C:%.*]] = add i32 [[A:%.*]], 1 +; CHECK-NEXT: [[C_PLUS_ONE:%.*]] = add i32 [[C]], [[B:%.*]] +; CHECK-NEXT: ret i32 [[C_PLUS_ONE]] +; + %c = or disjoint i32 %a, %b + %c.plus.one = add i32 %c, 1 + ret i32 %c.plus.one +} + declare i32 @llvm.ctlz.i32(i32, i1 immarg) #2 !0 = !{i32 0, i32 33} diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll index 70eb21fcbf12..efe8bd9e610b 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll @@ -205,7 +205,7 @@ entry: %idxprom7 = sext i32 %mul to i64 %arrayidx8 = getelementptr inbounds i16, ptr %x, i64 %idxprom7 %4 = load i16, ptr %arrayidx8, align 2 - %add10 = or i32 %mul, 1 + %add10 = or disjoint i32 %mul, 1 %idxprom11 = sext i32 %add10 to i64 %arrayidx12 = getelementptr inbounds i16, ptr %x, i64 %idxprom11 %5 = load i16, ptr %arrayidx12, align 2 @@ -754,7 +754,7 @@ entry: %idxprom11 = sext i32 %mul to i64 %arrayidx12 = getelementptr inbounds i32, ptr %x, i64 %idxprom11 %5 = load i32, ptr %arrayidx12, align 4 - %add14 = or i32 %mul, 1 + %add14 = or disjoint i32 %mul, 1 %idxprom15 = sext i32 %add14 to i64 %arrayidx16 = getelementptr inbounds i32, ptr %x, i64 %idxprom15 %6 = load i32, ptr %arrayidx16, align 4 diff --git a/llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll b/llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll index 712e847a49b1..5132e4918116 100644 --- a/llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll +++ b/llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll @@ -10,10 +10,10 @@ define void @fusion(ptr noalias nocapture align 256 dereferenceable(19267584) %a ; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64 ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds half, ptr [[ARG1:%.*]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds half, ptr [[ARG:%.*]], i64 [[TMP6]] -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr [[TMP11]], align 8 -; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x half> [[TMP2]], -; CHECK-NEXT: [[TMP4:%.*]] = fadd fast <2 x half> [[TMP3]], -; CHECK-NEXT: store <2 x half> [[TMP4]], ptr [[TMP16]], align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[TMP11]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = fmul fast <2 x half> [[TMP1]], +; CHECK-NEXT: [[TMP3:%.*]] = fadd fast <2 x half> [[TMP2]], +; CHECK-NEXT: store <2 x half> [[TMP3]], ptr [[TMP16]], align 8 ; CHECK-NEXT: ret void ; ; NOVECTOR-LABEL: @fusion( @@ -21,7 +21,7 @@ define void @fusion(ptr noalias nocapture align 256 dereferenceable(19267584) %a ; NOVECTOR-NEXT: [[TMP4:%.*]] = or i32 [[TMP]], [[ARG3:%.*]] ; NOVECTOR-NEXT: [[TMP5:%.*]] = shl nuw nsw i32 [[TMP4]], 2 ; NOVECTOR-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64 -; NOVECTOR-NEXT: [[TMP7:%.*]] = or i64 [[TMP6]], 1 +; NOVECTOR-NEXT: [[TMP7:%.*]] = or disjoint i64 [[TMP6]], 1 ; NOVECTOR-NEXT: [[TMP11:%.*]] = getelementptr inbounds half, ptr [[ARG1:%.*]], i64 [[TMP6]] ; NOVECTOR-NEXT: [[TMP12:%.*]] = load half, ptr [[TMP11]], align 8 ; NOVECTOR-NEXT: [[TMP13:%.*]] = fmul fast half [[TMP12]], 0xH5380 @@ -40,7 +40,7 @@ define void @fusion(ptr noalias nocapture align 256 dereferenceable(19267584) %a %tmp4 = or i32 %tmp, %arg3 %tmp5 = shl nuw nsw i32 %tmp4, 2 %tmp6 = zext i32 %tmp5 to i64 - %tmp7 = or i64 %tmp6, 1 + %tmp7 = or disjoint i64 %tmp6, 1 %tmp11 = getelementptr inbounds half, ptr %arg1, i64 %tmp6 %tmp12 = load half, ptr %tmp11, align 8 %tmp13 = fmul fast half %tmp12, 0xH5380 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll b/llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll index 2b27a7aed1be..22cba328b180 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll @@ -11,14 +11,14 @@ define void @reduce_compare(ptr nocapture %A, i32 %n) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[N:%.*]] to double ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV]], i32 0 -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ] -; CHECK-NEXT: [[TMP1:%.*]] = shl nsw i64 [[INDVARS_IV]], 1 -; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i64 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 [[TMP2]] ; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[SHUFFLE]], [[TMP3]] +; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP1]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], ; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[TMP5]], ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 0 @@ -48,7 +48,7 @@ for.body: ; preds = %for.inc, %entry %mul1 = fmul double %conv, %1 %mul2 = fmul double %mul1, 7.000000e+00 %add = fadd double %mul2, 5.000000e+00 - %2 = or i64 %0, 1 + %2 = or disjoint i64 %0, 1 %arrayidx6 = getelementptr inbounds double, ptr %A, i64 %2 %3 = load double, ptr %arrayidx6, align 8 %mul8 = fmul double %conv, %3 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll b/llvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll index 63eb5a4e07ba..2e733930650e 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll @@ -18,17 +18,17 @@ define void @foo_3double(i32 %u) #0 { ; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[MUL]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2000 x double], ptr @A, i32 0, i64 [[IDXPROM]] ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2000 x double], ptr @B, i32 0, i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[ARRAYIDX4]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]] -; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX4]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[TMP0]], [[TMP1]] +; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[ARRAYIDX]], align 8 ; CHECK-NEXT: [[ADD24:%.*]] = add nsw i32 [[MUL]], 2 ; CHECK-NEXT: [[IDXPROM25:%.*]] = sext i32 [[ADD24]] to i64 ; CHECK-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [2000 x double], ptr @A, i32 0, i64 [[IDXPROM25]] -; CHECK-NEXT: [[TMP6:%.*]] = load double, ptr [[ARRAYIDX26]], align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr [[ARRAYIDX26]], align 8 ; CHECK-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [2000 x double], ptr @B, i32 0, i64 [[IDXPROM25]] -; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr [[ARRAYIDX30]], align 8 -; CHECK-NEXT: [[ADD31:%.*]] = fadd double [[TMP6]], [[TMP7]] +; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX30]], align 8 +; CHECK-NEXT: [[ADD31:%.*]] = fadd double [[TMP3]], [[TMP4]] ; CHECK-NEXT: store double [[ADD31]], ptr [[ARRAYIDX26]], align 8 ; CHECK-NEXT: ret void ; @@ -75,10 +75,10 @@ define void @foo_2double(i32 %u) #0 { ; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[MUL]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2000 x double], ptr @A, i32 0, i64 [[IDXPROM]] ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2000 x double], ptr @B, i32 0, i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[ARRAYIDX4]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]] -; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX4]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[TMP0]], [[TMP1]] +; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[ARRAYIDX]], align 8 ; CHECK-NEXT: ret void ; entry: @@ -114,10 +114,10 @@ define void @foo_4float(i32 %u) #0 { ; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[MUL]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2000 x float], ptr @C, i32 0, i64 [[IDXPROM]] ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2000 x float], ptr @D, i32 0, i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[ARRAYIDX4]], align 4 -; CHECK-NEXT: [[TMP4:%.*]] = fadd <4 x float> [[TMP1]], [[TMP3]] -; CHECK-NEXT: store <4 x float> [[TMP4]], ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[ARRAYIDX4]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = fadd <4 x float> [[TMP0]], [[TMP1]] +; CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: ret void ; entry: @@ -181,11 +181,11 @@ define i32 @foo_loop(ptr %A, i32 %n) #0 { ; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP0]], 2 ; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[MUL]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> , [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0 -; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 1 -; CHECK-NEXT: [[ADD6:%.*]] = fadd double [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> , [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1 +; CHECK-NEXT: [[ADD6:%.*]] = fadd double [[TMP4]], [[TMP5]] ; CHECK-NEXT: [[ADD7]] = fadd double [[TMP1]], [[ADD6]] ; CHECK-NEXT: store double [[ADD7]], ptr [[SUM]], align 8 ; CHECK-NEXT: [[INC]] = add nsw i32 [[TMP0]], 1 @@ -259,10 +259,10 @@ define void @foo_2double_non_power_of_2(i32 %u) #0 { ; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[ADD6]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2000 x double], ptr @A, i32 0, i64 [[IDXPROM]] ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2000 x double], ptr @B, i32 0, i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[ARRAYIDX4]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]] -; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX4]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[TMP0]], [[TMP1]] +; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[ARRAYIDX]], align 8 ; CHECK-NEXT: ret void ; entry: @@ -300,10 +300,10 @@ define void @foo_2double_non_power_of_2_zext(i32 %u) #0 { ; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[ADD6]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2000 x double], ptr @A, i32 0, i64 [[IDXPROM]] ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2000 x double], ptr @B, i32 0, i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[ARRAYIDX4]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]] -; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX4]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[TMP0]], [[TMP1]] +; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[ARRAYIDX]], align 8 ; CHECK-NEXT: ret void ; entry: @@ -355,11 +355,11 @@ define i32 @foo_loop_non_power_of_2(ptr %A, i32 %n) #0 { ; CHECK-NEXT: [[ADD_5:%.*]] = add i32 [[MUL]], 5 ; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[ADD_5]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> , [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0 -; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 1 -; CHECK-NEXT: [[ADD6:%.*]] = fadd double [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> , [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1 +; CHECK-NEXT: [[ADD6:%.*]] = fadd double [[TMP4]], [[TMP5]] ; CHECK-NEXT: [[ADD7]] = fadd double [[TMP1]], [[ADD6]] ; CHECK-NEXT: store double [[ADD7]], ptr [[SUM]], align 8 ; CHECK-NEXT: [[INC]] = add i32 [[TMP0]], 1 @@ -445,18 +445,18 @@ define double @bar(ptr nocapture readonly %a, i32 %n) local_unnamed_addr #0 { ; CHECK-NEXT: [[CMP15:%.*]] = icmp eq i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP15]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY:%.*]] ; CHECK: for.cond.cleanup: -; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x double> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[TMP6:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x double> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[TMP5:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x double> [[TMP0]], i32 0 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP0]], i32 1 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret double [[MUL]] ; CHECK: for.body: ; CHECK-NEXT: [[I_018:%.*]] = phi i32 [ [[ADD5:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ] -; CHECK-NEXT: [[TMP3:%.*]] = phi <2 x double> [ [[TMP6]], [[FOR_BODY]] ], [ zeroinitializer, [[ENTRY]] ] +; CHECK-NEXT: [[TMP3:%.*]] = phi <2 x double> [ [[TMP5]], [[FOR_BODY]] ], [ zeroinitializer, [[ENTRY]] ] ; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[I_018]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 [[IDXPROM]] -; CHECK-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: [[TMP6]] = fadd <2 x double> [[TMP3]], [[TMP5]] +; CHECK-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 +; CHECK-NEXT: [[TMP5]] = fadd <2 x double> [[TMP3]], [[TMP4]] ; CHECK-NEXT: [[ADD5]] = add i32 [[I_018]], 2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD5]], [[N]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP]] @@ -479,7 +479,7 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds double, ptr %a, i64 %idxprom %0 = load double, ptr %arrayidx, align 8 %add = fadd double %x.016, %0 - %add1 = or i32 %i.018, 1 + %add1 = or disjoint i32 %i.018, 1 %idxprom2 = zext i32 %add1 to i64 %arrayidx3 = getelementptr inbounds double, ptr %a, i64 %idxprom2 %1 = load double, ptr %arrayidx3, align 8 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll b/llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll index 1cef1032bf5d..5562291dbb6b 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll @@ -15,7 +15,7 @@ define void @test() { ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> , float [[DOTPRE_PRE]], i32 0 ; CHECK-NEXT: br label [[BB1:%.*]] ; CHECK: bb1: -; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x float> [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP8:%.*]], [[BB2:%.*]] ] +; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x float> [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP10:%.*]], [[BB2:%.*]] ] ; CHECK-NEXT: br label [[BB2]] ; CHECK: bb2: ; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x float> [ [[TMP1]], [[BB1]] ], [ [[TMP9:%.*]], [[BB2]] ] @@ -29,8 +29,9 @@ define void @test() { ; CHECK-NEXT: tail call void @foo(float [[MUL]]) ; CHECK-NEXT: [[I2:%.*]] = load float, ptr poison, align 4 ; CHECK-NEXT: [[TOBOOL:%.*]] = fcmp une float [[I2]], 0.000000e+00 -; CHECK-NEXT: [[TMP8]] = insertelement <2 x float> [[TMP2]], float [[I2]], i32 0 -; CHECK-NEXT: [[TMP9]] = shufflevector <2 x float> [[TMP8]], <2 x float> [[TMP5]], <2 x i32> +; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP5]], <2 x float> poison, <2 x i32> +; CHECK-NEXT: [[TMP9]] = insertelement <2 x float> [[TMP8]], float [[I2]], i32 0 +; CHECK-NEXT: [[TMP10]] = shufflevector <2 x float> [[TMP9]], <2 x float> [[TMP2]], <2 x i32> ; CHECK-NEXT: br i1 [[TOBOOL]], label [[BB1]], label [[BB2]] ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll b/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll new file mode 100644 index 000000000000..16ede231c200 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll @@ -0,0 +1,45 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=slp-vectorizer -S -slp-threshold=-9999 < %s | FileCheck %s + +define i64 @foo() { +; CHECK-LABEL: define i64 @foo() { +; CHECK-NEXT: bb: +; CHECK-NEXT: br label [[BB3:%.*]] +; CHECK: bb1: +; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i64> [ [[TMP5:%.*]], [[BB3]] ] +; CHECK-NEXT: ret i64 0 +; CHECK: bb3: +; CHECK-NEXT: [[PHI5:%.*]] = phi i64 [ 0, [[BB:%.*]] ], [ 0, [[BB3]] ] +; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i64> [ zeroinitializer, [[BB]] ], [ [[TMP7:%.*]], [[BB3]] ] +; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> , i64 [[PHI5]], i32 0 +; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP5]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i32> +; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> , <2 x i32> +; CHECK-NEXT: [[TMP7]] = add <2 x i64> [[TMP6]], [[TMP2]] +; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP7]], i32 1 +; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr i64, ptr addrspace(1) null, i64 [[TMP8]] +; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP5]], i32 1 +; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i64 [[TMP9]], 0 +; CHECK-NEXT: br i1 false, label [[BB3]], label [[BB1:%.*]] +; +bb: + br label %bb3 + +bb1: + %phi = phi i64 [ %add, %bb3 ] + %phi2 = phi i64 [ %or, %bb3 ] + ret i64 0 + +bb3: + %phi4 = phi i64 [ 0, %bb ], [ %add7, %bb3 ] + %phi5 = phi i64 [ 0, %bb ], [ 0, %bb3 ] + %phi6 = phi i64 [ 0, %bb ], [ %add, %bb3 ] + %add = add i64 %phi6, %phi5 + %add7 = add i64 0, 0 + %getelementptr = getelementptr i64, ptr addrspace(1) null, i64 %add7 + %or = or i64 %phi4, 0 + %icmp = icmp ult i64 %or, 0 + br i1 false, label %bb3, label %bb1 +} + diff --git a/llvm/test/Transforms/SLPVectorizer/X86/hoist.ll b/llvm/test/Transforms/SLPVectorizer/X86/hoist.ll index 8290cfee3c3c..65ede4baf651 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/hoist.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/hoist.ll @@ -18,13 +18,13 @@ define i32 @foo(ptr nocapture %A, i32 %n, i32 %k) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[K:%.*]], i32 1 -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[I_024:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD10:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i32 [[I_024]] ; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], [[SHUFFLE]] +; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], [[TMP2]] ; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: [[ADD10]] = add nsw i32 [[I_024]], 4 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD10]], 10000 @@ -41,17 +41,17 @@ for.body: ; preds = %entry, %for.body %0 = load i32, ptr %arrayidx, align 4 %add = add nsw i32 %0, %n store i32 %add, ptr %arrayidx, align 4 - %add121 = or i32 %i.024, 1 + %add121 = or disjoint i32 %i.024, 1 %arrayidx2 = getelementptr inbounds i32, ptr %A, i32 %add121 %1 = load i32, ptr %arrayidx2, align 4 %add3 = add nsw i32 %1, %k store i32 %add3, ptr %arrayidx2, align 4 - %add422 = or i32 %i.024, 2 + %add422 = or disjoint i32 %i.024, 2 %arrayidx5 = getelementptr inbounds i32, ptr %A, i32 %add422 %2 = load i32, ptr %arrayidx5, align 4 %add6 = add nsw i32 %2, %n store i32 %add6, ptr %arrayidx5, align 4 - %add723 = or i32 %i.024, 3 + %add723 = or disjoint i32 %i.024, 3 %arrayidx8 = getelementptr inbounds i32, ptr %A, i32 %add723 %3 = load i32, ptr %arrayidx8, align 4 %add9 = add nsw i32 %3, %k diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll index 107237a8348f..197ffd11b245 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll @@ -28,10 +28,10 @@ define i32 @add_red(ptr %A, i32 %n) { ; CHECK-NEXT: [[SUM_032:%.*]] = phi float [ 0.000000e+00, [[FOR_BODY_LR_PH]] ], [ [[ADD17:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[MUL:%.*]] = shl nsw i64 [[I_033]], 2 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[MUL]] -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x float> [[TMP2]], -; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP3]]) -; CHECK-NEXT: [[ADD17]] = fadd fast float [[SUM_032]], [[TMP4]] +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x float> [[TMP1]], +; CHECK-NEXT: [[TMP3:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP2]]) +; CHECK-NEXT: [[ADD17]] = fadd fast float [[SUM_032]], [[TMP3]] ; CHECK-NEXT: [[INC]] = add nsw i64 [[I_033]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP0]] ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]], label [[FOR_BODY]] @@ -57,17 +57,17 @@ for.body: %arrayidx = getelementptr inbounds float, ptr %A, i64 %mul %1 = load float, ptr %arrayidx, align 4 %mul2 = fmul float %1, 7.000000e+00 - %add28 = or i64 %mul, 1 + %add28 = or disjoint i64 %mul, 1 %arrayidx4 = getelementptr inbounds float, ptr %A, i64 %add28 %2 = load float, ptr %arrayidx4, align 4 %mul5 = fmul float %2, 7.000000e+00 %add6 = fadd fast float %mul2, %mul5 - %add829 = or i64 %mul, 2 + %add829 = or disjoint i64 %mul, 2 %arrayidx9 = getelementptr inbounds float, ptr %A, i64 %add829 %3 = load float, ptr %arrayidx9, align 4 %mul10 = fmul float %3, 7.000000e+00 %add11 = fadd fast float %add6, %mul10 - %add1330 = or i64 %mul, 3 + %add1330 = or disjoint i64 %mul, 3 %arrayidx14 = getelementptr inbounds float, ptr %A, i64 %add1330 %4 = load float, ptr %arrayidx14, align 4 %mul15 = fmul float %4, 7.000000e+00 @@ -103,20 +103,20 @@ define i32 @mul_red(ptr noalias %A, ptr noalias %B, i32 %n) { ; CHECK-NEXT: [[CMP38:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP38]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.lr.ph: -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[B:%.*]], align 4 -; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[B:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[N]] to i64 ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[I_040:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[SUM_039:%.*]] = phi float [ 0.000000e+00, [[FOR_BODY_LR_PH]] ], [ [[MUL21:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[MUL:%.*]] = shl nsw i64 [[I_040]], 2 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[MUL]] -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr [[ARRAYIDX2]], align 4 -; CHECK-NEXT: [[TMP5:%.*]] = fmul <4 x float> [[TMP1]], [[TMP4]] -; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP5]]) -; CHECK-NEXT: [[MUL21]] = fmul float [[SUM_039]], [[TMP6]] +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[ARRAYIDX2]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x float> [[TMP0]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP3]]) +; CHECK-NEXT: [[MUL21]] = fmul float [[SUM_039]], [[TMP4]] ; CHECK-NEXT: [[INC]] = add nsw i64 [[I_040]], 1 -; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP2]] +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP1]] ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]], label [[FOR_BODY]] ; CHECK: for.cond.for.end_crit_edge: ; CHECK-NEXT: [[PHITMP:%.*]] = fptosi float [[MUL21]] to i32 @@ -147,17 +147,17 @@ for.body: %arrayidx2 = getelementptr inbounds float, ptr %A, i64 %mul %5 = load float, ptr %arrayidx2, align 4 %mul3 = fmul float %0, %5 - %add35 = or i64 %mul, 1 + %add35 = or disjoint i64 %mul, 1 %arrayidx6 = getelementptr inbounds float, ptr %A, i64 %add35 %6 = load float, ptr %arrayidx6, align 4 %mul7 = fmul float %1, %6 %add8 = fadd fast float %mul3, %mul7 - %add1136 = or i64 %mul, 2 + %add1136 = or disjoint i64 %mul, 2 %arrayidx12 = getelementptr inbounds float, ptr %A, i64 %add1136 %7 = load float, ptr %arrayidx12, align 4 %mul13 = fmul float %2, %7 %add14 = fadd fast float %add8, %mul13 - %add1737 = or i64 %mul, 3 + %add1737 = or disjoint i64 %mul, 3 %arrayidx18 = getelementptr inbounds float, ptr %A, i64 %add1737 %8 = load float, ptr %arrayidx18, align 4 %mul19 = fmul float %3, %8 @@ -198,27 +198,27 @@ define i32 @long_red(ptr noalias %A, ptr noalias %B, i32 %n) { ; CHECK-NEXT: [[CMP81:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP81]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.lr.ph: -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr [[B:%.*]], align 4 +; CHECK-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr [[B:%.*]], align 4 ; CHECK-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds float, ptr [[B]], i64 8 -; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[ARRAYIDX45]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX45]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[N]] to i64 ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[I_083:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[SUM_082:%.*]] = phi float [ 0.000000e+00, [[FOR_BODY_LR_PH]] ], [ [[ADD51:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[MUL:%.*]] = mul nsw i64 [[I_083]], 6 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[MUL]] -; CHECK-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr [[ARRAYIDX2]], align 4 -; CHECK-NEXT: [[TMP6:%.*]] = fmul fast <8 x float> [[TMP1]], [[TMP5]] +; CHECK-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr [[ARRAYIDX2]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = fmul fast <8 x float> [[TMP0]], [[TMP3]] ; CHECK-NEXT: [[ADD47:%.*]] = add nsw i64 [[MUL]], 8 ; CHECK-NEXT: [[ARRAYIDX48:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[ADD47]] -; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX48]], align 4 -; CHECK-NEXT: [[MUL49:%.*]] = fmul fast float [[TMP2]], [[TMP7]] -; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[TMP6]]) -; CHECK-NEXT: [[OP_RDX:%.*]] = fadd fast float [[TMP8]], [[MUL49]] +; CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX48]], align 4 +; CHECK-NEXT: [[MUL49:%.*]] = fmul fast float [[TMP1]], [[TMP5]] +; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[TMP4]]) +; CHECK-NEXT: [[OP_RDX:%.*]] = fadd fast float [[TMP6]], [[MUL49]] ; CHECK-NEXT: [[ADD51]] = fadd fast float [[SUM_082]], [[OP_RDX]] ; CHECK-NEXT: [[INC]] = add nsw i64 [[I_083]], 1 -; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP3]] +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP2]] ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]], label [[FOR_BODY]] ; CHECK: for.cond.for.end_crit_edge: ; CHECK-NEXT: [[PHITMP:%.*]] = fptosi float [[ADD51]] to i32 @@ -259,7 +259,7 @@ for.body: %arrayidx2 = getelementptr inbounds float, ptr %A, i64 %mul %10 = load float, ptr %arrayidx2, align 4 %mul3 = fmul fast float %0, %10 - %add80 = or i64 %mul, 1 + %add80 = or disjoint i64 %mul, 1 %arrayidx6 = getelementptr inbounds float, ptr %A, i64 %add80 %11 = load float, ptr %arrayidx6, align 4 %mul7 = fmul fast float %1, %11 @@ -330,20 +330,20 @@ define i32 @chain_red(ptr noalias %A, ptr noalias %B, i32 %n) { ; CHECK-NEXT: [[CMP41:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP41]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.lr.ph: -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[B:%.*]], align 4 -; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[B:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[N]] to i64 ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[I_043:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[SUM_042:%.*]] = phi float [ 0.000000e+00, [[FOR_BODY_LR_PH]] ], [ [[OP_RDX:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[MUL:%.*]] = shl nsw i64 [[I_043]], 2 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[MUL]] -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr [[ARRAYIDX2]], align 4 -; CHECK-NEXT: [[TMP5:%.*]] = fmul fast <4 x float> [[TMP1]], [[TMP4]] -; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP5]]) -; CHECK-NEXT: [[OP_RDX]] = fadd fast float [[TMP6]], [[SUM_042]] +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[ARRAYIDX2]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <4 x float> [[TMP0]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP3]]) +; CHECK-NEXT: [[OP_RDX]] = fadd fast float [[TMP4]], [[SUM_042]] ; CHECK-NEXT: [[INC]] = add nsw i64 [[I_043]], 1 -; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP2]] +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP1]] ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]], label [[FOR_BODY]] ; CHECK: for.cond.for.end_crit_edge: ; CHECK-NEXT: [[PHITMP:%.*]] = fptosi float [[OP_RDX]] to i32 @@ -375,17 +375,17 @@ for.body: %5 = load float, ptr %arrayidx2, align 4 %mul3 = fmul fast float %0, %5 %add = fadd fast float %sum.042, %mul3 - %add638 = or i64 %mul, 1 + %add638 = or disjoint i64 %mul, 1 %arrayidx7 = getelementptr inbounds float, ptr %A, i64 %add638 %6 = load float, ptr %arrayidx7, align 4 %mul8 = fmul fast float %1, %6 %add9 = fadd fast float %add, %mul8 - %add1239 = or i64 %mul, 2 + %add1239 = or disjoint i64 %mul, 2 %arrayidx13 = getelementptr inbounds float, ptr %A, i64 %add1239 %7 = load float, ptr %arrayidx13, align 4 %mul14 = fmul fast float %2, %7 %add15 = fadd fast float %add9, %mul14 - %add1840 = or i64 %mul, 3 + %add1840 = or disjoint i64 %mul, 3 %arrayidx19 = getelementptr inbounds float, ptr %A, i64 %add1840 %8 = load float, ptr %arrayidx19, align 4 %mul20 = fmul fast float %3, %8 @@ -441,13 +441,13 @@ define void @foo(ptr nocapture readonly %arg_A, i32 %arg_B, ptr nocapture %array ; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[INDVARS_IV]], 2 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[ARRAY:%.*]], i64 [[TMP0]] ; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP0]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i64 [[TMP0]], 1 ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[ARRAY]], i64 [[TMP2]] ; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 -; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP0]], 2 +; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i64 [[TMP0]], 2 ; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[ARRAY]], i64 [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX8]], align 4 -; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP0]], 3 +; CHECK-NEXT: [[TMP6:%.*]] = or disjoint i64 [[TMP0]], 3 ; CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, ptr [[ARRAY]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX12]], align 4 ; CHECK-NEXT: br i1 [[CMP1495]], label [[FOR_COND_CLEANUP15]], label [[FOR_BODY16_LR_PH:%.*]] @@ -502,13 +502,13 @@ for.body: ; preds = %for.cond.cleanup15, %0 = shl i64 %indvars.iv, 2 %arrayidx = getelementptr inbounds float, ptr %array, i64 %0 %1 = load float, ptr %arrayidx, align 4 - %2 = or i64 %0, 1 + %2 = or disjoint i64 %0, 1 %arrayidx4 = getelementptr inbounds float, ptr %array, i64 %2 %3 = load float, ptr %arrayidx4, align 4 - %4 = or i64 %0, 2 + %4 = or disjoint i64 %0, 2 %arrayidx8 = getelementptr inbounds float, ptr %array, i64 %4 %5 = load float, ptr %arrayidx8, align 4 - %6 = or i64 %0, 3 + %6 = or disjoint i64 %0, 3 %arrayidx12 = getelementptr inbounds float, ptr %array, i64 %6 %7 = load float, ptr %arrayidx12, align 4 br i1 %cmp1495, label %for.cond.cleanup15, label %for.body16.lr.ph @@ -569,22 +569,22 @@ define void @store_red_double(ptr noalias %A, ptr noalias %B, ptr noalias %C, i3 ; CHECK-NEXT: [[CMP17:%.*]] = icmp sgt i32 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[CMP17]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]] ; CHECK: for.body.lr.ph: -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8 -; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8 +; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[N]] to i64 ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[I_018:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[MUL:%.*]] = shl nsw i64 [[I_018]], 2 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 [[MUL]] -; CHECK-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr [[ARRAYIDX2]], align 8 -; CHECK-NEXT: [[TMP5:%.*]] = fmul fast <2 x double> [[TMP1]], [[TMP4]] -; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP5]], i32 0 -; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP5]], i32 1 -; CHECK-NEXT: [[ADD8:%.*]] = fadd fast double [[TMP6]], [[TMP7]] +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[ARRAYIDX2]], align 8 +; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x double> [[TMP0]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1 +; CHECK-NEXT: [[ADD8:%.*]] = fadd fast double [[TMP4]], [[TMP5]] ; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds double, ptr [[C:%.*]], i64 [[I_018]] ; CHECK-NEXT: store double [[ADD8]], ptr [[ARRAYIDX9]], align 8 ; CHECK-NEXT: [[INC]] = add nsw i64 [[I_018]], 1 -; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP2]] +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP1]] ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END]], label [[FOR_BODY]] ; CHECK: for.end: ; CHECK-NEXT: ret void @@ -606,7 +606,7 @@ for.body: %arrayidx2 = getelementptr inbounds double, ptr %A, i64 %mul %3 = load double, ptr %arrayidx2, align 8 %mul3 = fmul fast double %0, %3 - %add16 = or i64 %mul, 1 + %add16 = or disjoint i64 %mul, 1 %arrayidx6 = getelementptr inbounds double, ptr %A, i64 %add16 %4 = load double, ptr %arrayidx6, align 8 %mul7 = fmul fast double %1, %4 @@ -645,11 +645,11 @@ define i32 @store_red(ptr noalias %A, ptr noalias %B, ptr noalias %C, i32 %n) { ; CHECK-NEXT: [[C_ADDR_038:%.*]] = phi ptr [ [[C:%.*]], [[FOR_BODY_LR_PH]] ], [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[MUL:%.*]] = shl nsw i64 [[I_039]], 2 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[MUL]] -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[B:%.*]], align 4 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr [[ARRAYIDX2]], align 4 -; CHECK-NEXT: [[TMP5:%.*]] = fmul fast <4 x float> [[TMP2]], [[TMP4]] -; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP5]]) -; CHECK-NEXT: store float [[TMP6]], ptr [[C_ADDR_038]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[B:%.*]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[ARRAYIDX2]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <4 x float> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP3]]) +; CHECK-NEXT: store float [[TMP4]], ptr [[C_ADDR_038]], align 4 ; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds float, ptr [[C_ADDR_038]], i64 1 ; CHECK-NEXT: [[INC]] = add nsw i64 [[I_039]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INC]], [[TMP0]] @@ -677,19 +677,19 @@ for.body: %2 = load float, ptr %arrayidx2, align 4 %mul3 = fmul fast float %1, %2 %3 = load float, ptr %arrayidx4, align 4 - %add34 = or i64 %mul, 1 + %add34 = or disjoint i64 %mul, 1 %arrayidx6 = getelementptr inbounds float, ptr %A, i64 %add34 %4 = load float, ptr %arrayidx6, align 4 %mul7 = fmul fast float %3, %4 %add8 = fadd fast float %mul3, %mul7 %5 = load float, ptr %arrayidx9, align 4 - %add1135 = or i64 %mul, 2 + %add1135 = or disjoint i64 %mul, 2 %arrayidx12 = getelementptr inbounds float, ptr %A, i64 %add1135 %6 = load float, ptr %arrayidx12, align 4 %mul13 = fmul fast float %5, %6 %add14 = fadd fast float %add8, %mul13 %7 = load float, ptr %arrayidx15, align 4 - %add1736 = or i64 %mul, 3 + %add1736 = or disjoint i64 %mul, 3 %arrayidx18 = getelementptr inbounds float, ptr %A, i64 %add1736 %8 = load float, ptr %arrayidx18, align 4 %mul19 = fmul fast float %7, %8 @@ -1003,10 +1003,10 @@ define void @i32_red_invoke(i32 %val) personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr @arr_i32, align 16 ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP0]]) ; CHECK-NEXT: [[RES:%.*]] = invoke i32 @foobar(i32 [[TMP1]]) -; CHECK-NEXT: to label [[NORMAL:%.*]] unwind label [[EXCEPTION:%.*]] +; CHECK-NEXT: to label [[NORMAL:%.*]] unwind label [[EXCEPTION:%.*]] ; CHECK: exception: ; CHECK-NEXT: [[CLEANUP:%.*]] = landingpad i8 -; CHECK-NEXT: cleanup +; CHECK-NEXT: cleanup ; CHECK-NEXT: br label [[NORMAL]] ; CHECK: normal: ; CHECK-NEXT: ret void @@ -1041,11 +1041,11 @@ define i32 @reduction_result_used_in_phi(ptr nocapture readonly %data, i1 zeroex ; CHECK-NEXT: entry: ; CHECK-NEXT: br i1 [[B:%.*]], label [[BB:%.*]], label [[EXIT:%.*]] ; CHECK: bb: -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[DATA:%.*]], align 4 -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]]) +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[DATA:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP0]]) ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: -; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP2]], [[BB]] ] +; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP1]], [[BB]] ] ; CHECK-NEXT: ret i32 [[SUM_1]] ; entry: @@ -1074,11 +1074,11 @@ define i32 @reduction_result_used_in_phi_loop(ptr nocapture readonly %data, i1 z ; CHECK-NEXT: entry: ; CHECK-NEXT: br i1 [[B:%.*]], label [[BB:%.*]], label [[EXIT:%.*]] ; CHECK: bb: -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[DATA:%.*]], align 4 -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]]) +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[DATA:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP0]]) ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: -; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP2]], [[BB]] ] +; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP1]], [[BB]] ] ; CHECK-NEXT: ret i32 [[SUM_1]] ; entry: @@ -1131,9 +1131,9 @@ bb.1: define float @fadd_v4f32_fmf(ptr %p) { ; CHECK-LABEL: @fadd_v4f32_fmf( -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[P:%.*]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP2]]) -; CHECK-NEXT: ret float [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[P:%.*]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP1]]) +; CHECK-NEXT: ret float [[TMP2]] ; %p1 = getelementptr inbounds float, float* %p, i64 1 %p2 = getelementptr inbounds float, ptr %p, i64 2 @@ -1154,9 +1154,9 @@ define float @fadd_v4f32_fmf(ptr %p) { define float @fadd_v4f32_fmf_intersect(ptr %p) { ; CHECK-LABEL: @fadd_v4f32_fmf_intersect( -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[P:%.*]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = call reassoc ninf nsz float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP2]]) -; CHECK-NEXT: ret float [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[P:%.*]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = call reassoc ninf nsz float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP1]]) +; CHECK-NEXT: ret float [[TMP2]] ; %p1 = getelementptr inbounds float, float* %p, i64 1 %p2 = getelementptr inbounds float, ptr %p, i64 2 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll b/llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll index dcc012c9cd80..e4143a7b9116 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll @@ -12,14 +12,14 @@ define void @in_tree_user(ptr nocapture %A, i32 %n) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[N:%.*]] to double ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV]], i32 0 -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC:%.*]] ] -; CHECK-NEXT: [[TMP1:%.*]] = shl nsw i64 [[INDVARS_IV]], 1 -; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i64 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 [[TMP2]] ; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[SHUFFLE]], [[TMP3]] +; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP1]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], ; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[TMP5]], ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 0 @@ -52,7 +52,7 @@ for.body: ; preds = %for.inc, %entry %mul2 = fmul double %mul1, 7.000000e+00 %add = fadd double %mul2, 5.000000e+00 %InTreeUser = fadd double %add, %add ; <------------------ In tree user. - %2 = or i64 %0, 1 + %2 = or disjoint i64 %0, 1 %arrayidx6 = getelementptr inbounds double, ptr %A, i64 %2 %3 = load double, ptr %arrayidx6, align 8 %mul8 = fmul double %conv, %3 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll b/llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll index 42068c9bc5d4..20b0885b2253 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll @@ -12,14 +12,14 @@ define i32 @foo(ptr nocapture %A, i32 %n) { ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]] -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[N]], i32 0 -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <8 x i32> zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = add nsw <8 x i32> [[TMP1]], [[SHUFFLE]] +; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[N]], i32 0 +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer +; CHECK-NEXT: [[TMP3:%.*]] = add nsw <8 x i32> [[TMP0]], [[TMP2]] ; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 8 -; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[N]] +; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[N]] ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END]] ; CHECK: for.end: ; CHECK-NEXT: ret i32 undef @@ -34,37 +34,37 @@ for.body: %0 = load i32, ptr %arrayidx, align 4 %add1 = add nsw i32 %0, %n store i32 %add1, ptr %arrayidx, align 4 - %1 = or i64 %indvars.iv, 1 + %1 = or disjoint i64 %indvars.iv, 1 %arrayidx4 = getelementptr inbounds i32, ptr %A, i64 %1 %2 = load i32, ptr %arrayidx4, align 4 %add5 = add nsw i32 %2, %n store i32 %add5, ptr %arrayidx4, align 4 - %3 = or i64 %indvars.iv, 2 + %3 = or disjoint i64 %indvars.iv, 2 %arrayidx8 = getelementptr inbounds i32, ptr %A, i64 %3 %4 = load i32, ptr %arrayidx8, align 4 %add9 = add nsw i32 %4, %n store i32 %add9, ptr %arrayidx8, align 4 - %5 = or i64 %indvars.iv, 3 + %5 = or disjoint i64 %indvars.iv, 3 %arrayidx12 = getelementptr inbounds i32, ptr %A, i64 %5 %6 = load i32, ptr %arrayidx12, align 4 %add13 = add nsw i32 %6, %n store i32 %add13, ptr %arrayidx12, align 4 - %7 = or i64 %indvars.iv, 4 + %7 = or disjoint i64 %indvars.iv, 4 %arrayidx16 = getelementptr inbounds i32, ptr %A, i64 %7 %8 = load i32, ptr %arrayidx16, align 4 %add17 = add nsw i32 %8, %n store i32 %add17, ptr %arrayidx16, align 4 - %9 = or i64 %indvars.iv, 5 + %9 = or disjoint i64 %indvars.iv, 5 %arrayidx20 = getelementptr inbounds i32, ptr %A, i64 %9 %10 = load i32, ptr %arrayidx20, align 4 %add21 = add nsw i32 %10, %n store i32 %add21, ptr %arrayidx20, align 4 - %11 = or i64 %indvars.iv, 6 + %11 = or disjoint i64 %indvars.iv, 6 %arrayidx24 = getelementptr inbounds i32, ptr %A, i64 %11 %12 = load i32, ptr %arrayidx24, align 4 %add25 = add nsw i32 %12, %n store i32 %add25, ptr %arrayidx24, align 4 - %13 = or i64 %indvars.iv, 7 + %13 = or disjoint i64 %indvars.iv, 7 %arrayidx28 = getelementptr inbounds i32, ptr %A, i64 %13 %14 = load i32, ptr %arrayidx28, align 4 %add29 = add nsw i32 %14, %n diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll index ceee30a3360e..ce9158d8bf2e 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll @@ -21,11 +21,11 @@ define i32 @reduce(ptr nocapture %A, i32 %n, i32 %m) { ; CHECK-NEXT: [[SUM_014:%.*]] = phi double [ [[ADD6:%.*]], [[FOR_BODY]] ], [ 0.000000e+00, [[ENTRY]] ] ; CHECK-NEXT: [[MUL:%.*]] = shl nsw i32 [[I_015]], 1 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i32 [[MUL]] -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP1]], -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0 -; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP2]], i32 1 -; CHECK-NEXT: [[ADD5:%.*]] = fadd double [[TMP3]], [[TMP4]] +; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x double> [[TMP0]], +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1 +; CHECK-NEXT: [[ADD5:%.*]] = fadd double [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[ADD6]] = fadd double [[SUM_014]], [[ADD5]] ; CHECK-NEXT: [[INC]] = add nsw i32 [[I_015]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]] @@ -48,7 +48,7 @@ for.body: ; preds = %entry, %for.body %arrayidx = getelementptr inbounds double, ptr %A, i32 %mul %0 = load double, ptr %arrayidx, align 4 %mul1 = fmul double %0, 7.000000e+00 - %add12 = or i32 %mul, 1 + %add12 = or disjoint i32 %mul, 1 %arrayidx3 = getelementptr inbounds double, ptr %A, i32 %add12 %1 = load double, ptr %arrayidx3, align 4 %mul4 = fmul double %1, 7.000000e+00 @@ -74,12 +74,12 @@ define i32 @horiz_max_multiple_uses(ptr %x, ptr %p) { ; CHECK-LABEL: @horiz_max_multiple_uses( ; CHECK-NEXT: [[X4:%.*]] = getelementptr [32 x i32], ptr [[X:%.*]], i64 0, i64 4 ; CHECK-NEXT: [[X5:%.*]] = getelementptr [32 x i32], ptr [[X]], i64 0, i64 5 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[X]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[X]], align 4 ; CHECK-NEXT: [[T4:%.*]] = load i32, ptr [[X4]], align 4 ; CHECK-NEXT: [[T5:%.*]] = load i32, ptr [[X5]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP2]]) -; CHECK-NEXT: [[MAX_ROOT_CMP:%.*]] = icmp sgt i32 [[TMP3]], [[T4]] -; CHECK-NEXT: [[MAX_ROOT_SEL:%.*]] = select i1 [[MAX_ROOT_CMP]], i32 [[TMP3]], i32 [[T4]] +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP1]]) +; CHECK-NEXT: [[MAX_ROOT_CMP:%.*]] = icmp sgt i32 [[TMP2]], [[T4]] +; CHECK-NEXT: [[MAX_ROOT_SEL:%.*]] = select i1 [[MAX_ROOT_CMP]], i32 [[TMP2]], i32 [[T4]] ; CHECK-NEXT: [[C012345:%.*]] = icmp sgt i32 [[MAX_ROOT_SEL]], [[T5]] ; CHECK-NEXT: [[T17:%.*]] = select i1 [[C012345]], i32 [[MAX_ROOT_SEL]], i32 [[T5]] ; CHECK-NEXT: [[THREE_OR_FOUR:%.*]] = select i1 [[MAX_ROOT_CMP]], i32 3, i32 4 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll index b244715caa79..5dcd5d3190ad 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll @@ -35,7 +35,7 @@ define double @foo(ptr nocapture %D) { %4 = load double, ptr %3, align 4 %A4 = fmul double %4, %4 %A42 = fmul double %A4, %A4 - %5 = or i32 %2, 1 + %5 = or disjoint i32 %2, 1 %6 = getelementptr inbounds double, ptr %D, i32 %5 %7 = load double, ptr %6, align 4 %A7 = fmul double %7, %7 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll b/llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll index f657477ce8e5..f1cd42a2c404 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll @@ -10,17 +10,17 @@ define i32 @foo(ptr %diff) #0 { ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[A_088:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[OP_RDX:%.*]], [[FOR_BODY]] ] -; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[INDVARS_IV]], 3 -; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DIFF:%.*]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4 -; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[DIFF]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[INDVARS_IV]], 3 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DIFF:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i64 [[TMP0]], 4 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[DIFF]], i64 [[TMP1]] ; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [8 x [8 x i32]], ptr [[M2]], i64 0, i64 [[INDVARS_IV]], i64 0 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr [[ARRAYIDX2]], align 4 -; CHECK-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[TMP6]], [[TMP4]] -; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr [[ARRAYIDX6]], align 16 -; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]]) -; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP9]], [[A_088]] +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[ARRAYIDX2]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], [[TMP2]] +; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[ARRAYIDX6]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]]) +; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP5]], [[A_088]] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 8 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]] @@ -37,7 +37,7 @@ for.body: ; preds = %for.body, %entry %0 = shl i64 %indvars.iv, 3 %arrayidx = getelementptr inbounds i32, ptr %diff, i64 %0 %1 = load i32, ptr %arrayidx, align 4 - %2 = or i64 %0, 4 + %2 = or disjoint i64 %0, 4 %arrayidx2 = getelementptr inbounds i32, ptr %diff, i64 %2 %3 = load i32, ptr %arrayidx2, align 4 %add3 = add nsw i32 %3, %1 @@ -45,10 +45,10 @@ for.body: ; preds = %for.body, %entry store i32 %add3, ptr %arrayidx6, align 16 %add10 = add nsw i32 %add3, %a.088 - %4 = or i64 %0, 1 + %4 = or disjoint i64 %0, 1 %arrayidx13 = getelementptr inbounds i32, ptr %diff, i64 %4 %5 = load i32, ptr %arrayidx13, align 4 - %6 = or i64 %0, 5 + %6 = or disjoint i64 %0, 5 %arrayidx16 = getelementptr inbounds i32, ptr %diff, i64 %6 %7 = load i32, ptr %arrayidx16, align 4 %add17 = add nsw i32 %7, %5 @@ -56,10 +56,10 @@ for.body: ; preds = %for.body, %entry store i32 %add17, ptr %arrayidx20, align 4 %add24 = add nsw i32 %add10, %add17 - %8 = or i64 %0, 2 + %8 = or disjoint i64 %0, 2 %arrayidx27 = getelementptr inbounds i32, ptr %diff, i64 %8 %9 = load i32, ptr %arrayidx27, align 4 - %10 = or i64 %0, 6 + %10 = or disjoint i64 %0, 6 %arrayidx30 = getelementptr inbounds i32, ptr %diff, i64 %10 %11 = load i32, ptr %arrayidx30, align 4 %add31 = add nsw i32 %11, %9 @@ -67,10 +67,10 @@ for.body: ; preds = %for.body, %entry store i32 %add31, ptr %arrayidx34, align 8 %add38 = add nsw i32 %add24, %add31 - %12 = or i64 %0, 3 + %12 = or disjoint i64 %0, 3 %arrayidx41 = getelementptr inbounds i32, ptr %diff, i64 %12 %13 = load i32, ptr %arrayidx41, align 4 - %14 = or i64 %0, 7 + %14 = or disjoint i64 %0, 7 %arrayidx44 = getelementptr inbounds i32, ptr %diff, i64 %14 %15 = load i32, ptr %arrayidx44, align 4 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll b/llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll index 0a2cc76d2e25..6d96d6d29cd5 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll @@ -10,19 +10,19 @@ define i32 @foo(ptr nocapture readonly %diff) #0 { ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[A_088:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[ADD24:%.*]], [[FOR_BODY]] ] -; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[INDVARS_IV]], 3 -; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DIFF:%.*]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4 -; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[DIFF]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[INDVARS_IV]], 3 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DIFF:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i64 [[TMP0]], 4 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[DIFF]], i64 [[TMP1]] ; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [8 x [8 x i32]], ptr [[M2]], i64 0, i64 [[INDVARS_IV]], i64 0 -; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i32>, ptr [[ARRAYIDX2]], align 4 -; CHECK-NEXT: [[TMP7:%.*]] = add nsw <2 x i32> [[TMP6]], [[TMP4]] -; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i32> [[TMP7]], i32 0 -; CHECK-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP8]], [[A_088]] -; CHECK-NEXT: store <2 x i32> [[TMP7]], ptr [[ARRAYIDX6]], align 16 -; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i32> [[TMP7]], i32 1 -; CHECK-NEXT: [[ADD24]] = add nsw i32 [[ADD10]], [[TMP10]] +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr [[ARRAYIDX2]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = add nsw <2 x i32> [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP4]], i32 0 +; CHECK-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP5]], [[A_088]] +; CHECK-NEXT: store <2 x i32> [[TMP4]], ptr [[ARRAYIDX6]], align 16 +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP4]], i32 1 +; CHECK-NEXT: [[ADD24]] = add nsw i32 [[ADD10]], [[TMP6]] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 8 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]] @@ -39,17 +39,17 @@ for.body: ; preds = %for.body, %entry %0 = shl i64 %indvars.iv, 3 %arrayidx = getelementptr inbounds i32, ptr %diff, i64 %0 %1 = load i32, ptr %arrayidx, align 4 - %2 = or i64 %0, 4 + %2 = or disjoint i64 %0, 4 %arrayidx2 = getelementptr inbounds i32, ptr %diff, i64 %2 %3 = load i32, ptr %arrayidx2, align 4 %add3 = add nsw i32 %3, %1 %arrayidx6 = getelementptr inbounds [8 x [8 x i32]], ptr %m2, i64 0, i64 %indvars.iv, i64 0 store i32 %add3, ptr %arrayidx6, align 16 %add10 = add nsw i32 %add3, %a.088 - %4 = or i64 %0, 1 + %4 = or disjoint i64 %0, 1 %arrayidx13 = getelementptr inbounds i32, ptr %diff, i64 %4 %5 = load i32, ptr %arrayidx13, align 4 - %6 = or i64 %0, 5 + %6 = or disjoint i64 %0, 5 %arrayidx16 = getelementptr inbounds i32, ptr %diff, i64 %6 %7 = load i32, ptr %arrayidx16, align 4 %add17 = add nsw i32 %7, %5 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll b/llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll index 87d2a0034156..f682851b0406 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll @@ -9,17 +9,17 @@ define i32 @foo(ptr nocapture readonly %diff) #0 { ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] ; CHECK-NEXT: [[A_088:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[OP_RDX:%.*]], [[FOR_BODY]] ] -; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[INDVARS_IV]], 3 -; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DIFF:%.*]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 4 -; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[DIFF]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[INDVARS_IV]], 3 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[DIFF:%.*]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i64 [[TMP0]], 4 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[DIFF]], i64 [[TMP1]] ; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [8 x [8 x i32]], ptr [[M2]], i64 0, i64 [[INDVARS_IV]], i64 0 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr [[ARRAYIDX2]], align 4 -; CHECK-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[TMP6]], [[TMP4]] -; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr [[ARRAYIDX6]], align 16 -; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]]) -; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP9]], [[A_088]] +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[ARRAYIDX2]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], [[TMP2]] +; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[ARRAYIDX6]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]]) +; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP5]], [[A_088]] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 8 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]] @@ -37,37 +37,37 @@ for.body: ; preds = %for.body, %entry %0 = shl i64 %indvars.iv, 3 %arrayidx = getelementptr inbounds i32, ptr %diff, i64 %0 %1 = load i32, ptr %arrayidx, align 4 - %2 = or i64 %0, 4 + %2 = or disjoint i64 %0, 4 %arrayidx2 = getelementptr inbounds i32, ptr %diff, i64 %2 %3 = load i32, ptr %arrayidx2, align 4 %add3 = add nsw i32 %3, %1 %arrayidx6 = getelementptr inbounds [8 x [8 x i32]], ptr %m2, i64 0, i64 %indvars.iv, i64 0 store i32 %add3, ptr %arrayidx6, align 16 %add10 = add nsw i32 %add3, %a.088 - %4 = or i64 %0, 1 + %4 = or disjoint i64 %0, 1 %arrayidx13 = getelementptr inbounds i32, ptr %diff, i64 %4 %5 = load i32, ptr %arrayidx13, align 4 - %6 = or i64 %0, 5 + %6 = or disjoint i64 %0, 5 %arrayidx16 = getelementptr inbounds i32, ptr %diff, i64 %6 %7 = load i32, ptr %arrayidx16, align 4 %add17 = add nsw i32 %7, %5 %arrayidx20 = getelementptr inbounds [8 x [8 x i32]], ptr %m2, i64 0, i64 %indvars.iv, i64 1 store i32 %add17, ptr %arrayidx20, align 4 %add24 = add nsw i32 %add10, %add17 - %8 = or i64 %0, 2 + %8 = or disjoint i64 %0, 2 %arrayidx27 = getelementptr inbounds i32, ptr %diff, i64 %8 %9 = load i32, ptr %arrayidx27, align 4 - %10 = or i64 %0, 6 + %10 = or disjoint i64 %0, 6 %arrayidx30 = getelementptr inbounds i32, ptr %diff, i64 %10 %11 = load i32, ptr %arrayidx30, align 4 %add31 = add nsw i32 %11, %9 %arrayidx34 = getelementptr inbounds [8 x [8 x i32]], ptr %m2, i64 0, i64 %indvars.iv, i64 2 store i32 %add31, ptr %arrayidx34, align 8 %add38 = add nsw i32 %add24, %add31 - %12 = or i64 %0, 3 + %12 = or disjoint i64 %0, 3 %arrayidx41 = getelementptr inbounds i32, ptr %diff, i64 %12 %13 = load i32, ptr %arrayidx41, align 4 - %14 = or i64 %0, 7 + %14 = or disjoint i64 %0, 7 %arrayidx44 = getelementptr inbounds i32, ptr %diff, i64 %14 %15 = load i32, ptr %arrayidx44, align 4 %add45 = add nsw i32 %15, %13 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/simple-loop.ll b/llvm/test/Transforms/SLPVectorizer/X86/simple-loop.ll index cc7b0dab26ed..89c64d64b9c8 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/simple-loop.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/simple-loop.ll @@ -9,16 +9,16 @@ define i32 @rollable(ptr noalias nocapture %in, ptr noalias nocapture %out, i64 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label [[DOT_CRIT_EDGE:%.*]], label [[DOTLR_PH:%.*]] ; CHECK: .lr.ph: -; CHECK-NEXT: [[I_019:%.*]] = phi i64 [ [[TMP10:%.*]], [[DOTLR_PH]] ], [ 0, [[TMP0:%.*]] ] +; CHECK-NEXT: [[I_019:%.*]] = phi i64 [ [[TMP8:%.*]], [[DOTLR_PH]] ], [ 0, [[TMP0:%.*]] ] ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[I_019]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[IN:%.*]], i64 [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[OUT:%.*]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4 -; CHECK-NEXT: [[TMP7:%.*]] = mul <4 x i32> [[TMP6]], -; CHECK-NEXT: [[TMP8:%.*]] = add <4 x i32> [[TMP7]], -; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP4]], align 4 -; CHECK-NEXT: [[TMP10]] = add i64 [[I_019]], 1 -; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[TMP10]], [[N]] +; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4 +; CHECK-NEXT: [[TMP6:%.*]] = mul <4 x i32> [[TMP5]], +; CHECK-NEXT: [[TMP7:%.*]] = add <4 x i32> [[TMP6]], +; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr [[TMP4]], align 4 +; CHECK-NEXT: [[TMP8]] = add i64 [[I_019]], 1 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[TMP8]], [[N]] ; CHECK-NEXT: br i1 [[EXITCOND]], label [[DOT_CRIT_EDGE]], label [[DOTLR_PH]] ; CHECK: ._crit_edge: ; CHECK-NEXT: ret i32 undef @@ -31,13 +31,13 @@ define i32 @rollable(ptr noalias nocapture %in, ptr noalias nocapture %out, i64 %2 = shl i64 %i.019, 2 %3 = getelementptr inbounds i32, ptr %in, i64 %2 %4 = load i32, ptr %3, align 4 - %5 = or i64 %2, 1 + %5 = or disjoint i64 %2, 1 %6 = getelementptr inbounds i32, ptr %in, i64 %5 %7 = load i32, ptr %6, align 4 - %8 = or i64 %2, 2 + %8 = or disjoint i64 %2, 2 %9 = getelementptr inbounds i32, ptr %in, i64 %8 %10 = load i32, ptr %9, align 4 - %11 = or i64 %2, 3 + %11 = or disjoint i64 %2, 3 %12 = getelementptr inbounds i32, ptr %in, i64 %11 %13 = load i32, ptr %12, align 4 %14 = mul i32 %4, 7 @@ -69,24 +69,24 @@ define i32 @unrollable(ptr %in, ptr %out, i64 %n) nounwind ssp uwtable { ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[N:%.*]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label [[DOT_CRIT_EDGE:%.*]], label [[DOTLR_PH:%.*]] ; CHECK: .lr.ph: -; CHECK-NEXT: [[I_019:%.*]] = phi i64 [ [[TMP18:%.*]], [[DOTLR_PH]] ], [ 0, [[TMP0:%.*]] ] +; CHECK-NEXT: [[I_019:%.*]] = phi i64 [ [[TMP14:%.*]], [[DOTLR_PH]] ], [ 0, [[TMP0:%.*]] ] ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[I_019]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[IN:%.*]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], 2 +; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i64 [[TMP2]], 2 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[IN]], i64 [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[OUT:%.*]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4 -; CHECK-NEXT: [[TMP9:%.*]] = mul <2 x i32> [[TMP8]], -; CHECK-NEXT: [[TMP10:%.*]] = add <2 x i32> [[TMP9]], -; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 [[TMP4]] -; CHECK-NEXT: [[TMP14:%.*]] = load <2 x i32>, ptr [[TMP5]], align 4 -; CHECK-NEXT: [[TMP15:%.*]] = mul <2 x i32> [[TMP14]], -; CHECK-NEXT: [[TMP16:%.*]] = add <2 x i32> [[TMP15]], -; CHECK-NEXT: store <2 x i32> [[TMP10]], ptr [[TMP6]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4 +; CHECK-NEXT: [[TMP8:%.*]] = mul <2 x i32> [[TMP7]], +; CHECK-NEXT: [[TMP9:%.*]] = add <2 x i32> [[TMP8]], +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[OUT]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP11:%.*]] = load <2 x i32>, ptr [[TMP5]], align 4 +; CHECK-NEXT: [[TMP12:%.*]] = mul <2 x i32> [[TMP11]], +; CHECK-NEXT: [[TMP13:%.*]] = add <2 x i32> [[TMP12]], +; CHECK-NEXT: store <2 x i32> [[TMP9]], ptr [[TMP6]], align 4 ; CHECK-NEXT: [[BARRIER:%.*]] = call i32 @goo(i32 0) -; CHECK-NEXT: store <2 x i32> [[TMP16]], ptr [[TMP12]], align 4 -; CHECK-NEXT: [[TMP18]] = add i64 [[I_019]], 1 -; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[TMP18]], [[N]] +; CHECK-NEXT: store <2 x i32> [[TMP13]], ptr [[TMP10]], align 4 +; CHECK-NEXT: [[TMP14]] = add i64 [[I_019]], 1 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[TMP14]], [[N]] ; CHECK-NEXT: br i1 [[EXITCOND]], label [[DOT_CRIT_EDGE]], label [[DOTLR_PH]] ; CHECK: ._crit_edge: ; CHECK-NEXT: ret i32 undef @@ -99,13 +99,13 @@ define i32 @unrollable(ptr %in, ptr %out, i64 %n) nounwind ssp uwtable { %2 = shl i64 %i.019, 2 %3 = getelementptr inbounds i32, ptr %in, i64 %2 %4 = load i32, ptr %3, align 4 - %5 = or i64 %2, 1 + %5 = or disjoint i64 %2, 1 %6 = getelementptr inbounds i32, ptr %in, i64 %5 %7 = load i32, ptr %6, align 4 - %8 = or i64 %2, 2 + %8 = or disjoint i64 %2, 2 %9 = getelementptr inbounds i32, ptr %in, i64 %8 %10 = load i32, ptr %9, align 4 - %11 = or i64 %2, 3 + %11 = or disjoint i64 %2, 3 %12 = getelementptr inbounds i32, ptr %in, i64 %11 %13 = load i32, ptr %12, align 4 %14 = mul i32 %4, 7 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll b/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll index 17dc47ae9b5a..51ce40b7a178 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll @@ -20,7 +20,7 @@ define dso_local void @rftbsub(ptr %a) local_unnamed_addr #0 { entry: %arrayidx6 = getelementptr inbounds double, ptr %a, i64 2 %0 = load double, ptr %arrayidx6, align 8 - %1 = or i64 2, 1 + %1 = or disjoint i64 2, 1 %arrayidx12 = getelementptr inbounds double, ptr %a, i64 %1 %2 = load double, ptr %arrayidx12, align 8 %add16 = fadd double %2, undef diff --git a/llvm/test/Transforms/SimpleLoopUnswitch/2007-08-01-LCSSA.ll b/llvm/test/Transforms/SimpleLoopUnswitch/2007-08-01-LCSSA.ll index 339569484fc8..9e4b33d4c4d5 100644 --- a/llvm/test/Transforms/SimpleLoopUnswitch/2007-08-01-LCSSA.ll +++ b/llvm/test/Transforms/SimpleLoopUnswitch/2007-08-01-LCSSA.ll @@ -1,5 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt < %s -S -passes='loop(simple-loop-unswitch),instcombine' -verify-memoryssa | FileCheck %s +; RUN: opt < %s -S -passes='loop(simple-loop-unswitch),instcombine' -verify-memoryssa | FileCheck %s + +; We do not reach a fixpoint, because we first have to infer nsw on the IV add, +; and could eliminate the icmp slt afterwards, but don't revisit it. @.str9 = external constant [1 x i8] @@ -23,7 +26,7 @@ define i32 @_ZN9Generator6strregEPKc(ptr %this, ptr %s) { ; CHECK-NEXT: br i1 false, label [[BB250]], label [[BB166]] ; CHECK: bb166: ; CHECK-NEXT: [[TMP175:%.*]] = add i32 [[IDX_0:%.*]], 1 -; CHECK-NEXT: [[TMP183:%.*]] = add i32 [[I33_0:%.*]], 1 +; CHECK-NEXT: [[TMP183:%.*]] = add nsw i32 [[I33_0:%.*]], 1 ; CHECK-NEXT: br label [[BB184]] ; CHECK: bb184: ; CHECK-NEXT: [[I33_0]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP183]], [[BB166]] ] diff --git a/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll b/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll index 236b3a8e0780..b5c4b8aa51db 100644 --- a/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll +++ b/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll @@ -322,10 +322,9 @@ define i32 @test_diamond_alias3(ptr %p, ptr %q, i32 %a, i32 %b) { ; CHECK-NEXT: br label [[FALLTHROUGH:%.*]] ; CHECK: no1: ; CHECK-NEXT: call void @f() -; CHECK-NEXT: [[Z1:%.*]] = add i32 [[A]], [[B:%.*]] ; CHECK-NEXT: br label [[FALLTHROUGH]] ; CHECK: fallthrough: -; CHECK-NEXT: [[Z2:%.*]] = phi i32 [ [[Z1]], [[NO1]] ], [ 0, [[YES1]] ] +; CHECK-NEXT: [[Z2:%.*]] = phi i32 [ [[B:%.*]], [[NO1]] ], [ 0, [[YES1]] ] ; CHECK-NEXT: [[X2:%.*]] = icmp eq i32 [[B]], 0 ; CHECK-NEXT: br i1 [[X2]], label [[NO2:%.*]], label [[YES2:%.*]] ; CHECK: yes2: @@ -333,7 +332,7 @@ define i32 @test_diamond_alias3(ptr %p, ptr %q, i32 %a, i32 %b) { ; CHECK-NEXT: br label [[END:%.*]] ; CHECK: no2: ; CHECK-NEXT: call void @f() -; CHECK-NEXT: [[Z3:%.*]] = sub i32 [[Z2]], [[B]] +; CHECK-NEXT: [[Z3:%.*]] = sub nuw nsw i32 [[Z2]], [[B]] ; CHECK-NEXT: br label [[END]] ; CHECK: end: ; CHECK-NEXT: [[Z4:%.*]] = phi i32 [ [[Z3]], [[NO2]] ], [ 3, [[YES2]] ] diff --git a/llvm/test/Transforms/TailCallElim/accum_recursion.ll b/llvm/test/Transforms/TailCallElim/accum_recursion.ll index 6ddb321e6664..c093f026e467 100644 --- a/llvm/test/Transforms/TailCallElim/accum_recursion.ll +++ b/llvm/test/Transforms/TailCallElim/accum_recursion.ll @@ -78,7 +78,7 @@ define i64 @test3_fib(i64 %n) nounwind readnone { ; CHECK-NEXT: ] ; CHECK: bb1: ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N_TR]], -1 -; CHECK-NEXT: [[RECURSE1:%.*]] = tail call i64 @test3_fib(i64 [[TMP0]]) #[[ATTR1:[0-9]+]] +; CHECK-NEXT: [[RECURSE1:%.*]] = tail call i64 @test3_fib(i64 [[TMP0]]) #[[ATTR2:[0-9]+]] ; CHECK-NEXT: [[TMP1]] = add i64 [[N_TR]], -2 ; CHECK-NEXT: [[ACCUMULATE]] = add nsw i64 [[ACCUMULATOR_TR]], [[RECURSE1]] ; CHECK-NEXT: br label [[TAILRECURSE]] @@ -290,3 +290,41 @@ return: %retval.0 = phi i32 [ %accumulate1, %if.then2 ], [ %accumulate2, %if.end3 ], [ 0, %entry ] ret i32 %retval.0 } + +%struct.ListNode = type { i32, ptr } + +; We cannot TRE commutative, non-associative intrinsics +define i32 @test_non_associative_sadd_sat(ptr %a) local_unnamed_addr { +; CHECK-LABEL: define i32 @test_non_associative_sadd_sat( +; CHECK-SAME: ptr [[A:%.*]]) local_unnamed_addr { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq ptr [[A]], null +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[COMMON_RET6:%.*]], label [[IF_END:%.*]] +; CHECK: common.ret6: +; CHECK-NEXT: ret i32 -1 +; CHECK: if.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: [[NEXT:%.*]] = getelementptr inbounds [[STRUCT_LISTNODE:%.*]], ptr [[A]], i64 0, i32 1 +; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[NEXT]], align 8 +; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @test_non_associative_sadd_sat(ptr [[TMP1]]) +; CHECK-NEXT: [[DOTSROA_SPECULATED:%.*]] = tail call i32 @llvm.sadd.sat.i32(i32 [[TMP0]], i32 [[CALL]]) +; CHECK-NEXT: ret i32 [[DOTSROA_SPECULATED]] +; +entry: + %tobool.not = icmp eq ptr %a, null + br i1 %tobool.not, label %common.ret6, label %if.end + +common.ret6: ; preds = %entry, %if.end + %common.ret6.op = phi i32 [ %.sroa.speculated, %if.end ], [ -1, %entry ] + ret i32 %common.ret6.op + +if.end: ; preds = %entry + %0 = load i32, ptr %a + %next = getelementptr inbounds %struct.ListNode, ptr %a, i64 0, i32 1 + %1 = load ptr, ptr %next + %call = tail call i32 @test_non_associative_sadd_sat(ptr %1) + %.sroa.speculated = tail call i32 @llvm.sadd.sat.i32(i32 %0, i32 %call) + br label %common.ret6 +} + +declare i32 @llvm.sadd.sat.i32(i32, i32) diff --git a/llvm/test/Transforms/TailCallElim/tre-minmax-intrinsic.ll b/llvm/test/Transforms/TailCallElim/tre-minmax-intrinsic.ll new file mode 100644 index 000000000000..f8d9f9f9fbcb --- /dev/null +++ b/llvm/test/Transforms/TailCallElim/tre-minmax-intrinsic.ll @@ -0,0 +1,305 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 +; RUN: opt < %s -passes=tailcallelim -verify-dom-info -S | FileCheck %s + +%struct.ListNode = type { i32, ptr } + +define i32 @umin(ptr readonly %a) { +; CHECK-LABEL: define i32 @umin +; CHECK-SAME: (ptr readonly [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[TAILRECURSE:%.*]] +; CHECK: tailrecurse: +; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[DOTSROA_SPECULATED:%.*]], [[IF_END:%.*]] ] +; CHECK-NEXT: [[A_TR:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[TMP1:%.*]], [[IF_END]] ] +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq ptr [[A_TR]], null +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[COMMON_RET6:%.*]], label [[IF_END]] +; CHECK: common.ret6: +; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = tail call i32 @llvm.umin.i32(i32 -1, i32 [[ACCUMULATOR_TR]]) +; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]] +; CHECK: if.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_TR]], align 4 +; CHECK-NEXT: [[NEXT:%.*]] = getelementptr inbounds [[STRUCT_LISTNODE:%.*]], ptr [[A_TR]], i64 0, i32 1 +; CHECK-NEXT: [[TMP1]] = load ptr, ptr [[NEXT]], align 8 +; CHECK-NEXT: [[DOTSROA_SPECULATED]] = tail call i32 @llvm.umin.i32(i32 [[TMP0]], i32 [[ACCUMULATOR_TR]]) +; CHECK-NEXT: br label [[TAILRECURSE]] +; +entry: + %tobool.not = icmp eq ptr %a, null + br i1 %tobool.not, label %common.ret6, label %if.end + +common.ret6: ; preds = %entry, %if.end + %common.ret6.op = phi i32 [ %.sroa.speculated, %if.end ], [ -1, %entry ] + ret i32 %common.ret6.op + +if.end: ; preds = %entry + %0 = load i32, ptr %a + %next = getelementptr inbounds %struct.ListNode, ptr %a, i64 0, i32 1 + %1 = load ptr, ptr %next + %call = tail call i32 @umin(ptr %1) + %.sroa.speculated = tail call i32 @llvm.umin.i32(i32 %0, i32 %call) + br label %common.ret6 +} + +define i32 @umin2(ptr readonly %a) { +; CHECK-LABEL: define i32 @umin2 +; CHECK-SAME: (ptr readonly [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[TAILRECURSE:%.*]] +; CHECK: tailrecurse: +; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[DOTSROA_SPECULATED:%.*]], [[IF_END:%.*]] ] +; CHECK-NEXT: [[A_TR:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[TMP1:%.*]], [[IF_END]] ] +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq ptr [[A_TR]], null +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[COMMON_RET6:%.*]], label [[IF_END]] +; CHECK: common.ret6: +; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = tail call i32 @llvm.umin.i32(i32 [[ACCUMULATOR_TR]], i32 -1) +; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]] +; CHECK: if.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_TR]], align 4 +; CHECK-NEXT: [[NEXT:%.*]] = getelementptr inbounds [[STRUCT_LISTNODE:%.*]], ptr [[A_TR]], i64 0, i32 1 +; CHECK-NEXT: [[TMP1]] = load ptr, ptr [[NEXT]], align 8 +; CHECK-NEXT: [[DOTSROA_SPECULATED]] = tail call i32 @llvm.umin.i32(i32 [[ACCUMULATOR_TR]], i32 [[TMP0]]) +; CHECK-NEXT: br label [[TAILRECURSE]] +; +entry: + %tobool.not = icmp eq ptr %a, null + br i1 %tobool.not, label %common.ret6, label %if.end + +common.ret6: ; preds = %entry, %if.end + %common.ret6.op = phi i32 [ %.sroa.speculated, %if.end ], [ -1, %entry ] + ret i32 %common.ret6.op + +if.end: ; preds = %entry + %0 = load i32, ptr %a + %next = getelementptr inbounds %struct.ListNode, ptr %a, i64 0, i32 1 + %1 = load ptr, ptr %next + %call = tail call i32 @umin2(ptr %1) + %.sroa.speculated = tail call i32 @llvm.umin.i32(i32 %call, i32 %0) + br label %common.ret6 +} + +define i32 @umax(ptr readonly %a) { +; CHECK-LABEL: define i32 @umax +; CHECK-SAME: (ptr readonly [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[TAILRECURSE:%.*]] +; CHECK: tailrecurse: +; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[DOTSROA_SPECULATED:%.*]], [[IF_END:%.*]] ] +; CHECK-NEXT: [[A_TR:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[TMP1:%.*]], [[IF_END]] ] +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq ptr [[A_TR]], null +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[COMMON_RET6:%.*]], label [[IF_END]] +; CHECK: common.ret6: +; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = tail call i32 @llvm.umax.i32(i32 0, i32 [[ACCUMULATOR_TR]]) +; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]] +; CHECK: if.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_TR]], align 4 +; CHECK-NEXT: [[NEXT:%.*]] = getelementptr inbounds [[STRUCT_LISTNODE:%.*]], ptr [[A_TR]], i64 0, i32 1 +; CHECK-NEXT: [[TMP1]] = load ptr, ptr [[NEXT]], align 8 +; CHECK-NEXT: [[DOTSROA_SPECULATED]] = tail call i32 @llvm.umax.i32(i32 [[TMP0]], i32 [[ACCUMULATOR_TR]]) +; CHECK-NEXT: br label [[TAILRECURSE]] +; +entry: + %tobool.not = icmp eq ptr %a, null + br i1 %tobool.not, label %common.ret6, label %if.end + +common.ret6: ; preds = %entry, %if.end + %common.ret6.op = phi i32 [ %.sroa.speculated, %if.end ], [ 0, %entry ] + ret i32 %common.ret6.op + +if.end: ; preds = %entry + %0 = load i32, ptr %a + %next = getelementptr inbounds %struct.ListNode, ptr %a, i64 0, i32 1 + %1 = load ptr, ptr %next + %call = tail call i32 @umax(ptr %1) + %.sroa.speculated = tail call i32 @llvm.umax.i32(i32 %0, i32 %call) + br label %common.ret6 +} + +define i32 @umax2(ptr readonly %a) { +; CHECK-LABEL: define i32 @umax2 +; CHECK-SAME: (ptr readonly [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[TAILRECURSE:%.*]] +; CHECK: tailrecurse: +; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[DOTSROA_SPECULATED:%.*]], [[IF_END:%.*]] ] +; CHECK-NEXT: [[A_TR:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[TMP1:%.*]], [[IF_END]] ] +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq ptr [[A_TR]], null +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[COMMON_RET6:%.*]], label [[IF_END]] +; CHECK: common.ret6: +; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = tail call i32 @llvm.umax.i32(i32 [[ACCUMULATOR_TR]], i32 0) +; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]] +; CHECK: if.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_TR]], align 4 +; CHECK-NEXT: [[NEXT:%.*]] = getelementptr inbounds [[STRUCT_LISTNODE:%.*]], ptr [[A_TR]], i64 0, i32 1 +; CHECK-NEXT: [[TMP1]] = load ptr, ptr [[NEXT]], align 8 +; CHECK-NEXT: [[DOTSROA_SPECULATED]] = tail call i32 @llvm.umax.i32(i32 [[ACCUMULATOR_TR]], i32 [[TMP0]]) +; CHECK-NEXT: br label [[TAILRECURSE]] +; +entry: + %tobool.not = icmp eq ptr %a, null + br i1 %tobool.not, label %common.ret6, label %if.end + +common.ret6: ; preds = %entry, %if.end + %common.ret6.op = phi i32 [ %.sroa.speculated, %if.end ], [ 0, %entry ] + ret i32 %common.ret6.op + +if.end: ; preds = %entry + %0 = load i32, ptr %a + %next = getelementptr inbounds %struct.ListNode, ptr %a, i64 0, i32 1 + %1 = load ptr, ptr %next + %call = tail call i32 @umax2(ptr %1) + %.sroa.speculated = tail call i32 @llvm.umax.i32(i32 %call, i32 %0) + br label %common.ret6 +} + +define i32 @smin(ptr readonly %a) { +; CHECK-LABEL: define i32 @smin +; CHECK-SAME: (ptr readonly [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[TAILRECURSE:%.*]] +; CHECK: tailrecurse: +; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 2147483647, [[ENTRY:%.*]] ], [ [[DOTSROA_SPECULATED:%.*]], [[IF_END:%.*]] ] +; CHECK-NEXT: [[A_TR:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[TMP1:%.*]], [[IF_END]] ] +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq ptr [[A_TR]], null +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[COMMON_RET6:%.*]], label [[IF_END]] +; CHECK: common.ret6: +; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = tail call i32 @llvm.smin.i32(i32 2147483647, i32 [[ACCUMULATOR_TR]]) +; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]] +; CHECK: if.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_TR]], align 4 +; CHECK-NEXT: [[NEXT:%.*]] = getelementptr inbounds [[STRUCT_LISTNODE:%.*]], ptr [[A_TR]], i64 0, i32 1 +; CHECK-NEXT: [[TMP1]] = load ptr, ptr [[NEXT]], align 8 +; CHECK-NEXT: [[DOTSROA_SPECULATED]] = tail call i32 @llvm.smin.i32(i32 [[TMP0]], i32 [[ACCUMULATOR_TR]]) +; CHECK-NEXT: br label [[TAILRECURSE]] +; +entry: + %tobool.not = icmp eq ptr %a, null + br i1 %tobool.not, label %common.ret6, label %if.end + +common.ret6: ; preds = %entry, %if.end + %common.ret6.op = phi i32 [ %.sroa.speculated, %if.end ], [ 2147483647, %entry ] + ret i32 %common.ret6.op + +if.end: ; preds = %entry + %0 = load i32, ptr %a + %next = getelementptr inbounds %struct.ListNode, ptr %a, i64 0, i32 1 + %1 = load ptr, ptr %next + %call = tail call i32 @smin(ptr %1) + %.sroa.speculated = tail call i32 @llvm.smin.i32(i32 %0, i32 %call) + br label %common.ret6 +} + +define i32 @smin2(ptr readonly %a) { +; CHECK-LABEL: define i32 @smin2 +; CHECK-SAME: (ptr readonly [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[TAILRECURSE:%.*]] +; CHECK: tailrecurse: +; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ 2147483647, [[ENTRY:%.*]] ], [ [[DOTSROA_SPECULATED:%.*]], [[IF_END:%.*]] ] +; CHECK-NEXT: [[A_TR:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[TMP1:%.*]], [[IF_END]] ] +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq ptr [[A_TR]], null +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[COMMON_RET6:%.*]], label [[IF_END]] +; CHECK: common.ret6: +; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = tail call i32 @llvm.smin.i32(i32 [[ACCUMULATOR_TR]], i32 2147483647) +; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]] +; CHECK: if.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_TR]], align 4 +; CHECK-NEXT: [[NEXT:%.*]] = getelementptr inbounds [[STRUCT_LISTNODE:%.*]], ptr [[A_TR]], i64 0, i32 1 +; CHECK-NEXT: [[TMP1]] = load ptr, ptr [[NEXT]], align 8 +; CHECK-NEXT: [[DOTSROA_SPECULATED]] = tail call i32 @llvm.smin.i32(i32 [[ACCUMULATOR_TR]], i32 [[TMP0]]) +; CHECK-NEXT: br label [[TAILRECURSE]] +; +entry: + %tobool.not = icmp eq ptr %a, null + br i1 %tobool.not, label %common.ret6, label %if.end + +common.ret6: ; preds = %entry, %if.end + %common.ret6.op = phi i32 [ %.sroa.speculated, %if.end ], [ 2147483647, %entry ] + ret i32 %common.ret6.op + +if.end: ; preds = %entry + %0 = load i32, ptr %a + %next = getelementptr inbounds %struct.ListNode, ptr %a, i64 0, i32 1 + %1 = load ptr, ptr %next + %call = tail call i32 @smin2(ptr %1) + %.sroa.speculated = tail call i32 @llvm.smin.i32(i32 %call, i32 %0) + br label %common.ret6 +} + +define i32 @smax(ptr readonly %a) { +; CHECK-LABEL: define i32 @smax +; CHECK-SAME: (ptr readonly [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[TAILRECURSE:%.*]] +; CHECK: tailrecurse: +; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ -2147483648, [[ENTRY:%.*]] ], [ [[DOTSROA_SPECULATED:%.*]], [[IF_END:%.*]] ] +; CHECK-NEXT: [[A_TR:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[TMP1:%.*]], [[IF_END]] ] +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq ptr [[A_TR]], null +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[COMMON_RET6:%.*]], label [[IF_END]] +; CHECK: common.ret6: +; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = tail call i32 @llvm.smax.i32(i32 -2147483648, i32 [[ACCUMULATOR_TR]]) +; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]] +; CHECK: if.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_TR]], align 4 +; CHECK-NEXT: [[NEXT:%.*]] = getelementptr inbounds [[STRUCT_LISTNODE:%.*]], ptr [[A_TR]], i64 0, i32 1 +; CHECK-NEXT: [[TMP1]] = load ptr, ptr [[NEXT]], align 8 +; CHECK-NEXT: [[DOTSROA_SPECULATED]] = tail call i32 @llvm.smax.i32(i32 [[TMP0]], i32 [[ACCUMULATOR_TR]]) +; CHECK-NEXT: br label [[TAILRECURSE]] +; +entry: + %tobool.not = icmp eq ptr %a, null + br i1 %tobool.not, label %common.ret6, label %if.end + +common.ret6: ; preds = %entry, %if.end + %common.ret6.op = phi i32 [ %.sroa.speculated, %if.end ], [ -2147483648, %entry ] + ret i32 %common.ret6.op + +if.end: ; preds = %entry + %0 = load i32, ptr %a + %next = getelementptr inbounds %struct.ListNode, ptr %a, i64 0, i32 1 + %1 = load ptr, ptr %next + %call = tail call i32 @smax(ptr %1) + %.sroa.speculated = tail call i32 @llvm.smax.i32(i32 %0, i32 %call) + br label %common.ret6 +} + +define i32 @smax2(ptr readonly %a) { +; CHECK-LABEL: define i32 @smax2 +; CHECK-SAME: (ptr readonly [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[TAILRECURSE:%.*]] +; CHECK: tailrecurse: +; CHECK-NEXT: [[ACCUMULATOR_TR:%.*]] = phi i32 [ -2147483648, [[ENTRY:%.*]] ], [ [[DOTSROA_SPECULATED:%.*]], [[IF_END:%.*]] ] +; CHECK-NEXT: [[A_TR:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[TMP1:%.*]], [[IF_END]] ] +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq ptr [[A_TR]], null +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[COMMON_RET6:%.*]], label [[IF_END]] +; CHECK: common.ret6: +; CHECK-NEXT: [[ACCUMULATOR_RET_TR:%.*]] = tail call i32 @llvm.smax.i32(i32 [[ACCUMULATOR_TR]], i32 -2147483648) +; CHECK-NEXT: ret i32 [[ACCUMULATOR_RET_TR]] +; CHECK: if.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_TR]], align 4 +; CHECK-NEXT: [[NEXT:%.*]] = getelementptr inbounds [[STRUCT_LISTNODE:%.*]], ptr [[A_TR]], i64 0, i32 1 +; CHECK-NEXT: [[TMP1]] = load ptr, ptr [[NEXT]], align 8 +; CHECK-NEXT: [[DOTSROA_SPECULATED]] = tail call i32 @llvm.smax.i32(i32 [[ACCUMULATOR_TR]], i32 [[TMP0]]) +; CHECK-NEXT: br label [[TAILRECURSE]] +; +entry: + %tobool.not = icmp eq ptr %a, null + br i1 %tobool.not, label %common.ret6, label %if.end + +common.ret6: ; preds = %entry, %if.end + %common.ret6.op = phi i32 [ %.sroa.speculated, %if.end ], [ -2147483648, %entry ] + ret i32 %common.ret6.op + +if.end: ; preds = %entry + %0 = load i32, ptr %a + %next = getelementptr inbounds %struct.ListNode, ptr %a, i64 0, i32 1 + %1 = load ptr, ptr %next + %call = tail call i32 @smax2(ptr %1) + %.sroa.speculated = tail call i32 @llvm.smax.i32(i32 %call, i32 %0) + br label %common.ret6 +} + +declare i32 @llvm.umin.i32(i32, i32) +declare i32 @llvm.umax.i32(i32, i32) +declare i32 @llvm.smin.i32(i32, i32) +declare i32 @llvm.smax.i32(i32, i32) diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s new file mode 100644 index 000000000000..cb60d8ea935a --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s @@ -0,0 +1,65 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-u74 -timeline -iterations=1 < %s \ +# RUN: | FileCheck %s + +div a0, a1, a2 +fdiv.s f1, f2, f3 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 67 +# CHECK-NEXT: Total uOps: 2 + +# CHECK: Dispatch Width: 2 +# CHECK-NEXT: uOps Per Cycle: 0.03 +# CHECK-NEXT: IPC: 0.03 +# CHECK-NEXT: Block RThroughput: 65.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 66 65.00 div a0, a1, a2 +# CHECK-NEXT: 1 27 26.00 fdiv.s ft1, ft2, ft3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFive7FDiv +# CHECK-NEXT: [1] - SiFive7IDiv +# CHECK-NEXT: [2] - SiFive7PipeA +# CHECK-NEXT: [3] - SiFive7PipeB +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ +# CHECK-NEXT: [6] - SiFive7VL +# CHECK-NEXT: [7] - SiFive7VS + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] +# CHECK-NEXT: 26.00 65.00 - 2.00 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: +# CHECK-NEXT: - 65.00 - 1.00 - - - - div a0, a1, a2 +# CHECK-NEXT: 26.00 - - 1.00 - - - - fdiv.s ft1, ft2, ft3 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456 + +# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeE div a0, a1, a2 +# CHECK-NEXT: [0,1] . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeeeeE fdiv.s ft1, ft2, ft3 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 0.0 0.0 0.0 div a0, a1, a2 +# CHECK-NEXT: 1. 1 0.0 0.0 0.0 fdiv.s ft1, ft2, ft3 +# CHECK-NEXT: 1 0.0 0.0 0.0 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s index 86b7e51b4058..c7ff5e6a6b9c 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s @@ -70,8 +70,8 @@ c.jr a0 # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s index 491e3bb1aa67..892a5d14e8f3 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s @@ -218,8 +218,8 @@ jr a0 # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s index 11d0fbed8724..a6b756ba8151 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s @@ -223,13 +223,13 @@ vfredmin.vs v4, v8, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 206 -# CHECK-NEXT: Total Cycles: 8644 +# CHECK-NEXT: Total Cycles: 8746 # CHECK-NEXT: Total uOps: 206 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.02 # CHECK-NEXT: IPC: 0.02 -# CHECK-NEXT: Block RThroughput: 8640.0 +# CHECK-NEXT: Block RThroughput: 8743.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -241,431 +241,431 @@ vfredmin.vs v4, v8, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 46 46.00 vredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 46 46.00 vredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 46 46.00 vredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 47 47.00 vredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 47 48.00 vredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 49 49.00 vredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 49 50.00 vredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 53 53.00 vredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 53 54.00 vredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 61 61.00 vredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 61 62.00 vredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 41 41.00 vredand.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vredand.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 41 41.00 vredand.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vredand.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 42 42.00 vredand.vs v4, v8, v12 +# CHECK-NEXT: 1 42 43.00 vredand.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 44 44.00 vredand.vs v4, v8, v12 +# CHECK-NEXT: 1 44 45.00 vredand.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 48 48.00 vredand.vs v4, v8, v12 +# CHECK-NEXT: 1 48 49.00 vredand.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 56 56.00 vredand.vs v4, v8, v12 +# CHECK-NEXT: 1 56 57.00 vredand.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 36 36.00 vredor.vs v4, v8, v12 +# CHECK-NEXT: 1 36 37.00 vredor.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 37 37.00 vredor.vs v4, v8, v12 +# CHECK-NEXT: 1 37 38.00 vredor.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 39 39.00 vredor.vs v4, v8, v12 +# CHECK-NEXT: 1 39 40.00 vredor.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 43 43.00 vredor.vs v4, v8, v12 +# CHECK-NEXT: 1 43 44.00 vredor.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 51 51.00 vredor.vs v4, v8, v12 +# CHECK-NEXT: 1 51 52.00 vredor.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 32 32.00 vredxor.vs v4, v8, v12 +# CHECK-NEXT: 1 32 33.00 vredxor.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 34 34.00 vredxor.vs v4, v8, v12 +# CHECK-NEXT: 1 34 35.00 vredxor.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 38 38.00 vredxor.vs v4, v8, v12 +# CHECK-NEXT: 1 38 39.00 vredxor.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 46 46.00 vredxor.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vredxor.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 46 46.00 vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vredmaxu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 46 46.00 vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vredmaxu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 46 46.00 vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vredmaxu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 47 47.00 vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: 1 47 48.00 vredmaxu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 49 49.00 vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: 1 49 50.00 vredmaxu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 53 53.00 vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: 1 53 54.00 vredmaxu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 61 61.00 vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: 1 61 62.00 vredmaxu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 41 41.00 vredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 41 41.00 vredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 42 42.00 vredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 42 43.00 vredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 44 44.00 vredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 44 45.00 vredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 48 48.00 vredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 48 49.00 vredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 56 56.00 vredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 56 57.00 vredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 36 36.00 vredminu.vs v4, v8, v12 +# CHECK-NEXT: 1 36 37.00 vredminu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 37 37.00 vredminu.vs v4, v8, v12 +# CHECK-NEXT: 1 37 38.00 vredminu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 39 39.00 vredminu.vs v4, v8, v12 +# CHECK-NEXT: 1 39 40.00 vredminu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 43 43.00 vredminu.vs v4, v8, v12 +# CHECK-NEXT: 1 43 44.00 vredminu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 51 51.00 vredminu.vs v4, v8, v12 +# CHECK-NEXT: 1 51 52.00 vredminu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 32 32.00 vredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 32 33.00 vredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 34 34.00 vredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 34 35.00 vredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 38 38.00 vredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 38 39.00 vredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 46 46.00 vredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 46 46.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 46 46.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 46 46.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 47 47.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 47 48.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 49 49.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 49 50.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 53 53.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 53 54.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 61 61.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 61 62.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 41 41.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 41 41.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 42 42.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 42 43.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 44 44.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 44 45.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 48 48.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 48 49.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 56 56.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 56 57.00 vwredsumu.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 36 36.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 36 37.00 vwredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 37 37.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 37 38.00 vwredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 39 39.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 39 40.00 vwredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 43 43.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 43 44.00 vwredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 51 51.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 51 52.00 vwredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 61 61.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 61 62.00 vwredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 61 61.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 61 62.00 vwredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 61 61.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 61 62.00 vwredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 61 61.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 61 62.00 vwredsum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 48 48.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 48 49.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 96 96.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 96 97.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 192 192.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 192 193.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 384 384.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 384 385.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 768 768.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 768 769.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1536 1536.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 1536 1537.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 48 48.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 48 49.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 96 96.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 96 97.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 192 192.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 192 193.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 384 384.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 384 385.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 768 768.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 768 769.00 vfwredosum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 41 41.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 41 41.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 42 42.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 42 43.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 44 44.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 44 45.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 48 48.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 48 49.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 56 56.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 56 57.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 36 36.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 36 37.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 37 37.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 37 38.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 39 39.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 39 40.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 43 43.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 43 44.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 51 51.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 51 52.00 vfwredusum.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 41 41.00 vfredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vfredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 41 41.00 vfredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 41 42.00 vfredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 42 42.00 vfredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 42 43.00 vfredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 44 44.00 vfredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 44 45.00 vfredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 48 48.00 vfredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 48 49.00 vfredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 56 56.00 vfredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 56 57.00 vfredmax.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 36 36.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 36 37.00 vfredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 37 37.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 37 38.00 vfredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 39 39.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 39 40.00 vfredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 43 43.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 43 44.00 vfredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 51 51.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 51 52.00 vfredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 32 32.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 32 33.00 vfredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 34 34.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 34 35.00 vfredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 38 38.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 38 39.00 vfredmin.vs v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 46 46.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 46 47.00 vfredmin.vs v4, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 103.00 - 8640.00 8640.00 - - +# CHECK-NEXT: - - 103.00 - 8743.00 103.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 47.00 47.00 - - vredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 48.00 1.00 - - vredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 49.00 49.00 - - vredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 50.00 1.00 - - vredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 53.00 53.00 - - vredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 54.00 1.00 - - vredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 61.00 61.00 - - vredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 62.00 1.00 - - vredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vredand.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vredand.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vredand.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vredand.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 42.00 42.00 - - vredand.vs v4, v8, v12 +# CHECK-NEXT: - - - - 43.00 1.00 - - vredand.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 44.00 44.00 - - vredand.vs v4, v8, v12 +# CHECK-NEXT: - - - - 45.00 1.00 - - vredand.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 48.00 48.00 - - vredand.vs v4, v8, v12 +# CHECK-NEXT: - - - - 49.00 1.00 - - vredand.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 56.00 56.00 - - vredand.vs v4, v8, v12 +# CHECK-NEXT: - - - - 57.00 1.00 - - vredand.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 36.00 36.00 - - vredor.vs v4, v8, v12 +# CHECK-NEXT: - - - - 37.00 1.00 - - vredor.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 37.00 37.00 - - vredor.vs v4, v8, v12 +# CHECK-NEXT: - - - - 38.00 1.00 - - vredor.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 39.00 39.00 - - vredor.vs v4, v8, v12 +# CHECK-NEXT: - - - - 40.00 1.00 - - vredor.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 43.00 43.00 - - vredor.vs v4, v8, v12 +# CHECK-NEXT: - - - - 44.00 1.00 - - vredor.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 51.00 51.00 - - vredor.vs v4, v8, v12 +# CHECK-NEXT: - - - - 52.00 1.00 - - vredor.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 32.00 32.00 - - vredxor.vs v4, v8, v12 +# CHECK-NEXT: - - - - 33.00 1.00 - - vredxor.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 34.00 34.00 - - vredxor.vs v4, v8, v12 +# CHECK-NEXT: - - - - 35.00 1.00 - - vredxor.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 38.00 38.00 - - vredxor.vs v4, v8, v12 +# CHECK-NEXT: - - - - 39.00 1.00 - - vredxor.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vredxor.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vredxor.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vredmaxu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vredmaxu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vredmaxu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 47.00 47.00 - - vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 48.00 1.00 - - vredmaxu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 49.00 49.00 - - vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 50.00 1.00 - - vredmaxu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 53.00 53.00 - - vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 54.00 1.00 - - vredmaxu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 61.00 61.00 - - vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 62.00 1.00 - - vredmaxu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 42.00 42.00 - - vredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 43.00 1.00 - - vredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 44.00 44.00 - - vredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 45.00 1.00 - - vredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 48.00 48.00 - - vredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 49.00 1.00 - - vredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 56.00 56.00 - - vredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 57.00 1.00 - - vredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 36.00 36.00 - - vredminu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 37.00 1.00 - - vredminu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 37.00 37.00 - - vredminu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 38.00 1.00 - - vredminu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 39.00 39.00 - - vredminu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 40.00 1.00 - - vredminu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 43.00 43.00 - - vredminu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 44.00 1.00 - - vredminu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 51.00 51.00 - - vredminu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 52.00 1.00 - - vredminu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 32.00 32.00 - - vredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 33.00 1.00 - - vredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 34.00 34.00 - - vredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 35.00 1.00 - - vredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 38.00 38.00 - - vredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 39.00 1.00 - - vredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 47.00 47.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 48.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 49.00 49.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 50.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 53.00 53.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 54.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 61.00 61.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 62.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 42.00 42.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 43.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 44.00 44.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 45.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 48.00 48.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 49.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 56.00 56.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - - - 57.00 1.00 - - vwredsumu.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 36.00 36.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 37.00 1.00 - - vwredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 37.00 37.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 38.00 1.00 - - vwredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 39.00 39.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 40.00 1.00 - - vwredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 43.00 43.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 44.00 1.00 - - vwredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 51.00 51.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 52.00 1.00 - - vwredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 61.00 61.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 62.00 1.00 - - vwredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 61.00 61.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 62.00 1.00 - - vwredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 61.00 61.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 62.00 1.00 - - vwredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 61.00 61.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 62.00 1.00 - - vwredsum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 48.00 48.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 49.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 96.00 96.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 97.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 192.00 192.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 193.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 384.00 384.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 385.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 768.00 768.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 769.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 1536.00 1536.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 1537.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 48.00 48.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 49.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 96.00 96.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 97.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 192.00 192.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 193.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 384.00 384.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 385.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 768.00 768.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 769.00 1.00 - - vfwredosum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 42.00 42.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 43.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 44.00 44.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 45.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 48.00 48.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 49.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 56.00 56.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 36.00 36.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 37.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 37.00 37.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 38.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 39.00 39.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 40.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 43.00 43.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 44.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 51.00 51.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - - - 52.00 1.00 - - vfwredusum.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vfredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vfredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 41.00 41.00 - - vfredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 42.00 1.00 - - vfredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 42.00 42.00 - - vfredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 43.00 1.00 - - vfredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 44.00 44.00 - - vfredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 45.00 1.00 - - vfredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 48.00 48.00 - - vfredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 49.00 1.00 - - vfredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 56.00 56.00 - - vfredmax.vs v4, v8, v12 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfredmax.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 36.00 36.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 37.00 1.00 - - vfredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 37.00 37.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 38.00 1.00 - - vfredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 39.00 39.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 40.00 1.00 - - vfredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 43.00 43.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 44.00 1.00 - - vfredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 51.00 51.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 52.00 1.00 - - vfredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 32.00 32.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 33.00 1.00 - - vfredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 34.00 34.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 35.00 1.00 - - vfredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 38.00 38.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 39.00 1.00 - - vfredmin.vs v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 46.00 46.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - - - 47.00 1.00 - - vfredmin.vs v4, v8, v12 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-x0.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-x0.s index 41a6935873ad..eace2ad12d65 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-x0.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-x0.s @@ -37,13 +37,13 @@ vle64.v v1, (a1) # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 26 -# CHECK-NEXT: Total Cycles: 3523 +# CHECK-NEXT: Total Cycles: 3546 # CHECK-NEXT: Total uOps: 26 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.01 # CHECK-NEXT: IPC: 0.01 -# CHECK-NEXT: Block RThroughput: 3517.0 +# CHECK-NEXT: Block RThroughput: 3541.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -55,71 +55,71 @@ vle64.v v1, (a1) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 515 512.00 * vlse8.v v1, (a1), a2 -# CHECK-NEXT: 1 259 256.00 * vlse16.v v1, (a1), a2 -# CHECK-NEXT: 1 19 16.00 * vlse32.v v1, (a1), a2 -# CHECK-NEXT: 1 67 64.00 * vlse64.v v1, (a1), a2 -# CHECK-NEXT: 1 515 512.00 * vlse8.v v1, (a1), zero -# CHECK-NEXT: 1 259 256.00 * vlse16.v v1, (a1), zero -# CHECK-NEXT: 1 19 16.00 * vlse32.v v1, (a1), zero -# CHECK-NEXT: 1 67 64.00 * vlse64.v v1, (a1), zero -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a1) -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a1) -# CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a1) -# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a1) +# CHECK-NEXT: 1 515 513.00 * vlse8.v v1, (a1), a2 +# CHECK-NEXT: 1 259 257.00 * vlse16.v v1, (a1), a2 +# CHECK-NEXT: 1 19 17.00 * vlse32.v v1, (a1), a2 +# CHECK-NEXT: 1 67 65.00 * vlse64.v v1, (a1), a2 +# CHECK-NEXT: 1 515 513.00 * vlse8.v v1, (a1), zero +# CHECK-NEXT: 1 259 257.00 * vlse16.v v1, (a1), zero +# CHECK-NEXT: 1 19 17.00 * vlse32.v v1, (a1), zero +# CHECK-NEXT: 1 67 65.00 * vlse64.v v1, (a1), zero +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a1) +# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a1) +# CHECK-NEXT: 1 4 3.00 * vle32.v v1, (a1) +# CHECK-NEXT: 1 4 5.00 * vle64.v v1, (a1) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 515 512.00 * vlse8.v v1, (a1), a2 -# CHECK-NEXT: 1 259 256.00 * vlse16.v v1, (a1), a2 -# CHECK-NEXT: 1 131 128.00 * vlse32.v v1, (a1), a2 -# CHECK-NEXT: 1 11 8.00 * vlse64.v v1, (a1), a2 -# CHECK-NEXT: 1 515 512.00 * vlse8.v v1, (a1), zero -# CHECK-NEXT: 1 259 256.00 * vlse16.v v1, (a1), zero -# CHECK-NEXT: 1 131 128.00 * vlse32.v v1, (a1), zero -# CHECK-NEXT: 1 11 8.00 * vlse64.v v1, (a1), zero -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a1) -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a1) -# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a1) -# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a1) +# CHECK-NEXT: 1 515 513.00 * vlse8.v v1, (a1), a2 +# CHECK-NEXT: 1 259 257.00 * vlse16.v v1, (a1), a2 +# CHECK-NEXT: 1 131 129.00 * vlse32.v v1, (a1), a2 +# CHECK-NEXT: 1 11 9.00 * vlse64.v v1, (a1), a2 +# CHECK-NEXT: 1 515 513.00 * vlse8.v v1, (a1), zero +# CHECK-NEXT: 1 259 257.00 * vlse16.v v1, (a1), zero +# CHECK-NEXT: 1 131 129.00 * vlse32.v v1, (a1), zero +# CHECK-NEXT: 1 11 9.00 * vlse64.v v1, (a1), zero +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a1) +# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a1) +# CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a1) +# CHECK-NEXT: 1 4 3.00 * vle64.v v1, (a1) # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 2.00 - 3517.00 - 3517.00 - +# CHECK-NEXT: - - 2.00 - - 24.00 3541.00 - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 512.00 - 512.00 - vlse8.v v1, (a1), a2 -# CHECK-NEXT: - - - - 256.00 - 256.00 - vlse16.v v1, (a1), a2 -# CHECK-NEXT: - - - - 16.00 - 16.00 - vlse32.v v1, (a1), a2 -# CHECK-NEXT: - - - - 64.00 - 64.00 - vlse64.v v1, (a1), a2 -# CHECK-NEXT: - - - - 512.00 - 512.00 - vlse8.v v1, (a1), zero -# CHECK-NEXT: - - - - 256.00 - 256.00 - vlse16.v v1, (a1), zero -# CHECK-NEXT: - - - - 16.00 - 16.00 - vlse32.v v1, (a1), zero -# CHECK-NEXT: - - - - 64.00 - 64.00 - vlse64.v v1, (a1), zero -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a1) -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a1) -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle32.v v1, (a1) -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle64.v v1, (a1) +# CHECK-NEXT: - - - - - 1.00 513.00 - vlse8.v v1, (a1), a2 +# CHECK-NEXT: - - - - - 1.00 257.00 - vlse16.v v1, (a1), a2 +# CHECK-NEXT: - - - - - 1.00 17.00 - vlse32.v v1, (a1), a2 +# CHECK-NEXT: - - - - - 1.00 65.00 - vlse64.v v1, (a1), a2 +# CHECK-NEXT: - - - - - 1.00 513.00 - vlse8.v v1, (a1), zero +# CHECK-NEXT: - - - - - 1.00 257.00 - vlse16.v v1, (a1), zero +# CHECK-NEXT: - - - - - 1.00 17.00 - vlse32.v v1, (a1), zero +# CHECK-NEXT: - - - - - 1.00 65.00 - vlse64.v v1, (a1), zero +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a1) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a1) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle32.v v1, (a1) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle64.v v1, (a1) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 512.00 - 512.00 - vlse8.v v1, (a1), a2 -# CHECK-NEXT: - - - - 256.00 - 256.00 - vlse16.v v1, (a1), a2 -# CHECK-NEXT: - - - - 128.00 - 128.00 - vlse32.v v1, (a1), a2 -# CHECK-NEXT: - - - - 8.00 - 8.00 - vlse64.v v1, (a1), a2 -# CHECK-NEXT: - - - - 512.00 - 512.00 - vlse8.v v1, (a1), zero -# CHECK-NEXT: - - - - 256.00 - 256.00 - vlse16.v v1, (a1), zero -# CHECK-NEXT: - - - - 128.00 - 128.00 - vlse32.v v1, (a1), zero -# CHECK-NEXT: - - - - 8.00 - 8.00 - vlse64.v v1, (a1), zero -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a1) -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a1) -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a1) -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle64.v v1, (a1) +# CHECK-NEXT: - - - - - 1.00 513.00 - vlse8.v v1, (a1), a2 +# CHECK-NEXT: - - - - - 1.00 257.00 - vlse16.v v1, (a1), a2 +# CHECK-NEXT: - - - - - 1.00 129.00 - vlse32.v v1, (a1), a2 +# CHECK-NEXT: - - - - - 1.00 9.00 - vlse64.v v1, (a1), a2 +# CHECK-NEXT: - - - - - 1.00 513.00 - vlse8.v v1, (a1), zero +# CHECK-NEXT: - - - - - 1.00 257.00 - vlse16.v v1, (a1), zero +# CHECK-NEXT: - - - - - 1.00 129.00 - vlse32.v v1, (a1), zero +# CHECK-NEXT: - - - - - 1.00 9.00 - vlse64.v v1, (a1), zero +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a1) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a1) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle32.v v1, (a1) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle64.v v1, (a1) diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s index 716f0f12f433..21459bc45d45 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s @@ -755,13 +755,13 @@ vmv.v.v v4, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 707 -# CHECK-NEXT: Total Cycles: 11753 +# CHECK-NEXT: Total Cycles: 11962 # CHECK-NEXT: Total uOps: 707 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.06 # CHECK-NEXT: IPC: 0.06 -# CHECK-NEXT: Block RThroughput: 11175.0 +# CHECK-NEXT: Block RThroughput: 11549.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -773,1433 +773,1433 @@ vmv.v.v v4, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vadd.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vadd.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vadd.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vadd.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vadd.vi v4, v8, 0 +# CHECK-NEXT: 1 4 2.00 vadd.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vsub.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vsub.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vsub.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vsub.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vrsub.vx v4, v8, a0 +# CHECK-NEXT: 1 4 9.00 vrsub.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vrsub.vi v4, v8, 0 +# CHECK-NEXT: 1 4 17.00 vrsub.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vadd.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vadd.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vadd.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vadd.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vi v4, v8, 0 +# CHECK-NEXT: 1 4 3.00 vadd.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vsub.vv v4, v8, v12 +# CHECK-NEXT: 1 4 5.00 vsub.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vsub.vx v4, v8, a0 +# CHECK-NEXT: 1 4 9.00 vsub.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vrsub.vx v4, v8, a0 +# CHECK-NEXT: 1 4 17.00 vrsub.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vrsub.vi v4, v8, 0 +# CHECK-NEXT: 1 4 2.00 vrsub.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vadd.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vadd.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vadd.vi v4, v8, 0 +# CHECK-NEXT: 1 4 9.00 vadd.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vsub.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vsub.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vsub.vx v4, v8, a0 +# CHECK-NEXT: 1 4 3.00 vsub.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vrsub.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vrsub.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vrsub.vi v4, v8, 0 +# CHECK-NEXT: 1 4 9.00 vrsub.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vadd.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vadd.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 8 1.00 vwaddu.vv v4, v8, v12 +# CHECK-NEXT: 1 8 2.00 vwaddu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 8 1.00 vwaddu.vx v4, v8, a0 +# CHECK-NEXT: 1 8 2.00 vwaddu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 8 1.00 vwsubu.vv v4, v8, v12 +# CHECK-NEXT: 1 8 2.00 vwsubu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 8 2.00 vwsubu.vx v4, v8, a0 +# CHECK-NEXT: 1 8 3.00 vwsubu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 8 4.00 vwadd.vv v4, v8, v12 +# CHECK-NEXT: 1 8 5.00 vwadd.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 vwadd.vx v4, v8, a0 +# CHECK-NEXT: 1 8 9.00 vwadd.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 8 8.00 vwsub.vv v4, v8, v12 +# CHECK-NEXT: 1 8 9.00 vwsub.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 8 1.00 vwsub.vx v4, v8, a0 +# CHECK-NEXT: 1 8 2.00 vwsub.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 8 1.00 vwaddu.wv v4, v8, v12 +# CHECK-NEXT: 1 8 2.00 vwaddu.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 8 2.00 vwaddu.wx v4, v8, a0 +# CHECK-NEXT: 1 8 3.00 vwaddu.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 8 4.00 vwsubu.wv v4, v8, v12 +# CHECK-NEXT: 1 8 5.00 vwsubu.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 vwsubu.wx v4, v8, a0 +# CHECK-NEXT: 1 8 9.00 vwsubu.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 8 8.00 vwadd.wv v4, v8, v12 +# CHECK-NEXT: 1 8 9.00 vwadd.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 8 1.00 vwadd.wx v4, v8, a0 +# CHECK-NEXT: 1 8 2.00 vwadd.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 8 2.00 vwsub.wv v4, v8, v12 +# CHECK-NEXT: 1 8 3.00 vwsub.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 8 4.00 vwsub.wx v4, v8, a0 +# CHECK-NEXT: 1 8 5.00 vwsub.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 vwaddu.vv v4, v8, v12 +# CHECK-NEXT: 1 8 9.00 vwaddu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 8 8.00 vwaddu.vx v4, v8, a0 +# CHECK-NEXT: 1 8 9.00 vwaddu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 1.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 2.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 2.00 vsext.vf2 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 1.00 vsext.vf2 v4, v8 -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu # CHECK-NEXT: 1 4 2.00 vzext.vf2 v4, v8 # CHECK-NEXT: 1 4 2.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: 1 4 3.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 3.00 vsext.vf2 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 4.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 5.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 5.00 vsext.vf2 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 8.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 9.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 9.00 vsext.vf2 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 17.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 17.00 vsext.vf2 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 1.00 vsext.vf2 v4, v8 -# CHECK-NEXT: 1 4 1.00 vzext.vf4 v4, v8 -# CHECK-NEXT: 1 4 1.00 vsext.vf4 v4, v8 -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu # CHECK-NEXT: 1 4 2.00 vzext.vf2 v4, v8 # CHECK-NEXT: 1 4 2.00 vsext.vf2 v4, v8 # CHECK-NEXT: 1 4 2.00 vzext.vf4 v4, v8 # CHECK-NEXT: 1 4 2.00 vsext.vf4 v4, v8 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 4 3.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 3.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 3.00 vzext.vf4 v4, v8 +# CHECK-NEXT: 1 4 3.00 vsext.vf4 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 4.00 vsext.vf2 v4, v8 -# CHECK-NEXT: 1 4 4.00 vzext.vf4 v4, v8 -# CHECK-NEXT: 1 4 4.00 vsext.vf4 v4, v8 +# CHECK-NEXT: 1 4 5.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 5.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 5.00 vzext.vf4 v4, v8 +# CHECK-NEXT: 1 4 5.00 vsext.vf4 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 8.00 vsext.vf2 v4, v8 -# CHECK-NEXT: 1 4 8.00 vzext.vf4 v4, v8 -# CHECK-NEXT: 1 4 8.00 vsext.vf4 v4, v8 +# CHECK-NEXT: 1 4 9.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 9.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 9.00 vzext.vf4 v4, v8 +# CHECK-NEXT: 1 4 9.00 vsext.vf4 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8 -# CHECK-NEXT: 1 4 16.00 vzext.vf4 v4, v8 -# CHECK-NEXT: 1 4 16.00 vsext.vf4 v4, v8 +# CHECK-NEXT: 1 4 17.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 17.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 17.00 vzext.vf4 v4, v8 +# CHECK-NEXT: 1 4 17.00 vsext.vf4 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 2.00 vsext.vf2 v4, v8 -# CHECK-NEXT: 1 4 2.00 vzext.vf4 v4, v8 -# CHECK-NEXT: 1 4 2.00 vsext.vf4 v4, v8 -# CHECK-NEXT: 1 4 2.00 vzext.vf8 v4, v8 -# CHECK-NEXT: 1 4 2.00 vsext.vf8 v4, v8 +# CHECK-NEXT: 1 4 3.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 3.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 3.00 vzext.vf4 v4, v8 +# CHECK-NEXT: 1 4 3.00 vsext.vf4 v4, v8 +# CHECK-NEXT: 1 4 3.00 vzext.vf8 v4, v8 +# CHECK-NEXT: 1 4 3.00 vsext.vf8 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 4.00 vsext.vf2 v4, v8 -# CHECK-NEXT: 1 4 4.00 vzext.vf4 v4, v8 -# CHECK-NEXT: 1 4 4.00 vsext.vf4 v4, v8 -# CHECK-NEXT: 1 4 4.00 vzext.vf8 v4, v8 -# CHECK-NEXT: 1 4 4.00 vsext.vf8 v4, v8 +# CHECK-NEXT: 1 4 5.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 5.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 5.00 vzext.vf4 v4, v8 +# CHECK-NEXT: 1 4 5.00 vsext.vf4 v4, v8 +# CHECK-NEXT: 1 4 5.00 vzext.vf8 v4, v8 +# CHECK-NEXT: 1 4 5.00 vsext.vf8 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 8.00 vsext.vf2 v4, v8 -# CHECK-NEXT: 1 4 8.00 vzext.vf4 v4, v8 -# CHECK-NEXT: 1 4 8.00 vsext.vf4 v4, v8 -# CHECK-NEXT: 1 4 8.00 vzext.vf8 v4, v8 -# CHECK-NEXT: 1 4 8.00 vsext.vf8 v4, v8 +# CHECK-NEXT: 1 4 9.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 9.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 9.00 vzext.vf4 v4, v8 +# CHECK-NEXT: 1 4 9.00 vsext.vf4 v4, v8 +# CHECK-NEXT: 1 4 9.00 vzext.vf8 v4, v8 +# CHECK-NEXT: 1 4 9.00 vsext.vf8 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vzext.vf2 v4, v8 -# CHECK-NEXT: 1 4 16.00 vsext.vf2 v4, v8 -# CHECK-NEXT: 1 4 16.00 vzext.vf4 v4, v8 -# CHECK-NEXT: 1 4 16.00 vsext.vf4 v4, v8 -# CHECK-NEXT: 1 4 16.00 vzext.vf8 v4, v8 -# CHECK-NEXT: 1 4 16.00 vsext.vf8 v4, v8 +# CHECK-NEXT: 1 4 17.00 vzext.vf2 v4, v8 +# CHECK-NEXT: 1 4 17.00 vsext.vf2 v4, v8 +# CHECK-NEXT: 1 4 17.00 vzext.vf4 v4, v8 +# CHECK-NEXT: 1 4 17.00 vsext.vf4 v4, v8 +# CHECK-NEXT: 1 4 17.00 vzext.vf8 v4, v8 +# CHECK-NEXT: 1 4 17.00 vsext.vf8 v4, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vadc.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 2.00 vadc.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vadc.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 2.00 vadc.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vadc.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 2.00 vadc.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmadc.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 3.00 vmadc.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmadc.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 5.00 vmadc.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmadc.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 9.00 vmadc.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmadc.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vmadc.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmadc.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vmadc.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmadc.vi v4, v8, 0 +# CHECK-NEXT: 1 4 2.00 vmadc.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vsbc.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 3.00 vsbc.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vsbc.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 5.00 vsbc.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmsbc.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 9.00 vmsbc.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmsbc.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 17.00 vmsbc.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmsbc.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vmsbc.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmsbc.vx v4, v8, a0 +# CHECK-NEXT: 1 4 3.00 vmsbc.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vadc.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 5.00 vadc.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vadc.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 9.00 vadc.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vadc.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 17.00 vadc.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmadc.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 3.00 vmadc.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmadc.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 5.00 vmadc.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmadc.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 9.00 vmadc.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmadc.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vmadc.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vand.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vand.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vand.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vand.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vand.vi v4, v8, 0 +# CHECK-NEXT: 1 4 2.00 vand.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vor.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vor.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vor.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vor.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vor.vi v4, v8, 0 +# CHECK-NEXT: 1 4 9.00 vor.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vxor.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vxor.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vxor.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vxor.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vxor.vi v4, v8, 0 +# CHECK-NEXT: 1 4 2.00 vxor.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vand.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vand.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vand.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vand.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vand.vi v4, v8, 0 +# CHECK-NEXT: 1 4 9.00 vand.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vor.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vor.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vor.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vor.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vor.vi v4, v8, 0 +# CHECK-NEXT: 1 4 3.00 vor.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vxor.vv v4, v8, v12 +# CHECK-NEXT: 1 4 5.00 vxor.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vxor.vx v4, v8, a0 +# CHECK-NEXT: 1 4 9.00 vxor.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vxor.vi v4, v8, 0 +# CHECK-NEXT: 1 4 17.00 vxor.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vand.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vand.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vand.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vand.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vand.vi v4, v8, 0 +# CHECK-NEXT: 1 4 9.00 vand.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vor.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vor.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vsll.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vsll.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vsll.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vsll.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vsll.vi v4, v8, 0 +# CHECK-NEXT: 1 4 2.00 vsll.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vsrl.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vsrl.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vsrl.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vsrl.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vsrl.vi v4, v8, 0 +# CHECK-NEXT: 1 4 9.00 vsrl.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vsra.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vsra.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vsra.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vsra.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vsra.vi v4, v8, 0 +# CHECK-NEXT: 1 4 2.00 vsra.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vsll.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vsll.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vsll.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vsll.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vsll.vi v4, v8, 0 +# CHECK-NEXT: 1 4 9.00 vsll.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vsrl.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vsrl.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vsrl.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vsrl.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vsrl.vi v4, v8, 0 +# CHECK-NEXT: 1 4 3.00 vsrl.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vsra.vv v4, v8, v12 +# CHECK-NEXT: 1 4 5.00 vsra.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vsra.vx v4, v8, a0 +# CHECK-NEXT: 1 4 9.00 vsra.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vsra.vi v4, v8, 0 +# CHECK-NEXT: 1 4 17.00 vsra.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vsll.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vsll.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vsll.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vsll.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vsll.vi v4, v8, 0 +# CHECK-NEXT: 1 4 9.00 vsll.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vsrl.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vsrl.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 8 1.00 vnsrl.wv v4, v8, v12 +# CHECK-NEXT: 1 8 2.00 vnsrl.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 8 1.00 vnsrl.wx v4, v8, a0 +# CHECK-NEXT: 1 8 2.00 vnsrl.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 8 2.00 vnsrl.wi v4, v8, 0 +# CHECK-NEXT: 1 8 3.00 vnsrl.wi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 8 4.00 vnsra.wv v4, v8, v12 +# CHECK-NEXT: 1 8 5.00 vnsra.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 8 8.00 vnsra.wx v4, v8, a0 +# CHECK-NEXT: 1 8 9.00 vnsra.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 8 16.00 vnsra.wi v4, v8, 0 +# CHECK-NEXT: 1 8 17.00 vnsra.wi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 8 16.00 vnsrl.wv v4, v8, v12 +# CHECK-NEXT: 1 8 17.00 vnsrl.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 8 1.00 vnsrl.wx v4, v8, a0 +# CHECK-NEXT: 1 8 2.00 vnsrl.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 8 2.00 vnsrl.wi v4, v8, 0 +# CHECK-NEXT: 1 8 3.00 vnsrl.wi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 8 4.00 vnsra.wv v4, v8, v12 +# CHECK-NEXT: 1 8 5.00 vnsra.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 8 8.00 vnsra.wx v4, v8, a0 +# CHECK-NEXT: 1 8 9.00 vnsra.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 8 16.00 vnsra.wi v4, v8, 0 +# CHECK-NEXT: 1 8 17.00 vnsra.wi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 8 16.00 vnsrl.wv v4, v8, v12 +# CHECK-NEXT: 1 8 17.00 vnsrl.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 8 2.00 vnsrl.wx v4, v8, a0 +# CHECK-NEXT: 1 8 3.00 vnsrl.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 8 4.00 vnsrl.wi v4, v8, 0 +# CHECK-NEXT: 1 8 5.00 vnsrl.wi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 8 8.00 vnsra.wv v4, v8, v12 +# CHECK-NEXT: 1 8 9.00 vnsra.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 16.00 vnsra.wx v4, v8, a0 +# CHECK-NEXT: 1 8 17.00 vnsra.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 8 16.00 vnsra.wi v4, v8, 0 +# CHECK-NEXT: 1 8 17.00 vnsra.wi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 8 4.00 vnsrl.wv v4, v8, v12 +# CHECK-NEXT: 1 8 5.00 vnsrl.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 8 8.00 vnsrl.wx v4, v8, a0 +# CHECK-NEXT: 1 8 9.00 vnsrl.wx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 8 16.00 vnsrl.wi v4, v8, 0 +# CHECK-NEXT: 1 8 17.00 vnsrl.wi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 8 16.00 vnsra.wv v4, v8, v12 +# CHECK-NEXT: 1 8 17.00 vnsra.wv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vmseq.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vmseq.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmseq.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vmseq.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmseq.vi v4, v8, 0 +# CHECK-NEXT: 1 4 2.00 vmseq.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 vmsne.vv v4, v8, v12 +# CHECK-NEXT: 1 5 3.00 vmsne.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 7 4.00 vmsne.vx v4, v8, a0 +# CHECK-NEXT: 1 7 5.00 vmsne.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 11 8.00 vmsne.vi v4, v8, 0 +# CHECK-NEXT: 1 11 9.00 vmsne.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 19 16.00 vmsltu.vv v4, v8, v12 +# CHECK-NEXT: 1 19 17.00 vmsltu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmsltu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vmsltu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmslt.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vmslt.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 vmslt.vx v4, v8, a0 +# CHECK-NEXT: 1 5 3.00 vmslt.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 7 4.00 vmsleu.vv v4, v8, v12 +# CHECK-NEXT: 1 7 5.00 vmsleu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 11 8.00 vmsleu.vx v4, v8, a0 +# CHECK-NEXT: 1 11 9.00 vmsleu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 19 16.00 vmsleu.vi v4, v8, 0 +# CHECK-NEXT: 1 19 17.00 vmsleu.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmsle.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vmsle.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 vmsle.vx v4, v8, a0 +# CHECK-NEXT: 1 5 3.00 vmsle.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 7 4.00 vmsle.vi v4, v8, 0 +# CHECK-NEXT: 1 7 5.00 vmsle.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 11 8.00 vmsgtu.vx v4, v8, a0 +# CHECK-NEXT: 1 11 9.00 vmsgtu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 19 16.00 vmsgtu.vi v4, v8, 0 +# CHECK-NEXT: 1 19 17.00 vmsgtu.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 5 2.00 vmsgt.vx v4, v8, a0 +# CHECK-NEXT: 1 5 3.00 vmsgt.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 7 4.00 vmsgt.vi v4, v8, 0 +# CHECK-NEXT: 1 7 5.00 vmsgt.vi v4, v8, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 11 8.00 vmseq.vv v4, v8, v12 +# CHECK-NEXT: 1 11 9.00 vmseq.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 19 16.00 vmseq.vx v4, v8, a0 +# CHECK-NEXT: 1 19 17.00 vmseq.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vminu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vminu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vminu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vminu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmin.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vmin.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmin.vx v4, v8, a0 +# CHECK-NEXT: 1 4 3.00 vmin.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmaxu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 5.00 vmaxu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmaxu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 9.00 vmaxu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmax.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vmax.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmax.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vmax.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vminu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vminu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vminu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 3.00 vminu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmin.vv v4, v8, v12 +# CHECK-NEXT: 1 4 5.00 vmin.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmin.vx v4, v8, a0 +# CHECK-NEXT: 1 4 9.00 vmin.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmaxu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vmaxu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmaxu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vmaxu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmax.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vmax.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmax.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vmax.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vminu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 9.00 vminu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vminu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 17.00 vminu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmin.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vmin.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmin.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vmin.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmaxu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 9.00 vmaxu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmaxu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 17.00 vmaxu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vmul.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vmul.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmul.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vmul.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmulh.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vmulh.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmulh.vx v4, v8, a0 +# CHECK-NEXT: 1 4 3.00 vmulh.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmulhu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 5.00 vmulhu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmulhu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 9.00 vmulhu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmulhsu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vmulhsu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmulhsu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vmulhsu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmul.vv v4, v8, v12 +# CHECK-NEXT: 1 4 2.00 vmul.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmul.vx v4, v8, a0 +# CHECK-NEXT: 1 4 3.00 vmul.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmulh.vv v4, v8, v12 +# CHECK-NEXT: 1 4 5.00 vmulh.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmulh.vx v4, v8, a0 +# CHECK-NEXT: 1 4 9.00 vmulh.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmulhu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 17.00 vmulhu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmulhu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 2.00 vmulhu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmulhsu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vmulhsu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmulhsu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vmulhsu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmul.vv v4, v8, v12 +# CHECK-NEXT: 1 4 9.00 vmul.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmul.vx v4, v8, a0 +# CHECK-NEXT: 1 4 17.00 vmul.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmulh.vv v4, v8, v12 +# CHECK-NEXT: 1 4 3.00 vmulh.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmulh.vx v4, v8, a0 +# CHECK-NEXT: 1 4 5.00 vmulh.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmulhu.vv v4, v8, v12 +# CHECK-NEXT: 1 4 9.00 vmulhu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmulhu.vx v4, v8, a0 +# CHECK-NEXT: 1 4 17.00 vmulhu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 30 30.00 vdivu.vv v4, v8, v12 +# CHECK-NEXT: 1 30 31.00 vdivu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 60 60.00 vdivu.vx v4, v8, a0 +# CHECK-NEXT: 1 60 61.00 vdivu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 120 120.00 vdiv.vv v4, v8, v12 +# CHECK-NEXT: 1 120 121.00 vdiv.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 240 240.00 vdiv.vx v4, v8, a0 +# CHECK-NEXT: 1 240 241.00 vdiv.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 480 480.00 vremu.vv v4, v8, v12 +# CHECK-NEXT: 1 480 481.00 vremu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 960 960.00 vremu.vx v4, v8, a0 +# CHECK-NEXT: 1 960 961.00 vremu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1920 1920.00 vrem.vv v4, v8, v12 +# CHECK-NEXT: 1 1920 1921.00 vrem.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 30 30.00 vrem.vx v4, v8, a0 +# CHECK-NEXT: 1 30 31.00 vrem.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 60 60.00 vdivu.vv v4, v8, v12 +# CHECK-NEXT: 1 60 61.00 vdivu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 120 120.00 vdivu.vx v4, v8, a0 +# CHECK-NEXT: 1 120 121.00 vdivu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 240 240.00 vdiv.vv v4, v8, v12 +# CHECK-NEXT: 1 240 241.00 vdiv.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 480 480.00 vdiv.vx v4, v8, a0 +# CHECK-NEXT: 1 480 481.00 vdiv.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 960 960.00 vremu.vv v4, v8, v12 +# CHECK-NEXT: 1 960 961.00 vremu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 56 56.00 vremu.vx v4, v8, a0 +# CHECK-NEXT: 1 56 57.00 vremu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 112 112.00 vrem.vv v4, v8, v12 +# CHECK-NEXT: 1 112 113.00 vrem.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 224 224.00 vrem.vx v4, v8, a0 +# CHECK-NEXT: 1 224 225.00 vrem.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 448 448.00 vdivu.vv v4, v8, v12 +# CHECK-NEXT: 1 448 449.00 vdivu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 896 896.00 vdivu.vx v4, v8, a0 +# CHECK-NEXT: 1 896 897.00 vdivu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 114 114.00 vdiv.vv v4, v8, v12 +# CHECK-NEXT: 1 114 115.00 vdiv.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 228 228.00 vdiv.vx v4, v8, a0 +# CHECK-NEXT: 1 228 229.00 vdiv.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 456 456.00 vremu.vv v4, v8, v12 +# CHECK-NEXT: 1 456 457.00 vremu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 912 912.00 vremu.vx v4, v8, a0 +# CHECK-NEXT: 1 912 913.00 vremu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmul.vv v4, v8, v12 +# CHECK-NEXT: 1 8 2.00 vwmul.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmul.vx v4, v8, a0 +# CHECK-NEXT: 1 8 2.00 vwmul.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmulu.vv v4, v8, v12 +# CHECK-NEXT: 1 8 2.00 vwmulu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 8 2.00 vwmulu.vx v4, v8, a0 +# CHECK-NEXT: 1 8 3.00 vwmulu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 8 4.00 vwmulsu.vv v4, v8, v12 +# CHECK-NEXT: 1 8 5.00 vwmulsu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmulsu.vx v4, v8, a0 +# CHECK-NEXT: 1 8 9.00 vwmulsu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmul.vv v4, v8, v12 +# CHECK-NEXT: 1 8 9.00 vwmul.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmul.vx v4, v8, a0 +# CHECK-NEXT: 1 8 2.00 vwmul.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmulu.vv v4, v8, v12 +# CHECK-NEXT: 1 8 2.00 vwmulu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 8 2.00 vwmulu.vx v4, v8, a0 +# CHECK-NEXT: 1 8 3.00 vwmulu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 8 4.00 vwmulsu.vv v4, v8, v12 +# CHECK-NEXT: 1 8 5.00 vwmulsu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmulsu.vx v4, v8, a0 +# CHECK-NEXT: 1 8 9.00 vwmulsu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmul.vv v4, v8, v12 +# CHECK-NEXT: 1 8 9.00 vwmul.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmul.vx v4, v8, a0 +# CHECK-NEXT: 1 8 2.00 vwmul.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 8 2.00 vwmulu.vv v4, v8, v12 +# CHECK-NEXT: 1 8 3.00 vwmulu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 8 4.00 vwmulu.vx v4, v8, a0 +# CHECK-NEXT: 1 8 5.00 vwmulu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmulsu.vv v4, v8, v12 +# CHECK-NEXT: 1 8 9.00 vwmulsu.vv v4, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmulsu.vx v4, v8, a0 +# CHECK-NEXT: 1 8 9.00 vwmulsu.vx v4, v8, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vmacc.vv v4, v12, v8 +# CHECK-NEXT: 1 4 2.00 vmacc.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmacc.vx v4, a0, v8 +# CHECK-NEXT: 1 4 2.00 vmacc.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vnmsac.vv v4, v12, v8 +# CHECK-NEXT: 1 4 2.00 vnmsac.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vnmsac.vx v4, a0, v8 +# CHECK-NEXT: 1 4 3.00 vnmsac.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmadd.vv v4, v12, v8 +# CHECK-NEXT: 1 4 5.00 vmadd.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmadd.vx v4, a0, v8 +# CHECK-NEXT: 1 4 9.00 vmadd.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vnmsub.vv v4, v12, v8 +# CHECK-NEXT: 1 4 17.00 vnmsub.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vnmsub.vx v4, a0, v8 +# CHECK-NEXT: 1 4 2.00 vnmsub.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmacc.vv v4, v12, v8 +# CHECK-NEXT: 1 4 2.00 vmacc.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmacc.vx v4, a0, v8 +# CHECK-NEXT: 1 4 3.00 vmacc.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vnmsac.vv v4, v12, v8 +# CHECK-NEXT: 1 4 5.00 vnmsac.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vnmsac.vx v4, a0, v8 +# CHECK-NEXT: 1 4 9.00 vnmsac.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmadd.vv v4, v12, v8 +# CHECK-NEXT: 1 4 17.00 vmadd.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmadd.vx v4, a0, v8 +# CHECK-NEXT: 1 4 2.00 vmadd.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vnmsub.vv v4, v12, v8 +# CHECK-NEXT: 1 4 3.00 vnmsub.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vnmsub.vx v4, a0, v8 +# CHECK-NEXT: 1 4 5.00 vnmsub.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmacc.vv v4, v12, v8 +# CHECK-NEXT: 1 4 9.00 vmacc.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmacc.vx v4, a0, v8 +# CHECK-NEXT: 1 4 17.00 vmacc.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vnmsac.vv v4, v12, v8 +# CHECK-NEXT: 1 4 3.00 vnmsac.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vnmsac.vx v4, a0, v8 +# CHECK-NEXT: 1 4 5.00 vnmsac.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmadd.vv v4, v12, v8 +# CHECK-NEXT: 1 4 9.00 vmadd.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmadd.vx v4, a0, v8 +# CHECK-NEXT: 1 4 17.00 vmadd.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmaccu.vv v4, v12, v8 +# CHECK-NEXT: 1 8 2.00 vwmaccu.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmaccu.vx v4, a0, v8 +# CHECK-NEXT: 1 8 2.00 vwmaccu.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmacc.vv v4, v12, v8 +# CHECK-NEXT: 1 8 2.00 vwmacc.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 8 2.00 vwmacc.vx v4, a0, v8 +# CHECK-NEXT: 1 8 3.00 vwmacc.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 8 4.00 vwmaccsu.vv v4, v12, v8 +# CHECK-NEXT: 1 8 5.00 vwmaccsu.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmaccsu.vx v4, a0, v8 +# CHECK-NEXT: 1 8 9.00 vwmaccsu.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmaccus.vx v4, a0, v8 +# CHECK-NEXT: 1 8 9.00 vwmaccus.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmaccu.vv v4, v12, v8 +# CHECK-NEXT: 1 8 2.00 vwmaccu.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmaccu.vx v4, a0, v8 +# CHECK-NEXT: 1 8 2.00 vwmaccu.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 8 2.00 vwmacc.vv v4, v12, v8 +# CHECK-NEXT: 1 8 3.00 vwmacc.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 8 4.00 vwmacc.vx v4, a0, v8 +# CHECK-NEXT: 1 8 5.00 vwmacc.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmaccsu.vv v4, v12, v8 +# CHECK-NEXT: 1 8 9.00 vwmaccsu.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmaccsu.vx v4, a0, v8 +# CHECK-NEXT: 1 8 9.00 vwmaccsu.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 8 1.00 vwmaccus.vx v4, a0, v8 +# CHECK-NEXT: 1 8 2.00 vwmaccus.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 8 2.00 vwmaccu.vv v4, v12, v8 +# CHECK-NEXT: 1 8 3.00 vwmaccu.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 8 4.00 vwmaccu.vx v4, a0, v8 +# CHECK-NEXT: 1 8 5.00 vwmaccu.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmacc.vv v4, v12, v8 +# CHECK-NEXT: 1 8 9.00 vwmacc.vv v4, v12, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 8 8.00 vwmacc.vx v4, a0, v8 +# CHECK-NEXT: 1 8 9.00 vwmacc.vx v4, a0, v8 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 2.00 vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 2.00 vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 2.00 vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 3.00 vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 5.00 vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 9.00 vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 17.00 vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 2.00 vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 2.00 vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 3.00 vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 5.00 vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 9.00 vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 17.00 vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 2.00 vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 3.00 vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 5.00 vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 9.00 vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 17.00 vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 3.00 vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: 1 4 5.00 vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: 1 4 9.00 vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: 1 4 17.00 vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vmv.v.v v4, v12 +# CHECK-NEXT: 1 4 2.00 vmv.v.v v4, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmv.v.x v4, a0 +# CHECK-NEXT: 1 4 2.00 vmv.v.x v4, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmv.v.i v4, 0 +# CHECK-NEXT: 1 4 2.00 vmv.v.i v4, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmv.v.v v4, v12 +# CHECK-NEXT: 1 4 3.00 vmv.v.v v4, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmv.v.x v4, a0 +# CHECK-NEXT: 1 4 5.00 vmv.v.x v4, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmv.v.i v4, 0 +# CHECK-NEXT: 1 4 9.00 vmv.v.i v4, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmv.v.v v4, v12 +# CHECK-NEXT: 1 4 17.00 vmv.v.v v4, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 vmv.v.x v4, a0 +# CHECK-NEXT: 1 4 2.00 vmv.v.x v4, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmv.v.i v4, 0 +# CHECK-NEXT: 1 4 2.00 vmv.v.i v4, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmv.v.v v4, v12 +# CHECK-NEXT: 1 4 3.00 vmv.v.v v4, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmv.v.x v4, a0 +# CHECK-NEXT: 1 4 5.00 vmv.v.x v4, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmv.v.i v4, 0 +# CHECK-NEXT: 1 4 9.00 vmv.v.i v4, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmv.v.v v4, v12 +# CHECK-NEXT: 1 4 17.00 vmv.v.v v4, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 vmv.v.x v4, a0 +# CHECK-NEXT: 1 4 2.00 vmv.v.x v4, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmv.v.i v4, 0 +# CHECK-NEXT: 1 4 3.00 vmv.v.i v4, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmv.v.v v4, v12 +# CHECK-NEXT: 1 4 5.00 vmv.v.v v4, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmv.v.x v4, a0 +# CHECK-NEXT: 1 4 9.00 vmv.v.x v4, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmv.v.i v4, 0 +# CHECK-NEXT: 1 4 17.00 vmv.v.i v4, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vmv.v.v v4, v12 +# CHECK-NEXT: 1 4 3.00 vmv.v.v v4, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 vmv.v.x v4, a0 +# CHECK-NEXT: 1 4 5.00 vmv.v.x v4, a0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vmv.v.i v4, 0 +# CHECK-NEXT: 1 4 9.00 vmv.v.i v4, 0 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vmv.v.v v4, v12 +# CHECK-NEXT: 1 4 17.00 vmv.v.v v4, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 333.00 - 11175.00 11175.00 - - +# CHECK-NEXT: - - 333.00 - 11549.00 374.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vadd.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vadd.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vi v4, v8, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vadd.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsub.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vsub.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsub.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vrsub.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vrsub.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vrsub.vi v4, v8, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vrsub.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vadd.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vadd.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vi v4, v8, 0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vsub.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsub.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vsub.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsub.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vrsub.vx v4, v8, a0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vrsub.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vrsub.vi v4, v8, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vrsub.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vadd.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vadd.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vadd.vi v4, v8, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vadd.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vsub.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsub.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsub.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vrsub.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vrsub.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vrsub.vi v4, v8, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vrsub.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwaddu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwaddu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwaddu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwaddu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwsubu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwsubu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vwsubu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vwsubu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vwadd.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vwadd.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwadd.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwadd.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwsub.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwsub.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwsub.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwsub.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwaddu.wv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwaddu.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vwaddu.wx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vwaddu.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vwsubu.wv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vwsubu.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwsubu.wx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwsubu.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwadd.wv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwadd.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwadd.wx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwadd.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vwsub.wv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vwsub.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vwsub.wx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vwsub.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwaddu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwaddu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwaddu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwaddu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 1.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsext.vf2 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 1.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsext.vf2 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsext.vf2 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsext.vf2 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsext.vf2 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsext.vf2 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 1.00 1.00 - - vsext.vf2 v4, v8 -# CHECK-NEXT: - - - - 1.00 1.00 - - vzext.vf4 v4, v8 -# CHECK-NEXT: - - - - 1.00 1.00 - - vsext.vf4 v4, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vzext.vf4 v4, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsext.vf4 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf2 v4, v8 -# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf4 v4, v8 -# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf4 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vzext.vf4 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsext.vf4 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf2 v4, v8 -# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf4 v4, v8 -# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf4 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vzext.vf4 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsext.vf4 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf2 v4, v8 -# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf4 v4, v8 -# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf4 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vzext.vf4 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsext.vf4 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8 -# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf4 v4, v8 -# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf4 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vzext.vf4 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsext.vf4 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf2 v4, v8 -# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf4 v4, v8 -# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf4 v4, v8 -# CHECK-NEXT: - - - - 2.00 2.00 - - vzext.vf8 v4, v8 -# CHECK-NEXT: - - - - 2.00 2.00 - - vsext.vf8 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vzext.vf4 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsext.vf4 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vzext.vf8 v4, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsext.vf8 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf2 v4, v8 -# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf4 v4, v8 -# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf4 v4, v8 -# CHECK-NEXT: - - - - 4.00 4.00 - - vzext.vf8 v4, v8 -# CHECK-NEXT: - - - - 4.00 4.00 - - vsext.vf8 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vzext.vf4 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsext.vf4 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vzext.vf8 v4, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsext.vf8 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf2 v4, v8 -# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf4 v4, v8 -# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf4 v4, v8 -# CHECK-NEXT: - - - - 8.00 8.00 - - vzext.vf8 v4, v8 -# CHECK-NEXT: - - - - 8.00 8.00 - - vsext.vf8 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vzext.vf4 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsext.vf4 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vzext.vf8 v4, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsext.vf8 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf2 v4, v8 -# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf2 v4, v8 -# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf4 v4, v8 -# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf4 v4, v8 -# CHECK-NEXT: - - - - 16.00 16.00 - - vzext.vf8 v4, v8 -# CHECK-NEXT: - - - - 16.00 16.00 - - vsext.vf8 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vzext.vf2 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsext.vf2 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vzext.vf4 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsext.vf4 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vzext.vf8 v4, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsext.vf8 v4, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vadc.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vadc.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vadc.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vadc.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vadc.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vadc.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmadc.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmadc.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmadc.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmadc.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmadc.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmadc.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmadc.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmadc.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmadc.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmadc.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmadc.vi v4, v8, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmadc.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vsbc.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsbc.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vsbc.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsbc.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmsbc.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmsbc.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmsbc.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmsbc.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmsbc.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmsbc.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmsbc.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmsbc.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vadc.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vadc.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vadc.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vadc.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vadc.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadc.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmadc.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmadc.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmadc.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmadc.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmadc.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmadc.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmadc.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmadc.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vand.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vand.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vand.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vand.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vand.vi v4, v8, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vand.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vor.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vor.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vor.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vor.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vor.vi v4, v8, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vor.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vxor.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vxor.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vxor.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vxor.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vxor.vi v4, v8, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vxor.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vand.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vand.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vand.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vand.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vand.vi v4, v8, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vand.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vor.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vor.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vor.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vor.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vor.vi v4, v8, 0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vor.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vxor.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vxor.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vxor.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vxor.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vxor.vi v4, v8, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vxor.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vand.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vand.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vand.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vand.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vand.vi v4, v8, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vand.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vor.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vor.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vsll.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsll.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vsll.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsll.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vsll.vi v4, v8, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsll.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vsrl.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsrl.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vsrl.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsrl.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vsrl.vi v4, v8, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsrl.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vsra.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsra.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vsra.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsra.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vsra.vi v4, v8, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsra.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vsll.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsll.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vsll.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsll.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vsll.vi v4, v8, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsll.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vsrl.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsrl.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vsrl.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vsrl.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vsrl.vi v4, v8, 0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsrl.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vsra.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsra.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vsra.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsra.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vsra.vi v4, v8, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsra.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vsll.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsll.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vsll.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vsll.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vsll.vi v4, v8, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsll.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vsrl.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vsrl.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vnsrl.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vnsrl.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vnsrl.wi v4, v8, 0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vnsrl.wi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vnsra.wv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vnsra.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vnsra.wx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vnsra.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wi v4, v8, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vnsra.wi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vnsrl.wv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vnsrl.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vnsrl.wx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vnsrl.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vnsrl.wi v4, v8, 0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vnsrl.wi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vnsra.wv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vnsra.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vnsra.wx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vnsra.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wi v4, v8, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vnsra.wi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vnsrl.wv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vnsrl.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vnsrl.wx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vnsrl.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vnsrl.wi v4, v8, 0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vnsrl.wi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vnsra.wv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vnsra.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wx v4, v8, a0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vnsra.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wi v4, v8, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vnsra.wi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vnsrl.wv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vnsrl.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vnsrl.wx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vnsrl.wx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vnsrl.wi v4, v8, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vnsrl.wi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vnsra.wv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vnsra.wv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmseq.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmseq.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmseq.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmseq.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmseq.vi v4, v8, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmseq.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmsne.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmsne.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmsne.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmsne.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmsne.vi v4, v8, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmsne.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmsltu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmsltu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmsltu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmsltu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmslt.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmslt.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmslt.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmslt.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmsleu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmsleu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmsleu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmsleu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmsleu.vi v4, v8, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmsleu.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmsle.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmsle.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmsle.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmsle.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmsle.vi v4, v8, 0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmsle.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmsgtu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmsgtu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmsgtu.vi v4, v8, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmsgtu.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmsgt.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmsgt.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmsgt.vi v4, v8, 0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmsgt.vi v4, v8, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmseq.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmseq.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmseq.vx v4, v8, a0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmseq.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vminu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vminu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vminu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vminu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmin.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmin.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmin.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmin.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmaxu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmaxu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmaxu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmaxu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmax.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmax.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmax.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmax.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vminu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vminu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vminu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vminu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmin.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmin.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmin.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmin.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmaxu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmaxu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmaxu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmaxu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmax.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmax.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmax.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmax.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vminu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vminu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vminu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vminu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmin.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmin.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmin.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmin.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmaxu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmaxu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmaxu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmaxu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmul.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmul.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmul.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmul.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmulh.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmulh.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmulh.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmulh.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmulhu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmulhu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmulhu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmulhu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmulhsu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmulhsu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmulhsu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmulhsu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmul.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmul.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmul.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmul.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmulh.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmulh.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmulh.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmulh.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmulhu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmulhu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmulhu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmulhu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmulhsu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmulhsu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmulhsu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmulhsu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmul.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmul.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmul.vx v4, v8, a0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmul.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmulh.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmulh.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmulh.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmulh.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmulhu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmulhu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmulhu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmulhu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 30.00 30.00 - - vdivu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 31.00 1.00 - - vdivu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 60.00 60.00 - - vdivu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 61.00 1.00 - - vdivu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 120.00 120.00 - - vdiv.vv v4, v8, v12 +# CHECK-NEXT: - - - - 121.00 1.00 - - vdiv.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vx v4, v8, a0 +# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 480.00 480.00 - - vremu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 481.00 1.00 - - vremu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 960.00 960.00 - - vremu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 961.00 1.00 - - vremu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 1920.00 1920.00 - - vrem.vv v4, v8, v12 +# CHECK-NEXT: - - - - 1921.00 1.00 - - vrem.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 30.00 30.00 - - vrem.vx v4, v8, a0 +# CHECK-NEXT: - - - - 31.00 1.00 - - vrem.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 60.00 60.00 - - vdivu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 61.00 1.00 - - vdivu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 120.00 120.00 - - vdivu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 121.00 1.00 - - vdivu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v4, v8, v12 +# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 480.00 480.00 - - vdiv.vx v4, v8, a0 +# CHECK-NEXT: - - - - 481.00 1.00 - - vdiv.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 960.00 960.00 - - vremu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 961.00 1.00 - - vremu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 56.00 56.00 - - vremu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 57.00 1.00 - - vremu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 112.00 112.00 - - vrem.vv v4, v8, v12 +# CHECK-NEXT: - - - - 113.00 1.00 - - vrem.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 224.00 224.00 - - vrem.vx v4, v8, a0 +# CHECK-NEXT: - - - - 225.00 1.00 - - vrem.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 448.00 448.00 - - vdivu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 449.00 1.00 - - vdivu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 896.00 896.00 - - vdivu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 897.00 1.00 - - vdivu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v4, v8, v12 +# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 228.00 228.00 - - vdiv.vx v4, v8, a0 +# CHECK-NEXT: - - - - 229.00 1.00 - - vdiv.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 456.00 456.00 - - vremu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 457.00 1.00 - - vremu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 912.00 912.00 - - vremu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 913.00 1.00 - - vremu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmul.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmul.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmul.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmul.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmulu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmulu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vwmulu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vwmulu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vwmulsu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vwmulsu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmulsu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmulsu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmul.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmul.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmul.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmul.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmulu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmulu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vwmulu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vwmulu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vwmulsu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vwmulsu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmulsu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmulsu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmul.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmul.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmul.vx v4, v8, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmul.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vwmulu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vwmulu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vwmulu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vwmulu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmulsu.vv v4, v8, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmulsu.vv v4, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmulsu.vx v4, v8, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmulsu.vx v4, v8, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmacc.vv v4, v12, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmacc.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmacc.vx v4, a0, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmacc.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vnmsac.vv v4, v12, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vnmsac.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vnmsac.vx v4, a0, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vnmsac.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmadd.vv v4, v12, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmadd.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmadd.vx v4, a0, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmadd.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vnmsub.vv v4, v12, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vnmsub.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vnmsub.vx v4, a0, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vnmsub.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmacc.vv v4, v12, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmacc.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmacc.vx v4, a0, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmacc.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vnmsac.vv v4, v12, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vnmsac.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vnmsac.vx v4, a0, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vnmsac.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmadd.vv v4, v12, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmadd.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmadd.vx v4, a0, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmadd.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vnmsub.vv v4, v12, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vnmsub.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vnmsub.vx v4, a0, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vnmsub.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmacc.vv v4, v12, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmacc.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmacc.vx v4, a0, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmacc.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vnmsac.vv v4, v12, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vnmsac.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vnmsac.vx v4, a0, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vnmsac.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmadd.vv v4, v12, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmadd.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmadd.vx v4, a0, v8 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmadd.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccu.vv v4, v12, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmaccu.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccu.vx v4, a0, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmaccu.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmacc.vv v4, v12, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmacc.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vwmacc.vx v4, a0, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vwmacc.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vwmaccsu.vv v4, v12, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vwmaccsu.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmaccsu.vx v4, a0, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmaccsu.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmaccus.vx v4, a0, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmaccus.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccu.vv v4, v12, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmaccu.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccu.vx v4, a0, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmaccu.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vwmacc.vv v4, v12, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vwmacc.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vwmacc.vx v4, a0, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vwmacc.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmaccsu.vv v4, v12, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmaccsu.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmaccsu.vx v4, a0, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmaccsu.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vwmaccus.vx v4, a0, v8 +# CHECK-NEXT: - - - - 2.00 1.00 - - vwmaccus.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vwmaccu.vv v4, v12, v8 +# CHECK-NEXT: - - - - 3.00 1.00 - - vwmaccu.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vwmaccu.vx v4, a0, v8 +# CHECK-NEXT: - - - - 5.00 1.00 - - vwmaccu.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmacc.vv v4, v12, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmacc.vv v4, v12, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vwmacc.vx v4, a0, v8 +# CHECK-NEXT: - - - - 9.00 1.00 - - vwmacc.vx v4, a0, v8 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmerge.vxm v4, v8, a0, v0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmerge.vxm v4, v8, a0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmerge.vim v4, v8, 0, v0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmerge.vim v4, v8, 0, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmerge.vvm v4, v8, v12, v0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmerge.vvm v4, v8, v12, v0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.v v4, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmv.v.v v4, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.x v4, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmv.v.x v4, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.i v4, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmv.v.i v4, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmv.v.v v4, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmv.v.v v4, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmv.v.x v4, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmv.v.x v4, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmv.v.i v4, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmv.v.i v4, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmv.v.v v4, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmv.v.v v4, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.x v4, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmv.v.x v4, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.i v4, 0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmv.v.i v4, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmv.v.v v4, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmv.v.v v4, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmv.v.x v4, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmv.v.x v4, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmv.v.i v4, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmv.v.i v4, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmv.v.v v4, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmv.v.v v4, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vmv.v.x v4, a0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vmv.v.x v4, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmv.v.i v4, 0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmv.v.i v4, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmv.v.v v4, v12 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmv.v.v v4, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmv.v.x v4, a0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmv.v.x v4, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmv.v.i v4, 0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmv.v.i v4, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vmv.v.v v4, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vmv.v.v v4, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 4.00 - - vmv.v.x v4, a0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vmv.v.x v4, a0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vmv.v.i v4, 0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vmv.v.i v4, 0 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vmv.v.v v4, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vmv.v.v v4, v12 diff --git a/llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s b/llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s index 947b5dbbef1f..29148092882d 100644 --- a/llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s +++ b/llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s @@ -16,7 +16,7 @@ vadd.vv v12, v12, v12 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.33 # CHECK-NEXT: IPC: 0.33 -# CHECK-NEXT: Block RThroughput: 18.0 +# CHECK-NEXT: Block RThroughput: 20.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -28,30 +28,30 @@ vadd.vv v12, v12, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 2.00 - 18.00 18.00 - - +# CHECK-NEXT: - - 2.00 - 20.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: 01 diff --git a/llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s b/llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s index 810b38308462..44d6c442f52d 100644 --- a/llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s +++ b/llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s @@ -11,13 +11,13 @@ vdiv.vv v8, v8, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 4 -# CHECK-NEXT: Total Cycles: 358 +# CHECK-NEXT: Total Cycles: 359 # CHECK-NEXT: Total uOps: 4 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.01 # CHECK-NEXT: IPC: 0.01 -# CHECK-NEXT: Block RThroughput: 354.0 +# CHECK-NEXT: Block RThroughput: 356.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -29,30 +29,30 @@ vdiv.vv v8, v8, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 2.00 - 354.00 354.00 - - +# CHECK-NEXT: - - 2.00 - 356.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 0123 diff --git a/llvm/test/tools/llvm-mca/RISCV/disable-im.s b/llvm/test/tools/llvm-mca/RISCV/disable-im.s index fc969bf7c99a..9885d4accc44 100644 --- a/llvm/test/tools/llvm-mca/RISCV/disable-im.s +++ b/llvm/test/tools/llvm-mca/RISCV/disable-im.s @@ -13,13 +13,13 @@ vadd.vv v12, v12, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 6 -# CHECK-NEXT: Total Cycles: 40 +# CHECK-NEXT: Total Cycles: 42 # CHECK-NEXT: Total uOps: 6 # CHECK: Dispatch Width: 2 -# CHECK-NEXT: uOps Per Cycle: 0.15 -# CHECK-NEXT: IPC: 0.15 -# CHECK-NEXT: Block RThroughput: 48.0 +# CHECK-NEXT: uOps Per Cycle: 0.14 +# CHECK-NEXT: IPC: 0.14 +# CHECK-NEXT: Block RThroughput: 51.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -31,45 +31,45 @@ vadd.vv v12, v12, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu -# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 3.00 - 48.00 48.00 - - +# CHECK-NEXT: - - 3.00 - 51.00 3.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: 0123456789 0123456789 -# CHECK-NEXT: Index 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 01 -# CHECK: [0,0] DeeE . . . . . . . . vsetvli zero, a0, e8, m2, tu, mu -# CHECK-NEXT: [0,1] . DeeeE . . . . . . . vadd.vv v12, v12, v12 -# CHECK-NEXT: [0,2] . DeeE . . . . . . . vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: [0,3] . . . . DeeeE . . . . vadd.vv v12, v12, v12 -# CHECK-NEXT: [0,4] . . . . DeeE . . . . vsetvli zero, a0, e8, m8, tu, mu -# CHECK-NEXT: [0,5] . . . . . . . DeeeE vadd.vv v12, v12, v12 +# CHECK: [0,0] DeeE . . . . . . . .. vsetvli zero, a0, e8, m2, tu, mu +# CHECK-NEXT: [0,1] . DeeeE . . . . . . .. vadd.vv v12, v12, v12 +# CHECK-NEXT: [0,2] . DeeE . . . . . . .. vsetvli zero, a0, e8, m1, tu, mu +# CHECK-NEXT: [0,3] . . . . DeeeE. . . .. vadd.vv v12, v12, v12 +# CHECK-NEXT: [0,4] . . . . .DeeE. . . .. vsetvli zero, a0, e8, m8, tu, mu +# CHECK-NEXT: [0,5] . . . . . . . . DeeeE vadd.vv v12, v12, v12 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions diff --git a/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s b/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s index a72e87fab475..0b5a55717035 100644 --- a/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s +++ b/llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s @@ -11,13 +11,13 @@ vdiv.vv v12, v12, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 4 -# CHECK-NEXT: Total Cycles: 90 +# CHECK-NEXT: Total Cycles: 91 # CHECK-NEXT: Total uOps: 4 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.04 # CHECK-NEXT: IPC: 0.04 -# CHECK-NEXT: Block RThroughput: 86.0 +# CHECK-NEXT: Block RThroughput: 88.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -29,27 +29,27 @@ vdiv.vv v12, v12, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 56 56.00 vdiv.vv v12, v12, v12 +# CHECK-NEXT: 1 56 57.00 vdiv.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 30 30.00 vdiv.vv v12, v12, v12 +# CHECK-NEXT: 1 30 31.00 vdiv.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 2.00 - 86.00 86.00 - - +# CHECK-NEXT: - - 2.00 - 88.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 56.00 56.00 - - vdiv.vv v12, v12, v12 +# CHECK-NEXT: - - - - 57.00 1.00 - - vdiv.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 30.00 30.00 - - vdiv.vv v12, v12, v12 +# CHECK-NEXT: - - - - 31.00 1.00 - - vdiv.vv v12, v12, v12 diff --git a/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s index b4aa43396705..9a47f3fc4f8d 100644 --- a/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s +++ b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s @@ -13,7 +13,7 @@ vadd.vv v12, v12, v12 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: IPC: 0.25 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -25,26 +25,26 @@ vadd.vv v12, v12, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - +# CHECK-NEXT: - - 1.00 - 3.00 1.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 01234567 diff --git a/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s index cd477b60d7f5..b7525f5114be 100644 --- a/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s +++ b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s @@ -8,13 +8,13 @@ vadd.vv v12, v12, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 3 -# CHECK-NEXT: Total Cycles: 21 +# CHECK-NEXT: Total Cycles: 22 # CHECK-NEXT: Total uOps: 3 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.14 # CHECK-NEXT: IPC: 0.14 -# CHECK-NEXT: Block RThroughput: 17.0 +# CHECK-NEXT: Block RThroughput: 19.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -25,37 +25,37 @@ vadd.vv v12, v12, v12 # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 17.00 17.00 - - +# CHECK-NEXT: - - 1.00 - 19.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: -# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 2.00 1.00 - - vadd.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: 0123456789 -# CHECK-NEXT: Index 0123456789 0 +# CHECK-NEXT: Index 0123456789 01 -# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12 -# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, mf8, tu, mu -# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12 +# CHECK: [0,0] DeeeE. . . .. vadd.vv v12, v12, v12 +# CHECK-NEXT: [0,1] .DeeE. . . .. vsetvli zero, a0, e8, mf8, tu, mu +# CHECK-NEXT: [0,2] . . . . DeeeE vadd.vv v12, v12, v12 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions diff --git a/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s index 966531028a9c..918d03cb503a 100644 --- a/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s +++ b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s @@ -17,7 +17,7 @@ vadd.vv v12, v12, v12 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: IPC: 0.25 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -29,26 +29,26 @@ vadd.vv v12, v12, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - +# CHECK-NEXT: - - 1.00 - 3.00 1.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 01234567 diff --git a/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s index 160d01a5fae6..2b500ab9d014 100644 --- a/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s +++ b/llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s @@ -18,7 +18,7 @@ vadd.vv v12, v12, v12 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: IPC: 0.25 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -30,26 +30,26 @@ vadd.vv v12, v12, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - +# CHECK-NEXT: - - 1.00 - 3.00 1.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 01234567 diff --git a/llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s b/llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s index 424435356124..6cb19048665f 100644 --- a/llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s +++ b/llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s @@ -15,13 +15,13 @@ vsub.vv v12, v12, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 8 -# CHECK-NEXT: Total Cycles: 28 +# CHECK-NEXT: Total Cycles: 29 # CHECK-NEXT: Total uOps: 8 # CHECK: Dispatch Width: 2 -# CHECK-NEXT: uOps Per Cycle: 0.29 -# CHECK-NEXT: IPC: 0.29 -# CHECK-NEXT: Block RThroughput: 22.0 +# CHECK-NEXT: uOps Per Cycle: 0.28 +# CHECK-NEXT: IPC: 0.28 +# CHECK-NEXT: Block RThroughput: 27.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -33,51 +33,51 @@ vsub.vv v12, v12, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 -# CHECK-NEXT: 1 4 2.00 vsub.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vsub.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 vadd.vv v12, v12, v12 -# CHECK-NEXT: 1 4 8.00 vsub.vv v12, v12, v12 +# CHECK-NEXT: 1 4 9.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 9.00 vsub.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 3.00 - 22.00 22.00 - - +# CHECK-NEXT: - - 3.00 - 27.00 5.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 -# CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vsub.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 8.00 - - vadd.vv v12, v12, v12 -# CHECK-NEXT: - - - - 8.00 8.00 - - vsub.vv v12, v12, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 9.00 1.00 - - vsub.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: 0123456789 -# CHECK-NEXT: Index 0123456789 01234567 +# CHECK-NEXT: Index 0123456789 012345678 -# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12 -# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12 -# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12 -# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m4, tu, mu -# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12 -# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12 +# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu +# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12 +# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu +# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12 +# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12 +# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m4, tu, mu +# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12 +# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions diff --git a/llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s b/llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s index 08339adb5b16..ace5eac406bf 100644 --- a/llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s +++ b/llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s @@ -16,13 +16,13 @@ vdivu.vv v8, v8, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 8 -# CHECK-NEXT: Total Cycles: 570 +# CHECK-NEXT: Total Cycles: 574 # CHECK-NEXT: Total uOps: 8 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.01 # CHECK-NEXT: IPC: 0.01 -# CHECK-NEXT: Block RThroughput: 566.0 +# CHECK-NEXT: Block RThroughput: 571.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -34,38 +34,38 @@ vdivu.vv v8, v8, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12 -# CHECK-NEXT: 1 114 114.00 vdivu.vv v8, v8, v12 +# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 114 115.00 vdivu.vv v8, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m1, tu, mu -# CHECK-NEXT: 1 112 112.00 vdiv.vv v8, v8, v12 -# CHECK-NEXT: 1 112 112.00 vdivu.vv v8, v8, v12 +# CHECK-NEXT: 1 112 113.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 112 113.00 vdivu.vv v8, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 3.00 - 566.00 566.00 - - +# CHECK-NEXT: - - 3.00 - 571.00 5.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12 -# CHECK-NEXT: - - - - 114.00 114.00 - - vdivu.vv v8, v8, v12 +# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 115.00 1.00 - - vdivu.vv v8, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e32, m1, tu, mu -# CHECK-NEXT: - - - - 112.00 112.00 - - vdiv.vv v8, v8, v12 -# CHECK-NEXT: - - - - 112.00 112.00 - - vdivu.vv v8, v8, v12 +# CHECK-NEXT: - - - - 113.00 1.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 113.00 1.00 - - vdivu.vv v8, v8, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 0123 diff --git a/llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s b/llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s index 2864e6cc6bed..c20200bd536a 100644 --- a/llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s +++ b/llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s @@ -10,13 +10,13 @@ vdiv.vv v8, v8, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 3 -# CHECK-NEXT: Total Cycles: 484 +# CHECK-NEXT: Total Cycles: 485 # CHECK-NEXT: Total uOps: 3 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.01 # CHECK-NEXT: IPC: 0.01 -# CHECK-NEXT: Block RThroughput: 480.0 +# CHECK-NEXT: Block RThroughput: 482.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -28,28 +28,28 @@ vdiv.vv v8, v8, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12 -# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 480.00 480.00 - - +# CHECK-NEXT: - - 1.00 - 482.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12 -# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 0123 diff --git a/llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s b/llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s index c976d8ba4c9f..a8d25ed271f7 100644 --- a/llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s +++ b/llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s @@ -7,13 +7,13 @@ vadd.vv v12, v12, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 3 -# CHECK-NEXT: Total Cycles: 21 +# CHECK-NEXT: Total Cycles: 22 # CHECK-NEXT: Total uOps: 3 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.14 # CHECK-NEXT: IPC: 0.14 -# CHECK-NEXT: Block RThroughput: 18.0 +# CHECK-NEXT: Block RThroughput: 20.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -24,37 +24,37 @@ vadd.vv v12, v12, v12 # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 18.00 18.00 - - +# CHECK-NEXT: - - 1.00 - 20.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: -# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: 0123456789 -# CHECK-NEXT: Index 0123456789 0 +# CHECK-NEXT: Index 0123456789 01 -# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12 -# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12 +# CHECK: [0,0] DeeeE. . . .. vadd.vv v12, v12, v12 +# CHECK-NEXT: [0,1] .DeeE. . . .. vsetvli zero, a0, e8, m1, tu, mu +# CHECK-NEXT: [0,2] . . . . DeeeE vadd.vv v12, v12, v12 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions diff --git a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s index 19fe178ca26c..035589517670 100644 --- a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s +++ b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s @@ -14,7 +14,7 @@ vdiv.vv v8, v8, v12 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.01 # CHECK-NEXT: IPC: 0.01 -# CHECK-NEXT: Block RThroughput: 240.0 +# CHECK-NEXT: Block RThroughput: 241.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,26 +26,26 @@ vdiv.vv v8, v8, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 240.00 240.00 - - +# CHECK-NEXT: - - 1.00 - 241.00 1.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 0123 diff --git a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s index 79f0d2793718..fc3369bf4796 100644 --- a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s +++ b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s @@ -13,13 +13,13 @@ vdiv.vv v8, v8, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 3 -# CHECK-NEXT: Total Cycles: 2833 +# CHECK-NEXT: Total Cycles: 2834 # CHECK-NEXT: Total uOps: 3 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.00 # CHECK-NEXT: IPC: 0.00 -# CHECK-NEXT: Block RThroughput: 2832.0 +# CHECK-NEXT: Block RThroughput: 2834.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -30,29 +30,29 @@ vdiv.vv v8, v8, v12 # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1920 1920.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 1920 1921.00 vdiv.vv v8, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu -# CHECK-NEXT: 1 912 912.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 912 913.00 vdiv.vv v8, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 2832.00 2832.00 - - +# CHECK-NEXT: - - 1.00 - 2834.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: -# CHECK-NEXT: - - - - 1920.00 1920.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 1921.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu -# CHECK-NEXT: - - - - 912.00 912.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 913.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 0 diff --git a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s index 4f625782841f..5865d1488a11 100644 --- a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s +++ b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s @@ -18,7 +18,7 @@ vdiv.vv v8, v8, v12 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.02 # CHECK-NEXT: IPC: 0.02 -# CHECK-NEXT: Block RThroughput: 114.0 +# CHECK-NEXT: Block RThroughput: 115.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -30,26 +30,26 @@ vdiv.vv v8, v8, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 114.00 114.00 - - +# CHECK-NEXT: - - 1.00 - 115.00 1.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 0123 diff --git a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s index 12d4bb4783ce..323e10ba0b5f 100644 --- a/llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s +++ b/llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s @@ -19,7 +19,7 @@ vdiv.vv v8, v8, v12 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.02 # CHECK-NEXT: IPC: 0.02 -# CHECK-NEXT: Block RThroughput: 114.0 +# CHECK-NEXT: Block RThroughput: 115.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -31,26 +31,26 @@ vdiv.vv v8, v8, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 114.00 114.00 - - +# CHECK-NEXT: - - 1.00 - 115.00 1.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu -# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 0123 diff --git a/llvm/test/tools/llvm-mca/RISCV/vle-vse.s b/llvm/test/tools/llvm-mca/RISCV/vle-vse.s index 15b8f854c587..e9f4999a1035 100644 --- a/llvm/test/tools/llvm-mca/RISCV/vle-vse.s +++ b/llvm/test/tools/llvm-mca/RISCV/vle-vse.s @@ -413,13 +413,13 @@ vsm.v v1, (a0) # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 1084 +# CHECK-NEXT: Total Cycles: 1133 # CHECK-NEXT: Total uOps: 400 # CHECK: Dispatch Width: 2 -# CHECK-NEXT: uOps Per Cycle: 0.37 -# CHECK-NEXT: IPC: 0.37 -# CHECK-NEXT: Block RThroughput: 848.0 +# CHECK-NEXT: uOps Per Cycle: 0.35 +# CHECK-NEXT: IPC: 0.35 +# CHECK-NEXT: Block RThroughput: 524.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -431,819 +431,819 @@ vsm.v v1, (a0) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu # CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu # CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu # CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu # CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu # CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu # CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu # CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle16.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu # CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu # CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu # CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: 1 4 3.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle32.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 5.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 8.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 9.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 * vle64.v v1, (a0) +# CHECK-NEXT: 1 4 17.00 * vle64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu # CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu # CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu # CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu # CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse8.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu # CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu # CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu # CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse16.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse16.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse32.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu # CHECK-NEXT: 1 1 2.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse32.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 1 2.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse32.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu # CHECK-NEXT: 1 1 2.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 * vse32.v v1, (a0) -# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu # CHECK-NEXT: 1 1 2.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: 1 1 3.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse32.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse32.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 2.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 2.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 2.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 2.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 4.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 5.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 8.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 9.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 16.00 * vse64.v v1, (a0) +# CHECK-NEXT: 1 1 17.00 * vse64.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0) +# CHECK-NEXT: 1 4 3.00 * vlm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0) +# CHECK-NEXT: 1 1 3.00 * vsm.v v1, (a0) # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 200.00 - 848.00 - 424.00 424.00 +# CHECK-NEXT: - - 200.00 - - 200.00 524.00 524.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 2.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 - 4.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 5.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 - 8.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 9.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 - 16.00 - vle64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 17.00 - vle64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse8.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse8.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse16.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse16.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 1.00 - - 1.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 2.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse32.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse32.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 4.00 - - 4.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 5.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 8.00 - - 8.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 9.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 - - 16.00 vse64.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 17.00 vse64.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 3.00 - vlm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0) +# CHECK-NEXT: - - - - - 1.00 - 3.00 vsm.v v1, (a0) diff --git a/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-instrument.s b/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-instrument.s index 9c958f5a4939..d458a1126b4e 100644 --- a/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-instrument.s +++ b/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-instrument.s @@ -14,7 +14,7 @@ vadd.vv v12, v12, v12 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.33 # CHECK-NEXT: IPC: 0.33 -# CHECK-NEXT: Block RThroughput: 18.0 +# CHECK-NEXT: Block RThroughput: 20.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,30 +26,30 @@ vadd.vv v12, v12, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 2.00 - 18.00 18.00 - - +# CHECK-NEXT: - - 2.00 - 20.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: 01 diff --git a/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s b/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s index 4830fb12e6db..f649e047ece3 100644 --- a/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s +++ b/llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s @@ -8,13 +8,13 @@ vdiv.vv v8, v8, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 4 -# CHECK-NEXT: Total Cycles: 1140 +# CHECK-NEXT: Total Cycles: 1141 # CHECK-NEXT: Total uOps: 4 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.00 # CHECK-NEXT: IPC: 0.00 -# CHECK-NEXT: Block RThroughput: 1136.0 +# CHECK-NEXT: Block RThroughput: 1138.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,30 +26,30 @@ vdiv.vv v8, v8, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu -# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e32, m8, tu, mu -# CHECK-NEXT: 1 896 896.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 896 897.00 vdiv.vv v8, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 2.00 - 1136.00 1136.00 - - +# CHECK-NEXT: - - 2.00 - 1138.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu -# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e32, m8, tu, mu -# CHECK-NEXT: - - - - 896.00 896.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 897.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 0123 diff --git a/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s b/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s index 8beefd39cf84..5af02d7ebafe 100644 --- a/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s +++ b/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s @@ -14,7 +14,7 @@ vadd.vv v12, v12, v12 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.33 # CHECK-NEXT: IPC: 0.33 -# CHECK-NEXT: Block RThroughput: 18.0 +# CHECK-NEXT: Block RThroughput: 20.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,30 +26,30 @@ vadd.vv v12, v12, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu -# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 +# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 2.00 - 18.00 18.00 - - +# CHECK-NEXT: - - 2.00 - 20.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu -# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 +# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12 # CHECK: Timeline view: # CHECK-NEXT: 01 diff --git a/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s b/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s index 79d6d715207e..8016ca3eac44 100644 --- a/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s +++ b/llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s @@ -8,13 +8,13 @@ vdiv.vv v8, v8, v12 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 4 -# CHECK-NEXT: Total Cycles: 1140 +# CHECK-NEXT: Total Cycles: 1141 # CHECK-NEXT: Total uOps: 4 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.00 # CHECK-NEXT: IPC: 0.00 -# CHECK-NEXT: Block RThroughput: 1136.0 +# CHECK-NEXT: Block RThroughput: 1138.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,30 +26,30 @@ vdiv.vv v8, v8, v12 # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m8, tu, mu -# CHECK-NEXT: 1 896 896.00 vdiv.vv v8, v8, v12 +# CHECK-NEXT: 1 896 897.00 vdiv.vv v8, v8, v12 # CHECK: Resources: # CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [3] - SiFive7PipeB -# CHECK-NEXT: [4] - SiFive7PipeV -# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [4] - SiFive7VA +# CHECK-NEXT: [5] - SiFive7VCQ # CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [7] - SiFive7VS # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 2.00 - 1136.00 1136.00 - - +# CHECK-NEXT: - - 2.00 - 1138.00 2.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu -# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e32, m8, tu, mu -# CHECK-NEXT: - - - - 896.00 896.00 - - vdiv.vv v8, v8, v12 +# CHECK-NEXT: - - - - 897.00 1.00 - - vdiv.vv v8, v8, v12 # CHECK: Timeline view: # CHECK-NEXT: Index 0123 diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test index e32dc893fa79..55a3e645b883 100644 --- a/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test +++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-loongarch64.test @@ -93,15 +93,14 @@ # CHECK: Type: R_LARCH_TLS_GD_HI20 (98) # CHECK: Type: R_LARCH_32_PCREL (99) # CHECK: Type: R_LARCH_RELAX (100) -# CHECK: Type: R_LARCH_DELETE (101) # CHECK: Type: R_LARCH_ALIGN (102) # CHECK: Type: R_LARCH_PCREL20_S2 (103) -# CHECK: Type: R_LARCH_CFA (104) # CHECK: Type: R_LARCH_ADD6 (105) # CHECK: Type: R_LARCH_SUB6 (106) # CHECK: Type: R_LARCH_ADD_ULEB128 (107) # CHECK: Type: R_LARCH_SUB_ULEB128 (108) # CHECK: Type: R_LARCH_64_PCREL (109) +# CHECK: Type: R_LARCH_CALL36 (110) --- !ELF FileHeader: @@ -202,12 +201,11 @@ Sections: - Type: R_LARCH_TLS_GD_HI20 - Type: R_LARCH_32_PCREL - Type: R_LARCH_RELAX - - Type: R_LARCH_DELETE - Type: R_LARCH_ALIGN - Type: R_LARCH_PCREL20_S2 - - Type: R_LARCH_CFA - Type: R_LARCH_ADD6 - Type: R_LARCH_SUB6 - Type: R_LARCH_ADD_ULEB128 - Type: R_LARCH_SUB_ULEB128 - Type: R_LARCH_64_PCREL + - Type: R_LARCH_CALL36 diff --git a/llvm/tools/lli/lli.cpp b/llvm/tools/lli/lli.cpp index 9d95cbcb29c2..36fca4c40ed0 100644 --- a/llvm/tools/lli/lli.cpp +++ b/llvm/tools/lli/lli.cpp @@ -453,7 +453,7 @@ int main(int argc, char **argv, char * const *envp) { exit(1); } - if (UseJITKind == JITKind::MCJIT) + if (UseJITKind == JITKind::MCJIT || ForceInterpreter) disallowOrcOptions(); else return runOrcJIT(argv[0]); diff --git a/llvm/tools/llvm-c-test/echo.cpp b/llvm/tools/llvm-c-test/echo.cpp index 3b07ccb29f3e..e2617583ff9b 100644 --- a/llvm/tools/llvm-c-test/echo.cpp +++ b/llvm/tools/llvm-c-test/echo.cpp @@ -656,7 +656,9 @@ struct FunCloner { case LLVMOr: { LLVMValueRef LHS = CloneValue(LLVMGetOperand(Src, 0)); LLVMValueRef RHS = CloneValue(LLVMGetOperand(Src, 1)); + LLVMBool IsDisjoint = LLVMGetIsDisjoint(Src); Dst = LLVMBuildOr(Builder, LHS, RHS, Name); + LLVMSetIsDisjoint(Dst, IsDisjoint); break; } case LLVMXor: { diff --git a/llvm/tools/llvm-exegesis/lib/Analysis.cpp b/llvm/tools/llvm-exegesis/lib/Analysis.cpp index bd088b907aaf..2b924b9423f4 100644 --- a/llvm/tools/llvm-exegesis/lib/Analysis.cpp +++ b/llvm/tools/llvm-exegesis/lib/Analysis.cpp @@ -13,7 +13,6 @@ #include "llvm/MC/MCTargetOptions.h" #include "llvm/Support/FormatVariadic.h" #include -#include #include namespace llvm { diff --git a/llvm/tools/llvm-exegesis/lib/Analysis.h b/llvm/tools/llvm-exegesis/lib/Analysis.h index a0f22bad1ade..4a85d45a2d56 100644 --- a/llvm/tools/llvm-exegesis/lib/Analysis.h +++ b/llvm/tools/llvm-exegesis/lib/Analysis.h @@ -23,7 +23,6 @@ #include "llvm/Support/Error.h" #include "llvm/Support/raw_ostream.h" #include -#include namespace llvm { namespace exegesis { diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp b/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp index 33180d1099c7..dd7c1a315531 100644 --- a/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp +++ b/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// -#include #include #include @@ -17,7 +16,6 @@ #include "PerfHelper.h" #include "SubprocessMemory.h" #include "Target.h" -#include "llvm/ADT/ScopeExit.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Twine.h" diff --git a/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp b/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp index 08fd7184068c..59107577d17c 100644 --- a/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp +++ b/llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp @@ -12,8 +12,6 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/MCA/Support.h" #include "llvm/Support/FormatVariadic.h" -#include -#include #include namespace llvm { diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp index 4e0c968e28be..7dcff60a8fd1 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// -#include #include #include "Assembler.h" diff --git a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp index bb1b3a9569c7..cc5a045a8be5 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp @@ -6,8 +6,6 @@ // //===----------------------------------------------------------------------===// -#include - #include "SnippetRepetitor.h" #include "Target.h" #include "llvm/ADT/Sequence.h" diff --git a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp index 17fb70f39b6a..3d6247ca6a25 100644 --- a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp +++ b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp @@ -692,11 +692,12 @@ getTestObjectFileInterface(Session &S, MemoryBufferRef O) { } static Error loadProcessSymbols(Session &S) { + S.ProcessSymsJD = &S.ES.createBareJITDylib("Process"); auto FilterMainEntryPoint = [EPName = S.ES.intern(EntryPointName)](SymbolStringPtr Name) { return Name != EPName; }; - S.MainJD->addGenerator( + S.ProcessSymsJD->addGenerator( ExitOnErr(orc::EPCDynamicLibrarySearchGenerator::GetForTargetProcess( S.ES, std::move(FilterMainEntryPoint)))); @@ -707,8 +708,9 @@ static Error loadDylibs(Session &S) { LLVM_DEBUG(dbgs() << "Loading dylibs...\n"); for (const auto &Dylib : Dylibs) { LLVM_DEBUG(dbgs() << " " << Dylib << "\n"); - if (auto Err = S.loadAndLinkDynamicLibrary(*S.MainJD, Dylib)) - return Err; + auto DL = S.getOrLoadDynamicLibrary(Dylib); + if (!DL) + return DL.takeError(); } return Error::success(); @@ -963,69 +965,79 @@ Session::Session(std::unique_ptr EPC, Error &Err) ES.setErrorReporter(reportLLVMJITLinkError); - if (auto MainJDOrErr = ES.createJITDylib("main")) - MainJD = &*MainJDOrErr; - else { - Err = MainJDOrErr.takeError(); - return; - } - if (!NoProcessSymbols) ExitOnErr(loadProcessSymbols(*this)); - else { - // This symbol is used in testcases. - auto &TestResultJD = ES.createBareJITDylib(""); - ExitOnErr(TestResultJD.define(absoluteSymbols( - {{ES.intern("llvm_jitlink_setTestResultOverride"), - {ExecutorAddr::fromPtr(llvm_jitlink_setTestResultOverride), - JITSymbolFlags::Exported}}}))); - MainJD->addToLinkOrder(TestResultJD); - } ExitOnErr(loadDylibs(*this)); auto &TT = ES.getTargetTriple(); - if (DebuggerSupport && TT.isOSBinFormatMachO()) - ObjLayer.addPlugin(ExitOnErr( - GDBJITDebugInfoRegistrationPlugin::Create(this->ES, *MainJD, TT))); + if (DebuggerSupport && TT.isOSBinFormatMachO()) { + if (!ProcessSymsJD) { + Err = make_error("MachO debugging requires process symbols", + inconvertibleErrorCode()); + return; + } + ObjLayer.addPlugin(ExitOnErr(GDBJITDebugInfoRegistrationPlugin::Create( + this->ES, *ProcessSymsJD, TT))); + } if (PerfSupport && TT.isOSBinFormatELF()) { + if (!ProcessSymsJD) { + Err = make_error("MachO debugging requires process symbols", + inconvertibleErrorCode()); + return; + } ObjLayer.addPlugin(ExitOnErr(DebugInfoPreservationPlugin::Create())); ObjLayer.addPlugin(ExitOnErr(PerfSupportPlugin::Create( - this->ES.getExecutorProcessControl(), *MainJD, true, true))); + this->ES.getExecutorProcessControl(), *ProcessSymsJD, true, true))); } // Set up the platform. - if (TT.isOSBinFormatMachO() && !OrcRuntime.empty()) { - if (auto P = - MachOPlatform::Create(ES, ObjLayer, *MainJD, OrcRuntime.c_str())) - ES.setPlatform(std::move(*P)); - else { - Err = P.takeError(); - return; - } - } else if (TT.isOSBinFormatELF() && !OrcRuntime.empty()) { - if (auto P = - ELFNixPlatform::Create(ES, ObjLayer, *MainJD, OrcRuntime.c_str())) - ES.setPlatform(std::move(*P)); - else { - Err = P.takeError(); - return; - } - } else if (TT.isOSBinFormatCOFF() && !OrcRuntime.empty()) { - auto LoadDynLibrary = [&, this](JITDylib &JD, StringRef DLLName) -> Error { - if (!DLLName.ends_with_insensitive(".dll")) - return make_error("DLLName not ending with .dll", - inconvertibleErrorCode()); - return loadAndLinkDynamicLibrary(JD, DLLName); - }; + if (!OrcRuntime.empty()) { + assert(ProcessSymsJD && "ProcessSymsJD should have been set"); + PlatformJD = &ES.createBareJITDylib("Platform"); + PlatformJD->addToLinkOrder(*ProcessSymsJD); + + if (TT.isOSBinFormatMachO()) { + if (auto P = MachOPlatform::Create(ES, ObjLayer, *PlatformJD, + OrcRuntime.c_str())) + ES.setPlatform(std::move(*P)); + else { + Err = P.takeError(); + return; + } + } else if (TT.isOSBinFormatELF()) { + if (auto P = ELFNixPlatform::Create(ES, ObjLayer, *PlatformJD, + OrcRuntime.c_str())) + ES.setPlatform(std::move(*P)); + else { + Err = P.takeError(); + return; + } + } else if (TT.isOSBinFormatCOFF()) { + auto LoadDynLibrary = [&, this](JITDylib &JD, + StringRef DLLName) -> Error { + if (!DLLName.ends_with_insensitive(".dll")) + return make_error("DLLName not ending with .dll", + inconvertibleErrorCode()); + return loadAndLinkDynamicLibrary(JD, DLLName); + }; - if (auto P = COFFPlatform::Create(ES, ObjLayer, *MainJD, OrcRuntime.c_str(), - std::move(LoadDynLibrary))) - ES.setPlatform(std::move(*P)); - else { - Err = P.takeError(); + if (auto P = COFFPlatform::Create(ES, ObjLayer, *PlatformJD, + OrcRuntime.c_str(), + std::move(LoadDynLibrary))) + ES.setPlatform(std::move(*P)); + else { + Err = P.takeError(); + return; + } + } else { + Err = make_error( + "-" + OrcRuntime.ArgStr + " specified, but format " + + Triple::getObjectFormatTypeName(TT.getObjectFormat()) + + " not supported", + inconvertibleErrorCode()); return; } } else if (TT.isOSBinFormatELF()) { @@ -1037,6 +1049,24 @@ Session::Session(std::unique_ptr EPC, Error &Err) ES, ExitOnErr(createJITLoaderGDBRegistrar(this->ES)), true, true)); } + if (auto MainJDOrErr = ES.createJITDylib("main")) + MainJD = &*MainJDOrErr; + else { + Err = MainJDOrErr.takeError(); + return; + } + + if (NoProcessSymbols) { + // This symbol is used in testcases, but we're not reflecting process + // symbols so we'll need to make it available some other way. + auto &TestResultJD = ES.createBareJITDylib(""); + ExitOnErr(TestResultJD.define(absoluteSymbols( + {{ES.intern("llvm_jitlink_setTestResultOverride"), + {ExecutorAddr::fromPtr(llvm_jitlink_setTestResultOverride), + JITSymbolFlags::Exported}}}))); + MainJD->addToLinkOrder(TestResultJD); + } + ObjLayer.addPlugin(std::make_unique(*this)); // Process any harness files. @@ -1266,6 +1296,10 @@ static Error sanitizeArguments(const Triple &TT, const char *ArgV0) { if (DebuggerSupport.getNumOccurrences() == 0 && NoExec) DebuggerSupport = false; + if (!OrcRuntime.empty() && NoProcessSymbols) + return make_error("-orc-runtime requires process symbols", + inconvertibleErrorCode()); + // If -slab-allocate is passed, check that we're not trying to use it in // -oop-executor or -oop-executor-connect mode. // @@ -1365,6 +1399,13 @@ static Error createJITDylibs(Session &S, } } + if (S.PlatformJD) + S.JDSearchOrder.push_back( + {S.PlatformJD, JITDylibLookupFlags::MatchExportedSymbolsOnly}); + if (S.ProcessSymsJD) + S.JDSearchOrder.push_back( + {S.ProcessSymsJD, JITDylibLookupFlags::MatchExportedSymbolsOnly}); + LLVM_DEBUG({ dbgs() << "Dylib search order is [ "; for (auto &KV : S.JDSearchOrder) @@ -1416,23 +1457,67 @@ static Error addAliases(Session &S, const std::map &IdxToJD) { // Define absolute symbols. LLVM_DEBUG(dbgs() << "Defining aliases...\n"); + + DenseMap, SymbolAliasMap> Reexports; for (auto AliasItr = Aliases.begin(), AliasEnd = Aliases.end(); AliasItr != AliasEnd; ++AliasItr) { - unsigned AliasArgIdx = Aliases.getPosition(AliasItr - Aliases.begin()); - auto &JD = *std::prev(IdxToJD.lower_bound(AliasArgIdx))->second; - StringRef AliasStmt = *AliasItr; - size_t EqIdx = AliasStmt.find_first_of('='); - if (EqIdx == StringRef::npos) - return make_error("Invalid alias definition \"" + AliasStmt + - "\". Syntax: =", - inconvertibleErrorCode()); - StringRef Alias = AliasStmt.substr(0, EqIdx).trim(); - StringRef Aliasee = AliasStmt.substr(EqIdx + 1).trim(); + auto BadExpr = [&]() { + return make_error( + "Invalid alias definition \"" + *AliasItr + + "\". Syntax: [:]=[:]", + inconvertibleErrorCode()); + }; + + auto GetJD = [&](StringRef JDName) -> Expected { + if (JDName.empty()) { + unsigned AliasArgIdx = Aliases.getPosition(AliasItr - Aliases.begin()); + return std::prev(IdxToJD.lower_bound(AliasArgIdx))->second; + } + + auto *JD = S.ES.getJITDylibByName(JDName); + if (!JD) + return make_error(StringRef("In alias definition \"") + + *AliasItr + "\" no dylib named " + + JDName, + inconvertibleErrorCode()); - SymbolAliasMap SAM; - SAM[S.ES.intern(Alias)] = {S.ES.intern(Aliasee), JITSymbolFlags::Exported}; - if (auto Err = JD.define(symbolAliases(std::move(SAM)))) + return JD; + }; + + { + // First split on '=' to get alias and aliasee. + StringRef AliasStmt = *AliasItr; + auto [AliasExpr, AliaseeExpr] = AliasStmt.split('='); + if (AliaseeExpr.empty()) + return BadExpr(); + + auto [AliasJDName, Alias] = AliasExpr.split(':'); + if (Alias.empty()) + std::swap(AliasJDName, Alias); + + auto AliasJD = GetJD(AliasJDName); + if (!AliasJD) + return AliasJD.takeError(); + + auto [AliaseeJDName, Aliasee] = AliaseeExpr.split(':'); + if (Aliasee.empty()) + std::swap(AliaseeJDName, Aliasee); + + if (AliaseeJDName.empty() && !AliasJDName.empty()) + AliaseeJDName = AliasJDName; + auto AliaseeJD = GetJD(AliaseeJDName); + if (!AliaseeJD) + return AliaseeJD.takeError(); + + Reexports[{*AliasJD, *AliaseeJD}][S.ES.intern(Alias)] = { + S.ES.intern(Aliasee), JITSymbolFlags::Exported}; + } + } + + for (auto &[JDs, AliasMap] : Reexports) { + auto [DstJD, SrcJD] = JDs; + if (auto Err = DstJD->define(reexports(*SrcJD, std::move(AliasMap)))) return Err; } @@ -1766,6 +1851,14 @@ static Error addLibraries(Session &S, inconvertibleErrorCode()); } + // Add platform and process symbols if available. + for (auto &[Idx, JD] : IdxToJD) { + if (S.PlatformJD) + JD->addToLinkOrder(*S.PlatformJD); + if (S.ProcessSymsJD) + JD->addToLinkOrder(*S.ProcessSymsJD); + } + return Error::success(); } diff --git a/llvm/tools/llvm-jitlink/llvm-jitlink.h b/llvm/tools/llvm-jitlink/llvm-jitlink.h index 54a16ba171b3..3ff406b7b82d 100644 --- a/llvm/tools/llvm-jitlink/llvm-jitlink.h +++ b/llvm/tools/llvm-jitlink/llvm-jitlink.h @@ -31,6 +31,8 @@ struct Session { orc::ExecutionSession ES; orc::JITDylib *MainJD = nullptr; + orc::JITDylib *ProcessSymsJD = nullptr; + orc::JITDylib *PlatformJD = nullptr; orc::ObjectLinkingLayer ObjLayer; orc::JITDylibSearchOrder JDSearchOrder; SubtargetFeatures Features; diff --git a/llvm/tools/llvm-reduce/deltas/Delta.cpp b/llvm/tools/llvm-reduce/deltas/Delta.cpp index 46bc93c1ce33..62dfd62a4d5a 100644 --- a/llvm/tools/llvm-reduce/deltas/Delta.cpp +++ b/llvm/tools/llvm-reduce/deltas/Delta.cpp @@ -29,7 +29,6 @@ #include "llvm/Support/MemoryBufferRef.h" #include "llvm/Support/ThreadPool.h" #include -#include using namespace llvm; diff --git a/llvm/tools/llvm-reduce/deltas/Delta.h b/llvm/tools/llvm-reduce/deltas/Delta.h index f39ee00c066c..96fcea89484c 100644 --- a/llvm/tools/llvm-reduce/deltas/Delta.h +++ b/llvm/tools/llvm-reduce/deltas/Delta.h @@ -17,7 +17,6 @@ #include "ReducerWorkItem.h" #include "llvm/ADT/ArrayRef.h" -#include "llvm/ADT/ScopeExit.h" #include "llvm/Support/raw_ostream.h" #include #include diff --git a/llvm/tools/llvm-reduce/deltas/ReduceDIMetadata.cpp b/llvm/tools/llvm-reduce/deltas/ReduceDIMetadata.cpp index da4bde58e6ad..f4d8496aba4a 100644 --- a/llvm/tools/llvm-reduce/deltas/ReduceDIMetadata.cpp +++ b/llvm/tools/llvm-reduce/deltas/ReduceDIMetadata.cpp @@ -18,8 +18,6 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/InstIterator.h" -#include -#include #include #include diff --git a/llvm/tools/vfabi-demangle-fuzzer/vfabi-demangler-fuzzer.cpp b/llvm/tools/vfabi-demangle-fuzzer/vfabi-demangler-fuzzer.cpp index 09dc15c9e366..a6ca3bc4484e 100644 --- a/llvm/tools/vfabi-demangle-fuzzer/vfabi-demangler-fuzzer.cpp +++ b/llvm/tools/vfabi-demangle-fuzzer/vfabi-demangler-fuzzer.cpp @@ -31,14 +31,7 @@ extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) { if (!MangledName.empty() && MangledName.find_first_of(0) == StringRef::npos) { FunctionType *FTy = FunctionType::get(Type::getVoidTy(M->getContext()), false); - FunctionCallee F = M->getOrInsertFunction(MangledName, FTy); - // Fake the arguments to the CallInst. - SmallVector Args; - for (Type *ParamTy : FTy->params()) { - Args.push_back(Constant::getNullValue(ParamTy)); - } - std::unique_ptr CI(CallInst::Create(F, Args)); - const auto Info = VFABI::tryDemangleForVFABI(MangledName, *(CI.get())); + const auto Info = VFABI::tryDemangleForVFABI(MangledName, FTy); // Do not optimize away the return value. Inspired by // https://github.com/google/benchmark/blob/main/include/benchmark/benchmark.h#L307-L345 diff --git a/llvm/unittests/Analysis/ValueTrackingTest.cpp b/llvm/unittests/Analysis/ValueTrackingTest.cpp index 1190550340ef..0d3a594da0c0 100644 --- a/llvm/unittests/Analysis/ValueTrackingTest.cpp +++ b/llvm/unittests/Analysis/ValueTrackingTest.cpp @@ -2604,7 +2604,7 @@ TEST_F(ValueTrackingTest, HaveNoCommonBitsSet) { { // Check for an inverted mask: (X & ~M) op (Y & M). auto M = parseModule(R"( - define i32 @test(i32 %X, i32 %Y, i32 %M) { + define i32 @test(i32 %X, i32 %Y, i32 noundef %M) { %1 = xor i32 %M, -1 %LHS = and i32 %1, %X %RHS = and i32 %Y, %M @@ -2623,7 +2623,7 @@ TEST_F(ValueTrackingTest, HaveNoCommonBitsSet) { { // Check for (A & B) and ~(A | B) auto M = parseModule(R"( - define void @test(i32 %A, i32 %B) { + define void @test(i32 noundef %A, i32 noundef %B) { %LHS = and i32 %A, %B %or = or i32 %A, %B %RHS = xor i32 %or, -1 @@ -2651,7 +2651,7 @@ TEST_F(ValueTrackingTest, HaveNoCommonBitsSet) { { // Check for (A & B) and ~(A | B) in vector version auto M = parseModule(R"( - define void @test(<2 x i32> %A, <2 x i32> %B) { + define void @test(<2 x i32> noundef %A, <2 x i32> noundef %B) { %LHS = and <2 x i32> %A, %B %or = or <2 x i32> %A, %B %RHS = xor <2 x i32> %or, diff --git a/llvm/unittests/Analysis/VectorFunctionABITest.cpp b/llvm/unittests/Analysis/VectorFunctionABITest.cpp index e496d87c06de..81c1807cdcaa 100644 --- a/llvm/unittests/Analysis/VectorFunctionABITest.cpp +++ b/llvm/unittests/Analysis/VectorFunctionABITest.cpp @@ -82,7 +82,8 @@ protected: Args.push_back(Constant::getNullValue(ParamTy->getScalarType())); } std::unique_ptr CI(CallInst::Create(F, Args)); - const auto OptInfo = VFABI::tryDemangleForVFABI(MangledName, *(CI.get())); + const auto OptInfo = + VFABI::tryDemangleForVFABI(MangledName, CI->getFunctionType()); if (OptInfo) { Info = *OptInfo; return true; diff --git a/llvm/unittests/Analysis/VectorUtilsTest.cpp b/llvm/unittests/Analysis/VectorUtilsTest.cpp index c7419e032123..1b3a8b0259f0 100644 --- a/llvm/unittests/Analysis/VectorUtilsTest.cpp +++ b/llvm/unittests/Analysis/VectorUtilsTest.cpp @@ -580,7 +580,7 @@ protected: SmallVector &ExpectedParams = Expected.Parameters; void buildShape(ElementCount VF, bool HasGlobalPred) { - Shape = VFShape::get(*CI, VF, HasGlobalPred); + Shape = VFShape::get(CI->getFunctionType(), VF, HasGlobalPred); } bool validParams(ArrayRef Parameters) { @@ -619,11 +619,11 @@ TEST_F(VFShapeAPITest, API_buildVFShape) { TEST_F(VFShapeAPITest, API_getScalarShape) { buildShape(/*VF*/ ElementCount::getFixed(1), /*HasGlobalPred*/ false); - EXPECT_EQ(VFShape::getScalarShape(*CI), Shape); + EXPECT_EQ(VFShape::getScalarShape(CI->getFunctionType()), Shape); } TEST_F(VFShapeAPITest, API_getVectorizedFunction) { - VFShape ScalarShape = VFShape::getScalarShape(*CI); + VFShape ScalarShape = VFShape::getScalarShape(CI->getFunctionType()); EXPECT_EQ(VFDatabase(*CI).getVectorizedFunction(ScalarShape), M->getFunction("g")); diff --git a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp index 2876aa49da40..193ada3a4ea3 100644 --- a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp +++ b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp @@ -2228,9 +2228,77 @@ TEST_F(OpenMPIRBuilderTest, UnrollLoopHeuristic) { EXPECT_TRUE(getBooleanLoopAttribute(L, "llvm.loop.unroll.enable")); } +TEST_F(OpenMPIRBuilderTest, StaticWorkshareLoopTarget) { + using InsertPointTy = OpenMPIRBuilder::InsertPointTy; + std::string oldDLStr = M->getDataLayoutStr(); + M->setDataLayout( + "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:" + "256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:" + "256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"); + OpenMPIRBuilder OMPBuilder(*M); + OMPBuilder.Config.IsTargetDevice = true; + OMPBuilder.initialize(); + IRBuilder<> Builder(BB); + OpenMPIRBuilder::LocationDescription Loc({Builder.saveIP(), DL}); + InsertPointTy AllocaIP = Builder.saveIP(); + + Type *LCTy = Type::getInt32Ty(Ctx); + Value *StartVal = ConstantInt::get(LCTy, 10); + Value *StopVal = ConstantInt::get(LCTy, 52); + Value *StepVal = ConstantInt::get(LCTy, 2); + auto LoopBodyGen = [&](InsertPointTy, Value *) {}; + + CanonicalLoopInfo *CLI = OMPBuilder.createCanonicalLoop( + Loc, LoopBodyGen, StartVal, StopVal, StepVal, false, false); + BasicBlock *Preheader = CLI->getPreheader(); + Value *TripCount = CLI->getTripCount(); + + Builder.SetInsertPoint(BB, BB->getFirstInsertionPt()); + + IRBuilder<>::InsertPoint AfterIP = OMPBuilder.applyWorkshareLoop( + DL, CLI, AllocaIP, true, OMP_SCHEDULE_Static, nullptr, false, false, + false, false, WorksharingLoopType::ForStaticLoop); + Builder.restoreIP(AfterIP); + Builder.CreateRetVoid(); + + OMPBuilder.finalize(); + EXPECT_FALSE(verifyModule(*M, &errs())); + + CallInst *WorkshareLoopRuntimeCall = nullptr; + int WorkshareLoopRuntimeCallCnt = 0; + for (auto Inst = Preheader->begin(); Inst != Preheader->end(); ++Inst) { + CallInst *Call = dyn_cast(Inst); + if (!Call) + continue; + if (!Call->getCalledFunction()) + continue; + + if (Call->getCalledFunction()->getName() == "__kmpc_for_static_loop_4u") { + WorkshareLoopRuntimeCall = Call; + WorkshareLoopRuntimeCallCnt++; + } + } + EXPECT_NE(WorkshareLoopRuntimeCall, nullptr); + // Verify that there is only one call to workshare loop function + EXPECT_EQ(WorkshareLoopRuntimeCallCnt, 1); + // Check that pointer to loop body function is passed as second argument + Value *LoopBodyFuncArg = WorkshareLoopRuntimeCall->getArgOperand(1); + EXPECT_EQ(Builder.getPtrTy(), LoopBodyFuncArg->getType()); + Function *ArgFunction = dyn_cast(LoopBodyFuncArg); + EXPECT_NE(ArgFunction, nullptr); + EXPECT_EQ(ArgFunction->arg_size(), 1u); + EXPECT_EQ(ArgFunction->getArg(0)->getType(), TripCount->getType()); + // Check that no variables except for loop counter are used in loop body + EXPECT_EQ(Constant::getNullValue(Builder.getPtrTy()), + WorkshareLoopRuntimeCall->getArgOperand(2)); + // Check loop trip count argument + EXPECT_EQ(TripCount, WorkshareLoopRuntimeCall->getArgOperand(3)); +} + TEST_F(OpenMPIRBuilderTest, StaticWorkShareLoop) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); + OMPBuilder.Config.IsTargetDevice = false; OMPBuilder.initialize(); IRBuilder<> Builder(BB); OpenMPIRBuilder::LocationDescription Loc({Builder.saveIP(), DL}); @@ -2331,6 +2399,7 @@ TEST_P(OpenMPIRBuilderTestWithIVBits, StaticChunkedWorkshareLoop) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); + OMPBuilder.Config.IsTargetDevice = false; BasicBlock *Body; CallInst *Call; @@ -2405,6 +2474,7 @@ INSTANTIATE_TEST_SUITE_P(IVBits, OpenMPIRBuilderTestWithIVBits, TEST_P(OpenMPIRBuilderTestWithParams, DynamicWorkShareLoop) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); + OMPBuilder.Config.IsTargetDevice = false; OMPBuilder.initialize(); IRBuilder<> Builder(BB); OpenMPIRBuilder::LocationDescription Loc({Builder.saveIP(), DL}); @@ -2562,6 +2632,7 @@ INSTANTIATE_TEST_SUITE_P( TEST_F(OpenMPIRBuilderTest, DynamicWorkShareLoopOrdered) { using InsertPointTy = OpenMPIRBuilder::InsertPointTy; OpenMPIRBuilder OMPBuilder(*M); + OMPBuilder.Config.IsTargetDevice = false; OMPBuilder.initialize(); IRBuilder<> Builder(BB); OpenMPIRBuilder::LocationDescription Loc({Builder.saveIP(), DL}); diff --git a/llvm/unittests/IR/BasicBlockDbgInfoTest.cpp b/llvm/unittests/IR/BasicBlockDbgInfoTest.cpp index d239e3b2d83e..fb4847fc0a82 100644 --- a/llvm/unittests/IR/BasicBlockDbgInfoTest.cpp +++ b/llvm/unittests/IR/BasicBlockDbgInfoTest.cpp @@ -42,6 +42,78 @@ static std::unique_ptr parseIR(LLVMContext &C, const char *IR) { namespace { +// We can occasionally moveAfter an instruction so that it moves to the +// position that it already resides at. This is fine -- but gets complicated +// with dbg.value intrinsics. By moving an instruction, we can end up changing +// nothing but the location of debug-info intrinsics. That has to be modelled +// by DPValues, the dbg.value replacement. +TEST(BasicBlockDbgInfoTest, InsertAfterSelf) { + LLVMContext C; + UseNewDbgInfoFormat = true; + + std::unique_ptr M = parseIR(C, R"( + define i16 @f(i16 %a) !dbg !6 { + call void @llvm.dbg.value(metadata i16 %a, metadata !9, metadata !DIExpression()), !dbg !11 + %b = add i16 %a, 1, !dbg !11 + call void @llvm.dbg.value(metadata i16 %b, metadata !9, metadata !DIExpression()), !dbg !11 + %c = add i16 %b, 1, !dbg !11 + ret i16 0, !dbg !11 + } + declare void @llvm.dbg.value(metadata, metadata, metadata) #0 + attributes #0 = { nounwind readnone speculatable willreturn } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!5} + + !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) + !1 = !DIFile(filename: "t.ll", directory: "/") + !2 = !{} + !5 = !{i32 2, !"Debug Info Version", i32 3} + !6 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !7, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) + !7 = !DISubroutineType(types: !2) + !8 = !{!9} + !9 = !DILocalVariable(name: "1", scope: !6, file: !1, line: 1, type: !10) + !10 = !DIBasicType(name: "ty16", size: 16, encoding: DW_ATE_unsigned) + !11 = !DILocation(line: 1, column: 1, scope: !6) +)"); + + // Convert the module to "new" form debug-info. + M->convertToNewDbgValues(); + // Fetch the entry block. + BasicBlock &BB = M->getFunction("f")->getEntryBlock(); + + Instruction *Inst1 = &*BB.begin(); + Instruction *Inst2 = &*std::next(BB.begin()); + Instruction *RetInst = &*std::next(Inst2->getIterator()); + EXPECT_TRUE(Inst1->hasDbgValues()); + EXPECT_TRUE(Inst2->hasDbgValues()); + EXPECT_FALSE(RetInst->hasDbgValues()); + + // If we move Inst2 to be after Inst1, then it comes _immediately_ after. Were + // we in dbg.value form we would then have: + // dbg.value + // %b = add + // %c = add + // dbg.value + // Check that this is replicated by DPValues. + Inst2->moveAfter(Inst1); + + // Inst1 should only have one DPValue on it. + EXPECT_TRUE(Inst1->hasDbgValues()); + auto Range1 = Inst1->getDbgValueRange(); + EXPECT_EQ(std::distance(Range1.begin(), Range1.end()), 1u); + // Inst2 should have none. + EXPECT_FALSE(Inst2->hasDbgValues()); + // While the return inst should now have one on it. + EXPECT_TRUE(RetInst->hasDbgValues()); + auto Range2 = RetInst->getDbgValueRange(); + EXPECT_EQ(std::distance(Range2.begin(), Range2.end()), 1u); + + M->convertFromNewDbgValues(); + + UseNewDbgInfoFormat = false; +} + TEST(BasicBlockDbgInfoTest, MarkerOperations) { LLVMContext C; UseNewDbgInfoFormat = true; @@ -1409,5 +1481,58 @@ TEST(BasicBlockDbgInfoTest, DbgSpliceToEmpty2) { UseNewDbgInfoFormat = false; } + +// What if we moveBefore end() -- there might be no debug-info there, in which +// case we shouldn't crash. +TEST(BasicBlockDbgInfoTest, DbgMoveToEnd) { + LLVMContext C; + UseNewDbgInfoFormat = true; + + std::unique_ptr M = parseIR(C, R"( + define i16 @f(i16 %a) !dbg !6 { + entry: + br label %exit + + exit: + ret i16 0, !dbg !11 + } + declare void @llvm.dbg.value(metadata, metadata, metadata) #0 + attributes #0 = { nounwind readnone speculatable willreturn } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!5} + + !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) + !1 = !DIFile(filename: "t.ll", directory: "/") + !2 = !{} + !5 = !{i32 2, !"Debug Info Version", i32 3} + !6 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !7, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) + !7 = !DISubroutineType(types: !2) + !8 = !{!9} + !9 = !DILocalVariable(name: "1", scope: !6, file: !1, line: 1, type: !10) + !10 = !DIBasicType(name: "ty16", size: 16, encoding: DW_ATE_unsigned) + !11 = !DILocation(line: 1, column: 1, scope: !6) +)"); + + Function &F = *M->getFunction("f"); + BasicBlock &Entry = F.getEntryBlock(); + BasicBlock &Exit = *Entry.getNextNode(); + M->convertToNewDbgValues(); + + // Move the return to the end of the entry block. + Instruction *Br = Entry.getTerminator(); + Instruction *Ret = Exit.getTerminator(); + EXPECT_EQ(Entry.getTrailingDPValues(), nullptr); + Ret->moveBefore(Entry, Entry.end()); + Br->eraseFromParent(); + + // There should continue to not be any debug-info anywhere. + EXPECT_EQ(Entry.getTrailingDPValues(), nullptr); + EXPECT_EQ(Exit.getTrailingDPValues(), nullptr); + EXPECT_FALSE(Ret->hasDbgValues()); + + UseNewDbgInfoFormat = false; +} + } // End anonymous namespace. #endif // EXPERIMENTAL_DEBUGINFO_ITERATORS diff --git a/llvm/unittests/IR/DebugInfoTest.cpp b/llvm/unittests/IR/DebugInfoTest.cpp index a408c0af5623..be8f590a27eb 100644 --- a/llvm/unittests/IR/DebugInfoTest.cpp +++ b/llvm/unittests/IR/DebugInfoTest.cpp @@ -284,6 +284,71 @@ TEST(MetadataTest, DeleteInstUsedByDPValue) { UseNewDbgInfoFormat = OldDbgValueMode; } +// Ensure that the order of dbg.value intrinsics returned by findDbgValues, and +// their corresponding DPValue representation, are consistent. +TEST(MetadataTest, OrderingOfDPValues) { + LLVMContext C; + std::unique_ptr M = parseIR(C, R"( + define i16 @f(i16 %a) !dbg !6 { + %b = add i16 %a, 1, !dbg !11 + call void @llvm.dbg.value(metadata i16 %b, metadata !9, metadata !DIExpression()), !dbg !11 + call void @llvm.dbg.value(metadata i16 %b, metadata !12, metadata !DIExpression()), !dbg !11 + ret i16 0, !dbg !11 + } + declare void @llvm.dbg.value(metadata, metadata, metadata) #0 + attributes #0 = { nounwind readnone speculatable willreturn } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!5} + + !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) + !1 = !DIFile(filename: "t.ll", directory: "/") + !2 = !{} + !5 = !{i32 2, !"Debug Info Version", i32 3} + !6 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !7, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) + !7 = !DISubroutineType(types: !2) + !8 = !{!9} + !9 = !DILocalVariable(name: "foo", scope: !6, file: !1, line: 1, type: !10) + !10 = !DIBasicType(name: "ty16", size: 16, encoding: DW_ATE_unsigned) + !11 = !DILocation(line: 1, column: 1, scope: !6) + !12 = !DILocalVariable(name: "bar", scope: !6, file: !1, line: 1, type: !10) +)"); + + bool OldDbgValueMode = UseNewDbgInfoFormat; + UseNewDbgInfoFormat = true; + Instruction &I = *M->getFunction("f")->getEntryBlock().getFirstNonPHI(); + + SmallVector DVIs; + SmallVector DPVs; + findDbgValues(DVIs, &I, &DPVs); + ASSERT_EQ(DVIs.size(), 2u); + ASSERT_EQ(DPVs.size(), 0u); + + // The correct order of dbg.values is given by their use-list, which becomes + // the reverse order of creation. Thus the dbg.values should come out as + // "bar" and then "foo". + DILocalVariable *Var0 = DVIs[0]->getVariable(); + EXPECT_TRUE(Var0->getName() == "bar"); + DILocalVariable *Var1 = DVIs[1]->getVariable(); + EXPECT_TRUE(Var1->getName() == "foo"); + + // Now try again, but in DPValue form. + DVIs.clear(); + + M->convertToNewDbgValues(); + findDbgValues(DVIs, &I, &DPVs); + ASSERT_EQ(DVIs.size(), 0u); + ASSERT_EQ(DPVs.size(), 2u); + + Var0 = DPVs[0]->getVariable(); + EXPECT_TRUE(Var0->getName() == "bar"); + Var1 = DPVs[1]->getVariable(); + EXPECT_TRUE(Var1->getName() == "foo"); + + M->convertFromNewDbgValues(); + UseNewDbgInfoFormat = OldDbgValueMode; +} + TEST(DIBuiler, CreateFile) { LLVMContext Ctx; std::unique_ptr M(new Module("MyModule", Ctx)); diff --git a/llvm/unittests/Object/ELFTest.cpp b/llvm/unittests/Object/ELFTest.cpp index 50b1df124a4a..faf855c09cfe 100644 --- a/llvm/unittests/Object/ELFTest.cpp +++ b/llvm/unittests/Object/ELFTest.cpp @@ -233,14 +233,10 @@ TEST(ELFTest, getELFRelocationTypeNameForLoongArch) { getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_32_PCREL)); EXPECT_EQ("R_LARCH_RELAX", getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_RELAX)); - EXPECT_EQ("R_LARCH_DELETE", - getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_DELETE)); EXPECT_EQ("R_LARCH_ALIGN", getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_ALIGN)); EXPECT_EQ("R_LARCH_PCREL20_S2", getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_PCREL20_S2)); - EXPECT_EQ("R_LARCH_CFA", - getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_CFA)); EXPECT_EQ("R_LARCH_ADD6", getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_ADD6)); EXPECT_EQ("R_LARCH_SUB6", @@ -251,6 +247,8 @@ TEST(ELFTest, getELFRelocationTypeNameForLoongArch) { getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_SUB_ULEB128)); EXPECT_EQ("R_LARCH_64_PCREL", getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_64_PCREL)); + EXPECT_EQ("R_LARCH_CALL36", + getELFRelocationTypeName(EM_LOONGARCH, R_LARCH_CALL36)); } TEST(ELFTest, getELFRelativeRelocationType) { diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp index 135d7dbb426e..b4c96a9c2a62 100644 --- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp +++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp @@ -154,7 +154,6 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) { Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset, OffsetIsScalable, Width, TRI); - // TODO: AArch64 can handle this case, and we probably should too. BaseOps.clear(); MMO = MF->getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOStore, 4, Align(4)); @@ -165,7 +164,13 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) { .addMemOperand(MMO); Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset, OffsetIsScalable, Width, TRI); - EXPECT_FALSE(Res); + ASSERT_TRUE(Res); + ASSERT_EQ(BaseOps.size(), 1u); + ASSERT_TRUE(BaseOps.front()->isFI()); + EXPECT_EQ(BaseOps.front()->getIndex(), 2); + EXPECT_EQ(Offset, 4); + EXPECT_FALSE(OffsetIsScalable); + EXPECT_EQ(Width, 4u); } } // namespace diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp index 39294819f373..d93b02357ef7 100644 --- a/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp @@ -15,8 +15,6 @@ #include "SerialSnippetGenerator.h" #include "TestBase.h" -#include - namespace llvm { namespace exegesis { namespace { diff --git a/llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp index 007fa5b8c0d4..81651b359e93 100644 --- a/llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp @@ -15,8 +15,6 @@ #include "SerialSnippetGenerator.h" #include "TestBase.h" -#include - namespace llvm { namespace exegesis { namespace { diff --git a/llvm/utils/UpdateTestChecks/common.py b/llvm/utils/UpdateTestChecks/common.py index 5c3775e3d085..0fe0dfc506b0 100644 --- a/llvm/utils/UpdateTestChecks/common.py +++ b/llvm/utils/UpdateTestChecks/common.py @@ -1701,7 +1701,7 @@ def filter_globals_according_to_preference( METADATA_FILTERS = [ ( - r"(?<=\")(\w+ )?(\w+ version )[\d.]+(?: \([^)]+\))?", + r"(?<=\")(\w+ )?(\w+ version )[\d.]+(?:[^\" ]*)(?: \([^)]+\))?", r"{{.*}}\2{{.*}}", ), # preface with glob also, to capture optional CLANG_VENDOR (r'(!DIFile\(filename: ".+", directory: )".+"', r"\1{{.*}}"), diff --git a/llvm/utils/git/github-automation.py b/llvm/utils/git/github-automation.py index 3f24132ae8e3..c5fcf7523101 100755 --- a/llvm/utils/git/github-automation.py +++ b/llvm/utils/git/github-automation.py @@ -207,6 +207,39 @@ Author: {self.pr.user.name} ({self.pr.user.login}) return None +class PRGreeter: + def __init__(self, token: str, repo: str, pr_number: int): + repo = github.Github(token).get_repo(repo) + self.pr = repo.get_issue(pr_number).as_pull_request() + + def run(self) -> bool: + # We assume that this is only called for a PR that has just been opened + # by a user new to LLVM and/or GitHub itself. + + # This text is using Markdown formatting. + comment = f"""\ +Thank you for submitting a Pull Request (PR) to the LLVM Project! + +This PR will be automatically labeled and the relevant teams will be +notified. + +If you wish to, you can add reviewers by using the "Reviewers" section on this page. + +If this is not working for you, it is probably because you do not have write +permissions for the repository. In which case you can instead tag reviewers by +name in a comment by using `@` followed by their GitHub username. + +If you have received no comments on your PR for a week, you can request a review +by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate +is once a week. Please remember that you are asking for valuable time from other developers. + +If you have further questions, they may be answered by the [LLVM GitHub User Guide](https://llvm.org/docs/GitHub.html). + +You can also ask questions in a comment on this PR, on the [LLVM Discord](https://discord.com/invite/xS7Z362) or on the [forums](https://discourse.llvm.org/).""" + self.pr.as_issue().create_comment(comment) + return True + + def setup_llvmbot_git(git_dir="."): """ Configure the git repo in `git_dir` with the llvmbot account so @@ -651,6 +684,9 @@ pr_subscriber_parser = subparsers.add_parser("pr-subscriber") pr_subscriber_parser.add_argument("--label-name", type=str, required=True) pr_subscriber_parser.add_argument("--issue-number", type=int, required=True) +pr_greeter_parser = subparsers.add_parser("pr-greeter") +pr_greeter_parser.add_argument("--issue-number", type=int, required=True) + release_workflow_parser = subparsers.add_parser("release-workflow") release_workflow_parser.add_argument( "--llvm-project-dir", @@ -701,6 +737,9 @@ elif args.command == "pr-subscriber": args.token, args.repo, args.issue_number, args.label_name ) pr_subscriber.run() +elif args.command == "pr-greeter": + pr_greeter = PRGreeter(args.token, args.repo, args.issue_number) + pr_greeter.run() elif args.command == "release-workflow": release_workflow = ReleaseWorkflow( args.token, diff --git a/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/modernize/BUILD.gn b/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/modernize/BUILD.gn index 81134133ebbf..551c790e3c4d 100644 --- a/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/modernize/BUILD.gn +++ b/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/modernize/BUILD.gn @@ -48,6 +48,7 @@ static_library("modernize") { "UseNullptrCheck.cpp", "UseOverrideCheck.cpp", "UseStartsEndsWithCheck.cpp", + "UseStdNumbersCheck.cpp", "UseStdPrintCheck.cpp", "UseTrailingReturnTypeCheck.cpp", "UseTransparentFunctorsCheck.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn index 9766541771cf..6939cbfb5e0c 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn @@ -44,6 +44,7 @@ static_library("Analysis") { "DependenceAnalysis.cpp", "DependenceGraphBuilder.cpp", "DevelopmentModeInlineAdvisor.cpp", + "DomConditionCache.cpp", "DomPrinter.cpp", "DomTreeUpdater.cpp", "DominanceFrontier.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn index 7881905228a4..2e5b7e03bd65 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn @@ -74,6 +74,7 @@ static_library("LLVMBPFCodeGen") { "BPFMIPeephole.cpp", "BPFMISimplifyPatchable.cpp", "BPFPreserveDIType.cpp", + "BPFPreserveStaticOffset.cpp", "BPFRegisterInfo.cpp", "BPFSelectionDAGInfo.cpp", "BPFSubtarget.cpp", diff --git a/llvm/utils/gn/secondary/llvm/test/BUILD.gn b/llvm/utils/gn/secondary/llvm/test/BUILD.gn index dd9fd0c10d53..ab4fd8e6403e 100644 --- a/llvm/utils/gn/secondary/llvm/test/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/test/BUILD.gn @@ -65,6 +65,7 @@ write_lit_config("lit_site_cfg") { "LLVM_HAVE_OPT_VIEWER_MODULES=0", "LLVM_HOST_TRIPLE=$llvm_current_triple", "LLVM_INCLUDE_DXIL_TESTS=0", + "LLVM_INCLUDE_SPIRV_TOOLS_TESTS=0", "LLVM_LIBS_DIR=" + rebase_path("$root_out_dir/lib", dir), "LLVM_LINK_LLVM_DYLIB=0", "LLVM_LIT_TOOLS_DIR=", # Intentionally empty, matches cmake build. diff --git a/mlir/benchmark/python/common.py b/mlir/benchmark/python/common.py index b2dfc134b7c9..0b924172c8da 100644 --- a/mlir/benchmark/python/common.py +++ b/mlir/benchmark/python/common.py @@ -13,10 +13,9 @@ def setup_passes(mlir_module): """Setup pass pipeline parameters for benchmark functions.""" opt = ( "parallelization-strategy=none" - " vectorization-strategy=none vl=1 enable-simd-index32=False" ) - pipeline = f"sparsifier{{{opt}}}" - PassManager.parse(pipeline).run(mlir_module) + pipeline = f"builtin.module(sparsifier{{{opt}}})" + PassManager.parse(pipeline).run(mlir_module.operation) def create_sparse_np_tensor(dimensions, number_of_elements): @@ -73,7 +72,7 @@ def emit_benchmark_wrapped_main_func(kernel_func, timer_func): create a "time measuring" variant of a function. """ i64_type = ir.IntegerType.get_signless(64) - memref_of_i64_type = ir.MemRefType.get([-1], i64_type) + memref_of_i64_type = ir.MemRefType.get([ir.ShapedType.get_dynamic_size()], i64_type) wrapped_func = func.FuncOp( # Same signature and an extra buffer of indices to save timings. "main", @@ -86,7 +85,7 @@ def emit_benchmark_wrapped_main_func(kernel_func, timer_func): with ir.InsertionPoint(wrapped_func.add_entry_block()): timer_buffer = wrapped_func.arguments[-1] zero = arith.ConstantOp.create_index(0) - n_iterations = memref.DimOp(ir.IndexType.get(), timer_buffer, zero) + n_iterations = memref.DimOp(timer_buffer, zero) one = arith.ConstantOp.create_index(1) iter_args = list(wrapped_func.arguments[-num_results - 1 : -1]) loop = scf.ForOp(zero, n_iterations, one, iter_args) diff --git a/mlir/docs/Dialects/ArmSME.md b/mlir/docs/Dialects/ArmSME.md index 505b52938eac..7326150bcd11 100644 --- a/mlir/docs/Dialects/ArmSME.md +++ b/mlir/docs/Dialects/ArmSME.md @@ -1,13 +1,29 @@ # 'ArmSME' Dialect -[TOC] +Basic dialect to target Arm SME. + +This dialect defines custom and LLVM IR intrinsic operations that are used to +target Arm Scalable Matrix Extension. Through the available conversion and +ArmSME passes you can, for example, lower a +[linalg.matmul](https://mlir.llvm.org/docs/Dialects/Linalg/#linalgmatmul-linalgmatmulop) +opereation to Arm SME +[FMOPA](https://developer.arm.com/documentation/ddi0602/2023-03/SME-Instructions/FMOPA--widening---Half-precision-floating-point-sum-of-outer-products-and-accumulate-) +(floating-point outer product) operations. See one of the in-tree end-to-end +integration tests for reference: + +* [Linalg/CPU/ArmSME/matmul.mlir](https://github.com/llvm/llvm-project/blob/main/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir) +* [Vector/CPU/ArmSME/test-outerproduct-f64.mlir](https://github.com/llvm/llvm-project/blob/main/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f64.mlir) -Basic dialect to target Arm SME architectures This dialect contains the -definitions necessary to target Arm SME scalable matrix operations. +These tests are run "post-commit" by the +[clang-aarch64-sve-vla](https://lab.llvm.org/buildbot/#/builders/197) LLVM +BuildBot worker. -## References -* https://developer.arm.com/documentation/ddi0616 -* https://developer.arm.com/documentation/ddi0602/2023-03/SME-Instructions +**References:** + +* [The Scalable Matrix Extension (SME), for Armv9-A](https://developer.arm.com/documentation/ddi0616) +* [A64 -- SME Instructions (alphabetic order)](https://developer.arm.com/documentation/ddi0602/2023-03/SME-Instructions) + +[TOC] ## Operations diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td index 38cce99679e9..02e0b7980c10 100644 --- a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td +++ b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td @@ -1368,7 +1368,8 @@ def Arith_CmpIOp // CmpFOp //===----------------------------------------------------------------------===// -def Arith_CmpFOp : Arith_CompareOp<"cmpf"> { +def Arith_CmpFOp : Arith_CompareOp<"cmpf", + [DeclareOpInterfaceMethods]> { let summary = "floating-point comparison operation"; let description = [{ The `cmpf` operation compares its two operands according to the float @@ -1398,14 +1399,27 @@ def Arith_CmpFOp : Arith_CompareOp<"cmpf"> { let arguments = (ins Arith_CmpFPredicateAttr:$predicate, FloatLike:$lhs, - FloatLike:$rhs); + FloatLike:$rhs, + DefaultValuedAttr< + Arith_FastMathAttr, "::mlir::arith::FastMathFlags::none">:$fastmath); let extraClassDeclaration = [{ static arith::CmpFPredicate getPredicateByName(StringRef name); }]; + let builders = [ + OpBuilder<(ins "::mlir::arith::CmpFPredicateAttr":$predicate, + "Value":$lhs, "Value":$rhs), [{ + build($_builder, $_state, predicate, lhs, rhs, + mlir::arith::FastMathFlagsAttr::get($_builder.getContext(), + mlir::arith::FastMathFlags::none)); + }]> + ]; + let hasFolder = 1; let hasCanonicalizer = 1; + let assemblyFormat = [{ $predicate `,` $lhs `,` $rhs (`fastmath` `` $fastmath^)? + attr-dict `:` type($lhs)}]; } //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td index 5a65293a113c..6975b18ab7f8 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td @@ -48,6 +48,15 @@ def LinkageAttr : LLVM_Attr<"Linkage", "linkage"> { let assemblyFormat = "`<` $linkage `>`"; } +//===----------------------------------------------------------------------===// +// FramePointerKindAttr +//===----------------------------------------------------------------------===// + +def FramePointerKindAttr : LLVM_Attr<"FramePointerKind", "framePointerKind"> { + let parameters = (ins "framePointerKind::FramePointerKind":$framePointerKind); + let assemblyFormat = "`<` $framePointerKind `>`"; +} + //===----------------------------------------------------------------------===// // Loop Attributes //===----------------------------------------------------------------------===// @@ -924,4 +933,68 @@ def LLVM_VScaleRangeAttr : LLVM_Attr<"VScaleRange", "vscale_range"> { "IntegerAttr":$maxRange); let assemblyFormat = "`<` struct(params) `>`"; } + +//===----------------------------------------------------------------------===// +// TargetFeaturesAttr +//===----------------------------------------------------------------------===// + +def LLVM_TargetFeaturesAttr : LLVM_Attr<"TargetFeatures", "target_features"> +{ + let summary = "LLVM target features attribute"; + + let description = [{ + Represents the LLVM target features as a list that can be checked within + passes/rewrites. + + Example: + ```mlir + #llvm.target_features<["+sme", "+sve", "+sme-f64f64"]> + ``` + + Then within a pass or rewrite the features active at an op can be queried: + + ```c++ + auto targetFeatures = LLVM::TargetFeaturesAttr::featuresAt(op); + + if (!targetFeatures.contains("+sme-f64f64")) + return failure(); + ``` + }]; + + let parameters = (ins OptionalArrayRefParameter<"StringAttr">:$features); + + let builders = [ + TypeBuilder<(ins "::llvm::StringRef":$features)>, + TypeBuilder<(ins "::llvm::ArrayRef<::llvm::StringRef>":$features)> + ]; + + let extraClassDeclaration = [{ + /// Checks if a feature is contained within the features list. + /// Note: Using a StringAttr allows doing pointer-comparisons. + bool contains(::mlir::StringAttr feature) const; + bool contains(::llvm::StringRef feature) const; + + bool nullOrEmpty() const { + // Checks if this attribute is null, or the features are empty. + return !bool(*this) || getFeatures().empty(); + } + + /// Returns the list of features as an LLVM-compatible string. + std::string getFeaturesString() const; + + /// Finds the target features on the parent FunctionOpInterface. + /// Note: This assumes the attribute name matches the return value of + /// `getAttributeName()`. + static TargetFeaturesAttr featuresAt(Operation* op); + + /// Canonical name for this attribute within MLIR. + static constexpr StringLiteral getAttributeName() { + return StringLiteral("target_features"); + } + }]; + + let assemblyFormat = "`<` `[` (`]`) : ($features^ `]`)? `>`"; + let genVerifyDecl = 1; +} + #endif // LLVMIR_ATTRDEFS diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td index f05230526c21..3b5984498cf8 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td @@ -587,7 +587,6 @@ def Linkage : DialectAttr< "::mlir::LLVM::LinkageAttr::get($_builder.getContext(), $0)"; } - //===----------------------------------------------------------------------===// // Comdat //===----------------------------------------------------------------------===// @@ -664,4 +663,23 @@ def ModRefInfoEnum : LLVM_EnumAttr< let cppNamespace = "::mlir::LLVM"; } +//===----------------------------------------------------------------------===// +// FramePointerKind +//===----------------------------------------------------------------------===// + +def FramePointerKindNone + : LLVM_EnumAttrCase<"None", "none", "None", 0>; +def FramePointerKindNonLeaf + : LLVM_EnumAttrCase<"NonLeaf", "non-leaf", "NonLeaf", 1>; +def FramePointerKindAll + : LLVM_EnumAttrCase<"All", "all", "All", 2>; + +def FramePointerKindEnum : LLVM_EnumAttr< + "FramePointerKind", + "::llvm::FramePointerKind", + "LLVM FramePointerKind", + [FramePointerKindNone, FramePointerKindNonLeaf, FramePointerKindAll]> { + let cppNamespace = "::mlir::LLVM::framePointerKind"; +} + #endif // LLVMIR_ENUMS diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td index 8f166f0cc7cf..92460fa06f53 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td @@ -1393,7 +1393,9 @@ def LLVM_LLVMFuncOp : LLVM_Op<"func", [ OptionalAttr:$section, OptionalAttr:$unnamed_addr, OptionalAttr:$alignment, - OptionalAttr:$vscale_range + OptionalAttr:$vscale_range, + OptionalAttr:$frame_pointer, + OptionalAttr:$target_features ); let regions = (region AnyRegion:$body); diff --git a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td index 6670d94f842e..57986f291de7 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td @@ -471,6 +471,22 @@ def NVVM_SetMaxRegisterOp : NVVM_PTXBuilder_Op<"setmaxregister"> { let hasVerifier = 1; } +def NVVM_FenceMbarrierInitOp : NVVM_PTXBuilder_Op<"fence.mbarrier.init"> { + let arguments = (ins ); + let description = [{ + Fence operation that applies on the prior nvvm.mbarrier.init + [For more information, see PTX ISA] + (https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar) + }]; + + let assemblyFormat = "attr-dict"; + let extraClassDefinition = [{ + std::string $cppClass::getPtx() { + return std::string("fence.mbarrier_init.release.cluster;"); + } + }]; +} + def ShflKindBfly : I32EnumAttrCase<"bfly", 0>; def ShflKindUp : I32EnumAttrCase<"up", 1>; def ShflKindDown : I32EnumAttrCase<"down", 2>; diff --git a/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td b/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td index 002926ff965f..de65f3176c46 100644 --- a/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td +++ b/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td @@ -2038,6 +2038,7 @@ def VectorizeChildrenAndApplyPatternsOp : let arguments = (ins TransformHandleTypeInterface:$target, UnitAttr:$vectorize_padding, UnitAttr:$vectorize_nd_extract, + UnitAttr:$flatten_1d_depthwise_conv, UnitAttr:$disable_multi_reduction_to_contract_patterns, UnitAttr:$disable_transfer_permutation_map_lowering_patterns); let results = (outs TransformHandleTypeInterface:$transformed); @@ -2049,7 +2050,8 @@ def VectorizeChildrenAndApplyPatternsOp : let builders = [ OpBuilder<(ins "Value":$target, CArg<"bool", "false">:$vectorizePadding, - CArg<"bool", "false">:$vectorizeNDExtract)>, + CArg<"bool", "false">:$vectorizeNDExtract, + CArg<"bool", "false">:$flatten1DDepthwise)> ]; let extraClassDeclaration = [{ ::mlir::DiagnosedSilenceableFailure applyToOne( diff --git a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h index 6c4e16bd94f4..3f4dfe42b71f 100644 --- a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h +++ b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h @@ -753,7 +753,8 @@ LogicalResult deallocateGPUPrivateMemory(OpBuilder &, Value /*buffer*/); LogicalResult vectorize(RewriterBase &rewriter, Operation *op, ArrayRef inputVectorSizes = {}, ArrayRef inputScalableVecDims = {}, - bool vectorizeNDExtract = false); + bool vectorizeNDExtract = false, + bool flatten1DDepthwiseConv = false); /// Emit a suitable vector form for a Copy op with fully static shape. LogicalResult vectorizeCopy(RewriterBase &builder, memref::CopyOp copyOp); diff --git a/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td b/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td index 3c9f45366fa2..08a0398e74b0 100644 --- a/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td +++ b/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td @@ -566,7 +566,6 @@ def Shape_ShapeOfOp : Shape_Op<"shape_of", let assemblyFormat = "$arg attr-dict `:` type($arg) `->` type($result)"; let hasCanonicalizer = 1; - let hasFolder = 1; let hasVerifier = 1; } diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h b/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h index 9af42f00f91e..ac91bfa5ae62 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h +++ b/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h @@ -531,11 +531,11 @@ static_assert((isUniqueLT(LevelType::Dense) && constexpr uint64_t encodeDim(uint64_t i, uint64_t cf, uint64_t cm) { if (cf != 0) { assert(cf <= 0xfffff && cm == 0 && i <= 0xfffff); - return (0x01L << 60) | (cf << 20) | i; + return (0x01ULL << 60) | (cf << 20) | i; } if (cm != 0) { assert(cm <= 0xfffff && i <= 0xfffff); - return (0x02L << 60) | (cm << 20) | i; + return (0x02ULL << 60) | (cm << 20) | i; } assert(i <= 0x0fffffffffffffffu); return i; @@ -543,7 +543,7 @@ constexpr uint64_t encodeDim(uint64_t i, uint64_t cf, uint64_t cm) { constexpr uint64_t encodeLvl(uint64_t i, uint64_t c, uint64_t ii) { if (c != 0) { assert(c <= 0xfffff && ii <= 0xfffff && i <= 0xfffff); - return (0x03L << 60) | (c << 20) | (ii << 40) | i; + return (0x03ULL << 60) | (c << 20) | (ii << 40) | i; } assert(i <= 0x0fffffffffffffffu); return i; diff --git a/mlir/include/mlir/Dialect/Transform/IR/TransformInterfaces.h b/mlir/include/mlir/Dialect/Transform/IR/TransformInterfaces.h index 2fdc15db9ad8..23871cc16d87 100644 --- a/mlir/include/mlir/Dialect/Transform/IR/TransformInterfaces.h +++ b/mlir/include/mlir/Dialect/Transform/IR/TransformInterfaces.h @@ -310,10 +310,8 @@ public: /// with the type of the handle value. LogicalResult mapBlockArguments(BlockArgument argument, ArrayRef operations) { -#if LLVM_ENABLE_ABI_BREAKING_CHECKS - assert(argument.getParentRegion() == regionStack.back() && + assert(argument.getParentRegion() == regionStack.back()->region && "mapping block arguments from a region other than the active one"); -#endif // LLVM_ENABLE_ABI_BREAKING_CHECKS return setPayloadOps(argument, operations); } LogicalResult mapBlockArgument(BlockArgument argument, @@ -350,9 +348,7 @@ public: std::make_pair(®ion, std::make_unique())); assert(res.second && "the region scope is already present"); (void)res; -#if LLVM_ENABLE_ABI_BREAKING_CHECKS - state.regionStack.push_back(®ion); -#endif // LLVM_ENABLE_ABI_BREAKING_CHECKS + state.regionStack.push_back(this); } /// Back-reference to the transform state. @@ -361,7 +357,10 @@ public: /// The region this scope is associated with. Region *region; - friend RegionScope TransformState::make_region_scope(Region &); + /// The transform op within this region that is currently being applied. + TransformOpInterface currentTransform; + + friend class transform::TransformState; }; friend class RegionScope; @@ -784,12 +783,14 @@ private: /// location. InvalidatedHandleMap invalidatedHandles; -#if LLVM_ENABLE_ABI_BREAKING_CHECKS /// A stack of nested regions that are being processed in the transform IR. /// Each region must be an ancestor of the following regions in this list. /// These are also the keys for "mappings". - SmallVector regionStack; -#endif // LLVM_ENABLE_ABI_BREAKING_CHECKS + SmallVector regionStack; + + /// The top-level region scope. The first (bottom) element of `regionStack` + /// is the top-level region scope object. + std::unique_ptr topLevelRegionScope; }; /// Local mapping between values defined by a specific op implementing the @@ -926,8 +927,14 @@ TransformState::RegionScope TransformState::make_region_scope(Region ®ion) { class TrackingListener : public RewriterBase::Listener, public TransformState::Extension { public: + /// A function that returns "true" for handles that do not have to be updated. + using SkipHandleFn = std::function; + /// Create a new TrackingListener for usage in the specified transform op. - TrackingListener(TransformState &state, TransformOpInterface op); + /// Optionally, a function can be specified to identify handles that should + /// do not have to be updated. + TrackingListener(TransformState &state, TransformOpInterface op, + SkipHandleFn skipHandleFn = nullptr); protected: /// Return a replacement payload op for the given op, which is going to be @@ -1015,6 +1022,10 @@ private: /// The handles that are consumed by the transform op. DenseSet consumedHandles; + + /// Handles for which this function evaluates to "true" do not have to be + /// updated. These are typically dead or consumed handles. + SkipHandleFn skipHandleFn; }; /// A specialized listener that keeps track of cases in which no replacement diff --git a/mlir/include/mlir/Dialect/Utils/StaticValueUtils.h b/mlir/include/mlir/Dialect/Utils/StaticValueUtils.h index 502ab93ddbfa..1dc0398494dc 100644 --- a/mlir/include/mlir/Dialect/Utils/StaticValueUtils.h +++ b/mlir/include/mlir/Dialect/Utils/StaticValueUtils.h @@ -139,12 +139,36 @@ SmallVector getValuesSortedByKey(ArrayRef keys, ArrayRef values, llvm::function_ref compare); +/// Helper function to check whether the passed in `sizes` or `offsets` are +/// valid. This can be used to re-check whether dimensions are still valid +/// after constant folding the dynamic dimensions. +bool hasValidSizesOffsets(SmallVector sizesOrOffsets); + +/// Helper function to check whether the passed in `strides` are valid. This +/// can be used to re-check whether dimensions are still valid after constant +/// folding the dynamic dimensions. +bool hasValidStrides(SmallVector strides); + /// Returns "success" when any of the elements in `ofrs` is a constant value. In /// that case the value is replaced by an attribute. Returns "failure" when no -/// folding happened. If `onlyNonNegative` is set, only non-negative constant -/// values are folded. +/// folding happened. If `onlyNonNegative` and `onlyNonZero` are set, only +/// non-negative and non-zero constant values are folded respectively. LogicalResult foldDynamicIndexList(SmallVectorImpl &ofrs, - bool onlyNonNegative = false); + bool onlyNonNegative = false, + bool onlyNonZero = false); + +/// Returns "success" when any of the elements in `offsetsOrSizes` is a +/// constant value. In that case the value is replaced by an attribute. Returns +/// "failure" when no folding happened. Invalid values are not folded to avoid +/// canonicalization crashes. +LogicalResult +foldDynamicOffsetSizeList(SmallVectorImpl &offsetsOrSizes); + +/// Returns "success" when any of the elements in `strides` is a constant +/// value. In that case the value is replaced by an attribute. Returns +/// "failure" when no folding happened. Invalid values are not folded to avoid +/// canonicalization crashes. +LogicalResult foldDynamicStrideList(SmallVectorImpl &strides); /// Return the number of iterations for a loop with a lower bound `lb`, upper /// bound `ub` and step `step`. diff --git a/mlir/include/mlir/Target/LLVMIR/Dialect/All.h b/mlir/include/mlir/Target/LLVMIR/Dialect/All.h index 0563b9bf3d47..5dfc15afb759 100644 --- a/mlir/include/mlir/Target/LLVMIR/Dialect/All.h +++ b/mlir/include/mlir/Target/LLVMIR/Dialect/All.h @@ -26,6 +26,7 @@ #include "mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h" #include "mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h" #include "mlir/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.h" +#include "mlir/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.h" #include "mlir/Target/LLVMIR/Dialect/X86Vector/X86VectorToLLVMIRTranslation.h" namespace mlir { @@ -45,6 +46,7 @@ static inline void registerAllToLLVMIRTranslations(DialectRegistry ®istry) { registerOpenACCDialectTranslation(registry); registerOpenMPDialectTranslation(registry); registerROCDLDialectTranslation(registry); + registerSPIRVDialectTranslation(registry); registerX86VectorDialectTranslation(registry); // Extension required for translating GPU offloading Ops. @@ -61,6 +63,7 @@ registerAllGPUToLLVMIRTranslations(DialectRegistry ®istry) { registerLLVMDialectTranslation(registry); registerNVVMDialectTranslation(registry); registerROCDLDialectTranslation(registry); + registerSPIRVDialectTranslation(registry); // Extension required for translating GPU offloading Ops. gpu::registerOffloadingLLVMTranslationInterfaceExternalModels(registry); diff --git a/mlir/include/mlir/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.h b/mlir/include/mlir/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.h new file mode 100644 index 000000000000..2b066a528deb --- /dev/null +++ b/mlir/include/mlir/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.h @@ -0,0 +1,31 @@ +//===- SPIRVToLLVMIRTranslation.h - SPIR-V to LLVM IR -----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This provides registration calls for SPIR-V dialect to LLVM IR translation. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_TARGET_LLVMIR_DIALECT_SPIRV_SPIRVTOLLVMIRTRANSLATION_H +#define MLIR_TARGET_LLVMIR_DIALECT_SPIRV_SPIRVTOLLVMIRTRANSLATION_H + +namespace mlir { + +class DialectRegistry; +class MLIRContext; + +/// Register the SPIR-V dialect and the translation from it to the LLVM IR in +/// the given registry; +void registerSPIRVDialectTranslation(DialectRegistry ®istry); + +/// Register the SPIR-V dialect and the translation from it in the registry +/// associated with the given context. +void registerSPIRVDialectTranslation(MLIRContext &context); + +} // namespace mlir + +#endif // MLIR_TARGET_LLVMIR_DIALECT_SPIRV_SPIRVTOLLVMIRTRANSLATION_H diff --git a/mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp b/mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp index 337f2dbcbe4e..5e4213cc4e87 100644 --- a/mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp +++ b/mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp @@ -13,6 +13,7 @@ #include "mlir/Conversion/LLVMCommon/ConversionTarget.h" #include "mlir/Conversion/LLVMCommon/VectorPattern.h" #include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/LLVMIR/LLVMAttrs.h" #include "mlir/Dialect/LLVMIR/LLVMDialect.h" #include "mlir/IR/TypeUtilities.h" #include "mlir/Pass/Pass.h" @@ -394,13 +395,15 @@ CmpFOpLowering::matchAndRewrite(arith::CmpFOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const { Type operandType = adaptor.getLhs().getType(); Type resultType = op.getResult().getType(); + LLVM::FastmathFlags fmf = + arith::convertArithFastMathFlagsToLLVM(op.getFastmath()); // Handle the scalar and 1D vector cases. if (!isa(operandType)) { rewriter.replaceOpWithNewOp( op, typeConverter->convertType(resultType), convertCmpPredicate(op.getPredicate()), - adaptor.getLhs(), adaptor.getRhs()); + adaptor.getLhs(), adaptor.getRhs(), fmf); return success(); } @@ -414,7 +417,7 @@ CmpFOpLowering::matchAndRewrite(arith::CmpFOp op, OpAdaptor adaptor, return rewriter.create( op.getLoc(), llvm1DVectorTy, convertCmpPredicate(op.getPredicate()), - adaptor.getLhs(), adaptor.getRhs()); + adaptor.getLhs(), adaptor.getRhs(), fmf); }, rewriter); } diff --git a/mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp b/mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp index fece03040dbb..c3c9780318a9 100644 --- a/mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp +++ b/mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp @@ -61,16 +61,18 @@ void getMemrefIndices(ValueRange indices, unsigned rank, Value tileSliceIndex, /// AFTER: /// ```mlir /// %ptrue_s = arith.constant dense : vector<[4]xi1> -/// %tile = arm_sme.get_tile : vector<[4]x[4]xi32> +/// %init_tile = arm_sme.get_tile : vector<[4]x[4]xi32> /// %vscale = vector.vscale /// %c0 = arith.constant 0 : index /// %c1 = arith.constant 1 : index /// %min_svl_s = arith.constant 4 : index /// %svl_s = arith.muli %min_svl_s, %vscale : index -/// scf.for %tile_slice_idx = %c0 to %svl_s step %c1 { +/// %tile = scf.for %tile_slice_idx = %c0 to %svl_s step %c1 +/// iter_args(%iter_tile = %init_tile) -> (vector<[4]x[4]xi32>) { /// %tile_update = arm_sme.load_tile_slice %src[%tile_slice_idx], -/// %ptrue_s, %tile, %tile_slice_idx +/// %ptrue_s, %iter_tile, %tile_slice_idx /// : memref, vector<[4]xi1>, vector<[4]x[4]xi32> +/// scf.yield %tile_update : vector<[4]x[4]xi32> /// } /// ``` struct TileLoadOpConversion : public OpRewritePattern { @@ -88,7 +90,7 @@ struct TileLoadOpConversion : public OpRewritePattern { auto tileElementType = tileType.getElementType(); // Allocate a new SME tile. - auto tile = tileLoadOp.createOpAndForwardTileId( + auto initTile = tileLoadOp.createOpAndForwardTileId( rewriter, loc, tileType); // Create a loop that loads each ZA tile slice from memory. @@ -103,8 +105,8 @@ struct TileLoadOpConversion : public OpRewritePattern { // ..., SVL_Q). auto numTileSlices = rewriter.create(loc, minTileSlices, vscale); - auto forOp = - rewriter.create(loc, lowerBound, numTileSlices, step); + auto forOp = rewriter.create(loc, lowerBound, numTileSlices, + step, ValueRange{initTile}); rewriter.setInsertionPointToStart(forOp.getBody()); @@ -121,14 +123,17 @@ struct TileLoadOpConversion : public OpRewritePattern { getMemrefIndices(tileLoadOp.getIndices(), tileLoadOp.getMemRefType().getRank(), tileSliceIndex, numTileSlices, memrefIndices, loc, rewriter); - tileLoadOp.createOpAndForwardTileId( - rewriter, loc, tileType, tileLoadOp.getBase(), allTruePredicate, tile, - memrefIndices, tileSliceIndex, tileLoadOp.getLayout()); + auto currentTile = forOp.getRegionIterArg(0); + auto loadSlice = + tileLoadOp.createOpAndForwardTileId( + rewriter, loc, tileType, tileLoadOp.getBase(), allTruePredicate, + currentTile, memrefIndices, tileSliceIndex, tileLoadOp.getLayout()); + rewriter.create(loc, loadSlice.getResult()); rewriter.setInsertionPointAfter(forOp); - // Replace 'arm_sme.tile_load' with the tile. - rewriter.replaceOp(tileLoadOp, tile); + // Replace 'arm_sme.tile_load' with the result. + rewriter.replaceOp(tileLoadOp, forOp.getResult(0)); return success(); } @@ -150,13 +155,15 @@ struct TileLoadOpConversion : public OpRewritePattern { /// ```mlir /// %c0 = arith.constant 0 : index /// %c1 = arith.constant 1 : index -/// %tile = arm_sme.zero : vector<[4]x[4]xi32> +/// %init_tile = arm_sme.zero : vector<[4]x[4]xi32> /// %num_rows = arith.constant 2 : index /// %num_cols = vector.create_mask %c4 : vector<[4]xi1> -/// scf.for %tile_slice_idx = %c0 to %num_rows step %c1 { +/// %tile = scf.for %tile_slice_idx = %c0 to %num_rows step %c1 +/// iter_args(%iter_tile = %init_tile) -> (vector<[4]x[4]xi32>) { /// %tile_update = arm_sme.load_tile_slice -/// %src[%tile_slice_idx], %num_cols, %tile, %tile_slice_idx : +/// %src[%tile_slice_idx], %num_cols, %iter_tile, %tile_slice_idx : /// memref, vector<[1]xi32>, vector<[4]x[4]xi32> +/// scf.yield %tile_update : vector<[4]x[4]xi32> /// } /// ``` /// @@ -202,14 +209,15 @@ struct TileLoadOpWithMaskAndPadZeroConversion // Initialize tile with zero to satisfy padding. Inactive cols will be // zeroed anyway since the loads use zeroing predication. For inactive rows // however, no load will occur so these need to be zeroed. - auto tile = tileLoadOp.createOpAndForwardTileId( + auto initTile = tileLoadOp.createOpAndForwardTileId( rewriter, loc, tileType); // Create a loop to load the active tile slices from memory. auto step = rewriter.create(loc, 1); auto lowerBound = rewriter.create(loc, 0); auto upperBound = numRows; - auto forOp = rewriter.create(loc, lowerBound, upperBound, step); + auto forOp = rewriter.create(loc, lowerBound, upperBound, step, + ValueRange{initTile}); rewriter.setInsertionPointToStart(forOp.getBody()); @@ -217,17 +225,20 @@ struct TileLoadOpWithMaskAndPadZeroConversion // tile. SmallVector memrefIndices; auto tileSliceIndex = forOp.getInductionVar(); + auto currentTile = forOp.getRegionIterArg(0); getMemrefIndices(tileLoadOp.getIndices(), tileLoadOp.getMemRefType().getRank(), tileSliceIndex, upperBound, memrefIndices, loc, rewriter); - tileLoadOp.createOpAndForwardTileId( - rewriter, loc, tileType, tileLoadOp.getBase(), numColsOp, tile, - memrefIndices, tileSliceIndex, tileLoadOp.getLayout()); + auto loadSlice = + tileLoadOp.createOpAndForwardTileId( + rewriter, loc, tileType, tileLoadOp.getBase(), numColsOp, + currentTile, memrefIndices, tileSliceIndex, tileLoadOp.getLayout()); + rewriter.create(loc, loadSlice.getResult()); rewriter.setInsertionPointAfter(forOp); - // Replace 'arm_sme.tile_load' with the tile. - rewriter.replaceOp(tileLoadOp, tile); + // Replace 'arm_sme.tile_load' with the result. + rewriter.replaceOp(tileLoadOp, forOp.getResult(0)); return success(); } @@ -249,15 +260,18 @@ struct TileLoadOpWithMaskAndPadZeroConversion /// ```mlir /// ... /// %pad_1d = arith.constant dense<1> : vector<[4]xi32> -/// scf.for %tile_slice_idx = %c0 to %svl_s step %c1 { +/// %tile = scf.for %tile_slice_idx = %c0 to %svl_s step %c1 +/// iter_args(%iter_tile = %init_tile) -> (vector<[4]x[4]xi32>) { /// ... /// %mask_1d = vector.create_mask : vector<[4]xi1> /// %slice = vector.maskedload %base[%tile_slice_idx, %c0], %mask_1d, %pad_1d /// : memref, vector<[4]xi1>, /// vector<[4]xi32> into vector<[4]xi32> /// // Insert slice into tile -/// arm_sme.move_vector_to_tile_slice %slice, %tile, %tile_slice_idx -/// : vector<[4]xi32> into vector<[4]x[4]xi32> +/// %tile_update = arm_sme.move_vector_to_tile_slice +/// %slice, %iter_tile, %tile_slice_idx : +/// vector<[4]xi32> into vector<[4]x[4]xi32> +/// scf.yield %tile_update : vector<[4]x[4]xi32> /// } /// ``` struct TileLoadOpWithMaskAndPadNonZeroConversion @@ -298,7 +312,7 @@ struct TileLoadOpWithMaskAndPadNonZeroConversion loc, rewriter.getI32Type(), numCols); // Allocate a new SME tile. - auto tile = tileLoadOp.createOpAndForwardTileId( + auto initTile = tileLoadOp.createOpAndForwardTileId( rewriter, loc, tileType); // Create a loop that loads each ZA tile slice from memory. @@ -310,12 +324,13 @@ struct TileLoadOpWithMaskAndPadNonZeroConversion auto lowerBound = rewriter.create(loc, 0); auto numTileSlices = rewriter.create(loc, minTileSlices, vscale); - auto forOp = - rewriter.create(loc, lowerBound, numTileSlices, step); + auto forOp = rewriter.create(loc, lowerBound, numTileSlices, + step, ValueRange{initTile}); rewriter.setInsertionPointToStart(forOp.getBody()); auto tileSliceIndex = forOp.getInductionVar(); + auto currentTile = forOp.getRegionIterArg(0); // Combine masks. auto rowIsActive = rewriter.create( @@ -344,14 +359,16 @@ struct TileLoadOpWithMaskAndPadNonZeroConversion /*passthru=*/pad1DOp); // Create 'arm_sme.move_vector_to_tile_slice' to move slice into tile. - tileLoadOp.createOpAndForwardTileId( - rewriter, loc, tileType, loadSlice->getResult(0), tile, tileSliceIndex, - tileLoadOp.getLayout()); + auto moveSlice = + tileLoadOp.createOpAndForwardTileId( + rewriter, loc, tileType, loadSlice->getResult(0), currentTile, + tileSliceIndex, tileLoadOp.getLayout()); + rewriter.create(loc, moveSlice.getResult()); rewriter.setInsertionPointAfter(forOp); - // Replace 'arm_sme.tile_load' with the tile. - rewriter.replaceOp(tileLoadOp, tile); + // Replace 'arm_sme.tile_load' with the result. + rewriter.replaceOp(tileLoadOp, forOp.getResult(0)); return success(); } diff --git a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp index 4855fd187eb5..0e978ca0a642 100644 --- a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp +++ b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp @@ -21,6 +21,7 @@ #include "mlir/Conversion/LLVMCommon/LoweringOptions.h" #include "mlir/Conversion/LLVMCommon/TypeConverter.h" #include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h" +#include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" #include "mlir/Dialect/ControlFlow/IR/ControlFlow.h" #include "mlir/Dialect/Func/IR/FuncOps.h" #include "mlir/Dialect/GPU/IR/GPUDialect.h" @@ -282,6 +283,7 @@ struct LowerGpuOpsToNVVMOpsPass populateFinalizeMemRefToLLVMConversionPatterns(converter, llvmPatterns); populateGpuToNVVMConversionPatterns(converter, llvmPatterns); populateGpuWMMAToNVVMConversionPatterns(converter, llvmPatterns); + populateVectorToLLVMConversionPatterns(converter, llvmPatterns); if (this->hasRedux) populateGpuSubgroupReduceOpLoweringPattern(converter, llvmPatterns); LLVMConversionTarget target(getContext()); diff --git a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp index d9f94e30b04c..599bb13190f1 100644 --- a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp +++ b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp @@ -363,6 +363,8 @@ void mlir::populateGpuToROCDLConversionPatterns( // Use address space = 4 to match the OpenCL definition of printf() patterns.add(converter, /*addressSpace=*/4); } + // TODO: Add alignment for workgroup memory + patterns.add(converter); patterns.add(converter); diff --git a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp index ca37bd2b6643..beed71d93d9b 100644 --- a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp +++ b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp @@ -1502,6 +1502,9 @@ public: auto resultTy = cast(op.getType()); auto resultETy = resultTy.getElementType(); + bool floatingPointMode = resultETy.isF16() || resultETy.isF32(); + auto floatTy = resultETy.isF16() ? b.getF16Type() : b.getF32Type(); + auto imageH = inputTy.getShape()[1]; auto imageW = inputTy.getShape()[2]; @@ -1535,16 +1538,13 @@ public: Value zeroI32 = b.create(b.getZeroAttr(b.getI32Type())); - Value zeroFp32 = - b.create(b.getZeroAttr(b.getF32Type())); + Value zeroFp = b.create(b.getZeroAttr(floatTy)); Value hMax = b.create(b.getI32IntegerAttr(imageH - 1)); Value wMax = b.create(b.getI32IntegerAttr(imageW - 1)); Value inY = b.create(b.getI32Type(), y); Value inX = b.create(b.getI32Type(), x); - bool floatingPointMode = resultETy.isF32(); - ArrayRef offset = op.getOffset(); ArrayRef border = op.getBorder(); ArrayRef scale = op.getScale(); @@ -1567,16 +1567,16 @@ public: int size, ImplicitLocOpBuilder &b) { if (size == 1) { index = zeroI32; - delta = zeroFp32; + delta = zeroFp; return; } // x = x * scale_d + offset; // ix = floor(x / scale_n) // dx = x / scale_n - ix - Value val = b.create(b.getF32Type(), in); - scaleN = b.create(b.getF32Type(), scaleN); - scaleD = b.create(b.getF32Type(), scaleD); - offset = b.create(b.getF32Type(), offset); + Value val = b.create(floatTy, in); + scaleN = b.create(floatTy, scaleN); + scaleD = b.create(floatTy, scaleD); + offset = b.create(floatTy, offset); val = b.create(val, scaleD); val = b.create(val, offset); val = b.create(val, scaleN); @@ -1625,7 +1625,7 @@ public: Value pred; if (floatingPointMode) { - auto h = b.create(b.getF32FloatAttr(0.5f)); + auto h = b.create(b.getFloatAttr(floatTy, 0.5f)); pred = b.create(arith::CmpFPredicate::OGE, dval, h); } else { Value dvalDouble = b.create(dval, one); @@ -1681,7 +1681,8 @@ public: input, ValueRange{batch, y1, x1, channel}); if (floatingPointMode) { - auto oneVal = b.create(b.getF32FloatAttr(1.0f)); + auto oneVal = + b.create(b.getFloatAttr(floatTy, 1.0f)); auto interpolate = [&](Value val0, Value val1, Value delta, int inputSize, ImplicitLocOpBuilder &b) -> Value { diff --git a/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp b/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp index 4b3fd26c6d59..312e89c8f100 100644 --- a/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp +++ b/mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp @@ -26,21 +26,26 @@ static bool isSplatZero(Type elemType, DenseElementsAttr val) { } /// Generates a for loop over ZA tile slices where the induction variable is -/// the tile slice index. Sets the IR Builder insertion point as the loop body. -/// Callers of this method are responsible for restoring it if needed. -static scf::ForOp getLoopOverTileSlices(PatternRewriter &rewriter, Location loc, - Type eltType) { +/// the tile slice index and each iteration yields a new tile. Loop body is +/// built via the callback, which returns the next tile value. +template +static scf::ForOp createLoopOverTileSlices(PatternRewriter &rewriter, + Location loc, Value initTile, + LoopBodyCallback callback) { + OpBuilder::InsertionGuard g(rewriter); auto step = rewriter.create(loc, 1); auto minTileSlices = rewriter.create( - loc, arm_sme::getSMETileSliceMinNumElts(eltType)); + loc, llvm::cast(initTile.getType()).getDimSize(0)); auto vscale = rewriter.create(loc, rewriter.getIndexType()); auto lowerBound = rewriter.create(loc, 0); auto numTileSlices = rewriter.create(loc, minTileSlices, vscale); - auto forOp = - rewriter.create(loc, lowerBound, numTileSlices, step); + auto forOp = rewriter.create(loc, lowerBound, numTileSlices, step, + ValueRange{initTile}); rewriter.setInsertionPointToStart(forOp.getBody()); + auto nextTile = callback(forOp); + rewriter.create(loc, nextTile.getResult()); return forOp; } @@ -242,27 +247,27 @@ struct ConstantOpToArmSMELowering : public OpRewritePattern { // Lower non-zero constants to a loop of 'arm_sme.move_vector_to_tile_slice' // ops that broadcast the constant to each tile slice. - OpBuilder::InsertionGuard g(rewriter); auto loc = constantOp.getLoc(); - // Unpack 1-d vector type from 2-d vector type. - auto tileSliceType = - VectorType::get(tileType.getShape().drop_front(), tileElementType, - /*scalableDims=*/{true}); + // To fill a tile with a constant, we create a 1-D splat of the constant, + // then move that into each tile slice (the largest unit we can set at once, + // outside of operations like the outerproduct). + VectorType tileSliceType = VectorType::Builder(tileType).dropDim(0); auto denseAttr1D = DenseElementsAttr::get( tileSliceType, denseAttr.getSplatValue()); auto constantOp1D = rewriter.create(loc, denseAttr1D); - auto tile = rewriter.create(loc, tileType); - - auto forOp = getLoopOverTileSlices(rewriter, loc, tileElementType); - auto tileSliceIndex = forOp.getInductionVar(); - - // Create 'arm_sme.move_vector_to_tile_slice' to write vector to tile slice. - rewriter.create( - loc, tileType, constantOp1D, tile, tileSliceIndex); - - rewriter.replaceOp(constantOp, tile); + auto initTile = rewriter.create(loc, tileType); + auto forOp = + createLoopOverTileSlices(rewriter, loc, initTile, [&](auto forOp) { + auto tileSliceIndex = forOp.getInductionVar(); + auto currentTile = forOp.getRegionIterArg(0); + // Create 'arm_sme.move_vector_to_tile_slice' to write vector to tile + // slice. + return rewriter.create( + loc, tileType, constantOp1D, currentTile, tileSliceIndex); + }); + rewriter.replaceOp(constantOp, forOp.getResult(0)); return success(); } @@ -277,9 +282,13 @@ struct ConstantOpToArmSMELowering : public OpRewritePattern { /// is converted to: /// /// %broadcast_to_1d = vector.broadcast %src : i32 to vector<[4]xi32> -/// scf.for %tile_slice_index = %c0 to %num_tile_slices step %c1 { -/// arm_sme.move_vector_to_tile_slice %broadcast_to_1d, %tile, -/// %tile_slice_index : vector<[4]xi32> into vector<[4]x[4]xi32> +/// %broadcast_to_tile = scf.for %tile_slice_index = %c0 to %num_tile_slices +/// step %c1 iter_args(%iter_tile = %init_tile) -> (vector<[4]x[4]xi32>) +/// { +/// %tile_update = arm_sme.move_vector_to_tile_slice +/// %broadcast_to_1d, %iter_tile, %tile_slice_index : +/// vector<[4]xi32> into vector<[4]x[4]xi32> +/// scf.yield %tile_update : vector<[4]x[4]xi32> /// } /// /// Supports scalar, 0-d vector, and 1-d vector broadcasts. @@ -293,20 +302,16 @@ struct BroadcastOpToArmSMELowering if (!tileType || !arm_sme::isValidSMETileVectorType(tileType)) return failure(); - OpBuilder::InsertionGuard g(rewriter); auto loc = broadcastOp.getLoc(); auto srcType = broadcastOp.getSourceType(); auto srcVectorType = dyn_cast(srcType); - auto tileElementType = tileType.getElementType(); Value broadcastOp1D; if (srcType.isIntOrFloat() || (srcVectorType && (srcVectorType.getRank() == 0))) { // Broadcast scalar or 0-d vector to 1-d vector. - auto tileSliceType = - VectorType::get(tileType.getShape().drop_front(), tileElementType, - /*scalableDims=*/{true}); + VectorType tileSliceType = VectorType::Builder(tileType).dropDim(0); broadcastOp1D = rewriter.create( loc, tileSliceType, broadcastOp.getSource()); } else if (srcVectorType && (srcVectorType.getRank() == 1)) @@ -315,18 +320,20 @@ struct BroadcastOpToArmSMELowering else return failure(); - auto tile = rewriter.create(loc, tileType); + auto initTile = rewriter.create(loc, tileType); // Create a loop over ZA tile slices. - auto forOp = getLoopOverTileSlices(rewriter, loc, tileElementType); - auto tileSliceIndex = forOp.getInductionVar(); - - // Create 'arm_sme.move_vector_to_tile_slice' to broadcast the value to each - // tile slice. - rewriter.create( - loc, tileType, broadcastOp1D, tile, tileSliceIndex); - - rewriter.replaceOp(broadcastOp, tile); + auto forOp = + createLoopOverTileSlices(rewriter, loc, initTile, [&](auto forOp) { + auto tileSliceIndex = forOp.getInductionVar(); + auto currentTile = forOp.getRegionIterArg(0); + // Create 'arm_sme.move_vector_to_tile_slice' to broadcast the value + // to each tile slice. + return rewriter.create( + loc, tileType, broadcastOp1D, currentTile, tileSliceIndex); + }); + + rewriter.replaceOp(broadcastOp, forOp.getResult(0)); return success(); } @@ -341,9 +348,13 @@ struct BroadcastOpToArmSMELowering /// is converted to: /// /// %broadcast_to_1d = vector.broadcast %src : i32 to vector<[4]xi32> -/// scf.for %tile_slice_index = %c0 to %num_tile_slices step %c1 { -/// arm_sme.move_vector_to_tile_slice %broadcast_to_1d, %tile, -/// %tile_slice_index : vector<[4]xi32> into vector<[4]x[4]xi32> +/// %broadcast_to_tile = scf.for %tile_slice_index = %c0 to %num_tile_slices +/// step %c1 iter_args(%iter_tile = %init_tile) -> (vector<[4]x[4]xi32>) +/// { +/// %tile_update = arm_sme.move_vector_to_tile_slice +/// %broadcast_to_1d, %iter_tile, %tile_slice_index : +/// vector<[4]xi32> into vector<[4]x[4]xi32> +/// scf.yield %tile_update : vector<[4]x[4]xi32> /// } /// /// This is identical to vector.broadcast of a scalar. @@ -356,11 +367,8 @@ struct SplatOpToArmSMELowering : public OpRewritePattern { if (!tileType || !arm_sme::isValidSMETileVectorType(tileType)) return failure(); - OpBuilder::InsertionGuard g(rewriter); auto loc = splatOp.getLoc(); - auto srcType = splatOp.getOperand().getType(); - auto tileElementType = tileType.getElementType(); assert(srcType.isIntOrFloat() && "Invalid source type for vector.splat"); // Avoid unused-variable warning when building without assertions. @@ -371,17 +379,19 @@ struct SplatOpToArmSMELowering : public OpRewritePattern { Value broadcastOp1D = rewriter.create( loc, tileSliceType, splatOp.getInput()); - auto tile = rewriter.create(loc, tileType); + auto initTile = rewriter.create(loc, tileType); // Next, create a loop over ZA tile slices and "move" the generated 1-d // vector to each slice. - auto forOp = getLoopOverTileSlices(rewriter, loc, tileElementType); - auto tileSliceIndex = forOp.getInductionVar(); - - rewriter.create( - loc, tileType, broadcastOp1D, tile, tileSliceIndex); + auto forOp = + createLoopOverTileSlices(rewriter, loc, initTile, [&](auto forOp) { + auto tileSliceIndex = forOp.getInductionVar(); + auto currentTile = forOp.getRegionIterArg(0); + return rewriter.create( + loc, tileType, broadcastOp1D, currentTile, tileSliceIndex); + }); - rewriter.replaceOp(splatOp, tile); + rewriter.replaceOp(splatOp, forOp.getResult(0)); return success(); } @@ -424,7 +434,6 @@ struct TransposeOpToArmSMELowering if (permutation[0] != 1 || permutation[1] != 0) return failure(); - OpBuilder::InsertionGuard g(rewriter); auto loc = transposeOp.getLoc(); // Allocate buffer to store input tile to. diff --git a/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp b/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp index 33a77d7576ba..2ee314e9fedf 100644 --- a/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp +++ b/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp @@ -726,12 +726,14 @@ struct DecomposePrintOpConversion : public VectorToSCFPattern { auto targetVectorType = vectorType.cloneWith({}, legalIntTy); value = rewriter.create(loc, signlessSourceVectorType, value); - if (width == 1 || intTy.isUnsigned()) - value = rewriter.create(loc, signlessTargetVectorType, - value); - else - value = rewriter.create(loc, signlessTargetVectorType, - value); + if (value.getType() != signlessTargetVectorType) { + if (width == 1 || intTy.isUnsigned()) + value = rewriter.create(loc, signlessTargetVectorType, + value); + else + value = rewriter.create(loc, signlessTargetVectorType, + value); + } value = rewriter.create(loc, targetVectorType, value); vectorType = targetVectorType; } diff --git a/mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp b/mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp index ec5feab1ed0d..ca0d2f407c2d 100644 --- a/mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp +++ b/mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp @@ -507,8 +507,10 @@ struct SimplifyClones : public OpRewritePattern { return failure(); } - rewriter.replaceOpWithNewOp(cloneOp, cloneOp.getType(), - source); + if (source.getType() != cloneOp.getType()) + source = rewriter.create(cloneOp.getLoc(), + cloneOp.getType(), source); + rewriter.replaceOp(cloneOp, source); rewriter.eraseOp(redundantDealloc); return success(); } diff --git a/mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp b/mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp index 7bbdeab3ea1a..42653517249d 100644 --- a/mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp +++ b/mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp @@ -314,44 +314,51 @@ struct SplitDeallocWhenNotAliasingAnyOther LogicalResult matchAndRewrite(DeallocOp deallocOp, PatternRewriter &rewriter) const override { + Location loc = deallocOp.getLoc(); if (deallocOp.getMemrefs().size() <= 1) return failure(); - SmallVector newMemrefs, newConditions, replacements; - DenseSet exceptedUsers; - replacements = deallocOp.getUpdatedConditions(); + SmallVector remainingMemrefs, remainingConditions; + SmallVector> updatedConditions; for (auto [memref, cond] : llvm::zip(deallocOp.getMemrefs(), deallocOp.getConditions())) { + // Check if `memref` can split off into a separate bufferization.dealloc. if (potentiallyAliasesMemref(aliasAnalysis, deallocOp.getMemrefs(), memref, true)) { - newMemrefs.push_back(memref); - newConditions.push_back(cond); + // `memref` alias with other memrefs, do not split off. + remainingMemrefs.push_back(memref); + remainingConditions.push_back(cond); continue; } - auto newDeallocOp = rewriter.create( - deallocOp.getLoc(), memref, cond, deallocOp.getRetained()); - replacements = SmallVector(llvm::map_range( - llvm::zip(replacements, newDeallocOp.getUpdatedConditions()), - [&](auto replAndNew) -> Value { - auto orOp = rewriter.create(deallocOp.getLoc(), - std::get<0>(replAndNew), - std::get<1>(replAndNew)); - exceptedUsers.insert(orOp); - return orOp.getResult(); - })); + // Create new bufferization.dealloc op for `memref`. + auto newDeallocOp = rewriter.create(loc, memref, cond, + deallocOp.getRetained()); + updatedConditions.push_back( + llvm::to_vector(ValueRange(newDeallocOp.getUpdatedConditions()))); } - if (newMemrefs.size() == deallocOp.getMemrefs().size()) + // Fail if no memref was split off. + if (remainingMemrefs.size() == deallocOp.getMemrefs().size()) return failure(); - rewriter.replaceUsesWithIf(deallocOp.getUpdatedConditions(), replacements, - [&](OpOperand &operand) { - return !exceptedUsers.contains( - operand.getOwner()); - }); - return updateDeallocIfChanged(deallocOp, newMemrefs, newConditions, - rewriter); + // Create bufferization.dealloc op for all remaining memrefs. + auto newDeallocOp = rewriter.create( + loc, remainingMemrefs, remainingConditions, deallocOp.getRetained()); + + // Bit-or all conditions. + SmallVector replacements = + llvm::to_vector(ValueRange(newDeallocOp.getUpdatedConditions())); + for (auto additionalConditions : updatedConditions) { + assert(replacements.size() == additionalConditions.size() && + "expected same number of updated conditions"); + for (int64_t i = 0, e = replacements.size(); i < e; ++i) { + replacements[i] = rewriter.create( + loc, replacements[i], additionalConditions[i]); + } + } + rewriter.replaceOp(deallocOp, replacements); + return success(); } private: diff --git a/mlir/lib/Dialect/Complex/IR/ComplexOps.cpp b/mlir/lib/Dialect/Complex/IR/ComplexOps.cpp index 8fd914dd107f..6d8706775758 100644 --- a/mlir/lib/Dialect/Complex/IR/ComplexOps.cpp +++ b/mlir/lib/Dialect/Complex/IR/ComplexOps.cpp @@ -100,7 +100,8 @@ LogicalResult BitcastOp::verify() { } if (isa(operandType) == isa(resultType)) { - return emitOpError("requires input or output is a complex type"); + return emitOpError( + "requires that either input or output has a complex type"); } if (isa(resultType)) @@ -125,8 +126,15 @@ struct MergeComplexBitcast final : OpRewritePattern { LogicalResult matchAndRewrite(BitcastOp op, PatternRewriter &rewriter) const override { if (auto defining = op.getOperand().getDefiningOp()) { - rewriter.replaceOpWithNewOp(op, op.getType(), - defining.getOperand()); + if (isa(op.getType()) || + isa(defining.getOperand().getType())) { + // complex.bitcast requires that input or output is complex. + rewriter.replaceOpWithNewOp(op, op.getType(), + defining.getOperand()); + } else { + rewriter.replaceOpWithNewOp(op, op.getType(), + defining.getOperand()); + } return success(); } @@ -155,24 +163,9 @@ struct MergeArithBitcast final : OpRewritePattern { } }; -struct ArithBitcast final : OpRewritePattern { - using OpRewritePattern::OpRewritePattern; - - LogicalResult matchAndRewrite(BitcastOp op, - PatternRewriter &rewriter) const override { - if (isa(op.getType()) || - isa(op.getOperand().getType())) - return failure(); - - rewriter.replaceOpWithNewOp(op, op.getType(), - op.getOperand()); - return success(); - } -}; - void BitcastOp::getCanonicalizationPatterns(RewritePatternSet &results, MLIRContext *context) { - results.add(context); + results.add(context); } //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp index e2342670508c..645a45dd96be 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp @@ -14,6 +14,7 @@ #include "mlir/Dialect/LLVMIR/LLVMDialect.h" #include "mlir/IR/Builders.h" #include "mlir/IR/DialectImplementation.h" +#include "mlir/Interfaces/FunctionInterfaces.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/TypeSwitch.h" #include "llvm/BinaryFormat/Dwarf.h" @@ -183,3 +184,67 @@ void printExpressionArg(AsmPrinter &printer, uint64_t opcode, i++; }); } + +//===----------------------------------------------------------------------===// +// TargetFeaturesAttr +//===----------------------------------------------------------------------===// + +TargetFeaturesAttr TargetFeaturesAttr::get(MLIRContext *context, + llvm::ArrayRef features) { + return Base::get(context, + llvm::map_to_vector(features, [&](StringRef feature) { + return StringAttr::get(context, feature); + })); +} + +TargetFeaturesAttr TargetFeaturesAttr::get(MLIRContext *context, + StringRef targetFeatures) { + SmallVector features; + targetFeatures.split(features, ',', /*MaxSplit=*/-1, + /*KeepEmpty=*/false); + return get(context, features); +} + +LogicalResult +TargetFeaturesAttr::verify(function_ref emitError, + llvm::ArrayRef features) { + for (StringAttr featureAttr : features) { + if (!featureAttr || featureAttr.empty()) + return emitError() << "target features can not be null or empty"; + auto feature = featureAttr.strref(); + if (feature[0] != '+' && feature[0] != '-') + return emitError() << "target features must start with '+' or '-'"; + if (feature.contains(',')) + return emitError() << "target features can not contain ','"; + } + return success(); +} + +bool TargetFeaturesAttr::contains(StringAttr feature) const { + if (nullOrEmpty()) + return false; + // Note: Using StringAttr does pointer comparisons. + return llvm::is_contained(getFeatures(), feature); +} + +bool TargetFeaturesAttr::contains(StringRef feature) const { + if (nullOrEmpty()) + return false; + return llvm::is_contained(getFeatures(), feature); +} + +std::string TargetFeaturesAttr::getFeaturesString() const { + std::string featuresString; + llvm::raw_string_ostream ss(featuresString); + llvm::interleave( + getFeatures(), ss, [&](auto &feature) { ss << feature.strref(); }, ","); + return ss.str(); +} + +TargetFeaturesAttr TargetFeaturesAttr::featuresAt(Operation *op) { + auto parentFunction = op->getParentOfType(); + if (!parentFunction) + return {}; + return parentFunction.getOperation()->getAttrOfType( + getAttributeName()); +} diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp index 28445945f07d..c67bba04d697 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp @@ -1219,8 +1219,7 @@ ParseResult CallOp::parse(OpAsmParser &parser, OperationState &result) { return failure(); // Parse the function arguments. - if (parser.parseOperandList(operands, OpAsmParser::Delimiter::Paren) || - parser.parseOptionalAttrDict(result.attributes)) + if (parser.parseOperandList(operands, OpAsmParser::Delimiter::Paren)) return failure(); bool isVarArg = parser.parseOptionalKeyword("vararg").succeeded(); @@ -1232,6 +1231,9 @@ ParseResult CallOp::parse(OpAsmParser &parser, OperationState &result) { return failure(); } + if (parser.parseOptionalAttrDict(result.attributes)) + return failure(); + // Parse the trailing type list and resolve the operands. return parseCallTypeAndResolveOperands(parser, result, isDirect, operands); } @@ -2544,6 +2546,10 @@ LogicalResult LLVM::ConstantOp::verify() { if (!llvm::isa(getValue())) return emitOpError() << "only supports integer, float, string or elements attributes"; + if (auto intAttr = dyn_cast(getValue())) { + if (!llvm::isa(getType())) + return emitOpError() << "expected integer type"; + } if (auto floatAttr = dyn_cast(getValue())) { const llvm::fltSemantics &sem = floatAttr.getValue().getSemantics(); unsigned floatWidth = APFloat::getSizeInBits(sem); @@ -2558,6 +2564,12 @@ LogicalResult LLVM::ConstantOp::verify() { return emitOpError() << "expected integer type of width " << floatWidth; } } + if (auto splatAttr = dyn_cast(getValue())) { + if (!getType().isa() && !getType().isa() && + !getType().isa() && + !getType().isa()) + return emitOpError() << "expected vector or array type"; + } return success(); } diff --git a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp index 14404d837ff7..e3713457e841 100644 --- a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp +++ b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp @@ -2658,26 +2658,23 @@ SmallVector transform::TileUsingForOp::getMixedSizes() { // `array` prefix to be consistent in the IR with `parseDynamicIndexList`. ParseResult parseOptionalInterchange(OpAsmParser &parser, OperationState &result) { - if (succeeded(parser.parseOptionalLBrace())) { - if (failed(parser.parseKeyword("interchange"))) - return parser.emitError(parser.getNameLoc()) << "expect `interchange`"; - if (failed(parser.parseEqual())) - return parser.emitError(parser.getNameLoc()) << "expect `=`"; - result.addAttribute("interchange", - DenseI64ArrayAttr::parse(parser, Type{})); - if (failed(parser.parseRBrace())) - return parser.emitError(parser.getNameLoc()) << "expect `}`"; - } + if (failed(parser.parseOptionalKeyword("interchange"))) + return success(); + if (failed(parser.parseEqual())) + return failure(); + result.addAttribute( + transform::TileUsingForOp::getInterchangeAttrName(result.name), + DenseI64ArrayAttr::parse(parser, Type{})); return success(); } void printOptionalInterchange(OpAsmPrinter &p, ArrayRef interchangeVals) { if (!interchangeVals.empty()) { - p << " {interchange = ["; + p << " interchange = ["; llvm::interleaveComma(interchangeVals, p, [&](int64_t integer) { p << integer; }); - p << "]}"; + p << "]"; } } @@ -2693,6 +2690,7 @@ ParseResult transform::TileUsingForOp::parse(OpAsmParser &parser, if (parser.parseOperand(target) || parser.getCurrentLocation(&operandLoc) || parseDynamicIndexList(parser, dynamicSizes, staticSizes, scalableVals) || parseOptionalInterchange(parser, result) || + parser.parseOptionalAttrDict(result.attributes) || parser.parseColonType(functionalType)) return ParseResult::failure(); @@ -2727,6 +2725,11 @@ void TileUsingForOp::print(OpAsmPrinter &p) { /*valueTypes=*/{}, getScalableSizesAttr(), OpAsmParser::Delimiter::Square); printOptionalInterchange(p, getInterchange()); + p.printOptionalAttrDict( + (*this)->getAttrs(), + /*elidedAttrs=*/{getInterchangeAttrName(getOperation()->getName()), + getScalableSizesAttrName(getOperation()->getName()), + getStaticSizesAttrName(getOperation()->getName())}); p << " : "; p.printFunctionalType(getOperands().getTypes(), getResults().getTypes()); } @@ -2943,7 +2946,7 @@ LogicalResult TileUsingForallOp::verify() { void transform::VectorizeChildrenAndApplyPatternsOp::build( OpBuilder &builder, OperationState &result, Value target, - bool vectorizePadding, bool vectorizeExtract) { + bool vectorizePadding, bool vectorizeExtract, bool flatten1DDepthwiseConv) { result.addOperands(target); if (vectorizePadding) { result.addAttribute( @@ -2957,6 +2960,12 @@ void transform::VectorizeChildrenAndApplyPatternsOp::build( result.name), builder.getUnitAttr()); } + if (flatten1DDepthwiseConv) { + result.addAttribute( + VectorizeChildrenAndApplyPatternsOp::getFlatten_1dDepthwiseConvAttrName( + result.name), + builder.getUnitAttr()); + } result.addTypes(transform::AnyOpType::get(builder.getContext())); } @@ -2965,22 +2974,29 @@ namespace { /// VectorizeChildrenAndApplyPatternsOp::applyToOne. struct VectorizationPattern : public RewritePattern { explicit VectorizationPattern(MLIRContext *context, - bool vectorizeExtract = false) + bool vectorizeExtract = false, + bool flattenConv = false) : RewritePattern(MatchAnyOpTypeTag(), /*benefit=*/1, context), - vectorizeNDExtract(vectorizeExtract) {} + vectorizeNDExtract(vectorizeExtract), + flatten1DDepthwiseConv(flattenConv) {} LogicalResult matchAndRewrite(Operation *op, PatternRewriter &rewriter) const override { LinalgOp linalgOp = dyn_cast(op); if (!linalgOp) return rewriter.notifyMatchFailure(op, "expected Linalg Op"); return vectorize(rewriter, linalgOp, /*inputVectorSizes=*/{}, - /*scalableVecDims=*/{}, vectorizeNDExtract); + /*scalableVecDims=*/{}, vectorizeNDExtract, + flatten1DDepthwiseConv); } private: /// Controls whether to vectorize `tensor.extract` when the input tensor is /// rank >= 2. bool vectorizeNDExtract = false; + /// Controls whether to "flatten" the channel dimension when vectorising 1D + /// depthwise convolutions. This should lead to bette vectorization for + /// tensors with a low number of channel dimensions. + bool flatten1DDepthwiseConv = false; }; } // namespace @@ -2997,7 +3013,8 @@ transform::VectorizeChildrenAndApplyPatternsOp::applyToOne( MLIRContext *ctx = getContext(); RewritePatternSet patterns(ctx); - patterns.add(ctx, getVectorizeNdExtract()); + patterns.add(ctx, getVectorizeNdExtract(), + getFlatten_1dDepthwiseConv()); if (!getDisableTransferPermutationMapLoweringPatterns()) vector::populateVectorTransferPermutationMapLoweringPatterns(patterns); diff --git a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp index f9a53a8451a6..c21d007c931b 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp @@ -44,8 +44,9 @@ using namespace mlir::linalg; #define LDBG(X) LLVM_DEBUG(DBGS() << X << "\n") /// Try to vectorize `convOp` as a convolution. -static FailureOr vectorizeConvolution(RewriterBase &rewriter, - LinalgOp convOp); +static FailureOr +vectorizeConvolution(RewriterBase &rewriter, LinalgOp convOp, + bool flatten1DDepthwiseConv = false); /// Return the unique instance of OpType in `block` if it is indeed unique. /// Return null if none or more than 1 instances exist. @@ -1664,7 +1665,8 @@ static void convertAffineApply(RewriterBase &rewriter, LinalgOp linalgOp) { LogicalResult mlir::linalg::vectorize(RewriterBase &rewriter, Operation *op, ArrayRef inputVectorSizes, ArrayRef inputScalableVecDims, - bool vectorizeNDExtract) { + bool vectorizeNDExtract, + bool flatten1DDepthwiseConv) { LDBG("Attempting to vectorize:\n" << *op << "\n"); LDBG("Input vector sizes: "); LLVM_DEBUG(llvm::interleaveComma(inputVectorSizes, llvm::dbgs())); @@ -1696,8 +1698,8 @@ LogicalResult mlir::linalg::vectorize(RewriterBase &rewriter, Operation *op, // TODO: isaConvolutionOpInterface that can also infer from generic // features. Will require stride/dilation attributes inference. if (isa(linalgOp.getOperation())) { - FailureOr convOr = - vectorizeConvolution(rewriter, linalgOp); + FailureOr convOr = vectorizeConvolution( + rewriter, linalgOp, flatten1DDepthwiseConv); if (succeeded(convOr)) { llvm::append_range(results, (*convOr)->getResults()); return success(); @@ -2822,7 +2824,7 @@ struct Conv1DGenerator /// kw is always unrolled. /// TODO: w (resp. kw) is unrolled when the strideW ( resp. dilationW) is /// > 1. - FailureOr depthwiseConv() { + FailureOr depthwiseConv(bool flatten) { if (!valid) return rewriter.notifyMatchFailure(op, "unvectorizable depthwise conv"); @@ -2869,6 +2871,9 @@ struct Conv1DGenerator //===------------------------------------------------------------------===// // Unroll along kw and read slices of lhs and rhs. SmallVector lhsVals, rhsVals, resVals; + auto inOutSliceSizes = SmallVector{nSize, wSizeStep, cSize}; + auto inOutStrides = SmallVector{1, 1, 1}; + // Extract lhs slice of size {n, wSizeStep, c} // @ [0, sw * w + dw * kw, 0]. for (int64_t kw = 0; kw < kwSize; ++kw) { @@ -2876,8 +2881,7 @@ struct Conv1DGenerator lhsVals.push_back(rewriter.create( loc, lhs, /*offsets=*/ArrayRef{0, w * strideW + kw * dilationW, 0}, - /*sizes=*/ArrayRef{nSize, wSizeStep, cSize}, - /*strides=*/ArrayRef{1, 1, 1})); + inOutSliceSizes, inOutStrides)); } } // Extract rhs slice of size {c} @ [kw]. @@ -2889,21 +2893,39 @@ struct Conv1DGenerator for (int64_t w = 0; w < wSize; w += wSizeStep) { resVals.push_back(rewriter.create( loc, res, - /*offsets=*/ArrayRef{0, w, 0}, - /*sizes=*/ArrayRef{nSize, wSizeStep, cSize}, - /*strides=*/ArrayRef{1, 1, 1})); + /*offsets=*/ArrayRef{0, w, 0}, inOutSliceSizes, + inOutStrides)); } auto linearIndex = [&](int64_t kw, int64_t w) { return kw * (wSize / wSizeStep) + w; }; + auto inOutFlattenSliceSizes = + SmallVector{nSize, wSizeStep * cSize}; + auto lhsCastType = VectorType::get(inOutFlattenSliceSizes, lhsEltType); + auto resCastType = VectorType::get(inOutFlattenSliceSizes, resEltType); // Compute contraction: O{n, w, c} += I{n, sw * w + dw * kw, c} * F{c} for (int64_t kw = 0; kw < kwSize; ++kw) { for (int64_t w = 0; w < wSize; w += wSizeStep) { - resVals[w] = depthwiseConv1dSliceAsMulAcc(rewriter, loc, - lhsVals[linearIndex(kw, w)], - rhsVals[kw], resVals[w]); + Value lhsVal = lhsVals[linearIndex(kw, w)]; + Value resVal = resVals[w]; + ShapedType filterBCastTy = cast(resVal.getType()); + if (flatten) { + // Flatten the input and filter vectors (collapse the channel + // dimension) + lhsVal = rewriter.create( + loc, lhsCastType, lhsVals[linearIndex(kw, w)]); + resVal = rewriter.create(loc, resCastType, + resVals[w]); + } + resVals[w] = depthwiseConv1dSliceAsMulAcc( + rewriter, loc, lhsVal, rhsVals[kw], resVal, filterBCastTy, flatten); + if (flatten) { + // Un-flatten the output vector (restore the channel dimension) + resVals[w] = rewriter.create( + loc, VectorType::get(inOutSliceSizes, resEltType), resVals[w]); + } } } @@ -2936,9 +2958,13 @@ struct Conv1DGenerator .getOperation(); } - /// Lower lhs{n, w, c} * rhs{c} -> res{n, w, c} to MulAcc + /// Lower: + /// * lhs{n, w, c} * rhs{c} -> res{n, w, c} (flatten = false) + /// * lhs{n, w * c} * rhs{c} -> res{n, w * c} (flatten = true) + /// to MulAcc. Value depthwiseConv1dSliceAsMulAcc(RewriterBase &rewriter, Location loc, - Value lhs, Value rhs, Value res) { + Value lhs, Value rhs, Value res, + ShapedType bcastTy, bool flatten) { auto rhsTy = cast(rhs.getType()); auto resTy = cast(res.getType()); @@ -2946,7 +2972,13 @@ struct Conv1DGenerator lhs = promote(rewriter, loc, lhs, resTy); rhs = rewriter.create( - loc, resTy.clone(rhsTy.getElementType()), rhs); + loc, bcastTy.clone(rhsTy.getElementType()), rhs); + if (flatten) { + // Flatten the channel dimension + rhs = rewriter.create( + loc, resTy.clone(rhsTy.getElementType()), rhs); + } + rhs = promote(rewriter, loc, rhs, resTy); if (!lhs || !rhs) @@ -3049,7 +3081,7 @@ struct Conv1DGenerator /// Entry point that transposes into the common form: /// {{n, strideW * w + dilationW * kw, c}, {kw, c}, {n, w, c}} - FailureOr generateDilatedConv() { + FailureOr generateDilatedConv(bool flatten = false) { AffineExpr n, w, c, kw; bindDims(ctx, n, w, c, kw); if (!iters({Par(), Par(), Par(), Red()})) @@ -3060,7 +3092,7 @@ struct Conv1DGenerator if (layout({/*lhsIndex*/ {n, strideW * w + dilationW * kw, c}, /*rhsIndex*/ {kw, c}, /*resIndex*/ {n, w, c}})) - return depthwiseConv(); + return depthwiseConv(flatten); return rewriter.notifyMatchFailure(op, "not a depthwise::Nwc layout"); } @@ -3125,8 +3157,9 @@ private: /// Helper function to vectorize a LinalgOp with convolution semantics. // TODO: extend the generic vectorization to support windows and drop this. -static FailureOr vectorizeConvolution(RewriterBase &rewriter, - LinalgOp op) { +static FailureOr +vectorizeConvolution(RewriterBase &rewriter, LinalgOp op, + bool flatten1DDepthwiseConv) { // The ConvolutionOpInterface gives us guarantees of existence for // strides/dilations. However, we do not need to rely on those, we can simply // use them if present, otherwise use the default and let the generic conv. @@ -3151,7 +3184,7 @@ static FailureOr vectorizeConvolution(RewriterBase &rewriter, res = e.generateNcwPooling(); if (succeeded(res)) return res; - return e.generateDilatedConv(); + return e.generateDilatedConv(flatten1DDepthwiseConv); } struct VectorizeConvolution : public OpInterfaceRewritePattern { diff --git a/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp b/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp index a397506629cf..93327a28234e 100644 --- a/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp +++ b/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp @@ -2582,17 +2582,12 @@ Type SubViewOp::inferResultType(MemRefType sourceMemRefType, dispatchIndexOpFoldResults(offsets, dynamicOffsets, staticOffsets); dispatchIndexOpFoldResults(sizes, dynamicSizes, staticSizes); dispatchIndexOpFoldResults(strides, dynamicStrides, staticStrides); - - // If one of the offsets or sizes is invalid, fail the canonicalization. - // These checks also occur in the verifier, but they are needed here - // because some dynamic dimensions may have been constant folded. - for (int64_t offset : staticOffsets) - if (offset < 0 && !ShapedType::isDynamic(offset)) - return {}; - for (int64_t size : staticSizes) - if (size < 0 && !ShapedType::isDynamic(size)) - return {}; - + if (!hasValidSizesOffsets(staticOffsets)) + return {}; + if (!hasValidSizesOffsets(staticSizes)) + return {}; + if (!hasValidStrides(staticStrides)) + return {}; return SubViewOp::inferResultType(sourceMemRefType, staticOffsets, staticSizes, staticStrides); } diff --git a/mlir/lib/Dialect/Mesh/IR/CMakeLists.txt b/mlir/lib/Dialect/Mesh/IR/CMakeLists.txt index 700e6e21f36b..634a94f8cec8 100644 --- a/mlir/lib/Dialect/Mesh/IR/CMakeLists.txt +++ b/mlir/lib/Dialect/Mesh/IR/CMakeLists.txt @@ -13,4 +13,5 @@ add_mlir_dialect_library(MLIRMeshDialect MLIRArithDialect MLIRIR MLIRSupport + MLIRViewLikeInterface ) diff --git a/mlir/lib/Dialect/SCF/IR/SCF.cpp b/mlir/lib/Dialect/SCF/IR/SCF.cpp index 3b55704c4ea0..2e7382160f8e 100644 --- a/mlir/lib/Dialect/SCF/IR/SCF.cpp +++ b/mlir/lib/Dialect/SCF/IR/SCF.cpp @@ -3040,6 +3040,8 @@ struct ParallelOpSingleOrZeroIterationDimsFolder auto newOp = rewriter.create(op.getLoc(), newLowerBounds, newUpperBounds, newSteps, op.getInitVals(), nullptr); + // Erase the empty block that was inserted by the builder. + rewriter.eraseBlock(newOp.getBody()); // Clone the loop body and remap the block arguments of the collapsed loops // (inlining does not support a cancellable block argument mapping). rewriter.cloneRegionBefore(op.getRegion(), newOp.getRegion(), diff --git a/mlir/lib/Dialect/Shape/IR/Shape.cpp b/mlir/lib/Dialect/Shape/IR/Shape.cpp index 2444556a4563..4f829db1305c 100644 --- a/mlir/lib/Dialect/Shape/IR/Shape.cpp +++ b/mlir/lib/Dialect/Shape/IR/Shape.cpp @@ -1678,15 +1678,30 @@ LogicalResult shape::MulOp::verify() { return verifySizeOrIndexOp(*this); } // ShapeOfOp //===----------------------------------------------------------------------===// -OpFoldResult ShapeOfOp::fold(FoldAdaptor) { - auto type = llvm::dyn_cast(getOperand().getType()); - if (!type || !type.hasStaticShape()) - return nullptr; - Builder builder(getContext()); - return builder.getIndexTensorAttr(type.getShape()); -} - namespace { +/// Replace shape_of(x) where x has a constant shape with a const_shape op. +struct ShapeOfOpToConstShapeOp : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(shape::ShapeOfOp op, + PatternRewriter &rewriter) const override { + auto type = llvm::dyn_cast(op.getArg().getType()); + if (!type || !type.hasStaticShape()) + return failure(); + Location loc = op.getLoc(); + Value constShape = + rewriter + .create(loc, + rewriter.getIndexTensorAttr(type.getShape())) + .getResult(); + if (constShape.getType() != op.getResult().getType()) + constShape = rewriter.create( + loc, op.getResult().getType(), constShape); + rewriter.replaceOp(op, constShape); + return success(); + } +}; + struct ShapeOfWithTensor : public OpRewritePattern { using OpRewritePattern::OpRewritePattern; @@ -1739,7 +1754,8 @@ struct ShapeOfCastExtentTensor : public OpRewritePattern { void ShapeOfOp::getCanonicalizationPatterns(RewritePatternSet &patterns, MLIRContext *context) { patterns.add(context); + ExtractFromShapeOfExtentTensor, ShapeOfOpToConstShapeOp>( + context); } LogicalResult mlir::shape::ShapeOfOp::inferReturnTypes( diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/CodegenEnv.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/CodegenEnv.cpp index cc05f1d06e30..312aefc0936c 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/CodegenEnv.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/CodegenEnv.cpp @@ -206,9 +206,8 @@ void CodegenEnv::updateInsertionChain(Value chain) { insChain = chain; } -// FIXME: clarify what this "rank" is really supposed to mean/be. -bool CodegenEnv::atExpandLevel(OpOperand *o, unsigned rank, LoopOrd n) const { - return sparseOut == o && outerParNest == static_cast(rank - 1) && +bool CodegenEnv::atExpandLevel(OpOperand *o, unsigned rank, LoopId n) const { + return sparseOut == o && outerParNest == static_cast(rank - 1) && outerParNest == n; } diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/CodegenEnv.h b/mlir/lib/Dialect/SparseTensor/Transforms/CodegenEnv.h index 7e825dde2783..a1947f48393e 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/CodegenEnv.h +++ b/mlir/lib/Dialect/SparseTensor/Transforms/CodegenEnv.h @@ -108,7 +108,7 @@ public: return loopEmitter.unpackTensorLevelRange(std::forward(c)); } - unsigned getLoopDepth() const { return loopEmitter.getCurrentDepth(); } + unsigned getCurrentDepth() const { return loopEmitter.getCurrentDepth(); } // // Code generation environment verify functions. @@ -118,9 +118,7 @@ public: /// It also sets the sparseOut if the output tensor is sparse. bool isAdmissibleTensorExp(ExprId e); - /// Returns the induction-variable for the loop identified by the given - /// `LoopId`. This method handles application of the topological sort - /// in order to convert the `LoopId` into the corresponding `LoopOrd`. + /// Returns the induction-variable for the given loop. Value getLoopVar(LoopId i) const; // @@ -133,8 +131,7 @@ public: Value getInsertionChain() const { return insChain; } void updateInsertionChain(Value chain); - // FIXME: clarify what this "rank" is really supposed to mean/be. - bool atExpandLevel(OpOperand *o, unsigned rank, LoopOrd n) const; + bool atExpandLevel(OpOperand *o, unsigned rank, LoopId n) const; void startExpand(Value values, Value filled, Value added, Value count); bool isExpand() const { return expValues != nullptr; } void updateExpandCount(Value count); @@ -180,7 +177,7 @@ private: // expansion in the innermost loop nest (`expValues` through `expCount`). OpOperand *sparseOut; // The count of outer non-filter loops, as defined by `isAdmissibleTopoOrder`. - LoopOrd outerParNest; + LoopId outerParNest; Value insChain; Value expValues; Value expFilled; diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.h b/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.h index e3e620b92257..0bdd9d45e6ae 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.h +++ b/mlir/lib/Dialect/SparseTensor/Transforms/LoopEmitter.h @@ -19,31 +19,9 @@ namespace mlir { namespace sparse_tensor { -//===----------------------------------------------------------------------===// -/// The position of a loop in the loop-stack, or the position of a -/// `LoopId` in a topologically-sorted list of `LoopId`s. -/// -/// Although this type may have the same cardinality as `LoopId`, it must -/// not be confused with that type. The `LoopId` type is used by the `Merger` -/// as a unique identifier for loop-variables, regardless of the ordering -/// of those loops. Whereas the `LoopOrd` type is used by the `LoopEmitter` -/// (and `CodegenEnv`) to refer to the actual order in which loops are -/// generated. -/// -/// TODO: further explicate the correspondences between these various -/// types. In particular, since the `$dim` argument to `linalg::IndexOp` -/// is a De Bruijn index, it seems like that should correspond to `LoopOrd`, -/// and yet the `Merger` has that correspond with `LoopId` instead. -/// In addition `LoopEmitter::genAffine` has `AffineDimExpr::position` -/// correspond to `LoopId`, however it is unclear what the providence -/// of those `AffineDimExpr` is. -// -// TODO: use a struct/class rather than a typedef, so that we can actually -// typecheck this to avoid mixups in the code. -using LoopOrd = unsigned; - // A compressed pair. using TensorLevel = unsigned; + //===----------------------------------------------------------------------===// // SparseTensorLoopEmiter class, manages sparse tensors and helps to // generate loop structure to (co)-iterate sparse tensors. @@ -108,9 +86,7 @@ public: /// to the position of that tensor `Value` in the array). Setting /// `isSparseOut` indicates that the sparse output tensor is empty, /// so the loop emitter will generate loops over it according to the - /// level-sizes. The `topSort` array specifies the actual order in - /// which loops are generated, thus providing a mapping from `LoopOrd` - /// to `LoopId`. + /// level-sizes. void initialize(ValueRange tensors, StringAttr loopTag = nullptr, bool hasOutput = false, bool isSparseOut = false, unsigned numLoops = 0, DependentLvlGetter getter = nullptr); @@ -193,21 +169,16 @@ public: } /// Fills the out-parameter with the loop induction variables for all - /// loops in the current loop-stack. The variables are given in the - /// same order as the loop-stack, hence `ivs` should be indexed into - /// by `LoopOrd` (not `LoopId`). + /// loops in the current loop-stack. SmallVector getLoopIVs() const { return llvm::to_vector(getLoopIVsRange()); } - /// Gets the current depth of the loop-stack. The result is given - /// the type `LoopOrd` for the same reason as one-past-the-end iterators. - LoopOrd getCurrentDepth() const { - return llvm::range_size(getLoopIVsRange()); - } + /// Gets the current depth of the loop-stack. + LoopId getCurrentDepth() const { return llvm::range_size(getLoopIVsRange()); } - /// Gets loop induction variable for the given `LoopOrd`. - Value getLoopIV(LoopOrd n) const { + /// Gets loop induction variable for the given loop + Value getLoopIV(LoopId n) const { if (n >= getCurrentDepth()) return Value(); auto it = getLoopIVsRange().begin(); diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp index e0d3ce241e45..6c9adf9fa21a 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp @@ -34,6 +34,7 @@ #include "mlir/IR/Matchers.h" #include "mlir/IR/TensorEncoding.h" #include "llvm/ADT/SmallBitVector.h" + #include using namespace mlir; @@ -43,30 +44,23 @@ using namespace mlir::sparse_tensor; // Sparsifier analysis methods. //===----------------------------------------------------------------------===// -// TODO: the "idx"-vs-"ldx" naming convention is not self-explanatory, -// and those letters are too easy to confuse visually. We should switch -// to a more self-explanatory naming convention like "curLoop"-vs-"prevLoop" -// (assuming that's the actual meaning behind the "idx"-vs-"ldx" convention). - -/// Determines if affine expression is invariant. -static bool isInvariantAffine(AffineExpr a, unsigned loopDepth, LoopId ldx, - bool &isAtLoop) { +/// Returns true iff affine expression is invariant. Sets the +/// parameter `isCurrentLoop` when expression just became invariant. +static bool isInvariantAffine(AffineExpr a, LoopId curr, bool &isCurrentLoop) { switch (a.getKind()) { case AffineExprKind::DimId: { const LoopId i = cast(a).getPosition(); - if (i == ldx) { - isAtLoop = true; - // Must be invariant if we are at the given loop. - return true; + if (i + 1 == curr) { + isCurrentLoop = true; + return true; // becomes invariant at current loop } - // The DimExpr is invariant the loop has already been generated. - return i < loopDepth; + return i < curr; // invariant when already generated } case AffineExprKind::Add: case AffineExprKind::Mul: { auto binOp = cast(a); - return isInvariantAffine(binOp.getLHS(), loopDepth, ldx, isAtLoop) && - isInvariantAffine(binOp.getRHS(), loopDepth, ldx, isAtLoop); + return isInvariantAffine(binOp.getLHS(), curr, isCurrentLoop) && + isInvariantAffine(binOp.getRHS(), curr, isCurrentLoop); } default: { assert(isa(a)); @@ -85,7 +79,6 @@ static bool findAffine(Merger &merger, TensorId tid, Level lvl, AffineExpr a, const LoopId idx = merger.makeLoopId(cast(a).getPosition()); if (!isUndefLT(merger.getLvlType(tid, idx))) return false; // used more than once - if (setLvlFormat) merger.setLevelAndType(tid, idx, lvl, lt); return true; @@ -96,9 +89,8 @@ static bool findAffine(Merger &merger, TensorId tid, Level lvl, AffineExpr a, assert(isDenseLT(lt)); if (auto binOp = dyn_cast(a)) { // We do not set dim level format for affine expression like d0 + d1 on - // either loop index at d0 or d1. - // We continue the recursion merely to check whether current affine is - // admissible or not. + // either loop index at d0 or d1. We continue the recursion merely to + // check whether current affine is admissible or not. return findAffine(merger, tid, lvl, binOp.getLHS(), lt, false) && findAffine(merger, tid, lvl, binOp.getRHS(), lt, false); } @@ -133,8 +125,8 @@ static bool findDepIdxSet(Merger &merger, TensorId tensor, Level lvl, if (coefficient <= 0) return false; - const LoopId ldx = merger.makeLoopId(cast(a).getPosition()); - if (!isUndefLT(merger.getLvlType(tensor, ldx))) + const LoopId idx = merger.makeLoopId(cast(a).getPosition()); + if (!isUndefLT(merger.getLvlType(tensor, idx))) return false; // used more than once, e.g., A[i][i] // TODO: Generalizes the following two cases. A[i] (with trivial index @@ -142,14 +134,14 @@ static bool findDepIdxSet(Merger &merger, TensorId tensor, Level lvl, // not necessarily need to differentiate them. if (!isSubExp) { assert(coefficient == 1); - merger.setLevelAndType(tensor, ldx, lvl, lt); + merger.setLevelAndType(tensor, idx, lvl, lt); } if (isSubExp) { // The current loops appears in more than one affine expressions on the // same tensor. We can not handle this case. e.g., A[i+j][i+k], `i` is // used twice. - if (merger.hasDependentLvl(ldx, tensor)) { + if (merger.hasDependentLvl(idx, tensor)) { // TODO: This can be supported by coiterate slices if the loop idx is // appeared on affine index for different tensor, or take slice on // multiple dimensions when it is on the same tensor. @@ -161,7 +153,7 @@ static bool findDepIdxSet(Merger &merger, TensorId tensor, Level lvl, // else increase min(d0_1, d0_2). return false; } - merger.setLoopDependentTensorLevel(ldx, tensor, lvl, lt, coefficient); + merger.setLoopDependentTensorLevel(idx, tensor, lvl, lt, coefficient); } return true; } @@ -195,7 +187,7 @@ static bool findDepIdxSet(Merger &merger, TensorId tensor, Level lvl, } } -/// Get the total number of compound affine expressions in the +/// Gets the total number of compound affine expressions in the /// `getMatchingIndexingMap` for the given tensor. For the following inputs: /// /// map = (d0, d1, d2) => (d0 + d1 : compressed, d2 : compressed) @@ -225,7 +217,7 @@ static unsigned getNumNonTrivialIdxExpOnSparseLvls(AffineMap map, return num; } -/// Get the total number of sparse levels with compound affine +/// Gets the total number of sparse levels with compound affine /// expressions, summed over all operands of the `GenericOp`. static unsigned getNumNonTrivialIdxExpOnSparseLvls(linalg::GenericOp op) { unsigned num = 0; @@ -235,6 +227,7 @@ static unsigned getNumNonTrivialIdxExpOnSparseLvls(linalg::GenericOp op) { return num; } +// Returns true iff output has nontrivial affine indices. static bool hasNonTrivialAffineOnSparseOut(linalg::GenericOp op) { OpOperand *out = op.getDpsInitOperand(0); if (getSparseTensorType(out->get()).isAllDense()) @@ -260,15 +253,13 @@ static bool findSparseAnnotations(CodegenEnv &env, bool idxReducBased) { const auto enc = getSparseTensorEncoding(t.get().getType()); if (enc) annotated = true; - const Level lvlRank = map.getNumResults(); assert(!enc || lvlRank == enc.getLvlRank()); assert(static_cast(env.op().getRank(&t)) == lvlRank); - - // We only need to do index reduction if there is at least one non-trivial - // index expression on sparse levels. - // If all non-trivial index expression is on dense levels, we can - // efficiently rely on the random access to locate the element. + // We only need to do index reduction if there is at least one + // non-trivial index expression on sparse levels. If all non-trivial + // index expression is on dense levels, we can efficiently rely on + // the random access to locate the element. bool needIdxReduc = enc && getNumNonTrivialIdxExpOnSparseLvls(map, t.get()) != 0; // If then current tensor being inspected requires affine index, it need @@ -343,9 +334,6 @@ static void genBuffers(CodegenEnv &env, OpBuilder &builder) { } /// Generates index for load/store on sparse tensor. -// FIXME: It's not entirely clear what "index" means here (i.e., is it -// a "coordinate", or "Ldx", or what). So the function should be renamed -// and/or the documentation expanded in order to clarify. static Value genIndex(CodegenEnv &env, OpOperand *t) { const auto map = env.op().getMatchingIndexingMap(t); const auto stt = getSparseTensorType(t->get()); @@ -422,11 +410,10 @@ static void genInsertionStore(CodegenEnv &env, OpBuilder &builder, OpOperand *t, Location loc = op.getLoc(); // Direct insertion in lexicographic coordinate order. if (!env.isExpand()) { - const LoopOrd numLoops = op.getRank(t); + const LoopId numLoops = op.getRank(t); // Retrieves the first `numLoop` induction variables. - SmallVector ivs = llvm::to_vector( - llvm::drop_end(env.emitter().getLoopIVsRange(), - env.emitter().getCurrentDepth() - numLoops)); + SmallVector ivs = llvm::to_vector(llvm::drop_end( + env.emitter().getLoopIVsRange(), env.getCurrentDepth() - numLoops)); Value chain = env.getInsertionChain(); if (!env.getValidLexInsert()) { env.updateInsertionChain(builder.create(loc, rhs, chain, ivs)); @@ -495,7 +482,6 @@ static Value genTensorLoad(CodegenEnv &env, OpBuilder &builder, ExprId exp) { Value val = env.exp(exp).val; if (val) return val; - // Load during insertion. linalg::GenericOp op = env.op(); OpOperand *t = &op->getOpOperand(env.exp(exp).tensor); @@ -574,7 +560,7 @@ inline static Value genInvariantValue(CodegenEnv &env, ExprId exp) { /// exception of index computations, which need to be relinked to actual /// inlined cloned code. static Value relinkBranch(CodegenEnv &env, RewriterBase &rewriter, Block *block, - Value e, LoopId ldx) { + Value e) { if (auto arg = dyn_cast(e)) { // Direct arguments of the original linalg op must be converted // into dense tensor loads. Note that we should not encounter @@ -598,7 +584,7 @@ static Value relinkBranch(CodegenEnv &env, RewriterBase &rewriter, Block *block, for (unsigned i = 0, n = def->getNumOperands(); i < n; i++) { rewriter.updateRootInPlace(def, [&]() { def->setOperand( - i, relinkBranch(env, rewriter, block, def->getOperand(i), ldx)); + i, relinkBranch(env, rewriter, block, def->getOperand(i))); }); } } @@ -607,8 +593,7 @@ static Value relinkBranch(CodegenEnv &env, RewriterBase &rewriter, Block *block, } /// Recursively generates tensor expression. -static Value genExp(CodegenEnv &env, RewriterBase &rewriter, ExprId e, - LoopId ldx) { +static Value genExp(CodegenEnv &env, RewriterBase &rewriter, ExprId e) { if (e == ::mlir::sparse_tensor::detail::kInvalidId) return Value(); @@ -626,20 +611,20 @@ static Value genExp(CodegenEnv &env, RewriterBase &rewriter, ExprId e, if (kind == TensorExp::Kind::kReduce) env.startCustomReduc(e); // enter custom - Value v0, v1; // If either lhs/rhs is a synthetic zero, we infer the type for the zero value // based on the type of the other operand. + Value v0, v1; if (exp.children.e0 != ::mlir::sparse_tensor::detail::kInvalidId && env.exp(exp.children.e0).kind == TensorExp::Kind::kSynZero) { - v1 = genExp(env, rewriter, exp.children.e1, ldx); + v1 = genExp(env, rewriter, exp.children.e1); v0 = constantZero(rewriter, loc, v1.getType()); } else if (exp.children.e1 != ::mlir::sparse_tensor::detail::kInvalidId && env.exp(exp.children.e1).kind == TensorExp::Kind::kSynZero) { - v0 = genExp(env, rewriter, exp.children.e0, ldx); + v0 = genExp(env, rewriter, exp.children.e0); v1 = constantZero(rewriter, loc, v0.getType()); } else { - v0 = genExp(env, rewriter, exp.children.e0, ldx); - v1 = genExp(env, rewriter, exp.children.e1, ldx); + v0 = genExp(env, rewriter, exp.children.e0); + v1 = genExp(env, rewriter, exp.children.e1); } Value ee; @@ -653,7 +638,7 @@ static Value genExp(CodegenEnv &env, RewriterBase &rewriter, ExprId e, kind == TensorExp::Kind::kReduce || kind == TensorExp::Kind::kSelect)) { OpBuilder::InsertionGuard guard(rewriter); - ee = relinkBranch(env, rewriter, ee.getParentBlock(), ee, ldx); + ee = relinkBranch(env, rewriter, ee.getParentBlock(), ee); } } @@ -668,30 +653,30 @@ static Value genExp(CodegenEnv &env, RewriterBase &rewriter, ExprId e, /// Hoists loop invariant tensor loads for which indices have been exhausted. static void genInvariants(CodegenEnv &env, OpBuilder &builder, ExprId exp, - LoopId ldx, bool atStart) { + LoopId curr, bool isStart) { if (exp == ::mlir::sparse_tensor::detail::kInvalidId) return; if (env.exp(exp).kind == TensorExp::Kind::kTensor) { // Inspect tensor indices. - bool isAtLoop = ldx == ::mlir::sparse_tensor::detail::kInvalidId; linalg::GenericOp op = env.op(); OpOperand &t = op->getOpOperand(env.exp(exp).tensor); const auto map = op.getMatchingIndexingMap(&t); const auto stt = getSparseTensorType(t.get()); const Level lvlRank = stt.getLvlRank(); assert(static_cast(map.getNumResults()) == lvlRank); + bool isCurrentLoop = curr == 0; // for scalar tensors for (Level l = 0; l < lvlRank; l++) { const AffineExpr a = map.getResult(l); - if (!isInvariantAffine(a, env.getLoopDepth(), ldx, isAtLoop)) + if (!isInvariantAffine(a, curr, /*out*/ isCurrentLoop)) return; // still in play } - // All exhausted at this level (isAtLoop denotes exactly at this LoopId). - if (!isAtLoop) + // All exhausted at current level. + if (!isCurrentLoop) return; OpOperand *lhs = op.getDpsInitOperand(0); if (lhs == &t) { // Start or end a scalarized reduction. - if (atStart) { + if (isStart) { Value load = env.isCustomReduc() ? env.getCustomRedId() : genTensorLoad(env, builder, exp); env.startReduc(exp, load); @@ -703,7 +688,7 @@ static void genInvariants(CodegenEnv &env, OpBuilder &builder, ExprId exp, } } else { // Start or end loop invariant hoisting of a tensor load. - if (atStart) + if (isStart) env.merger().setExprValue(exp, genTensorLoad(env, builder, exp)); else env.merger().clearExprValue(exp); @@ -718,20 +703,20 @@ static void genInvariants(CodegenEnv &env, OpBuilder &builder, ExprId exp, env.startCustomReduc(exp); // enter custom const ExprId e0 = env.exp(exp).children.e0; const ExprId e1 = env.exp(exp).children.e1; - genInvariants(env, builder, e0, ldx, atStart); - genInvariants(env, builder, e1, ldx, atStart); + genInvariants(env, builder, e0, curr, isStart); + genInvariants(env, builder, e1, curr, isStart); if (env.exp(exp).kind == TensorExp::Kind::kReduce) env.endCustomReduc(); // exit custom } } /// Generates an expanded access pattern in innermost dimension. -static void genExpand(CodegenEnv &env, OpBuilder &builder, LoopOrd at, - bool atStart) { +static void genExpand(CodegenEnv &env, OpBuilder &builder, LoopId curr, + bool isStart) { linalg::GenericOp op = env.op(); OpOperand *lhs = op.getDpsInitOperand(0); - if (!env.atExpandLevel(lhs, op.getRank(lhs), at)) - return; // not needed at this level + if (!env.atExpandLevel(lhs, op.getRank(lhs), curr)) + return; // not needed at current level assert(!env.isReduc()); // Generate start or end of an expanded access pattern. Note that because // an expansion does not rely on the ongoing contents of the sparse storage @@ -740,7 +725,7 @@ static void genExpand(CodegenEnv &env, OpBuilder &builder, LoopOrd at, // needed, we will need to use the SSA value in the insertion chain instead. Value tensor = lhs->get(); Location loc = op.getLoc(); - if (atStart) { + if (isStart) { auto dynShape = {ShapedType::kDynamic}; Type etp = cast(tensor.getType()).getElementType(); Type t1 = MemRefType::get(dynShape, etp); @@ -753,7 +738,7 @@ static void genExpand(CodegenEnv &env, OpBuilder &builder, LoopOrd at, r.getResult(3)); } else { SmallVector indices; - for (LoopOrd i = 0; i < at; i++) + for (LoopId i = 0; i < curr; i++) indices.push_back(env.emitter().getLoopIV(i)); Value values = env.getExpandValues(); Value filled = env.getExpandFilled(); @@ -795,30 +780,28 @@ static bool isParallelFor(CodegenEnv &env, bool isOuter, bool isSparse) { /// Whether or not the current loop being generated should be parallized (if /// possible) according to the configuration. -static bool shouldTryParallize(CodegenEnv &env, LoopId ldx, bool isOuter, +static bool shouldTryParallize(CodegenEnv &env, LoopId curr, ArrayRef tidLvls) { linalg::GenericOp op = env.op(); auto iteratorTypes = op.getIteratorTypesArray(); - bool isSparse = llvm::any_of(tidLvls, [ldx, &env](TensorLevel tidLvl) { - // Queries the LT based on the tensor id and loop idx, as requested by - // `CodegenEnv::lt(TensorId, LoopIdx)`. The returned LT from CodegenEnv + bool isSparse = llvm::any_of(tidLvls, [curr, &env](TensorLevel tidLvl) { + // Queries the LT based on the tensor and loop id, as requested by + // `CodegenEnv::lt(TensorId, LoopId)`. The returned LT from CodegenEnv // should be consistent with the LT indexed by . - const auto lt = env.lt(env.unpackTensorLevel(tidLvl).first, ldx); + const auto lt = env.lt(env.unpackTensorLevel(tidLvl).first, curr); return isCompressedLT(lt) || isSingletonLT(lt); }); - - return isParallelFor(env, isOuter, isSparse); + return isParallelFor(env, /*isOuter=*/curr == 0, isSparse); } /// Emit a loop to coiterate over the list of tensor levels. The generated loop /// can either be a for loop or while loop depending on whether there is at most /// one sparse level in the list. static Operation *genCoIteration(CodegenEnv &env, OpBuilder &builder, - LoopId idx, ArrayRef tidLvls, + ArrayRef tidLvls, bool tryParallel, bool needsUniv) { Operation *loop = *env.genLoopBoundary([&](MutableArrayRef reduc) { - // Construct the while-loop with a parameter for each - // index. + // Construct while-loop with a parameter for each index. return env.emitter().enterCoIterationOverTensorsAtLvls( builder, env.op().getLoc(), tidLvls, reduc, tryParallel, /*genDedup=*/true, needsUniv); @@ -829,14 +812,14 @@ static Operation *genCoIteration(CodegenEnv &env, OpBuilder &builder, /// Generates a for-loop or a while-loop, depending on whether it implements /// singleton iteration or co-iteration over the given conjunction. -static Operation *genLoop(CodegenEnv &env, OpBuilder &builder, LoopOrd at, +static Operation *genLoop(CodegenEnv &env, OpBuilder &builder, LoopId curr, bool needsUniv, ArrayRef tidLvls) { - bool tryParallel = shouldTryParallize(env, at, at == 0, tidLvls); - return genCoIteration(env, builder, at, tidLvls, tryParallel, needsUniv); + bool tryParallel = shouldTryParallize(env, curr, tidLvls); + return genCoIteration(env, builder, tidLvls, tryParallel, needsUniv); } /// Generates the induction structure for a while-loop. -static void finalizeWhileOp(CodegenEnv &env, OpBuilder &builder, LoopId idx, +static void finalizeWhileOp(CodegenEnv &env, OpBuilder &builder, bool needsUniv) { Location loc = env.op().getLoc(); // Finalize each else branch of all if statements. @@ -876,7 +859,7 @@ static void finalizeWhileOp(CodegenEnv &env, OpBuilder &builder, LoopId idx, } /// Generates a single if-statement within a while-loop. -static scf::IfOp genIf(CodegenEnv &env, OpBuilder &builder, LoopId ldx, +static scf::IfOp genIf(CodegenEnv &env, OpBuilder &builder, LoopId curr, LatPointId p) { Location loc = env.op().getLoc(); SmallVector types; @@ -894,13 +877,13 @@ static scf::IfOp genIf(CodegenEnv &env, OpBuilder &builder, LoopId ldx, auto stt = getSparseTensorType(env.op().getInputs()[tid]); lt = stt.getLvlType(*lvl); } - assert(ldx == env.merger().loop(b)); + assert(curr == env.merger().loop(b)); Value clause; if (isCompressedLT(lt) || isSingletonLT(lt) || isLooseCompressedLT(lt) || is2OutOf4LT(lt)) { assert(lvl.has_value()); const Value crd = env.emitter().getCoords()[tid][*lvl]; - const Value lvar = env.getLoopVar(ldx); + const Value lvar = env.getLoopVar(curr); clause = builder.create(loc, arith::CmpIPredicate::eq, crd, lvar); } else { @@ -957,12 +940,12 @@ static void endIf(CodegenEnv &env, OpBuilder &builder, scf::IfOp ifOp, /// Starts a loop sequence at given level. Returns true if /// the universal loop index must be maintained at this level. static bool startLoopSeq(CodegenEnv &env, OpBuilder &builder, ExprId exp, - LoopOrd idx, LoopId ldx, LatSetId lts) { - assert(!env.getLoopVar(idx)); + LoopId curr, LatSetId lts) { + assert(!env.getLoopVar(curr)); // Emit invariants at this loop sequence level. - genInvariants(env, builder, exp, ldx, /*atStart=*/true); + genInvariants(env, builder, exp, curr, /*isStart=*/true); // Emit access pattern expansion for sparse tensor output. - genExpand(env, builder, idx, /*atStart=*/true); + genExpand(env, builder, curr, /*isStart=*/true); // Emit further intitialization at this loop sequence level. const LatPointId l0 = env.set(lts)[0]; bool needsUniv = false; @@ -971,13 +954,12 @@ static bool startLoopSeq(CodegenEnv &env, OpBuilder &builder, ExprId exp, env.merger().foreachTensorLoopId(l0, [&](TensorLoopId b, TensorId tid, std::optional lvl, LevelType lt, bool isIdxReduc) { - assert(env.merger().loop(b) == idx); + assert(env.merger().loop(b) == curr); if (isDenseLT(lt) || isUndefLT(lt)) { if (tid == env.merger().getSynTensorID()) { // Needs loop emitter to set up loop bounds for synthetic tensor too if // there is a loop condition imposed on the synthetic tensor. - tidLvls.push_back( - env.makeTensorLevel(tid, env.emitter().getCurrentDepth())); + tidLvls.push_back(env.makeTensorLevel(tid, env.getCurrentDepth())); } needsUniv = true; } @@ -1002,6 +984,7 @@ static bool startLoopSeq(CodegenEnv &env, OpBuilder &builder, ExprId exp, return false; } +// Generates dense affine address for encoding. static void genConstantDenseAddressFromLevel(CodegenEnv &env, OpBuilder &builder, TensorId tid, Level startLvl) { @@ -1027,104 +1010,101 @@ static void genConstantDenseAddressFromLevel(CodegenEnv &env, } } +// We can generate address for constant affine expression before any loops +// starting from the first level as they do not depend on any thing. +// E.g., [Dense, Dense, Sparse] -> (1, 2, d0), the addresses for the first two +// levels can be determined before loops. static void genInitConstantDenseAddress(CodegenEnv &env, RewriterBase &rewriter) { - // We can generate address for constant affine expression before any loops - // starting from the first level as they do not depend on any thing. - // E.g., [Dense, Dense, Sparse] -> (1, 2, d0), the addresses for the first two - // levels can be determined before loops. for (TensorId tid = 0, e = env.op().getNumDpsInputs(); tid < e; tid++) genConstantDenseAddressFromLevel(env, rewriter, tid, 0); } /// Return true if the lattices bit can be iterated by a for loop. static bool translateBitsToTidLvlPairs( - CodegenEnv &env, LatPointId li, LoopId ldx, + CodegenEnv &env, LatPointId li, LoopId curr, SmallVectorImpl &tidLvls, SmallVectorImpl> &affineTidLvls) { const BitVector &simple = env.lat(li).simple; const TensorId outTid = env.merger().getOutTensorID(); - const std::optional outLvl = env.merger().getLvl(outTid, ldx); + const std::optional outLvl = env.merger().getLvl(outTid, curr); unsigned numloopCond = 0; bool hasNonUnique = false; - env.merger().foreachTensorLoopId(li, [&, ldx](TensorLoopId b, TensorId tid, - std::optional lvl, - LevelType lt, bool isIdxReduc) { - if (simple[b]) { - if (isIdxReduc) { - tidLvls.push_back(env.makeTensorLevel(tid, *lvl)); - numloopCond++; - return; - } - if (isUndefLT(lt)) { - // An undefined lt in the lattices, we probably mean to - // generate a dense loop according to the synthetic tensor (for - // invariants and sparse output tensor). - if (env.merger().getSynTensorID() == tid) { - // Coiterating with an invariant - // e.g., out = prod(in[i][j] op invariant); - // or a broadcast - // e.g., out[i][j] = in[i] (j is undef for input) - // - // The level of the synthetic tensor is the current loop depth; - // the rank of the synthetic tensor equals to number of loops. - lvl = env.emitter().getCurrentDepth(); - } else if (!lvl) { - // Skips invalid lvl (e.g., when this is a zero ranked tensor). - return; - } - } - hasNonUnique = !isUniqueLT(lt) || hasNonUnique; - tidLvls.push_back(env.makeTensorLevel(tid, *lvl)); - numloopCond++; - } else if (isDenseLT(lt) || isIdxReduc) { - tidLvls.push_back(env.makeTensorLevel(tid, *lvl)); - } else { - assert(isUndefLT(lt)); - linalg::GenericOp op = env.op(); - if (tid >= op.getNumDpsInputs()) - // We only handle affine expression on input tensors (for now). - return; - OpOperand *operand = &op->getOpOperand(tid); - const auto stt = getSparseTensorType(operand->get()); - // Non-annotated dense tensors requires no special handling. - if (!stt.hasEncoding()) - return; - - ArrayRef affines = - op.getMatchingIndexingMap(operand).getResults(); - const Level lvlRank = stt.getLvlRank(); - assert(affines.size() == static_cast(lvlRank)); - for (Level l = 0; l < lvlRank; l++) { - AffineExpr exp = affines[l]; - // Skip simple affine expression and non-dense levels (which - // have their own filter loop). - if (isa(exp) || !stt.isDenseLvl(l)) - continue; - - // Constant affine expression are handled in genLoop - if (!isa(exp)) { - bool isAtLoop = false; - if (isInvariantAffine(exp, env.getLoopDepth(), ldx, isAtLoop) && - isAtLoop) { - // If the compound affine is invariant and we are right at the - // level. We need to generate the address according to the - // affine expression. This is also the best place we can do it - // to avoid putting it inside inner loops. - // NOTE: It assumes that the levels of the input tensor are - // initialized in order (and it is also currently guaranteed by - // computeIterationGraph), another more admissible approach - // might be accepting out-of-order access between consecutive - // dense levels. - affineTidLvls.emplace_back(env.makeTensorLevel(tid, l), exp); + env.merger().foreachTensorLoopId( + li, [&, curr](TensorLoopId b, TensorId tid, std::optional lvl, + LevelType lt, bool isIdxReduc) { + if (simple[b]) { + if (isIdxReduc) { + tidLvls.push_back(env.makeTensorLevel(tid, *lvl)); + numloopCond++; + return; + } + if (isUndefLT(lt)) { + // An undefined lt in the lattices, we probably mean to + // generate a dense loop according to the synthetic tensor (for + // invariants and sparse output tensor). + if (env.merger().getSynTensorID() == tid) { + // Coiterating with an invariant + // e.g., out = prod(in[i][j] op invariant); + // or a broadcast + // e.g., out[i][j] = in[i] (j is undef for input) + // + // The level of the synthetic tensor is the current loop depth; + // the rank of the synthetic tensor equals to number of loops. + assert(curr == env.getCurrentDepth()); + lvl = curr; + } else if (!lvl) { + // Skips invalid lvl (e.g., when this is a zero ranked tensor). + return; + } + } + hasNonUnique = !isUniqueLT(lt) || hasNonUnique; + tidLvls.push_back(env.makeTensorLevel(tid, *lvl)); + numloopCond++; + } else if (isDenseLT(lt) || isIdxReduc) { + tidLvls.push_back(env.makeTensorLevel(tid, *lvl)); + } else { + assert(isUndefLT(lt)); + linalg::GenericOp op = env.op(); + if (tid >= op.getNumDpsInputs()) + // We only handle affine expression on input tensors (for now). + return; + OpOperand *operand = &op->getOpOperand(tid); + const auto stt = getSparseTensorType(operand->get()); + // Non-annotated dense tensors requires no special handling. + if (!stt.hasEncoding()) + return; + + ArrayRef affines = + op.getMatchingIndexingMap(operand).getResults(); + const Level lvlRank = stt.getLvlRank(); + assert(affines.size() == static_cast(lvlRank)); + for (Level l = 0; l < lvlRank; l++) { + AffineExpr exp = affines[l]; + // Skip simple affine expression and non-dense levels (which + // have their own filter loop). + if (isa(exp) || !stt.isDenseLvl(l)) + continue; + + // Constant affine expression are handled in genLoop. + if (!isa(exp)) { + bool isCurrentLoop = false; + assert(curr == env.getCurrentDepth()); + if (isInvariantAffine(exp, curr + 1, /*out*/ isCurrentLoop) && + isCurrentLoop) { + // If the compound affine is invariant and we are right at the + // level. We need to generate the address according to the + // affine expression. This is also the best place we can do it + // to avoid putting it inside inner loops. + affineTidLvls.emplace_back(env.makeTensorLevel(tid, l), exp); + } + } } } - } - } - }); + }); - if (isDenseLT(env.lt(outTid, ldx))) { + if (isDenseLT(env.lt(outTid, curr))) { // Note that we generate dense indices of the output tensor // unconditionally, since they may not appear in the lattice, but may be // needed for linearized env. @@ -1136,7 +1116,7 @@ static bool translateBitsToTidLvlPairs( // this case, we just generate a dense "fake" loop by iterating over the // synthetic tensor. tidLvls.push_back(env.makeTensorLevel(env.merger().getSynTensorID(), - env.emitter().getCurrentDepth())); + env.getCurrentDepth())); numloopCond++; } // If we just need to one loop conditions and the conditions is not imposed on @@ -1146,19 +1126,19 @@ static bool translateBitsToTidLvlPairs( /// Starts a single loop in current sequence. static std::pair startLoop(CodegenEnv &env, - OpBuilder &builder, LoopOrd at, + OpBuilder &builder, LoopId curr, LatPointId li, bool needsUniv) { // The set of tensors + lvls to generate loops on SmallVector tidLvls; + // The set of dense tensors with non-trivial affine expression that just - // becomes invariant and the address shall now be generated at the current - // level. + // becomes invariant and the address are generated at the current level. SmallVector> affineTidLvls; bool isSingleCond = - translateBitsToTidLvlPairs(env, li, at, tidLvls, affineTidLvls); + translateBitsToTidLvlPairs(env, li, curr, tidLvls, affineTidLvls); // Emit the for/while-loop control. - Operation *loop = genLoop(env, builder, at, needsUniv, tidLvls); + Operation *loop = genLoop(env, builder, curr, needsUniv, tidLvls); Location loc = env.op().getLoc(); for (auto [tidLvl, exp] : affineTidLvls) { env.emitter().genDenseAffineAddress(builder, loc, tidLvl, exp); @@ -1180,70 +1160,66 @@ static std::pair startLoop(CodegenEnv &env, /// Ends a single loop in current sequence. Returns new values for needsUniv. static bool endLoop(CodegenEnv &env, RewriterBase &rewriter, Operation *loop, - LoopId idx, LatPointId li, bool needsUniv, - bool isSingleCond) { - + LatPointId li, bool needsUniv, bool isSingleCond) { + // Either a for-loop or a while-loop that iterates over a slice. if (isSingleCond) { - // Either a for-loop or a while-loop that iterates over a slice. // Any iteration creates a valid lex insert. if (env.isReduc() && env.getValidLexInsert()) env.setValidLexInsert(constantI1(rewriter, env.op().getLoc(), true)); } else if (auto whileOp = dyn_cast(loop)) { // End a while-loop. - finalizeWhileOp(env, rewriter, idx, needsUniv); + finalizeWhileOp(env, rewriter, needsUniv); } else { needsUniv = false; } - env.genLoopBoundary([&](MutableArrayRef reduc) { env.emitter().exitCurrentLoop(rewriter, env.op().getLoc(), reduc); return std::nullopt; }); - return needsUniv; } /// Ends a loop sequence at given level. static void endLoopSeq(CodegenEnv &env, OpBuilder &builder, unsigned exp, - unsigned idx, unsigned ldx) { - assert(!env.getLoopVar(idx)); + unsigned at) { + assert(!env.getLoopVar(at)); env.emitter().exitCurrentLoopSeq(builder, env.op().getLoc()); // Unmark bookkeeping of invariants and loop index. - genInvariants(env, builder, exp, ldx, /*atStart=*/false); + genInvariants(env, builder, exp, at, /*isStart=*/false); // Finalize access pattern expansion for sparse tensor output. - genExpand(env, builder, idx, /*atStart=*/false); + genExpand(env, builder, at, /*isStart=*/false); } /// Recursively generates code while computing iteration lattices in order /// to manage the complexity of implementing co-iteration over unions /// and intersections of sparse iterations spaces. static void genStmt(CodegenEnv &env, RewriterBase &rewriter, ExprId exp, - LoopOrd at) { + LoopId curr) { + assert(curr == env.getCurrentDepth()); + // At each leaf, assign remaining tensor (sub)expression to output tensor. - if (at == env.getLoopNum()) { - Value rhs = genExp(env, rewriter, exp, at - 1); + if (curr == env.getLoopNum()) { + Value rhs = genExp(env, rewriter, exp); genTensorStore(env, rewriter, exp, rhs); return; } - // Construct iteration lattices for current loop index, with L0 at top. - const LoopId ldx = at == 0 ? sparse_tensor::detail::kInvalidId : at - 1; + // Construct iteration lattices for current loop index. const LatSetId lts = - env.merger().optimizeSet(env.merger().buildLattices(exp, at)); + env.merger().optimizeSet(env.merger().buildLattices(exp, curr)); // Start a loop sequence. - bool needsUniv = startLoopSeq(env, rewriter, exp, at, ldx, lts); + bool needsUniv = startLoopSeq(env, rewriter, exp, curr, lts); // Emit a loop for every lattice point L0 >= Li in this loop sequence. - // - // NOTE: We cannot change this to `for (const LatPointId li : env.set(lts))` + // We cannot change this to `for (const LatPointId li : env.set(lts))` // because the loop body causes data-movement which invalidates // the iterator. const unsigned lsize = env.set(lts).size(); for (unsigned i = 0; i < lsize; i++) { const LatPointId li = env.set(lts)[i]; // Start a loop. - auto [loop, isSingleCond] = startLoop(env, rewriter, at, li, needsUniv); + auto [loop, isSingleCond] = startLoop(env, rewriter, curr, li, needsUniv); // Visit all lattices points with Li >= Lj to generate the // loop-body, possibly with if statements for coiteration. @@ -1251,7 +1227,7 @@ static void genStmt(CodegenEnv &env, RewriterBase &rewriter, ExprId exp, Value cntInput = env.getExpandCount(); Value insInput = env.getInsertionChain(); Value validIns = env.getValidLexInsert(); - // NOTE: We cannot change this to `for (const LatPointId lj : env.set(lts))` + // We cannot change this to `for (const LatPointId lj : env.set(lts))` // because the loop body causes data-movement which invalidates the // iterator. for (unsigned j = 0; j < lsize; j++) { @@ -1260,21 +1236,22 @@ static void genStmt(CodegenEnv &env, RewriterBase &rewriter, ExprId exp, if (li == lj || env.merger().latGT(li, lj)) { // Recurse into body of each branch. if (!isSingleCond) { - scf::IfOp ifOp = genIf(env, rewriter, at, lj); - genStmt(env, rewriter, ej, at + 1); + scf::IfOp ifOp = genIf(env, rewriter, curr, lj); + genStmt(env, rewriter, ej, curr + 1); endIf(env, rewriter, ifOp, redInput, cntInput, insInput, validIns); } else { - genStmt(env, rewriter, ej, at + 1); + genStmt(env, rewriter, ej, curr + 1); } } } // End a loop. - needsUniv = endLoop(env, rewriter, loop, at, li, needsUniv, isSingleCond); + needsUniv = endLoop(env, rewriter, loop, curr, needsUniv, isSingleCond); } // End a loop sequence. - endLoopSeq(env, rewriter, exp, at, ldx); + endLoopSeq(env, rewriter, exp, curr); + assert(curr == env.getCurrentDepth()); } /// Converts the result computed by the sparse kernel into the required form. @@ -1323,11 +1300,13 @@ public: if (hasNonTrivialAffineOnSparseOut(op)) return failure(); + // Only accept scheduled loops. if (!op->hasAttr("sorted")) { return rewriter.notifyMatchFailure( op, "Loops not yet scheduled, try run --sparse-reinterpret-map " "before sparsification."); } + // Must have been demapped as well if the generic op is sorted. assert(!hasAnyNonIdentityOperandsOrResults(op)); @@ -1348,9 +1327,9 @@ public: } } - CodegenEnv env(op, options, numTensors, numLoops, maxLvlRank); // Detects sparse annotations and translates the per-level sparsity // information for all tensors to loop indices in the kernel. + CodegenEnv env(op, options, numTensors, numLoops, maxLvlRank); if (!findSparseAnnotations(env, needIdxRed)) return failure(); @@ -1382,7 +1361,7 @@ public: genBuffers(env, rewriter); // TODO: Constant affine expression should be handled differently when using // slice-based codegen, it does not matter now because we already reject the - // constant expression at a earlier stage. + // constant expression at an earlier stage. genInitConstantDenseAddress(env, rewriter); genStmt(env, rewriter, env.getExprId(), 0); genResult(env, rewriter); diff --git a/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp b/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp index f15695383d34..55f813df78b8 100644 --- a/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp +++ b/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp @@ -1447,13 +1447,8 @@ struct StaticTensorGenerate : public OpRewritePattern { SmallVector newShape; operandsAndShape(resultType, dynamicExtents, newOperands, newShape); - for (int64_t newdim : newShape) { - // This check also occurs in the verifier, but we need it here too - // since intermediate passes may have replaced some dynamic dimensions - // by constants. - if (newdim < 0 && !ShapedType::isDynamic(newdim)) - return failure(); - } + if (!hasValidSizesOffsets(newShape)) + return failure(); if (newOperands.size() == tensorFromElements.getDynamicExtents().size()) return failure(); @@ -2549,9 +2544,9 @@ public: SmallVector mixedStrides(insertSliceOp.getMixedStrides()); // No constant operands were folded, just return; - if (failed(foldDynamicIndexList(mixedOffsets, /*onlyNonNegative=*/true)) && - failed(foldDynamicIndexList(mixedSizes, /*onlyNonNegative=*/true)) && - failed(foldDynamicIndexList(mixedStrides))) + if (failed(foldDynamicOffsetSizeList(mixedOffsets)) && + failed(foldDynamicOffsetSizeList(mixedSizes)) && + failed(foldDynamicStrideList(mixedStrides))) return failure(); // Create the new op in canonical form. @@ -2692,6 +2687,8 @@ struct InsertSliceOpSourceCastInserter final newSrcShape[i] = *constInt; } } + if (!hasValidSizesOffsets(newSrcShape)) + return failure(); RankedTensorType newSrcType = RankedTensorType::get(newSrcShape, srcType.getElementType()); diff --git a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp index f490cb1baa30..259fb6394669 100644 --- a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp +++ b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp @@ -983,6 +983,10 @@ LogicalResult tosa::TransposeOp::inferReturnTypeComponents( ShapeAdaptor inputShape(adaptor.getInput1().getType()); ShapeAdaptor permsShape(adaptor.getPerms().getType()); + // We cannot infer anything from a rank-0 "permutation" tensor. + if (permsShape.hasRank() && permsShape.getRank() == 0) + return failure(); + // If input rank and permutation length is unknown, the output rank is // unknown. if (!inputShape.hasRank() || !permsShape.hasRank() || @@ -997,15 +1001,7 @@ LogicalResult tosa::TransposeOp::inferReturnTypeComponents( return failure(); } - // Without the input dims we cannot determine the output dim sizes but we - // can determine the output rank. SmallVector outputShape; - if (!inputShape.hasRank()) { - outputShape.resize(permsShape.getDimSize(0), ShapedType::kDynamic); - inferredReturnShapes.push_back(ShapedTypeComponents(outputShape)); - return success(); - } - // Rank-0 means no permutations matter. if (inputShape.getRank() == 0) { inferredReturnShapes.push_back(ShapedTypeComponents(outputShape)); diff --git a/mlir/lib/Dialect/Transform/IR/TransformInterfaces.cpp b/mlir/lib/Dialect/Transform/IR/TransformInterfaces.cpp index de5b7a81286b..cd66a0e566f6 100644 --- a/mlir/lib/Dialect/Transform/IR/TransformInterfaces.cpp +++ b/mlir/lib/Dialect/Transform/IR/TransformInterfaces.cpp @@ -30,6 +30,23 @@ using namespace mlir; +//===----------------------------------------------------------------------===// +// Helper functions +//===----------------------------------------------------------------------===// + +/// Return true if `a` happens before `b`, i.e., `a` or one of its ancestors +/// properly dominates `b` and `b` is not inside `a`. +static bool happensBefore(Operation *a, Operation *b) { + do { + if (a->isProperAncestor(b)) + return false; + if (Operation *bAncestor = a->getBlock()->findAncestorOpInBlock(*b)) { + return a->isBeforeInBlock(bAncestor); + } + } while ((a = a->getParentOp())); + return false; +} + //===----------------------------------------------------------------------===// // TransformState //===----------------------------------------------------------------------===// @@ -44,14 +61,10 @@ transform::TransformState::TransformState( topLevelMappedValues.reserve(extraMappings.size()); for (ArrayRef mapping : extraMappings) topLevelMappedValues.push_back(mapping); - - auto result = - mappings.insert(std::make_pair(region, std::make_unique())); - assert(result.second && "the region scope is already present"); - (void)result; -#if LLVM_ENABLE_ABI_BREAKING_CHECKS - regionStack.push_back(region); -#endif // LLVM_ENABLE_ABI_BREAKING_CHECKS + if (region) { + RegionScope *scope = new RegionScope(*this, *region); + topLevelRegionScope.reset(scope); + } } Operation *transform::TransformState::getTopLevel() const { return topLevel; } @@ -811,6 +824,11 @@ transform::TransformState::applyTransform(TransformOpInterface transform) { LLVM_DEBUG(DBGS() << "Failing Top-level payload:\n"; getTopLevel()->print( llvm::dbgs(), mlir::OpPrintingFlags().printGenericOpForm());); }); + + // Set current transform op. + regionStack.back()->currentTransform = transform; + + // Expensive checks to detect invalid transform IR. if (options.getExpensiveChecksEnabled()) { FULL_LDBG("ExpensiveChecksEnabled\n"); if (failed(checkAndRecordHandleInvalidation(transform))) @@ -899,7 +917,24 @@ transform::TransformState::applyTransform(TransformOpInterface transform) { } // Prepare rewriter and listener. - transform::ErrorCheckingTrackingListener trackingListener(*this, transform); + TrackingListener::SkipHandleFn skipHandleFn = [&](Value handle) { + // Skip handle if it is dead. + auto scopeIt = + llvm::find_if(llvm::reverse(regionStack), [&](RegionScope *scope) { + return handle.getParentRegion() == scope->region; + }); + assert(scopeIt != regionStack.rend() && + "could not find region scope for handle"); + RegionScope *scope = *scopeIt; + for (Operation *user : handle.getUsers()) { + if (user != scope->currentTransform && + !happensBefore(user, scope->currentTransform)) + return false; + } + return true; + }; + transform::ErrorCheckingTrackingListener trackingListener(*this, transform, + skipHandleFn); transform::TransformRewriter rewriter(transform->getContext(), &trackingListener); @@ -1040,10 +1075,7 @@ transform::TransformState::RegionScope::~RegionScope() { #endif // LLVM_ENABLE_ABI_BREAKING_CHECKS state.mappings.erase(region); - -#if LLVM_ENABLE_ABI_BREAKING_CHECKS state.regionStack.pop_back(); -#endif // LLVM_ENABLE_ABI_BREAKING_CHECKS } //===----------------------------------------------------------------------===// @@ -1150,8 +1182,10 @@ bool transform::TransformResults::isSet(unsigned resultNumber) const { //===----------------------------------------------------------------------===// transform::TrackingListener::TrackingListener(TransformState &state, - TransformOpInterface op) - : TransformState::Extension(state), transformOp(op) { + TransformOpInterface op, + SkipHandleFn skipHandleFn) + : TransformState::Extension(state), transformOp(op), + skipHandleFn(skipHandleFn) { if (op) { for (OpOperand *opOperand : transformOp.getConsumedHandleOpOperands()) { consumedHandles.insert(opOperand->get()); @@ -1251,19 +1285,6 @@ void transform::TrackingListener::notifyOperationRemoved(Operation *op) { }); } -/// Return true if `a` happens before `b`, i.e., `a` or one of its ancestors -/// properly dominates `b` and `b` is not inside `a`. -static bool happensBefore(Operation *a, Operation *b) { - do { - if (a->isProperAncestor(b)) - return false; - if (Operation *bAncestor = a->getBlock()->findAncestorOpInBlock(*b)) { - return a->isBeforeInBlock(bAncestor); - } - } while ((a = a->getParentOp())); - return false; -} - void transform::TrackingListener::notifyOperationReplaced( Operation *op, ValueRange newValues) { assert(op->getNumResults() == newValues.size() && @@ -1295,18 +1316,17 @@ void transform::TrackingListener::notifyOperationReplaced( [&](Value h) { return consumedHandles.contains(h); }); }; - // Helper function to check if the handle is alive. - auto firstAliveUser = [&]() -> std::optional { - for (Value v : opHandles) { - for (OpOperand &use : v.getUses()) - if (use.getOwner() != transformOp && - !happensBefore(use.getOwner(), transformOp)) - return &use; - } - return std::nullopt; - }(); - - if (!firstAliveUser.has_value() || handleWasConsumed()) { + // Check if there are any handles that must be updated. + Value aliveHandle; + if (skipHandleFn) { + auto it = + llvm::find_if(opHandles, [&](Value v) { return !skipHandleFn(v); }); + if (it != opHandles.end()) + aliveHandle = *it; + } else if (!opHandles.empty()) { + aliveHandle = opHandles.front(); + } + if (!aliveHandle || handleWasConsumed()) { // The op is tracked but the corresponding handles are dead or were // consumed. Drop the op form the mapping. (void)replacePayloadOp(op, nullptr); @@ -1319,10 +1339,8 @@ void transform::TrackingListener::notifyOperationReplaced( // If the op is tracked but no replacement op was found, send a // notification. if (!diag.succeeded()) { - diag.attachNote((*firstAliveUser)->getOwner()->getLoc()) - << "replacement is required because alive handle(s) exist " - << "(first use in this op as operand number " - << (*firstAliveUser)->getOperandNumber() << ")"; + diag.attachNote(aliveHandle.getLoc()) + << "replacement is required because this handle must be updated"; notifyPayloadReplacementNotFound(op, newValues, std::move(diag)); (void)replacePayloadOp(op, nullptr); return; diff --git a/mlir/lib/Dialect/Utils/StaticValueUtils.cpp b/mlir/lib/Dialect/Utils/StaticValueUtils.cpp index c7a3d8fc8eb2..0c8a88da789e 100644 --- a/mlir/lib/Dialect/Utils/StaticValueUtils.cpp +++ b/mlir/lib/Dialect/Utils/StaticValueUtils.cpp @@ -256,8 +256,20 @@ std::optional constantTripCount(OpFoldResult lb, OpFoldResult ub, return mlir::ceilDiv(*ubConstant - *lbConstant, *stepConstant); } +bool hasValidSizesOffsets(SmallVector sizesOrOffsets) { + return llvm::none_of(sizesOrOffsets, [](int64_t value) { + return !ShapedType::isDynamic(value) && value < 0; + }); +} + +bool hasValidStrides(SmallVector strides) { + return llvm::none_of(strides, [](int64_t value) { + return !ShapedType::isDynamic(value) && value == 0; + }); +} + LogicalResult foldDynamicIndexList(SmallVectorImpl &ofrs, - bool onlyNonNegative) { + bool onlyNonNegative, bool onlyNonZero) { bool valuesChanged = false; for (OpFoldResult &ofr : ofrs) { if (ofr.is()) @@ -267,6 +279,8 @@ LogicalResult foldDynamicIndexList(SmallVectorImpl &ofrs, // Note: All ofrs have index type. if (onlyNonNegative && *getConstantIntValue(attr) < 0) continue; + if (onlyNonZero && *getConstantIntValue(attr) == 0) + continue; ofr = attr; valuesChanged = true; } @@ -274,4 +288,15 @@ LogicalResult foldDynamicIndexList(SmallVectorImpl &ofrs, return success(valuesChanged); } +LogicalResult +foldDynamicOffsetSizeList(SmallVectorImpl &offsetsOrSizes) { + return foldDynamicIndexList(offsetsOrSizes, /*onlyNonNegative=*/true, + /*onlyNonZero=*/false); +} + +LogicalResult foldDynamicStrideList(SmallVectorImpl &strides) { + return foldDynamicIndexList(strides, /*onlyNonNegative=*/false, + /*onlyNonZero=*/true); +} + } // namespace mlir diff --git a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp index caffd344848b..c462b23e1133 100644 --- a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp +++ b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp @@ -5548,57 +5548,12 @@ public: } }; -/// Folds transpose(shape_cast) into a new shape_cast, when the transpose just -/// permutes a unit dim from the result of the shape_cast. -class FoldTransposeShapeCast : public OpRewritePattern { - using OpRewritePattern::OpRewritePattern; - - LogicalResult matchAndRewrite(TransposeOp transpOp, - PatternRewriter &rewriter) const override { - Value transposeSrc = transpOp.getVector(); - auto shapeCastOp = transposeSrc.getDefiningOp(); - if (!shapeCastOp) - return rewriter.notifyMatchFailure( - transpOp, "TransposeOp source is not ShapeCastOp"); - - auto sourceType = transpOp.getSourceVectorType(); - auto resultType = transpOp.getResultVectorType(); - - auto filterUnitDims = [](VectorType type) { - return llvm::make_filter_range( - llvm::zip_equal(type.getShape(), type.getScalableDims()), - [&](auto dim) { - auto [size, isScalable] = dim; - return size != 1 || isScalable; - }); - }; - - auto sourceWithoutUnitDims = filterUnitDims(sourceType); - auto resultWithoutUnitDims = filterUnitDims(resultType); - - // If this transpose just permutes a unit dim, then we can fold it into the - // shape_cast. - for (auto [srcDim, resDim] : - llvm::zip_equal(sourceWithoutUnitDims, resultWithoutUnitDims)) { - if (srcDim != resDim) - return rewriter.notifyMatchFailure(transpOp, - "TransposeOp permutes non-unit dim"); - } - - rewriter.replaceOpWithNewOp(transpOp, resultType, - shapeCastOp.getSource()); - - return success(); - }; -}; - } // namespace void vector::TransposeOp::getCanonicalizationPatterns( RewritePatternSet &results, MLIRContext *context) { results.add( - context); + TransposeFolder, FoldTransposeSplat>(context); } //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp index aab707500603..ed42e6508b43 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp @@ -511,6 +511,8 @@ static Value collapseInnerDims(PatternRewriter &rewriter, mlir::Location loc, /// Checks that the indices corresponding to dimensions starting at /// `firstDimToCollapse` are constant 0, and writes to `outIndices` /// the truncated indices where `firstDimToCollapse` is now the innermost dim. +/// TODO: Extract the logic that writes to outIndices so that this method +/// simply checks one pre-condition. static LogicalResult checkAndCollapseInnerZeroIndices(ValueRange indices, int64_t firstDimToCollapse, SmallVector &outIndices) { @@ -542,18 +544,18 @@ class FlattenContiguousRowMajorTransferReadPattern auto loc = transferReadOp.getLoc(); Value vector = transferReadOp.getVector(); VectorType vectorType = cast(vector.getType()); - Value source = transferReadOp.getSource(); + auto source = transferReadOp.getSource(); MemRefType sourceType = dyn_cast(source.getType()); + + // 0. Check pre-conditions // Contiguity check is valid on tensors only. if (!sourceType) return failure(); + // If this is already 0D/1D, there's nothing to do. if (vectorType.getRank() <= 1) - // Already 0D/1D, nothing to do. return failure(); if (!vector::isContiguousSlice(sourceType, vectorType)) return failure(); - int64_t firstContiguousInnerDim = - sourceType.getRank() - vectorType.getRank(); // TODO: generalize this pattern, relax the requirements here. if (transferReadOp.hasOutOfBoundsDim()) return failure(); @@ -561,26 +563,81 @@ class FlattenContiguousRowMajorTransferReadPattern return failure(); if (transferReadOp.getMask()) return failure(); + SmallVector collapsedIndices; - if (failed(checkAndCollapseInnerZeroIndices(transferReadOp.getIndices(), - firstContiguousInnerDim, - collapsedIndices))) - return failure(); + int64_t firstDimToCollapse = sourceType.getRank() - vectorType.getRank(); + + // 1. Collapse the source memref Value collapsedSource = - collapseInnerDims(rewriter, loc, source, firstContiguousInnerDim); + collapseInnerDims(rewriter, loc, source, firstDimToCollapse); MemRefType collapsedSourceType = dyn_cast(collapsedSource.getType()); int64_t collapsedRank = collapsedSourceType.getRank(); - assert(collapsedRank == firstContiguousInnerDim + 1); + assert(collapsedRank == firstDimToCollapse + 1); + + // 2. Generate input args for a new vector.transfer_read that will read + // from the collapsed memref. + // 2.1. New dim exprs + affine map SmallVector dimExprs{ - getAffineDimExpr(firstContiguousInnerDim, rewriter.getContext())}; + getAffineDimExpr(firstDimToCollapse, rewriter.getContext())}; auto collapsedMap = AffineMap::get(collapsedRank, 0, dimExprs, rewriter.getContext()); + + // 2.2 New indices + // If all the collapsed indices are zero then no extra logic is needed. + // Otherwise, a new offset/index has to be computed. + if (failed(checkAndCollapseInnerZeroIndices(transferReadOp.getIndices(), + firstDimToCollapse, + collapsedIndices))) { + // Copy all the leading indices + collapsedIndices = transferReadOp.getIndices(); + collapsedIndices.resize(firstDimToCollapse); + + // Compute the remaining trailing index/offset required for reading from + // the collapsed memref: + // + // offset = 0 + // for (i = firstDimToCollapse; i < outputRank; ++i) + // offset += sourceType.getDimSize(i) * transferReadOp.indices[i] + // + // For this example: + // %2 = vector.transfer_read %arg4[%c0, %arg0, %c0] (...) : + // memref<1x43x2xi32>, vector<1x2xi32> + // which would be collapsed to: + // %1 = vector.transfer_read %collapse_shape[%c0, %offset] (...) : + // memref<1x86xi32>, vector<2xi32> + // one would get the following offset: + // %offset = %arg0 * 43 + AffineExpr offsetExpr, idxExpr; + bindSymbols(rewriter.getContext(), offsetExpr, idxExpr); + + int64_t outputRank = transferReadOp.getIndices().size(); + OpFoldResult offset = + rewriter.create(loc, 0).getResult(); + + for (int64_t i = firstDimToCollapse; i < outputRank; ++i) { + int64_t dim = dyn_cast(source.getType()).getDimSize(i); + offset = affine::makeComposedFoldedAffineApply( + rewriter, loc, offsetExpr + dim * idxExpr, + {offset, transferReadOp.getIndices()[i]}); + } + if (offset.is()) { + collapsedIndices.push_back(offset.get()); + } else { + collapsedIndices.push_back(rewriter.create( + loc, *getConstantIntValue(offset))); + } + } + + // 3. Create new vector.transfer_read that reads from the collapsed memref VectorType flatVectorType = VectorType::get({vectorType.getNumElements()}, vectorType.getElementType()); vector::TransferReadOp flatRead = rewriter.create( loc, flatVectorType, collapsedSource, collapsedIndices, collapsedMap); flatRead.setInBoundsAttr(rewriter.getBoolArrayAttr({true})); + + // 4. Replace the old transfer_read with the new one reading from the + // collapsed shape rewriter.replaceOpWithNewOp( transferReadOp, cast(vector.getType()), flatRead); return success(); diff --git a/mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp b/mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp index ac0fe64c70cd..2ad992af989c 100644 --- a/mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp +++ b/mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp @@ -265,6 +265,11 @@ bool vector::isContiguousSlice(MemRefType memrefType, VectorType vectorType) { return false; auto strides = ArrayRef(stridesFull).take_back(vecRank); + // TODO: Add support for memref with trailing dynamic shapes. Memrefs + // with leading dynamic dimensions are already supported. + if (ShapedType::isDynamicShape(memrefShape)) + return false; + // Cond 1: A contiguous memref will always have a unit trailing stride. if (strides.back() != 1) return false; diff --git a/mlir/lib/IR/Verifier.cpp b/mlir/lib/IR/Verifier.cpp index 0d2fa6486e21..a09b47ee981c 100644 --- a/mlir/lib/IR/Verifier.cpp +++ b/mlir/lib/IR/Verifier.cpp @@ -378,39 +378,39 @@ static void diagnoseInvalidOperandDominance(Operation &op, unsigned operandNo) { LogicalResult OperationVerifier::verifyDominanceOfContainedRegions(Operation &op, DominanceInfo &domInfo) { - for (Region ®ion : op.getRegions()) { - // Verify the dominance of each of the held operations. - for (Block &block : region) { - // Dominance is only meaningful inside reachable blocks. - bool isReachable = domInfo.isReachableFromEntry(&block); - - for (Operation &op : block) { - if (isReachable) { - // Check that operands properly dominate this use. - for (const auto &operand : llvm::enumerate(op.getOperands())) { - if (domInfo.properlyDominates(operand.value(), &op)) - continue; - - diagnoseInvalidOperandDominance(op, operand.index()); - return failure(); + llvm::SmallVector worklist{&op}; + while (!worklist.empty()) { + auto *op = worklist.pop_back_val(); + for (auto ®ion : op->getRegions()) + for (auto &block : region.getBlocks()) { + // Dominance is only meaningful inside reachable blocks. + bool isReachable = domInfo.isReachableFromEntry(&block); + for (auto &op : block) { + if (isReachable) { + // Check that operands properly dominate this use. + for (const auto &operand : llvm::enumerate(op.getOperands())) { + if (domInfo.properlyDominates(operand.value(), &op)) + continue; + + diagnoseInvalidOperandDominance(op, operand.index()); + return failure(); + } } - } - // Recursively verify dominance within each operation in the block, even - // if the block itself is not reachable, or we are in a region which - // doesn't respect dominance. - if (verifyRecursively && op.getNumRegions() != 0) { - // If this operation is IsolatedFromAbove, then we'll handle it in the - // outer verification loop. - if (op.hasTrait()) - continue; - - if (failed(verifyDominanceOfContainedRegions(op, domInfo))) - return failure(); + // Recursively verify dominance within each operation in the block, + // even if the block itself is not reachable, or we are in a region + // which doesn't respect dominance. + if (verifyRecursively && op.getNumRegions() != 0) { + // If this operation is IsolatedFromAbove, then we'll handle it in + // the outer verification loop. + if (op.hasTrait()) + continue; + worklist.push_back(&op); + } } } - } } + return success(); } diff --git a/mlir/lib/Target/LLVMIR/CMakeLists.txt b/mlir/lib/Target/LLVMIR/CMakeLists.txt index 5db0885d70d6..531c15a8703e 100644 --- a/mlir/lib/Target/LLVMIR/CMakeLists.txt +++ b/mlir/lib/Target/LLVMIR/CMakeLists.txt @@ -58,6 +58,7 @@ add_mlir_translation_library(MLIRToLLVMIRTranslationRegistration MLIROpenACCToLLVMIRTranslation MLIROpenMPToLLVMIRTranslation MLIRROCDLToLLVMIRTranslation + MLIRSPIRVToLLVMIRTranslation ) add_mlir_translation_library(MLIRTargetLLVMIRImport diff --git a/mlir/lib/Target/LLVMIR/DebugImporter.cpp b/mlir/lib/Target/LLVMIR/DebugImporter.cpp index 89d34e4e6f6c..13b81d134cbe 100644 --- a/mlir/lib/Target/LLVMIR/DebugImporter.cpp +++ b/mlir/lib/Target/LLVMIR/DebugImporter.cpp @@ -282,14 +282,15 @@ Location DebugImporter::translateLoc(llvm::DILocation *loc) { Location result = FileLineColLoc::get(context, loc->getFilename(), loc->getLine(), loc->getColumn()); - // Add call site information, if available. - if (llvm::DILocation *inlinedAt = loc->getInlinedAt()) - result = CallSiteLoc::get(result, translateLoc(inlinedAt)); - // Add scope information. assert(loc->getScope() && "expected non-null scope"); result = FusedLocWith::get({result}, translate(loc->getScope()), context); + + // Add call site information, if available. + if (llvm::DILocation *inlinedAt = loc->getInlinedAt()) + result = CallSiteLoc::get(result, translateLoc(inlinedAt)); + return result; } diff --git a/mlir/lib/Target/LLVMIR/DebugTranslation.cpp b/mlir/lib/Target/LLVMIR/DebugTranslation.cpp index 6d845e27ffa2..16918aab5497 100644 --- a/mlir/lib/Target/LLVMIR/DebugTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/DebugTranslation.cpp @@ -102,7 +102,9 @@ llvm::DICompileUnit *DebugTranslation::translateImpl(DICompileUnitAttr attr) { attr.getSourceLanguage(), translate(attr.getFile()), attr.getProducer() ? attr.getProducer().getValue() : "", attr.getIsOptimized(), - /*Flags=*/"", /*RV=*/0); + /*Flags=*/"", /*RV=*/0, /*SplitName=*/{}, + static_cast( + attr.getEmissionKind())); } /// Returns a new `DINodeT` that is either distinct or not, depending on @@ -328,7 +330,10 @@ llvm::DILocation *DebugTranslation::translateLoc(Location loc, if (auto callLoc = dyn_cast(loc)) { // For callsites, the caller is fed as the inlinedAt for the callee. auto *callerLoc = translateLoc(callLoc.getCaller(), scope, inlinedAt); - llvmLoc = translateLoc(callLoc.getCallee(), scope, callerLoc); + llvmLoc = translateLoc(callLoc.getCallee(), nullptr, callerLoc); + // Fallback: Ignore callee if it has no debug scope. + if (!llvmLoc) + llvmLoc = callerLoc; } else if (auto fileLoc = dyn_cast(loc)) { // A scope of a DILocation cannot be null. diff --git a/mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt b/mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt index fb0e5cd0649f..c9d916d8a5d8 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt +++ b/mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt @@ -9,4 +9,5 @@ add_subdirectory(NVVM) add_subdirectory(OpenACC) add_subdirectory(OpenMP) add_subdirectory(ROCDL) +add_subdirectory(SPIRV) add_subdirectory(X86Vector) diff --git a/mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp b/mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp index 2acccb7c2faf..0eb33287d608 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp @@ -175,6 +175,7 @@ private: IRBuilderBase &builder; mlir::LLVM::ModuleTranslation &moduleTranslation; Type *i32Ty{}; + Type *i64Ty{}; Type *voidTy{}; Type *intPtrTy{}; PointerType *ptrTy{}; @@ -216,6 +217,7 @@ llvm::LaunchKernel::LaunchKernel( mlir::LLVM::ModuleTranslation &moduleTranslation) : module(module), builder(builder), moduleTranslation(moduleTranslation) { i32Ty = builder.getInt32Ty(); + i64Ty = builder.getInt64Ty(); ptrTy = builder.getPtrTy(0); voidTy = builder.getVoidTy(); intPtrTy = builder.getIntPtrTy(module.getDataLayout()); @@ -224,11 +226,11 @@ llvm::LaunchKernel::LaunchKernel( llvm::FunctionCallee llvm::LaunchKernel::getKernelLaunchFn() { return module.getOrInsertFunction( "mgpuLaunchKernel", - FunctionType::get( - voidTy, - ArrayRef({ptrTy, intPtrTy, intPtrTy, intPtrTy, intPtrTy, - intPtrTy, intPtrTy, i32Ty, ptrTy, ptrTy, ptrTy}), - false)); + FunctionType::get(voidTy, + ArrayRef({ptrTy, intPtrTy, intPtrTy, intPtrTy, + intPtrTy, intPtrTy, intPtrTy, i32Ty, + ptrTy, ptrTy, ptrTy, i64Ty}), + false)); } llvm::FunctionCallee llvm::LaunchKernel::getClusterKernelLaunchFn() { @@ -251,7 +253,7 @@ llvm::FunctionCallee llvm::LaunchKernel::getModuleFunctionFn() { llvm::FunctionCallee llvm::LaunchKernel::getModuleLoadFn() { return module.getOrInsertFunction( "mgpuModuleLoad", - FunctionType::get(ptrTy, ArrayRef({ptrTy}), false)); + FunctionType::get(ptrTy, ArrayRef({ptrTy, i64Ty}), false)); } llvm::FunctionCallee llvm::LaunchKernel::getModuleLoadJITFn() { @@ -391,10 +393,24 @@ llvm::LaunchKernel::createKernelLaunch(mlir::gpu::LaunchFuncOp op, if (!binary) return op.emitError() << "Couldn't find the binary: " << binaryIdentifier; + auto binaryVar = dyn_cast(binary); + if (!binaryVar) + return op.emitError() << "Binary is not a global variable: " + << binaryIdentifier; + llvm::Constant *binaryInit = binaryVar->getInitializer(); + auto binaryDataSeq = + dyn_cast_if_present(binaryInit); + if (!binaryDataSeq) + return op.emitError() << "Couldn't find binary data array: " + << binaryIdentifier; + llvm::Constant *binarySize = + llvm::ConstantInt::get(i64Ty, binaryDataSeq->getNumElements() * + binaryDataSeq->getElementByteSize()); + Value *moduleObject = object.getFormat() == gpu::CompilationTarget::Assembly ? builder.CreateCall(getModuleLoadJITFn(), {binary, optV}) - : builder.CreateCall(getModuleLoadFn(), {binary}); + : builder.CreateCall(getModuleLoadFn(), {binary, binarySize}); // Load the kernel function. Value *moduleFunction = builder.CreateCall( @@ -413,6 +429,9 @@ llvm::LaunchKernel::createKernelLaunch(mlir::gpu::LaunchFuncOp op, stream = builder.CreateCall(getStreamCreateFn(), {}); } + llvm::Constant *paramsCount = + llvm::ConstantInt::get(i64Ty, op.getNumKernelOperands()); + // Create the launch call. Value *nullPtr = ConstantPointerNull::get(ptrTy); @@ -426,10 +445,10 @@ llvm::LaunchKernel::createKernelLaunch(mlir::gpu::LaunchFuncOp op, ArrayRef({moduleFunction, cx, cy, cz, gx, gy, gz, bx, by, bz, dynamicMemorySize, stream, argArray, nullPtr})); } else { - builder.CreateCall( - getKernelLaunchFn(), - ArrayRef({moduleFunction, gx, gy, gz, bx, by, bz, - dynamicMemorySize, stream, argArray, nullPtr})); + builder.CreateCall(getKernelLaunchFn(), + ArrayRef({moduleFunction, gx, gy, gz, bx, by, + bz, dynamicMemorySize, stream, + argArray, nullPtr, paramsCount})); } // Sync & destroy the stream, for synchronous launches. diff --git a/mlir/lib/Target/LLVMIR/Dialect/SPIRV/CMakeLists.txt b/mlir/lib/Target/LLVMIR/Dialect/SPIRV/CMakeLists.txt new file mode 100644 index 000000000000..850b95b8ddc7 --- /dev/null +++ b/mlir/lib/Target/LLVMIR/Dialect/SPIRV/CMakeLists.txt @@ -0,0 +1,13 @@ +add_mlir_translation_library(MLIRSPIRVToLLVMIRTranslation + SPIRVToLLVMIRTranslation.cpp + + LINK_COMPONENTS + Core + + LINK_LIBS PUBLIC + MLIRIR + MLIRLLVMDialect + MLIRSPIRVDialect + MLIRSupport + MLIRTargetLLVMIRExport + ) diff --git a/mlir/lib/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.cpp new file mode 100644 index 000000000000..638edca5efde --- /dev/null +++ b/mlir/lib/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.cpp @@ -0,0 +1,31 @@ +//===- SPIRVToLLVMIRTranslation.cpp - Translate SPIR-V to LLVM IR ---------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements a translation between the MLIR SPIR-V dialect and +// LLVM IR. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Target/LLVMIR/Dialect/SPIRV/SPIRVToLLVMIRTranslation.h" +#include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h" +#include "mlir/IR/BuiltinAttributes.h" +#include "mlir/IR/Operation.h" +#include "mlir/Target/LLVMIR/ModuleTranslation.h" + +using namespace mlir; +using namespace mlir::LLVM; + +void mlir::registerSPIRVDialectTranslation(DialectRegistry ®istry) { + registry.insert(); +} + +void mlir::registerSPIRVDialectTranslation(MLIRContext &context) { + DialectRegistry registry; + registerSPIRVDialectTranslation(registry); + context.appendDialectRegistry(registry); +} diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp index 2d1aaa9229cd..4bdffa572e31 100644 --- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp @@ -1626,6 +1626,8 @@ static constexpr std::array ExplicitAttributes{ StringLiteral("aarch64_pstate_sm_body"), StringLiteral("aarch64_pstate_za_new"), StringLiteral("vscale_range"), + StringLiteral("frame-pointer"), + StringLiteral("target-features"), }; static void processPassthroughAttrs(llvm::Function *func, LLVMFuncOp funcOp) { @@ -1706,6 +1708,22 @@ void ModuleImport::processFunctionAttributes(llvm::Function *func, context, IntegerAttr::get(intTy, attr.getVScaleRangeMin()), IntegerAttr::get(intTy, attr.getVScaleRangeMax().value_or(0)))); } + + // Process frame-pointer attribute. + if (func->hasFnAttribute("frame-pointer")) { + StringRef stringRefFramePointerKind = + func->getFnAttribute("frame-pointer").getValueAsString(); + funcOp.setFramePointerAttr(LLVM::FramePointerKindAttr::get( + funcOp.getContext(), LLVM::framePointerKind::symbolizeFramePointerKind( + stringRefFramePointerKind) + .value())); + } + + if (llvm::Attribute attr = func->getFnAttribute("target-features"); + attr.isStringAttribute()) { + funcOp.setTargetFeaturesAttr( + LLVM::TargetFeaturesAttr::get(context, attr.getValueAsString())); + } } DictionaryAttr diff --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp index 836f23b23862..d6afe354178d 100644 --- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp @@ -968,11 +968,20 @@ LogicalResult ModuleTranslation::convertOneFunction(LLVMFuncOp func) { if (func.getArmNewZa()) llvmFunc->addFnAttr("aarch64_pstate_za_new"); + if (auto targetFeatures = func.getTargetFeatures()) + llvmFunc->addFnAttr("target-features", targetFeatures->getFeaturesString()); + if (auto attr = func.getVscaleRange()) llvmFunc->addFnAttr(llvm::Attribute::getWithVScaleRangeArgs( getLLVMContext(), attr->getMinRange().getInt(), attr->getMaxRange().getInt())); + // Add function attribute frame-pointer, if found. + if (FramePointerKindAttr attr = func.getFramePointerAttr()) + llvmFunc->addFnAttr("frame-pointer", + LLVM::framePointerKind::stringifyFramePointerKind( + (attr.getFramePointerKind()))); + // First, create all blocks so we can jump to them. llvm::LLVMContext &llvmContext = llvmFunc->getContext(); for (auto &bb : func) { diff --git a/mlir/python/mlir/_mlir_libs/__init__.py b/mlir/python/mlir/_mlir_libs/__init__.py index 32f46d24cc73..98dbbc6adf9c 100644 --- a/mlir/python/mlir/_mlir_libs/__init__.py +++ b/mlir/python/mlir/_mlir_libs/__init__.py @@ -94,6 +94,7 @@ def _site_initialize(): "encountered otherwise and the MLIR Python API may not function." ) logger.warning(message, exc_info=True) + return False logger.debug("Initializing MLIR with module: %s", module_name) if hasattr(m, "register_dialects"): diff --git a/mlir/python/mlir/dialects/affine.py b/mlir/python/mlir/dialects/affine.py index 80d3873e19a0..26e827009bc0 100644 --- a/mlir/python/mlir/dialects/affine.py +++ b/mlir/python/mlir/dialects/affine.py @@ -3,3 +3,141 @@ # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception from ._affine_ops_gen import * +from ._affine_ops_gen import _Dialect, AffineForOp +from .arith import constant + +try: + from ..ir import * + from ._ods_common import ( + get_op_result_or_value as _get_op_result_or_value, + get_op_results_or_values as _get_op_results_or_values, + _cext as _ods_cext, + ) +except ImportError as e: + raise RuntimeError("Error loading imports from extension module") from e + +from typing import Optional, Sequence, Union + + +@_ods_cext.register_operation(_Dialect, replace=True) +class AffineForOp(AffineForOp): + """Specialization for the Affine for op class""" + + def __init__( + self, + lower_bound, + upper_bound, + step, + iter_args: Optional[Union[Operation, OpView, Sequence[Value]]] = None, + *, + lower_bound_operands=[], + upper_bound_operands=[], + loc=None, + ip=None, + ): + """Creates an Affine `for` operation. + + - `lower_bound` is the affine map to use as lower bound of the loop. + - `upper_bound` is the affine map to use as upper bound of the loop. + - `step` is the value to use as loop step. + - `iter_args` is a list of additional loop-carried arguments or an operation + producing them as results. + - `lower_bound_operands` is the list of arguments to substitute the dimensions, + then symbols in the `lower_bound` affine map, in an increasing order + - `upper_bound_operands` is the list of arguments to substitute the dimensions, + then symbols in the `upper_bound` affine map, in an increasing order + """ + + if iter_args is None: + iter_args = [] + iter_args = _get_op_results_or_values(iter_args) + if len(lower_bound_operands) != lower_bound.n_inputs: + raise ValueError( + f"Wrong number of lower bound operands passed to AffineForOp. " + + "Expected {lower_bound.n_symbols}, got {len(lower_bound_operands)}." + ) + + if len(upper_bound_operands) != upper_bound.n_inputs: + raise ValueError( + f"Wrong number of upper bound operands passed to AffineForOp. " + + "Expected {upper_bound.n_symbols}, got {len(upper_bound_operands)}." + ) + + results = [arg.type for arg in iter_args] + super().__init__( + results_=results, + lowerBoundOperands=_get_op_results_or_values(lower_bound_operands), + upperBoundOperands=_get_op_results_or_values(upper_bound_operands), + inits=list(iter_args), + lowerBoundMap=AffineMapAttr.get(lower_bound), + upperBoundMap=AffineMapAttr.get(upper_bound), + step=IntegerAttr.get(IndexType.get(), step), + loc=loc, + ip=ip, + ) + self.regions[0].blocks.append(IndexType.get(), *results) + + @property + def body(self): + """Returns the body (block) of the loop.""" + return self.regions[0].blocks[0] + + @property + def induction_variable(self): + """Returns the induction variable of the loop.""" + return self.body.arguments[0] + + @property + def inner_iter_args(self): + """Returns the loop-carried arguments usable within the loop. + + To obtain the loop-carried operands, use `iter_args`. + """ + return self.body.arguments[1:] + + +def for_( + start, + stop=None, + step=None, + iter_args: Optional[Sequence[Value]] = None, + *, + loc=None, + ip=None, +): + if step is None: + step = 1 + if stop is None: + stop = start + start = 0 + params = [start, stop] + for i, p in enumerate(params): + if isinstance(p, int): + p = constant(IntegerAttr.get(IndexType.get(), p)) + elif isinstance(p, float): + raise ValueError(f"{p=} must be int.") + params[i] = p + + start, stop = params + s0 = AffineSymbolExpr.get(0) + lbmap = AffineMap.get(0, 1, [s0]) + ubmap = AffineMap.get(0, 1, [s0]) + for_op = AffineForOp( + lbmap, + ubmap, + step, + iter_args=iter_args, + lower_bound_operands=[start], + upper_bound_operands=[stop], + loc=loc, + ip=ip, + ) + iv = for_op.induction_variable + iter_args = tuple(for_op.inner_iter_args) + with InsertionPoint(for_op.body): + if len(iter_args) > 1: + yield iv, iter_args + elif len(iter_args) == 1: + yield iv, iter_args[0] + else: + yield iv diff --git a/mlir/test/CMakeLists.txt b/mlir/test/CMakeLists.txt index ccb4a98254cd..3f312164cb1f 100644 --- a/mlir/test/CMakeLists.txt +++ b/mlir/test/CMakeLists.txt @@ -142,6 +142,10 @@ if(MLIR_ENABLE_ROCM_RUNNER) list(APPEND MLIR_TEST_DEPENDS mlir_rocm_runtime) endif() +if(MLIR_ENABLE_SYCL_RUNNER) + list(APPEND MLIR_TEST_DEPENDS mlir_sycl_runtime) +endif() + if (MLIR_RUN_ARM_SME_TESTS AND NOT ARM_SME_ABI_ROUTINES_SHLIB) list(APPEND MLIR_TEST_DEPENDS mlir_arm_sme_abi_stubs) endif() diff --git a/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir b/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir index 6f614b113788..e16dbb566105 100644 --- a/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir +++ b/mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir @@ -330,6 +330,7 @@ func.func @fcmp(f32, f32) -> () { // CHECK-NEXT: llvm.fcmp "ule" %arg0, %arg1 : f32 // CHECK-NEXT: llvm.fcmp "une" %arg0, %arg1 : f32 // CHECK-NEXT: llvm.fcmp "uno" %arg0, %arg1 : f32 + // CHECK-NEXT: llvm.fcmp "oeq" %arg0, %arg1 {fastmathFlags = #llvm.fastmath} : f32 // CHECK-NEXT: return %1 = arith.cmpf oeq, %arg0, %arg1 : f32 %2 = arith.cmpf ogt, %arg0, %arg1 : f32 @@ -346,6 +347,8 @@ func.func @fcmp(f32, f32) -> () { %13 = arith.cmpf une, %arg0, %arg1 : f32 %14 = arith.cmpf uno, %arg0, %arg1 : f32 + %15 = arith.cmpf oeq, %arg0, %arg1 {fastmath = #arith.fastmath} : f32 + return } diff --git a/mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir b/mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir index efefc6c49e08..5d79a0405114 100644 --- a/mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir +++ b/mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir @@ -6,16 +6,17 @@ // CHECK-LABEL: func.func @arm_sme_tile_load_hor( // CHECK-SAME: %[[SRC:.*]]: memref) { -// CHECK-DAG: %[[TILE:.*]] = arm_sme.get_tile : vector<[4]x[4]xi32> +// CHECK-DAG: %[[INIT_TILE:.*]] = arm_sme.get_tile : vector<[4]x[4]xi32> // CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index // CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index // CHECK-DAG: %[[C4:.*]] = arith.constant 4 : index // CHECK-DAG: %[[VSCALE:.*]] = vector.vscale // CHECK-NEXT: %[[NUM_TILE_SLICES:.*]] = arith.muli %[[C4]], %[[VSCALE]] : index -// CHECK-NEXT: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] { +// CHECK-NEXT: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] iter_args(%[[CURRENT_TILE:.*]] = %[[INIT_TILE]]) -> (vector<[4]x[4]xi32>) { // CHECK-NEXT: %[[PTRUE_S:.*]] = arith.constant dense : vector<[4]xi1> // CHECK-NEXT: %[[OFFSET:.*]] = arith.addi %[[C0]], %[[TILE_SLICE_INDEX]] : index -// CHECK-NEXT: arm_sme.load_tile_slice %[[SRC]]{{\[}}%[[OFFSET]], %[[C0]]], %[[PTRUE_S]], %[[TILE]], %[[TILE_SLICE_INDEX]] : memref, vector<[4]xi1>, vector<[4]x[4]xi32> +// CHECK-NEXT: %[[TILE_UPDATE:.*]] = arm_sme.load_tile_slice %[[SRC]]{{\[}}%[[OFFSET]], %[[C0]]], %[[PTRUE_S]], %[[CURRENT_TILE]], %[[TILE_SLICE_INDEX]] : memref, vector<[4]xi1>, vector<[4]x[4]xi32> +// CHECK-NEXT: scf.yield %[[TILE_UPDATE]] : vector<[4]x[4]xi32> func.func @arm_sme_tile_load_hor(%src : memref) { %c0 = arith.constant 0 : index %tile = arm_sme.tile_load %src[%c0, %c0] : memref, vector<[4]x[4]xi32> @@ -40,10 +41,11 @@ func.func @arm_sme_tile_load_ver(%src : memref) { // CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index // CHECK-DAG: %[[NUM_ROWS:.*]] = arith.constant 3 : index // CHECK-DAG: %[[NUM_COLS:.*]] = vector.create_mask %c2 : vector<[4]xi1> -// CHECK-DAG: %[[TILEZERO:.*]] = arm_sme.zero : vector<[4]x[4]xi32> -// CHECK-NEXT: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_ROWS]] step %[[C1]] { +// CHECK-DAG: %[[TILE_ZERO:.*]] = arm_sme.zero : vector<[4]x[4]xi32> +// CHECK-NEXT: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_ROWS]] step %[[C1]] iter_args(%[[CURRENT_TILE:.*]] = %[[TILE_ZERO]]) -> (vector<[4]x[4]xi32>) { // CHECK-NEXT: %[[OFFSET:.*]] = arith.addi %[[C0]], %[[TILE_SLICE_INDEX]] : index -// CHECK-NEXT: arm_sme.load_tile_slice %[[SRC]]{{\[}}%[[OFFSET]], %[[C0]]], %[[NUM_COLS]], %[[TILEZERO]], %[[TILE_SLICE_INDEX]] : memref, vector<[4]xi1>, vector<[4]x[4]xi32> +// CHECK-NEXT: %[[TILE_UPDATE:.*]] = arm_sme.load_tile_slice %[[SRC]]{{\[}}%[[OFFSET]], %[[C0]]], %[[NUM_COLS]], %[[CURRENT_TILE]], %[[TILE_SLICE_INDEX]] : memref, vector<[4]xi1>, vector<[4]x[4]xi32> +// CHECK-NEXT: scf.yield %[[TILE_UPDATE]] : vector<[4]x[4]xi32> func.func @arm_sme_tile_load_hor_with_mask_and_pad_zero(%src : memref) { %c0 = arith.constant 0 : index %c2 = arith.constant 2 : index @@ -68,7 +70,7 @@ func.func @arm_sme_tile_load_hor_with_mask_and_pad_zero(%src : memref) // CHECK-DAG: %[[NUM_COLS_I32:.*]] = arith.index_castui %[[NUM_COLS]] : index to i32 // CHECK-DAG: %[[VSCALE:.*]] = vector.vscale // CHECK-NEXT: %[[NUM_TILE_SLICES:.*]] = arith.muli %[[C4]], %[[VSCALE]] : index -// CHECK-NEXT: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] { +// CHECK-NEXT: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] iter_args(%[[CURRENT_TILE:.*]] = %[[TILE]]) -> (vector<[4]x[4]xi32>) { // CHECK-NEXT: %[[ROW_IS_ACTIVE:.*]] = arith.cmpi ult, %[[TILE_SLICE_INDEX]], %[[NUM_ROWS]] : index // CHECK-NEXT: %[[ROW_IS_ACTIVE_SEXT_I32:.*]] = arith.extsi %[[ROW_IS_ACTIVE]] : i1 to i32 // CHECK-NEXT: %[[MASK:.*]] = arith.andi %[[ROW_IS_ACTIVE_SEXT_I32]], %[[NUM_COLS_I32]] : i32 @@ -77,7 +79,8 @@ func.func @arm_sme_tile_load_hor_with_mask_and_pad_zero(%src : memref) // CHECK-NEXT: %[[OFFSET:.*]] = arith.addi %[[C0]], %[[TILE_SLICE_INDEX]] : index // CHECK: %[[PAD_1D:.*]] = vector.splat %[[PAD]] : vector<[4]xi32> // CHECK: %[[LOAD_SLICE:.*]] = vector.maskedload %[[SRC]]{{\[}}%[[OFFSET]], %[[C0]]], %[[MASK_1D]], %[[PAD_1D]] : memref, vector<[4]xi1>, vector<[4]xi32> into vector<[4]xi32> -// CHECK: arm_sme.move_vector_to_tile_slice %[[LOAD_SLICE]], %[[TILE]], %[[TILE_SLICE_INDEX]] : vector<[4]xi32> into vector<[4]x[4]xi32> +// CHECK: %[[TILE_UPDATE:.*]] = arm_sme.move_vector_to_tile_slice %[[LOAD_SLICE]], %[[CURRENT_TILE]], %[[TILE_SLICE_INDEX]] : vector<[4]xi32> into vector<[4]x[4]xi32> +// CHECK-NEXT: scf.yield %[[TILE_UPDATE]] : vector<[4]x[4]xi32> func.func @arm_sme_tile_load_hor_with_mask_and_nonzero_pad(%src : memref, %pad : i32) { %c0 = arith.constant 0 : index %c2 = arith.constant 2 : index diff --git a/mlir/test/Conversion/GPUCommon/lower-memory-space-attrs.mlir b/mlir/test/Conversion/GPUCommon/lower-memory-space-attrs.mlir index 14f5302ac200..771f3185904b 100644 --- a/mlir/test/Conversion/GPUCommon/lower-memory-space-attrs.mlir +++ b/mlir/test/Conversion/GPUCommon/lower-memory-space-attrs.mlir @@ -46,3 +46,40 @@ gpu.module @kernel { // CHECK: [[value:%.+]] = llvm.load // CHECK-SAME: : !llvm.ptr<1> -> f32 // CHECK: llvm.return [[value]] + +// ----- + +gpu.module @kernel { + gpu.func @dynamic_shmem_with_vector(%arg1: memref<1xf32>) { + %0 = arith.constant 0 : index + %1 = gpu.dynamic_shared_memory : memref> + %2 = memref.view %1[%0][] : memref> to memref<1xf32, #gpu.address_space> + %3 = vector.load %2[%0] : memref<1xf32, #gpu.address_space>, vector<1xf32> + vector.store %3, %arg1[%0] : memref<1xf32>, vector<1xf32> + gpu.return + } +} + +// ROCDL: llvm.mlir.global internal @__dynamic_shmem__0() {addr_space = 3 : i32} : !llvm.array<0 x i8> +// NVVM: llvm.mlir.global internal @__dynamic_shmem__0() {addr_space = 3 : i32, alignment = 16 : i64} : !llvm.array<0 x i8> +// CHECK-LABEL: llvm.func @dynamic_shmem_with_vector +// CHECK: llvm.mlir.addressof @__dynamic_shmem__0 : !llvm.ptr<3> +// CHECK: llvm.load %{{.*}} {alignment = 4 : i64} : !llvm.ptr<3> -> vector<1xf32> +// CHECK: llvm.store + +// ----- + +gpu.module @kernel { + gpu.func @dynamic_shmem(%arg0: f32) { + %0 = arith.constant 0 : index + %1 = gpu.dynamic_shared_memory : memref> + %2 = memref.view %1[%0][] : memref> to memref<4xf32, #gpu.address_space> + memref.store %arg0, %2[%0] : memref<4xf32, #gpu.address_space> + gpu.return + } +} + +// CHECK-LABEL: llvm.func @dynamic_shmem +// CHECK: llvm.store +// CHECK-SAME: : f32, !llvm.ptr<3> + diff --git a/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir b/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir index 4d2d15284589..43de50f3dc8d 100644 --- a/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir +++ b/mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir @@ -642,6 +642,15 @@ func.func @cp_bulk_commit() { nvvm.cp.async.bulk.commit.group func.return } + + +// ----- + +func.func @fence_mbarrier_init() { + //CHECK: llvm.inline_asm has_side_effects asm_dialect = att "fence.mbarrier_init.release.cluster;" + nvvm.fence.mbarrier.init + func.return +} // ----- func.func @fence_proxy() { diff --git a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir index e7db61a78883..aedc6b7fae4a 100644 --- a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir +++ b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir @@ -1,7 +1,7 @@ // RUN: mlir-opt --split-input-file -pass-pipeline="builtin.module(func.func(tosa-to-linalg))" %s -o -| FileCheck %s -// CHECK-LABEL: @unary_resize_nearest_fp -func.func @unary_resize_nearest_fp(%arg0 : tensor<3x1x1x7xf32>) -> tensor<3x1x1x7xf32> { +// CHECK-LABEL: @unary_resize_nearest_fp32 +func.func @unary_resize_nearest_fp32(%arg0 : tensor<3x1x1x7xf32>) -> tensor<3x1x1x7xf32> { %resize = "tosa.resize"(%arg0) {mode = "NEAREST_NEIGHBOR", scale = array, offset = array, border = array} : (tensor<3x1x1x7xf32>) -> tensor<3x1x1x7xf32> // CHECK: return %arg0 return %resize : tensor<3x1x1x7xf32> @@ -9,8 +9,17 @@ func.func @unary_resize_nearest_fp(%arg0 : tensor<3x1x1x7xf32>) -> tensor<3x1x1x // ----- -// CHECK-LABEL: @unary_resize_bilinear_fp -func.func @unary_resize_bilinear_fp(%arg0 : tensor<3x1x1x7xf32>) -> tensor<3x1x1x7xf32> { +// CHECK-LABEL: @unary_resize_nearest_fp16 +func.func @unary_resize_nearest_fp16(%arg0 : tensor<3x1x1x7xf16>) -> tensor<3x1x1x7xf16> { + %resize = "tosa.resize"(%arg0) {mode = "NEAREST_NEIGHBOR", scale = array, offset = array, border = array} : (tensor<3x1x1x7xf16>) -> tensor<3x1x1x7xf16> + // CHECK: return %arg0 + return %resize : tensor<3x1x1x7xf16> +} + +// ----- + +// CHECK-LABEL: @unary_resize_bilinear_fp32 +func.func @unary_resize_bilinear_fp32(%arg0 : tensor<3x1x1x7xf32>) -> tensor<3x1x1x7xf32> { %resize = "tosa.resize"(%arg0) {mode = "BILINEAR", scale = array, offset = array, border = array} : (tensor<3x1x1x7xf32>) -> tensor<3x1x1x7xf32> // CHECK: return %arg0 return %resize : tensor<3x1x1x7xf32> @@ -18,6 +27,15 @@ func.func @unary_resize_bilinear_fp(%arg0 : tensor<3x1x1x7xf32>) -> tensor<3x1x1 // ----- +// CHECK-LABEL: @unary_resize_bilinear_fp16 +func.func @unary_resize_bilinear_fp16(%arg0 : tensor<3x1x1x7xf16>) -> tensor<3x1x1x7xf16> { + %resize = "tosa.resize"(%arg0) {mode = "BILINEAR", scale = array, offset = array, border = array} : (tensor<3x1x1x7xf16>) -> tensor<3x1x1x7xf16> + // CHECK: return %arg0 + return %resize : tensor<3x1x1x7xf16> +} + +// ----- + // CHECK-LABEL: @unary_resize_nearest_i8 func.func @unary_resize_nearest_i8(%arg0 : tensor<3x1x1x7xi8>) -> tensor<3x1x1x7xi8> { %resize = "tosa.resize"(%arg0) {mode = "NEAREST_NEIGHBOR", scale = array, offset = array, border = array} : (tensor<3x1x1x7xi8>) -> tensor<3x1x1x7xi8> @@ -285,8 +303,8 @@ func.func @resize_bilinear_int(%arg0: tensor<1x19x20x1xi8>) { // ----- -// CHECK-LABEL: @resize_nearest_fp -func.func @resize_nearest_fp(%input: tensor<1x50x48x1xf32>) -> () { +// CHECK-LABEL: @resize_nearest_fp32 +func.func @resize_nearest_fp32(%input: tensor<1x50x48x1xf32>) -> () { // CHECK: %[[INIT:.+]] = tensor.empty() : tensor<1x1600x1536x1xf32> // CHECK: %[[GENERIC:.+]] = linalg.generic // CHECK: %[[IDX0:.+]] = linalg.index 0 diff --git a/mlir/test/Dialect/Arith/ops.mlir b/mlir/test/Dialect/Arith/ops.mlir index 88cc0072c7c5..6e10e540d1d1 100644 --- a/mlir/test/Dialect/Arith/ops.mlir +++ b/mlir/test/Dialect/Arith/ops.mlir @@ -1118,6 +1118,8 @@ func.func @fastmath(%arg0: f32, %arg1: f32, %arg2: i32) { %7 = arith.addf %arg0, %arg1 fastmath : f32 // CHECK: {{.*}} = arith.mulf %arg0, %arg1 fastmath : f32 %8 = arith.mulf %arg0, %arg1 fastmath : f32 +// CHECK: {{.*}} = arith.cmpf oeq, %arg0, %arg1 fastmath : f32 + %9 = arith.cmpf oeq, %arg0, %arg1 fastmath : f32 return } diff --git a/mlir/test/Dialect/ArmSME/arith-ops-to-sme.mlir b/mlir/test/Dialect/ArmSME/arith-ops-to-sme.mlir index b8db105f9c60..ae2d0f40f03a 100644 --- a/mlir/test/Dialect/ArmSME/arith-ops-to-sme.mlir +++ b/mlir/test/Dialect/ArmSME/arith-ops-to-sme.mlir @@ -95,11 +95,12 @@ func.func @arith_constant_dense_2d_zero_f64() { // CHECK: %[[C1:.*]] = arith.constant 1 : index // CHECK: %[[C16:.*]] = arith.constant 16 : index // CHECK: %[[C0:.*]] = arith.constant 0 : index -// CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[16]x[16]xi8> +// CHECK: %[[INIT_TILE:.*]] = arm_sme.get_tile : vector<[16]x[16]xi8> // CHECK: %[[VSCALE:.*]] = vector.vscale // CHECK: %[[NUM_TILE_SLICES:.*]] = arith.muli %[[VSCALE]], %[[C16]] : index -// CHECK: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] { -// CHECK: arm_sme.move_vector_to_tile_slice %[[C2_SPLAT]], %[[TILE]], %[[TILE_SLICE_INDEX]] : vector<[16]xi8> into vector<[16]x[16]xi8> +// CHECK: %[[TILE:.*]] = scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] iter_args(%[[CURRENT_TILE:.*]] = %[[INIT_TILE]]) -> (vector<[16]x[16]xi8>) { +// CHECK: %[[TILE_UPDATE:.*]] = arm_sme.move_vector_to_tile_slice %[[C2_SPLAT]], %[[CURRENT_TILE]], %[[TILE_SLICE_INDEX]] : vector<[16]xi8> into vector<[16]x[16]xi8> +// CHECK: scf.yield %[[TILE_UPDATE]] : vector<[16]x[16]xi8> // CHECK: "prevent.dce"(%[[TILE]]) : (vector<[16]x[16]xi8>) -> () func.func @arith_constant_dense_2d_nonzero_i8() { %two = arith.constant dense<2> : vector<[16]x[16]xi8> @@ -114,11 +115,12 @@ func.func @arith_constant_dense_2d_nonzero_i8() { // CHECK: %[[C1:.*]] = arith.constant 1 : index // CHECK: %[[C2:.*]] = arith.constant 2 : index // CHECK: %[[C0:.*]] = arith.constant 0 : index -// CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[2]x[2]xf64> +// CHECK: %[[INIT_TILE:.*]] = arm_sme.get_tile : vector<[2]x[2]xf64> // CHECK: %[[VSCALE:.*]] = vector.vscale // CHECK: %[[NUM_TILE_SLICES:.*]] = arith.muli %[[VSCALE]], %[[C2]] : index -// CHECK: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] { -// CHECK: arm_sme.move_vector_to_tile_slice %[[C2_SPLAT]], %[[TILE]], %[[TILE_SLICE_INDEX]] : vector<[2]xf64> into vector<[2]x[2]xf64> +// CHECK: %[[TILE:.*]] = scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] iter_args(%[[CURRENT_TILE:.*]] = %[[INIT_TILE]]) -> (vector<[2]x[2]xf64>) { +// CHECK: %[[TILE_UPDATE:.*]] = arm_sme.move_vector_to_tile_slice %[[C2_SPLAT]], %[[CURRENT_TILE]], %[[TILE_SLICE_INDEX]] : vector<[2]xf64> into vector<[2]x[2]xf64> +// CHECK: scf.yield %[[TILE_UPDATE]] : vector<[2]x[2]xf64> // CHECK: "prevent.dce"(%[[TILE]]) : (vector<[2]x[2]xf64>) -> () func.func @arith_constant_dense_2d_nonzero_f64() { %two = arith.constant dense<2.0> : vector<[2]x[2]xf64> diff --git a/mlir/test/Dialect/ArmSME/vector-ops-to-sme.mlir b/mlir/test/Dialect/ArmSME/vector-ops-to-sme.mlir index 5bc147c60f3a..6ea949d9c165 100644 --- a/mlir/test/Dialect/ArmSME/vector-ops-to-sme.mlir +++ b/mlir/test/Dialect/ArmSME/vector-ops-to-sme.mlir @@ -452,11 +452,12 @@ func.func @transfer_write_2d__out_of_bounds(%vector : vector<[4]x[4]xf32>, %dest // CHECK: %[[C4:.*]] = arith.constant 4 : index // CHECK: %[[C0:.*]] = arith.constant 0 : index // CHECK: %[[SRC_1D:.*]] = vector.broadcast %[[SRC]] : i32 to vector<[4]xi32> -// CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[4]x[4]xi32> +// CHECK: %[[INIT_TILE:.*]] = arm_sme.get_tile : vector<[4]x[4]xi32> // CHECK: %[[VSCALE:.*]] = vector.vscale // CHECK: %[[NUM_TILE_SLICES:.*]] = arith.muli %[[VSCALE]], %[[C4]] : index -// CHECK: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] { -// CHECK: %[[C10:.*]] = arm_sme.move_vector_to_tile_slice %[[SRC_1D]], %[[TILE]], %[[TILE_SLICE_INDEX]] : vector<[4]xi32> into vector<[4]x[4]xi32> +// CHECK: %[[TILE:.*]] = scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] iter_args(%[[CURRENT_TILE:.*]] = %[[INIT_TILE]]) -> (vector<[4]x[4]xi32>) { +// CHECK: %[[NEW_TILE:.*]] = arm_sme.move_vector_to_tile_slice %[[SRC_1D]], %[[CURRENT_TILE]], %[[TILE_SLICE_INDEX]] : vector<[4]xi32> into vector<[4]x[4]xi32> +// CHECK: scf.yield %[[NEW_TILE]] : vector<[4]x[4]xi32> // CHECK: "prevent.dce"(%[[TILE]]) : (vector<[4]x[4]xi32>) -> () func.func @broadcast_vec2d_from_i32(%arg0: i32) { %0 = vector.broadcast %arg0 : i32 to vector<[4]x[4]xi32> diff --git a/mlir/test/Dialect/Complex/invalid.mlir b/mlir/test/Dialect/Complex/invalid.mlir index 51b1b0fda202..ba6995b727bc 100644 --- a/mlir/test/Dialect/Complex/invalid.mlir +++ b/mlir/test/Dialect/Complex/invalid.mlir @@ -25,7 +25,7 @@ func.func @complex_constant_two_different_element_types() { // ----- func.func @complex_bitcast_i64(%arg0 : i64) { - // expected-error @+1 {{op requires input or output is a complex type}} + // expected-error @+1 {{op requires that either input or output has a complex type}} %0 = complex.bitcast %arg0: i64 to f64 return } diff --git a/mlir/test/Dialect/LLVMIR/func.mlir b/mlir/test/Dialect/LLVMIR/func.mlir index 63e20b1d8fc3..d09df0767612 100644 --- a/mlir/test/Dialect/LLVMIR/func.mlir +++ b/mlir/test/Dialect/LLVMIR/func.mlir @@ -249,6 +249,12 @@ module { // CHECK-SAME: vscale_range(1, 2) llvm.return } + + // CHECK-LABEL: @frame_pointer_roundtrip() + // CHECK-SAME: attributes {frame_pointer = #llvm.framePointerKind<"non-leaf">} + llvm.func @frame_pointer_roundtrip() attributes {frame_pointer = #llvm.framePointerKind<"non-leaf">} { + llvm.return + } } // ----- diff --git a/mlir/test/Dialect/LLVMIR/roundtrip.mlir b/mlir/test/Dialect/LLVMIR/roundtrip.mlir index ee724a482cfb..42589972ef2b 100644 --- a/mlir/test/Dialect/LLVMIR/roundtrip.mlir +++ b/mlir/test/Dialect/LLVMIR/roundtrip.mlir @@ -73,11 +73,15 @@ func.func @ops(%arg0: i32, %arg1: f32, // Variadic calls // CHECK: llvm.call @vararg_func(%arg0, %arg0) vararg(!llvm.func) : (i32, i32) -> () +// CHECK: llvm.call @vararg_func(%arg0, %arg0) vararg(!llvm.func) {fastmathFlags = #llvm.fastmath} : (i32, i32) -> () // CHECK: %[[VARIADIC_FUNC:.*]] = llvm.mlir.addressof @vararg_func : !llvm.ptr // CHECK: llvm.call %[[VARIADIC_FUNC]](%[[I32]], %[[I32]]) vararg(!llvm.func) : !llvm.ptr, (i32, i32) -> () +// CHECK: llvm.call %[[VARIADIC_FUNC]](%[[I32]], %[[I32]]) vararg(!llvm.func) {fastmathFlags = #llvm.fastmath} : !llvm.ptr, (i32, i32) -> () llvm.call @vararg_func(%arg0, %arg0) vararg(!llvm.func) : (i32, i32) -> () + llvm.call @vararg_func(%arg0, %arg0) vararg(!llvm.func) {fastmathFlags = #llvm.fastmath} : (i32, i32) -> () %variadic_func = llvm.mlir.addressof @vararg_func : !llvm.ptr llvm.call %variadic_func(%arg0, %arg0) vararg(!llvm.func) : !llvm.ptr, (i32, i32) -> () + llvm.call %variadic_func(%arg0, %arg0) vararg(!llvm.func) {fastmathFlags = #llvm.fastmath} : !llvm.ptr, (i32, i32) -> () // Terminator operations and their successors. // diff --git a/mlir/test/Dialect/Linalg/transform-ops.mlir b/mlir/test/Dialect/Linalg/transform-ops.mlir index e9f044be5b4e..6b276e69a595 100644 --- a/mlir/test/Dialect/Linalg/transform-ops.mlir +++ b/mlir/test/Dialect/Linalg/transform-ops.mlir @@ -6,6 +6,16 @@ transform.sequence failures(propagate) { %0, %1:2 = transform.structured.tile_using_for %arg0 [2, 0, 3] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) } +// check that the Attributes of `tile_using_for` are preserved through printing +// and parsing with and without use of the optional `interchange` Attribute. +transform.sequence failures(propagate) { +^bb1(%arg0: !transform.any_op): + // CHECK %{{.*}}, %{{.*}}:2 = transform.structured.tile %arg0 [2, 0, 3] interchange = [2, 1] {test_attr1 = 1 : i64, test_attr2} + %0, %1:2 = transform.structured.tile_using_for %arg0 [2, 0, 3] interchange = [2, 1] {test_attr1 = 1 : i64, test_attr2}: (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + // CHECK %{{.*}}, %{{.*}}:2 = transform.structured.tile %arg0 [4, 5, 3] {test_attr3 = 1 : i64, test_attr4} + %2, %3:2 = transform.structured.tile_using_for %0 [0, 5, 3] {test_attr3 = 1 : i64, test_attr4}: (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) +} + transform.sequence failures(propagate) { ^bb1(%arg0: !transform.any_op): %0:2 = transform.structured.split %arg0 after 42 { dimension = 0 } : !transform.any_op diff --git a/mlir/test/Dialect/Linalg/transform-patterns.mlir b/mlir/test/Dialect/Linalg/transform-patterns.mlir index 77ce4d0b211f..5a9b490c07ff 100644 --- a/mlir/test/Dialect/Linalg/transform-patterns.mlir +++ b/mlir/test/Dialect/Linalg/transform-patterns.mlir @@ -170,7 +170,7 @@ func.func @matvec_perm(%A: memref>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matvec"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:2 = transform.structured.tile_using_for %0 [5, 6] {interchange = [1, 0]} : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:2 = transform.structured.tile_using_for %0 [5, 6] interchange = [1, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op) transform.yield } } @@ -199,8 +199,8 @@ func.func @matmul_perm(%A: memref>, module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { %0 = transform.structured.match ops{["linalg.matmul"]} in %arg1 : (!transform.any_op) -> !transform.any_op - %1, %loops:3 = transform.structured.tile_using_for %0 [2000, 3000, 4000] {interchange = [1, 2, 0]} : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) - %2, %loops_2:3 = transform.structured.tile_using_for %1 [200, 300, 400] {interchange = [1, 0, 2]} : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %1, %loops:3 = transform.structured.tile_using_for %0 [2000, 3000, 4000] interchange = [1, 2, 0] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) + %2, %loops_2:3 = transform.structured.tile_using_for %1 [200, 300, 400] interchange = [1, 0, 2] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) %3, %loops_3:3 = transform.structured.tile_using_for %2 [20, 30, 40] : (!transform.any_op) -> (!transform.any_op, !transform.any_op, !transform.any_op, !transform.any_op) transform.yield } diff --git a/mlir/test/Dialect/Linalg/vectorize-convolution-flatten.mlir b/mlir/test/Dialect/Linalg/vectorize-convolution-flatten.mlir new file mode 100644 index 000000000000..a242d0967182 --- /dev/null +++ b/mlir/test/Dialect/Linalg/vectorize-convolution-flatten.mlir @@ -0,0 +1,309 @@ +// RUN: mlir-opt -split-input-file -transform-interpreter %s | FileCheck %s + +func.func @depthwise_conv1d_nwc_wc_1x8x3xi8_tensor(%input: tensor<1x8x3xi8>, + %filter: tensor<1x3xi8>, + %output: tensor<1x8x3xi8>) -> (tensor<1x8x3xi8>) { + %res = linalg.depthwise_conv_1d_nwc_wc + {dilations = dense<1> : vector<1xi64>, + strides = dense<1> : vector<1xi64>} + ins(%input, %filter : tensor<1x8x3xi8>, tensor<1x3xi8>) + outs(%output : tensor<1x8x3xi8>) -> tensor<1x8x3xi8> + return %res : tensor<1x8x3xi8> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["linalg.depthwise_conv_1d_nwc_wc"]} in %arg0 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 {flatten_1d_depthwise_conv} : (!transform.any_op) -> !transform.any_op + transform.yield + } +} +// CHECK-LABEL: func.func @depthwise_conv1d_nwc_wc_1x8x3xi8_tensor +// CHECK-SAME: %[[INPUT:.*]]: tensor<1x8x3xi8>, +// CHECK-SAME: %[[FILTER:.*]]: tensor<1x3xi8>, +// CHECK-SAME: %[[OUTPUT:.*]]: tensor<1x8x3xi8>) -> tensor<1x8x3xi8> { + +// CHECK-DAG: %[[C0_IDX:.*]] = arith.constant 0 : index + +/// Read the whole data in one shot. +// CHECK: %[[V_INPUT_R:.*]] = vector.transfer_read %[[INPUT]][%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] +// CHECK: %[[V_FILTER_R:.*]] = vector.transfer_read %[[FILTER]][%[[C0_IDX]], %[[C0_IDX]]] +// CHECK: %[[V_OUTPUT_R:.*]] = vector.transfer_read %[[OUTPUT]][%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] + +// CHECK: %[[V_FILTER_0:.*]] = vector.extract %[[V_FILTER_R]][0] : vector<3xi8> from vector<1x3xi8> + +/// w == 0, kw = 0 +// CHECK: %[[SC_INPUT:.*]] = vector.shape_cast %[[V_INPUT_R]] : vector<1x8x3xi8> to vector<1x24xi8> +// CHECK: %[[SC_OUTPUT:.*]] = vector.shape_cast %[[V_OUTPUT_R]] : vector<1x8x3xi8> to vector<1x24xi8> +// CHECK: %[[B_FILTER:.*]] = vector.broadcast %[[V_FILTER_0]] : vector<3xi8> to vector<1x8x3xi8> +// CHECK: %[[SC_FILTER:.*]] = vector.shape_cast %[[B_FILTER]] : vector<1x8x3xi8> to vector<1x24xi8> +// CHECK: %[[MULI:.*]] = arith.muli %[[SC_INPUT]], %[[SC_FILTER]] : vector<1x24xi8> +// CHECK: %[[ADDI:.*]] = arith.addi %[[MULI]], %[[SC_OUTPUT]] : vector<1x24xi8> + +// Write the result back in one shot. +// CHECK: %[[SC_ADDI:.*]] = vector.shape_cast %[[ADDI]] : vector<1x24xi8> to vector<1x8x3xi8> +// CHECK: vector.transfer_write %[[SC_ADDI]], %[[OUTPUT]][%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] + +//------ + +func.func @depthwise_conv1d_nwc_wc_3x5x4xf32_memref_dillation_2(%input: memref<3x5x4xf32>, + %filter: memref<2x4xf32>, + %output: memref<3x2x4xf32>) { + linalg.depthwise_conv_1d_nwc_wc + {dilations = dense<2> : tensor<1xi64>, strides = dense<1> : tensor<1xi64>} + ins(%input, %filter : memref<3x5x4xf32>, memref<2x4xf32>) + outs(%output : memref<3x2x4xf32>) + return +} + +// CHECK: func @depthwise_conv1d_nwc_wc_3x5x4xf32_memref_dillation_2 +// CHECK-SAME: (%[[INPUT:[0-9a-z]+]]: memref<3x5x4xf32>, %[[FILTER:[0-9a-z]+]]: memref<2x4xf32>, %[[OUTPUT:[0-9a-z]+]]: memref<3x2x4xf32>) + +// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index +// CHECK-DAG: %[[F0:.+]] = arith.constant 0.000000e+00 : f32 + +/// Read the whole data in one shot. +// CHECK-DAG: %[[V_INPUT_R:.+]] = vector.transfer_read %[[INPUT]][%[[C0]], %[[C0]], %[[C0]]] +// CHECK-DAG: %[[V_FILTER_R:.+]] = vector.transfer_read %[[FILTER]][%[[C0]], %[[C0]]] +// CHECK-DAG: %[[V_OUTPUT_R:.+]] = vector.transfer_read %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]] + +// CHECK: %[[V_INPUT_0:.+]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 0, 0], sizes = [3, 2, 4], strides = [1, 1, 1]} : vector<3x4x4xf32> to vector<3x2x4xf32> +// CHECK: %[[V_INPUT_1:.+]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 2, 0], sizes = [3, 2, 4], strides = [1, 1, 1]} : vector<3x4x4xf32> to vector<3x2x4xf32> + +// CHECK: %[[V_FILTER_0:.+]] = vector.extract %[[V_FILTER_R]][0] : vector<4xf32> from vector<2x4xf32> +// CHECK: %[[V_FILTER_1:.+]] = vector.extract %[[V_FILTER_R]][1] : vector<4xf32> from vector<2x4xf32> + + +/// w == 0, kw = 0 +// CHECK: %[[SC_V_INPUT_0:.*]] = vector.shape_cast %[[V_INPUT_0]] : vector<3x2x4xf32> to vector<3x8xf32> +// CHECK: %[[SC_V_OUTPUT_R:.*]] = vector.shape_cast %[[V_OUTPUT_R]] : vector<3x2x4xf32> to vector<3x8xf32> +// CHECK: %[[B_FILTER_0:.*]] = vector.broadcast %[[V_FILTER_0]] : vector<4xf32> to vector<3x2x4xf32> +// CHECK: %[[SC_B_FILTER_0:.*]] = vector.shape_cast %[[B_FILTER_0]] : vector<3x2x4xf32> to vector<3x8xf32> +// CHECK: %[[FMA_0:.*]] = vector.fma %[[SC_V_INPUT_0]], %[[SC_B_FILTER_0]], %[[SC_V_OUTPUT_R]] : vector<3x8xf32> + +/// w == 0, kw = 1 +// CHECK: %[[SC_V_INPUT_1:.*]] = vector.shape_cast %[[V_INPUT_1]] : vector<3x2x4xf32> to vector<3x8xf32> +// CHECK: %[[B_V_FILTER_1:.*]] = vector.broadcast %[[V_FILTER_1]] : vector<4xf32> to vector<3x2x4xf32> +// CHECK: %[[SC_B_FILTER_1:.*]] = vector.shape_cast %[[B_V_FILTER_1]] : vector<3x2x4xf32> to vector<3x8xf32> +// CHECK: %[[FMA_1:.*]] = vector.fma %[[SC_V_INPUT_1]], %[[SC_B_FILTER_1]], %[[FMA_0]] : vector<3x8xf32> + +// Write the result back in one shot. +// CHECK: %[[SC_FMA_1:.*]] = vector.shape_cast %[[FMA_1]] : vector<3x8xf32> to vector<3x2x4xf32> +// CHECK: vector.transfer_write %[[SC_FMA_1]], %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]] + + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["linalg.depthwise_conv_1d_nwc_wc"]} in %arg0 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 {flatten_1d_depthwise_conv} : (!transform.any_op) -> !transform.any_op + transform.yield + } +} + +// ----- + +func.func @depthwise_conv1d_nwc_wc_3x5x4xi8_memref_dilation_2(%input: memref<3x5x4xi8>, + %filter: memref<2x4xi8>, + %output: memref<3x2x4xi32>) { + linalg.depthwise_conv_1d_nwc_wc + {dilations = dense<2> : tensor<1xi64>, strides = dense<1> : tensor<1xi64>} + ins(%input, %filter : memref<3x5x4xi8>, memref<2x4xi8>) + outs(%output : memref<3x2x4xi32>) + return +} + +// CHECK: func @depthwise_conv1d_nwc_wc_3x5x4xi8_memref_dilation_2 +// CHECK-SAME: (%[[INPUT:[0-9a-z]+]]: memref<3x5x4xi8>, %[[FILTER:[0-9a-z]+]]: memref<2x4xi8>, %[[OUTPUT:[0-9a-z]+]]: memref<3x2x4xi32>) + +// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index + +/// Read the whole data in one shot. +// CHECK-DAG: %[[V_INPUT_R:.+]] = vector.transfer_read %[[INPUT]][%[[C0]], %[[C0]], %[[C0]]] +// CHECK-DAG: %[[V_FILTER_R:.+]] = vector.transfer_read %[[FILTER]][%[[C0]], %[[C0]]] +// CHECK-DAG: %[[V_OUTPUT_R:.+]] = vector.transfer_read %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]] + +// CHECK: %[[V_INPUT_0:.+]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 0, 0], sizes = [3, 2, 4], strides = [1, 1, 1]} : vector<3x4x4xi8> to vector<3x2x4xi8> +// CHECK: %[[V_INPUT_1:.+]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 2, 0], sizes = [3, 2, 4], strides = [1, 1, 1]} : vector<3x4x4xi8> to vector<3x2x4xi8> + +// CHECK: %[[V_FILTER_0:.+]] = vector.extract %[[V_FILTER_R]][0] : vector<4xi8> from vector<2x4xi8> +// CHECK: %[[V_FILTER_1:.+]] = vector.extract %[[V_FILTER_R]][1] : vector<4xi8> from vector<2x4xi8> + +/// w == 0, kw = 0 +// CHECK: %[[SC_V_INPUT_0:.*]] = vector.shape_cast %[[V_INPUT_0]] : vector<3x2x4xi8> to vector<3x8xi8> +// CHECK: %[[SC_V_OUTPUT_R:.*]] = vector.shape_cast %[[V_OUTPUT_R]] : vector<3x2x4xi32> to vector<3x8xi32> +// CHECK: %[[EXT_INPUT_0:.*]] = arith.extsi %[[SC_V_INPUT_0]] : vector<3x8xi8> to vector<3x8xi32> +// CHECK: %[[B_FILTER_0:.*]] = vector.broadcast %[[V_FILTER_0]] : vector<4xi8> to vector<3x2x4xi8> +// CHECK: %[[SC_B_FILTER_0:.*]] = vector.shape_cast %[[B_FILTER_0]] : vector<3x2x4xi8> to vector<3x8xi8> +// CHECK: %[[EXT_FILTER_0:.*]] = arith.extsi %[[SC_B_FILTER_0]] : vector<3x8xi8> to vector<3x8xi32> +// CHECK: %[[MUL_0:.*]] = arith.muli %[[EXT_INPUT_0]], %[[EXT_FILTER_0]] : vector<3x8xi32> +// CHECK: %[[ADD_0:.*]] = arith.addi %[[MUL_0]], %[[SC_V_OUTPUT_R]] : vector<3x8xi32> + +/// w == 0, kw = 1 +// CHECK: %[[SC_V_INPUT_1:.*]] = vector.shape_cast %[[V_INPUT_1]] : vector<3x2x4xi8> to vector<3x8xi8> +// CHECK: %[[EXT_INPUT_1:.*]] = arith.extsi %[[SC_V_INPUT_1]] : vector<3x8xi8> to vector<3x8xi32> +// CHECK: %[[B_FILTER_1:.*]] = vector.broadcast %[[V_FILTER_1]] : vector<4xi8> to vector<3x2x4xi8> +// CHECK: %[[SC_B_FILTER_1:.*]] = vector.shape_cast %[[B_FILTER_1]] : vector<3x2x4xi8> to vector<3x8xi8> +// CHECK: %[[EXT_FILTER_1:.*]] = arith.extsi %[[SC_B_FILTER_1]] : vector<3x8xi8> to vector<3x8xi32> +// CHECK: %[[MUL_1:.*]] = arith.muli %[[EXT_INPUT_1]], %[[EXT_FILTER_1]] : vector<3x8xi32> +// CHECK: %[[ADD_1:.*]] = arith.addi %[[MUL_1]], %[[ADD_0]] : vector<3x8xi32> + +// Write the result back in one shot. +// CHECK: %[[SC_ADD_1:.*]] = vector.shape_cast %[[ADD_1]] : vector<3x8xi32> to vector<3x2x4xi32> +// CHECK: vector.transfer_write %[[SC_ADD_1]], %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]] + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["linalg.depthwise_conv_1d_nwc_wc"]} in %arg0 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 {flatten_1d_depthwise_conv} : (!transform.any_op) -> !transform.any_op + transform.yield + } +} + +// ----- + +func.func @depthwise_conv1d_nwc_wc_3x9x4xi8_tensor_stride_2(%input: tensor<3x9x4xi8>, + %filter: tensor<3x4xi8>, + %output: tensor<3x3x4xi8>) -> tensor<3x3x4xi8> { + %res = linalg.depthwise_conv_1d_nwc_wc + {dilations = dense<1> : tensor<1xi64>, strides = dense<2> : tensor<1xi64>} + ins(%input, %filter : tensor<3x9x4xi8>, tensor<3x4xi8>) + outs(%output : tensor<3x3x4xi8>) -> tensor<3x3x4xi8> + return %res : tensor<3x3x4xi8> +} +// CHECK-LABEL: func.func @depthwise_conv1d_nwc_wc_3x9x4xi8_tensor_stride_2 +// CHECK-SAME: %[[INPUT:.*]]: tensor<3x9x4xi8>, +// CHECK-SAME: %[[FILTER:.*]]: tensor<3x4xi8>, +// CHECK-SAME: %[[OUTPUT:.*]]: tensor<3x3x4xi8>) -> tensor<3x3x4xi8> { + +// CHECK-DAG: %[[C0_IDX:.*]] = arith.constant 0 : index +// CHECK-DAG: %[[C0_I8:.*]] = arith.constant 0 : i8 + +/// Read the whole data in one shot. +// CHECK: %[[V_INPUT_R:.*]] = vector.transfer_read %[[INPUT]][%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]], %[[C0_I8]] +// CHECK: %[[V_FILTER_R:.*]] = vector.transfer_read %[[FILTER]][%[[C0_IDX]], %[[C0_IDX]]], %[[C0_I8]] +// CHECK: %[[V_OUTPUT_R:.*]] = vector.transfer_read %[[OUTPUT]][%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]], %[[C0_I8]] + +// CHECK: %[[V_INPUT_0:.*]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 0, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x7x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_INPUT_1:.*]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 2, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x7x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_INPUT_2:.*]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 4, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x7x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_INPUT_3:.*]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 1, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x7x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_INPUT_4:.*]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 3, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x7x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_INPUT_5:.*]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 5, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x7x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_INPUT_6:.*]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 2, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x7x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_INPUT_7:.*]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 4, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x7x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_INPUT_8:.*]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0, 6, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x7x4xi8> to vector<3x1x4xi8> + +// CHECK: %[[V_FILTER_0:.*]] = vector.extract %[[V_FILTER_R]][0] : vector<4xi8> from vector<3x4xi8> +// CHECK: %[[V_FILTER_1:.*]] = vector.extract %[[V_FILTER_R]][1] : vector<4xi8> from vector<3x4xi8> +// CHECK: %[[V_FILTER_2:.*]] = vector.extract %[[V_FILTER_R]][2] : vector<4xi8> from vector<3x4xi8> + +// CHECK: %[[V_OUTPUT_0:.*]] = vector.extract_strided_slice %[[V_OUTPUT_R]] +// CHECK-SAME: {offsets = [0, 0, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x3x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_OUTPUT_1:.*]] = vector.extract_strided_slice %[[V_OUTPUT_R]] +// CHECK-SAME: {offsets = [0, 1, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x3x4xi8> to vector<3x1x4xi8> +// CHECK: %[[V_OUTPUT_2:.*]] = vector.extract_strided_slice %[[V_OUTPUT_R]] +// CHECK-SAME: {offsets = [0, 2, 0], sizes = [3, 1, 4], strides = [1, 1, 1]} : vector<3x3x4xi8> to vector<3x1x4xi8> + +/// w == 0, kw == 0 +// CHECK: %[[VAL_23:.*]] = vector.shape_cast %[[V_INPUT_0]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_24:.*]] = vector.shape_cast %[[V_OUTPUT_0]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[B_FILTER_0:.*]] = vector.broadcast %[[V_FILTER_0]] : vector<4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_26:.*]] = vector.shape_cast %[[B_FILTER_0]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_27:.*]] = arith.muli %[[VAL_23]], %[[VAL_26]] : vector<3x4xi8> +// CHECK: %[[VAL_28:.*]] = arith.addi %[[VAL_27]], %[[VAL_24]] : vector<3x4xi8> + +/// w == 1, kw == 0 +// CHECK: %[[VAL_29:.*]] = vector.shape_cast %[[V_INPUT_1]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_30:.*]] = vector.shape_cast %[[V_OUTPUT_1]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[B_FILTER_0:.*]] = vector.broadcast %[[V_FILTER_0]] : vector<4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_32:.*]] = vector.shape_cast %[[B_FILTER_0]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_33:.*]] = arith.muli %[[VAL_29]], %[[VAL_32]] : vector<3x4xi8> +// CHECK: %[[VAL_34:.*]] = arith.addi %[[VAL_33]], %[[VAL_30]] : vector<3x4xi8> + +/// w == 2, kw == 0 +// CHECK: %[[VAL_35:.*]] = vector.shape_cast %[[V_INPUT_2]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_36:.*]] = vector.shape_cast %[[V_OUTPUT_2]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[B_FILTER_0:.*]] = vector.broadcast %[[V_FILTER_0]] : vector<4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_38:.*]] = vector.shape_cast %[[B_FILTER_0]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_39:.*]] = arith.muli %[[VAL_35]], %[[VAL_38]] : vector<3x4xi8> +// CHECK: %[[VAL_40:.*]] = arith.addi %[[VAL_39]], %[[VAL_36]] : vector<3x4xi8> + +/// w == 3, kw == 1 +// CHECK: %[[VAL_41:.*]] = vector.shape_cast %[[V_INPUT_3]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[B_FILTER_1:.*]] = vector.broadcast %[[V_FILTER_1]] : vector<4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_43:.*]] = vector.shape_cast %[[B_FILTER_1]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_44:.*]] = arith.muli %[[VAL_41]], %[[VAL_43]] : vector<3x4xi8> +// CHECK: %[[VAL_45:.*]] = arith.addi %[[VAL_44]], %[[VAL_28]] : vector<3x4xi8> + +/// w == 4, kw == 1 +// CHECK: %[[VAL_46:.*]] = vector.shape_cast %[[V_INPUT_4]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[B_FILTER_1:.*]] = vector.broadcast %[[V_FILTER_1]] : vector<4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_48:.*]] = vector.shape_cast %[[B_FILTER_1]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_49:.*]] = arith.muli %[[VAL_46]], %[[VAL_48]] : vector<3x4xi8> +// CHECK: %[[VAL_50:.*]] = arith.addi %[[VAL_49]], %[[VAL_34]] : vector<3x4xi8> + +/// w == 5, kw == 1 +// CHECK: %[[VAL_51:.*]] = vector.shape_cast %[[V_INPUT_5]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[B_FILTER_1:.*]] = vector.broadcast %[[V_FILTER_1]] : vector<4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_53:.*]] = vector.shape_cast %[[B_FILTER_1]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_54:.*]] = arith.muli %[[VAL_51]], %[[VAL_53]] : vector<3x4xi8> +// CHECK: %[[VAL_55:.*]] = arith.addi %[[VAL_54]], %[[VAL_40]] : vector<3x4xi8> + +/// w == 6, kw == 2 +// CHECK: %[[VAL_56:.*]] = vector.shape_cast %[[V_INPUT_6]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[B_FILTER_2:.*]] = vector.broadcast %[[V_FILTER_2]] : vector<4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_58:.*]] = vector.shape_cast %[[B_FILTER_2]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_59:.*]] = arith.muli %[[VAL_56]], %[[VAL_58]] : vector<3x4xi8> +// CHECK: %[[VAL_60:.*]] = arith.addi %[[VAL_59]], %[[VAL_45]] : vector<3x4xi8> + +/// w == 7, kw == 2 +// CHECK: %[[VAL_61:.*]] = vector.shape_cast %[[VAL_60]] : vector<3x4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_62:.*]] = vector.shape_cast %[[V_INPUT_7]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[B_FILTER_2:.*]] = vector.broadcast %[[V_FILTER_2]] : vector<4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_64:.*]] = vector.shape_cast %[[B_FILTER_2]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_65:.*]] = arith.muli %[[VAL_62]], %[[VAL_64]] : vector<3x4xi8> +// CHECK: %[[VAL_66:.*]] = arith.addi %[[VAL_65]], %[[VAL_50]] : vector<3x4xi8> + +/// w == 8, kw == 2 +// CHECK: %[[VAL_67:.*]] = vector.shape_cast %[[VAL_66]] : vector<3x4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_68:.*]] = vector.shape_cast %[[V_INPUT_8]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[B_FILTER_2:.*]] = vector.broadcast %[[V_FILTER_2]] : vector<4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_70:.*]] = vector.shape_cast %[[B_FILTER_2]] : vector<3x1x4xi8> to vector<3x4xi8> +// CHECK: %[[VAL_71:.*]] = arith.muli %[[VAL_68]], %[[VAL_70]] : vector<3x4xi8> +// CHECK: %[[VAL_72:.*]] = arith.addi %[[VAL_71]], %[[VAL_55]] : vector<3x4xi8> + +// Write the result back. +// CHECK: %[[VAL_73:.*]] = vector.shape_cast %[[VAL_72]] : vector<3x4xi8> to vector<3x1x4xi8> +// CHECK: %[[VAL_74:.*]] = vector.insert_strided_slice %[[VAL_61]], %[[V_OUTPUT_R]] +// CHECK-SAME: {offsets = [0, 0, 0], strides = [1, 1, 1]} : vector<3x1x4xi8> into vector<3x3x4xi8> +// CHECK: %[[VAL_75:.*]] = vector.insert_strided_slice %[[VAL_67]], %[[VAL_74]] +// CHECK-SAME: {offsets = [0, 1, 0], strides = [1, 1, 1]} : vector<3x1x4xi8> into vector<3x3x4xi8> +// CHECK: %[[VAL_76:.*]] = vector.insert_strided_slice %[[VAL_73]], %[[VAL_75]] +// CHECK-SAME: {offsets = [0, 2, 0], strides = [1, 1, 1]} : vector<3x1x4xi8> into vector<3x3x4xi8> +// CHECK: %[[VAL_77:.*]] = vector.transfer_write %[[VAL_76]], %[[OUTPUT]][%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["linalg.depthwise_conv_1d_nwc_wc"]} in %arg0 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 {flatten_1d_depthwise_conv} : (!transform.any_op) -> !transform.any_op + transform.yield + } +} + diff --git a/mlir/test/Dialect/MemRef/canonicalize.mlir b/mlir/test/Dialect/MemRef/canonicalize.mlir index a1f8673638ff..d3406c630f6d 100644 --- a/mlir/test/Dialect/MemRef/canonicalize.mlir +++ b/mlir/test/Dialect/MemRef/canonicalize.mlir @@ -191,6 +191,18 @@ func.func @no_fold_subview_negative_size(%input: memref<4x1024xf32>) -> memref) -> memref<1xf32, strided<[?], offset: 1>> { + %c0 = arith.constant 0 : index + %c1 = arith.constant 1 : index + %1 = memref.subview %arg0[1] [1] [%c0] : memref<10xf32> to memref<1xf32, strided<[?], offset: 1>> + return %1 : memref<1xf32, strided<[?], offset: 1>> +} + +// ----- + // CHECK-LABEL: func @no_fold_of_store // CHECK: %[[cst:.+]] = memref.cast %arg // CHECK: memref.store %[[cst]] diff --git a/mlir/test/Dialect/Shape/canonicalize.mlir b/mlir/test/Dialect/Shape/canonicalize.mlir index 8edbae3baf52..40b137f1fa36 100644 --- a/mlir/test/Dialect/Shape/canonicalize.mlir +++ b/mlir/test/Dialect/Shape/canonicalize.mlir @@ -1492,3 +1492,15 @@ func.func @add_poison() -> !shape.size { %result = shape.add %1, %2 : !shape.size, !shape.size -> !shape.size return %result : !shape.size } + +// ----- + +// CHECK-LABEL: func @shape_of_0d( +// CHECK-SAME: %[[arg0:.*]]: tensor +// CHECK: %[[const:.*]] = shape.const_shape [] : tensor<0xindex> +// CHECK: %[[cast:.*]] = tensor.cast %[[const]] : tensor<0xindex> to tensor +// CHECK: return %[[cast]] +func.func @shape_of_0d(%arg0: tensor) -> tensor { + %0 = shape.shape_of %arg0 : tensor -> tensor + return %0 : tensor +} diff --git a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir index f057431a841b..c240f5334c14 100644 --- a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir +++ b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir @@ -1310,3 +1310,14 @@ func.func @test_large_constant_permutation() { return } +// ----- + +// CHECK-LABEL: test_rank0_transpose_perms +// Fail to infer the shape but not crash. +func.func @test_rank0_transpose_perms() { + %14 = tensor.empty() : tensor<5x27xi64> + %cst = tensor.empty() : tensor + // CHECK: tosa.transpose + %72 = tosa.transpose %14, %cst : (tensor<5x27xi64>, tensor) -> tensor + return +} diff --git a/mlir/test/Dialect/Transform/test-pattern-application.mlir b/mlir/test/Dialect/Transform/test-pattern-application.mlir index 2d57d4aa2547..2fd47c6bae39 100644 --- a/mlir/test/Dialect/Transform/test-pattern-application.mlir +++ b/mlir/test/Dialect/Transform/test-pattern-application.mlir @@ -36,6 +36,7 @@ func.func @replacement_op_not_found() { transform.sequence failures(propagate) { ^bb1(%arg1: !transform.any_op): %0 = transform.structured.match ops{["test.container"]} in %arg1 : (!transform.any_op) -> !transform.any_op + // expected-note @below {{replacement is required because this handle must be updated}} %1 = transform.structured.match ops{["test.foo"]} in %arg1 : (!transform.any_op) -> !transform.any_op // expected-error @below {{tracking listener failed to find replacement op during application of this transform op}} // expected-note @below {{ran out of suitable replacement values}} @@ -44,7 +45,6 @@ transform.sequence failures(propagate) { } : !transform.any_op // %1 must be used in some way. If no replacement payload op could be found, // an error is thrown only if the handle is not dead. - // expected-note @below {{replacement is required because alive handle(s) exist (first use in this op as operand number 0)}} transform.annotate %1 "annotated" : !transform.any_op } @@ -363,3 +363,31 @@ transform.sequence failures(propagate) { legal_ops = ["func.func", "func.return", "test.new_op"]} : !transform.any_op } + +// ----- + +module attributes { transform.with_named_sequence } { +func.func @replacement_op_not_found() { + // No op replacement can be found, but there are no handles that must be + // updated. No error should be reported. + "test.container"() ({ + %0 = "test.foo"() {replace_with_new_op = "test.bar"} : () -> (i32) + }) : () -> () + return +} + +transform.named_sequence @patterns(%container: !transform.any_op {transform.readonly}) { + transform.apply_patterns to %container { + transform.apply_patterns.transform.test_patterns + } : !transform.any_op + transform.yield +} + +transform.sequence failures(propagate) { +^bb1(%arg1: !transform.any_op): + %0 = transform.structured.match ops{["test.container"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.structured.match ops{["test.foo"]} in %arg1 : (!transform.any_op) -> !transform.any_op + transform.annotate %1 "annotated" : !transform.any_op + transform.include @patterns failures(propagate) (%0) : (!transform.any_op) -> () +} +} diff --git a/mlir/test/Dialect/Vector/canonicalize.mlir b/mlir/test/Dialect/Vector/canonicalize.mlir index 6bfb477ecf97..1021c73cc57d 100644 --- a/mlir/test/Dialect/Vector/canonicalize.mlir +++ b/mlir/test/Dialect/Vector/canonicalize.mlir @@ -67,18 +67,6 @@ func.func @create_mask_transpose_to_transposed_create_mask( // ----- -// CHECK-LABEL: transposed_unit_dim_shape_cast_to_shape_cast -// CHECK-SAME: %[[VEC:.*]]: vector<[4]xf32> -func.func @transposed_unit_dim_shape_cast_to_shape_cast(%vec: vector<[4]xf32>) -> vector<1x[4]xf32> { - // CHECK: vector.shape_cast %[[VEC]] : vector<[4]xf32> to vector<1x[4]xf32> - // CHECK-NOT: vector.transpose - %0 = vector.shape_cast %vec : vector<[4]xf32> to vector<[4]x1xf32> - %1 = vector.transpose %0, [1, 0] : vector<[4]x1xf32> to vector<1x[4]xf32> - return %1 : vector<1x[4]xf32> -} - -// ----- - // CHECK-LABEL: extract_from_create_mask // CHECK-SAME: %[[DIM0:.*]]: index, %[[DIM1:.*]]: index func.func @extract_from_create_mask(%dim0: index, %dim1: index) -> vector<[4]x[4]xi1> { diff --git a/mlir/test/Dialect/Vector/vector-transfer-flatten.mlir b/mlir/test/Dialect/Vector/vector-transfer-flatten.mlir index 2ffe85bf3bfa..ebec2274655e 100644 --- a/mlir/test/Dialect/Vector/vector-transfer-flatten.mlir +++ b/mlir/test/Dialect/Vector/vector-transfer-flatten.mlir @@ -41,6 +41,64 @@ func.func @transfer_read_dims_mismatch_contiguous( // ----- +func.func @transfer_read_dims_mismatch_non_zero_indices( + %idx_1: index, + %idx_2: index, + %m_in: memref<1x43x4x6xi32>, + %m_out: memref<1x2x6xi32>) { + %c0 = arith.constant 0 : index + %c0_i32 = arith.constant 0 : i32 + %2 = vector.transfer_read %m_in[%c0, %idx_1, %idx_2, %c0], %c0_i32 {in_bounds = [true, true, true]} : + memref<1x43x4x6xi32>, vector<1x2x6xi32> + vector.transfer_write %2, %m_out[%c0, %c0, %c0] {in_bounds = [true, true, true]} : + vector<1x2x6xi32>, memref<1x2x6xi32> + return +} + +// CHECK: #[[$ATTR_0:.+]] = affine_map<()[s0, s1] -> (s0 * 4 + s1 * 43)> + +// CHECK-LABEL: func.func @transfer_read_dims_mismatch_non_zero_indices( +// CHECK-SAME: %[[IDX_1:.*]]: index, %[[IDX_2:.*]]: index, +// CHECK-SAME: %[[M_IN:.*]]: memref<1x43x4x6xi32>, +// CHECK-SAME: %[[M_OUT:.*]]: memref<1x2x6xi32>) { +// CHECK: %[[C_0:.*]] = arith.constant 0 : i32 +// CHECK: %[[C_0_IDX:.*]] = arith.constant 0 : index +// CHECK: %[[COLLAPSED_IN:.*]] = memref.collapse_shape %[[M_IN]] {{\[}}[0], [1, 2, 3]] : memref<1x43x4x6xi32> into memref<1x1032xi32> +// CHECK: %[[COLLAPSED_IDX:.*]] = affine.apply #[[$ATTR_0]]()[%[[IDX_2]], %[[IDX_1]]] +// CHECK: %[[READ:.*]] = vector.transfer_read %[[COLLAPSED_IN]][%[[C_0_IDX]], %[[COLLAPSED_IDX]]], %[[C_0]] {in_bounds = [true]} : memref<1x1032xi32>, vector<12xi32> +// CHECK: %[[COLLAPSED_OUT:.*]] = memref.collapse_shape %[[M_OUT]] {{\[}}[0, 1, 2]] : memref<1x2x6xi32> into memref<12xi32> +// CHECK: vector.transfer_write %[[READ]], %[[COLLAPSED_OUT]][%[[C_0_IDX]]] {in_bounds = [true]} : vector<12xi32>, memref<12xi32> + +// ----- + +// The input memref has a dynamic trailing shape and hence is not flattened. +// TODO: This case could be supported via memref.dim + +func.func @transfer_read_dims_mismatch_non_zero_indices_dynamic_shapes( + %idx_1: index, + %idx_2: index, + %m_in: memref<1x?x4x6xi32>, + %m_out: memref<1x2x6xi32>) { + %c0 = arith.constant 0 : index + %c0_i32 = arith.constant 0 : i32 + %2 = vector.transfer_read %m_in[%c0, %idx_1, %idx_2, %c0], %c0_i32 {in_bounds = [true, true, true]} : + memref<1x?x4x6xi32>, vector<1x2x6xi32> + vector.transfer_write %2, %m_out[%c0, %c0, %c0] {in_bounds = [true, true, true]} : + vector<1x2x6xi32>, memref<1x2x6xi32> + return +} + +// CHECK-LABEL: func.func @transfer_read_dims_mismatch_non_zero_indices_dynamic_shapes( +// CHECK-SAME: %[[IDX_1:.*]]: index, %[[IDX_2:.*]]: index, +// CHECK-SAME: %[[M_IN:.*]]: memref<1x?x4x6xi32>, +// CHECK-SAME: %[[M_OUT:.*]]: memref<1x2x6xi32>) { +// CHECK: %[[READ:.*]] = vector.transfer_read %[[M_IN]]{{.*}} : memref<1x?x4x6xi32>, vector<1x2x6xi32> +// CHECK: %[[COLLAPSED:.*]] = memref.collapse_shape %[[M_OUT]]{{.*}} : memref<1x2x6xi32> into memref<12xi32> +// CHECK: %[[SC:.*]] = vector.shape_cast %[[READ]] : vector<1x2x6xi32> to vector<12xi32> +// CHECK: vector.transfer_write %[[SC]], %[[COLLAPSED]]{{.*}} : vector<12xi32>, memref<12xi32> + +// ----- + func.func @transfer_read_dims_mismatch_non_contiguous( %arg : memref<5x4x3x2xi8, strided<[24, 6, 2, 1], offset: ?>>) -> vector<2x1x2x2xi8> { %c0 = arith.constant 0 : index diff --git a/mlir/test/Integration/GPU/SYCL/gpu-addf32-to-spirv.mlir b/mlir/test/Integration/GPU/SYCL/gpu-addf32-to-spirv.mlir new file mode 100644 index 000000000000..c0e2903aee2d --- /dev/null +++ b/mlir/test/Integration/GPU/SYCL/gpu-addf32-to-spirv.mlir @@ -0,0 +1,56 @@ +// RUN: mlir-opt %s -pass-pipeline='builtin.module(spirv-attach-target{ver=v1.0 caps=Addresses,Int64,Kernel},convert-gpu-to-spirv{use-64bit-index=true},gpu.module(spirv.module(spirv-lower-abi-attrs,spirv-update-vce)),func.func(llvm-request-c-wrappers),convert-scf-to-cf,convert-cf-to-llvm,convert-arith-to-llvm,convert-math-to-llvm,convert-func-to-llvm,gpu-to-llvm{use-bare-pointers-for-kernels=true},gpu-module-to-binary,expand-strided-metadata,lower-affine,finalize-memref-to-llvm,reconcile-unrealized-casts)' \ +// RUN: | mlir-cpu-runner \ +// RUN: --shared-libs=%mlir_sycl_runtime \ +// RUN: --shared-libs=%mlir_runner_utils \ +// RUN: --entry-point-result=void \ +// RUN: | FileCheck %s + +module @add attributes {gpu.container_module} { + memref.global "private" constant @__constant_2x2x2xf32_0 : memref<2x2x2xf32> = dense<[[[1.1, 2.2], [3.3, 4.4]], [[5.5, 6.6], [7.7, 8.8 ]]]> + memref.global "private" constant @__constant_2x2x2xf32 : memref<2x2x2xf32> = dense<[[[1.2, 2.3], [4.5, 5.8]], [[7.2, 8.3], [10.5, 11.8]]]> + func.func @main() { + %0 = memref.get_global @__constant_2x2x2xf32 : memref<2x2x2xf32> + %1 = memref.get_global @__constant_2x2x2xf32_0 : memref<2x2x2xf32> + %2 = call @test(%0, %1) : (memref<2x2x2xf32>, memref<2x2x2xf32>) -> memref<2x2x2xf32> + %cast = memref.cast %2 : memref<2x2x2xf32> to memref<*xf32> + call @printMemrefF32(%cast) : (memref<*xf32>) -> () + return + } + func.func private @printMemrefF32(memref<*xf32>) + func.func @test(%arg0: memref<2x2x2xf32>, %arg1: memref<2x2x2xf32>) -> memref<2x2x2xf32> { + %c2 = arith.constant 2 : index + %c1 = arith.constant 1 : index + %mem = gpu.alloc host_shared () : memref<2x2x2xf32> + memref.copy %arg1, %mem : memref<2x2x2xf32> to memref<2x2x2xf32> + %memref_0 = gpu.alloc host_shared () : memref<2x2x2xf32> + memref.copy %arg0, %memref_0 : memref<2x2x2xf32> to memref<2x2x2xf32> + %memref_2 = gpu.alloc host_shared () : memref<2x2x2xf32> + %2 = gpu.wait async + %3 = gpu.launch_func async [%2] @test_kernel::@test_kernel blocks in (%c2, %c2, %c2) threads in (%c1, %c1, %c1) args(%memref_0 : memref<2x2x2xf32>, %mem : memref<2x2x2xf32>, %memref_2 : memref<2x2x2xf32>) + gpu.wait [%3] + %alloc = memref.alloc() : memref<2x2x2xf32> + memref.copy %memref_2, %alloc : memref<2x2x2xf32> to memref<2x2x2xf32> + %4 = gpu.wait async + %5 = gpu.dealloc async [%4] %memref_2 : memref<2x2x2xf32> + %6 = gpu.dealloc async [%5] %memref_0 : memref<2x2x2xf32> + %7 = gpu.dealloc async [%6] %mem : memref<2x2x2xf32> + gpu.wait [%7] + return %alloc : memref<2x2x2xf32> + } + gpu.module @test_kernel attributes {spirv.target_env = #spirv.target_env<#spirv.vce, api=OpenCL, #spirv.resource_limits<>>} { + gpu.func @test_kernel(%arg0: memref<2x2x2xf32>, %arg1: memref<2x2x2xf32>, %arg2: memref<2x2x2xf32>) kernel attributes {gpu.known_block_size = array, gpu.known_grid_size = array, spirv.entry_point_abi = #spirv.entry_point_abi<>} { + %0 = gpu.block_id x + %1 = gpu.block_id y + %2 = gpu.block_id z + %3 = memref.load %arg0[%0, %1, %2] : memref<2x2x2xf32> + %4 = memref.load %arg1[%0, %1, %2] : memref<2x2x2xf32> + %5 = arith.addf %3, %4 : f32 + memref.store %5, %arg2[%0, %1, %2] : memref<2x2x2xf32> + gpu.return + } + } + // CHECK: [2.3, 4.5] + // CHECK: [7.8, 10.2] + // CHECK: [12.7, 14.9] + // CHECK: [18.2, 20.6] +} diff --git a/mlir/test/Integration/GPU/SYCL/gpu-addi64-to-spirv.mlir b/mlir/test/Integration/GPU/SYCL/gpu-addi64-to-spirv.mlir new file mode 100644 index 000000000000..4ac1533b75d2 --- /dev/null +++ b/mlir/test/Integration/GPU/SYCL/gpu-addi64-to-spirv.mlir @@ -0,0 +1,54 @@ +// RUN: mlir-opt %s -pass-pipeline='builtin.module(spirv-attach-target{ver=v1.0 caps=Addresses,Int64,Kernel},convert-gpu-to-spirv{use-64bit-index=true},gpu.module(spirv.module(spirv-lower-abi-attrs,spirv-update-vce)),func.func(llvm-request-c-wrappers),convert-scf-to-cf,convert-cf-to-llvm,convert-arith-to-llvm,convert-math-to-llvm,convert-func-to-llvm,gpu-to-llvm{use-bare-pointers-for-kernels=true},gpu-module-to-binary,expand-strided-metadata,lower-affine,finalize-memref-to-llvm,reconcile-unrealized-casts)' \ +// RUN: | mlir-cpu-runner \ +// RUN: --shared-libs=%mlir_sycl_runtime \ +// RUN: --shared-libs=%mlir_runner_utils \ +// RUN: --entry-point-result=void \ +// RUN: | FileCheck %s + +module @add attributes {gpu.container_module} { + memref.global "private" constant @__constant_3x3xi64_0 : memref<3x3xi64> = dense<[[1, 4098, 3], [16777220, 5, 4294967302], [7, 1099511627784, 9]]> + memref.global "private" constant @__constant_3x3xi64 : memref<3x3xi64> = dense<[[1, 2, 3], [4, 5, 4102], [16777223, 4294967304, 1099511627785]]> + func.func @main() { + %0 = memref.get_global @__constant_3x3xi64 : memref<3x3xi64> + %1 = memref.get_global @__constant_3x3xi64_0 : memref<3x3xi64> + %2 = call @test(%0, %1) : (memref<3x3xi64>, memref<3x3xi64>) -> memref<3x3xi64> + %cast = memref.cast %2 : memref<3x3xi64> to memref<*xi64> + call @printMemrefI64(%cast) : (memref<*xi64>) -> () + return + } + func.func private @printMemrefI64(memref<*xi64>) + func.func @test(%arg0: memref<3x3xi64>, %arg1: memref<3x3xi64>) -> memref<3x3xi64> { + %c3 = arith.constant 3 : index + %c1 = arith.constant 1 : index + %mem = gpu.alloc host_shared () : memref<3x3xi64> + memref.copy %arg1, %mem : memref<3x3xi64> to memref<3x3xi64> + %memref_0 = gpu.alloc host_shared () : memref<3x3xi64> + memref.copy %arg0, %memref_0 : memref<3x3xi64> to memref<3x3xi64> + %memref_2 = gpu.alloc host_shared () : memref<3x3xi64> + %2 = gpu.wait async + %3 = gpu.launch_func async [%2] @test_kernel::@test_kernel blocks in (%c3, %c3, %c1) threads in (%c1, %c1, %c1) args(%memref_0 : memref<3x3xi64>, %mem : memref<3x3xi64>, %memref_2 : memref<3x3xi64>) + gpu.wait [%3] + %alloc = memref.alloc() : memref<3x3xi64> + memref.copy %memref_2, %alloc : memref<3x3xi64> to memref<3x3xi64> + %4 = gpu.wait async + %5 = gpu.dealloc async [%4] %memref_2 : memref<3x3xi64> + %6 = gpu.dealloc async [%5] %memref_0 : memref<3x3xi64> + %7 = gpu.dealloc async [%6] %mem : memref<3x3xi64> + gpu.wait [%7] + return %alloc : memref<3x3xi64> + } + gpu.module @test_kernel attributes {spirv.target_env = #spirv.target_env<#spirv.vce, api=OpenCL, #spirv.resource_limits<>>} { + gpu.func @test_kernel(%arg0: memref<3x3xi64>, %arg1: memref<3x3xi64>, %arg2: memref<3x3xi64>) kernel attributes {gpu.known_block_size = array, gpu.known_grid_size = array, spirv.entry_point_abi = #spirv.entry_point_abi<>} { + %0 = gpu.block_id x + %1 = gpu.block_id y + %2 = memref.load %arg0[%0, %1] : memref<3x3xi64> + %3 = memref.load %arg1[%0, %1] : memref<3x3xi64> + %4 = arith.addi %2, %3 : i64 + memref.store %4, %arg2[%0, %1] : memref<3x3xi64> + gpu.return + } + } + // CHECK: [2, 4100, 6], + // CHECK: [16777224, 10, 4294971404], + // CHECK: [16777230, 1103806595088, 1099511627794] +} diff --git a/mlir/test/Integration/GPU/SYCL/gpu-reluf32-to-spirv.mlir b/mlir/test/Integration/GPU/SYCL/gpu-reluf32-to-spirv.mlir new file mode 100644 index 000000000000..162a793305e9 --- /dev/null +++ b/mlir/test/Integration/GPU/SYCL/gpu-reluf32-to-spirv.mlir @@ -0,0 +1,79 @@ +// RUN: mlir-opt %s -pass-pipeline='builtin.module(spirv-attach-target{ver=v1.0 caps=Addresses,Int64,Kernel},convert-gpu-to-spirv{use-64bit-index=true},gpu.module(spirv.module(spirv-lower-abi-attrs,spirv-update-vce)),func.func(llvm-request-c-wrappers),convert-scf-to-cf,convert-cf-to-llvm,convert-arith-to-llvm,convert-math-to-llvm,convert-func-to-llvm,gpu-to-llvm{use-bare-pointers-for-kernels=true},gpu-module-to-binary,expand-strided-metadata,lower-affine,finalize-memref-to-llvm,reconcile-unrealized-casts)' \ +// RUN: | mlir-cpu-runner \ +// RUN: --shared-libs=%mlir_sycl_runtime \ +// RUN: --shared-libs=%mlir_runner_utils \ +// RUN: --entry-point-result=void \ +// RUN: | FileCheck %s + +module @relu attributes {gpu.container_module} { + memref.global "private" constant @__constant_4x5xf32 : memref<4x5xf32> = dense<[ + [-1.000000e-01, -2.000000e-01, -3.000000e-01, 4.000000e-01, 5.000000e-01], + [1.000000e-01, -2.000000e-01, 3.000000e-01, -4.000000e-01, 5.000000e-01], + [1.000000e-01, 2.000000e-01, 3.000000e-01, -4.000000e-01, -5.000000e-01], + [1.000000e-01, 2.000000e-01, 3.000000e-01, 4.000000e-01, 5.000000e-01] + ]> + + func.func @main() { + %c1 = arith.constant 1 : index + %c100 = arith.constant 100 : index + %c0 = arith.constant 0 : index + %0 = memref.get_global @__constant_4x5xf32 : memref<4x5xf32> + + scf.for %arg0 = %c0 to %c100 step %c1 { + %1 = func.call @test(%0) : (memref<4x5xf32>) -> memref<4x5xf32> + %cast = memref.cast %1 : memref<4x5xf32> to memref<*xf32> + func.call @printMemrefF32(%cast) : (memref<*xf32>) -> () + // CHECK: [0, 0, 0, 0.4, 0.5], + // CHECK: [0.1, 0, 0.3, 0, 0.5], + // CHECK: [0.1, 0.2, 0.3, 0, 0], + // CHECK: [0.1, 0.2, 0.3, 0.4, 0.5] + } + return + } + + func.func private @printMemrefF32(memref<*xf32>) + func.func @test(%arg0: memref<4x5xf32>) -> memref<4x5xf32> { + %c5 = arith.constant 5 : index + %c4 = arith.constant 4 : index + %cst = arith.constant 0.000000e+00 : f32 + %c1 = arith.constant 1 : index + %memref = gpu.alloc host_shared () : memref<4x5xf32> + memref.copy %arg0, %memref : memref<4x5xf32> to memref<4x5xf32> + %memref_0 = gpu.alloc host_shared () : memref<4x5xi1> + %2 = gpu.wait async + %3 = gpu.launch_func async [%2] @test_kernel::@test_kernel blocks in (%c4, %c5, %c1) threads in (%c1, %c1, %c1) args(%memref : memref<4x5xf32>, %cst : f32, %memref_0 : memref<4x5xi1>) + gpu.wait [%3] + %memref_1 = gpu.alloc host_shared () : memref<4x5xf32> + %4 = gpu.wait async + %5 = gpu.launch_func async [%4] @test_kernel_0::@test_kernel blocks in (%c4, %c5, %c1) threads in (%c1, %c1, %c1) args(%memref_0 : memref<4x5xi1>, %memref : memref<4x5xf32>, %cst : f32, %memref_1 : memref<4x5xf32>) + gpu.wait [%5] + %alloc = memref.alloc() : memref<4x5xf32> + memref.copy %memref_1, %alloc : memref<4x5xf32> to memref<4x5xf32> + %6 = gpu.wait async + %7 = gpu.dealloc async [%6] %memref_1 : memref<4x5xf32> + %8 = gpu.dealloc async [%7] %memref_0 : memref<4x5xi1> + %9 = gpu.dealloc async [%8] %memref : memref<4x5xf32> + return %alloc : memref<4x5xf32> + } + gpu.module @test_kernel attributes {spirv.target_env = #spirv.target_env<#spirv.vce, api=OpenCL, #spirv.resource_limits<>>} { + gpu.func @test_kernel(%arg0: memref<4x5xf32>, %arg1: f32, %arg2: memref<4x5xi1>) kernel attributes {gpu.known_block_size = array, gpu.known_grid_size = array, spirv.entry_point_abi = #spirv.entry_point_abi<>} { + %0 = gpu.block_id x + %1 = gpu.block_id y + %2 = memref.load %arg0[%0, %1] : memref<4x5xf32> + %3 = arith.cmpf olt, %2, %arg1 : f32 + memref.store %3, %arg2[%0, %1] : memref<4x5xi1> + gpu.return + } + } + gpu.module @test_kernel_0 attributes {spirv.target_env = #spirv.target_env<#spirv.vce, api=OpenCL, #spirv.resource_limits<>>} { + gpu.func @test_kernel(%arg0: memref<4x5xi1>, %arg1: memref<4x5xf32>, %arg2: f32, %arg3: memref<4x5xf32>) kernel attributes {gpu.known_block_size = array, gpu.known_grid_size = array, spirv.entry_point_abi = #spirv.entry_point_abi<>} { + %0 = gpu.block_id x + %1 = gpu.block_id y + %2 = memref.load %arg0[%0, %1] : memref<4x5xi1> + %3 = memref.load %arg1[%0, %1] : memref<4x5xf32> + %4 = arith.select %2, %arg2, %3 : f32 + memref.store %4, %arg3[%0, %1] : memref<4x5xf32> + gpu.return + } + } +} diff --git a/mlir/test/Integration/GPU/SYCL/lit.local.cfg b/mlir/test/Integration/GPU/SYCL/lit.local.cfg new file mode 100644 index 000000000000..75bac1882eed --- /dev/null +++ b/mlir/test/Integration/GPU/SYCL/lit.local.cfg @@ -0,0 +1,2 @@ +if not config.enable_sycl_runner: + config.unsupported = True diff --git a/mlir/test/Target/LLVMIR/Import/debug-info.ll b/mlir/test/Target/LLVMIR/Import/debug-info.ll index c8f40cfeabdb..f8bf00bbf3f6 100644 --- a/mlir/test/Target/LLVMIR/Import/debug-info.ll +++ b/mlir/test/Target/LLVMIR/Import/debug-info.ll @@ -33,11 +33,11 @@ define i32 @instruction_loc(i32 %arg1) { ; CHECK-DAG: #[[SP:.+]] = #llvm.di_subprogram[#[[RAW_FILE_LOC]]]) -; CHECK-DAG: #[[CALLEE_LOC:.+]] = loc("debug-info.ll":7:4) +; CHECK-DAG: #[[RAW_CALLEE_LOC:.+]] = loc("debug-info.ll":7:4) +; CHECK-DAG: #[[CALLEE_LOC:.+]] = loc(fused<#[[CALLEE]]>[#[[RAW_CALLEE_LOC]]]) ; CHECK-DAG: #[[RAW_CALLER_LOC:.+]] = loc("debug-info.ll":2:2) ; CHECK-DAG: #[[CALLER_LOC:.+]] = loc(fused<#[[SP]]>[#[[RAW_CALLER_LOC]]]) -; CHECK-DAG: #[[RAW_CALLSITE_LOC:.+]] = loc(callsite(#[[CALLEE_LOC]] at #[[CALLER_LOC]])) -; CHECK-DAG: #[[CALLSITE_LOC]] = loc(fused<#[[CALLEE]]>[#[[RAW_CALLSITE_LOC]]]) +; CHECK-DAG: #[[CALLSITE_LOC:.+]] = loc(callsite(#[[CALLEE_LOC]] at #[[CALLER_LOC]])) !llvm.dbg.cu = !{!1} !llvm.module.flags = !{!0} diff --git a/mlir/test/Target/LLVMIR/Import/frame-pointer.ll b/mlir/test/Target/LLVMIR/Import/frame-pointer.ll new file mode 100644 index 000000000000..7e811b635ebe --- /dev/null +++ b/mlir/test/Target/LLVMIR/Import/frame-pointer.ll @@ -0,0 +1,8 @@ +; RUN: mlir-translate -import-llvm -split-input-file %s | FileCheck %s + +; CHECK-LABEL: llvm.func @frame_pointer_func +; CHECK-SAME: attributes {frame_pointer = #llvm.framePointerKind<"non-leaf">} + +define void @frame_pointer_func() "frame-pointer"="non-leaf" { + ret void +} diff --git a/mlir/test/Target/LLVMIR/Import/target-features.ll b/mlir/test/Target/LLVMIR/Import/target-features.ll new file mode 100644 index 000000000000..d3feeda85691 --- /dev/null +++ b/mlir/test/Target/LLVMIR/Import/target-features.ll @@ -0,0 +1,9 @@ +; RUN: mlir-translate -import-llvm -split-input-file %s | FileCheck %s + +; CHECK-LABEL: llvm.func @target_features() +; CHECK-SAME: #llvm.target_features<["+sme", "+sme-f64f64", "+sve"]> +define void @target_features() #0 { + ret void +} + +attributes #0 = { "target-features"="+sme,+sme-f64f64,+sve" } diff --git a/mlir/test/Target/LLVMIR/frame-pointer.mlir b/mlir/test/Target/LLVMIR/frame-pointer.mlir new file mode 100644 index 000000000000..5224e97a4080 --- /dev/null +++ b/mlir/test/Target/LLVMIR/frame-pointer.mlir @@ -0,0 +1,8 @@ +// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s + +// CHECK-LABEL: define void @frame_pointer_func() +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @frame_pointer_func() attributes {frame_pointer = #llvm.framePointerKind<"non-leaf">} { + llvm.return +} +// CHECK: attributes #[[ATTRS]] = { "frame-pointer"="non-leaf" } diff --git a/mlir/test/Target/LLVMIR/gpu.mlir b/mlir/test/Target/LLVMIR/gpu.mlir index 190b53bcf208..88672bd231df 100644 --- a/mlir/test/Target/LLVMIR/gpu.mlir +++ b/mlir/test/Target/LLVMIR/gpu.mlir @@ -1,5 +1,5 @@ // RUN: mlir-translate -mlir-to-llvmir -split-input-file %s | FileCheck %s - + // Checking the translation of the `gpu.binary` & `gpu.launch_fun` ops. module attributes {gpu.container_module} { // CHECK: [[ARGS_TY:%.*]] = type { i32, i32 } @@ -17,10 +17,10 @@ module attributes {gpu.container_module} { // CHECK: store i32 32, ptr [[ARG1]], align 4 // CHECK: %{{.*}} = getelementptr ptr, ptr [[ARGS_ARRAY]], i32 1 // CHECK: store ptr [[ARG1]], ptr %{{.*}}, align 8 - // CHECK: [[MODULE:%.*]] = call ptr @mgpuModuleLoad(ptr @kernel_module_bin_cst) + // CHECK: [[MODULE:%.*]] = call ptr @mgpuModuleLoad(ptr @kernel_module_bin_cst, i64 4) // CHECK: [[FUNC:%.*]] = call ptr @mgpuModuleGetFunction(ptr [[MODULE]], ptr @kernel_module_kernel_kernel_name) // CHECK: [[STREAM:%.*]] = call ptr @mgpuStreamCreate() - // CHECK: call void @mgpuLaunchKernel(ptr [[FUNC]], i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i32 256, ptr [[STREAM]], ptr [[ARGS_ARRAY]], ptr null) + // CHECK: call void @mgpuLaunchKernel(ptr [[FUNC]], i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i32 256, ptr [[STREAM]], ptr [[ARGS_ARRAY]], ptr null, i64 2) // CHECK: call void @mgpuStreamSynchronize(ptr [[STREAM]]) // CHECK: call void @mgpuStreamDestroy(ptr [[STREAM]]) // CHECK: call void @mgpuModuleUnload(ptr [[MODULE]]) @@ -50,6 +50,13 @@ module { // ----- +// Checking the correct selection of the second object using a target as a selector. +module { + // CHECK: @kernel_module_bin_cst = internal constant [4 x i8] c"BLOB", align 8 + gpu.binary @kernel_module <#gpu.select_object<#spirv.target_env<#spirv.vce, api=OpenCL, #spirv.resource_limits<>>>> [#gpu.object<#nvvm.target, "NVPTX">, #gpu.object<#spirv.target_env<#spirv.vce, api=OpenCL, #spirv.resource_limits<>>, "BLOB">] +} + +// ----- // Checking the translation of `gpu.launch_fun` with an async dependency. module attributes {gpu.container_module} { // CHECK: @kernel_module_bin_cst = internal constant [4 x i8] c"BLOB", align 8 @@ -59,9 +66,9 @@ module attributes {gpu.container_module} { // CHECK: = call ptr @mgpuStreamCreate() // CHECK-NEXT: = alloca {{.*}}, align 8 // CHECK-NEXT: [[ARGS:%.*]] = alloca ptr, i64 0, align 8 - // CHECK-NEXT: [[MODULE:%.*]] = call ptr @mgpuModuleLoad(ptr @kernel_module_bin_cst) + // CHECK-NEXT: [[MODULE:%.*]] = call ptr @mgpuModuleLoad(ptr @kernel_module_bin_cst, i64 4) // CHECK-NEXT: [[FUNC:%.*]] = call ptr @mgpuModuleGetFunction(ptr [[MODULE]], ptr @kernel_module_kernel_kernel_name) - // CHECK-NEXT: call void @mgpuLaunchKernel(ptr [[FUNC]], i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i32 0, ptr {{.*}}, ptr [[ARGS]], ptr null) + // CHECK-NEXT: call void @mgpuLaunchKernel(ptr [[FUNC]], i64 8, i64 8, i64 8, i64 8, i64 8, i64 8, i32 0, ptr {{.*}}, ptr [[ARGS]], ptr null, i64 0) // CHECK-NEXT: call void @mgpuModuleUnload(ptr [[MODULE]]) // CHECK-NEXT: call void @mgpuStreamSynchronize(ptr %{{.*}}) // CHECK-NEXT: call void @mgpuStreamDestroy(ptr %{{.*}}) @@ -84,7 +91,7 @@ module attributes {gpu.container_module} { gpu.binary @kernel_module [#gpu.object<#nvvm.target, "BLOB">] llvm.func @foo() { // CHECK: [[S2:%.*]] = alloca ptr, i64 0, align 8 - // CHECK: [[S3:%.*]] = call ptr @mgpuModuleLoad(ptr @kernel_module_bin_cst) + // CHECK: [[S3:%.*]] = call ptr @mgpuModuleLoad(ptr @kernel_module_bin_cst, i64 4) // CHECK: [[S4:%.*]] = call ptr @mgpuModuleGetFunction(ptr [[S3]], ptr @kernel_module_kernel_kernel_name) // CHECK: [[S5:%.*]] = call ptr @mgpuStreamCreate() // CHECK: call void @mgpuLaunchClusterKernel(ptr [[S4]], i64 2, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i32 0, ptr [[S5]], ptr [[S2]], ptr null) diff --git a/mlir/test/Target/LLVMIR/llvmir-debug.mlir b/mlir/test/Target/LLVMIR/llvmir-debug.mlir index e62ee35f6c00..fe7f1b96d323 100644 --- a/mlir/test/Target/LLVMIR/llvmir-debug.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-debug.mlir @@ -100,20 +100,23 @@ llvm.func @func_with_debug(%arg: i64) { // CHECK: call void @llvm.dbg.value(metadata i64 %[[ARG]], metadata ![[NO_NAME_VAR:[0-9]+]], metadata !DIExpression()) llvm.intr.dbg.value #noNameVariable = %arg : i64 - // CHECK: call void @func_no_debug(), !dbg ![[CALLSITE_LOC:[0-9]+]] - llvm.call @func_no_debug() : () -> () loc(callsite("mysource.cc":3:4 at "mysource.cc":5:6)) - // CHECK: call void @func_no_debug(), !dbg ![[FILE_LOC:[0-9]+]] llvm.call @func_no_debug() : () -> () loc("foo.mlir":1:2) // CHECK: call void @func_no_debug(), !dbg ![[NAMED_LOC:[0-9]+]] llvm.call @func_no_debug() : () -> () loc("named"("foo.mlir":10:10)) + // CHECK: call void @func_no_debug(), !dbg ![[CALLSITE_LOC:[0-9]+]] + llvm.call @func_no_debug() : () -> () loc(callsite("nodebug.cc":3:4 at "mysource.cc":5:6)) + + // CHECK: call void @func_no_debug(), !dbg ![[CALLSITE_LOC:[0-9]+]] + llvm.call @func_no_debug() : () -> () loc(callsite("nodebug.cc":3:4 at fused<#sp0>["mysource.cc":5:6])) + // CHECK: call void @func_no_debug(), !dbg ![[FUSED_LOC:[0-9]+]] - llvm.call @func_no_debug() : () -> () loc(fused[callsite("mysource.cc":5:6 at "mysource.cc":1:1), "mysource.cc":1:1]) + llvm.call @func_no_debug() : () -> () loc(fused[callsite(fused<#callee>["mysource.cc":5:6] at "mysource.cc":1:1), "mysource.cc":1:1]) // CHECK: add i64 %[[ARG]], %[[ARG]], !dbg ![[FUSEDWITH_LOC:[0-9]+]] - %sum = llvm.add %arg, %arg : i64 loc(fused<#callee>[callsite("foo.mlir":2:4 at fused<#sp0>["foo.mlir":28:5])]) + %sum = llvm.add %arg, %arg : i64 loc(callsite(fused<#callee>["foo.mlir":2:4] at fused<#sp0>["foo.mlir":28:5])) llvm.return } loc(fused<#sp0>["foo.mlir":1:1]) @@ -148,7 +151,7 @@ llvm.func @empty_types() { // CHECK: ![[BLOCK_LOC]] = distinct !DILexicalBlock(scope: ![[FUNC_LOC]]) // CHECK: ![[NO_NAME_VAR]] = !DILocalVariable(scope: ![[BLOCK_LOC]]) -// CHECK-DAG: ![[CALLSITE_LOC]] = !DILocation(line: 3, column: 4, +// CHECK-DAG: ![[CALLSITE_LOC]] = !DILocation(line: 5, column: 6, // CHECK-DAG: ![[FILE_LOC]] = !DILocation(line: 1, column: 2, // CHECK-DAG: ![[NAMED_LOC]] = !DILocation(line: 10, column: 10 // CHECK-DAG: ![[FUSED_LOC]] = !DILocation(line: 1, column: 1 @@ -186,7 +189,7 @@ llvm.func @empty_types() { #di_label = #llvm.di_label #loc0 = loc("foo.mlir":0:0) -#loc1 = loc(callsite(#loc0 at fused<#di_subprogram>["foo.mlir":4:2])) +#loc1 = loc(callsite(fused<#di_lexical_block_file>[#loc0] at fused<#di_subprogram>["foo.mlir":4:2])) // CHECK-LABEL: define i32 @func_with_inlined_dbg_value( // CHECK-SAME: i32 %[[ARG:.*]]) !dbg ![[OUTER_FUNC:[0-9]+]] @@ -194,9 +197,9 @@ llvm.func @func_with_inlined_dbg_value(%arg0: i32) -> (i32) { // CHECK: call void @llvm.dbg.value(metadata i32 %[[ARG]], metadata ![[VAR_LOC0:[0-9]+]], metadata !DIExpression()), !dbg ![[DBG_LOC0:.*]] llvm.intr.dbg.value #di_local_variable0 = %arg0 : i32 loc(fused<#di_subprogram>[#loc0]) // CHECK: call void @llvm.dbg.value(metadata i32 %[[ARG]], metadata ![[VAR_LOC1:[0-9]+]], metadata !DIExpression()), !dbg ![[DBG_LOC1:.*]] - llvm.intr.dbg.value #di_local_variable1 = %arg0 : i32 loc(fused<#di_lexical_block_file>[#loc1]) + llvm.intr.dbg.value #di_local_variable1 = %arg0 : i32 loc(#loc1) // CHECK: call void @llvm.dbg.label(metadata ![[LABEL:[0-9]+]]), !dbg ![[DBG_LOC1:.*]] - llvm.intr.dbg.label #di_label loc(fused<#di_lexical_block_file>[#loc1]) + llvm.intr.dbg.label #di_label loc(#loc1) llvm.return %arg0 : i32 } loc(fused<#di_subprogram>["caller"]) @@ -286,3 +289,24 @@ llvm.func @dbg_intrinsics_with_no_location(%arg0: i32) -> (i32) { #di_basic_type_2 = #llvm.di_basic_type llvm.mlir.global external @global_with_expr_1() {addr_space = 0 : i32, dbg_expr = #llvm.di_global_variable_expression, expr = <>>} : i64 llvm.mlir.global external @global_with_expr_2() {addr_space = 0 : i32, dbg_expr = #llvm.di_global_variable_expression, expr = <>>} : i64 + +// ----- + +// CHECK-DAG: ![[FILE1:.*]] = !DIFile(filename: "foo1.mlir", directory: "/test/") +#di_file_1 = #llvm.di_file<"foo1.mlir" in "/test/"> +// CHECK-DAG: ![[FILE2:.*]] = !DIFile(filename: "foo2.mlir", directory: "/test/") +#di_file_2 = #llvm.di_file<"foo2.mlir" in "/test/"> +// CHECK-DAG: ![[SCOPE2:.*]] = distinct !DICompileUnit(language: DW_LANG_C, file: ![[FILE2]], producer: "MLIR", isOptimized: true, runtimeVersion: 0, emissionKind: DebugDirectivesOnly) +#di_compile_unit_1 = #llvm.di_compile_unit +// CHECK-DAG: ![[SCOPE1:.*]] = distinct !DICompileUnit(language: DW_LANG_C, file: ![[FILE1]], producer: "MLIR", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly) +#di_compile_unit_2 = #llvm.di_compile_unit +#di_subprogram_1 = #llvm.di_subprogram +#di_subprogram_2 = #llvm.di_subprogram + +llvm.func @func_line_tables() { + llvm.return +} loc(fused<#di_subprogram_1>["foo1.mlir":0:0]) + +llvm.func @func_debug_directives() { + llvm.return +} loc(fused<#di_subprogram_2>["foo2.mlir":0:0]) diff --git a/mlir/test/Target/LLVMIR/llvmir-invalid.mlir b/mlir/test/Target/LLVMIR/llvmir-invalid.mlir index 0def5895fb33..38601c863b98 100644 --- a/mlir/test/Target/LLVMIR/llvmir-invalid.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-invalid.mlir @@ -7,6 +7,14 @@ func.func @foo() { // ----- +llvm.func @vector_with_non_vector_type() -> f32 { + // expected-error @below{{expected vector or array type}} + %cst = llvm.mlir.constant(dense<100.0> : vector<1xf64>) : f32 + llvm.return %cst : f32 +} + +// ----- + llvm.func @no_non_complex_struct() -> !llvm.array<2 x array<2 x array<2 x struct<(i32)>>>> { // expected-error @below{{expected struct type to be a complex number}} %0 = llvm.mlir.constant(dense<[[[1, 2], [3, 4]], [[42, 43], [44, 45]]]> : tensor<2x2x2xi32>) : !llvm.array<2 x array<2 x array<2 x struct<(i32)>>>> @@ -31,6 +39,14 @@ llvm.func @struct_wrong_attribute_element_type() -> !llvm.struct<(f64, f64)> { // ----- +llvm.func @integer_with_float_type() -> f32 { + // expected-error @+1 {{expected integer type}} + %0 = llvm.mlir.constant(1 : index) : f32 + llvm.return %0 : f32 +} + +// ----- + llvm.func @incompatible_float_attribute_type() -> f32 { // expected-error @below{{expected float type of width 64}} %cst = llvm.mlir.constant(1.0 : f64) : f32 @@ -261,6 +277,27 @@ llvm.func @stepvector_intr_wrong_type() -> vector<7xf32> { // ----- +// expected-error @below{{target features can not contain ','}} +llvm.func @invalid_target_feature() attributes { target_features = #llvm.target_features<["+bad,feature", "+test"]> } +{ +} + +// ----- + +// expected-error @below{{target features must start with '+' or '-'}} +llvm.func @missing_target_feature_prefix() attributes { target_features = #llvm.target_features<["sme"]> } +{ +} + +// ----- + +// expected-error @below{{target features can not be null or empty}} +llvm.func @empty_target_feature() attributes { target_features = #llvm.target_features<["", "+sve"]> } +{ +} + +// ----- + llvm.comdat @__llvm_comdat { llvm.comdat_selector @foo any } diff --git a/mlir/test/Target/LLVMIR/llvmir.mlir b/mlir/test/Target/LLVMIR/llvmir.mlir index 3f84f9dc5a9b..d9e7b790dd80 100644 --- a/mlir/test/Target/LLVMIR/llvmir.mlir +++ b/mlir/test/Target/LLVMIR/llvmir.mlir @@ -1223,19 +1223,23 @@ llvm.func @dereferenceableornullattr_ret_decl() -> (!llvm.ptr {llvm.dereferencea llvm.func @inregattr_ret_decl() -> (!llvm.ptr {llvm.inreg}) // CHECK-LABEL: @varargs(...) -llvm.func @varargs(...) +llvm.func @varargs(...) -> f32 // CHECK-LABEL: define void @varargs_call llvm.func @varargs_call(%arg0 : i32) { -// CHECK: call void (...) @varargs(i32 %{{.*}}) - llvm.call @varargs(%arg0) vararg(!llvm.func) : (i32) -> () +// CHECK: call float (...) @varargs(i32 %{{.*}}) +// CHECK: call nnan float (...) @varargs(i32 %{{.*}}) + llvm.call @varargs(%arg0) vararg(!llvm.func) : (i32) -> (f32) + llvm.call @varargs(%arg0) vararg(!llvm.func) {fastmathFlags = #llvm.fastmath} : (i32) -> (f32) llvm.return } // CHECK-LABEL: define void @indirect_varargs_call(ptr %0, i32 %1) llvm.func @indirect_varargs_call(%arg0 : !llvm.ptr, %arg1 : i32) { -// CHECK: call void (...) %0(i32 %1) - llvm.call %arg0(%arg1) vararg(!llvm.func) : !llvm.ptr, (i32) -> () +// CHECK: call float (...) %0(i32 %1) +// CHECK: call nnan float (...) %0(i32 %1) + llvm.call %arg0(%arg1) vararg(!llvm.func) : !llvm.ptr, (i32) -> (f32) + llvm.call %arg0(%arg1) vararg(!llvm.func) {fastmathFlags = #llvm.fastmath} : !llvm.ptr, (i32) -> (f32) llvm.return } diff --git a/mlir/test/Target/LLVMIR/target-features.mlir b/mlir/test/Target/LLVMIR/target-features.mlir new file mode 100644 index 000000000000..7a69a2c78897 --- /dev/null +++ b/mlir/test/Target/LLVMIR/target-features.mlir @@ -0,0 +1,9 @@ +// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s + +// CHECK-LABEL: define void @target_features +// CHECK: attributes #{{.*}} = { "target-features"="+sme,+sve,+sme-f64f64" } +llvm.func @target_features() attributes { + target_features = #llvm.target_features<["+sme", "+sve", "+sme-f64f64"]> +} { + llvm.return +} diff --git a/mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp b/mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp index feb716cdbf40..86b8d5f9b099 100644 --- a/mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp +++ b/mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp @@ -454,6 +454,7 @@ struct TestFlattenVectorTransferPatterns } void getDependentDialects(DialectRegistry ®istry) const override { registry.insert(); + registry.insert(); } void runOnOperation() override { RewritePatternSet patterns(&getContext()); diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py index 17c29445ba82..5b92491175e5 100644 --- a/mlir/test/lit.cfg.py +++ b/mlir/test/lit.cfg.py @@ -132,6 +132,9 @@ if config.enable_rocm_runner: if config.enable_cuda_runner: tools.extend([add_runtime("mlir_cuda_runtime")]) +if config.enable_sycl_runner: + tools.extend([add_runtime("mlir_sycl_runtime")]) + if config.mlir_run_arm_sme_tests: config.substitutions.append( ( diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in index 146e8443f5c9..c0fa1b8980e5 100644 --- a/mlir/test/lit.site.cfg.py.in +++ b/mlir/test/lit.site.cfg.py.in @@ -31,6 +31,7 @@ config.run_rocm_tests = @MLIR_ENABLE_ROCM_CONVERSIONS@ config.enable_rocm_runner = @MLIR_ENABLE_ROCM_RUNNER@ config.gpu_compilation_format = "@MLIR_GPU_COMPILATION_TEST_FORMAT@" config.rocm_test_chipset = "@ROCM_TEST_CHIPSET@" +config.enable_sycl_runner = @MLIR_ENABLE_SYCL_RUNNER@ config.enable_spirv_cpu_runner = @MLIR_ENABLE_SPIRV_CPU_RUNNER@ config.enable_vulkan_runner = @MLIR_ENABLE_VULKAN_RUNNER@ config.enable_bindings_python = @MLIR_ENABLE_BINDINGS_PYTHON@ diff --git a/mlir/test/python/dialects/affine.py b/mlir/test/python/dialects/affine.py index c5ec85457493..df42f8fcf1a5 100644 --- a/mlir/test/python/dialects/affine.py +++ b/mlir/test/python/dialects/affine.py @@ -1,44 +1,172 @@ # RUN: %PYTHON %s | FileCheck %s from mlir.ir import * -import mlir.dialects.func as func -import mlir.dialects.arith as arith -import mlir.dialects.affine as affine -import mlir.dialects.memref as memref +from mlir.dialects import func +from mlir.dialects import arith +from mlir.dialects import memref +from mlir.dialects import affine -def run(f): +def constructAndPrintInModule(f): print("\nTEST:", f.__name__) - f() + with Context(), Location.unknown(): + module = Module.create() + with InsertionPoint(module.body): + f() + print(module) return f # CHECK-LABEL: TEST: testAffineStoreOp -@run +@constructAndPrintInModule def testAffineStoreOp(): - with Context() as ctx, Location.unknown(): - module = Module.create() - with InsertionPoint(module.body): - f32 = F32Type.get() - index_type = IndexType.get() - memref_type_out = MemRefType.get([12, 12], f32) + f32 = F32Type.get() + index_type = IndexType.get() + memref_type_out = MemRefType.get([12, 12], f32) - # CHECK: func.func @affine_store_test(%[[ARG0:.*]]: index) -> memref<12x12xf32> { - @func.FuncOp.from_py_func(index_type) - def affine_store_test(arg0): - # CHECK: %[[O_VAR:.*]] = memref.alloc() : memref<12x12xf32> - mem = memref.AllocOp(memref_type_out, [], []).result + # CHECK: func.func @affine_store_test(%[[ARG0:.*]]: index) -> memref<12x12xf32> { + @func.FuncOp.from_py_func(index_type) + def affine_store_test(arg0): + # CHECK: %[[O_VAR:.*]] = memref.alloc() : memref<12x12xf32> + mem = memref.AllocOp(memref_type_out, [], []).result - d0 = AffineDimExpr.get(0) - s0 = AffineSymbolExpr.get(0) - map = AffineMap.get(1, 1, [s0 * 3, d0 + s0 + 1]) + d0 = AffineDimExpr.get(0) + s0 = AffineSymbolExpr.get(0) + map = AffineMap.get(1, 1, [s0 * 3, d0 + s0 + 1]) - # CHECK: %[[A1:.*]] = arith.constant 2.100000e+00 : f32 - a1 = arith.ConstantOp(f32, 2.1) + # CHECK: %[[A1:.*]] = arith.constant 2.100000e+00 : f32 + a1 = arith.ConstantOp(f32, 2.1) - # CHECK: affine.store %[[A1]], %alloc[symbol(%[[ARG0]]) * 3, %[[ARG0]] + symbol(%[[ARG0]]) + 1] : memref<12x12xf32> - affine.AffineStoreOp(a1, mem, indices=[arg0, arg0], map=map) + # CHECK: affine.store %[[A1]], %alloc[symbol(%[[ARG0]]) * 3, %[[ARG0]] + symbol(%[[ARG0]]) + 1] : memref<12x12xf32> + affine.AffineStoreOp(a1, mem, indices=[arg0, arg0], map=map) - return mem + return mem - print(module) + +# CHECK-LABEL: TEST: testAffineLoadOp +@constructAndPrintInModule +def testAffineLoadOp(): + f32 = F32Type.get() + index_type = IndexType.get() + memref_type_in = MemRefType.get([10, 10], f32) + + # CHECK: func.func @affine_load_test(%[[I_VAR:.*]]: memref<10x10xf32>, %[[ARG0:.*]]: index) -> f32 { + @func.FuncOp.from_py_func(memref_type_in, index_type) + def affine_load_test(I, arg0): + d0 = AffineDimExpr.get(0) + s0 = AffineSymbolExpr.get(0) + map = AffineMap.get(1, 1, [s0 * 3, d0 + s0 + 1]) + + # CHECK: {{.*}} = affine.load %[[I_VAR]][symbol(%[[ARG0]]) * 3, %[[ARG0]] + symbol(%[[ARG0]]) + 1] : memref<10x10xf32> + a1 = affine.AffineLoadOp(f32, I, indices=[arg0, arg0], map=map) + + return a1 + + +# CHECK-LABEL: TEST: testAffineForOp +@constructAndPrintInModule +def testAffineForOp(): + f32 = F32Type.get() + index_type = IndexType.get() + memref_type = MemRefType.get([1024], f32) + + # CHECK: #[[MAP0:.*]] = affine_map<(d0)[s0] -> (0, d0 + s0)> + # CHECK: #[[MAP1:.*]] = affine_map<(d0, d1) -> (d0 - 2, d1 * 32)> + # CHECK: func.func @affine_for_op_test(%[[BUFFER:.*]]: memref<1024xf32>) { + @func.FuncOp.from_py_func(memref_type) + def affine_for_op_test(buffer): + # CHECK: %[[C1:.*]] = arith.constant 1 : index + c1 = arith.ConstantOp(index_type, 1) + # CHECK: %[[C2:.*]] = arith.constant 2 : index + c2 = arith.ConstantOp(index_type, 2) + # CHECK: %[[C3:.*]] = arith.constant 3 : index + c3 = arith.ConstantOp(index_type, 3) + # CHECK: %[[C9:.*]] = arith.constant 9 : index + c9 = arith.ConstantOp(index_type, 9) + # CHECK: %[[AC0:.*]] = arith.constant 0.000000e+00 : f32 + ac0 = AffineConstantExpr.get(0) + + d0 = AffineDimExpr.get(0) + d1 = AffineDimExpr.get(1) + s0 = AffineSymbolExpr.get(0) + lb = AffineMap.get(1, 1, [ac0, d0 + s0]) + ub = AffineMap.get(2, 0, [d0 - 2, 32 * d1]) + sum_0 = arith.ConstantOp(f32, 0.0) + + # CHECK: %0 = affine.for %[[INDVAR:.*]] = max #[[MAP0]](%[[C2]])[%[[C3]]] to min #[[MAP1]](%[[C9]], %[[C1]]) step 2 iter_args(%[[SUM0:.*]] = %[[AC0]]) -> (f32) { + sum = affine.AffineForOp( + lb, + ub, + 2, + iter_args=[sum_0], + lower_bound_operands=[c2, c3], + upper_bound_operands=[c9, c1], + ) + + with InsertionPoint(sum.body): + # CHECK: %[[TMP:.*]] = memref.load %[[BUFFER]][%[[INDVAR]]] : memref<1024xf32> + tmp = memref.LoadOp(buffer, [sum.induction_variable]) + sum_next = arith.AddFOp(sum.inner_iter_args[0], tmp) + + affine.AffineYieldOp([sum_next]) + + return + + +@constructAndPrintInModule +def testForSugar(): + index_type = IndexType.get() + memref_t = MemRefType.get([10], index_type) + range = affine.for_ + + # CHECK: func.func @range_loop_1(%[[VAL_0:.*]]: index, %[[VAL_1:.*]]: index, %[[VAL_2:.*]]: index, %[[VAL_3:.*]]: memref<10xindex>) { + # CHECK: %[[VAL_4:.*]] = arith.constant 10 : index + # CHECK: affine.for %[[VAL_6:.*]] = %[[VAL_0]] to %[[VAL_4]] step 2 { + # CHECK: %[[VAL_7:.*]] = arith.addi %[[VAL_6]], %[[VAL_6]] : index + # CHECK: affine.store %[[VAL_7]], %[[VAL_3]]{{\[symbol\(}}%[[VAL_6]]{{\)\]}} : memref<10xindex> + # CHECK: } + # CHECK: return + # CHECK: } + @func.FuncOp.from_py_func(index_type, index_type, index_type, memref_t) + def range_loop_1(lb, ub, step, memref_v): + for i in range(lb, 10, 2): + add = arith.addi(i, i) + s0 = AffineSymbolExpr.get(0) + map = AffineMap.get(0, 1, [s0]) + affine.store(add, memref_v, [i], map=map) + affine.AffineYieldOp([]) + + # CHECK: func.func @range_loop_2(%[[VAL_0:.*]]: index, %[[VAL_1:.*]]: index, %[[VAL_2:.*]]: index, %[[VAL_3:.*]]: memref<10xindex>) { + # CHECK: %[[VAL_4:.*]] = arith.constant 0 : index + # CHECK: %[[VAL_5:.*]] = arith.constant 10 : index + # CHECK: affine.for %[[VAL_7:.*]] = %[[VAL_4]] to %[[VAL_5]] { + # CHECK: %[[VAL_8:.*]] = arith.addi %[[VAL_7]], %[[VAL_7]] : index + # CHECK: affine.store %[[VAL_8]], %[[VAL_3]]{{\[symbol\(}}%[[VAL_7]]{{\)\]}} : memref<10xindex> + # CHECK: } + # CHECK: return + # CHECK: } + @func.FuncOp.from_py_func(index_type, index_type, index_type, memref_t) + def range_loop_2(lb, ub, step, memref_v): + for i in range(0, 10, 1): + add = arith.addi(i, i) + s0 = AffineSymbolExpr.get(0) + map = AffineMap.get(0, 1, [s0]) + affine.store(add, memref_v, [i], map=map) + affine.AffineYieldOp([]) + + # CHECK: func.func @range_loop_3(%[[VAL_0:.*]]: index, %[[VAL_1:.*]]: index, %[[VAL_2:.*]]: index, %[[VAL_3:.*]]: memref<10xindex>) { + # CHECK: %[[VAL_4:.*]] = arith.constant 0 : index + # CHECK: affine.for %[[VAL_6:.*]] = %[[VAL_4]] to %[[VAL_1]] { + # CHECK: %[[VAL_7:.*]] = arith.addi %[[VAL_6]], %[[VAL_6]] : index + # CHECK: affine.store %[[VAL_7]], %[[VAL_3]]{{\[symbol\(}}%[[VAL_6]]{{\)\]}} : memref<10xindex> + # CHECK: } + # CHECK: return + # CHECK: } + @func.FuncOp.from_py_func(index_type, index_type, index_type, memref_t) + def range_loop_3(lb, ub, step, memref_v): + for i in range(0, ub, 1): + add = arith.addi(i, i) + s0 = AffineSymbolExpr.get(0) + map = AffineMap.get(0, 1, [s0]) + affine.store(add, memref_v, [i], map=map) + affine.AffineYieldOp([]) diff --git a/openmp/libomptarget/CMakeLists.txt b/openmp/libomptarget/CMakeLists.txt index 972b887c7c95..115189a28ce1 100644 --- a/openmp/libomptarget/CMakeLists.txt +++ b/openmp/libomptarget/CMakeLists.txt @@ -110,10 +110,6 @@ set(LIBOMPTARGET_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/include) message(STATUS "OpenMP tools dir in libomptarget: ${LIBOMP_OMP_TOOLS_INCLUDE_DIR}") include_directories(${LIBOMP_OMP_TOOLS_INCLUDE_DIR}) -# Build target agnostic offloading library. -set(LIBOMPTARGET_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/src) -add_subdirectory(${LIBOMPTARGET_SRC_DIR}) - # Definitions for testing, for reuse when testing libomptarget-nvptx. set(LIBOMPTARGET_OPENMP_HEADER_FOLDER "${LIBOMP_INCLUDE_DIR}" CACHE STRING "Path to folder containing omp.h") @@ -129,5 +125,9 @@ add_subdirectory(plugins-nextgen) add_subdirectory(DeviceRTL) add_subdirectory(tools) +# Build target agnostic offloading library. +set(LIBOMPTARGET_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/src) +add_subdirectory(${LIBOMPTARGET_SRC_DIR}) + # Add tests. add_subdirectory(test) diff --git a/openmp/libomptarget/include/PluginManager.h b/openmp/libomptarget/include/PluginManager.h index 94ecce01ca74..6af99efa32a0 100644 --- a/openmp/libomptarget/include/PluginManager.h +++ b/openmp/libomptarget/include/PluginManager.h @@ -14,6 +14,7 @@ #define OMPTARGET_PLUGIN_MANAGER_H #include "DeviceImage.h" +#include "ExclusiveAccess.h" #include "Shared/APITypes.h" #include "Shared/PluginAPI.h" #include "Shared/Requirements.h" @@ -25,6 +26,7 @@ #include "llvm/ADT/iterator.h" #include "llvm/ADT/iterator_range.h" #include "llvm/Support/DynamicLibrary.h" +#include "llvm/Support/Error.h" #include #include @@ -32,13 +34,29 @@ #include #include +struct PluginManager; + +/// Plugin adaptors should be created via `PluginAdaptorTy::create` which will +/// invoke the constructor and call `PluginAdaptorTy::init`. Eventual errors are +/// reported back to the caller, otherwise a valid and initialized adaptor is +/// returned. struct PluginAdaptorTy { - PluginAdaptorTy(const std::string &Name); + /// Try to create a plugin adaptor from a filename. + static llvm::Expected> + create(const std::string &Name); + + /// Initialize as many devices as possible for this plugin adaptor. Devices + /// that fail to initialize are ignored. + void initDevices(PluginManager &PM); bool isUsed() const { return DeviceOffset >= 0; } - /// Return the number of devices available to this plugin. - int32_t getNumDevices() const { return NumberOfDevices; } + /// Return the number of devices visible to the underlying plugin. + int32_t getNumberOfPluginDevices() const { return NumberOfPluginDevices; } + + /// Return the number of devices successfully initialized and visible to the + /// user. + int32_t getNumberOfUserDevices() const { return NumberOfUserDevices; } /// Add all offload entries described by \p DI to the devices managed by this /// plugin. @@ -49,9 +67,6 @@ struct PluginAdaptorTy { /// registered with this RTL. int32_t DeviceOffset = -1; - /// Number of devices this RTL deals with. - int32_t NumberOfDevices = -1; - /// Name of the shared object file representing the plugin. std::string Name; @@ -71,10 +86,33 @@ struct PluginAdaptorTy { // It is easier to enforce thread-safety at the libomptarget level, // so that developers of new RTLs do not have to worry about it. std::mutex Mtx; + +private: + /// Number of devices the underling plugins sees. + int32_t NumberOfPluginDevices = -1; + + /// Number of devices exposed to the user. This can be less than the number of + /// devices for the plugin if some failed to initialize. + int32_t NumberOfUserDevices = 0; + + /// Create a plugin adaptor for filename \p Name with a dynamic library \p DL. + PluginAdaptorTy(const std::string &Name, + std::unique_ptr DL); + + /// Initialize the plugin adaptor, this can fail in which case the adaptor is + /// useless. + llvm::Error init(); }; /// Struct for the data required to handle plugins struct PluginManager { + /// Type of the devices container. We hand out DeviceTy& to queries which are + /// stable addresses regardless if the container changes. + using DeviceContainerTy = llvm::SmallVector>; + + /// Exclusive accessor type for the device container. + using ExclusiveDevicesAccessorTy = Accessor; + PluginManager() {} void init(); @@ -89,13 +127,19 @@ struct PluginManager { DeviceImages.emplace_back(std::make_unique(TgtBinDesc, TgtDeviceImage)); } + /// Return the device presented to the user as device \p DeviceNo if it is + /// initialized and ready. Otherwise return an error explaining the problem. + llvm::Expected getDevice(uint32_t DeviceNo); + + /// Iterate over all initialized and ready devices registered with this + /// plugin. + auto devices(ExclusiveDevicesAccessorTy &DevicesAccessor) { + return llvm::make_pointee_range(*DevicesAccessor); + } + /// Iterate over all device images registered with this plugin. auto deviceImages() { return llvm::make_pointee_range(DeviceImages); } - /// Devices associated with RTLs - llvm::SmallVector> Devices; - std::mutex RTLsMtx; ///< For RTLs and Devices - /// Translation table retreived from the binary HostEntriesBeginToTransTableTy HostEntriesBeginToTransTable; std::mutex TrlTblMtx; ///< For Translation Table @@ -106,46 +150,26 @@ struct PluginManager { HostPtrToTableMapTy HostPtrToTableMap; std::mutex TblMapMtx; ///< For HostPtrToTableMap - // Work around for plugins that call dlopen on shared libraries that call - // tgt_register_lib during their initialisation. Stash the pointers in a - // vector until the plugins are all initialised and then register them. - bool delayRegisterLib(__tgt_bin_desc *Desc) { - if (RTLsLoaded) - return false; - DelayedBinDesc.push_back(Desc); - return true; - } - - void registerDelayedLibraries() { - // Only called by libomptarget constructor - RTLsLoaded = true; - for (auto *Desc : DelayedBinDesc) - __tgt_register_lib(Desc); - DelayedBinDesc.clear(); - } + /// Return the number of usable devices. + int getNumDevices() { return getExclusiveDevicesAccessor()->size(); } - int getNumDevices() { - std::lock_guard Lock(RTLsMtx); - return Devices.size(); + /// Return an exclusive handle to access the devices container. + ExclusiveDevicesAccessorTy getExclusiveDevicesAccessor() { + return Devices.getExclusiveAccessor(); } int getNumUsedPlugins() const { int NCI = 0; for (auto &P : PluginAdaptors) - NCI += P.isUsed(); + NCI += P->isUsed(); return NCI; } - // Initialize \p Plugin if it has not been initialized. - void initPlugin(PluginAdaptorTy &Plugin); - // Initialize all plugins. void initAllPlugins(); /// Iterator range for all plugin adaptors (in use or not, but always valid). - auto pluginAdaptors() { - return llvm::make_range(PluginAdaptors.begin(), PluginAdaptors.end()); - } + auto pluginAdaptors() { return llvm::make_pointee_range(PluginAdaptors); } /// Return the user provided requirements. int64_t getRequirements() const { return Requirements.getRequirements(); } @@ -154,11 +178,8 @@ struct PluginManager { void addRequirements(int64_t Flags) { Requirements.addRequirements(Flags); } private: - bool RTLsLoaded = false; - llvm::SmallVector<__tgt_bin_desc *> DelayedBinDesc; - // List of all plugin adaptors, in use or not. - std::list PluginAdaptors; + llvm::SmallVector> PluginAdaptors; /// Executable images and information extracted from the input images passed /// to the runtime. @@ -166,6 +187,11 @@ private: /// The user provided requirements. RequirementCollection Requirements; + + std::mutex RTLsMtx; ///< For RTLs + + /// Devices associated with plugins, accesses to the container are exclusive. + ProtectedObj Devices; }; extern PluginManager *PM; diff --git a/openmp/libomptarget/include/Shared/Debug.h b/openmp/libomptarget/include/Shared/Debug.h index 9f8818429c77..a39626d15386 100644 --- a/openmp/libomptarget/include/Shared/Debug.h +++ b/openmp/libomptarget/include/Shared/Debug.h @@ -115,15 +115,16 @@ inline uint32_t getDebugLevel() { /// Print fatal error message with an error string and error identifier #define FATAL_MESSAGE0(_num, _str) \ do { \ - fprintf(stderr, GETNAME(TARGET_NAME) " fatal error %d: %s\n", _num, _str); \ + fprintf(stderr, GETNAME(TARGET_NAME) " fatal error %d: %s\n", (int)_num, \ + _str); \ abort(); \ } while (0) /// Print fatal error message with a printf string and error identifier #define FATAL_MESSAGE(_num, _str, ...) \ do { \ - fprintf(stderr, GETNAME(TARGET_NAME) " fatal error %d: " _str "\n", _num, \ - __VA_ARGS__); \ + fprintf(stderr, GETNAME(TARGET_NAME) " fatal error %d: " _str "\n", \ + (int)_num, __VA_ARGS__); \ abort(); \ } while (0) diff --git a/openmp/libomptarget/include/device.h b/openmp/libomptarget/include/device.h index 05ed6546557a..a84551accaf9 100644 --- a/openmp/libomptarget/include/device.h +++ b/openmp/libomptarget/include/device.h @@ -51,8 +51,6 @@ struct DeviceTy { PluginAdaptorTy *RTL; int32_t RTLDeviceID; - bool IsInit; - std::once_flag InitFlag; bool HasMappedGlobalData = false; /// Host data to device map type with a wrapper key indirection that allows @@ -72,13 +70,16 @@ struct DeviceTy { std::mutex PendingGlobalsMtx; - DeviceTy(PluginAdaptorTy *RTL); + DeviceTy(PluginAdaptorTy *RTL, int32_t DeviceID, int32_t RTLDeviceID); // DeviceTy is not copyable DeviceTy(const DeviceTy &D) = delete; DeviceTy &operator=(const DeviceTy &D) = delete; ~DeviceTy(); + /// Try to initialize the device and return any failure. + llvm::Error init(); + // Return true if data can be copied to DstDevice directly bool isDataExchangable(const DeviceTy &DstDevice); @@ -145,8 +146,6 @@ struct DeviceTy { int associatePtr(void *HstPtrBegin, void *TgtPtrBegin, int64_t Size); int disassociatePtr(void *HstPtrBegin); - // calls to RTL - int32_t initOnce(); __tgt_target_table *loadBinary(__tgt_device_image *Img); // device memory allocation/deallocation routines @@ -170,11 +169,14 @@ struct DeviceTy { // Copy data from host to device int32_t submitData(void *TgtPtrBegin, void *HstPtrBegin, int64_t Size, AsyncInfoTy &AsyncInfo, - HostDataToTargetTy *Entry = nullptr); + HostDataToTargetTy *Entry = nullptr, + DeviceTy::HDTTMapAccessorTy *HDTTMapPtr = nullptr); // Copy data from device back to host int32_t retrieveData(void *HstPtrBegin, void *TgtPtrBegin, int64_t Size, AsyncInfoTy &AsyncInfo, - HostDataToTargetTy *Entry = nullptr); + HostDataToTargetTy *Entry = nullptr, + DeviceTy::HDTTMapAccessorTy *HDTTMapPtr = nullptr); + // Copy data from current device to destination device directly int32_t dataExchange(void *SrcPtr, DeviceTy &DstDev, void *DstPtr, int64_t Size, AsyncInfoTy &AsyncInfo); @@ -202,9 +204,8 @@ struct DeviceTy { /// completed and AsyncInfo.isDone() returns true. int32_t queryAsync(AsyncInfoTy &AsyncInfo); - /// Calls the corresponding print in the \p RTLDEVID - /// device RTL to obtain the information of the specific device. - bool printDeviceInfo(int32_t RTLDevID); + /// Calls the corresponding print device info function in the plugin. + bool printDeviceInfo(); /// Event related interfaces. /// { @@ -235,9 +236,6 @@ struct DeviceTy { void dumpOffloadEntries(); private: - // Call to RTL - void init(); // To be called only via DeviceTy::initOnce() - /// Deinitialize the device (and plugin). void deinit(); @@ -245,6 +243,4 @@ private: llvm::DenseMap DeviceOffloadEntries; }; -extern bool deviceIsReady(int DeviceNum); - #endif diff --git a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp index 69acfa54e6c9..0ffdabe5bcd4 100644 --- a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp @@ -2692,11 +2692,8 @@ private: // Perform a quick check for the named kernel in the image. The kernel // should be created by the 'amdgpu-lower-ctor-dtor' pass. GenericGlobalHandlerTy &Handler = Plugin.getGlobalHandler(); - GlobalTy Global(Name, sizeof(void *)); - if (auto Err = Handler.getGlobalMetadataFromImage(*this, Image, Global)) { - consumeError(std::move(Err)); + if (!Handler.isSymbolInImage(*this, Image, Name)) return Plugin::success(); - } // Allocate and construct the AMDGPU kernel. AMDGPUKernelTy AMDGPUKernel(Name); diff --git a/openmp/libomptarget/plugins-nextgen/common/include/GlobalHandler.h b/openmp/libomptarget/plugins-nextgen/common/include/GlobalHandler.h index aff10b1d504f..fa788c5e1d02 100644 --- a/openmp/libomptarget/plugins-nextgen/common/include/GlobalHandler.h +++ b/openmp/libomptarget/plugins-nextgen/common/include/GlobalHandler.h @@ -120,6 +120,11 @@ public: const ELF64LEObjectFile * getOrCreateELFObjectFile(const GenericDeviceTy &Device, DeviceImageTy &Image); + /// Returns whether the symbol named \p SymName is present in the given \p + /// Image. + bool isSymbolInImage(GenericDeviceTy &Device, DeviceImageTy &Image, + StringRef SymName); + /// Get the address and size of a global in the image. Address and size are /// return in \p ImageGlobal, the global name is passed in \p ImageGlobal. Error getGlobalMetadataFromImage(GenericDeviceTy &Device, diff --git a/openmp/libomptarget/plugins-nextgen/common/src/GlobalHandler.cpp b/openmp/libomptarget/plugins-nextgen/common/src/GlobalHandler.cpp index 6cb9a366f8b2..a3d16d3a5bcf 100644 --- a/openmp/libomptarget/plugins-nextgen/common/src/GlobalHandler.cpp +++ b/openmp/libomptarget/plugins-nextgen/common/src/GlobalHandler.cpp @@ -105,6 +105,26 @@ Error GenericGlobalHandlerTy::moveGlobalBetweenDeviceAndHost( return Plugin::success(); } +bool GenericGlobalHandlerTy::isSymbolInImage(GenericDeviceTy &Device, + DeviceImageTy &Image, + StringRef SymName) { + // Get the ELF object file for the image. Notice the ELF object may already + // be created in previous calls, so we can reuse it. If this is unsuccessful + // just return false as we couldn't find it. + const ELF64LEObjectFile *ELFObj = getOrCreateELFObjectFile(Device, Image); + if (!ELFObj) + return false; + + // Search the ELF symbol using the symbol name. + auto SymOrErr = utils::elf::getSymbol(*ELFObj, SymName); + if (!SymOrErr) { + consumeError(SymOrErr.takeError()); + return false; + } + + return *SymOrErr; +} + Error GenericGlobalHandlerTy::getGlobalMetadataFromImage( GenericDeviceTy &Device, DeviceImageTy &Image, GlobalTy &ImageGlobal) { diff --git a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp index 5a3fd140f27a..912e3d2c479b 100644 --- a/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp +++ b/openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp @@ -785,12 +785,9 @@ Error GenericDeviceTy::deinit(GenericPluginTy &Plugin) { GenericGlobalHandlerTy &GHandler = Plugin.getGlobalHandler(); for (auto *Image : LoadedImages) { DeviceMemoryPoolTrackingTy ImageDeviceMemoryPoolTracking = {0, 0, ~0U, 0}; - GlobalTy TrackerGlobal("__omp_rtl_device_memory_pool_tracker", - sizeof(DeviceMemoryPoolTrackingTy), - &ImageDeviceMemoryPoolTracking); - if (auto Err = - GHandler.readGlobalFromDevice(*this, *Image, TrackerGlobal)) - return Err; + if (!GHandler.isSymbolInImage(*this, *Image, + "__omp_rtl_device_memory_pool_tracker")) + continue; DeviceMemoryPoolTracking.combine(ImageDeviceMemoryPoolTracking); } @@ -975,6 +972,12 @@ Error GenericDeviceTy::setupDeviceMemoryPool(GenericPluginTy &Plugin, sizeof(DeviceMemoryPoolTrackingTy), &DeviceMemoryPoolTracking); GenericGlobalHandlerTy &GHandler = Plugin.getGlobalHandler(); + if (auto Err = GHandler.readGlobalFromImage(*this, Image, TrackerGlobal)) { + [[maybe_unused]] std::string ErrStr = toString(std::move(Err)); + DP("Avoid the memory pool: %s.\n", ErrStr.c_str()); + return Error::success(); + } + if (auto Err = GHandler.writeGlobalToDevice(*this, Image, TrackerGlobal)) return Err; @@ -1704,7 +1707,7 @@ int32_t __tgt_rtl_number_of_devices() { return Plugin::get().getNumDevices(); } int64_t __tgt_rtl_init_requires(int64_t RequiresFlags) { Plugin::get().setRequiresFlag(RequiresFlags); - return RequiresFlags; + return OFFLOAD_SUCCESS; } int32_t __tgt_rtl_is_data_exchangable(int32_t SrcDeviceId, diff --git a/openmp/libomptarget/plugins-nextgen/common/src/RPC.cpp b/openmp/libomptarget/plugins-nextgen/common/src/RPC.cpp index a40bf147b224..60e0540e9602 100644 --- a/openmp/libomptarget/plugins-nextgen/common/src/RPC.cpp +++ b/openmp/libomptarget/plugins-nextgen/common/src/RPC.cpp @@ -38,14 +38,7 @@ RPCServerTy::isDeviceUsingRPC(plugin::GenericDeviceTy &Device, plugin::GenericGlobalHandlerTy &Handler, plugin::DeviceImageTy &Image) { #ifdef LIBOMPTARGET_RPC_SUPPORT - void *ClientPtr; - plugin::GlobalTy Global(rpc_client_symbol_name, sizeof(void *), &ClientPtr); - if (auto Err = Handler.readGlobalFromImage(Device, Image, Global)) { - llvm::consumeError(std::move(Err)); - return false; - } - - return true; + return Handler.isSymbolInImage(Device, Image, rpc_client_symbol_name); #else return false; #endif diff --git a/openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp index 698517179e4c..7bad411b9d8e 100644 --- a/openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp @@ -1055,11 +1055,8 @@ private: // Perform a quick check for the named kernel in the image. The kernel // should be created by the 'nvptx-lower-ctor-dtor' pass. GenericGlobalHandlerTy &Handler = Plugin.getGlobalHandler(); - GlobalTy Global(KernelName, sizeof(void *)); - if (auto Err = Handler.getGlobalMetadataFromImage(*this, Image, Global)) { - consumeError(std::move(Err)); + if (!Handler.isSymbolInImage(*this, Image, KernelName)) return Plugin::success(); - } // The Nvidia backend cannot handle creating the ctor / dtor array // automatically so we must create it ourselves. The backend will emit diff --git a/openmp/libomptarget/src/CMakeLists.txt b/openmp/libomptarget/src/CMakeLists.txt index 7c311f738ac8..7c07c61142ba 100644 --- a/openmp/libomptarget/src/CMakeLists.txt +++ b/openmp/libomptarget/src/CMakeLists.txt @@ -55,6 +55,27 @@ target_compile_definitions(omptarget PRIVATE DEBUG_PREFIX="omptarget" ) +macro(check_plugin_target target) +if (TARGET omptarget.rtl.${target}) + list(APPEND LIBOMPTARGET_PLUGINS_TO_LOAD ${target}) +endif() +endmacro() + +set(LIBOMPTARGET_PLUGINS_TO_LOAD "" CACHE STRING + "Comma separated list of plugin names to look for at runtime") +if (NOT LIBOMPTARGET_PLUGINS_TO_LOAD) + check_plugin_target(ppc64) + check_plugin_target(x86_64) + check_plugin_target(cuda) + check_plugin_target(aarch64) + check_plugin_target(amdgpu) +endif() + +list(TRANSFORM LIBOMPTARGET_PLUGINS_TO_LOAD PREPEND "\"libomptarget.rtl.") +list(TRANSFORM LIBOMPTARGET_PLUGINS_TO_LOAD APPEND "\"") +list(JOIN LIBOMPTARGET_PLUGINS_TO_LOAD "," ENABLED_OFFLOAD_PLUGINS) +target_compile_definitions(omptarget PRIVATE ENABLED_OFFLOAD_PLUGINS=${ENABLED_OFFLOAD_PLUGINS}) + # libomptarget.so needs to be aware of where the plugins live as they # are now separated in the build directory. set_target_properties(omptarget PROPERTIES diff --git a/openmp/libomptarget/src/OpenMP/InteropAPI.cpp b/openmp/libomptarget/src/OpenMP/InteropAPI.cpp index 6a40dbca87af..c96ce2ce60b7 100644 --- a/openmp/libomptarget/src/OpenMP/InteropAPI.cpp +++ b/openmp/libomptarget/src/OpenMP/InteropAPI.cpp @@ -13,6 +13,9 @@ #include "PluginManager.h" #include "device.h" #include "omptarget.h" +#include "llvm/Support/Error.h" +#include +#include extern "C" { @@ -190,6 +193,14 @@ __OMP_GET_INTEROP_TY3(const char *, type_desc) __OMP_GET_INTEROP_TY3(const char *, rc_desc) #undef __OMP_GET_INTEROP_TY3 +static const char *copyErrorString(llvm::Error &&Err) { + // TODO: Use the error string while avoiding leaks. + std::string ErrMsg = llvm::toString(std::move(Err)); + char *UsrMsg = reinterpret_cast(malloc(ErrMsg.size() + 1)); + strcpy(UsrMsg, ErrMsg.c_str()); + return UsrMsg; +}; + extern "C" { void __tgt_interop_init(ident_t *LocRef, int32_t Gtid, @@ -211,12 +222,14 @@ void __tgt_interop_init(ident_t *LocRef, int32_t Gtid, } InteropPtr = new omp_interop_val_t(DeviceId, InteropType); - if (!deviceIsReady(DeviceId)) { - InteropPtr->err_str = "Device not ready!"; + + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) { + InteropPtr->err_str = copyErrorString(DeviceOrErr.takeError()); return; } - DeviceTy &Device = *PM->Devices[DeviceId]; + DeviceTy &Device = *DeviceOrErr; if (!Device.RTL || !Device.RTL->init_device_info || Device.RTL->init_device_info(DeviceId, &(InteropPtr)->device_info, &(InteropPtr)->err_str)) { @@ -248,8 +261,9 @@ void __tgt_interop_use(ident_t *LocRef, int32_t Gtid, assert((DeviceId == -1 || InteropVal->device_id == DeviceId) && "Inconsistent device-id usage!"); - if (!deviceIsReady(DeviceId)) { - InteropPtr->err_str = "Device not ready!"; + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) { + InteropPtr->err_str = copyErrorString(DeviceOrErr.takeError()); return; } @@ -277,8 +291,9 @@ void __tgt_interop_destroy(ident_t *LocRef, int32_t Gtid, assert((DeviceId == -1 || InteropVal->device_id == DeviceId) && "Inconsistent device-id usage!"); - if (!deviceIsReady(DeviceId)) { - InteropPtr->err_str = "Device not ready!"; + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) { + InteropPtr->err_str = copyErrorString(DeviceOrErr.takeError()); return; } diff --git a/openmp/libomptarget/src/PluginManager.cpp b/openmp/libomptarget/src/PluginManager.cpp index e6dedeb699b1..f93e88e9e274 100644 --- a/openmp/libomptarget/src/PluginManager.cpp +++ b/openmp/libomptarget/src/PluginManager.cpp @@ -11,6 +11,11 @@ //===----------------------------------------------------------------------===// #include "PluginManager.h" +#include "Shared/Debug.h" + +#include "llvm/Support/Error.h" +#include "llvm/Support/ErrorHandling.h" +#include using namespace llvm; using namespace llvm::sys; @@ -18,35 +23,45 @@ using namespace llvm::sys; PluginManager *PM; // List of all plugins that can support offloading. -static const char *RTLNames[] = { - /* PowerPC target */ "libomptarget.rtl.ppc64", - /* x86_64 target */ "libomptarget.rtl.x86_64", - /* CUDA target */ "libomptarget.rtl.cuda", - /* AArch64 target */ "libomptarget.rtl.aarch64", - /* AMDGPU target */ "libomptarget.rtl.amdgpu", -}; - -PluginAdaptorTy::PluginAdaptorTy(const std::string &Name) : Name(Name) { +static const char *RTLNames[] = {ENABLED_OFFLOAD_PLUGINS}; + +Expected> +PluginAdaptorTy::create(const std::string &Name) { DP("Attempting to load library '%s'...\n", Name.c_str()); std::string ErrMsg; - LibraryHandler = std::make_unique( + auto LibraryHandler = std::make_unique( DynamicLibrary::getPermanentLibrary(Name.c_str(), &ErrMsg)); if (!LibraryHandler->isValid()) { // Library does not exist or cannot be found. - DP("Unable to load library '%s': %s!\n", Name.c_str(), ErrMsg.c_str()); - return; + return createStringError(inconvertibleErrorCode(), + "Unable to load library '%s': %s!\n", Name.c_str(), + ErrMsg.c_str()); } DP("Successfully loaded library '%s'!\n", Name.c_str()); + auto PluginAdaptor = std::unique_ptr( + new PluginAdaptorTy(Name, std::move(LibraryHandler))); + if (auto Err = PluginAdaptor->init()) + return Err; + return PluginAdaptor; +} + +PluginAdaptorTy::PluginAdaptorTy(const std::string &Name, + std::unique_ptr DL) + : Name(Name), LibraryHandler(std::move(DL)) {} + +Error PluginAdaptorTy::init() { #define PLUGIN_API_HANDLE(NAME, MANDATORY) \ NAME = reinterpret_cast( \ LibraryHandler->getAddressOfSymbol(GETNAME(__tgt_rtl_##NAME))); \ if (MANDATORY && !NAME) { \ - DP("Invalid plugin as necessary interface is not found.\n"); \ - return; \ + return createStringError(inconvertibleErrorCode(), \ + "Invalid plugin as necessary interface function " \ + "(%s) was not found.\n", \ + NAME); \ } #include "Shared/PluginAPI.inc" @@ -55,23 +70,31 @@ PluginAdaptorTy::PluginAdaptorTy(const std::string &Name) : Name(Name) { // Remove plugin on failure to call optional init_plugin int32_t Rc = init_plugin(); if (Rc != OFFLOAD_SUCCESS) { - DP("Unable to initialize library '%s': %u!\n", Name.c_str(), Rc); - return; + return createStringError(inconvertibleErrorCode(), + "Unable to initialize library '%s': %u!\n", + Name.c_str(), Rc); } // No devices are supported by this RTL? - NumberOfDevices = number_of_devices(); - if (!NumberOfDevices) { - DP("No devices supported in this RTL\n"); - return; + NumberOfPluginDevices = number_of_devices(); + if (!NumberOfPluginDevices) { + return createStringError(inconvertibleErrorCode(), + "No devices supported in this RTL\n"); } - DP("Registered '%s' with %d devices!\n", Name.c_str(), NumberOfDevices); + DP("Registered '%s' with %d plugin visible devices!\n", Name.c_str(), + NumberOfPluginDevices); + return Error::success(); } void PluginAdaptorTy::addOffloadEntries(DeviceImageTy &DI) { - for (int32_t I = 0; I < NumberOfDevices; ++I) { - DeviceTy &Device = *PM->Devices[DeviceOffset + I]; + for (int32_t I = 0, E = getNumberOfUserDevices(); I < E; ++I) { + auto DeviceOrErr = PM->getDevice(DeviceOffset + I); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceOffset + I, "%s", + toString(DeviceOrErr.takeError()).c_str()); + + DeviceTy &Device = *DeviceOrErr; for (OffloadEntryTy &Entry : DI.entries()) Device.addOffloadEntry(Entry); } @@ -83,44 +106,61 @@ void PluginManager::init() { // Attempt to open all the plugins and, if they exist, check if the interface // is correct and if they are supporting any devices. for (const char *Name : RTLNames) { - PluginAdaptors.emplace_back(std::string(Name) + ".so"); - if (PluginAdaptors.back().getNumDevices() <= 0) - PluginAdaptors.pop_back(); + auto PluginAdaptorOrErr = + PluginAdaptorTy::create(std::string(Name) + ".so"); + if (!PluginAdaptorOrErr) { + [[maybe_unused]] std::string InfoMsg = + toString(PluginAdaptorOrErr.takeError()); + DP("%s", InfoMsg.c_str()); + } else { + PluginAdaptors.push_back(std::move(*PluginAdaptorOrErr)); + } } DP("RTLs loaded!\n"); } -void PluginManager::initPlugin(PluginAdaptorTy &Plugin) { - // If this RTL is not already in use, initialize it. - if (Plugin.isUsed() || !Plugin.NumberOfDevices) +void PluginAdaptorTy::initDevices(PluginManager &PM) { + if (isUsed()) return; + // If this RTL is not already in use, initialize it. + assert(getNumberOfPluginDevices() > 0 && + "Tried to initialize useless plugin adaptor"); + // Initialize the device information for the RTL we are about to use. - const size_t Start = Devices.size(); - Devices.reserve(Start + Plugin.NumberOfDevices); - for (int32_t DeviceId = 0; DeviceId < Plugin.NumberOfDevices; DeviceId++) { - Devices.push_back(std::make_unique(&Plugin)); - // global device ID - Devices[Start + DeviceId]->DeviceID = Start + DeviceId; - // RTL local device ID - Devices[Start + DeviceId]->RTLDeviceID = DeviceId; - } + auto ExclusiveDevicesAccessor = PM.getExclusiveDevicesAccessor(); // Initialize the index of this RTL and save it in the used RTLs. - Plugin.DeviceOffset = Start; + DeviceOffset = ExclusiveDevicesAccessor->size(); // If possible, set the device identifier offset in the plugin. - if (Plugin.set_device_offset) - Plugin.set_device_offset(Start); + if (set_device_offset) + set_device_offset(DeviceOffset); + + int32_t NumPD = getNumberOfPluginDevices(); + ExclusiveDevicesAccessor->reserve(DeviceOffset + NumPD); + for (int32_t PDevI = 0, UserDevId = DeviceOffset; PDevI < NumPD; PDevI++) { + auto Device = std::make_unique(this, UserDevId, PDevI); + if (auto Err = Device->init()) { + DP("Skip plugin known device %d: %s\n", PDevI, + toString(std::move(Err)).c_str()); + continue; + } + + ExclusiveDevicesAccessor->push_back(std::move(Device)); + ++NumberOfUserDevices; + ++UserDevId; + } - DP("RTL " DPxMOD " has index %d!\n", DPxPTR(Plugin.LibraryHandler.get()), - Plugin.DeviceOffset); + DP("Plugin adaptor " DPxMOD " has index %d, exposes %d out of %d devices!\n", + DPxPTR(LibraryHandler.get()), DeviceOffset, NumberOfUserDevices, + NumberOfPluginDevices); } void PluginManager::initAllPlugins() { for (auto &R : PluginAdaptors) - initPlugin(R); + R->initDevices(*this); } static void registerImageIntoTranslationTable(TranslationTable &TT, @@ -133,7 +173,8 @@ static void registerImageIntoTranslationTable(TranslationTable &TT, // Resize the Targets Table and Images to accommodate the new targets if // required - unsigned TargetsTableMinimumSize = RTL.DeviceOffset + RTL.NumberOfDevices; + unsigned TargetsTableMinimumSize = + RTL.DeviceOffset + RTL.getNumberOfUserDevices(); if (TT.TargetsTable.size() < TargetsTableMinimumSize) { TT.TargetsImages.resize(TargetsTableMinimumSize, 0); @@ -141,7 +182,7 @@ static void registerImageIntoTranslationTable(TranslationTable &TT, } // Register the image in all devices for this target type. - for (int32_t I = 0; I < RTL.NumberOfDevices; ++I) { + for (int32_t I = 0; I < RTL.getNumberOfUserDevices(); ++I) { // If we are changing the image we are also invalidating the target table. if (TT.TargetsImages[RTL.DeviceOffset + I] != Image) { TT.TargetsImages[RTL.DeviceOffset + I] = Image; @@ -184,7 +225,7 @@ void PluginManager::registerLib(__tgt_bin_desc *Desc) { DP("Image " DPxMOD " is compatible with RTL %s!\n", DPxPTR(Img->ImageStart), R.Name.c_str()); - PM->initPlugin(R); + R.initDevices(*this); // Initialize (if necessary) translation table for this library. PM->TrlTblMtx.lock(); @@ -253,8 +294,13 @@ void PluginManager::unregisterLib(__tgt_bin_desc *Desc) { // Execute dtors for static objects if the device has been used, i.e. // if its PendingCtors list has been emptied. - for (int32_t I = 0; I < FoundRTL->NumberOfDevices; ++I) { - DeviceTy &Device = *PM->Devices[FoundRTL->DeviceOffset + I]; + for (int32_t I = 0; I < FoundRTL->getNumberOfUserDevices(); ++I) { + auto DeviceOrErr = PM->getDevice(FoundRTL->DeviceOffset + I); + if (!DeviceOrErr) + FATAL_MESSAGE(FoundRTL->DeviceOffset + I, "%s", + toString(DeviceOrErr.takeError()).c_str()); + + DeviceTy &Device = *DeviceOrErr; Device.PendingGlobalsMtx.lock(); if (Device.PendingCtorsDtors[Desc].PendingCtors.empty()) { AsyncInfoTy AsyncInfo(Device); @@ -313,3 +359,14 @@ void PluginManager::unregisterLib(__tgt_bin_desc *Desc) { DP("Done unregistering library!\n"); } + +Expected PluginManager::getDevice(uint32_t DeviceNo) { + auto ExclusiveDevicesAccessor = getExclusiveDevicesAccessor(); + if (DeviceNo >= ExclusiveDevicesAccessor->size()) + return createStringError( + inconvertibleErrorCode(), + "Device number '%i' out of range, only %i devices available", DeviceNo, + ExclusiveDevicesAccessor->size()); + + return *(*ExclusiveDevicesAccessor)[DeviceNo]; +} diff --git a/openmp/libomptarget/src/api.cpp b/openmp/libomptarget/src/api.cpp index cc4cca286df5..0341e0c75464 100644 --- a/openmp/libomptarget/src/api.cpp +++ b/openmp/libomptarget/src/api.cpp @@ -110,21 +110,18 @@ EXTERN int omp_target_is_present(const void *Ptr, int DeviceNum) { return true; } - size_t NumDevices = PM->getNumDevices(); - if (NumDevices <= (size_t)DeviceNum) { - DP("Call to omp_target_is_present with invalid device ID, returning " - "false\n"); - return false; - } + auto DeviceOrErr = PM->getDevice(DeviceNum); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceNum, "%s", toString(DeviceOrErr.takeError()).c_str()); - DeviceTy &Device = *PM->Devices[DeviceNum]; // omp_target_is_present tests whether a host pointer refers to storage that // is mapped to a given device. However, due to the lack of the storage size, // only check 1 byte. Cannot set size 0 which checks whether the pointer (zero // lengh array) is mapped instead of the referred storage. - TargetPointerResultTy TPR = Device.getTgtPtrBegin(const_cast(Ptr), 1, - /*UpdateRefCount=*/false, - /*UseHoldRefCount=*/false); + TargetPointerResultTy TPR = + DeviceOrErr->getTgtPtrBegin(const_cast(Ptr), 1, + /*UpdateRefCount=*/false, + /*UseHoldRefCount=*/false); int Rc = TPR.isPresent(); DP("Call to omp_target_is_present returns %d\n", Rc); return Rc; @@ -150,16 +147,6 @@ EXTERN int omp_target_memcpy(void *Dst, const void *Src, size_t Length, return OFFLOAD_FAIL; } - if (SrcDevice != omp_get_initial_device() && !deviceIsReady(SrcDevice)) { - REPORT("omp_target_memcpy returns OFFLOAD_FAIL\n"); - return OFFLOAD_FAIL; - } - - if (DstDevice != omp_get_initial_device() && !deviceIsReady(DstDevice)) { - REPORT("omp_target_memcpy returns OFFLOAD_FAIL\n"); - return OFFLOAD_FAIL; - } - int Rc = OFFLOAD_SUCCESS; void *SrcAddr = (char *)const_cast(Src) + SrcOffset; void *DstAddr = (char *)Dst + DstOffset; @@ -172,35 +159,49 @@ EXTERN int omp_target_memcpy(void *Dst, const void *Src, size_t Length, Rc = OFFLOAD_FAIL; } else if (SrcDevice == omp_get_initial_device()) { DP("copy from host to device\n"); - DeviceTy &DstDev = *PM->Devices[DstDevice]; - AsyncInfoTy AsyncInfo(DstDev); - Rc = DstDev.submitData(DstAddr, SrcAddr, Length, AsyncInfo); + auto DstDeviceOrErr = PM->getDevice(DstDevice); + if (!DstDeviceOrErr) + FATAL_MESSAGE(DstDevice, "%s", + toString(DstDeviceOrErr.takeError()).c_str()); + AsyncInfoTy AsyncInfo(*DstDeviceOrErr); + Rc = DstDeviceOrErr->submitData(DstAddr, SrcAddr, Length, AsyncInfo); } else if (DstDevice == omp_get_initial_device()) { DP("copy from device to host\n"); - DeviceTy &SrcDev = *PM->Devices[SrcDevice]; - AsyncInfoTy AsyncInfo(SrcDev); - Rc = SrcDev.retrieveData(DstAddr, SrcAddr, Length, AsyncInfo); + auto SrcDeviceOrErr = PM->getDevice(SrcDevice); + if (!SrcDeviceOrErr) + FATAL_MESSAGE(SrcDevice, "%s", + toString(SrcDeviceOrErr.takeError()).c_str()); + AsyncInfoTy AsyncInfo(*SrcDeviceOrErr); + Rc = SrcDeviceOrErr->retrieveData(DstAddr, SrcAddr, Length, AsyncInfo); } else { DP("copy from device to device\n"); - DeviceTy &SrcDev = *PM->Devices[SrcDevice]; - DeviceTy &DstDev = *PM->Devices[DstDevice]; + auto SrcDeviceOrErr = PM->getDevice(SrcDevice); + if (!SrcDeviceOrErr) + FATAL_MESSAGE(SrcDevice, "%s", + toString(SrcDeviceOrErr.takeError()).c_str()); + AsyncInfoTy AsyncInfo(*SrcDeviceOrErr); + auto DstDeviceOrErr = PM->getDevice(DstDevice); + if (!DstDeviceOrErr) + FATAL_MESSAGE(DstDevice, "%s", + toString(DstDeviceOrErr.takeError()).c_str()); // First try to use D2D memcpy which is more efficient. If fails, fall back // to unefficient way. - if (SrcDev.isDataExchangable(DstDev)) { - AsyncInfoTy AsyncInfo(SrcDev); - Rc = SrcDev.dataExchange(SrcAddr, DstDev, DstAddr, Length, AsyncInfo); + if (SrcDeviceOrErr->isDataExchangable(*DstDeviceOrErr)) { + AsyncInfoTy AsyncInfo(*SrcDeviceOrErr); + Rc = SrcDeviceOrErr->dataExchange(SrcAddr, *DstDeviceOrErr, DstAddr, + Length, AsyncInfo); if (Rc == OFFLOAD_SUCCESS) return OFFLOAD_SUCCESS; } void *Buffer = malloc(Length); { - AsyncInfoTy AsyncInfo(SrcDev); - Rc = SrcDev.retrieveData(Buffer, SrcAddr, Length, AsyncInfo); + AsyncInfoTy AsyncInfo(*SrcDeviceOrErr); + Rc = SrcDeviceOrErr->retrieveData(Buffer, SrcAddr, Length, AsyncInfo); } if (Rc == OFFLOAD_SUCCESS) { - AsyncInfoTy AsyncInfo(DstDev); - Rc = DstDev.submitData(DstAddr, Buffer, Length, AsyncInfo); + AsyncInfoTy AsyncInfo(*DstDeviceOrErr); + Rc = DstDeviceOrErr->submitData(DstAddr, Buffer, Length, AsyncInfo); } free(Buffer); } @@ -507,15 +508,13 @@ EXTERN int omp_target_associate_ptr(const void *HostPtr, const void *DevicePtr, return OFFLOAD_FAIL; } - if (!deviceIsReady(DeviceNum)) { - REPORT("omp_target_associate_ptr returns OFFLOAD_FAIL\n"); - return OFFLOAD_FAIL; - } + auto DeviceOrErr = PM->getDevice(DeviceNum); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceNum, "%s", toString(DeviceOrErr.takeError()).c_str()); - DeviceTy &Device = *PM->Devices[DeviceNum]; void *DeviceAddr = (void *)((uint64_t)DevicePtr + (uint64_t)DeviceOffset); - int Rc = Device.associatePtr(const_cast(HostPtr), - const_cast(DeviceAddr), Size); + int Rc = DeviceOrErr->associatePtr(const_cast(HostPtr), + const_cast(DeviceAddr), Size); DP("omp_target_associate_ptr returns %d\n", Rc); return Rc; } @@ -537,13 +536,11 @@ EXTERN int omp_target_disassociate_ptr(const void *HostPtr, int DeviceNum) { return OFFLOAD_FAIL; } - if (!deviceIsReady(DeviceNum)) { - REPORT("omp_target_disassociate_ptr returns OFFLOAD_FAIL\n"); - return OFFLOAD_FAIL; - } + auto DeviceOrErr = PM->getDevice(DeviceNum); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceNum, "%s", toString(DeviceOrErr.takeError()).c_str()); - DeviceTy &Device = *PM->Devices[DeviceNum]; - int Rc = Device.disassociatePtr(const_cast(HostPtr)); + int Rc = DeviceOrErr->disassociatePtr(const_cast(HostPtr)); DP("omp_target_disassociate_ptr returns %d\n", Rc); return Rc; } @@ -570,15 +567,14 @@ EXTERN void *omp_get_mapped_ptr(const void *Ptr, int DeviceNum) { return nullptr; } - if (!deviceIsReady(DeviceNum)) { - REPORT("Device %d is not ready, returning nullptr.\n", DeviceNum); - return nullptr; - } + auto DeviceOrErr = PM->getDevice(DeviceNum); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceNum, "%s", toString(DeviceOrErr.takeError()).c_str()); - auto &Device = *PM->Devices[DeviceNum]; - TargetPointerResultTy TPR = Device.getTgtPtrBegin(const_cast(Ptr), 1, - /*UpdateRefCount=*/false, - /*UseHoldRefCount=*/false); + TargetPointerResultTy TPR = + DeviceOrErr->getTgtPtrBegin(const_cast(Ptr), 1, + /*UpdateRefCount=*/false, + /*UseHoldRefCount=*/false); if (!TPR.isPresent()) { DP("Ptr " DPxMOD "is not present on device %d, returning nullptr.\n", DPxPTR(Ptr), DeviceNum); diff --git a/openmp/libomptarget/src/device.cpp b/openmp/libomptarget/src/device.cpp index d3481d42af96..1302c4e3d917 100644 --- a/openmp/libomptarget/src/device.cpp +++ b/openmp/libomptarget/src/device.cpp @@ -22,6 +22,7 @@ #include "rtl.h" #include "Shared/EnvironmentVar.h" +#include "llvm/Support/Error.h" #include #include @@ -62,8 +63,8 @@ int HostDataToTargetTy::addEventIfNecessary(DeviceTy &Device, return OFFLOAD_SUCCESS; } -DeviceTy::DeviceTy(PluginAdaptorTy *RTL) - : DeviceID(-1), RTL(RTL), RTLDeviceID(-1), IsInit(false), InitFlag(), +DeviceTy::DeviceTy(PluginAdaptorTy *RTL, int32_t DeviceID, int32_t RTLDeviceID) + : DeviceID(DeviceID), RTL(RTL), RTLDeviceID(RTLDeviceID), PendingCtorsDtors(), PendingGlobalsMtx() {} DeviceTy::~DeviceTy() { @@ -528,14 +529,21 @@ int DeviceTy::deallocTgtPtrAndEntry(HostDataToTargetTy *Entry, int64_t Size) { return Ret; } -/// Init device, should not be called directly. -void DeviceTy::init() { +llvm::Error DeviceTy::init() { // Make call to init_requires if it exists for this plugin. + int32_t Ret = 0; if (RTL->init_requires) - RTL->init_requires(PM->getRequirements()); - int32_t Ret = RTL->init_device(RTLDeviceID); + Ret = RTL->init_requires(PM->getRequirements()); if (Ret != OFFLOAD_SUCCESS) - return; + return llvm::createStringError( + llvm::inconvertibleErrorCode(), + "Failed to initialize requirements for device %d\n", DeviceID); + + Ret = RTL->init_device(RTLDeviceID); + if (Ret != OFFLOAD_SUCCESS) + return llvm::createStringError(llvm::inconvertibleErrorCode(), + "Failed to initialize device %d\n", + DeviceID); // Enables recording kernels if set. BoolEnvar OMPX_RecordKernel("LIBOMPTARGET_RECORD", false); @@ -548,22 +556,7 @@ void DeviceTy::init() { OMPX_ReplaySaveOutput, ReqPtrArgOffset); } - IsInit = true; -} - -/// Thread-safe method to initialize the device only once. -int32_t DeviceTy::initOnce() { - std::call_once(InitFlag, &DeviceTy::init, this); - - // At this point, if IsInit is true, then either this thread or some other - // thread in the past successfully initialized the device, so we can return - // OFFLOAD_SUCCESS. If this thread executed init() via call_once() and it - // failed, return OFFLOAD_FAIL. If call_once did not invoke init(), it means - // that some other thread already attempted to execute init() and if IsInit - // is still false, return OFFLOAD_FAIL. - if (IsInit) - return OFFLOAD_SUCCESS; - return OFFLOAD_FAIL; + return llvm::Error::success(); } // Load binary to device. @@ -609,13 +602,14 @@ static void printCopyInfo(int DeviceId, bool H2D, void *SrcPtrBegin, // Submit data to device int32_t DeviceTy::submitData(void *TgtPtrBegin, void *HstPtrBegin, int64_t Size, - AsyncInfoTy &AsyncInfo, - HostDataToTargetTy *Entry) { + AsyncInfoTy &AsyncInfo, HostDataToTargetTy *Entry, + DeviceTy::HDTTMapAccessorTy *HDTTMapPtr) { if (getInfoLevel() & OMP_INFOTYPE_DATA_TRANSFER) { - HDTTMapAccessorTy HDTTMap = HostDataToTargetMap.getExclusiveAccessor(Entry); + HDTTMapAccessorTy HDTTMap = + HostDataToTargetMap.getExclusiveAccessor(!!Entry || !!HDTTMapPtr); LookupResult LR; if (!Entry) { - LR = lookupMapping(HDTTMap, HstPtrBegin, Size); + LR = lookupMapping(HDTTMapPtr ? *HDTTMapPtr : HDTTMap, HstPtrBegin, Size); Entry = LR.TPR.getEntry(); } printCopyInfo(DeviceID, /* H2D */ true, HstPtrBegin, TgtPtrBegin, Size, @@ -638,12 +632,14 @@ int32_t DeviceTy::submitData(void *TgtPtrBegin, void *HstPtrBegin, int64_t Size, // Retrieve data from device int32_t DeviceTy::retrieveData(void *HstPtrBegin, void *TgtPtrBegin, int64_t Size, AsyncInfoTy &AsyncInfo, - HostDataToTargetTy *Entry) { + HostDataToTargetTy *Entry, + DeviceTy::HDTTMapAccessorTy *HDTTMapPtr) { if (getInfoLevel() & OMP_INFOTYPE_DATA_TRANSFER) { - HDTTMapAccessorTy HDTTMap = HostDataToTargetMap.getExclusiveAccessor(Entry); + HDTTMapAccessorTy HDTTMap = + HostDataToTargetMap.getExclusiveAccessor(!!Entry || !!HDTTMapPtr); LookupResult LR; if (!Entry) { - LR = lookupMapping(HDTTMap, HstPtrBegin, Size); + LR = lookupMapping(HDTTMapPtr ? *HDTTMapPtr : HDTTMap, HstPtrBegin, Size); Entry = LR.TPR.getEntry(); } printCopyInfo(DeviceID, /* H2D */ false, TgtPtrBegin, HstPtrBegin, Size, @@ -711,10 +707,10 @@ int32_t DeviceTy::launchKernel(void *TgtEntryPtr, void **TgtVarsPtr, } // Run region on device -bool DeviceTy::printDeviceInfo(int32_t RTLDevId) { +bool DeviceTy::printDeviceInfo() { if (!RTL->print_device_info) return false; - RTL->print_device_info(RTLDevId); + RTL->print_device_info(RTLDeviceID); return true; } @@ -778,39 +774,6 @@ int32_t DeviceTy::destroyEvent(void *Event) { return OFFLOAD_SUCCESS; } -/// Check whether a device has an associated RTL and initialize it if it's not -/// already initialized. -bool deviceIsReady(int DeviceNum) { - DP("Checking whether device %d is ready.\n", DeviceNum); - // Devices.size() can only change while registering a new - // library, so try to acquire the lock of RTLs' mutex. - size_t DevicesSize; - { - std::lock_guardRTLsMtx)> LG(PM->RTLsMtx); - DevicesSize = PM->Devices.size(); - } - if (DevicesSize <= (size_t)DeviceNum) { - DP("Device ID %d does not have a matching RTL\n", DeviceNum); - return false; - } - - // Get device info - DeviceTy &Device = *PM->Devices[DeviceNum]; - - DP("Is the device %d (local ID %d) initialized? %d\n", DeviceNum, - Device.RTLDeviceID, Device.IsInit); - - // Init the device if not done before - if (!Device.IsInit && Device.initOnce() != OFFLOAD_SUCCESS) { - DP("Failed to init device %d\n", DeviceNum); - return false; - } - - DP("Device %d is ready to use.\n", DeviceNum); - - return true; -} - void DeviceTy::addOffloadEntry(OffloadEntryTy &Entry) { std::lock_guard Lock(PendingGlobalsMtx); DeviceOffloadEntries[Entry.getName()] = &Entry; diff --git a/openmp/libomptarget/src/interface.cpp b/openmp/libomptarget/src/interface.cpp index 62cf2262deb6..777dc07943aa 100644 --- a/openmp/libomptarget/src/interface.cpp +++ b/openmp/libomptarget/src/interface.cpp @@ -46,9 +46,6 @@ EXTERN void __tgt_register_requires(int64_t Flags) { /// adds a target shared library to the target execution image EXTERN void __tgt_register_lib(__tgt_bin_desc *Desc) { TIMESCOPE(); - if (PM->delayRegisterLib(Desc)) - return; - PM->registerLib(Desc); } @@ -95,8 +92,11 @@ targetData(ident_t *Loc, int64_t DeviceId, int32_t ArgNum, void **ArgsBase, } #endif - DeviceTy &Device = *PM->Devices[DeviceId]; - TargetAsyncInfoTy TargetAsyncInfo(Device); + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceId, "%s", toString(DeviceOrErr.takeError()).c_str()); + + TargetAsyncInfoTy TargetAsyncInfo(*DeviceOrErr); AsyncInfoTy &AsyncInfo = TargetAsyncInfo; /// RAII to establish tool anchors before and after data begin / end / update @@ -115,7 +115,7 @@ targetData(ident_t *Loc, int64_t DeviceId, int32_t ArgNum, void **ArgsBase, OMPT_GET_RETURN_ADDRESS(0));) int Rc = OFFLOAD_SUCCESS; - Rc = TargetDataFunction(Loc, Device, ArgNum, ArgsBase, Args, ArgSizes, + Rc = TargetDataFunction(Loc, *DeviceOrErr, ArgNum, ArgsBase, Args, ArgSizes, ArgTypes, ArgNames, ArgMappers, AsyncInfo, false /* FromMapper */); @@ -286,8 +286,11 @@ static inline int targetKernel(ident_t *Loc, int64_t DeviceId, int32_t NumTeams, } #endif - DeviceTy &Device = *PM->Devices[DeviceId]; - TargetAsyncInfoTy TargetAsyncInfo(Device); + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceId, "%s", toString(DeviceOrErr.takeError()).c_str()); + + TargetAsyncInfoTy TargetAsyncInfo(*DeviceOrErr); AsyncInfoTy &AsyncInfo = TargetAsyncInfo; /// RAII to establish tool anchors before and after target region OMPT_IF_BUILT(InterfaceRAII TargetRAII( @@ -295,7 +298,7 @@ static inline int targetKernel(ident_t *Loc, int64_t DeviceId, int32_t NumTeams, /* CodePtr */ OMPT_GET_RETURN_ADDRESS(0));) int Rc = OFFLOAD_SUCCESS; - Rc = target(Loc, Device, HostPtr, *KernelArgs, AsyncInfo); + Rc = target(Loc, *DeviceOrErr, HostPtr, *KernelArgs, AsyncInfo); if (Rc == OFFLOAD_SUCCESS) Rc = AsyncInfo.synchronize(); @@ -339,14 +342,12 @@ EXTERN int __tgt_activate_record_replay(int64_t DeviceId, uint64_t MemorySize, void *VAddr, bool IsRecord, bool SaveOutput, uint64_t &ReqPtrArgOffset) { - if (!deviceIsReady(DeviceId)) { - DP("Device %" PRId64 " is not ready\n", DeviceId); - return OMP_TGT_FAIL; - } + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceId, "%s", toString(DeviceOrErr.takeError()).c_str()); - DeviceTy &Device = *PM->Devices[DeviceId]; [[maybe_unused]] int Rc = target_activate_rr( - Device, MemorySize, VAddr, IsRecord, SaveOutput, ReqPtrArgOffset); + *DeviceOrErr, MemorySize, VAddr, IsRecord, SaveOutput, ReqPtrArgOffset); assert(Rc == OFFLOAD_SUCCESS && "__tgt_activate_record_replay unexpected failure!"); return OMP_TGT_SUCCESS; @@ -380,16 +381,19 @@ EXTERN int __tgt_target_kernel_replay(ident_t *Loc, int64_t DeviceId, DP("Not offloading to device %" PRId64 "\n", DeviceId); return OMP_TGT_FAIL; } - DeviceTy &Device = *PM->Devices[DeviceId]; + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceId, "%s", toString(DeviceOrErr.takeError()).c_str()); + /// RAII to establish tool anchors before and after target region OMPT_IF_BUILT(InterfaceRAII TargetRAII( RegionInterface.getCallbacks(), DeviceId, /* CodePtr */ OMPT_GET_RETURN_ADDRESS(0));) - AsyncInfoTy AsyncInfo(Device); - int Rc = target_replay(Loc, Device, HostPtr, DeviceMemory, DeviceMemorySize, - TgtArgs, TgtOffsets, NumArgs, NumTeams, ThreadLimit, - LoopTripCount, AsyncInfo); + AsyncInfoTy AsyncInfo(*DeviceOrErr); + int Rc = target_replay(Loc, *DeviceOrErr, HostPtr, DeviceMemory, + DeviceMemorySize, TgtArgs, TgtOffsets, NumArgs, + NumTeams, ThreadLimit, LoopTripCount, AsyncInfo); if (Rc == OFFLOAD_SUCCESS) Rc = AsyncInfo.synchronize(); handleTargetOutcome(Rc == OFFLOAD_SUCCESS, Loc); @@ -433,14 +437,11 @@ EXTERN void __tgt_set_info_flag(uint32_t NewInfoLevel) { } EXTERN int __tgt_print_device_info(int64_t DeviceId) { - // Make sure the device is ready. - if (!deviceIsReady(DeviceId)) { - DP("Device %" PRId64 " is not ready\n", DeviceId); - return OMP_TGT_FAIL; - } + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceId, "%s", toString(DeviceOrErr.takeError()).c_str()); - return PM->Devices[DeviceId]->printDeviceInfo( - PM->Devices[DeviceId]->RTLDeviceID); + return DeviceOrErr->printDeviceInfo(); } EXTERN void __tgt_target_nowait_query(void **AsyncHandle) { diff --git a/openmp/libomptarget/src/omptarget.cpp b/openmp/libomptarget/src/omptarget.cpp index 1fcadc018f72..2edbadaa6e02 100644 --- a/openmp/libomptarget/src/omptarget.cpp +++ b/openmp/libomptarget/src/omptarget.cpp @@ -16,6 +16,7 @@ #include "OpenMP/OMPT/Callback.h" #include "OpenMP/OMPT/Interface.h" #include "PluginManager.h" +#include "Shared/Debug.h" #include "Shared/EnvironmentVar.h" #include "device.h" #include "private.h" @@ -224,7 +225,7 @@ static int initLibrary(DeviceTy &Device) { AsyncInfoTy AsyncInfo(Device); void *DevPtr; Device.retrieveData(&DevPtr, CurrDeviceEntryAddr, sizeof(void *), - AsyncInfo); + AsyncInfo, /* Entry */ nullptr, &HDTTMap); if (AsyncInfo.synchronize() != OFFLOAD_SUCCESS) return OFFLOAD_FAIL; CurrDeviceEntryAddr = DevPtr; @@ -299,10 +300,11 @@ void handleTargetOutcome(bool Success, ident_t *Loc) { break; case OffloadPolicy::MANDATORY: if (!Success) { - if (getInfoLevel() & OMP_INFOTYPE_DUMP_TABLE) - for (auto &Device : PM->Devices) - dumpTargetPointerMappings(Loc, *Device); - else + if (getInfoLevel() & OMP_INFOTYPE_DUMP_TABLE) { + auto ExclusiveDevicesAccessor = PM->getExclusiveDevicesAccessor(); + for (auto &Device : PM->devices(ExclusiveDevicesAccessor)) + dumpTargetPointerMappings(Loc, Device); + } else FAILURE_MESSAGE("Consult https://openmp.llvm.org/design/Runtimes.html " "for debugging options.\n"); @@ -325,9 +327,11 @@ void handleTargetOutcome(bool Success, ident_t *Loc) { FATAL_MESSAGE0( 1, "failure of target construct while offloading is mandatory"); } else { - if (getInfoLevel() & OMP_INFOTYPE_DUMP_TABLE) - for (auto &Device : PM->Devices) - dumpTargetPointerMappings(Loc, *Device); + if (getInfoLevel() & OMP_INFOTYPE_DUMP_TABLE) { + auto ExclusiveDevicesAccessor = PM->getExclusiveDevicesAccessor(); + for (auto &Device : PM->devices(ExclusiveDevicesAccessor)) + dumpTargetPointerMappings(Loc, Device); + } } break; } @@ -369,21 +373,15 @@ bool checkDeviceAndCtors(int64_t &DeviceID, ident_t *Loc) { return true; } - // Is device ready? - if (!deviceIsReady(DeviceID)) { - REPORT("Device %" PRId64 " is not ready.\n", DeviceID); - handleTargetOutcome(false, Loc); - return true; - } - - // Get device info. - DeviceTy &Device = *PM->Devices[DeviceID]; + auto DeviceOrErr = PM->getDevice(DeviceID); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceID, "%s", toString(DeviceOrErr.takeError()).data()); // Check whether global data has been mapped for this device { - std::lock_guard LG( - Device.PendingGlobalsMtx); - if (initLibrary(Device) != OFFLOAD_SUCCESS) { + std::lock_guardPendingGlobalsMtx)> LG( + DeviceOrErr->PendingGlobalsMtx); + if (initLibrary(*DeviceOrErr) != OFFLOAD_SUCCESS) { REPORT("Failed to init globals on device %" PRId64 "\n", DeviceID); handleTargetOutcome(false, Loc); return true; @@ -415,13 +413,11 @@ void *targetAllocExplicit(size_t Size, int DeviceNum, int Kind, return Rc; } - if (!deviceIsReady(DeviceNum)) { - DP("%s returns NULL ptr\n", Name); - return NULL; - } + auto DeviceOrErr = PM->getDevice(DeviceNum); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceNum, "%s", toString(DeviceOrErr.takeError()).c_str()); - DeviceTy &Device = *PM->Devices[DeviceNum]; - Rc = Device.allocData(Size, nullptr, Kind); + Rc = DeviceOrErr->allocData(Size, nullptr, Kind); DP("%s returns device ptr " DPxMOD "\n", Name, DPxPTR(Rc)); return Rc; } @@ -443,12 +439,11 @@ void targetFreeExplicit(void *DevicePtr, int DeviceNum, int Kind, return; } - if (!deviceIsReady(DeviceNum)) { - DP("%s returns, nothing to do\n", Name); - return; - } + auto DeviceOrErr = PM->getDevice(DeviceNum); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceNum, "%s", toString(DeviceOrErr.takeError()).c_str()); - PM->Devices[DeviceNum]->deleteData(DevicePtr, Kind); + DeviceOrErr->deleteData(DevicePtr, Kind); DP("omp_target_free deallocated device ptr\n"); } @@ -464,26 +459,13 @@ void *targetLockExplicit(void *HostPtr, size_t Size, int DeviceNum, void *RC = NULL; - if (!deviceIsReady(DeviceNum)) { - DP("%s returns NULL ptr\n", Name); - return NULL; - } - - DeviceTy *DevicePtr = nullptr; - { - std::lock_guardRTLsMtx)> LG(PM->RTLsMtx); - - if (!PM->Devices[DeviceNum]) { - DP("%s returns, device %d not available\n", Name, DeviceNum); - return nullptr; - } - - DevicePtr = PM->Devices[DeviceNum].get(); - } + auto DeviceOrErr = PM->getDevice(DeviceNum); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceNum, "%s", toString(DeviceOrErr.takeError()).c_str()); int32_t Err = 0; - if (DevicePtr->RTL->data_lock) { - Err = DevicePtr->RTL->data_lock(DeviceNum, HostPtr, Size, &RC); + if (!DeviceOrErr->RTL->data_lock) { + Err = DeviceOrErr->RTL->data_lock(DeviceNum, HostPtr, Size, &RC); if (Err) { DP("Could not lock ptr %p\n", HostPtr); return nullptr; @@ -497,31 +479,12 @@ void targetUnlockExplicit(void *HostPtr, int DeviceNum, const char *Name) { TIMESCOPE(); DP("Call to %s for device %d unlocking\n", Name, DeviceNum); - DeviceTy *DevicePtr = nullptr; - { - std::lock_guardRTLsMtx)> LG(PM->RTLsMtx); - - // Don't check deviceIsReady as it can initialize the device if needed. - // Just check if DeviceNum exists as targetUnlockExplicit can be called - // during process exit/free (and it may have been already destroyed) and - // targetAllocExplicit will have already checked deviceIsReady anyway. - size_t DevicesSize = PM->Devices.size(); + auto DeviceOrErr = PM->getDevice(DeviceNum); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceNum, "%s", toString(DeviceOrErr.takeError()).c_str()); - if (DevicesSize <= (size_t)DeviceNum) { - DP("Device ID %d does not have a matching RTL\n", DeviceNum); - return; - } - - if (!PM->Devices[DeviceNum]) { - DP("%s returns, device %d not available\n", Name, DeviceNum); - return; - } - - DevicePtr = PM->Devices[DeviceNum].get(); - } // unlock RTLsMtx - - if (DevicePtr->RTL->data_unlock) - DevicePtr->RTL->data_unlock(DeviceNum, HostPtr); + if (!DeviceOrErr->RTL->data_unlock) + DeviceOrErr->RTL->data_unlock(DeviceNum, HostPtr); DP("%s returns\n", Name); } @@ -1446,8 +1409,12 @@ static int processDataBefore(ident_t *Loc, int64_t DeviceId, void *HostPtr, PrivateArgumentManagerTy &PrivateArgumentManager, AsyncInfoTy &AsyncInfo) { TIMESCOPE_WITH_NAME_AND_IDENT("mappingBeforeTargetRegion", Loc); - DeviceTy &Device = *PM->Devices[DeviceId]; - int Ret = targetDataBegin(Loc, Device, ArgNum, ArgBases, Args, ArgSizes, + + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceId, "%s", toString(DeviceOrErr.takeError()).c_str()); + + int Ret = targetDataBegin(Loc, *DeviceOrErr, ArgNum, ArgBases, Args, ArgSizes, ArgTypes, ArgNames, ArgMappers, AsyncInfo); if (Ret != OFFLOAD_SUCCESS) { REPORT("Call to targetDataBegin failed, abort target.\n"); @@ -1478,7 +1445,7 @@ static int processDataBefore(ident_t *Loc, int64_t DeviceId, void *HostPtr, uint64_t Delta = (uint64_t)HstPtrBegin - (uint64_t)HstPtrBase; void *TgtPtrBegin = (void *)((uintptr_t)TgtPtrBase + Delta); void *&PointerTgtPtrBegin = AsyncInfo.getVoidPtrLocation(); - TargetPointerResultTy TPR = Device.getTgtPtrBegin( + TargetPointerResultTy TPR = DeviceOrErr->getTgtPtrBegin( HstPtrVal, ArgSizes[I], /*UpdateRefCount=*/false, /*UseHoldRefCount=*/false); PointerTgtPtrBegin = TPR.TargetPointer; @@ -1495,8 +1462,9 @@ static int processDataBefore(ident_t *Loc, int64_t DeviceId, void *HostPtr, } DP("Update lambda reference (" DPxMOD ") -> [" DPxMOD "]\n", DPxPTR(PointerTgtPtrBegin), DPxPTR(TgtPtrBegin)); - Ret = Device.submitData(TgtPtrBegin, &PointerTgtPtrBegin, - sizeof(void *), AsyncInfo, TPR.getEntry()); + Ret = + DeviceOrErr->submitData(TgtPtrBegin, &PointerTgtPtrBegin, + sizeof(void *), AsyncInfo, TPR.getEntry()); if (Ret != OFFLOAD_SUCCESS) { REPORT("Copying data to device failed.\n"); return OFFLOAD_FAIL; @@ -1535,9 +1503,9 @@ static int processDataBefore(ident_t *Loc, int64_t DeviceId, void *HostPtr, } else { if (ArgTypes[I] & OMP_TGT_MAPTYPE_PTR_AND_OBJ) HstPtrBase = *reinterpret_cast(HstPtrBase); - TPR = Device.getTgtPtrBegin(HstPtrBegin, ArgSizes[I], - /*UpdateRefCount=*/false, - /*UseHoldRefCount=*/false); + TPR = DeviceOrErr->getTgtPtrBegin(HstPtrBegin, ArgSizes[I], + /*UpdateRefCount=*/false, + /*UseHoldRefCount=*/false); TgtPtrBegin = TPR.TargetPointer; TgtBaseOffset = (intptr_t)HstPtrBase - (intptr_t)HstPtrBegin; #ifdef OMPTARGET_DEBUG @@ -1573,10 +1541,12 @@ static int processDataAfter(ident_t *Loc, int64_t DeviceId, void *HostPtr, PrivateArgumentManagerTy &PrivateArgumentManager, AsyncInfoTy &AsyncInfo) { TIMESCOPE_WITH_NAME_AND_IDENT("mappingAfterTargetRegion", Loc); - DeviceTy &Device = *PM->Devices[DeviceId]; + auto DeviceOrErr = PM->getDevice(DeviceId); + if (!DeviceOrErr) + FATAL_MESSAGE(DeviceId, "%s", toString(DeviceOrErr.takeError()).c_str()); // Move data from device. - int Ret = targetDataEnd(Loc, Device, ArgNum, ArgBases, Args, ArgSizes, + int Ret = targetDataEnd(Loc, *DeviceOrErr, ArgNum, ArgBases, Args, ArgSizes, ArgTypes, ArgNames, ArgMappers, AsyncInfo); if (Ret != OFFLOAD_SUCCESS) { REPORT("Call to targetDataEnd failed, abort target.\n"); diff --git a/openmp/libomptarget/src/rtl.cpp b/openmp/libomptarget/src/rtl.cpp index 5eb1c553df49..27db7034d895 100644 --- a/openmp/libomptarget/src/rtl.cpp +++ b/openmp/libomptarget/src/rtl.cpp @@ -51,7 +51,6 @@ __attribute__((constructor(101))) void init() { PM->init(); Profiler::get(); - PM->registerDelayedLibraries(); } __attribute__((destructor(101))) void deinit() { diff --git a/openmp/libomptarget/test/Inputs/declare_indirect_func.c b/openmp/libomptarget/test/Inputs/declare_indirect_func.c new file mode 100644 index 000000000000..20ac6617649a --- /dev/null +++ b/openmp/libomptarget/test/Inputs/declare_indirect_func.c @@ -0,0 +1,3 @@ + +int func() { return 42; } +#pragma omp declare target indirect to(func) diff --git a/openmp/libomptarget/test/Inputs/empty.c b/openmp/libomptarget/test/Inputs/empty.c new file mode 100644 index 000000000000..8b137891791f --- /dev/null +++ b/openmp/libomptarget/test/Inputs/empty.c @@ -0,0 +1 @@ + diff --git a/openmp/libomptarget/test/offloading/barrier_fence.c b/openmp/libomptarget/test/offloading/barrier_fence.c index 5d1096478ed9..a0b672fb1a84 100644 --- a/openmp/libomptarget/test/offloading/barrier_fence.c +++ b/openmp/libomptarget/test/offloading/barrier_fence.c @@ -7,6 +7,8 @@ // UNSUPPORTED: aarch64-unknown-linux-gnu-LTO // UNSUPPORTED: x86_64-pc-linux-gnu // UNSUPPORTED: x86_64-pc-linux-gnu-LTO +// UNSUPPORTED: amdgcn-amd-amdhsa +// UNSUPPORTED: amdgcn-amd-amdhsa-LTO #include #include diff --git a/openmp/libomptarget/test/offloading/bug60119.c b/openmp/libomptarget/test/offloading/bug60119.c new file mode 100644 index 000000000000..e32f1ccd5988 --- /dev/null +++ b/openmp/libomptarget/test/offloading/bug60119.c @@ -0,0 +1,6 @@ +// RUN: %clang-generic -fPIC -shared %S/../Inputs/empty.c -o %T/liba.so +// RUN: %clang-generic -fPIC -shared %S/../Inputs/empty.c -o %T/libb.so +// RUN: %clang-generic -rpath %T -L %T -l a -l b %s -o %t +// RUN: %t + +int main() {} diff --git a/openmp/libomptarget/test/offloading/shared_lib_fp_mapping.c b/openmp/libomptarget/test/offloading/shared_lib_fp_mapping.c new file mode 100644 index 000000000000..a98a84ccceaa --- /dev/null +++ b/openmp/libomptarget/test/offloading/shared_lib_fp_mapping.c @@ -0,0 +1,22 @@ +// clang-format off +// RUN: %clang-generic -fPIC -shared %S/../Inputs/declare_indirect_func.c -o %T/liba.so -fopenmp-version=51 +// RUN: %libomptarget-compile-generic -rpath %T -L %T -l a -o %t -fopenmp-version=51 +// RUN: env LIBOMPTARGET_INFO=32 %t 2>&1 | %fcheck-generic +// clang-format on + +#include + +extern int func(); // Provided in liba.so, returns 42 +typedef int (*fp_t)(); + +int main() { + int x = 0; + fp_t fp = &func; + printf("TARGET\n"); +#pragma omp target map(from : x) + x = fp(); + // CHECK: Copying data from device to host, {{.*}} Size=8 + // CHECK: Copying data from device to host, {{.*}} Size=4 + // CHECK: 42 + printf("%i\n", x); +} diff --git a/polly/include/polly/CodeGen/CodegenCleanup.h b/polly/include/polly/CodeGen/CodegenCleanup.h deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/polly/lib/External/isl/interface/extract_interface.cc b/polly/lib/External/isl/interface/extract_interface.cc index b94847c59035..9bd20b0c72c6 100644 --- a/polly/lib/External/isl/interface/extract_interface.cc +++ b/polly/lib/External/isl/interface/extract_interface.cc @@ -47,8 +47,8 @@ #endif #include #include -#include #include +#include #include #include #include diff --git a/polly/test/CodeGen/MemAccess/create_arrays_heap.ll b/polly/test/CodeGen/MemAccess/create_arrays_heap.ll index d2554d24711d..1202d21998c9 100644 --- a/polly/test/CodeGen/MemAccess/create_arrays_heap.ll +++ b/polly/test/CodeGen/MemAccess/create_arrays_heap.ll @@ -72,17 +72,17 @@ for.body6: ; preds = %for.body6, %for.con %0 = load double, ptr %arrayidx8, align 8 %mul = fmul double %0, %beta store double %mul, ptr %arrayidx12, align 8 - %indvars.iv.next = or i64 %indvars.iv, 1 + %indvars.iv.next = or disjoint i64 %indvars.iv, 1 %arrayidx8.1 = getelementptr inbounds [1024 x double], ptr %A, i64 %indvars.iv35, i64 %indvars.iv.next %1 = load double, ptr %arrayidx8.1, align 8 %mul.1 = fmul double %1, %beta store double %mul.1, ptr %arrayidx12, align 8 - %indvars.iv.next.1 = or i64 %indvars.iv, 2 + %indvars.iv.next.1 = or disjoint i64 %indvars.iv, 2 %arrayidx8.2 = getelementptr inbounds [1024 x double], ptr %A, i64 %indvars.iv35, i64 %indvars.iv.next.1 %2 = load double, ptr %arrayidx8.2, align 8 %mul.2 = fmul double %2, %beta store double %mul.2, ptr %arrayidx12, align 8 - %indvars.iv.next.2 = or i64 %indvars.iv, 3 + %indvars.iv.next.2 = or disjoint i64 %indvars.iv, 3 %arrayidx8.3 = getelementptr inbounds [1024 x double], ptr %A, i64 %indvars.iv35, i64 %indvars.iv.next.2 %3 = load double, ptr %arrayidx8.3, align 8 %mul.3 = fmul double %3, %beta diff --git a/polly/test/ForwardOpTree/out-of-quota1.ll b/polly/test/ForwardOpTree/out-of-quota1.ll index c31ee51d519f..7afdb8e60244 100644 --- a/polly/test/ForwardOpTree/out-of-quota1.ll +++ b/polly/test/ForwardOpTree/out-of-quota1.ll @@ -25,7 +25,7 @@ for.body215: %4 = shl nuw nsw i64 %indvars.iv1921, 1 %arrayidx230 = getelementptr inbounds %struct.storable_picture.5.221.389.509.629.797.917.1133.1205.1445.1469.1517.1541.1565.1589.1661.1685.1757.1781.1829.1877.2165.2285.2405.2429.2453.2477.2501.2525.2837.2861.2885.2909.4417.1.7.13.17.23.29.55.57.59.61.187, ptr %1, i64 0, i32 5, i64 %indvars.iv1926, i64 1, i64 %4 store i64 undef, ptr %arrayidx230, align 8 - %5 = or i64 %4, 1 + %5 = or disjoint i64 %4, 1 %arrayidx248 = getelementptr inbounds %struct.storable_picture.5.221.389.509.629.797.917.1133.1205.1445.1469.1517.1541.1565.1589.1661.1685.1757.1781.1829.1877.2165.2285.2405.2429.2453.2477.2501.2525.2837.2861.2885.2909.4417.1.7.13.17.23.29.55.57.59.61.187, ptr %1, i64 0, i32 5, i64 %indvars.iv1926, i64 1, i64 %5 store i64 undef, ptr %arrayidx248, align 8 %arrayidx264 = getelementptr inbounds %struct.storable_picture.5.221.389.509.629.797.917.1133.1205.1445.1469.1517.1541.1565.1589.1661.1685.1757.1781.1829.1877.2165.2285.2405.2429.2453.2477.2501.2525.2837.2861.2885.2909.4417.1.7.13.17.23.29.55.57.59.61.187, ptr %2, i64 0, i32 5, i64 %indvars.iv1926, i64 1, i64 %4 diff --git a/polly/test/JSONExporter/ImportArrays/ImportArrays-Negative-size.ll b/polly/test/JSONExporter/ImportArrays/ImportArrays-Negative-size.ll index 70652a1918b4..2a03197f1c1b 100644 --- a/polly/test/JSONExporter/ImportArrays/ImportArrays-Negative-size.ll +++ b/polly/test/JSONExporter/ImportArrays/ImportArrays-Negative-size.ll @@ -43,17 +43,17 @@ for.body6: ; preds = %for.body6, %for.con %0 = load double, ptr %arrayidx8, align 8 %mul = fmul double %0, %beta store double %mul, ptr %arrayidx12, align 8 - %indvars.iv.next = or i64 %indvars.iv, 1 + %indvars.iv.next = or disjoint i64 %indvars.iv, 1 %arrayidx8.1 = getelementptr inbounds [1024 x double], ptr %A, i64 %indvars.iv35, i64 %indvars.iv.next %1 = load double, ptr %arrayidx8.1, align 8 %mul.1 = fmul double %1, %beta store double %mul.1, ptr %arrayidx12, align 8 - %indvars.iv.next.1 = or i64 %indvars.iv, 2 + %indvars.iv.next.1 = or disjoint i64 %indvars.iv, 2 %arrayidx8.2 = getelementptr inbounds [1024 x double], ptr %A, i64 %indvars.iv35, i64 %indvars.iv.next.1 %2 = load double, ptr %arrayidx8.2, align 8 %mul.2 = fmul double %2, %beta store double %mul.2, ptr %arrayidx12, align 8 - %indvars.iv.next.2 = or i64 %indvars.iv, 3 + %indvars.iv.next.2 = or disjoint i64 %indvars.iv, 3 %arrayidx8.3 = getelementptr inbounds [1024 x double], ptr %A, i64 %indvars.iv35, i64 %indvars.iv.next.2 %3 = load double, ptr %arrayidx8.3, align 8 %mul.3 = fmul double %3, %beta diff --git a/polly/test/ScopInfo/multi-scop.ll b/polly/test/ScopInfo/multi-scop.ll index 186aee832946..e26c8c7bae10 100644 --- a/polly/test/ScopInfo/multi-scop.ll +++ b/polly/test/ScopInfo/multi-scop.ll @@ -20,7 +20,7 @@ for.end: ; preds = %for.body, %entry.sp for.body81: ; preds = %for.body81, %for.end %j.19 = phi i32 [ %shl, %for.end ], [ %add169, %for.body81 ] - %add13710 = or i32 %j.19, 1 + %add13710 = or disjoint i32 %j.19, 1 %idxprom138 = sext i32 %add13710 to i64 %arrayidx139 = getelementptr inbounds double, ptr %a, i64 %idxprom138 store double undef, ptr %arrayidx139, align 8 diff --git a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel index 4cef996d9c82..9d5dc8edebcc 100644 --- a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel @@ -468,7 +468,7 @@ genrule( "echo '#define CLANG_VERSION_MAJOR_STRING \"{major}\"' >> $@\n" + "echo '#define CLANG_VERSION_MINOR {minor}' >> $@\n" + "echo '#define CLANG_VERSION_PATCHLEVEL {patch}' >> $@\n" + - "echo '#define CLANG_VERSION_STRING \"{vers}\"' >> $@\n" + "echo '#define CLANG_VERSION_STRING \"{vers}git\"' >> $@\n" ).format( major = LLVM_VERSION_MAJOR, minor = LLVM_VERSION_MINOR, diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 46d81987e7b3..95d6f9d220c2 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -439,9 +439,9 @@ libc_support_library( name = "__support_integer_utils", hdrs = ["src/__support/integer_utils.h"], deps = [ - ":__support_bit", ":__support_common", ":__support_cpp_type_traits", + ":__support_math_extras", ":__support_number_pair", ], ) @@ -450,8 +450,8 @@ libc_support_library( name = "__support_uint", hdrs = ["src/__support/UInt.h"], deps = [ - ":__support_bit", ":__support_cpp_array", + ":__support_cpp_bit", ":__support_cpp_limits", ":__support_cpp_optional", ":__support_cpp_type_traits", @@ -536,8 +536,8 @@ libc_support_library( "src/__support/str_to_float.h", ], deps = [ - ":__support_bit", ":__support_common", + ":__support_cpp_bit", ":__support_cpp_limits", ":__support_cpp_optional", ":__support_ctype_utils", @@ -586,15 +586,6 @@ libc_support_library( ], ) -libc_support_library( - name = "__support_bit", - hdrs = ["src/__support/bit.h"], - deps = [ - ":__support_cpp_type_traits", - ":__support_macros_attributes", - ], -) - libc_support_library( name = "__support_math_extras", hdrs = ["src/__support/math_extras.h"], @@ -609,8 +600,8 @@ libc_support_library( name = "__support_fputil_generic_fmod", hdrs = ["src/__support/FPUtil/generic/FMod.h"], deps = [ - ":__support_bit", ":__support_common", + ":__support_cpp_bit", ":__support_cpp_limits", ":__support_cpp_type_traits", ":__support_fputil_fenv_impl", @@ -682,7 +673,6 @@ libc_support_library( hdrs = ["src/__support/FPUtil/FPBits.h"], textual_hdrs = ["src/__support/FPUtil/x86_64/LongDoubleBits.h"], deps = [ - ":__support_bit", ":__support_common", ":__support_cpp_bit", ":__support_cpp_type_traits", @@ -710,7 +700,6 @@ libc_support_library( name = "__support_fputil_hypot", hdrs = ["src/__support/FPUtil/Hypot.h"], deps = [ - ":__support_bit", ":__support_common", ":__support_cpp_bit", ":__support_cpp_type_traits", @@ -781,7 +770,6 @@ libc_support_library( name = "__support_fputil_sqrt", hdrs = sqrt_hdrs, deps = [ - ":__support_bit", ":__support_common", ":__support_cpp_bit", ":__support_cpp_type_traits", @@ -809,7 +797,6 @@ libc_support_library( # doesn't support FMA, so they can't be compiled on their own. textual_hdrs = fma_platform_hdrs, deps = [ - ":__support_bit", ":__support_cpp_bit", ":__support_cpp_type_traits", ":__support_fputil_fenv_impl", diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel index 23071c292b82..a973e6541da0 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel @@ -10,12 +10,6 @@ package(default_visibility = ["//visibility:public"]) licenses(["notice"]) -libc_test( - name = "bit_test", - srcs = ["bit_test.cpp"], - deps = ["//libc:__support_bit"], -) - libc_test( name = "math_extras_test", srcs = ["math_extras_test.cpp"], diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl b/utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl index 2843270d414a..1dffafdd5394 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl +++ b/utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl @@ -25,7 +25,6 @@ def math_test(name, hdrs = [], deps = [], **kwargs): srcs = [test_name + ".cpp"] + hdrs, libc_function_deps = ["//libc:func_name".replace("func_name", name)], deps = [ - "//libc:__support_bit", "//libc:__support_fputil_basic_operations", "//libc:__support_fputil_fenv_impl", "//libc:__support_fputil_float_properties", diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 3a9bfa0644c4..7b64a4956e1e 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -3237,6 +3237,7 @@ cc_library( ":InferTypeOpInterface", ":MeshIncGen", ":Support", + ":ViewLikeInterface", "//llvm:Support", ], ) @@ -5567,6 +5568,7 @@ cc_library( ":NVVMDialect", ":Pass", ":Transforms", + ":VectorToLLVM", "//llvm:Support", ], ) @@ -8379,6 +8381,18 @@ cc_library( ], ) +cc_library( + name = "SPIRVToLLVMIRTranslation", + srcs = glob(["lib/Target/LLVMIR/Dialect/SPIRV/*.cpp"]), + hdrs = glob(["include/mlir/Target/LLVMIR/Dialect/SPIRV/*.h"]), + includes = ["include"], + deps = [ + ":IR", + ":SPIRVDialect", + ":ToLLVMIRTranslation", + ], +) + cc_library( name = "GPUToLLVMIRTranslation", srcs = [ @@ -8515,6 +8529,7 @@ cc_library( ":OpenMPToLLVMIRTranslation", ":ROCDLTarget", ":ROCDLToLLVMIRTranslation", + ":SPIRVToLLVMIRTranslation", ":X86VectorToLLVMIRTranslation", ], ) diff --git a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel index 3f43c3f2365d..5d5c4b450a0b 100644 --- a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel @@ -41,6 +41,7 @@ expand_template( "@MLIR_ENABLE_CUDA_RUNNER@": "0", "@MLIR_ENABLE_ROCM_CONVERSIONS@": "0", "@MLIR_ENABLE_ROCM_RUNNER@": "0", + "@MLIR_ENABLE_SYCL_RUNNER@": "0", "@MLIR_ENABLE_SPIRV_CPU_RUNNER@": "0", "@MLIR_ENABLE_VULKAN_RUNNER@": "0", "@MLIR_ENABLE_BINDINGS_PYTHON@": "0", -- GitLab