Commit ff88e1c9 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Bjorn Andersson
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arm64: dts: qcom: msm8998: Add DPU1 nodes 



Add the required nodes to support the display hardware on msm8998.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
[konrad: update the commit msg and AGdR's email, rebase]
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230805-topic-8998_dpu-v1-1-9d402dc1ecc0@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent bd3b4ac1

arch/arm64/boot/dts/qcom/msm8998.dtsi

+279 −4
Original line number Diff line number Diff line
@@ -316,6 +316,25 @@ scm { 
		};

	};



	dsi_opp_table: opp-table-dsi {

		compatible = "operating-points-v2";



		opp-131250000 {

			opp-hz = /bits/ 64 <131250000>;

			required-opps = <&rpmpd_opp_low_svs>;

		};



		opp-210000000 {

			opp-hz = /bits/ 64 <210000000>;

			required-opps = <&rpmpd_opp_svs>;

		};



		opp-312500000 {

			opp-hz = /bits/ 64 <312500000>;

			required-opps = <&rpmpd_opp_nom>;

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";
@@ -2728,16 +2747,272 @@ mmcc: clock-controller@c8c0000 { 
				      "gpll0_div";

			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,

				 <&gcc GCC_MMSS_GPLL0_CLK>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <&mdss_dsi0_phy 1>,

				 <&mdss_dsi0_phy 0>,

				 <&mdss_dsi1_phy 1>,

				 <&mdss_dsi1_phy 0>,

				 <0>,

				 <0>,

				 <0>,

				 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;

		};



		mdss: display-subsystem@c900000 {

			compatible = "qcom,msm8998-mdss";

			reg = <0x0c900000 0x1000>;

			reg-names = "mdss";



			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <1>;



			clocks = <&mmcc MDSS_AHB_CLK>,

				 <&mmcc MDSS_AXI_CLK>,

				 <&mmcc MDSS_MDP_CLK>;

			clock-names = "iface",

				      "bus",

				      "core";



			power-domains = <&mmcc MDSS_GDSC>;

			iommus = <&mmss_smmu 0>;



			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			status = "disabled";



			mdss_mdp: display-controller@c901000 {

				compatible = "qcom,msm8998-dpu";

				reg = <0x0c901000 0x8f000>,

				      <0x0c9a8e00 0xf0>,

				      <0x0c9b0000 0x2008>,

				      <0x0c9b8000 0x1040>;

				reg-names = "mdp",

					    "regdma",

					    "vbif",

					    "vbif_nrt";



				interrupt-parent = <&mdss>;

				interrupts = <0>;



				clocks = <&mmcc MDSS_AHB_CLK>,

					 <&mmcc MDSS_AXI_CLK>,

					 <&mmcc MNOC_AHB_CLK>,

					 <&mmcc MDSS_MDP_CLK>,

					 <&mmcc MDSS_VSYNC_CLK>;

				clock-names = "iface",

					      "bus",

					      "mnoc",

					      "core",

					      "vsync";



				assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;

				assigned-clock-rates = <19200000>;



				operating-points-v2 = <&mdp_opp_table>;

				power-domains = <&rpmpd MSM8998_VDDMX>;



				mdp_opp_table: opp-table {

					compatible = "operating-points-v2";



					opp-171430000 {

						opp-hz = /bits/ 64 <171430000>;

						required-opps = <&rpmpd_opp_low_svs>;

					};



					opp-275000000 {

						opp-hz = /bits/ 64 <275000000>;

						required-opps = <&rpmpd_opp_svs>;

					};



					opp-330000000 {

						opp-hz = /bits/ 64 <330000000>;

						required-opps = <&rpmpd_opp_nom>;

					};



					opp-412500000 {

						opp-hz = /bits/ 64 <412500000>;

						required-opps = <&rpmpd_opp_turbo>;

					};

				};



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						dpu_intf1_out: endpoint {

							remote-endpoint = <&mdss_dsi0_in>;

						};

					};



					port@1 {

						reg = <1>;



						dpu_intf2_out: endpoint {

							remote-endpoint = <&mdss_dsi1_in>;

						};

					};

				};

			};



			mdss_dsi0: dsi@c994000 {

				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";

				reg = <0x0c994000 0x400>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <4>;



				clocks = <&mmcc MDSS_BYTE0_CLK>,

					 <&mmcc MDSS_BYTE0_INTF_CLK>,

					 <&mmcc MDSS_PCLK0_CLK>,

					 <&mmcc MDSS_ESC0_CLK>,

					 <&mmcc MDSS_AHB_CLK>,

					 <&mmcc MDSS_AXI_CLK>;

				clock-names = "byte",

					      "byte_intf",

					      "pixel",

					      "core",

					      "iface",

					      "bus";

				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,

						  <&mmcc PCLK0_CLK_SRC>;

				assigned-clock-parents = <&mdss_dsi0_phy 0>,

							 <&mdss_dsi0_phy 1>;



				operating-points-v2 = <&dsi_opp_table>;

				power-domains = <&rpmpd MSM8998_VDDCX>;



				phys = <&mdss_dsi0_phy>;

				phy-names = "dsi";



				#address-cells = <1>;

				#size-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						mdss_dsi0_in: endpoint {

							remote-endpoint = <&dpu_intf1_out>;

						};

					};



					port@1 {

						reg = <1>;



						mdss_dsi0_out: endpoint {

						};

					};

				};

			};



			mdss_dsi0_phy: phy@c994400 {

				compatible = "qcom,dsi-phy-10nm-8998";

				reg = <0x0c994400 0x200>,

				      <0x0c994600 0x280>,

				      <0x0c994a00 0x1e0>;

				reg-names = "dsi_phy",

					    "dsi_phy_lane",

					    "dsi_pll";



				clocks = <&mmcc MDSS_AHB_CLK>,

					 <&rpmcc RPM_SMD_XO_CLK_SRC>;

				clock-names = "iface", "ref";



				#clock-cells = <1>;

				#phy-cells = <0>;



				status = "disabled";

			};



			mdss_dsi1: dsi@c996000 {

				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";

				reg = <0x0c996000 0x400>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <5>;



				clocks = <&mmcc MDSS_BYTE1_CLK>,

					 <&mmcc MDSS_BYTE1_INTF_CLK>,

					 <&mmcc MDSS_PCLK1_CLK>,

					 <&mmcc MDSS_ESC1_CLK>,

					 <&mmcc MDSS_AHB_CLK>,

					 <&mmcc MDSS_AXI_CLK>;

				clock-names = "byte",

					      "byte_intf",

					      "pixel",

					      "core",

					      "iface",

					      "bus";

				assigned-clocks = <&mmcc BYTE1_CLK_SRC>,

						  <&mmcc PCLK1_CLK_SRC>;

				assigned-clock-parents = <&mdss_dsi1_phy 0>,

							 <&mdss_dsi1_phy 1>;



				operating-points-v2 = <&dsi_opp_table>;

				power-domains = <&rpmpd MSM8998_VDDCX>;



				phys = <&mdss_dsi1_phy>;

				phy-names = "dsi";



				#address-cells = <1>;

				#size-cells = <0>;



				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						mdss_dsi1_in: endpoint {

							remote-endpoint = <&dpu_intf2_out>;

						};

					};



					port@1 {

						reg = <1>;



						mdss_dsi1_out: endpoint {

						};

					};

				};

			};



			mdss_dsi1_phy: phy@c996400 {

				compatible = "qcom,dsi-phy-10nm-8998";

				reg = <0x0c996400 0x200>,

				      <0x0c996600 0x280>,

				      <0x0c996a00 0x10e>;

				reg-names = "dsi_phy",

					    "dsi_phy_lane",

					    "dsi_pll";



				clocks = <&mmcc MDSS_AHB_CLK>,

					 <&rpmcc RPM_SMD_XO_CLK_SRC>;

				clock-names = "iface",

					      "ref";



				#clock-cells = <1>;

				#phy-cells = <0>;



				status = "disabled";

			};

		};



		mmss_smmu: iommu@cd00000 {

			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";

			reg = <0x0cd00000 0x40000>;