Commit ff0f23dd authored by Manjunath Hadli's avatar Manjunath Hadli Committed by Mauro Carvalho Chehab
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[media] davinci vpbe: OSD(On Screen Display) block 



This patch implements the functionality of the OSD block
of the VPBE. The OSD in total supports 4 planes or Video
sources - 2 mainly RGB and 2 Video. The patch implements general
handling of all the planes, with specific emphasis on the Video
plane capabilities as the Video planes are supported through the
V4L2 driver.

Signed-off-by: default avatarManjunath Hadli <manjunath.hadli@ti.com>
Acked-by: default avatarMuralidharan Karicheri <m-karicheri2@ti.com>
Acked-by: default avatarHans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 66715cdc

drivers/media/video/davinci/vpbe_osd.c

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drivers/media/video/davinci/vpbe_osd_regs.h

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/*

 * Copyright (C) 2006-2010 Texas Instruments Inc

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation version 2.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA

 */

#ifndef _VPBE_OSD_REGS_H

#define _VPBE_OSD_REGS_H



/* VPBE Global Registers */

#define VPBE_PID				0x0

#define VPBE_PCR				0x4



/* VPSS CLock Registers */

#define VPSSCLK_PID				0x00

#define VPSSCLK_CLKCTRL				0x04



/* VPSS Buffer Logic Registers */

#define VPSSBL_PID				0x00

#define VPSSBL_PCR				0x04

#define VPSSBL_BCR				0x08

#define VPSSBL_INTSTAT				0x0C

#define VPSSBL_INTSEL				0x10

#define VPSSBL_EVTSEL				0x14

#define VPSSBL_MEMCTRL				0x18

#define VPSSBL_CCDCMUX				0x1C



/* DM365 ISP5 system configuration */

#define ISP5_PID				0x0

#define ISP5_PCCR				0x4

#define ISP5_BCR				0x8

#define ISP5_INTSTAT				0xC

#define ISP5_INTSEL1				0x10

#define ISP5_INTSEL2				0x14

#define ISP5_INTSEL3				0x18

#define ISP5_EVTSEL				0x1c

#define ISP5_CCDCMUX				0x20



/* VPBE On-Screen Display Subsystem Registers (OSD) */

#define OSD_MODE				0x00

#define OSD_VIDWINMD				0x04

#define OSD_OSDWIN0MD				0x08

#define OSD_OSDWIN1MD				0x0C

#define OSD_OSDATRMD				0x0C

#define OSD_RECTCUR				0x10

#define OSD_VIDWIN0OFST				0x18

#define OSD_VIDWIN1OFST				0x1C

#define OSD_OSDWIN0OFST				0x20

#define OSD_OSDWIN1OFST				0x24

#define OSD_VIDWINADH				0x28

#define OSD_VIDWIN0ADL				0x2C

#define OSD_VIDWIN0ADR				0x2C

#define OSD_VIDWIN1ADL				0x30

#define OSD_VIDWIN1ADR				0x30

#define OSD_OSDWINADH				0x34

#define OSD_OSDWIN0ADL				0x38

#define OSD_OSDWIN0ADR				0x38

#define OSD_OSDWIN1ADL				0x3C

#define OSD_OSDWIN1ADR				0x3C

#define OSD_BASEPX				0x40

#define OSD_BASEPY				0x44

#define OSD_VIDWIN0XP				0x48

#define OSD_VIDWIN0YP				0x4C

#define OSD_VIDWIN0XL				0x50

#define OSD_VIDWIN0YL				0x54

#define OSD_VIDWIN1XP				0x58

#define OSD_VIDWIN1YP				0x5C

#define OSD_VIDWIN1XL				0x60

#define OSD_VIDWIN1YL				0x64

#define OSD_OSDWIN0XP				0x68

#define OSD_OSDWIN0YP				0x6C

#define OSD_OSDWIN0XL				0x70

#define OSD_OSDWIN0YL				0x74

#define OSD_OSDWIN1XP				0x78

#define OSD_OSDWIN1YP				0x7C

#define OSD_OSDWIN1XL				0x80

#define OSD_OSDWIN1YL				0x84

#define OSD_CURXP				0x88

#define OSD_CURYP				0x8C

#define OSD_CURXL				0x90

#define OSD_CURYL				0x94

#define OSD_W0BMP01				0xA0

#define OSD_W0BMP23				0xA4

#define OSD_W0BMP45				0xA8

#define OSD_W0BMP67				0xAC

#define OSD_W0BMP89				0xB0

#define OSD_W0BMPAB				0xB4

#define OSD_W0BMPCD				0xB8

#define OSD_W0BMPEF				0xBC

#define OSD_W1BMP01				0xC0

#define OSD_W1BMP23				0xC4

#define OSD_W1BMP45				0xC8

#define OSD_W1BMP67				0xCC

#define OSD_W1BMP89				0xD0

#define OSD_W1BMPAB				0xD4

#define OSD_W1BMPCD				0xD8

#define OSD_W1BMPEF				0xDC

#define OSD_VBNDRY				0xE0

#define OSD_EXTMODE				0xE4

#define OSD_MISCCTL				0xE8

#define OSD_CLUTRAMYCB				0xEC

#define OSD_CLUTRAMCR				0xF0

#define OSD_TRANSPVAL				0xF4

#define OSD_TRANSPVALL				0xF4

#define OSD_TRANSPVALU				0xF8

#define OSD_TRANSPBMPIDX			0xFC

#define OSD_PPVWIN0ADR				0xFC



/* bit definitions */

#define VPBE_PCR_VENC_DIV			(1 << 1)

#define VPBE_PCR_CLK_OFF			(1 << 0)



#define VPSSBL_INTSTAT_HSSIINT			(1 << 14)

#define VPSSBL_INTSTAT_CFALDINT			(1 << 13)

#define VPSSBL_INTSTAT_IPIPE_INT5		(1 << 12)

#define VPSSBL_INTSTAT_IPIPE_INT4		(1 << 11)

#define VPSSBL_INTSTAT_IPIPE_INT3		(1 << 10)

#define VPSSBL_INTSTAT_IPIPE_INT2		(1 << 9)

#define VPSSBL_INTSTAT_IPIPE_INT1		(1 << 8)

#define VPSSBL_INTSTAT_IPIPE_INT0		(1 << 7)

#define VPSSBL_INTSTAT_IPIPEIFINT		(1 << 6)

#define VPSSBL_INTSTAT_OSDINT			(1 << 5)

#define VPSSBL_INTSTAT_VENCINT			(1 << 4)

#define VPSSBL_INTSTAT_H3AINT			(1 << 3)

#define VPSSBL_INTSTAT_CCDC_VDINT2		(1 << 2)

#define VPSSBL_INTSTAT_CCDC_VDINT1		(1 << 1)

#define VPSSBL_INTSTAT_CCDC_VDINT0		(1 << 0)



/* DM365 ISP5 bit definitions */

#define ISP5_INTSTAT_VENCINT			(1 << 21)

#define ISP5_INTSTAT_OSDINT			(1 << 20)



/* VMOD TVTYP options for HDMD=0 */

#define SDTV_NTSC				0

#define SDTV_PAL				1

/* VMOD TVTYP options for HDMD=1 */

#define HDTV_525P				0

#define HDTV_625P				1

#define HDTV_1080I				2

#define HDTV_720P				3



#define OSD_MODE_CS				(1 << 15)

#define OSD_MODE_OVRSZ				(1 << 14)

#define OSD_MODE_OHRSZ				(1 << 13)

#define OSD_MODE_EF				(1 << 12)

#define OSD_MODE_VVRSZ				(1 << 11)

#define OSD_MODE_VHRSZ				(1 << 10)

#define OSD_MODE_FSINV				(1 << 9)

#define OSD_MODE_BCLUT				(1 << 8)

#define OSD_MODE_CABG_SHIFT			0

#define OSD_MODE_CABG				(0xff << 0)



#define OSD_VIDWINMD_VFINV			(1 << 15)

#define OSD_VIDWINMD_V1EFC			(1 << 14)

#define OSD_VIDWINMD_VHZ1_SHIFT			12

#define OSD_VIDWINMD_VHZ1			(3 << 12)

#define OSD_VIDWINMD_VVZ1_SHIFT			10

#define OSD_VIDWINMD_VVZ1			(3 << 10)

#define OSD_VIDWINMD_VFF1			(1 << 9)

#define OSD_VIDWINMD_ACT1			(1 << 8)

#define OSD_VIDWINMD_V0EFC			(1 << 6)

#define OSD_VIDWINMD_VHZ0_SHIFT			4

#define OSD_VIDWINMD_VHZ0			(3 << 4)

#define OSD_VIDWINMD_VVZ0_SHIFT			2

#define OSD_VIDWINMD_VVZ0			(3 << 2)

#define OSD_VIDWINMD_VFF0			(1 << 1)

#define OSD_VIDWINMD_ACT0			(1 << 0)



#define OSD_OSDWIN0MD_ATN0E			(1 << 14)

#define OSD_OSDWIN0MD_RGB0E			(1 << 13)

#define OSD_OSDWIN0MD_BMP0MD_SHIFT		13

#define OSD_OSDWIN0MD_BMP0MD			(3 << 13)

#define OSD_OSDWIN0MD_CLUTS0			(1 << 12)

#define OSD_OSDWIN0MD_OHZ0_SHIFT		10

#define OSD_OSDWIN0MD_OHZ0			(3 << 10)

#define OSD_OSDWIN0MD_OVZ0_SHIFT		8

#define OSD_OSDWIN0MD_OVZ0			(3 << 8)

#define OSD_OSDWIN0MD_BMW0_SHIFT		6

#define OSD_OSDWIN0MD_BMW0			(3 << 6)

#define OSD_OSDWIN0MD_BLND0_SHIFT		3

#define OSD_OSDWIN0MD_BLND0			(7 << 3)

#define OSD_OSDWIN0MD_TE0			(1 << 2)

#define OSD_OSDWIN0MD_OFF0			(1 << 1)

#define OSD_OSDWIN0MD_OACT0			(1 << 0)



#define OSD_OSDWIN1MD_OASW			(1 << 15)

#define OSD_OSDWIN1MD_ATN1E			(1 << 14)

#define OSD_OSDWIN1MD_RGB1E			(1 << 13)

#define OSD_OSDWIN1MD_BMP1MD_SHIFT		13

#define OSD_OSDWIN1MD_BMP1MD			(3 << 13)

#define OSD_OSDWIN1MD_CLUTS1			(1 << 12)

#define OSD_OSDWIN1MD_OHZ1_SHIFT		10

#define OSD_OSDWIN1MD_OHZ1			(3 << 10)

#define OSD_OSDWIN1MD_OVZ1_SHIFT		8

#define OSD_OSDWIN1MD_OVZ1			(3 << 8)

#define OSD_OSDWIN1MD_BMW1_SHIFT		6

#define OSD_OSDWIN1MD_BMW1			(3 << 6)

#define OSD_OSDWIN1MD_BLND1_SHIFT		3

#define OSD_OSDWIN1MD_BLND1			(7 << 3)

#define OSD_OSDWIN1MD_TE1			(1 << 2)

#define OSD_OSDWIN1MD_OFF1			(1 << 1)

#define OSD_OSDWIN1MD_OACT1			(1 << 0)



#define OSD_OSDATRMD_OASW			(1 << 15)

#define OSD_OSDATRMD_OHZA_SHIFT			10

#define OSD_OSDATRMD_OHZA			(3 << 10)

#define OSD_OSDATRMD_OVZA_SHIFT			8

#define OSD_OSDATRMD_OVZA			(3 << 8)

#define OSD_OSDATRMD_BLNKINT_SHIFT		6

#define OSD_OSDATRMD_BLNKINT			(3 << 6)

#define OSD_OSDATRMD_OFFA			(1 << 1)

#define OSD_OSDATRMD_BLNK			(1 << 0)



#define OSD_RECTCUR_RCAD_SHIFT			8

#define OSD_RECTCUR_RCAD			(0xff << 8)

#define OSD_RECTCUR_CLUTSR			(1 << 7)

#define OSD_RECTCUR_RCHW_SHIFT			4

#define OSD_RECTCUR_RCHW			(7 << 4)

#define OSD_RECTCUR_RCVW_SHIFT			1

#define OSD_RECTCUR_RCVW			(7 << 1)

#define OSD_RECTCUR_RCACT			(1 << 0)



#define OSD_VIDWIN0OFST_V0LO			(0x1ff << 0)



#define OSD_VIDWIN1OFST_V1LO			(0x1ff << 0)



#define OSD_OSDWIN0OFST_O0LO			(0x1ff << 0)



#define OSD_OSDWIN1OFST_O1LO			(0x1ff << 0)



#define OSD_WINOFST_AH_SHIFT			9



#define OSD_VIDWIN0OFST_V0AH			(0xf << 9)

#define OSD_VIDWIN1OFST_V1AH			(0xf << 9)

#define OSD_OSDWIN0OFST_O0AH			(0xf << 9)

#define OSD_OSDWIN1OFST_O1AH			(0xf << 9)



#define OSD_VIDWINADH_V1AH_SHIFT		8

#define OSD_VIDWINADH_V1AH			(0x7f << 8)

#define OSD_VIDWINADH_V0AH_SHIFT		0

#define OSD_VIDWINADH_V0AH			(0x7f << 0)



#define OSD_VIDWIN0ADL_V0AL			(0xffff << 0)



#define OSD_VIDWIN1ADL_V1AL			(0xffff << 0)



#define OSD_OSDWINADH_O1AH_SHIFT		8

#define OSD_OSDWINADH_O1AH			(0x7f << 8)

#define OSD_OSDWINADH_O0AH_SHIFT		0

#define OSD_OSDWINADH_O0AH			(0x7f << 0)



#define OSD_OSDWIN0ADL_O0AL			(0xffff << 0)



#define OSD_OSDWIN1ADL_O1AL			(0xffff << 0)



#define OSD_BASEPX_BPX				(0x3ff << 0)



#define OSD_BASEPY_BPY				(0x1ff << 0)



#define OSD_VIDWIN0XP_V0X			(0x7ff << 0)



#define OSD_VIDWIN0YP_V0Y			(0x7ff << 0)



#define OSD_VIDWIN0XL_V0W			(0x7ff << 0)



#define OSD_VIDWIN0YL_V0H			(0x7ff << 0)



#define OSD_VIDWIN1XP_V1X			(0x7ff << 0)



#define OSD_VIDWIN1YP_V1Y			(0x7ff << 0)



#define OSD_VIDWIN1XL_V1W			(0x7ff << 0)



#define OSD_VIDWIN1YL_V1H			(0x7ff << 0)



#define OSD_OSDWIN0XP_W0X			(0x7ff << 0)



#define OSD_OSDWIN0YP_W0Y			(0x7ff << 0)



#define OSD_OSDWIN0XL_W0W			(0x7ff << 0)



#define OSD_OSDWIN0YL_W0H			(0x7ff << 0)



#define OSD_OSDWIN1XP_W1X			(0x7ff << 0)



#define OSD_OSDWIN1YP_W1Y			(0x7ff << 0)



#define OSD_OSDWIN1XL_W1W			(0x7ff << 0)



#define OSD_OSDWIN1YL_W1H			(0x7ff << 0)



#define OSD_CURXP_RCSX				(0x7ff << 0)



#define OSD_CURYP_RCSY				(0x7ff << 0)



#define OSD_CURXL_RCSW				(0x7ff << 0)



#define OSD_CURYL_RCSH				(0x7ff << 0)



#define OSD_EXTMODE_EXPMDSEL			(1 << 15)

#define OSD_EXTMODE_SCRNHEXP_SHIFT		13

#define OSD_EXTMODE_SCRNHEXP			(3 << 13)

#define OSD_EXTMODE_SCRNVEXP			(1 << 12)

#define OSD_EXTMODE_OSD1BLDCHR			(1 << 11)

#define OSD_EXTMODE_OSD0BLDCHR			(1 << 10)

#define OSD_EXTMODE_ATNOSD1EN			(1 << 9)

#define OSD_EXTMODE_ATNOSD0EN			(1 << 8)

#define OSD_EXTMODE_OSDHRSZ15			(1 << 7)

#define OSD_EXTMODE_VIDHRSZ15			(1 << 6)

#define OSD_EXTMODE_ZMFILV1HEN			(1 << 5)

#define OSD_EXTMODE_ZMFILV1VEN			(1 << 4)

#define OSD_EXTMODE_ZMFILV0HEN			(1 << 3)

#define OSD_EXTMODE_ZMFILV0VEN			(1 << 2)

#define OSD_EXTMODE_EXPFILHEN			(1 << 1)

#define OSD_EXTMODE_EXPFILVEN			(1 << 0)



#define OSD_MISCCTL_BLDSEL			(1 << 15)

#define OSD_MISCCTL_S420D			(1 << 14)

#define OSD_MISCCTL_BMAPT			(1 << 13)

#define OSD_MISCCTL_DM365M			(1 << 12)

#define OSD_MISCCTL_RGBEN			(1 << 7)

#define OSD_MISCCTL_RGBWIN			(1 << 6)

#define OSD_MISCCTL_DMANG			(1 << 6)

#define OSD_MISCCTL_TMON			(1 << 5)

#define OSD_MISCCTL_RSEL			(1 << 4)

#define OSD_MISCCTL_CPBSY			(1 << 3)

#define OSD_MISCCTL_PPSW			(1 << 2)

#define OSD_MISCCTL_PPRV			(1 << 1)



#define OSD_CLUTRAMYCB_Y_SHIFT			8

#define OSD_CLUTRAMYCB_Y			(0xff << 8)

#define OSD_CLUTRAMYCB_CB_SHIFT			0

#define OSD_CLUTRAMYCB_CB			(0xff << 0)



#define OSD_CLUTRAMCR_CR_SHIFT			8

#define OSD_CLUTRAMCR_CR			(0xff << 8)

#define OSD_CLUTRAMCR_CADDR_SHIFT		0

#define OSD_CLUTRAMCR_CADDR			(0xff << 0)



#define OSD_TRANSPVAL_RGBTRANS			(0xffff << 0)



#define OSD_TRANSPVALL_RGBL			(0xffff << 0)



#define OSD_TRANSPVALU_Y_SHIFT			8

#define OSD_TRANSPVALU_Y			(0xff << 8)

#define OSD_TRANSPVALU_RGBU_SHIFT		0

#define OSD_TRANSPVALU_RGBU			(0xff << 0)



#define OSD_TRANSPBMPIDX_BMP1_SHIFT		8

#define OSD_TRANSPBMPIDX_BMP1			(0xff << 8)

#define OSD_TRANSPBMPIDX_BMP0_SHIFT		0

#define OSD_TRANSPBMPIDX_BMP0			0xff



#endif				/* _DAVINCI_VPBE_H_ */

include/media/davinci/vpbe_osd.h

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/*

 * Copyright (C) 2007-2009 Texas Instruments Inc

 * Copyright (C) 2007 MontaVista Software, Inc.

 *

 * Andy Lowe (alowe@mvista.com), MontaVista Software

 * - Initial version

 * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.

 * - ported to sub device interface

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation version 2..

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 *

 */

#ifndef _OSD_H

#define _OSD_H



#include <media/davinci/vpbe_types.h>



#define VPBE_OSD_SUBDEV_NAME "vpbe-osd"



/**

 * enum osd_layer

 * @WIN_OSD0: On-Screen Display Window 0

 * @WIN_VID0: Video Window 0

 * @WIN_OSD1: On-Screen Display Window 1

 * @WIN_VID1: Video Window 1

 *

 * Description:

 * An enumeration of the osd display layers.

 */

enum osd_layer {

	WIN_OSD0,

	WIN_VID0,

	WIN_OSD1,

	WIN_VID1,

};



/**

 * enum osd_win_layer

 * @OSDWIN_OSD0: On-Screen Display Window 0

 * @OSDWIN_OSD1: On-Screen Display Window 1

 *

 * Description:

 * An enumeration of the OSD Window layers.

 */

enum osd_win_layer {

	OSDWIN_OSD0,

	OSDWIN_OSD1,

};



/**

 * enum osd_pix_format

 * @PIXFMT_1BPP: 1-bit-per-pixel bitmap

 * @PIXFMT_2BPP: 2-bits-per-pixel bitmap

 * @PIXFMT_4BPP: 4-bits-per-pixel bitmap

 * @PIXFMT_8BPP: 8-bits-per-pixel bitmap

 * @PIXFMT_RGB565: 16-bits-per-pixel RGB565

 * @PIXFMT_YCbCrI: YUV 4:2:2

 * @PIXFMT_RGB888: 24-bits-per-pixel RGB888

 * @PIXFMT_YCrCbI: YUV 4:2:2 with chroma swap

 * @PIXFMT_NV12: YUV 4:2:0 planar

 * @PIXFMT_OSD_ATTR: OSD Attribute Window pixel format (4bpp)

 *

 * Description:

 * An enumeration of the DaVinci pixel formats.

 */

enum osd_pix_format {

	PIXFMT_1BPP = 0,

	PIXFMT_2BPP,

	PIXFMT_4BPP,

	PIXFMT_8BPP,

	PIXFMT_RGB565,

	PIXFMT_YCbCrI,

	PIXFMT_RGB888,

	PIXFMT_YCrCbI,

	PIXFMT_NV12,

	PIXFMT_OSD_ATTR,

};



/**

 * enum osd_h_exp_ratio

 * @H_EXP_OFF: no expansion (1/1)

 * @H_EXP_9_OVER_8: 9/8 expansion ratio

 * @H_EXP_3_OVER_2: 3/2 expansion ratio

 *

 * Description:

 * An enumeration of the available horizontal expansion ratios.

 */

enum osd_h_exp_ratio {

	H_EXP_OFF,

	H_EXP_9_OVER_8,

	H_EXP_3_OVER_2,

};



/**

 * enum osd_v_exp_ratio

 * @V_EXP_OFF: no expansion (1/1)

 * @V_EXP_6_OVER_5: 6/5 expansion ratio

 *

 * Description:

 * An enumeration of the available vertical expansion ratios.

 */

enum osd_v_exp_ratio {

	V_EXP_OFF,

	V_EXP_6_OVER_5,

};



/**

 * enum osd_zoom_factor

 * @ZOOM_X1: no zoom (x1)

 * @ZOOM_X2: x2 zoom

 * @ZOOM_X4: x4 zoom

 *

 * Description:

 * An enumeration of the available zoom factors.

 */

enum osd_zoom_factor {

	ZOOM_X1,

	ZOOM_X2,

	ZOOM_X4,

};



/**

 * enum osd_clut

 * @ROM_CLUT: ROM CLUT

 * @RAM_CLUT: RAM CLUT

 *

 * Description:

 * An enumeration of the available Color Lookup Tables (CLUTs).

 */

enum osd_clut {

	ROM_CLUT,

	RAM_CLUT,

};



/**

 * enum osd_rom_clut

 * @ROM_CLUT0: Macintosh CLUT

 * @ROM_CLUT1: CLUT from DM270 and prior devices

 *

 * Description:

 * An enumeration of the ROM Color Lookup Table (CLUT) options.

 */

enum osd_rom_clut {

	ROM_CLUT0,

	ROM_CLUT1,

};



/**

 * enum osd_blending_factor

 * @OSD_0_VID_8: OSD pixels are fully transparent

 * @OSD_1_VID_7: OSD pixels contribute 1/8, video pixels contribute 7/8

 * @OSD_2_VID_6: OSD pixels contribute 2/8, video pixels contribute 6/8

 * @OSD_3_VID_5: OSD pixels contribute 3/8, video pixels contribute 5/8

 * @OSD_4_VID_4: OSD pixels contribute 4/8, video pixels contribute 4/8

 * @OSD_5_VID_3: OSD pixels contribute 5/8, video pixels contribute 3/8

 * @OSD_6_VID_2: OSD pixels contribute 6/8, video pixels contribute 2/8

 * @OSD_8_VID_0: OSD pixels are fully opaque

 *

 * Description:

 * An enumeration of the DaVinci pixel blending factor options.

 */

enum osd_blending_factor {

	OSD_0_VID_8,

	OSD_1_VID_7,

	OSD_2_VID_6,

	OSD_3_VID_5,

	OSD_4_VID_4,

	OSD_5_VID_3,

	OSD_6_VID_2,

	OSD_8_VID_0,

};



/**

 * enum osd_blink_interval

 * @BLINK_X1: blink interval is 1 vertical refresh cycle

 * @BLINK_X2: blink interval is 2 vertical refresh cycles

 * @BLINK_X3: blink interval is 3 vertical refresh cycles

 * @BLINK_X4: blink interval is 4 vertical refresh cycles

 *

 * Description:

 * An enumeration of the DaVinci pixel blinking interval options.

 */

enum osd_blink_interval {

	BLINK_X1,

	BLINK_X2,

	BLINK_X3,

	BLINK_X4,

};



/**

 * enum osd_cursor_h_width

 * @H_WIDTH_1: horizontal line width is 1 pixel

 * @H_WIDTH_4: horizontal line width is 4 pixels

 * @H_WIDTH_8: horizontal line width is 8 pixels

 * @H_WIDTH_12: horizontal line width is 12 pixels

 * @H_WIDTH_16: horizontal line width is 16 pixels

 * @H_WIDTH_20: horizontal line width is 20 pixels

 * @H_WIDTH_24: horizontal line width is 24 pixels

 * @H_WIDTH_28: horizontal line width is 28 pixels

 */

enum osd_cursor_h_width {

	H_WIDTH_1,

	H_WIDTH_4,

	H_WIDTH_8,

	H_WIDTH_12,

	H_WIDTH_16,

	H_WIDTH_20,

	H_WIDTH_24,

	H_WIDTH_28,

};



/**

 * enum davinci_cursor_v_width

 * @V_WIDTH_1: vertical line width is 1 line

 * @V_WIDTH_2: vertical line width is 2 lines

 * @V_WIDTH_4: vertical line width is 4 lines

 * @V_WIDTH_6: vertical line width is 6 lines

 * @V_WIDTH_8: vertical line width is 8 lines

 * @V_WIDTH_10: vertical line width is 10 lines

 * @V_WIDTH_12: vertical line width is 12 lines

 * @V_WIDTH_14: vertical line width is 14 lines

 */

enum osd_cursor_v_width {

	V_WIDTH_1,

	V_WIDTH_2,

	V_WIDTH_4,

	V_WIDTH_6,

	V_WIDTH_8,

	V_WIDTH_10,

	V_WIDTH_12,

	V_WIDTH_14,

};



/**

 * struct osd_cursor_config

 * @xsize: horizontal size in pixels

 * @ysize: vertical size in lines

 * @xpos: horizontal offset in pixels from the left edge of the display

 * @ypos: vertical offset in lines from the top of the display

 * @interlaced: Non-zero if the display is interlaced, or zero otherwise

 * @h_width: horizontal line width

 * @v_width: vertical line width

 * @clut: the CLUT selector (ROM or RAM) for the cursor color

 * @clut_index: an index into the CLUT for the cursor color

 *

 * Description:

 * A structure describing the configuration parameters of the hardware

 * rectangular cursor.

 */

struct osd_cursor_config {

	unsigned xsize;

	unsigned ysize;

	unsigned xpos;

	unsigned ypos;

	int interlaced;

	enum osd_cursor_h_width h_width;

	enum osd_cursor_v_width v_width;

	enum osd_clut clut;

	unsigned char clut_index;

};



/**

 * struct osd_layer_config

 * @pixfmt: pixel format

 * @line_length: offset in bytes between start of each line in memory

 * @xsize: number of horizontal pixels displayed per line

 * @ysize: number of lines displayed

 * @xpos: horizontal offset in pixels from the left edge of the display

 * @ypos: vertical offset in lines from the top of the display

 * @interlaced: Non-zero if the display is interlaced, or zero otherwise

 *

 * Description:

 * A structure describing the configuration parameters of an On-Screen Display

 * (OSD) or video layer related to how the image is stored in memory.

 * @line_length must be a multiple of the cache line size (32 bytes).

 */

struct osd_layer_config {

	enum osd_pix_format pixfmt;

	unsigned line_length;

	unsigned xsize;

	unsigned ysize;

	unsigned xpos;

	unsigned ypos;

	int interlaced;

};



/* parameters that apply on a per-window (OSD or video) basis */

struct osd_window_state {

	int is_allocated;

	int is_enabled;

	unsigned long fb_base_phys;

	enum osd_zoom_factor h_zoom;

	enum osd_zoom_factor v_zoom;

	struct osd_layer_config lconfig;

};



/* parameters that apply on a per-OSD-window basis */

struct osd_osdwin_state {

	enum osd_clut clut;

	enum osd_blending_factor blend;

	int colorkey_blending;

	unsigned colorkey;

	int rec601_attenuation;

	/* index is pixel value */

	unsigned char palette_map[16];

};



/* hardware rectangular cursor parameters */

struct osd_cursor_state {

	int is_enabled;

	struct osd_cursor_config config;

};



struct osd_state;



struct vpbe_osd_ops {

	int (*initialize)(struct osd_state *sd);

	int (*request_layer)(struct osd_state *sd, enum osd_layer layer);

	void (*release_layer)(struct osd_state *sd, enum osd_layer layer);

	int (*enable_layer)(struct osd_state *sd, enum osd_layer layer,

			    int otherwin);

	void (*disable_layer)(struct osd_state *sd, enum osd_layer layer);

	int (*set_layer_config)(struct osd_state *sd, enum osd_layer layer,

				struct osd_layer_config *lconfig);

	void (*get_layer_config)(struct osd_state *sd, enum osd_layer layer,

				 struct osd_layer_config *lconfig);

	void (*start_layer)(struct osd_state *sd, enum osd_layer layer,

			    unsigned long fb_base_phys,

			    unsigned long cbcr_ofst);

	void (*set_left_margin)(struct osd_state *sd, u32 val);

	void (*set_top_margin)(struct osd_state *sd, u32 val);

	void (*set_interpolation_filter)(struct osd_state *sd, int filter);

	int (*set_vid_expansion)(struct osd_state *sd,

					enum osd_h_exp_ratio h_exp,

					enum osd_v_exp_ratio v_exp);

	void (*get_vid_expansion)(struct osd_state *sd,

					enum osd_h_exp_ratio *h_exp,

					enum osd_v_exp_ratio *v_exp);

	void (*set_zoom)(struct osd_state *sd, enum osd_layer layer,

				enum osd_zoom_factor h_zoom,

				enum osd_zoom_factor v_zoom);

};



struct osd_state {

	enum vpbe_version vpbe_type;

	spinlock_t lock;

	struct device *dev;

	dma_addr_t osd_base_phys;

	unsigned long osd_base;

	unsigned long osd_size;

	/* 1-->the isr will toggle the VID0 ping-pong buffer */

	int pingpong;

	int interpolation_filter;

	int field_inversion;

	enum osd_h_exp_ratio osd_h_exp;

	enum osd_v_exp_ratio osd_v_exp;

	enum osd_h_exp_ratio vid_h_exp;

	enum osd_v_exp_ratio vid_v_exp;

	enum osd_clut backg_clut;

	unsigned backg_clut_index;

	enum osd_rom_clut rom_clut;

	int is_blinking;

	/* attribute window blinking enabled */

	enum osd_blink_interval blink;

	/* YCbCrI or YCrCbI */

	enum osd_pix_format yc_pixfmt;

	/* columns are Y, Cb, Cr */

	unsigned char clut_ram[256][3];

	struct osd_cursor_state cursor;

	/* OSD0, VID0, OSD1, VID1 */

	struct osd_window_state win[4];

	/* OSD0, OSD1 */

	struct osd_osdwin_state osdwin[2];

	/* OSD device Operations */

	struct vpbe_osd_ops ops;

};



struct osd_platform_data {

	enum vpbe_version vpbe_type;

	int  field_inv_wa_enable;

};



#endif