Commit fe8858bb authored by Nikola Cornij's avatar Nikola Cornij Committed by Alex Deucher
Browse files

drm/amd/display: Fix black screen with scaled modes on some eDP panels 



[why]
This was a regression introduced by commit:

        drm/amd/display: Skip modeset for front porch change

Due to the change how timing parameters were set, scaled modes would
cause a black screen on some eDP panels. Would probably apply to
other displays (i.e. even non-eDP) that only have scaled modes,
but such case is not that usual for external displays.

[how]
Pick up crtc frame dimensions when programming the timing unless
it's FreeSync video mode.

Fixes: 6f59f229 ("drm/amd/display: Skip modeset for front porch change")
Signed-off-by: default avatarNikola Cornij <nikola.cornij@amd.com>
Reviewed-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 03e70a02

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+26 −13
Original line number Diff line number Diff line
@@ -130,6 +130,7 @@ MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 
/* basic init/fini API */

static int amdgpu_dm_init(struct amdgpu_device *adev);

static void amdgpu_dm_fini(struct amdgpu_device *adev);

static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);



static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)

{
@@ -5165,6 +5166,7 @@ static void fill_stream_properties_from_drm_display_mode( 
		timing_out->hdmi_vic = hv_frame.vic;

	}



	if (is_freesync_video_mode(mode_in, aconnector)) {

		timing_out->h_addressable = mode_in->hdisplay;

		timing_out->h_total = mode_in->htotal;

		timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
@@ -5174,6 +5176,17 @@ static void fill_stream_properties_from_drm_display_mode( 
		timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;

		timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;

		timing_out->pix_clk_100hz = mode_in->clock * 10;

	} else {

		timing_out->h_addressable = mode_in->crtc_hdisplay;

		timing_out->h_total = mode_in->crtc_htotal;

		timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;

		timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;

		timing_out->v_total = mode_in->crtc_vtotal;

		timing_out->v_addressable = mode_in->crtc_vdisplay;

		timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;

		timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;

		timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;

	}



	timing_out->aspect_ratio = get_aspect_ratio(mode_in);
@@ -5394,7 +5407,7 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 
	return m_pref;

}



static bool is_freesync_video_mode(struct drm_display_mode *mode,

static bool is_freesync_video_mode(const struct drm_display_mode *mode,

				   struct amdgpu_dm_connector *aconnector)

{

	struct drm_display_mode *high_mode;
@@ -5517,7 +5530,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 


	if (recalculate_timing)

		drm_mode_set_crtcinfo(&saved_mode, 0);

	else

	else if (!dm_state)

		drm_mode_set_crtcinfo(&mode, 0);



       /*