Merge tag 'nolibc.2022.05.20a' of git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu (f814957b) · Commits · github.com / kvm-riscv / linux

tools/Makefile

+4 −0

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@ help:
		@echo ' intel-speed-select - Intel Speed Select tool'
		@echo ' kvm_stat - top-like utility for displaying kvm statistics'
		@echo ' leds - LEDs tools'
		@echo ' nolibc - nolibc headers testing and installation'
		@echo ' objtool - an ELF object analysis tool'
		@echo ' pci - PCI tools'
		@echo ' perf - Linux performance measurement and analysis tool'
		@@ -74,6 +75,9 @@ bpf/%: FORCE
		libapi: FORCE
		$(call descend,lib/api)

		nolibc_%: FORCE
		$(call descend,include/nolibc,$(patsubst nolibc_%,%,$@))

		# The perf build does not follow the descend function setup,
		# invoking it via it's own make rule.
		PERF_O = $(if $(O),$(O)/tools/perf,)

tools/include/nolibc/Makefile

0 → 100644

+42 −0

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: GPL-2.0
		# Makefile for nolibc installation and tests
		include ../../scripts/Makefile.include

		# we're in ".../tools/include/nolibc"
		ifeq ($(srctree),)
		srctree := $(patsubst %/tools/include/,%,$(dir $(CURDIR)))
		endif

		nolibc_arch := $(patsubst arm64,aarch64,$(ARCH))
		arch_file := arch-$(nolibc_arch).h
		all_files := ctype.h errno.h nolibc.h signal.h std.h stdio.h stdlib.h string.h \
		sys.h time.h types.h unistd.h

		# install all headers needed to support a bare-metal compiler
		all:

		# Note: when ARCH is "x86" we concatenate both x86_64 and i386
		headers:
		$(Q)mkdir -p $(OUTPUT)sysroot
		$(Q)mkdir -p $(OUTPUT)sysroot/include
		$(Q)cp $(all_files) $(OUTPUT)sysroot/include/
		$(Q)if [ "$(ARCH)" = "x86" ]; then \
		sed -e \
		's,^#ifndef _NOLIBC_ARCH_X86_64_H,#if !defined(_NOLIBC_ARCH_X86_64_H) \&\& defined(__x86_64__),' \
		arch-x86_64.h; \
		sed -e \
		's,^#ifndef _NOLIBC_ARCH_I386_H,#if !defined(_NOLIBC_ARCH_I386_H) \&\& !defined(__x86_64__),' \
		arch-i386.h; \
		elif [ -e "$(arch_file)" ]; then \
		cat $(arch_file); \
		else \
		echo "Fatal: architecture $(ARCH) not yet supported by nolibc." >&2; \
		exit 1; \
		fi > $(OUTPUT)sysroot/include/arch.h

		headers_standalone: headers
		$(Q)$(MAKE) -C $(srctree) headers
		$(Q)$(MAKE) -C $(srctree) headers_install INSTALL_HDR_PATH=$(OUTPUT)/sysroot

		clean:
		$(call QUIET_CLEAN, nolibc) rm -rf "$(OUTPUT)sysroot"

tools/include/nolibc/arch-aarch64.h

0 → 100644

+199 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
		/*
		* AARCH64 specific definitions for NOLIBC
		* Copyright (C) 2017-2022 Willy Tarreau <w@1wt.eu>
		*/

		#ifndef _NOLIBC_ARCH_AARCH64_H
		#define _NOLIBC_ARCH_AARCH64_H

		/* O_* macros for fcntl/open are architecture-specific */
		#define O_RDONLY 0
		#define O_WRONLY 1
		#define O_RDWR 2
		#define O_CREAT 0x40
		#define O_EXCL 0x80
		#define O_NOCTTY 0x100
		#define O_TRUNC 0x200
		#define O_APPEND 0x400
		#define O_NONBLOCK 0x800
		#define O_DIRECTORY 0x4000

		/* The struct returned by the newfstatat() syscall. Differs slightly from the
		* x86_64's stat one by field ordering, so be careful.
		*/
		struct sys_stat_struct {
		unsigned long st_dev;
		unsigned long st_ino;
		unsigned int st_mode;
		unsigned int st_nlink;
		unsigned int st_uid;
		unsigned int st_gid;

		unsigned long st_rdev;
		unsigned long __pad1;
		long st_size;
		int st_blksize;
		int __pad2;

		long st_blocks;
		long st_atime;
		unsigned long st_atime_nsec;
		long st_mtime;

		unsigned long st_mtime_nsec;
		long st_ctime;
		unsigned long st_ctime_nsec;
		unsigned int __unused[2];
		};

		/* Syscalls for AARCH64 :
		* - registers are 64-bit
		* - stack is 16-byte aligned
		* - syscall number is passed in x8
		* - arguments are in x0, x1, x2, x3, x4, x5
		* - the system call is performed by calling svc 0
		* - syscall return comes in x0.
		* - the arguments are cast to long and assigned into the target registers
		* which are then simply passed as registers to the asm code, so that we
		* don't have to experience issues with register constraints.
		*
		* On aarch64, select() is not implemented so we have to use pselect6().
		*/
		#define __ARCH_WANT_SYS_PSELECT6

		#define my_syscall0(num) \
		({ \
		register long _num __asm__ ("x8") = (num); \
		register long _arg1 __asm__ ("x0"); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_num) \
		: "memory", "cc" \
		); \
		_arg1; \
		})

		#define my_syscall1(num, arg1) \
		({ \
		register long _num __asm__ ("x8") = (num); \
		register long _arg1 __asm__ ("x0") = (long)(arg1); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_arg1), \
		"r"(_num) \
		: "memory", "cc" \
		); \
		_arg1; \
		})

		#define my_syscall2(num, arg1, arg2) \
		({ \
		register long _num __asm__ ("x8") = (num); \
		register long _arg1 __asm__ ("x0") = (long)(arg1); \
		register long _arg2 __asm__ ("x1") = (long)(arg2); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_arg1), "r"(_arg2), \
		"r"(_num) \
		: "memory", "cc" \
		); \
		_arg1; \
		})

		#define my_syscall3(num, arg1, arg2, arg3) \
		({ \
		register long _num __asm__ ("x8") = (num); \
		register long _arg1 __asm__ ("x0") = (long)(arg1); \
		register long _arg2 __asm__ ("x1") = (long)(arg2); \
		register long _arg3 __asm__ ("x2") = (long)(arg3); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_arg1), "r"(_arg2), "r"(_arg3), \
		"r"(_num) \
		: "memory", "cc" \
		); \
		_arg1; \
		})

		#define my_syscall4(num, arg1, arg2, arg3, arg4) \
		({ \
		register long _num __asm__ ("x8") = (num); \
		register long _arg1 __asm__ ("x0") = (long)(arg1); \
		register long _arg2 __asm__ ("x1") = (long)(arg2); \
		register long _arg3 __asm__ ("x2") = (long)(arg3); \
		register long _arg4 __asm__ ("x3") = (long)(arg4); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), \
		"r"(_num) \
		: "memory", "cc" \
		); \
		_arg1; \
		})

		#define my_syscall5(num, arg1, arg2, arg3, arg4, arg5) \
		({ \
		register long _num __asm__ ("x8") = (num); \
		register long _arg1 __asm__ ("x0") = (long)(arg1); \
		register long _arg2 __asm__ ("x1") = (long)(arg2); \
		register long _arg3 __asm__ ("x2") = (long)(arg3); \
		register long _arg4 __asm__ ("x3") = (long)(arg4); \
		register long _arg5 __asm__ ("x4") = (long)(arg5); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r" (_arg1) \
		: "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \
		"r"(_num) \
		: "memory", "cc" \
		); \
		_arg1; \
		})

		#define my_syscall6(num, arg1, arg2, arg3, arg4, arg5, arg6) \
		({ \
		register long _num __asm__ ("x8") = (num); \
		register long _arg1 __asm__ ("x0") = (long)(arg1); \
		register long _arg2 __asm__ ("x1") = (long)(arg2); \
		register long _arg3 __asm__ ("x2") = (long)(arg3); \
		register long _arg4 __asm__ ("x3") = (long)(arg4); \
		register long _arg5 __asm__ ("x4") = (long)(arg5); \
		register long _arg6 __asm__ ("x5") = (long)(arg6); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r" (_arg1) \
		: "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \
		"r"(_arg6), "r"(_num) \
		: "memory", "cc" \
		); \
		_arg1; \
		})

		/* startup code */
		__asm__ (".section .text\n"
		".weak _start\n"
		"_start:\n"
		"ldr x0, [sp]\n" // argc (x0) was in the stack
		"add x1, sp, 8\n" // argv (x1) = sp
		"lsl x2, x0, 3\n" // envp (x2) = 8*argc ...
		"add x2, x2, 8\n" // + 8 (skip null)
		"add x2, x2, x1\n" // + argv
		"and sp, x1, -16\n" // sp must be 16-byte aligned in the callee
		"bl main\n" // main() returns the status code, we'll exit with it.
		"mov x8, 93\n" // NR_exit == 93
		"svc #0\n"
		"");

		#endif // _NOLIBC_ARCH_AARCH64_H

tools/include/nolibc/arch-arm.h

0 → 100644

+204 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
		/*
		* ARM specific definitions for NOLIBC
		* Copyright (C) 2017-2022 Willy Tarreau <w@1wt.eu>
		*/

		#ifndef _NOLIBC_ARCH_ARM_H
		#define _NOLIBC_ARCH_ARM_H

		/* O_* macros for fcntl/open are architecture-specific */
		#define O_RDONLY 0
		#define O_WRONLY 1
		#define O_RDWR 2
		#define O_CREAT 0x40
		#define O_EXCL 0x80
		#define O_NOCTTY 0x100
		#define O_TRUNC 0x200
		#define O_APPEND 0x400
		#define O_NONBLOCK 0x800
		#define O_DIRECTORY 0x4000

		/* The struct returned by the stat() syscall, 32-bit only, the syscall returns
		* exactly 56 bytes (stops before the unused array). In big endian, the format
		* differs as devices are returned as short only.
		*/
		struct sys_stat_struct {
		#if defined(__ARMEB__)
		unsigned short st_dev;
		unsigned short __pad1;
		#else
		unsigned long st_dev;
		#endif
		unsigned long st_ino;
		unsigned short st_mode;
		unsigned short st_nlink;
		unsigned short st_uid;
		unsigned short st_gid;

		#if defined(__ARMEB__)
		unsigned short st_rdev;
		unsigned short __pad2;
		#else
		unsigned long st_rdev;
		#endif
		unsigned long st_size;
		unsigned long st_blksize;
		unsigned long st_blocks;

		unsigned long st_atime;
		unsigned long st_atime_nsec;
		unsigned long st_mtime;
		unsigned long st_mtime_nsec;

		unsigned long st_ctime;
		unsigned long st_ctime_nsec;
		unsigned long __unused[2];
		};

		/* Syscalls for ARM in ARM or Thumb modes :
		* - registers are 32-bit
		* - stack is 8-byte aligned
		* ( http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4127.html)
		* - syscall number is passed in r7
		* - arguments are in r0, r1, r2, r3, r4, r5
		* - the system call is performed by calling svc #0
		* - syscall return comes in r0.
		* - only lr is clobbered.
		* - the arguments are cast to long and assigned into the target registers
		* which are then simply passed as registers to the asm code, so that we
		* don't have to experience issues with register constraints.
		* - the syscall number is always specified last in order to allow to force
		* some registers before (gcc refuses a %-register at the last position).
		*
		* Also, ARM supports the old_select syscall if newselect is not available
		*/
		#define __ARCH_WANT_SYS_OLD_SELECT

		#define my_syscall0(num) \
		({ \
		register long _num __asm__ ("r7") = (num); \
		register long _arg1 __asm__ ("r0"); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_num) \
		: "memory", "cc", "lr" \
		); \
		_arg1; \
		})

		#define my_syscall1(num, arg1) \
		({ \
		register long _num __asm__ ("r7") = (num); \
		register long _arg1 __asm__ ("r0") = (long)(arg1); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_arg1), \
		"r"(_num) \
		: "memory", "cc", "lr" \
		); \
		_arg1; \
		})

		#define my_syscall2(num, arg1, arg2) \
		({ \
		register long _num __asm__ ("r7") = (num); \
		register long _arg1 __asm__ ("r0") = (long)(arg1); \
		register long _arg2 __asm__ ("r1") = (long)(arg2); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_arg1), "r"(_arg2), \
		"r"(_num) \
		: "memory", "cc", "lr" \
		); \
		_arg1; \
		})

		#define my_syscall3(num, arg1, arg2, arg3) \
		({ \
		register long _num __asm__ ("r7") = (num); \
		register long _arg1 __asm__ ("r0") = (long)(arg1); \
		register long _arg2 __asm__ ("r1") = (long)(arg2); \
		register long _arg3 __asm__ ("r2") = (long)(arg3); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_arg1), "r"(_arg2), "r"(_arg3), \
		"r"(_num) \
		: "memory", "cc", "lr" \
		); \
		_arg1; \
		})

		#define my_syscall4(num, arg1, arg2, arg3, arg4) \
		({ \
		register long _num __asm__ ("r7") = (num); \
		register long _arg1 __asm__ ("r0") = (long)(arg1); \
		register long _arg2 __asm__ ("r1") = (long)(arg2); \
		register long _arg3 __asm__ ("r2") = (long)(arg3); \
		register long _arg4 __asm__ ("r3") = (long)(arg4); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r"(_arg1) \
		: "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), \
		"r"(_num) \
		: "memory", "cc", "lr" \
		); \
		_arg1; \
		})

		#define my_syscall5(num, arg1, arg2, arg3, arg4, arg5) \
		({ \
		register long _num __asm__ ("r7") = (num); \
		register long _arg1 __asm__ ("r0") = (long)(arg1); \
		register long _arg2 __asm__ ("r1") = (long)(arg2); \
		register long _arg3 __asm__ ("r2") = (long)(arg3); \
		register long _arg4 __asm__ ("r3") = (long)(arg4); \
		register long _arg5 __asm__ ("r4") = (long)(arg5); \
		\
		__asm__ volatile ( \
		"svc #0\n" \
		: "=r" (_arg1) \
		: "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \
		"r"(_num) \
		: "memory", "cc", "lr" \
		); \
		_arg1; \
		})

		/* startup code */
		__asm__ (".section .text\n"
		".weak _start\n"
		"_start:\n"
		#if defined(__THUMBEB__) \|\| defined(__THUMBEL__)
		/* We enter here in 32-bit mode but if some previous functions were in
		* 16-bit mode, the assembler cannot know, so we need to tell it we're in
		* 32-bit now, then switch to 16-bit (is there a better way to do it than
		* adding 1 by hand ?) and tell the asm we're now in 16-bit mode so that
		* it generates correct instructions. Note that we do not support thumb1.
		*/
		".code 32\n"
		"add r0, pc, #1\n"
		"bx r0\n"
		".code 16\n"
		#endif
		"pop {%r0}\n" // argc was in the stack
		"mov %r1, %sp\n" // argv = sp
		"add %r2, %r1, %r0, lsl #2\n" // envp = argv + 4*argc ...
		"add %r2, %r2, $4\n" // ... + 4
		"and %r3, %r1, $-8\n" // AAPCS : sp must be 8-byte aligned in the
		"mov %sp, %r3\n" // callee, an bl doesn't push (lr=pc)
		"bl main\n" // main() returns the status code, we'll exit with it.
		"movs r7, $1\n" // NR_exit == 1
		"svc $0x00\n"
		"");

		#endif // _NOLIBC_ARCH_ARM_H

tools/include/nolibc/arch-i386.h

0 → 100644

+219 −0

File added.

Preview size limit exceeded, changes collapsed.