Commit f4f5df23 authored by Vikas Chaudhary's avatar Vikas Chaudhary Committed by James Bottomley
Browse files

[SCSI] qla4xxx: Added support for ISP82XX 



Signed-off-by: default avatarVikas Chaudhary &lt;Vikas <Chaudhary@qlogic.com>
Signed-off-by: default avatarKaren Higgins <karen.higgins@qlogic.com>
Signed-off-by: default avatarRavi Anand <ravi.anand@qlogic.com>
Signed-off-by: default avatarJames Bottomley <James.Bottomley@suse.de>
parent dbaf82ec

drivers/scsi/qla4xxx/Kconfig

+4 −4
Original line number Diff line number Diff line 
config SCSI_QLA_ISCSI

	tristate "QLogic ISP4XXX host adapter family support"

	depends on PCI && SCSI && NET

	tristate "QLogic ISP4XXX and ISP82XX host adapter family support"

	depends on PCI && SCSI

	select SCSI_ISCSI_ATTRS

	---help---

	This driver supports the QLogic 40xx (ISP4XXX) iSCSI host

	adapter family.
 
	This driver supports the QLogic 40xx (ISP4XXX) and 8022 (ISP82XX)

	iSCSI host adapter family.

drivers/scsi/qla4xxx/Makefile

+1 −1
Original line number Diff line number Diff line 
qla4xxx-y := ql4_os.o ql4_init.o ql4_mbx.o ql4_iocb.o ql4_isr.o \

		ql4_nvram.o ql4_dbg.o

		ql4_nx.o ql4_nvram.o ql4_dbg.o



obj-$(CONFIG_SCSI_QLA_ISCSI) += qla4xxx.o

drivers/scsi/qla4xxx/ql4_def.h

+130 −11
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ 
#include <scsi/scsi_transport.h>

#include <scsi/scsi_transport_iscsi.h>



#include "ql4_dbg.h"

#include "ql4_nx.h"



#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010

#define PCI_DEVICE_ID_QLOGIC_ISP4010	0x4010
@@ -46,6 +48,10 @@ 
#define PCI_DEVICE_ID_QLOGIC_ISP4032	0x4032

#endif



#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022

#define PCI_DEVICE_ID_QLOGIC_ISP8022	0x8022

#endif



#define QLA_SUCCESS			0

#define QLA_ERROR			1
@@ -85,15 +91,22 @@ 
#define BIT_30	0x40000000

#define BIT_31	0x80000000



/**

 * Macros to help code, maintain, etc.

 **/

#define ql4_printk(level, ha, format, arg...) \

	dev_printk(level , &((ha)->pdev->dev) , format , ## arg)





/*

 * Host adapter default definitions

 ***********************************/

#define MAX_HBAS		16

#define MAX_BUSES		1

#define MAX_TARGETS		(MAX_PRST_DEV_DB_ENTRIES +  MAX_DEV_DB_ENTRIES)

#define MAX_TARGETS		MAX_DEV_DB_ENTRIES

#define MAX_LUNS		0xffff

#define MAX_AEN_ENTRIES		256 /* should be > EXT_DEF_MAX_AEN_QUEUE */

#define MAX_DDB_ENTRIES		(MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES)

#define MAX_DDB_ENTRIES		MAX_DEV_DB_ENTRIES

#define MAX_PDU_ENTRIES		32

#define INVALID_ENTRY		0xFFFF

#define MAX_CMDS_TO_RISC	1024
@@ -134,7 +147,7 @@ 
#define SOFT_RESET_TOV			30

#define RESET_INTR_TOV			3

#define SEMAPHORE_TOV			10

#define ADAPTER_INIT_TOV		120

#define ADAPTER_INIT_TOV		30

#define ADAPTER_RESET_TOV		180

#define EXTEND_CMD_TOV			60

#define WAIT_CMD_TOV			30
@@ -184,8 +197,6 @@ struct srb { 
	uint16_t iocb_tov;

	uint16_t iocb_cnt;	/* Number of used iocbs */

	uint16_t cc_stat;

	u_long r_start;		/* Time we recieve a cmd from OS */

	u_long u_start;		/* Time when we handed the cmd to F/W */



	/* Used for extended sense / status continuation */

	uint8_t *req_sense_ptr;
@@ -221,7 +232,6 @@ struct ddb_entry { 
	unsigned long dev_scan_wait_to_start_relogin;

	unsigned long dev_scan_wait_to_complete_relogin;



	uint16_t os_target_id;	/* Target ID */

	uint16_t fw_ddb_index;	/* DDB firmware index */

	uint16_t options;

	uint32_t fw_ddb_device_state; /* F/W Device State  -- see ql4_fw.h */
@@ -285,6 +295,67 @@ struct ddb_entry { 
#include "ql4_fw.h"

#include "ql4_nvram.h"



struct ql82xx_hw_data {

	/* Offsets for flash/nvram access (set to ~0 if not used). */

	uint32_t flash_conf_off;

	uint32_t flash_data_off;



	uint32_t fdt_wrt_disable;

	uint32_t fdt_erase_cmd;

	uint32_t fdt_block_size;

	uint32_t fdt_unprotect_sec_cmd;

	uint32_t fdt_protect_sec_cmd;



	uint32_t flt_region_flt;

	uint32_t flt_region_fdt;

	uint32_t flt_region_boot;

	uint32_t flt_region_bootload;

	uint32_t flt_region_fw;

	uint32_t reserved;

};



struct qla4_8xxx_legacy_intr_set {

	uint32_t int_vec_bit;

	uint32_t tgt_status_reg;

	uint32_t tgt_mask_reg;

	uint32_t pci_int_reg;

};



/* MSI-X Support */



#define QLA_MSIX_DEFAULT	0x00

#define QLA_MSIX_RSP_Q		0x01



#define QLA_MSIX_ENTRIES	2

#define QLA_MIDX_DEFAULT	0

#define QLA_MIDX_RSP_Q		1



struct ql4_msix_entry {

	int have_irq;

	uint16_t msix_vector;

	uint16_t msix_entry;

};



/*

 * ISP Operations

 */

struct isp_operations {

	int (*iospace_config) (struct scsi_qla_host *ha);

	void (*pci_config) (struct scsi_qla_host *);

	void (*disable_intrs) (struct scsi_qla_host *);

	void (*enable_intrs) (struct scsi_qla_host *);

	int (*start_firmware) (struct scsi_qla_host *);

	irqreturn_t (*intr_handler) (int , void *);

	void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);

	int (*reset_chip) (struct scsi_qla_host *);

	int (*reset_firmware) (struct scsi_qla_host *);

	void (*queue_iocb) (struct scsi_qla_host *);

	void (*complete_iocb) (struct scsi_qla_host *);

	uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);

	uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);

	int (*get_sys_info) (struct scsi_qla_host *);

};



/*

 * Linux Host Adapter structure

 */
@@ -296,23 +367,34 @@ struct scsi_qla_host { 
#define AF_INIT_DONE			1 /* 0x00000002 */

#define AF_MBOX_COMMAND			2 /* 0x00000004 */

#define AF_MBOX_COMMAND_DONE		3 /* 0x00000008 */

#define AF_DPC_SCHEDULED		5 /* 0x00000020 */

#define AF_INTERRUPTS_ON		6 /* 0x00000040 */

#define AF_GET_CRASH_RECORD		7 /* 0x00000080 */

#define AF_LINK_UP			8 /* 0x00000100 */

#define AF_IRQ_ATTACHED			10 /* 0x00000400 */

#define AF_DISABLE_ACB_COMPLETE		11 /* 0x00000800 */

#define AF_HBA_GOING_AWAY		12 /* 0x00001000 */

#define AF_INTx_ENABLED			15 /* 0x00008000 */

#define AF_MSI_ENABLED			16 /* 0x00010000 */

#define AF_MSIX_ENABLED			17 /* 0x00020000 */

#define AF_MBOX_COMMAND_NOPOLL		18 /* 0x00040000 */





	unsigned long dpc_flags;



#define DPC_RESET_HA			1 /* 0x00000002 */

#define DPC_RETRY_RESET_HA		2 /* 0x00000004 */

#define DPC_RELOGIN_DEVICE		3 /* 0x00000008 */

#define DPC_RESET_HA_DESTROY_DDB_LIST	4 /* 0x00000010 */

#define DPC_RESET_HA_FW_CONTEXT		4 /* 0x00000010 */

#define DPC_RESET_HA_INTR		5 /* 0x00000020 */

#define DPC_ISNS_RESTART		7 /* 0x00000080 */

#define DPC_AEN				9 /* 0x00000200 */

#define DPC_GET_DHCP_IP_ADDR		15 /* 0x00008000 */

#define DPC_LINK_CHANGED		18 /* 0x00040000 */

#define DPC_RESET_ACTIVE		20 /* 0x00040000 */

#define DPC_HA_UNRECOVERABLE		21 /* 0x00080000 ISP-82xx only*/

#define DPC_HA_NEED_QUIESCENT		22 /* 0x00100000 ISP-82xx only*/





	struct Scsi_Host *host; /* pointer to host data */

	uint32_t tot_ddbs;
@@ -332,7 +414,6 @@ struct scsi_qla_host { 
#define MIN_IOBASE_LEN		0x100



	uint16_t req_q_count;

	uint8_t rsvd1[2];



	unsigned long host_no;
@@ -375,7 +456,6 @@ struct scsi_qla_host { 
	uint8_t alias[32];

	uint8_t name_string[256];

	uint8_t heartbeat_interval;

	uint8_t rsvd;



	/* --- From FlashSysInfo --- */

	uint8_t my_mac[MAC_ADDR_LEN];
@@ -469,6 +549,40 @@ struct scsi_qla_host { 
	struct in6_addr ipv6_addr0;

	struct in6_addr ipv6_addr1;

	struct in6_addr ipv6_default_router_addr;



	/* qla82xx specific fields */

	struct device_reg_82xx  __iomem *qla4_8xxx_reg; /* Base I/O address */

	unsigned long nx_pcibase;	/* Base I/O address */

	uint8_t *nx_db_rd_ptr;		/* Doorbell read pointer */

	unsigned long nx_db_wr_ptr;	/* Door bell write pointer */

	unsigned long first_page_group_start;

	unsigned long first_page_group_end;



	uint32_t crb_win;

	uint32_t curr_window;

	uint32_t ddr_mn_window;

	unsigned long mn_win_crb;

	unsigned long ms_win_crb;

	int qdr_sn_window;

	rwlock_t hw_lock;

	uint16_t func_num;

	int link_width;



	struct qla4_8xxx_legacy_intr_set nx_legacy_intr;

	u32 nx_crb_mask;



	uint8_t revision_id;

	uint32_t fw_heartbeat_counter;



	struct isp_operations *isp_ops;

	struct ql82xx_hw_data hw;



	struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];



	uint32_t nx_dev_init_timeout;

	uint32_t nx_reset_timeout;



	struct completion mbx_intr_comp;

};



static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
@@ -496,6 +610,11 @@ static inline int is_qla4032(struct scsi_qla_host *ha) 
	return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;

}



static inline int is_qla8022(struct scsi_qla_host *ha)

{

	return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;

}



static inline int adapter_up(struct scsi_qla_host *ha)

{

	return (test_bit(AF_ONLINE, &ha->flags) != 0) &&

drivers/scsi/qla4xxx/ql4_fw.h

+138 −1
Original line number Diff line number Diff line
@@ -37,6 +37,33 @@ struct host_mem_cfg_regs { 
	__le32 rsrvd1[31];	/* 0x84-0xFF */

};



/*

 * ISP 82xx I/O Register Set structure definitions.

 */

struct device_reg_82xx {

	__le32 req_q_out;	/* 0x0000 (R): Request Queue out-Pointer. */

	__le32 reserve1[63];	/* Request Queue out-Pointer. (64 * 4) */

	__le32 rsp_q_in;	/* 0x0100 (R/W): Response Queue In-Pointer. */

	__le32 reserve2[63];	/* Response Queue In-Pointer. */

	__le32 rsp_q_out;	/* 0x0200 (R/W): Response Queue Out-Pointer. */

	__le32 reserve3[63];	/* Response Queue Out-Pointer. */



	__le32 mailbox_in[8];	/* 0x0300 (R/W): Mail box In registers */

	__le32 reserve4[24];

	__le32 hint;		/* 0x0380 (R/W): Host interrupt register */

#define HINT_MBX_INT_PENDING	BIT_0

	__le32 reserve5[31];

	__le32 mailbox_out[8];	/* 0x0400 (R): Mail box Out registers */

	__le32 reserve6[56];



	__le32 host_status;	/* Offset 0x500 (R): host status */

#define HSRX_RISC_MB_INT	BIT_0  /* RISC to Host Mailbox interrupt */

#define HSRX_RISC_IOCB_INT	BIT_1  /* RISC to Host IOCB interrupt */



	__le32 host_int;	/* Offset 0x0504 (R/W): Interrupt status. */

#define ISRX_82XX_RISC_INT	BIT_0 /* RISC interrupt. */

};



/*  remote register set (access via PCI memory read/write) */

struct isp_reg {

#define MBOX_REG_COUNT 8
@@ -206,6 +233,79 @@ union external_hw_config_reg { 
	uint32_t Asuint32_t;

};



/* 82XX Support  start */

/* 82xx Default FLT Addresses */

#define FA_FLASH_LAYOUT_ADDR_82		0xFC400

#define FA_FLASH_DESCR_ADDR_82		0xFC000

#define FA_BOOT_LOAD_ADDR_82		0x04000

#define FA_BOOT_CODE_ADDR_82		0x20000

#define FA_RISC_CODE_ADDR_82		0x40000

#define FA_GOLD_RISC_CODE_ADDR_82	0x80000



/* Flash Description Table */

struct qla_fdt_layout {

	uint8_t sig[4];

	uint16_t version;

	uint16_t len;

	uint16_t checksum;

	uint8_t unused1[2];

	uint8_t model[16];

	uint16_t man_id;

	uint16_t id;

	uint8_t flags;

	uint8_t erase_cmd;

	uint8_t alt_erase_cmd;

	uint8_t wrt_enable_cmd;

	uint8_t wrt_enable_bits;

	uint8_t wrt_sts_reg_cmd;

	uint8_t unprotect_sec_cmd;

	uint8_t read_man_id_cmd;

	uint32_t block_size;

	uint32_t alt_block_size;

	uint32_t flash_size;

	uint32_t wrt_enable_data;

	uint8_t read_id_addr_len;

	uint8_t wrt_disable_bits;

	uint8_t read_dev_id_len;

	uint8_t chip_erase_cmd;

	uint16_t read_timeout;

	uint8_t protect_sec_cmd;

	uint8_t unused2[65];

};



/* Flash Layout Table */



struct qla_flt_location {

	uint8_t sig[4];

	uint16_t start_lo;

	uint16_t start_hi;

	uint8_t version;

	uint8_t unused[5];

	uint16_t checksum;

};



struct qla_flt_header {

	uint16_t version;

	uint16_t length;

	uint16_t checksum;

	uint16_t unused;

};



/* 82xx FLT Regions */

#define FLT_REG_FDT		0x1a

#define FLT_REG_FLT		0x1c

#define FLT_REG_BOOTLOAD_82	0x72

#define FLT_REG_FW_82		0x74

#define FLT_REG_GOLD_FW_82	0x75

#define FLT_REG_BOOT_CODE_82	0x78



struct qla_flt_region {

	uint32_t code;

	uint32_t size;

	uint32_t start;

	uint32_t end;

};



/*************************************************************************

 *

 *		Mailbox Commands Structures and Definitions
@@ -215,6 +315,10 @@ union external_hw_config_reg { 
/*  Mailbox command definitions */

#define MBOX_CMD_ABOUT_FW			0x0009

#define MBOX_CMD_PING				0x000B

#define MBOX_CMD_ENABLE_INTRS			0x0010

#define INTR_DISABLE				0

#define INTR_ENABLE				1

#define MBOX_CMD_STOP_FW			0x0014

#define MBOX_CMD_ABORT_TASK			0x0015

#define MBOX_CMD_LUN_RESET			0x0016

#define MBOX_CMD_TARGET_WARM_RESET		0x0017
@@ -243,6 +347,7 @@ union external_hw_config_reg { 
#define DDB_DS_LOGIN_IN_PROCESS			0x07

#define MBOX_CMD_GET_FW_STATE			0x0069

#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A

#define MBOX_CMD_GET_SYS_INFO			0x0078

#define MBOX_CMD_RESTORE_FACTORY_DEFAULTS	0x0087

#define MBOX_CMD_SET_ACB			0x0088

#define MBOX_CMD_GET_ACB			0x0089
@@ -318,6 +423,15 @@ union external_hw_config_reg { 
#define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR	0x8022

#define MBOX_ASTS_SUBNET_STATE_CHANGE		0x8027



/* ACB State Defines */

#define ACB_STATE_UNCONFIGURED	0x00

#define ACB_STATE_INVALID	0x01

#define ACB_STATE_ACQUIRING	0x02

#define ACB_STATE_TENTATIVE	0x03

#define ACB_STATE_DEPRICATED	0x04

#define ACB_STATE_VALID		0x05

#define ACB_STATE_DISABLING	0x06



/*************************************************************************/



/* Host Adapter Initialization Control Block (from host) */
@@ -558,6 +672,20 @@ struct flash_sys_info { 
	uint32_t reserved1[39]; /* 170-1ff */

};	/* 200 */



struct mbx_sys_info {

	uint8_t board_id_str[16];	/* Keep board ID string first */

					/* in this structure for GUI. */

	uint16_t board_id;	/* board ID code */

	uint16_t phys_port_cnt;	/* number of physical network ports */

	uint16_t port_num;	/* network port for this PCI function */

				/* (port 0 is first port) */

	uint8_t mac_addr[6];	/* MAC address for this PCI function */

	uint32_t iscsi_pci_func_cnt;	/* number of iSCSI PCI functions */

	uint32_t pci_func;		/* this PCI function */

	unsigned char serial_number[16];	/* serial number string */

	uint8_t reserved[16];

};



struct crash_record {

	uint16_t fw_major_version;	/* 00 - 01 */

	uint16_t fw_minor_version;	/* 02 - 03 */
@@ -814,4 +942,13 @@ struct passthru_status { 
	uint8_t res4[16];	/* 30-3F */

};



/*

 * ISP queue - response queue entry definition.

 */

struct response {

	uint8_t data[60];

	uint32_t signature;

#define RESPONSE_PROCESSED	0xDEADDEAD	/* Signature */

};



#endif /*  _QLA4X_FW_H */

drivers/scsi/qla4xxx/ql4_glbl.h

+82 −24
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ 


struct iscsi_cls_conn;



void qla4xxx_hw_reset(struct scsi_qla_host *ha);

int qla4xxx_hw_reset(struct scsi_qla_host *ha);

int ql4xxx_lock_drvr_wait(struct scsi_qla_host *a);

int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port);

int qla4xxx_send_command_to_isp(struct scsi_qla_host *ha, struct srb *srb);
@@ -20,6 +20,7 @@ int qla4xxx_soft_reset(struct scsi_qla_host *ha); 
irqreturn_t qla4xxx_intr_handler(int irq, void *dev_id);



void qla4xxx_free_ddb_list(struct scsi_qla_host *ha);

void qla4xxx_free_ddb(struct scsi_qla_host *ha, struct ddb_entry *ddb_entry);

void qla4xxx_process_aen(struct scsi_qla_host *ha, uint8_t process_aen);



int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host *ha);
@@ -64,9 +65,9 @@ int qla4xxx_get_fw_version(struct scsi_qla_host * ha); 
void qla4xxx_interrupt_service_routine(struct scsi_qla_host *ha,

				       uint32_t intr_status);

int qla4xxx_init_rings(struct scsi_qla_host *ha);

void qla4xxx_srb_compl(struct kref *ref);

struct srb *qla4xxx_del_from_active_array(struct scsi_qla_host *ha,

		uint32_t index);

void qla4xxx_srb_compl(struct kref *ref);

int qla4xxx_reinitialize_ddb_list(struct scsi_qla_host *ha);

int qla4xxx_process_ddb_changed(struct scsi_qla_host *ha, uint32_t fw_ddb_index,

		uint32_t state, uint32_t conn_error);
@@ -75,8 +76,65 @@ int qla4xxx_send_marker_iocb(struct scsi_qla_host *ha, 
	struct ddb_entry *ddb_entry, int lun, uint16_t mrkr_mod);

int qla4_is_relogin_allowed(struct scsi_qla_host *ha, uint32_t conn_err);



int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,

		uint8_t outCount, uint32_t *mbx_cmd, uint32_t *mbx_sts);



void qla4xxx_queue_iocb(struct scsi_qla_host *ha);

void qla4xxx_complete_iocb(struct scsi_qla_host *ha);

int qla4xxx_get_sys_info(struct scsi_qla_host *ha);

int qla4xxx_iospace_config(struct scsi_qla_host *ha);

void qla4xxx_pci_config(struct scsi_qla_host *ha);

int qla4xxx_start_firmware(struct scsi_qla_host *ha);

irqreturn_t qla4xxx_intr_handler(int irq, void *dev_id);

uint16_t qla4xxx_rd_shdw_req_q_out(struct scsi_qla_host *ha);

uint16_t qla4xxx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha);

int qla4xxx_request_irqs(struct scsi_qla_host *ha);

void qla4xxx_free_irqs(struct scsi_qla_host *ha);

void qla4xxx_process_response_queue(struct scsi_qla_host *ha);

void qla4xxx_wake_dpc(struct scsi_qla_host *ha);

void qla4xxx_get_conn_event_log(struct scsi_qla_host *ha);



void qla4_8xxx_pci_config(struct scsi_qla_host *);

int qla4_8xxx_iospace_config(struct scsi_qla_host *ha);

int qla4_8xxx_load_risc(struct scsi_qla_host *);

irqreturn_t qla4_8xxx_intr_handler(int irq, void *dev_id);

void qla4_8xxx_queue_iocb(struct scsi_qla_host *ha);

void qla4_8xxx_complete_iocb(struct scsi_qla_host *ha);



int qla4_8xxx_crb_win_lock(struct scsi_qla_host *);

void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *);

int qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *, ulong *);

void qla4_8xxx_wr_32(struct scsi_qla_host *, ulong, u32);

int qla4_8xxx_rd_32(struct scsi_qla_host *, ulong);

int qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *, u64, void *, int);

int qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha, u64, void *, int);

int qla4_8xxx_isp_reset(struct scsi_qla_host *ha);

void qla4_8xxx_interrupt_service_routine(struct scsi_qla_host *ha,

		uint32_t intr_status);

uint16_t qla4_8xxx_rd_shdw_req_q_out(struct scsi_qla_host *ha);

uint16_t qla4_8xxx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha);

int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha);

void qla4_8xxx_watchdog(struct scsi_qla_host *ha);

int qla4_8xxx_stop_firmware(struct scsi_qla_host *ha);

int qla4_8xxx_get_flash_info(struct scsi_qla_host *ha);

void qla4_8xxx_enable_intrs(struct scsi_qla_host *ha);

void qla4_8xxx_disable_intrs(struct scsi_qla_host *ha);

int qla4_8xxx_enable_msix(struct scsi_qla_host *ha);

void qla4_8xxx_disable_msix(struct scsi_qla_host *ha);

irqreturn_t qla4_8xxx_msi_handler(int irq, void *dev_id);

irqreturn_t qla4_8xxx_default_intr_handler(int irq, void *dev_id);

irqreturn_t qla4_8xxx_msix_rsp_q(int irq, void *dev_id);

void qla4xxx_mark_all_devices_missing(struct scsi_qla_host *ha);

void qla4xxx_dead_adapter_cleanup(struct scsi_qla_host *ha);

int qla4_8xxx_idc_lock(struct scsi_qla_host *ha);

void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha);

int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha);

void qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha);

void qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha);



extern int ql4xextended_error_logging;

extern int ql4xdiscoverywait;

extern int ql4xdontresethba;

extern int ql4_mod_unload;

extern int ql4xenablemsix;



#endif /* _QLA4x_GBL_H */