Commit ee546904 authored by Chia-Yuan Li's avatar Chia-Yuan Li Committed by Kalle Valo
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rtw89: 8852c: adjust mactxen delay of mac/phy interface



mac_txen time is to inform TMAC tx after rx air end.
Modify 8852c value to meet TB SIFS time.

Signed-off-by: default avatarChia-Yuan Li <leo.li@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220704023453.19935-7-pkshih@realtek.com
parent 60b2ede9
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+6 −1
Original line number Diff line number Diff line
@@ -1754,7 +1754,12 @@ static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)
		return ret;

	reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx);
	rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, SIFS_MACTXEN_T1);
	if (rtwdev->chip->chip_id == RTL8852C)
		rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
				   SIFS_MACTXEN_T1_V1);
	else
		rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
				   SIFS_MACTXEN_T1);

	if (rtwdev->chip->chip_id == RTL8852B) {
		reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx);
+1 −0
Original line number Diff line number Diff line
@@ -1877,6 +1877,7 @@
#define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
#define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
#define SIFS_MACTXEN_T1 0x47
#define SIFS_MACTXEN_T1_V1 0x41

#define R_AX_CCA_CFG_0 0xC340
#define R_AX_CCA_CFG_0_C1 0xE340