Unverified Commit edfe84ae authored by Dave Stevenson's avatar Dave Stevenson Committed by Maxime Ripard
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drm/vc4: dsi: Correct pixel order for DSI0 



For slightly unknown reasons, dsi0 takes a different pixel format
to dsi1, and that has to be set in the pixel valve.

Amend the setup accordingly.

Fixes: a86773d1 ("drm/vc4: Add support for feeding DSI encoders from the pixel valve.")
Signed-off-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20220613144800.326124-14-maxime@cerno.tech


Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent 3b45eee8

drivers/gpu/drm/vc4/vc4_crtc.c

+2 −1
Original line number Diff line number Diff line
@@ -320,7 +320,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode 
	u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;

	bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||

		       vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);

	u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;

	bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;

	u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;

	u8 ppc = pv_data->pixels_per_clock;

	bool debug_dump_regs = false;