Commit ec0eb562 authored by Philipp Hortmann's avatar Philipp Hortmann Committed by Greg Kroah-Hartman
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staging: rtl8192e: Rename AcmHw_ViqEn, AcmHw_VoqEn and ANAPAR_FOR_8192PciE 



Rename constants AcmHw_ViqEn to ACM_HW_VIQ_EN and AcmHw_VoqEn to
ACM_HW_VOQ_EN and ANAPAR_FOR_8192PciE to ANAPAR_FOR_8192PCIE to avoid
CamelCase which is not accepted by checkpatch.

Signed-off-by: default avatarPhilipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/ecdb350dcd9b1860496c1835980d34c5bca0d39e.1675792435.git.philipp.g.hortmann@gmail.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 7652f95f

drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c

+3 −3
Original line number Diff line number Diff line
@@ -225,11 +225,11 @@ void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val) 
				break;



			case AC2_VI:

				AcmCtrl |= AcmHw_ViqEn;

				AcmCtrl |= ACM_HW_VIQ_EN;

				break;



			case AC3_VO:

				AcmCtrl |= AcmHw_VoqEn;

				AcmCtrl |= ACM_HW_VOQ_EN;

				break;

			}

		} else {
@@ -239,7 +239,7 @@ void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val) 
				break;



			case AC2_VI:

				AcmCtrl &= (~AcmHw_ViqEn);

				AcmCtrl &= (~ACM_HW_VIQ_EN);

				break;



			case AC3_VO:

drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h

+3 −3
Original line number Diff line number Diff line
@@ -144,8 +144,8 @@ enum _RTL8192PCI_HW { 
#define CPU_GEN_NO_LOOPBACK_SET	0x00080000

	ACM_HW_CTRL		= 0x171,

#define	ACM_HW_BEQ_EN		BIT1

#define	AcmHw_ViqEn		BIT2

#define	AcmHw_VoqEn		BIT3

#define	ACM_HW_VIQ_EN		BIT2

#define	ACM_HW_VOQ_EN		BIT3

	RQPN1			= 0x180,

	RQPN2			= 0x184,

	RQPN3			= 0x188,
@@ -250,6 +250,6 @@ enum _RTL8192PCI_HW { 


#define GPI 0x108



#define	ANAPAR_FOR_8192PciE				0x17

#define	ANAPAR_FOR_8192PCIE	0x17



#endif

drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c

+1 −1
Original line number Diff line number Diff line
@@ -1273,7 +1273,7 @@ void rtl92e_set_rf_off(struct net_device *dev) 
	rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);

	rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);

	rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);

	rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07);

	rtl92e_writeb(dev, ANAPAR_FOR_8192PCIE, 0x07);



}