Commit ebe5f898 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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ARM: dts: r8a7742: Add PCIe Controller device node 



Add a device node for the PCIe controller on the Renesas
RZ/G1H (r8a7742) SoC.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarChris Paterson <Chris.Paterson2@renesas.com>
Link: https://lore.kernel.org/r/20200810174156.30880-3-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e7cc614b

arch/arm/boot/dts/r8a7742.dtsi

+35 −0
Original line number Diff line number Diff line
@@ -188,6 +188,13 @@ extal_clk: extal { 
		clock-frequency = <0>;

	};



	/* External PCIe clock - can be overridden by the board */

	pcie_bus_clk: pcie_bus {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	pmu-0 {

		compatible = "arm,cortex-a15-pmu";

		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
@@ -1509,6 +1516,34 @@ gic: interrupt-controller@f1001000 { 
			resets = <&cpg 408>;

		};



		pciec: pcie@fe000000 {

			compatible = "renesas,pcie-r8a7742",

				     "renesas,pcie-rcar-gen2";

			reg = <0 0xfe000000 0 0x80000>;

			#address-cells = <3>;

			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			device_type = "pci";

			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,

				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,

				     <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;

			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			status = "disabled";

		};



		du: display@feb00000 {

			compatible = "renesas,du-r8a7742";

			reg = <0 0xfeb00000 0 0x70000>;