Commit eb53aa39 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn2.6: Add vcn2.6 support 



Aldebaran is using vcn2.6, and the main change is vcn2.6 using
AMDGPU_MMHUB_0, and vcn2.5 using AMDGPU_MMHUB_1

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 86d848b1

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

+97 −2
Original line number Diff line number Diff line
@@ -1545,6 +1545,36 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { 
	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

};



static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = {

	.type = AMDGPU_RING_TYPE_VCN_DEC,

	.align_mask = 0xf,

	.vmhub = AMDGPU_MMHUB_0,

	.get_rptr = vcn_v2_5_dec_ring_get_rptr,

	.get_wptr = vcn_v2_5_dec_ring_get_wptr,

	.set_wptr = vcn_v2_5_dec_ring_set_wptr,

	.emit_frame_size =

		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +

		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

		8 + /* vcn_v2_0_dec_ring_emit_vm_flush */

		14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */

		6,

	.emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */

	.emit_ib = vcn_v2_0_dec_ring_emit_ib,

	.emit_fence = vcn_v2_0_dec_ring_emit_fence,

	.emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,

	.test_ring = vcn_v2_0_dec_ring_test_ring,

	.test_ib = amdgpu_vcn_dec_ring_test_ib,

	.insert_nop = vcn_v2_0_dec_ring_insert_nop,

	.insert_start = vcn_v2_0_dec_ring_insert_start,

	.insert_end = vcn_v2_0_dec_ring_insert_end,

	.pad_ib = amdgpu_ring_generic_pad_ib,

	.begin_use = amdgpu_vcn_ring_begin_use,

	.end_use = amdgpu_vcn_ring_end_use,

	.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,

	.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,

	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

};



/**

 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer

 *
@@ -1644,6 +1674,36 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { 
	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

};



static const struct amdgpu_ring_funcs vcn_v2_6_enc_ring_vm_funcs = {

        .type = AMDGPU_RING_TYPE_VCN_ENC,

        .align_mask = 0x3f,

        .nop = VCN_ENC_CMD_NO_OP,

        .vmhub = AMDGPU_MMHUB_0,

        .get_rptr = vcn_v2_5_enc_ring_get_rptr,

        .get_wptr = vcn_v2_5_enc_ring_get_wptr,

        .set_wptr = vcn_v2_5_enc_ring_set_wptr,

        .emit_frame_size =

                SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +

                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +

                4 + /* vcn_v2_0_enc_ring_emit_vm_flush */

                5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */

                1, /* vcn_v2_0_enc_ring_insert_end */

        .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */

        .emit_ib = vcn_v2_0_enc_ring_emit_ib,

        .emit_fence = vcn_v2_0_enc_ring_emit_fence,

        .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,

        .test_ring = amdgpu_vcn_enc_ring_test_ring,

        .test_ib = amdgpu_vcn_enc_ring_test_ib,

        .insert_nop = amdgpu_ring_insert_nop,

        .insert_end = vcn_v2_0_enc_ring_insert_end,

        .pad_ib = amdgpu_ring_generic_pad_ib,

        .begin_use = amdgpu_vcn_ring_begin_use,

        .end_use = amdgpu_vcn_ring_end_use,

        .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,

        .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,

        .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,

};



static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)

{

	int i;
@@ -1651,7 +1711,10 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 
	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {

		if (adev->vcn.harvest_config & (1 << i))

			continue;

		if (adev->asic_type == CHIP_ARCTURUS)

			adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;

		else /* CHIP_ALDEBARAN */

			adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;

		adev->vcn.inst[i].ring_dec.me = i;

		DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);

	}
@@ -1665,7 +1728,10 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) 
		if (adev->vcn.harvest_config & (1 << j))

			continue;

		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {

			if (adev->asic_type == CHIP_ARCTURUS)

				adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;

			else /* CHIP_ALDEBARAN */

				adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;

			adev->vcn.inst[j].ring_enc[i].me = j;

		}

		DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j);
@@ -1830,6 +1896,26 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { 
	.set_powergating_state = vcn_v2_5_set_powergating_state,

};



static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {

        .name = "vcn_v2_6",

        .early_init = vcn_v2_5_early_init,

        .late_init = NULL,

        .sw_init = vcn_v2_5_sw_init,

        .sw_fini = vcn_v2_5_sw_fini,

        .hw_init = vcn_v2_5_hw_init,

        .hw_fini = vcn_v2_5_hw_fini,

        .suspend = vcn_v2_5_suspend,

        .resume = vcn_v2_5_resume,

        .is_idle = vcn_v2_5_is_idle,

        .wait_for_idle = vcn_v2_5_wait_for_idle,

        .check_soft_reset = NULL,

        .pre_soft_reset = NULL,

        .soft_reset = NULL,

        .post_soft_reset = NULL,

        .set_clockgating_state = vcn_v2_5_set_clockgating_state,

        .set_powergating_state = vcn_v2_5_set_powergating_state,

};



const struct amdgpu_ip_block_version vcn_v2_5_ip_block =

{

		.type = AMD_IP_BLOCK_TYPE_VCN,
@@ -1838,3 +1924,12 @@ const struct amdgpu_ip_block_version vcn_v2_5_ip_block = 
		.rev = 0,

		.funcs = &vcn_v2_5_ip_funcs,

};



const struct amdgpu_ip_block_version vcn_v2_6_ip_block =

{

		.type = AMD_IP_BLOCK_TYPE_VCN,

		.major = 2,

		.minor = 6,

		.rev = 0,

		.funcs = &vcn_v2_6_ip_funcs,

};

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h

+1 −0
Original line number Diff line number Diff line
@@ -25,5 +25,6 @@ 
#define __VCN_V2_5_H__



extern const struct amdgpu_ip_block_version vcn_v2_5_ip_block;

extern const struct amdgpu_ip_block_version vcn_v2_6_ip_block;



#endif /* __VCN_V2_5_H__ */