Commit e9a60cac authored by Shawn Lin's avatar Shawn Lin Committed by Bjorn Helgaas
Browse files

arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339 



Convert all RK3399 platforms to use per-lane PHY model in order to save
more power by idling unused lane(s).

Tested-by: default avatarJeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarBrian Norris <briannorris@chromium.org>
parent f06c6c41

arch/arm64/boot/dts/rockchip/rk3399.dtsi

+5 −3
Original line number Diff line number Diff line
@@ -238,8 +238,10 @@ pcie0: pcie@f8000000 { 
		linux,pci-domain = <0>;

		max-link-speed = <1>;

		msi-map = <0x0 &its 0x0 0x1000>;

		phys = <&pcie_phy>;

		phy-names = "pcie-phy";

		phys = <&pcie_phy 0>, <&pcie_phy 1>,

		       <&pcie_phy 2>, <&pcie_phy 3>;

		phy-names = "pcie-phy-0", "pcie-phy-1",

			    "pcie-phy-2", "pcie-phy-3";

		ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000

			  0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;

		resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
@@ -1295,7 +1297,7 @@ pcie_phy: pcie-phy { 
			compatible = "rockchip,rk3399-pcie-phy";

			clocks = <&cru SCLK_PCIEPHY_REF>;

			clock-names = "refclk";

			#phy-cells = <0>;

			#phy-cells = <1>;

			resets = <&cru SRST_PCIEPHY>;

			reset-names = "phy";

			status = "disabled";