Commit e97cc04f authored by Josip Pavic's avatar Josip Pavic Committed by Alex Deucher
Browse files

drm/amd/display: refactor dmub commands into single function 



[Why & How]
Consolidate dmub access to a single interface. This makes it easier to
add code in the future that needs to run every time a dmub command is
requested (e.g. instrumentation, locking etc).

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarJosip Pavic <Josip.Pavic@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c4edb013

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+11 −1
Original line number Diff line number Diff line
@@ -10311,7 +10311,7 @@ static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 
	input->cea_total_length = total_length;

	memcpy(input->payload, data, length);



	res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);

	res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);

	if (!res) {

		DRM_ERROR("EDID CEA parser failed\n");

		return false;
@@ -10761,3 +10761,13 @@ bool check_seamless_boot_capability(struct amdgpu_device *adev) 


	return false;

}



bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)

{

	return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);

}



bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)

{

	return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);

}

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

+6 −19
Original line number Diff line number Diff line
@@ -123,9 +123,7 @@ static void encoder_control_dmcub( 
		sizeof(cmd.digx_encoder_control.header);

	cmd.digx_encoder_control.encoder_control.dig.stream_param = *dig;



	dc_dmub_srv_cmd_queue(dmcub, &cmd);

	dc_dmub_srv_cmd_execute(dmcub);

	dc_dmub_srv_wait_idle(dmcub);

	dm_execute_dmub_cmd(dmcub->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



static enum bp_result encoder_control_digx_v1_5(
@@ -261,9 +259,7 @@ static void transmitter_control_dmcub( 
		sizeof(cmd.dig1_transmitter_control.header);

	cmd.dig1_transmitter_control.transmitter_control.dig = *dig;



	dc_dmub_srv_cmd_queue(dmcub, &cmd);

	dc_dmub_srv_cmd_execute(dmcub);

	dc_dmub_srv_wait_idle(dmcub);

	dm_execute_dmub_cmd(dmcub->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



static enum bp_result transmitter_control_v1_6(
@@ -325,9 +321,7 @@ static void transmitter_control_dmcub_v1_7( 
		sizeof(cmd.dig1_transmitter_control.header);

	cmd.dig1_transmitter_control.transmitter_control.dig_v1_7 = *dig;



	dc_dmub_srv_cmd_queue(dmcub, &cmd);

	dc_dmub_srv_cmd_execute(dmcub);

	dc_dmub_srv_wait_idle(dmcub);

	dm_execute_dmub_cmd(dmcub->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



static enum bp_result transmitter_control_v1_7(
@@ -435,9 +429,7 @@ static void set_pixel_clock_dmcub( 
		sizeof(cmd.set_pixel_clock.header);

	cmd.set_pixel_clock.pixel_clock.clk = *clk;



	dc_dmub_srv_cmd_queue(dmcub, &cmd);

	dc_dmub_srv_cmd_execute(dmcub);

	dc_dmub_srv_wait_idle(dmcub);

	dm_execute_dmub_cmd(dmcub->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



static enum bp_result set_pixel_clock_v7(
@@ -804,9 +796,7 @@ static void enable_disp_power_gating_dmcub( 
		sizeof(cmd.enable_disp_power_gating.header);

	cmd.enable_disp_power_gating.power_gating.pwr = *pwr;



	dc_dmub_srv_cmd_queue(dmcub, &cmd);

	dc_dmub_srv_cmd_execute(dmcub);

	dc_dmub_srv_wait_idle(dmcub);

	dm_execute_dmub_cmd(dmcub->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



static enum bp_result enable_disp_power_gating_v2_1(
@@ -1016,10 +1006,7 @@ static void enable_lvtma_control_dmcub( 
			panel_instance;

	cmd.lvtma_control.data.bypass_panel_control_wait =

			bypass_panel_control_wait;

	dc_dmub_srv_cmd_queue(dmcub, &cmd);

	dc_dmub_srv_cmd_execute(dmcub);

	dc_dmub_srv_wait_idle(dmcub);



	dm_execute_dmub_cmd(dmcub->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



static enum bp_result enable_lvtma_control(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+1 −3
Original line number Diff line number Diff line
@@ -250,9 +250,7 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 
	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;

	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;



	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);

	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);

	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);

	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

+1 −3
Original line number Diff line number Diff line
@@ -286,9 +286,7 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, 
	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;

	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;



	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);

	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);

	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);

	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+1 −3
Original line number Diff line number Diff line
@@ -234,9 +234,7 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, 
	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;

	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;



	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);

	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);

	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);

	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

}



static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,