Commit e9141f71 authored by Sujith's avatar Sujith Committed by John W. Linville
Browse files

ath9k_hw: Fix async fifo for AR9287 



Async fifo is now enabled only for versions 1.3 and above.
Enable it in the appropriate place, in the reset routine,
instead of process_ini().

Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 15ae733b

drivers/net/wireless/ath/ath9k/ar5008_phy.c

+0 −11
Original line number Diff line number Diff line
@@ -742,17 +742,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, 
		return -EINVAL;

	}



	if (AR_SREV_9287_12_OR_LATER(ah)) {

		/* Enable ASYNC FIFO */

		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

				AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);

		REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);

		REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);

		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);

	}



	/*

	 * Set correct baseband to analog shift setting to

	 * access analog chips.

drivers/net/wireless/ath/ath9k/ar9002_hw.c

+18 −6
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include "ar5008_initvals.h"

#include "ar9001_initvals.h"

#include "ar9002_initvals.h"

#include "ar9002_phy.h"



/* General hardware code for the A5008/AR9001/AR9002 hadware families */
@@ -565,18 +566,29 @@ int ar9002_hw_rf_claim(struct ath_hw *ah) 
	return 0;

}



void ar9002_hw_enable_async_fifo(struct ath_hw *ah)

{

	if (AR_SREV_9287_13_OR_LATER(ah)) {

		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

				AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);

		REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);

		REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);

		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);

	}

}



/*

 * Enable ASYNC FIFO

 *

 * If Async FIFO is enabled, the following counters change as MAC now runs

 * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.

 *

 * The values below tested for ht40 2 chain.

 * Overwrite the delay/timeouts initialized in process ini.

 */

void ar9002_hw_enable_async_fifo(struct ath_hw *ah)

void ar9002_hw_update_async_fifo(struct ath_hw *ah)

{

	if (AR_SREV_9287_12_OR_LATER(ah)) {

	if (AR_SREV_9287_13_OR_LATER(ah)) {

		REG_WRITE(ah, AR_D_GBL_IFS_SIFS,

			  AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);

		REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
@@ -600,7 +612,7 @@ void ar9002_hw_enable_async_fifo(struct ath_hw *ah) 
 */

void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)

{

	if (AR_SREV_9287_12_OR_LATER(ah)) {

	if (AR_SREV_9287_13_OR_LATER(ah)) {

		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,

			    AR_PCU_MISC_MODE2_ENABLE_AGGWEP);

	}

drivers/net/wireless/ath/ath9k/hw.c

+4 −1
Original line number Diff line number Diff line
@@ -1298,6 +1298,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 
	if (AR_SREV_9280_10_OR_LATER(ah))

		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);



	if (!AR_SREV_9300_20_OR_LATER(ah))

		ar9002_hw_enable_async_fifo(ah);



	r = ath9k_hw_process_ini(ah, chan);

	if (r)

		return r;
@@ -1370,7 +1373,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 
	ath9k_hw_init_global_settings(ah);



	if (!AR_SREV_9300_20_OR_LATER(ah)) {

		ar9002_hw_enable_async_fifo(ah);

		ar9002_hw_update_async_fifo(ah);

		ar9002_hw_enable_wep_aggregation(ah);

	}

drivers/net/wireless/ath/ath9k/hw.h

+1 −0
Original line number Diff line number Diff line
@@ -911,6 +911,7 @@ void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 
void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);

int ar9002_hw_rf_claim(struct ath_hw *ah);

void ar9002_hw_enable_async_fifo(struct ath_hw *ah);

void ar9002_hw_update_async_fifo(struct ath_hw *ah);

void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);



/*

drivers/net/wireless/ath/ath9k/reg.h

+32 −26
Original line number Diff line number Diff line
@@ -781,6 +781,7 @@ 
#define AR_SREV_REVISION_9287_10	0

#define AR_SREV_REVISION_9287_11	1

#define AR_SREV_REVISION_9287_12	2

#define AR_SREV_REVISION_9287_13	3

#define AR_SREV_VERSION_9271		0x140

#define AR_SREV_REVISION_9271_10	0

#define AR_SREV_REVISION_9271_11	1
@@ -863,6 +864,11 @@ 
	(((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \

	 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \

	  ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12)))

#define AR_SREV_9287_13_OR_LATER(_ah) \

	(((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \

	 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \

	  ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13)))



#define AR_SREV_9271(_ah) \

    (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271)

#define AR_SREV_9271_10(_ah) \