Commit e8fac46c authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Nuke the magic FBC_CONTROL save/restore 



The FBC_CONTROL save restore is there just to preserve the
compression interval setting. Since commit a68ce21b
("drm/i915/fbc: Store the fbc1 compression interval in the params")
we've been explicitly setting the interval to a specific
value, so the sace/restore is now entirely pointless.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200908140210.31048-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 0f7071c2

drivers/gpu/drm/i915/i915_drv.h

+0 −1
Original line number Diff line number Diff line
@@ -537,7 +537,6 @@ struct intel_gmbus { 


struct i915_suspend_saved_registers {

	u32 saveDSPARB;

	u32 saveFBC_CONTROL;

	u32 saveCACHE_MODE_0;

	u32 saveMI_ARB_STATE;

	u32 saveSWF0[16];

drivers/gpu/drm/i915/i915_suspend.c

+0 −8
Original line number Diff line number Diff line
@@ -40,10 +40,6 @@ static void i915_save_display(struct drm_i915_private *dev_priv) 
	if (INTEL_GEN(dev_priv) <= 4)

		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);



	/* save FBC interval */

	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))

		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);



	if (IS_GEN(dev_priv, 4))

		pci_read_config_word(pdev, GCDGMBUS,

				     &dev_priv->regfile.saveGCDGMBUS);
@@ -64,10 +60,6 @@ static void i915_restore_display(struct drm_i915_private *dev_priv) 
	/* only restore FBC info on the platform that supports FBC*/

	intel_fbc_global_disable(dev_priv);



	/* restore FBC interval */

	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))

		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);



	intel_vga_redisable(dev_priv);



	intel_gmbus_reset(dev_priv);