Commit e87eb585 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/misc' 

  - Add NumaChip SPDX header (Krzysztof Wilczynski)

  - Replace EXTRA_CFLAGS with ccflags-y (Krzysztof Wilczynski)

  - Remove unused includes (Krzysztof Wilczynski)

  - Avoid AMD FCH XHCI USB PME# from D0 defect that prevents wakeup on USB
    2.0 or 1.1 connect events (Kai-Heng Feng)

  - Removed unused sysfs attribute groups (Ben Dooks)

  - Remove PTM and ASPM dependencies on PCIEPORTBUS (Bjorn Helgaas)

  - Add PCIe Link Control 2 register field definitions to replace magic
    numbers in AMDGPU and Radeon CIK/SI (Bjorn Helgaas)

  - Fix incorrect Link Control 2 Transmit Margin usage in AMDGPU and Radeon
    CIK/SI PCIe Gen3 link training (Bjorn Helgaas)

  - Use pcie_capability_read_word() instead of pci_read_config_word() in
    AMDGPU and Radeon CIK/SI (Frederick Lawler)

* pci/misc:
  drm/radeon: Prefer pcie_capability_read_word()
  drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions
  drm/radeon: Correct Transmit Margin masks
  drm/amdgpu: Prefer pcie_capability_read_word()
  drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions
  drm/amdgpu: Correct Transmit Margin masks
  PCI: Add #defines for Enter Compliance, Transmit Margin
  PCI: Allow building PCIe things without PCIEPORTBUS
  PCI: Remove PCIe Kconfig dependencies on PCI
  PCI/ASPM: Remove dependency on PCIEPORTBUS
  PCI/PTM: Remove dependency on PCIEPORTBUS
  PCI/PTM: Remove spurious "d" from granularity message
  PCI: sysfs: Remove unused attribute groups
  x86/PCI: Avoid AMD FCH XHCI USB PME# from D0 defect
  PCI: Remove unused includes and superfluous struct declaration
  x86/PCI: Replace deprecated EXTRA_CFLAGS with ccflags-y
  x86/PCI: Correct SPDX comment style
  x86/PCI: Add NumaChip SPDX GPL-2.0 to replace COPYING boilerplate
parents 2df08822 3d581b11

arch/x86/pci/Makefile

+1 −3
Original line number Diff line number Diff line
@@ -24,6 +24,4 @@ obj-y += bus_numa.o 
obj-$(CONFIG_AMD_NB)		+= amd_bus.o

obj-$(CONFIG_PCI_CNB20LE_QUIRK)	+= broadcom_bus.o



ifeq ($(CONFIG_PCI_DEBUG),y)

EXTRA_CFLAGS += -DDEBUG

endif
 
ccflags-$(CONFIG_PCI_DEBUG)	+= -DDEBUG

arch/x86/pci/fixup.c

+11 −0
Original line number Diff line number Diff line
@@ -588,6 +588,17 @@ static void pci_fixup_amd_ehci_pme(struct pci_dev *dev) 
}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme);



/*

 * Device [1022:7914]

 * When in D0, PME# doesn't get asserted when plugging USB 2.0 device.

 */

static void pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev)

{

	dev_info(&dev->dev, "PME# does not work under D0, disabling it\n");

	dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme);



/*

 * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff]

 *

arch/x86/pci/numachip.c

+1 −4
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Numascale NumaConnect-specific PCI code

 *

 * Copyright (C) 2012 Numascale AS. All rights reserved.

drivers/gpu/drm/amd/amdgpu/cik.c

+60 −35
Original line number Diff line number Diff line
@@ -1384,7 +1384,6 @@ static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 
static void cik_pcie_gen3_enable(struct amdgpu_device *adev)

{

	struct pci_dev *root = adev->pdev->bus->self;

	int bridge_pos, gpu_pos;

	u32 speed_cntl, current_data_rate;

	int i;

	u16 tmp16;
@@ -1419,12 +1418,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 
		DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");

	}



	bridge_pos = pci_pcie_cap(root);

	if (!bridge_pos)

		return;



	gpu_pos = pci_pcie_cap(adev->pdev);

	if (!gpu_pos)

	if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))

		return;



	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
@@ -1434,14 +1428,17 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 
			u16 bridge_cfg2, gpu_cfg2;

			u32 max_lw, current_lw, tmp;



			pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);

			pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);

			pcie_capability_read_word(root, PCI_EXP_LNKCTL,

						  &bridge_cfg);

			pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,

						  &gpu_cfg);



			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;

			pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);

			pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);



			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;

			pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);

			pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,

						   tmp16);



			tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);

			max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
@@ -1465,15 +1462,23 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 


			for (i = 0; i < 10; i++) {

				/* check status */

				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);

				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_DEVSTA,

							  &tmp16);

				if (tmp16 & PCI_EXP_DEVSTA_TRPND)

					break;



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);

				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &bridge_cfg);

				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL,

							  &gpu_cfg);



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);

				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &bridge_cfg2);

				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL2,

							  &gpu_cfg2);



				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);

				tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
@@ -1486,26 +1491,45 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 
				msleep(100);



				/* linkctl */

				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);

				pcie_capability_write_word(root, PCI_EXP_LNKCTL,

							   tmp16);



				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);

				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);

				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);

				pcie_capability_write_word(adev->pdev,

							   PCI_EXP_LNKCTL,

							   tmp16);



				/* linkctl2 */

				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 9));

				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);



				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 9));

				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));

				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pcie_capability_write_word(root,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pcie_capability_write_word(adev->pdev,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);

				tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
@@ -1520,15 +1544,16 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 
	speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;

	WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);



	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~0xf;

	pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;



	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

		tmp16 |= 3; /* gen3 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */

	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)

		tmp16 |= 2; /* gen2 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= 1; /* gen1 */

	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);



	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);

	speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;

drivers/gpu/drm/amd/amdgpu/si.c

+61 −36
Original line number Diff line number Diff line
@@ -1633,7 +1633,6 @@ static void si_init_golden_registers(struct amdgpu_device *adev) 
static void si_pcie_gen3_enable(struct amdgpu_device *adev)

{

	struct pci_dev *root = adev->pdev->bus->self;

	int bridge_pos, gpu_pos;

	u32 speed_cntl, current_data_rate;

	int i;

	u16 tmp16;
@@ -1668,12 +1667,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 
		DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");

	}



	bridge_pos = pci_pcie_cap(root);

	if (!bridge_pos)

		return;



	gpu_pos = pci_pcie_cap(adev->pdev);

	if (!gpu_pos)

	if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))

		return;



	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
@@ -1682,14 +1676,17 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 
			u16 bridge_cfg2, gpu_cfg2;

			u32 max_lw, current_lw, tmp;



			pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);

			pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);

			pcie_capability_read_word(root, PCI_EXP_LNKCTL,

						  &bridge_cfg);

			pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,

						  &gpu_cfg);



			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;

			pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);

			pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);



			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;

			pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);

			pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,

						   tmp16);



			tmp = RREG32_PCIE(PCIE_LC_STATUS1);

			max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -1706,15 +1703,23 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 
			}



			for (i = 0; i < 10; i++) {

				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);

				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_DEVSTA,

							  &tmp16);

				if (tmp16 & PCI_EXP_DEVSTA_TRPND)

					break;



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);

				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &bridge_cfg);

				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL,

							  &gpu_cfg);



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);

				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &bridge_cfg2);

				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL2,

							  &gpu_cfg2);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);

				tmp |= LC_SET_QUIESCE;
@@ -1726,25 +1731,44 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 


				mdelay(100);



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);

				pcie_capability_write_word(root, PCI_EXP_LNKCTL,

							   tmp16);



				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);

				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);

				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 9));

				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);



				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 9));

				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));

				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);

				pcie_capability_write_word(adev->pdev,

							   PCI_EXP_LNKCTL,

							   tmp16);



				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pcie_capability_write_word(root,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pcie_capability_write_word(adev->pdev,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);

				tmp &= ~LC_SET_QUIESCE;
@@ -1757,15 +1781,16 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 
	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;

	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);



	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~0xf;

	pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;



	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

		tmp16 |= 3;

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */

	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)

		tmp16 |= 2;

		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= 1;

	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;