Commit e756e932 authored by David Virag's avatar David Virag Committed by Krzysztof Kozlowski
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dt-bindings: clock: Add indices for Exynos7885 TREX clocks 



TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic
Shaper) inside the Exynos7885 SoC, and are needed for the SoC to
function correctly.

Add indices for these clocks.

Signed-off-by: default avatarDavid Virag <virag.david003@gmail.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220601233743.56317-3-virag.david003@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent cd268e30

include/dt-bindings/clock/exynos7885.h

+15 −8
Original line number Diff line number Diff line
@@ -79,7 +79,14 @@ 
#define CLK_DOUT_CORE_BUSP			5

#define CLK_GOUT_CCI_ACLK			6

#define CLK_GOUT_GIC400_CLK			7

#define CORE_NR_CLK			8

#define CLK_GOUT_TREX_D_CORE_ACLK		8

#define CLK_GOUT_TREX_D_CORE_GCLK		9

#define CLK_GOUT_TREX_D_CORE_PCLK		10

#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE	11

#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE	12

#define CLK_GOUT_TREX_P_CORE_PCLK		13

#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE	14

#define CORE_NR_CLK				15



/* CMU_PERI */

#define CLK_MOUT_PERI_BUS_USER		1