Commit e602157e authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu: fix S3 issue if MQD in VRAM 



1. Need flush HDP for MQD putting in vram
2. Zero out mes MQD

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e03f04b8

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+4 −0
Original line number Diff line number Diff line
@@ -593,6 +593,8 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id) 


	DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,

							kiq_ring->queue);

	amdgpu_device_flush_hdp(adev, NULL);



	spin_lock(&kiq->ring_lock);

	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *

					adev->gfx.num_compute_rings +
@@ -630,6 +632,8 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id) 
	if (!kiq->pmf || !kiq->pmf->kiq_map_queues)

		return -EINVAL;



	amdgpu_device_flush_hdp(adev, NULL);



	spin_lock(&kiq->ring_lock);

	/* No need to map kcq on the slave */

	if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {

drivers/gpu/drm/amd/amdgpu/mes_v10_1.c

+3 −0
Original line number Diff line number Diff line
@@ -632,6 +632,8 @@ static int mes_v10_1_mqd_init(struct amdgpu_ring *ring) 
	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;

	uint32_t tmp;



	memset(mqd, 0, sizeof(*mqd));



	mqd->header = 0xC0310800;

	mqd->compute_pipelinestat_enable = 0x00000001;

	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
@@ -728,6 +730,7 @@ static int mes_v10_1_mqd_init(struct amdgpu_ring *ring) 
	/* offset: 184 - this is used for CP_HQD_GFX_CONTROL */

	mqd->cp_hqd_suspend_cntl_stack_offset = tmp;



	amdgpu_device_flush_hdp(ring->adev, NULL);

	return 0;

}

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+3 −0
Original line number Diff line number Diff line
@@ -704,6 +704,8 @@ static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 
	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;

	uint32_t tmp;



	memset(mqd, 0, sizeof(*mqd));



	mqd->header = 0xC0310800;

	mqd->compute_pipelinestat_enable = 0x00000001;

	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
@@ -797,6 +799,7 @@ static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 
	mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;

	mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;



	amdgpu_device_flush_hdp(ring->adev, NULL);

	return 0;

}