Commit e3a2b0d9 authored by R Veera Kumar's avatar R Veera Kumar Committed by Greg Kroah-Hartman
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staging: rtl8723bs: Correct misspelt symbolic names 



Correct misspelt symbolic names.
Misspelling found using checkpatch.pl.

Signed-off-by: default avatarR Veera Kumar <vkor@vkten.in>
Link: https://lore.kernel.org/r/abe807c11a5fda479ed6079a11d528989fe7b63e.1586187304.git.vkor@vkten.in


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 3f84adfe

drivers/staging/rtl8723bs/hal/hal_com_phycfg.c

+4 −4
Original line number Diff line number Diff line
@@ -1816,7 +1816,7 @@ static void phy_CrossReferenceHTAndVHTTxPowerLimit(struct adapter *padapter) 
	s8 tempPwrLmt = 0;



	for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {

		for (bw = 0; bw < MAX_5G_BANDWITH_NUM; ++bw) {

		for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {

			for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {

				for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {

					tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][ODM_RF_PATH_A];
@@ -1877,7 +1877,7 @@ void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter) 
	phy_CrossReferenceHTAndVHTTxPowerLimit(Adapter);



	for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {

		for (bw = 0; bw < MAX_2_4G_BANDWITH_NUM; ++bw) {

		for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {

			for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {

				for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {

					tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][ODM_RF_PATH_A];
@@ -1920,7 +1920,7 @@ void PHY_InitTxPowerLimit(struct adapter *Adapter) 
	/* DBG_871X("=====> PHY_InitTxPowerLimit()!\n"); */



	for (i = 0; i < MAX_REGULATION_NUM; ++i) {

		for (j = 0; j < MAX_2_4G_BANDWITH_NUM; ++j)

		for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)

			for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)

				for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)

					for (l = 0; l < MAX_RF_PATH_NUM; ++l)
@@ -1928,7 +1928,7 @@ void PHY_InitTxPowerLimit(struct adapter *Adapter) 
	}



	for (i = 0; i < MAX_REGULATION_NUM; ++i) {

		for (j = 0; j < MAX_5G_BANDWITH_NUM; ++j)

		for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)

			for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)

				for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m)

					for (l = 0; l < MAX_RF_PATH_NUM; ++l)

drivers/staging/rtl8723bs/include/hal_data.h

+4 −4
Original line number Diff line number Diff line
@@ -56,9 +56,9 @@ enum RT_AMPDU_BURST { 
/*  Tx Power Limit Table Size */

#define MAX_REGULATION_NUM			4

#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE	4

#define MAX_2_4G_BANDWITH_NUM			4

#define MAX_2_4G_BANDWIDTH_NUM			4

#define MAX_RATE_SECTION_NUM			10

#define MAX_5G_BANDWITH_NUM			4

#define MAX_5G_BANDWIDTH_NUM			4



#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G		10 /*   CCK:1, OFDM:1, HT:4, VHT:4 */

#define MAX_BASE_NUM_IN_PHY_REG_PG_5G		9 /*  OFDM:1, HT:4, VHT:4 */
@@ -280,14 +280,14 @@ struct hal_com_data { 


	/*  Power Limit Table for 2.4G */

	s8	TxPwrLimit_2_4G[MAX_REGULATION_NUM]

						[MAX_2_4G_BANDWITH_NUM]

						[MAX_2_4G_BANDWIDTH_NUM]

	                                [MAX_RATE_SECTION_NUM]

	                                [CHANNEL_MAX_NUMBER_2G]

						[MAX_RF_PATH_NUM];



	/*  Power Limit Table for 5G */

	s8	TxPwrLimit_5G[MAX_REGULATION_NUM]

						[MAX_5G_BANDWITH_NUM]

						[MAX_5G_BANDWIDTH_NUM]

						[MAX_RATE_SECTION_NUM]

						[CHANNEL_MAX_NUMBER_5G]

						[MAX_RF_PATH_NUM];