Commit e338aab0 authored by Vitaly Prosyak's avatar Vitaly Prosyak Committed by Alex Deucher
Browse files

drm/amd/display: Update DPP registers 



Signed-off-by: default avatarVitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2e0ac3d6

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

+6 −12
Original line number Diff line number Diff line
@@ -742,17 +742,11 @@ 
	type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G; \

	type CM_SHAPER_RAMB_EXP_REGION_START_R; \

	type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R; \

	type CM_SHAPER_RAMB_EXP_REGION_LINEAR_SLOPE_B; \

	type CM_SHAPER_RAMB_EXP_REGION_LINEAR_SLOPE_G; \

	type CM_SHAPER_RAMB_EXP_REGION_LINEAR_SLOPE_R; \

	type CM_SHAPER_RAMB_EXP_REGION_END_B; \

	type CM_SHAPER_RAMB_EXP_REGION_END_SLOPE_B; \

	type CM_SHAPER_RAMB_EXP_REGION_END_BASE_B; \

	type CM_SHAPER_RAMB_EXP_REGION_END_G; \

	type CM_SHAPER_RAMB_EXP_REGION_END_SLOPE_G; \

	type CM_SHAPER_RAMB_EXP_REGION_END_BASE_G; \

	type CM_SHAPER_RAMB_EXP_REGION_END_R; \

	type CM_SHAPER_RAMB_EXP_REGION_END_SLOPE_R; \

	type CM_SHAPER_RAMB_EXP_REGION_END_BASE_R; \

	type CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET; \

	type CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS; \
@@ -828,17 +822,11 @@ 
	type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \

	type CM_SHAPER_RAMA_EXP_REGION_START_R; \

	type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \

	type CM_SHAPER_RAMA_EXP_REGION_LINEAR_SLOPE_B; \

	type CM_SHAPER_RAMA_EXP_REGION_LINEAR_SLOPE_G; \

	type CM_SHAPER_RAMA_EXP_REGION_LINEAR_SLOPE_R; \

	type CM_SHAPER_RAMA_EXP_REGION_END_B; \

	type CM_SHAPER_RAMA_EXP_REGION_END_SLOPE_B; \

	type CM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \

	type CM_SHAPER_RAMA_EXP_REGION_END_G; \

	type CM_SHAPER_RAMA_EXP_REGION_END_SLOPE_G; \

	type CM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \

	type CM_SHAPER_RAMA_EXP_REGION_END_R; \

	type CM_SHAPER_RAMA_EXP_REGION_END_SLOPE_R; \

	type CM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \

	type CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \

	type CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \
@@ -1160,6 +1148,9 @@ struct dcn_dpp_registers { 
	uint32_t CM_SHAPER_RAMB_START_CNTL_B;

	uint32_t CM_SHAPER_RAMB_START_CNTL_G;

	uint32_t CM_SHAPER_RAMB_START_CNTL_R;

	uint32_t CM_SHAPER_RAMB_END_CNTL_B;

	uint32_t CM_SHAPER_RAMB_END_CNTL_G;

	uint32_t CM_SHAPER_RAMB_END_CNTL_R;

	uint32_t CM_SHAPER_RAMB_REGION_0_1;

	uint32_t CM_SHAPER_RAMB_REGION_2_3;

	uint32_t CM_SHAPER_RAMB_REGION_4_5;
@@ -1180,6 +1171,9 @@ struct dcn_dpp_registers { 
	uint32_t CM_SHAPER_RAMA_START_CNTL_B;

	uint32_t CM_SHAPER_RAMA_START_CNTL_G;

	uint32_t CM_SHAPER_RAMA_START_CNTL_R;

	uint32_t CM_SHAPER_RAMA_END_CNTL_B;

	uint32_t CM_SHAPER_RAMA_END_CNTL_G;

	uint32_t CM_SHAPER_RAMA_END_CNTL_R;

	uint32_t CM_SHAPER_RAMA_REGION_0_1;

	uint32_t CM_SHAPER_RAMA_REGION_2_3;

	uint32_t CM_SHAPER_RAMA_REGION_4_5;