Commit e1c0fc10 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Greg Kroah-Hartman
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dt-bindings: serial: renesas,sci: Document RZ/G2L SoC 



Add SCI binding documentation for Renesas RZ/G2L SoC.

Also update the example node with RZ/G2L SCI0 node.

Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211110232920.19198-3-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0836150c

Documentation/devicetree/bindings/serial/renesas,sci.yaml

+40 −6
Original line number Diff line number Diff line
@@ -14,7 +14,14 @@ allOf: 


properties:

  compatible:

    const: renesas,sci

    oneOf:

      - items:

          - enum:

              - renesas,r9a07g044-sci     # RZ/G2{L,LC}

          - const: renesas,sci            # generic SCI compatible UART



      - items:

          - const: renesas,sci            # generic SCI compatible UART



  reg:

    maxItems: 1
@@ -54,18 +61,45 @@ required: 
  - clocks

  - clock-names



if:

  properties:

    compatible:

      contains:

        enum:

          - renesas,r9a07g044-sci

then:

  properties:

    resets:

      maxItems: 1



    power-domains:

      maxItems: 1



  required:

    - resets

    - power-domains



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/r9a07g044-cpg.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    aliases {

            serial0 = &sci0;

    };



    sci0: serial@ffff78 {

            compatible = "renesas,sci";

            reg = <0xffff78 8>;

            interrupts = <88 0>, <89 0>, <90 0>, <91 0>;

            clocks = <&fclk>;

    sci0: serial@1004d000 {

            compatible = "renesas,r9a07g044-sci", "renesas,sci";

            reg = <0x1004d000 0x400>;

            interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "eri", "rxi", "txi", "tei";

            clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;

            clock-names = "fck";

            power-domains = <&cpg>;

            resets = <&cpg R9A07G044_SCI0_RST>;

    };