Commit e0cffa9a authored by Marcel Ziswiler's avatar Marcel Ziswiler Committed by Thierry Reding
Browse files

ARM: tegra: apalis-tk1: reorder cpu dfll clock properties 



Reorder CPU DFLL clock properties.

Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent a052d2b6

arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1925,8 +1925,8 @@ sdhci@700b0600 { 
	/* CPU DFLL clock */

	clock@70110000 {

		status = "okay";

		vdd-cpu-supply = <&reg_vdd_cpu>;

		nvidia,i2c-fs-rate = <400000>;

		vdd-cpu-supply = <&reg_vdd_cpu>;

	};



	ahub@70300000 {

arch/arm/boot/dts/tegra124-apalis.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1954,8 +1954,8 @@ sdhci@700b0600 { 
	/* CPU DFLL clock */

	clock@70110000 {

		status = "okay";

		vdd-cpu-supply = <&reg_vdd_cpu>;

		nvidia,i2c-fs-rate = <400000>;

		vdd-cpu-supply = <&reg_vdd_cpu>;

	};



	ahub@70300000 {