Commit e0bcf165 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: add support for ASPM on SI asics (v2) 



Enables PCIE ASPM (Active State Power Management) on
SI asics.

v2: fix typo

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f52382d7

drivers/gpu/drm/radeon/si.c

+203 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ MODULE_FIRMWARE("radeon/HAINAN_mc.bin"); 
MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");



static void si_pcie_gen3_enable(struct radeon_device *rdev);

static void si_program_aspm(struct radeon_device *rdev);

extern int r600_ih_ring_alloc(struct radeon_device *rdev);

extern void r600_ih_ring_fini(struct radeon_device *rdev);

extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
@@ -5319,6 +5320,8 @@ static int si_startup(struct radeon_device *rdev) 


	/* enable pcie gen2/3 link */

	si_pcie_gen3_enable(rdev);

	/* enable aspm */

	si_program_aspm(rdev);



	if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||

	    !rdev->rlc_fw || !rdev->mc_fw) {
@@ -5943,3 +5946,203 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
	}

}



static void si_program_aspm(struct radeon_device *rdev)

{

	u32 data, orig;

	bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;

	bool disable_clkreq = false;



	if (!(rdev->flags & RADEON_IS_PCIE))

		return;



	orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);

	data &= ~LC_XMIT_N_FTS_MASK;

	data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;

	if (orig != data)

		WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);



	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);

	data |= LC_GO_TO_RECOVERY;

	if (orig != data)

		WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);



	orig = data = RREG32_PCIE(PCIE_P_CNTL);

	data |= P_IGNORE_EDB_ERR;

	if (orig != data)

		WREG32_PCIE(PCIE_P_CNTL, data);



	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);

	data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);

	data |= LC_PMI_TO_L1_DIS;

	if (!disable_l0s)

		data |= LC_L0S_INACTIVITY(7);



	if (!disable_l1) {

		data |= LC_L1_INACTIVITY(7);

		data &= ~LC_PMI_TO_L1_DIS;

		if (orig != data)

			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);



		if (!disable_plloff_in_l1) {

			bool clk_req_support;



			orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);

			data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);

			data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);

			if (orig != data)

				WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);



			orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);

			data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);

			data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);

			if (orig != data)

				WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);



			orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);

			data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);

			data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);

			if (orig != data)

				WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);



			orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);

			data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);

			data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);

			if (orig != data)

				WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);



			if ((rdev->family != CHIP_OLAND) && (rdev->family != CHIP_HAINAN)) {

				orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);

				data &= ~PLL_RAMP_UP_TIME_0_MASK;

				if (orig != data)

					WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);



				orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);

				data &= ~PLL_RAMP_UP_TIME_1_MASK;

				if (orig != data)

					WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);



				orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2);

				data &= ~PLL_RAMP_UP_TIME_2_MASK;

				if (orig != data)

					WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2, data);



				orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3);

				data &= ~PLL_RAMP_UP_TIME_3_MASK;

				if (orig != data)

					WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3, data);



				orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);

				data &= ~PLL_RAMP_UP_TIME_0_MASK;

				if (orig != data)

					WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);



				orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);

				data &= ~PLL_RAMP_UP_TIME_1_MASK;

				if (orig != data)

					WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);



				orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2);

				data &= ~PLL_RAMP_UP_TIME_2_MASK;

				if (orig != data)

					WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2, data);



				orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3);

				data &= ~PLL_RAMP_UP_TIME_3_MASK;

				if (orig != data)

					WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3, data);

			}

			orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);

			data &= ~LC_DYN_LANES_PWR_STATE_MASK;

			data |= LC_DYN_LANES_PWR_STATE(3);

			if (orig != data)

				WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);



			orig = data = RREG32_PIF_PHY0(PB0_PIF_CNTL);

			data &= ~LS2_EXIT_TIME_MASK;

			if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))

				data |= LS2_EXIT_TIME(5);

			if (orig != data)

				WREG32_PIF_PHY0(PB0_PIF_CNTL, data);



			orig = data = RREG32_PIF_PHY1(PB1_PIF_CNTL);

			data &= ~LS2_EXIT_TIME_MASK;

			if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))

				data |= LS2_EXIT_TIME(5);

			if (orig != data)

				WREG32_PIF_PHY1(PB1_PIF_CNTL, data);



			if (!disable_clkreq) {

				struct pci_dev *root = rdev->pdev->bus->self;

				u32 lnkcap;



				clk_req_support = false;

				pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);

				if (lnkcap & PCI_EXP_LNKCAP_CLKPM)

					clk_req_support = true;

			} else {

				clk_req_support = false;

			}



			if (clk_req_support) {

				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);

				data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;

				if (orig != data)

					WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);



				orig = data = RREG32(THM_CLK_CNTL);

				data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);

				data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);

				if (orig != data)

					WREG32(THM_CLK_CNTL, data);



				orig = data = RREG32(MISC_CLK_CNTL);

				data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);

				data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);

				if (orig != data)

					WREG32(MISC_CLK_CNTL, data);



				orig = data = RREG32(CG_CLKPIN_CNTL);

				data &= ~BCLK_AS_XCLK;

				if (orig != data)

					WREG32(CG_CLKPIN_CNTL, data);



				orig = data = RREG32(CG_CLKPIN_CNTL_2);

				data &= ~FORCE_BIF_REFCLK_EN;

				if (orig != data)

					WREG32(CG_CLKPIN_CNTL_2, data);



				orig = data = RREG32(MPLL_BYPASSCLK_SEL);

				data &= ~MPLL_CLKOUT_SEL_MASK;

				data |= MPLL_CLKOUT_SEL(4);

				if (orig != data)

					WREG32(MPLL_BYPASSCLK_SEL, data);



				orig = data = RREG32(SPLL_CNTL_MODE);

				data &= ~SPLL_REFCLK_SEL_MASK;

				if (orig != data)

					WREG32(SPLL_CNTL_MODE, data);

			}

		}

	} else {

		if (orig != data)

			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);

	}



	orig = data = RREG32_PCIE(PCIE_CNTL2);

	data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;

	if (orig != data)

		WREG32_PCIE(PCIE_CNTL2, data);



	if (!disable_l0s) {

		data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);

		if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {

			data = RREG32_PCIE(PCIE_LC_STATUS1);

			if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {

				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);

				data &= ~LC_L0S_INACTIVITY_MASK;

				if (orig != data)

					WREG32_PCIE_PORT(PCIE_LC_CNTL, data);

			}

		}

	}

}

drivers/gpu/drm/radeon/sid.h

+111 −0
Original line number Diff line number Diff line
@@ -88,11 +88,32 @@ 
#define VGA_HDP_CONTROL  				0x328

#define		VGA_MEMORY_DISABLE				(1 << 4)



#define	SPLL_CNTL_MODE					0x618

#	define SPLL_REFCLK_SEL(x)			((x) << 8)

#	define SPLL_REFCLK_SEL_MASK			0xFF00



#define	MPLL_BYPASSCLK_SEL				0x65c

#	define MPLL_CLKOUT_SEL(x)			((x) << 8)

#	define MPLL_CLKOUT_SEL_MASK			0xFF00



#define CG_CLKPIN_CNTL                                    0x660

#       define XTALIN_DIVIDE                              (1 << 1)

#       define BCLK_AS_XCLK                               (1 << 2)

#define CG_CLKPIN_CNTL_2                                  0x664

#       define FORCE_BIF_REFCLK_EN                        (1 << 3)

#       define MUX_TCLK_TO_XCLK                           (1 << 8)



#define	THM_CLK_CNTL					0x66c

#	define CMON_CLK_SEL(x)				((x) << 0)

#	define CMON_CLK_SEL_MASK			0xFF

#	define TMON_CLK_SEL(x)				((x) << 8)

#	define TMON_CLK_SEL_MASK			0xFF00

#define	MISC_CLK_CNTL					0x670

#	define DEEP_SLEEP_CLK_SEL(x)			((x) << 0)

#	define DEEP_SLEEP_CLK_SEL_MASK			0xFF

#	define ZCLK_SEL(x)				((x) << 8)

#	define ZCLK_SEL_MASK				0xFF00



#define DMIF_ADDR_CONFIG  				0xBD4



#define DMIF_ADDR_CALC  				0xC00
@@ -829,14 +850,88 @@ 
#       define THREAD_TRACE_FLUSH                       (54 << 0)

#       define THREAD_TRACE_FINISH                      (55 << 0)



/* PIF PHY0 registers idx/data 0x8/0xc */

#define PB0_PIF_CNTL                                      0x10

#       define LS2_EXIT_TIME(x)                           ((x) << 17)

#       define LS2_EXIT_TIME_MASK                         (0x7 << 17)

#       define LS2_EXIT_TIME_SHIFT                        17

#define PB0_PIF_PAIRING                                   0x11

#       define MULTI_PIF                                  (1 << 25)

#define PB0_PIF_PWRDOWN_0                                 0x12

#       define PLL_POWER_STATE_IN_TXS2_0(x)               ((x) << 7)

#       define PLL_POWER_STATE_IN_TXS2_0_MASK             (0x7 << 7)

#       define PLL_POWER_STATE_IN_TXS2_0_SHIFT            7

#       define PLL_POWER_STATE_IN_OFF_0(x)                ((x) << 10)

#       define PLL_POWER_STATE_IN_OFF_0_MASK              (0x7 << 10)

#       define PLL_POWER_STATE_IN_OFF_0_SHIFT             10

#       define PLL_RAMP_UP_TIME_0(x)                      ((x) << 24)

#       define PLL_RAMP_UP_TIME_0_MASK                    (0x7 << 24)

#       define PLL_RAMP_UP_TIME_0_SHIFT                   24

#define PB0_PIF_PWRDOWN_1                                 0x13

#       define PLL_POWER_STATE_IN_TXS2_1(x)               ((x) << 7)

#       define PLL_POWER_STATE_IN_TXS2_1_MASK             (0x7 << 7)

#       define PLL_POWER_STATE_IN_TXS2_1_SHIFT            7

#       define PLL_POWER_STATE_IN_OFF_1(x)                ((x) << 10)

#       define PLL_POWER_STATE_IN_OFF_1_MASK              (0x7 << 10)

#       define PLL_POWER_STATE_IN_OFF_1_SHIFT             10

#       define PLL_RAMP_UP_TIME_1(x)                      ((x) << 24)

#       define PLL_RAMP_UP_TIME_1_MASK                    (0x7 << 24)

#       define PLL_RAMP_UP_TIME_1_SHIFT                   24



#define PB0_PIF_PWRDOWN_2                                 0x17

#       define PLL_POWER_STATE_IN_TXS2_2(x)               ((x) << 7)

#       define PLL_POWER_STATE_IN_TXS2_2_MASK             (0x7 << 7)

#       define PLL_POWER_STATE_IN_TXS2_2_SHIFT            7

#       define PLL_POWER_STATE_IN_OFF_2(x)                ((x) << 10)

#       define PLL_POWER_STATE_IN_OFF_2_MASK              (0x7 << 10)

#       define PLL_POWER_STATE_IN_OFF_2_SHIFT             10

#       define PLL_RAMP_UP_TIME_2(x)                      ((x) << 24)

#       define PLL_RAMP_UP_TIME_2_MASK                    (0x7 << 24)

#       define PLL_RAMP_UP_TIME_2_SHIFT                   24

#define PB0_PIF_PWRDOWN_3                                 0x18

#       define PLL_POWER_STATE_IN_TXS2_3(x)               ((x) << 7)

#       define PLL_POWER_STATE_IN_TXS2_3_MASK             (0x7 << 7)

#       define PLL_POWER_STATE_IN_TXS2_3_SHIFT            7

#       define PLL_POWER_STATE_IN_OFF_3(x)                ((x) << 10)

#       define PLL_POWER_STATE_IN_OFF_3_MASK              (0x7 << 10)

#       define PLL_POWER_STATE_IN_OFF_3_SHIFT             10

#       define PLL_RAMP_UP_TIME_3(x)                      ((x) << 24)

#       define PLL_RAMP_UP_TIME_3_MASK                    (0x7 << 24)

#       define PLL_RAMP_UP_TIME_3_SHIFT                   24

/* PIF PHY1 registers idx/data 0x10/0x14 */

#define PB1_PIF_CNTL                                      0x10

#define PB1_PIF_PAIRING                                   0x11

#define PB1_PIF_PWRDOWN_0                                 0x12

#define PB1_PIF_PWRDOWN_1                                 0x13



#define PB1_PIF_PWRDOWN_2                                 0x17

#define PB1_PIF_PWRDOWN_3                                 0x18

/* PCIE registers idx/data 0x30/0x34 */

#define PCIE_CNTL2                                        0x1c /* PCIE */

#       define SLV_MEM_LS_EN                              (1 << 16)

#       define MST_MEM_LS_EN                              (1 << 18)

#       define REPLAY_MEM_LS_EN                           (1 << 19)

#define PCIE_LC_STATUS1                                   0x28 /* PCIE */

#       define LC_REVERSE_RCVR                            (1 << 0)

#       define LC_REVERSE_XMIT                            (1 << 1)

#       define LC_OPERATING_LINK_WIDTH_MASK               (0x7 << 2)

#       define LC_OPERATING_LINK_WIDTH_SHIFT              2

#       define LC_DETECTED_LINK_WIDTH_MASK                (0x7 << 5)

#       define LC_DETECTED_LINK_WIDTH_SHIFT               5



#define PCIE_P_CNTL                                       0x40 /* PCIE */

#       define P_IGNORE_EDB_ERR                           (1 << 6)



/* PCIE PORT registers idx/data 0x38/0x3c */

#define PCIE_LC_CNTL                                      0xa0

#       define LC_L0S_INACTIVITY(x)                       ((x) << 8)

#       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)

#       define LC_L0S_INACTIVITY_SHIFT                    8

#       define LC_L1_INACTIVITY(x)                        ((x) << 12)

#       define LC_L1_INACTIVITY_MASK                      (0xf << 12)

#       define LC_L1_INACTIVITY_SHIFT                     12

#       define LC_PMI_TO_L1_DIS                           (1 << 16)

#       define LC_ASPM_TO_L1_DIS                          (1 << 24)

#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */

#       define LC_LINK_WIDTH_SHIFT                        0

#       define LC_LINK_WIDTH_MASK                         0x7
@@ -855,6 +950,15 @@ 
#       define LC_SHORT_RECONFIG_EN                       (1 << 11)

#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)

#       define LC_UPCONFIGURE_DIS                         (1 << 13)

#       define LC_DYN_LANES_PWR_STATE(x)                  ((x) << 21)

#       define LC_DYN_LANES_PWR_STATE_MASK                (0x3 << 21)

#       define LC_DYN_LANES_PWR_STATE_SHIFT               21

#define PCIE_LC_N_FTS_CNTL                                0xa3 /* PCIE_P */

#       define LC_XMIT_N_FTS(x)                           ((x) << 0)

#       define LC_XMIT_N_FTS_MASK                         (0xff << 0)

#       define LC_XMIT_N_FTS_SHIFT                        0

#       define LC_XMIT_N_FTS_OVERRIDE_EN                  (1 << 8)

#       define LC_N_FTS_MASK                              (0xff << 24)

#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */

#       define LC_GEN2_EN_STRAP                           (1 << 0)

#       define LC_GEN3_EN_STRAP                           (1 << 1)
@@ -875,6 +979,13 @@ 
#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 19)

#       define LC_OTHER_SIDE_EVER_SENT_GEN3               (1 << 20)

#       define LC_OTHER_SIDE_SUPPORTS_GEN3                (1 << 21)



#define PCIE_LC_CNTL2                                     0xb1

#       define LC_ALLOW_PDWN_IN_L1                        (1 << 17)

#       define LC_ALLOW_PDWN_IN_L23                       (1 << 18)



#define PCIE_LC_CNTL3                                     0xb5 /* PCIE_P */

#       define LC_GO_TO_RECOVERY                          (1 << 30)

#define PCIE_LC_CNTL4                                     0xb6 /* PCIE_P */

#       define LC_REDO_EQ                                 (1 << 5)

#       define LC_SET_QUIESCE                             (1 << 13)