Commit de1aa629 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Disable primary plane trickle feed for g4x 



The docs say that the trickle feed disable bit is present (for primary
planes only, not video sprites) on CTG, and that it must be set
for ELK. Just set it for all g4x chipsets.

v2: Do it in init_clock_gating too

Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3e7ca985

drivers/gpu/drm/i915/intel_display.c

+3 −0
Original line number Diff line number Diff line
@@ -1958,6 +1958,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 
			dspcntr &= ~DISPPLANE_TILED;

	}



	if (IS_G4X(dev))

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;



	I915_WRITE(reg, dspcntr);



	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

drivers/gpu/drm/i915/intel_pm.c

+9 −0
Original line number Diff line number Diff line
@@ -4908,6 +4908,7 @@ static void g4x_init_clock_gating(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t dspclk_gate;

	int pipe;



	I915_WRITE(RENCLK_GATE_D1, 0);

	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
@@ -4924,6 +4925,14 @@ static void g4x_init_clock_gating(struct drm_device *dev) 
	/* WaDisableRenderCachePipelinedFlush */

	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_display_plane(dev_priv, pipe);

	}



}



static void crestline_init_clock_gating(struct drm_device *dev)