Loading Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt 0 → 100644 +30 −0 Original line number Diff line number Diff line Rockchip SRAM for smp bringup: ------------------------------ Rockchip's smp-capable SoCs use the first part of the sram for the bringup of the cores. Once the core gets powered up it executes the code that is residing at the very beginning of the sram. Therefore a reserved section sub-node has to be added to the mmio-sram declaration. Required sub-node properties: - compatible : should be "rockchip,rk3066-smp-sram" The rest of the properties should follow the generic mmio-sram discription found in ../../misc/sram.txt Example: sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; #address-cells = <1>; #size-cells = <1>; ranges; smp-sram@10080000 { compatible = "rockchip,rk3066-smp-sram"; reg = <0x10080000 0x50>; }; }; arch/arm/boot/dts/rk3066a.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,19 @@ timer@2000e000 { clock-names = "timer", "pclk"; }; sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x10080000 0x10000>; smp-sram@0 { compatible = "rockchip,rk3066-smp-sram"; reg = <0x0 0x50>; }; }; pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; reg = <0x20008000 0x150>; Loading arch/arm/boot/dts/rk3188.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -60,6 +60,19 @@ local-timer@1013c600 { interrupts = <GIC_PPI 13 0xf04>; }; sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x8000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x10080000 0x8000>; smp-sram@0 { compatible = "rockchip,rk3066-smp-sram"; reg = <0x0 0x50>; }; }; pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; reg = <0x20008000 0xa0>, Loading Loading
Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt 0 → 100644 +30 −0 Original line number Diff line number Diff line Rockchip SRAM for smp bringup: ------------------------------ Rockchip's smp-capable SoCs use the first part of the sram for the bringup of the cores. Once the core gets powered up it executes the code that is residing at the very beginning of the sram. Therefore a reserved section sub-node has to be added to the mmio-sram declaration. Required sub-node properties: - compatible : should be "rockchip,rk3066-smp-sram" The rest of the properties should follow the generic mmio-sram discription found in ../../misc/sram.txt Example: sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; #address-cells = <1>; #size-cells = <1>; ranges; smp-sram@10080000 { compatible = "rockchip,rk3066-smp-sram"; reg = <0x10080000 0x50>; }; };
arch/arm/boot/dts/rk3066a.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,19 @@ timer@2000e000 { clock-names = "timer", "pclk"; }; sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x10080000 0x10000>; smp-sram@0 { compatible = "rockchip,rk3066-smp-sram"; reg = <0x0 0x50>; }; }; pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; reg = <0x20008000 0x150>; Loading
arch/arm/boot/dts/rk3188.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -60,6 +60,19 @@ local-timer@1013c600 { interrupts = <GIC_PPI 13 0xf04>; }; sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x8000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x10080000 0x8000>; smp-sram@0 { compatible = "rockchip,rk3066-smp-sram"; reg = <0x0 0x50>; }; }; pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; reg = <0x20008000 0xa0>, Loading