Loading drivers/gpu/drm/nouveau/nouveau_drv.h +6 −7 Original line number Diff line number Diff line Loading @@ -471,11 +471,6 @@ struct nouveau_pm_tbl_entry{ u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; }; /* nouveau_mem.c */ void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing); #define NOUVEAU_PM_MAX_LEVEL 8 struct nouveau_pm_level { struct device_attribute dev_attr; Loading Loading @@ -918,6 +913,10 @@ extern void nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_fence *fence); extern const struct ttm_mem_type_manager_func nouveau_vram_manager; extern const struct ttm_mem_type_manager_func nouveau_gart_manager; void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing); /* nouveau_notifier.c */ extern int nouveau_notifier_init_channel(struct nouveau_channel *); Loading drivers/gpu/drm/nouveau/nouveau_mem.c +81 −48 Original line number Diff line number Diff line Loading @@ -473,16 +473,21 @@ nouveau_mem_gart_init(struct drm_device *dev) /* XXX: For now a dummy. More samples required, possibly even a card * Called from nouveau_perf.c */ void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing) { struct nouveau_pm_memtiming *timing) { NV_DEBUG(dev,"Timing entry format unknown, please contact nouveau developers"); NV_DEBUG(dev, "Timing entry format unknown, " "please contact nouveau developers"); } void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing) { struct nouveau_pm_memtiming *timing) { timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP); Loading @@ -492,15 +497,19 @@ void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header 1 << 16 | (e->tUNK_1 + 2 + magic_number) << 8 | (e->tCL + 2 - magic_number); timing->reg_2 = (magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10); timing->reg_2 = magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10; timing->reg_2 |= 0x20200000; NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id, timing->reg_0, timing->reg_1, timing->reg_2); } void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number,struct nouveau_pm_memtiming *timing) { void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint8_t unk18 = 1, Loading @@ -527,11 +536,11 @@ void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct n timing->reg_1 = (e->tWR + unk19 + 1 + magic_number) << 24 | max(unk18, (u8) 1) << 16 | (e->tUNK_1 + unk19 + 1 + magic_number) << 8; if (dev_priv->chipset == 0xa8) { if (dev_priv->chipset == 0xa8) timing->reg_1 |= (e->tCL - 1); } else { else timing->reg_1 |= (e->tCL + 2 - magic_number); } timing->reg_2 = (e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10); timing->reg_5 = (e->tRAS << 24 | e->tRC); Loading @@ -539,12 +548,17 @@ void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct n if (P->version == 1) { timing->reg_2 |= magic_number << 24; timing->reg_3 = (0x14 + e->tCL) << 24 | 0x16 << 16 | (e->tCL - 1) << 8 | (e->tCL - 1); timing->reg_4 = (nv_rd32(dev,0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13; timing->reg_4 = (nv_rd32(dev, 0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13; timing->reg_5 |= (e->tCL + 2) << 8; timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16; } else { timing->reg_2 |= (unk19 - 1) << 24; Loading @@ -569,13 +583,26 @@ void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct n NV_DEBUG(dev, " 240: %08x\n", timing->reg_8); } void nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, struct nouveau_pm_memtiming *timing) { timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | e->tRAS << 8 | e->tRP); timing->reg_1 = (nv_rd32(dev,0x10f294) & 0xff000000) | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | (e->tCL & 0x0f); timing->reg_2 = (nv_rd32(dev,0x10f298) & 0xff0000ff) | e->tWR << 16 | e->tUNK_1 << 8; void nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, struct nouveau_pm_memtiming *timing) { timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | e->tRAS << 8 | e->tRP); timing->reg_1 = (nv_rd32(dev, 0x10f294) & 0xff000000) | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | (e->tCL & 0x0f); timing->reg_2 = (nv_rd32(dev, 0x10f298) & 0xff0000ff) | e->tWR << 16 | e->tUNK_1 << 8; timing->reg_3 = e->tUNK_20 << 9 | e->tUNK_13; timing->reg_4 = (nv_rd32(dev,0x10f2a0) & 0xfff000ff) | e->tUNK_12 << 15; timing->reg_4 = (nv_rd32(dev, 0x10f2a0) & 0xfff000ff) | e->tUNK_12 << 15; NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id, timing->reg_0, timing->reg_1, timing->reg_2, timing->reg_3); Loading Loading @@ -607,13 +634,13 @@ nouveau_mem_timing_init(struct drm_device *dev) return; if (P.version == 1) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]); hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]); else if (P.version == 2) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]); else if (P.version == 2) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]); else { NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); } } else { NV_DEBUG(dev, "BMP version too old for memory\n"); return; Loading @@ -625,32 +652,35 @@ nouveau_mem_timing_init(struct drm_device *dev) } if (hdr->version != 0x10) { NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version); NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version); return; } /* validate record length */ if (hdr->entry_len < 15) { NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len); NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len); return; } /* parse vbios entries into common format */ memtimings->timing = kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL); memtimings->timing = kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL); if (!memtimings->timing) return; /* Get "some number" from the timing reg for NV_40 and NV_50 * Used in calculations later... source unknown */ magic_number = 0; if (P.version == 1) { if (P.version == 1) magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24; } entry = (u8 *) hdr + hdr->header_len; for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) { struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i]; struct nouveau_pm_tbl_entry *entry_struct = (struct nouveau_pm_tbl_entry *) entry; if (entry[0] == 0) continue; Loading @@ -659,16 +689,21 @@ nouveau_mem_timing_init(struct drm_device *dev) timing->CL = entry[2]; if (dev_priv->card_type <= NV_40) { nv40_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); nv40_mem_timing_entry(dev, hdr, entry_struct, magic_number, &pm->memtimings.timing[i]); } else if (dev_priv->card_type == NV_50) { nv50_mem_timing_entry(dev,&P,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); nv50_mem_timing_entry(dev, &P, hdr, entry_struct, magic_number, &pm->memtimings.timing[i]); } else if (dev_priv->card_type == NV_C0) { nvc0_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,&pm->memtimings.timing[i]); nvc0_mem_timing_entry(dev, hdr, entry_struct, &pm->memtimings.timing[i]); } } memtimings->nr_timing = hdr->entry_cnt; memtimings->supported = P.version == 1; memtimings->supported = (P.version == 1); } void Loading @@ -677,11 +712,9 @@ nouveau_mem_timing_fini(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings; if(mem->timing) { kfree(mem->timing); mem->timing = NULL; } } int nouveau_mem_vbios_type(struct drm_device *dev) Loading drivers/gpu/drm/nouveau/nouveau_perf.c +11 −7 Original line number Diff line number Diff line Loading @@ -230,7 +230,8 @@ nouveau_perf_init(struct drm_device *dev) } if (entries > NOUVEAU_PM_MAX_LEVEL) { NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n"); NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n"); entries = NOUVEAU_PM_MAX_LEVEL; } Loading @@ -238,8 +239,9 @@ nouveau_perf_init(struct drm_device *dev) /* For version 0x15, initialize memtiming table */ if (version == 0x15) { memtimings->timing = kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL); memtimings->timing = kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL); if (!memtimings->timing) { NV_WARN(dev, "Could not allocate memtiming table\n"); return; Loading Loading @@ -304,7 +306,7 @@ nouveau_perf_init(struct drm_device *dev) perflvl->dom6 = ROM16(entry[20]) * 1000; break; case 0x40: #define subent(n) (ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000 #define subent(n) ((ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000) perflvl->fanspeed = 0; /*XXX*/ perflvl->volt_min = entry[2]; if (dev_priv->card_type == NV_50) { Loading Loading @@ -342,7 +344,9 @@ nouveau_perf_init(struct drm_device *dev) /* get the corresponding memory timings */ if (version == 0x15) { memtimings->timing[i].id = i; nv30_mem_timing_entry(dev,&mt_hdr,(struct nouveau_pm_tbl_entry*) &entry[41],0,&memtimings->timing[i]); nv30_mem_timing_entry(dev, &mt_hdr, (struct nouveau_pm_tbl_entry *) &entry[41], 0, &memtimings->timing[i]); perflvl->timing = &memtimings->timing[i]; } else if (version > 0x15) { /* last 3 args are for < 0x40, ignored for >= 0x40 */ Loading drivers/gpu/drm/nouveau/nouveau_pm.c +12 −8 Original line number Diff line number Diff line Loading @@ -162,6 +162,7 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; struct nouveau_pm_level *perflvl = NULL; long pl; /* safety precaution, for now */ if (nouveau_perflvl_wr != 7777) Loading @@ -170,8 +171,9 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile) if (!strncmp(profile, "boot", 4)) perflvl = &pm->boot; else { int pl = simple_strtol(profile, NULL, 10); int i; if (kstrtol(profile, 10, &pl) == -EINVAL) return -EINVAL; for (i = 0; i < pm->nr_perflvl; i++) { if (pm->perflvl[i].id == pl) { Loading Loading @@ -397,7 +399,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a, struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; long value; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return count; temp->down_clock = value/1000; Loading Loading @@ -432,7 +434,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a, struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; long value; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return count; temp->critical = value/1000; Loading Loading @@ -529,7 +531,7 @@ nouveau_hwmon_set_pwm0(struct device *d, struct device_attribute *a, if (nouveau_perflvl_wr != 7777) return -EPERM; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return -EINVAL; if (value < pm->fan.min_duty) Loading Loading @@ -568,7 +570,7 @@ nouveau_hwmon_set_pwm0_min(struct device *d, struct device_attribute *a, struct nouveau_pm_engine *pm = &dev_priv->engine.pm; long value; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return -EINVAL; if (value < 0) Loading Loading @@ -609,7 +611,7 @@ nouveau_hwmon_set_pwm0_max(struct device *d, struct device_attribute *a, struct nouveau_pm_engine *pm = &dev_priv->engine.pm; long value; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return -EINVAL; if (value < 0) Loading Loading @@ -731,8 +733,10 @@ nouveau_hwmon_fini(struct drm_device *dev) if (pm->hwmon) { sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup); sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_pwm_fan_attrgroup); sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_fan_rpm_attrgroup); sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_pwm_fan_attrgroup); sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_fan_rpm_attrgroup); hwmon_device_unregister(pm->hwmon); } Loading Loading
drivers/gpu/drm/nouveau/nouveau_drv.h +6 −7 Original line number Diff line number Diff line Loading @@ -471,11 +471,6 @@ struct nouveau_pm_tbl_entry{ u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; }; /* nouveau_mem.c */ void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing); #define NOUVEAU_PM_MAX_LEVEL 8 struct nouveau_pm_level { struct device_attribute dev_attr; Loading Loading @@ -918,6 +913,10 @@ extern void nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_fence *fence); extern const struct ttm_mem_type_manager_func nouveau_vram_manager; extern const struct ttm_mem_type_manager_func nouveau_gart_manager; void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing); /* nouveau_notifier.c */ extern int nouveau_notifier_init_channel(struct nouveau_channel *); Loading
drivers/gpu/drm/nouveau/nouveau_mem.c +81 −48 Original line number Diff line number Diff line Loading @@ -473,16 +473,21 @@ nouveau_mem_gart_init(struct drm_device *dev) /* XXX: For now a dummy. More samples required, possibly even a card * Called from nouveau_perf.c */ void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing) { struct nouveau_pm_memtiming *timing) { NV_DEBUG(dev,"Timing entry format unknown, please contact nouveau developers"); NV_DEBUG(dev, "Timing entry format unknown, " "please contact nouveau developers"); } void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing) { struct nouveau_pm_memtiming *timing) { timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP); Loading @@ -492,15 +497,19 @@ void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header 1 << 16 | (e->tUNK_1 + 2 + magic_number) << 8 | (e->tCL + 2 - magic_number); timing->reg_2 = (magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10); timing->reg_2 = magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10; timing->reg_2 |= 0x20200000; NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id, timing->reg_0, timing->reg_1, timing->reg_2); } void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number,struct nouveau_pm_memtiming *timing) { void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, uint8_t magic_number, struct nouveau_pm_memtiming *timing) { struct drm_nouveau_private *dev_priv = dev->dev_private; uint8_t unk18 = 1, Loading @@ -527,11 +536,11 @@ void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct n timing->reg_1 = (e->tWR + unk19 + 1 + magic_number) << 24 | max(unk18, (u8) 1) << 16 | (e->tUNK_1 + unk19 + 1 + magic_number) << 8; if (dev_priv->chipset == 0xa8) { if (dev_priv->chipset == 0xa8) timing->reg_1 |= (e->tCL - 1); } else { else timing->reg_1 |= (e->tCL + 2 - magic_number); } timing->reg_2 = (e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10); timing->reg_5 = (e->tRAS << 24 | e->tRC); Loading @@ -539,12 +548,17 @@ void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct n if (P->version == 1) { timing->reg_2 |= magic_number << 24; timing->reg_3 = (0x14 + e->tCL) << 24 | 0x16 << 16 | (e->tCL - 1) << 8 | (e->tCL - 1); timing->reg_4 = (nv_rd32(dev,0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13; timing->reg_4 = (nv_rd32(dev, 0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13; timing->reg_5 |= (e->tCL + 2) << 8; timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16; } else { timing->reg_2 |= (unk19 - 1) << 24; Loading @@ -569,13 +583,26 @@ void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct n NV_DEBUG(dev, " 240: %08x\n", timing->reg_8); } void nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, struct nouveau_pm_memtiming *timing) { timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | e->tRAS << 8 | e->tRP); timing->reg_1 = (nv_rd32(dev,0x10f294) & 0xff000000) | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | (e->tCL & 0x0f); timing->reg_2 = (nv_rd32(dev,0x10f298) & 0xff0000ff) | e->tWR << 16 | e->tUNK_1 << 8; void nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, struct nouveau_pm_tbl_entry *e, struct nouveau_pm_memtiming *timing) { timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | e->tRAS << 8 | e->tRP); timing->reg_1 = (nv_rd32(dev, 0x10f294) & 0xff000000) | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | (e->tCL & 0x0f); timing->reg_2 = (nv_rd32(dev, 0x10f298) & 0xff0000ff) | e->tWR << 16 | e->tUNK_1 << 8; timing->reg_3 = e->tUNK_20 << 9 | e->tUNK_13; timing->reg_4 = (nv_rd32(dev,0x10f2a0) & 0xfff000ff) | e->tUNK_12 << 15; timing->reg_4 = (nv_rd32(dev, 0x10f2a0) & 0xfff000ff) | e->tUNK_12 << 15; NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id, timing->reg_0, timing->reg_1, timing->reg_2, timing->reg_3); Loading Loading @@ -607,13 +634,13 @@ nouveau_mem_timing_init(struct drm_device *dev) return; if (P.version == 1) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]); hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]); else if (P.version == 2) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]); else if (P.version == 2) hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]); else { NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); } } else { NV_DEBUG(dev, "BMP version too old for memory\n"); return; Loading @@ -625,32 +652,35 @@ nouveau_mem_timing_init(struct drm_device *dev) } if (hdr->version != 0x10) { NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version); NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version); return; } /* validate record length */ if (hdr->entry_len < 15) { NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len); NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len); return; } /* parse vbios entries into common format */ memtimings->timing = kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL); memtimings->timing = kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL); if (!memtimings->timing) return; /* Get "some number" from the timing reg for NV_40 and NV_50 * Used in calculations later... source unknown */ magic_number = 0; if (P.version == 1) { if (P.version == 1) magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24; } entry = (u8 *) hdr + hdr->header_len; for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) { struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i]; struct nouveau_pm_tbl_entry *entry_struct = (struct nouveau_pm_tbl_entry *) entry; if (entry[0] == 0) continue; Loading @@ -659,16 +689,21 @@ nouveau_mem_timing_init(struct drm_device *dev) timing->CL = entry[2]; if (dev_priv->card_type <= NV_40) { nv40_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); nv40_mem_timing_entry(dev, hdr, entry_struct, magic_number, &pm->memtimings.timing[i]); } else if (dev_priv->card_type == NV_50) { nv50_mem_timing_entry(dev,&P,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); nv50_mem_timing_entry(dev, &P, hdr, entry_struct, magic_number, &pm->memtimings.timing[i]); } else if (dev_priv->card_type == NV_C0) { nvc0_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,&pm->memtimings.timing[i]); nvc0_mem_timing_entry(dev, hdr, entry_struct, &pm->memtimings.timing[i]); } } memtimings->nr_timing = hdr->entry_cnt; memtimings->supported = P.version == 1; memtimings->supported = (P.version == 1); } void Loading @@ -677,11 +712,9 @@ nouveau_mem_timing_fini(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings; if(mem->timing) { kfree(mem->timing); mem->timing = NULL; } } int nouveau_mem_vbios_type(struct drm_device *dev) Loading
drivers/gpu/drm/nouveau/nouveau_perf.c +11 −7 Original line number Diff line number Diff line Loading @@ -230,7 +230,8 @@ nouveau_perf_init(struct drm_device *dev) } if (entries > NOUVEAU_PM_MAX_LEVEL) { NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n"); NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n"); entries = NOUVEAU_PM_MAX_LEVEL; } Loading @@ -238,8 +239,9 @@ nouveau_perf_init(struct drm_device *dev) /* For version 0x15, initialize memtiming table */ if (version == 0x15) { memtimings->timing = kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL); memtimings->timing = kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL); if (!memtimings->timing) { NV_WARN(dev, "Could not allocate memtiming table\n"); return; Loading Loading @@ -304,7 +306,7 @@ nouveau_perf_init(struct drm_device *dev) perflvl->dom6 = ROM16(entry[20]) * 1000; break; case 0x40: #define subent(n) (ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000 #define subent(n) ((ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000) perflvl->fanspeed = 0; /*XXX*/ perflvl->volt_min = entry[2]; if (dev_priv->card_type == NV_50) { Loading Loading @@ -342,7 +344,9 @@ nouveau_perf_init(struct drm_device *dev) /* get the corresponding memory timings */ if (version == 0x15) { memtimings->timing[i].id = i; nv30_mem_timing_entry(dev,&mt_hdr,(struct nouveau_pm_tbl_entry*) &entry[41],0,&memtimings->timing[i]); nv30_mem_timing_entry(dev, &mt_hdr, (struct nouveau_pm_tbl_entry *) &entry[41], 0, &memtimings->timing[i]); perflvl->timing = &memtimings->timing[i]; } else if (version > 0x15) { /* last 3 args are for < 0x40, ignored for >= 0x40 */ Loading
drivers/gpu/drm/nouveau/nouveau_pm.c +12 −8 Original line number Diff line number Diff line Loading @@ -162,6 +162,7 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile) struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; struct nouveau_pm_level *perflvl = NULL; long pl; /* safety precaution, for now */ if (nouveau_perflvl_wr != 7777) Loading @@ -170,8 +171,9 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile) if (!strncmp(profile, "boot", 4)) perflvl = &pm->boot; else { int pl = simple_strtol(profile, NULL, 10); int i; if (kstrtol(profile, 10, &pl) == -EINVAL) return -EINVAL; for (i = 0; i < pm->nr_perflvl; i++) { if (pm->perflvl[i].id == pl) { Loading Loading @@ -397,7 +399,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a, struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; long value; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return count; temp->down_clock = value/1000; Loading Loading @@ -432,7 +434,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a, struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; long value; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return count; temp->critical = value/1000; Loading Loading @@ -529,7 +531,7 @@ nouveau_hwmon_set_pwm0(struct device *d, struct device_attribute *a, if (nouveau_perflvl_wr != 7777) return -EPERM; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return -EINVAL; if (value < pm->fan.min_duty) Loading Loading @@ -568,7 +570,7 @@ nouveau_hwmon_set_pwm0_min(struct device *d, struct device_attribute *a, struct nouveau_pm_engine *pm = &dev_priv->engine.pm; long value; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return -EINVAL; if (value < 0) Loading Loading @@ -609,7 +611,7 @@ nouveau_hwmon_set_pwm0_max(struct device *d, struct device_attribute *a, struct nouveau_pm_engine *pm = &dev_priv->engine.pm; long value; if (strict_strtol(buf, 10, &value) == -EINVAL) if (kstrtol(buf, 10, &value) == -EINVAL) return -EINVAL; if (value < 0) Loading Loading @@ -731,8 +733,10 @@ nouveau_hwmon_fini(struct drm_device *dev) if (pm->hwmon) { sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup); sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_pwm_fan_attrgroup); sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_fan_rpm_attrgroup); sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_pwm_fan_attrgroup); sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_fan_rpm_attrgroup); hwmon_device_unregister(pm->hwmon); } Loading