Unverified Commit db554515 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'zynqmp-dt-for-v5.16' of https://github.com/Xilinx/linux-xlnx into arm/dt 

arm64: dts: ZynqMP DT changes for v5.16

- Fix issues reported by dtbs_check
- Enable DMAs, DP, USB, NAND on various boards
- Add description for irps5401
- Add pinctrl description
- Add psgtr description for usb3, sata and DP
- Start to use nvmem alias for eeprom reference
- Clean up aliases list
- Wire qspi and usb3.0
- Add support for zcu102-rev1.1
- Couple of minor fixes and sync patches

* tag 'zynqmp-dt-for-v5.16' of https://github.com/Xilinx/linux-xlnx: (36 commits)
  arm64: zynqmp: Wire psgtr for zc1751-xm013
  arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards
  arm64: zynqmp: Enable gpio and qspi for zc1275-revA
  arm64: zynqmp: Fix serial compatible string
  arm64: zynqmp: Remove not documented is-dual property
  arm64: zynqmp: Add psgtr description to zc1751 dc1 board
  arm64: zynqmp: Add support for zcu102-rev1.1 board
  arm64: zynqmp: Remove description for 8T49N287 and si5382 chips
  arm64: zynqmp: Sync psgtr node location with zcu104-revA
  arm64: zynqmp: Add reset description for sata
  arm64: zynqmp: Move rtc to different location on zcu104-revA
  arm64: zynqmp: Wire qspi on multiple boards
  arm64: zynqmp: Remove information about dma clock on zcu106
  arm64: zynqmp: Update rtc calibration value
  arm64: zynqmp: Add note about UHS mode on some boards
  arm64: zynqmp: Move DP nodes to the end of file on zcu106
  arm64: zynqmp: Remove can aliases from zc1751
  arm64: zynqmp: Add reset-on-timeout to all boards and modify default timeout value
  arm64: zynqmp: List reset property for ethernet phy
  arm64: zynqmp: Add nvmem alises for eeproms
  ...

Link: https://lore.kernel.org/r/b1cbd05d-ab40-e1fc-4001-6cf88e1e81f9@monstr.eu


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 5816b3e6 35a7430d

Documentation/devicetree/bindings/arm/xilinx.yaml

+1 −0
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@ properties: 
              - xlnx,zynqmp-zcu102-revA

              - xlnx,zynqmp-zcu102-revB

              - xlnx,zynqmp-zcu102-rev1.0

              - xlnx,zynqmp-zcu102-rev1.1

          - const: xlnx,zynqmp-zcu102

          - const: xlnx,zynqmp

arch/arm64/boot/dts/xilinx/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb 
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.1.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb

dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

+12 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * Clock specification for Xilinx ZynqMP

 *

 * (C) Copyright 2017 - 2019, Xilinx, Inc.

 * (C) Copyright 2017 - 2021, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */
@@ -40,6 +40,17 @@ aux_ref_clk: aux_ref_clk { 
	};

};



&zynqmp_firmware {

	zynqmp_clk: clock-controller {

		#clock-cells = <1>;

		compatible = "xlnx,zynqmp-clk";

		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,

			 <&aux_ref_clk>, <&gt_crx_ref_clk>;

		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",

			      "aux_ref_clk", "gt_crx_ref_clk";

	};

};



&can0 {

	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;

};

arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts

+15 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1232

 *

 * (C) Copyright 2017 - 2019, Xilinx, Inc.

 * (C) Copyright 2017 - 2021, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 */
@@ -19,6 +19,7 @@ / { 
	aliases {

		serial0 = &uart0;

		serial1 = &dcc;

		spi0 = &qspi;

	};



	chosen {
@@ -36,6 +37,19 @@ &dcc { 
	status = "okay";

};



&qspi {

	status = "okay";

	flash@0 {

		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

};



&sata {

	status = "okay";

	/* SATA OOB timing settings */

arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts

+15 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * dts file for Xilinx ZynqMP ZC1254

 *

 * (C) Copyright 2015 - 2019, Xilinx, Inc.

 * (C) Copyright 2015 - 2021, Xilinx, Inc.

 *

 * Michal Simek <michal.simek@xilinx.com>

 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@@ -20,6 +20,7 @@ / { 
	aliases {

		serial0 = &uart0;

		serial1 = &dcc;

		spi0 = &qspi;

	};



	chosen {
@@ -37,6 +38,19 @@ &dcc { 
	status = "okay";

};



&qspi {

	status = "okay";

	flash@0 {

		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0>;

		spi-tx-bus-width = <1>;

		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */

		spi-max-frequency = <108000000>; /* Based on DC1 spec */

	};

};



&uart0 {

	status = "okay";

};