Commit dad52589 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Remove Keystone specific dw_pcie_host_ops 



Now that Keystone started using its own msi_irq_chip, remove
Keystone specific callback functions defined in dw_pcie_host_ops.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
parent 117c3b60

drivers/pci/controller/dwc/pcie-designware-host.c

+14 −36
Original line number Diff line number Diff line
@@ -126,17 +126,11 @@ static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) 
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	u64 msi_target;



	if (pp->ops->get_msi_addr)

		msi_target = pp->ops->get_msi_addr(pp);

	else

	msi_target = (u64)pp->msi_data;



	msg->address_lo = lower_32_bits(msi_target);

	msg->address_hi = upper_32_bits(msi_target);



	if (pp->ops->get_msi_data)

		msg->data = pp->ops->get_msi_data(pp, d->hwirq);

	else

	msg->data = d->hwirq;



	dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
@@ -157,9 +151,6 @@ static void dw_pci_bottom_mask(struct irq_data *d) 


	raw_spin_lock_irqsave(&pp->lock, flags);



	if (pp->ops->msi_clear_irq) {

		pp->ops->msi_clear_irq(pp, d->hwirq);

	} else {

	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;

	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;

	bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
@@ -167,7 +158,6 @@ static void dw_pci_bottom_mask(struct irq_data *d) 
	pp->irq_mask[ctrl] |= BIT(bit);

	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,

			    pp->irq_mask[ctrl]);

	}



	raw_spin_unlock_irqrestore(&pp->lock, flags);

}
@@ -180,9 +170,6 @@ static void dw_pci_bottom_unmask(struct irq_data *d) 


	raw_spin_lock_irqsave(&pp->lock, flags);



	if (pp->ops->msi_set_irq) {

		pp->ops->msi_set_irq(pp, d->hwirq);

	} else {

	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;

	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;

	bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
@@ -190,7 +177,6 @@ static void dw_pci_bottom_unmask(struct irq_data *d) 
	pp->irq_mask[ctrl] &= ~BIT(bit);

	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,

			    pp->irq_mask[ctrl]);

	}



	raw_spin_unlock_irqrestore(&pp->lock, flags);

}
@@ -199,20 +185,12 @@ static void dw_pci_bottom_ack(struct irq_data *d) 
{

	struct pcie_port *pp  = irq_data_get_irq_chip_data(d);

	unsigned int res, bit, ctrl;

	unsigned long flags;



	ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;

	res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;

	bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;



	raw_spin_lock_irqsave(&pp->lock, flags);



	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));



	if (pp->ops->msi_irq_ack)

		pp->ops->msi_irq_ack(d->hwirq, pp);



	raw_spin_unlock_irqrestore(&pp->lock, flags);

}



static struct irq_chip dw_pci_msi_bottom_irq_chip = {

drivers/pci/controller/dwc/pcie-designware.h

+0 −5
Original line number Diff line number Diff line
@@ -145,14 +145,9 @@ struct dw_pcie_host_ops { 
	int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,

			     unsigned int devfn, int where, int size, u32 val);

	int (*host_init)(struct pcie_port *pp);

	void (*msi_set_irq)(struct pcie_port *pp, int irq);

	void (*msi_clear_irq)(struct pcie_port *pp, int irq);

	phys_addr_t (*get_msi_addr)(struct pcie_port *pp);

	u32 (*get_msi_data)(struct pcie_port *pp, int pos);

	void (*scan_bus)(struct pcie_port *pp);

	void (*set_num_vectors)(struct pcie_port *pp);

	int (*msi_host_init)(struct pcie_port *pp);

	void (*msi_irq_ack)(int irq, struct pcie_port *pp);

};



struct pcie_port {