Commit da6b9937 authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher
Browse files

drm/amdgpu: Enable TCP channel hashing for Aldebaran 



Enable TCP channel hashing to match DF hash settings for Aldebaran.

Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarJoseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: default avatarHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ddec8d3b

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

+11 −6
Original line number Diff line number Diff line
@@ -219,11 +219,11 @@ static void df_v3_6_query_hashes(struct amdgpu_device *adev) 
	adev->df.hash_status.hash_2m = false;

	adev->df.hash_status.hash_1g = false;



	if (adev->asic_type != CHIP_ARCTURUS)

		return;



	/* encoding for hash-enabled on Arcturus */

	if (adev->df.funcs->get_fb_channel_number(adev) == 0xe) {

	/* encoding for hash-enabled on Arcturus and Aldebaran */

	if ((adev->asic_type == CHIP_ARCTURUS &&

	     adev->df.funcs->get_fb_channel_number(adev) == 0xe) ||

	     (adev->asic_type == CHIP_ALDEBARAN &&

	      adev->df.funcs->get_fb_channel_number(adev) == 0x1e)) {

		tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);

		adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,

						DF_CS_UMC_AON0_DfGlobalCtrl,
@@ -278,7 +278,12 @@ static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev) 
	u32 tmp;



	tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);

	if (adev->asic_type == CHIP_ALDEBARAN)

		tmp &=

		ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;

	else

		tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;



	tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;



	return tmp;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+2 −1
Original line number Diff line number Diff line
@@ -3937,7 +3937,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 
{

	u32 tmp;



	if (adev->asic_type != CHIP_ARCTURUS)

	if (adev->asic_type != CHIP_ARCTURUS &&

	    adev->asic_type != CHIP_ALDEBARAN)

		return;



	tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);

drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK						0x00000001L

#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK						0x00000002L

#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK						0x0000003CL

#define ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK					0x0000007CL

#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK						0x00000E00L

#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK						0xFFFFF000L