Commit d7fe0cc0 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Fix DSPCLK_GATE_D for VLV 



Fix the DSPCLK_GATE_D access for VLV. The code incorrectly tried to
poke at the ILK+ version of the register which is at the wrong offset.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4548feb1

drivers/gpu/drm/i915/i915_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -1256,7 +1256,7 @@ 
#define  DSTATE_PLL_D3_OFF			(1<<3)

#define  DSTATE_GFX_CLOCK_GATING		(1<<1)

#define  DSTATE_DOT_CLOCK_GATING		(1<<0)

#define DSPCLK_GATE_D		0x6200

#define DSPCLK_GATE_D	(dev_priv->info->display_mmio_offset + 0x6200)

# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */

# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */

# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */

drivers/gpu/drm/i915/intel_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -4797,7 +4797,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;



	I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);



	/* WaDisableEarlyCull:vlv */

	I915_WRITE(_3D_CHICKEN3,