Commit d7d45d5d authored by Zhen Lei's avatar Zhen Lei Committed by Wei Xu
Browse files

arm64: dts: hisilicon: normalize the node name of the SMMU devices 



Change the node name of the SMMU devices to match "^iommu@[0-9a-f]*".
Otherwise, the errors similar to the following will be reported by
arm,smmu-v3.yaml.

smmu_pcie: $nodename:0: 'smmu_pcie' does not match '^iommu@[0-9a-f]*'

Signed-off-by: default avatarZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent ee6ff04f

arch/arm64/boot/dts/hisilicon/hip06.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -330,7 +330,7 @@ mbigen_sas0: intc-sas0 { 
	 *  when iommu-map entry is used along with the PCIe node.

	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html

	 */

	smmu0: smmu_pcie {

	smmu0: iommu@a0040000 {

		compatible = "arm,smmu-v3";

		reg = <0x0 0xa0040000 0x0 0x20000>;

		#iommu-cells = <1>;

arch/arm64/boot/dts/hisilicon/hip07.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -1161,7 +1161,7 @@ mbigen_smmu_dsa: intc_smmu_dsa { 
	 *  when iommu-map entry is used along with the PCIe node.

	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html

	 */

	smmu0: smmu_pcie {

	smmu0: iommu@a0040000 {

		compatible = "arm,smmu-v3";

		reg = <0x0 0xa0040000 0x0 0x20000>;

		#iommu-cells = <1>;
@@ -1170,7 +1170,7 @@ smmu0: smmu_pcie { 
		hisilicon,broken-prefetch-cmd;

		status = "disabled";

	};

	p0_smmu_alg_a: smmu_alg@d0040000 {

	p0_smmu_alg_a: iommu@d0040000 {

		compatible = "arm,smmu-v3";

		reg = <0x0 0xd0040000 0x0 0x20000>;

		interrupt-parent = <&p0_mbigen_smmu_alg_a>;
@@ -1183,7 +1183,7 @@ p0_smmu_alg_a: smmu_alg@d0040000 { 
		hisilicon,broken-prefetch-cmd;

		/* smmu-cb-memtype = <0x0 0x1>;*/

	};

	p0_smmu_alg_b: smmu_alg@8,d0040000 {

	p0_smmu_alg_b: iommu@8d0040000 {

		compatible = "arm,smmu-v3";

		reg = <0x8 0xd0040000 0x0 0x20000>;

		interrupt-parent = <&p0_mbigen_smmu_alg_b>;
@@ -1196,7 +1196,7 @@ p0_smmu_alg_b: smmu_alg@8,d0040000 { 
		hisilicon,broken-prefetch-cmd;

		/* smmu-cb-memtype = <0x0 0x1>;*/

	};

	p1_smmu_alg_a: smmu_alg@400,d0040000 {

	p1_smmu_alg_a: iommu@400d0040000 {

		compatible = "arm,smmu-v3";

		reg = <0x400 0xd0040000 0x0 0x20000>;

		interrupt-parent = <&p1_mbigen_smmu_alg_a>;
@@ -1209,7 +1209,7 @@ p1_smmu_alg_a: smmu_alg@400,d0040000 { 
		hisilicon,broken-prefetch-cmd;

		/* smmu-cb-memtype = <0x0 0x1>;*/

	};

	p1_smmu_alg_b: smmu_alg@408,d0040000 {

	p1_smmu_alg_b: iommu@408d0040000 {

		compatible = "arm,smmu-v3";

		reg = <0x408 0xd0040000 0x0 0x20000>;

		interrupt-parent = <&p1_mbigen_smmu_alg_b>;