Commit d0e70d13 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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dt-bindings: clock: tegra-car: Document new clock sub-nodes 



Document sub-nodes which describe Tegra SoC clocks that require a higher
voltage of the core power domain in order to operate properly on a higher
clock rates.  Each node contains a phandle to OPP table and power domain.

The root PLLs and system clocks don't have any specific device dedicated
to them, clock controller is in charge of managing power for them.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent f64de71a

Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml

+37 −0
Original line number Diff line number Diff line
@@ -42,6 +42,36 @@ properties: 
  "#reset-cells":

    const: 1



patternProperties:

  "^(sclk)|(pll-[cem])$":

    type: object

    properties:

      compatible:

        enum:

          - nvidia,tegra20-sclk

          - nvidia,tegra30-sclk

          - nvidia,tegra30-pllc

          - nvidia,tegra30-plle

          - nvidia,tegra30-pllm



      operating-points-v2: true



      clocks:

        items:

          - description: node's clock



      power-domains:

        maxItems: 1

        description: phandle to the core SoC power domain



    required:

      - compatible

      - operating-points-v2

      - clocks

      - power-domains



    additionalProperties: false



required:

  - compatible

  - reg
@@ -59,6 +89,13 @@ examples: 
        reg = <0x60006000 0x1000>;

        #clock-cells = <1>;

        #reset-cells = <1>;



        sclk {

            compatible = "nvidia,tegra20-sclk";

            operating-points-v2 = <&opp_table>;

            clocks = <&tegra_car TEGRA20_CLK_SCLK>;

            power-domains = <&domain>;

        };

    };



    usb-controller@c5004000 {