Commit d0a767f7 authored by Sung Joon Kim's avatar Sung Joon Kim Committed by Alex Deucher
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drm/amd/display: Revert "drm/amd/display: Add a check for idle power optimization" 



Revert commit 434cf7af ("drm/amd/display: Add a check for idle power optimization")
Because it cause Freesync and S4 regression

Reviewed-by: default avatarAric Cyr <aric.cyr@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarSung Joon Kim <sungkim@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 061863e5

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −19
Original line number Diff line number Diff line
@@ -4908,8 +4908,7 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable) 


void dc_allow_idle_optimizations(struct dc *dc, bool allow)

{

	if (dc->debug.disable_idle_power_optimizations ||

		(dc->caps.ips_support && dc->config.disable_ips))

	if (dc->debug.disable_idle_power_optimizations)

		return;



	if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
@@ -4923,23 +4922,6 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow) 
		dc->idle_optimizations_allowed = allow;

}



bool dc_is_idle_power_optimized(struct dc *dc)

{

	uint32_t idle_state = 0;



	if (dc->debug.disable_idle_power_optimizations)

		return false;



	if (dc->hwss.get_idle_state)

		idle_state = dc->hwss.get_idle_state(dc);



	if ((idle_state & DMUB_IPS1_ALLOW_MASK) ||

		(idle_state & DMUB_IPS2_ALLOW_MASK))

		return true;



	return false;

}



/* set min and max memory clock to lowest and highest DPM level, respectively */

void dc_unlock_memory_clock_frequency(struct dc *dc)

{

drivers/gpu/drm/amd/display/dc/dc.h

+0 −1
Original line number Diff line number Diff line
@@ -2317,7 +2317,6 @@ bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_ 
				struct dc_cursor_attributes *cursor_attr);



void dc_allow_idle_optimizations(struct dc *dc, bool allow);

bool dc_is_idle_power_optimized(struct dc *dc);



/* set min and max memory clock to lowest and highest DPM level, respectively */

void dc_unlock_memory_clock_frequency(struct dc *dc);

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

+0 −1
Original line number Diff line number Diff line
@@ -352,7 +352,6 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 
			funcs->init_reg_offsets = dmub_srv_dcn35_regs_init;



			funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up;

			funcs->should_detect = dmub_dcn35_should_detect;

			break;



	default: