Commit cff81a61 authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Vinod Koul
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phy: mediatek: hdmi: mt2701: use common helper to access registers 



Use MediaTek phy's common helper to access registers, then we can remove
hdmi's I/O helpers.

Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220920090038.15133-9-chunfeng.yun@mediatek.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent a98d935e

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

+71 −75
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
 */



#include "phy-mtk-hdmi.h"

#include "phy-mtk-io.h"



#define HDMI_CON0	0x00

#define RG_HDMITX_DRV_IBIAS_MASK	GENMASK(5, 0)
@@ -49,20 +50,21 @@ 
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)

{

	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);

	void __iomem *base = hdmi_phy->regs;



	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);

	mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);

	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);

	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);

	usleep_range(80, 100);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);

	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);

	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	usleep_range(80, 100);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	usleep_range(80, 100);

	return 0;

}
@@ -70,20 +72,21 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw) 
static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)

{

	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);

	void __iomem *base = hdmi_phy->regs;



	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	usleep_range(80, 100);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);

	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);

	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);

	usleep_range(80, 100);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);

	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);

	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);

	mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);

	usleep_range(80, 100);

}
@@ -97,6 +100,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
				 unsigned long parent_rate)

{

	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);

	void __iomem *base = hdmi_phy->regs;

	u32 pos_div;



	if (rate <= 64000000)
@@ -106,37 +110,25 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	else

		pos_div = 1;



	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IC_MASK, 0x1),

			  RG_HTPLL_IC_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IR_MASK, 0x1),

			  RG_HTPLL_IR_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, FIELD_PREP(RG_HDMITX_TX_POSDIV_MASK, pos_div),

			  RG_HDMITX_TX_POSDIV_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKSEL_MASK, 1),

			  RG_HTPLL_FBKSEL_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKDIV_MASK, 19),

			  RG_HTPLL_FBKDIV_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, FIELD_PREP(RG_HTPLL_DIVEN_MASK, 0x2),

			  RG_HTPLL_DIVEN_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BP_MASK, 0xc),

			  RG_HTPLL_BP_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BC_MASK, 0x2),

			  RG_HTPLL_BC_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BR_MASK, 0x1),

			  RG_HTPLL_BR_MASK);



	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_PRED_IBIAS_MASK, 0x3),

			  RG_HDMITX_PRED_IBIAS_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_DRV_IMP_MASK, 0x28),

			  RG_HDMITX_DRV_IMP_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);

	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, FIELD_PREP(RG_HDMITX_DRV_IBIAS_MASK, 0xa),

			  RG_HDMITX_DRV_IBIAS_MASK);

	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK);

	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);

	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1);

	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1);

	mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div);

	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1);

	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19);

	mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2);

	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc);

	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2);

	mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1);



	mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP);

	mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3);

	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK);

	mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28);

	mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28);

	mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa);

	return 0;

}
@@ -184,37 +176,41 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = { 


static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)

{

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);

	void __iomem *base = hdmi_phy->regs;



	mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);

	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);

	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);

	usleep_range(80, 100);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);

	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);

	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	usleep_range(80, 100);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	usleep_range(80, 100);

}



static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)

{

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	void __iomem *base = hdmi_phy->regs;



	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);

	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);

	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);

	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);

	usleep_range(80, 100);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);

	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);

	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);

	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);

	usleep_range(80, 100);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);

	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);

	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);

	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);

	mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);

	usleep_range(80, 100);

}