Loading Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml +3 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ properties: - const: nvidia,tegra30-hda - items: - enum: - nvidia,tegra234-hda - nvidia,tegra194-hda - nvidia,tegra186-hda - nvidia,tegra210-hda Loading @@ -41,9 +42,11 @@ properties: maxItems: 1 clocks: minItems: 2 maxItems: 3 clock-names: minItems: 2 items: - const: hda - const: hda2hdmi Loading include/dt-bindings/clock/tegra234-clock.h +133 −2 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H Loading @@ -9,6 +9,26 @@ * @defgroup bpmp_clock_ids Clock ID's * @{ */ /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ #define TEGRA234_CLK_AHUB 4U /** @brief output of gate CLK_ENB_APB2APE */ #define TEGRA234_CLK_APB2APE 5U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ #define TEGRA234_CLK_APE 6U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ #define TEGRA234_CLK_AUD_MCLK 7U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ #define TEGRA234_CLK_DMIC1 15U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ #define TEGRA234_CLK_DMIC2 16U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ #define TEGRA234_CLK_DMIC3 17U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ #define TEGRA234_CLK_DMIC4 18U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ #define TEGRA234_CLK_DSPK1 29U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ #define TEGRA234_CLK_DSPK2 30U /** * @brief controls the EMC clock frequency. * @details Doing a clk_set_rate on this clock will select the Loading @@ -20,15 +40,126 @@ #define TEGRA234_CLK_EMC 31U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ #define TEGRA234_CLK_I2C1 48U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ #define TEGRA234_CLK_I2C2 49U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ #define TEGRA234_CLK_I2C3 50U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ #define TEGRA234_CLK_I2C4 51U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ #define TEGRA234_CLK_I2C6 52U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ #define TEGRA234_CLK_I2C7 53U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ #define TEGRA234_CLK_I2C8 54U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ #define TEGRA234_CLK_I2C9 55U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ #define TEGRA234_CLK_I2S1 56U /** @brief clock recovered from I2S1 input */ #define TEGRA234_CLK_I2S1_SYNC_INPUT 57U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ #define TEGRA234_CLK_I2S2 58U /** @brief clock recovered from I2S2 input */ #define TEGRA234_CLK_I2S2_SYNC_INPUT 59U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ #define TEGRA234_CLK_I2S3 60U /** @brief clock recovered from I2S3 input */ #define TEGRA234_CLK_I2S3_SYNC_INPUT 61U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ #define TEGRA234_CLK_I2S4 62U /** @brief clock recovered from I2S4 input */ #define TEGRA234_CLK_I2S4_SYNC_INPUT 63U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ #define TEGRA234_CLK_I2S5 64U /** @brief clock recovered from I2S5 input */ #define TEGRA234_CLK_I2S5_SYNC_INPUT 65U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ #define TEGRA234_CLK_I2S6 66U /** @brief clock recovered from I2S6 input */ #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ #define TEGRA234_CLK_PLLA 93U /** @brief PLLP clk output */ #define TEGRA234_CLK_PLLP_OUT0 102U /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ #define TEGRA234_CLK_PLLA_OUT0 104U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ #define TEGRA234_CLK_PWM1 105U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ #define TEGRA234_CLK_PWM2 106U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ #define TEGRA234_CLK_PWM3 107U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ #define TEGRA234_CLK_PWM4 108U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ #define TEGRA234_CLK_PWM5 109U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ #define TEGRA234_CLK_PWM6 110U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ #define TEGRA234_CLK_PWM7 111U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ #define TEGRA234_CLK_PWM8 112U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ #define TEGRA234_CLK_SDMMC4 123U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ #define TEGRA234_CLK_SYNC_DMIC1 139U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ #define TEGRA234_CLK_SYNC_DMIC2 140U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ #define TEGRA234_CLK_SYNC_DMIC3 141U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ #define TEGRA234_CLK_SYNC_DMIC4 142U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ #define TEGRA234_CLK_SYNC_DSPK1 143U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ #define TEGRA234_CLK_SYNC_DSPK2 144U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ #define TEGRA234_CLK_SYNC_I2S1 145U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ #define TEGRA234_CLK_SYNC_I2S2 146U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ #define TEGRA234_CLK_SYNC_I2S3 147U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ #define TEGRA234_CLK_SYNC_I2S4 148U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ #define TEGRA234_CLK_SYNC_I2S5 149U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ #define TEGRA234_CLK_SYNC_I2S6 150U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ #define TEGRA234_CLK_UARTA 155U /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ #define TEGRA234_CLK_PEX1_C6_CORE 161U /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ #define TEGRA234_CLK_PEX2_C7_CORE 171U /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ #define TEGRA234_CLK_PEX2_C8_CORE 172U /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ #define TEGRA234_CLK_PEX2_C9_CORE 173U /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ #define TEGRA234_CLK_PEX2_C10_CORE 187U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ #define TEGRA234_CLK_PEX0_C0_CORE 220U /** @brief output of gate CLK_ENB_PEX0_CORE_1 */ #define TEGRA234_CLK_PEX0_C1_CORE 221U /** @brief output of gate CLK_ENB_PEX0_CORE_2 */ #define TEGRA234_CLK_PEX0_C2_CORE 222U /** @brief output of gate CLK_ENB_PEX0_CORE_3 */ #define TEGRA234_CLK_PEX0_C3_CORE 223U /** @brief output of gate CLK_ENB_PEX0_CORE_4 */ #define TEGRA234_CLK_PEX0_C4_CORE 224U /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ #define TEGRA234_CLK_PEX1_C5_CORE 225U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ #define TEGRA234_CLK_AZA_2XBIT 457U /** @brief aza_2xbitclk / 2 (aza_bitclk) */ #define TEGRA234_CLK_AZA_BIT 458U #endif include/dt-bindings/memory/tegra234-mc.h +75 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H #define DT_BINDINGS_MEMORY_TEGRA234_MC_H Loading @@ -7,15 +8,59 @@ #define TEGRA234_SID_INVALID 0x00 #define TEGRA234_SID_PASSTHROUGH 0x7f /* NISO0 stream IDs */ #define TEGRA234_SID_APE 0x02 #define TEGRA234_SID_HDA 0x03 #define TEGRA234_SID_PCIE0 0x12 #define TEGRA234_SID_PCIE4 0x13 #define TEGRA234_SID_PCIE5 0x14 #define TEGRA234_SID_PCIE6 0x15 #define TEGRA234_SID_PCIE9 0x1f /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 #define TEGRA234_SID_PCIE1 0x05 #define TEGRA234_SID_PCIE2 0x06 #define TEGRA234_SID_PCIE3 0x07 #define TEGRA234_SID_PCIE7 0x08 #define TEGRA234_SID_PCIE8 0x09 #define TEGRA234_SID_PCIE10 0x0b #define TEGRA234_SID_BPMP 0x10 /* * memory client IDs */ /* High-definition audio (HDA) read clients */ #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 /* PCIE6 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 /* PCIE6 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 /* PCIE7 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a /* PCIE7 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 /* PCIE8 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 /* High-definition audio (HDA) write clients */ #define TEGRA234_MEMORY_CLIENT_HDAW 0x35 /* PCIE8 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b /* PCIE9 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c /* PCIE6r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d /* PCIE9 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e /* PCIE10 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f /* PCIE10 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 /* PCIE10r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 /* PCIE7r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 /* sdmmcd memory write client */ Loading @@ -28,5 +73,35 @@ #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 /* BPMPDMA write client */ #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 /* APEDMA read client */ #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f /* APEDMA write client */ #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 /* PCIE0 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 /* PCIE0 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 /* PCIE1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda /* PCIE1 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb /* PCIE2 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc /* PCIE2 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd /* PCIE3 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde /* PCIE3 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf /* PCIE4 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 /* PCIE4 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 /* PCIE5 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 /* PCIE5 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 /* PCIE5r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef #endif include/dt-bindings/power/tegra234-powergate.h 0 → 100644 +22 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef __ABI_MACH_T234_POWERGATE_T234_H_ #define __ABI_MACH_T234_POWERGATE_T234_H_ #define TEGRA234_POWER_DOMAIN_AUD 2U #define TEGRA234_POWER_DOMAIN_DISP 3U #define TEGRA234_POWER_DOMAIN_PCIEX8A 5U #define TEGRA234_POWER_DOMAIN_PCIEX4A 6U #define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U #define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U #define TEGRA234_POWER_DOMAIN_PCIEX1A 9U #define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U #define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U #define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U #define TEGRA234_POWER_DOMAIN_PCIEX8B 16U #define TEGRA234_POWER_DOMAIN_MGBEA 17U #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U #endif include/dt-bindings/reset/tegra234-reset.h +44 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H #define DT_BINDINGS_RESET_TEGRA234_RESET_H Loading @@ -10,8 +10,51 @@ * @brief Identifiers for Resets controllable by firmware * @{ */ #define TEGRA234_RESET_PEX1_CORE_6 11U #define TEGRA234_RESET_PEX1_CORE_6_APB 12U #define TEGRA234_RESET_PEX1_COMMON_APB 13U #define TEGRA234_RESET_PEX2_CORE_7 14U #define TEGRA234_RESET_PEX2_CORE_7_APB 15U #define TEGRA234_RESET_HDA 20U #define TEGRA234_RESET_HDACODEC 21U #define TEGRA234_RESET_I2C1 24U #define TEGRA234_RESET_PEX2_CORE_8 25U #define TEGRA234_RESET_PEX2_CORE_8_APB 26U #define TEGRA234_RESET_PEX2_CORE_9 27U #define TEGRA234_RESET_PEX2_CORE_9_APB 28U #define TEGRA234_RESET_I2C2 29U #define TEGRA234_RESET_I2C3 30U #define TEGRA234_RESET_I2C4 31U #define TEGRA234_RESET_I2C6 32U #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U #define TEGRA234_RESET_PEX2_CORE_10 56U #define TEGRA234_RESET_PEX2_CORE_10_APB 57U #define TEGRA234_RESET_PEX2_COMMON_APB 58U #define TEGRA234_RESET_PWM1 68U #define TEGRA234_RESET_PWM2 69U #define TEGRA234_RESET_PWM3 70U #define TEGRA234_RESET_PWM4 71U #define TEGRA234_RESET_PWM5 72U #define TEGRA234_RESET_PWM6 73U #define TEGRA234_RESET_PWM7 74U #define TEGRA234_RESET_PWM8 75U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U #define TEGRA234_RESET_PEX0_CORE_2 118U #define TEGRA234_RESET_PEX0_CORE_3 119U #define TEGRA234_RESET_PEX0_CORE_4 120U #define TEGRA234_RESET_PEX0_CORE_0_APB 121U #define TEGRA234_RESET_PEX0_CORE_1_APB 122U #define TEGRA234_RESET_PEX0_CORE_2_APB 123U #define TEGRA234_RESET_PEX0_CORE_3_APB 124U #define TEGRA234_RESET_PEX0_CORE_4_APB 125U #define TEGRA234_RESET_PEX0_COMMON_APB 126U #define TEGRA234_RESET_PEX1_CORE_5 129U #define TEGRA234_RESET_PEX1_CORE_5_APB 130U /** @} */ Loading Loading
Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.yaml +3 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ properties: - const: nvidia,tegra30-hda - items: - enum: - nvidia,tegra234-hda - nvidia,tegra194-hda - nvidia,tegra186-hda - nvidia,tegra210-hda Loading @@ -41,9 +42,11 @@ properties: maxItems: 1 clocks: minItems: 2 maxItems: 3 clock-names: minItems: 2 items: - const: hda - const: hda2hdmi Loading
include/dt-bindings/clock/tegra234-clock.h +133 −2 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H Loading @@ -9,6 +9,26 @@ * @defgroup bpmp_clock_ids Clock ID's * @{ */ /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ #define TEGRA234_CLK_AHUB 4U /** @brief output of gate CLK_ENB_APB2APE */ #define TEGRA234_CLK_APB2APE 5U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ #define TEGRA234_CLK_APE 6U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ #define TEGRA234_CLK_AUD_MCLK 7U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ #define TEGRA234_CLK_DMIC1 15U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ #define TEGRA234_CLK_DMIC2 16U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ #define TEGRA234_CLK_DMIC3 17U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ #define TEGRA234_CLK_DMIC4 18U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ #define TEGRA234_CLK_DSPK1 29U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ #define TEGRA234_CLK_DSPK2 30U /** * @brief controls the EMC clock frequency. * @details Doing a clk_set_rate on this clock will select the Loading @@ -20,15 +40,126 @@ #define TEGRA234_CLK_EMC 31U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ #define TEGRA234_CLK_I2C1 48U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ #define TEGRA234_CLK_I2C2 49U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ #define TEGRA234_CLK_I2C3 50U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ #define TEGRA234_CLK_I2C4 51U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ #define TEGRA234_CLK_I2C6 52U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ #define TEGRA234_CLK_I2C7 53U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ #define TEGRA234_CLK_I2C8 54U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ #define TEGRA234_CLK_I2C9 55U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ #define TEGRA234_CLK_I2S1 56U /** @brief clock recovered from I2S1 input */ #define TEGRA234_CLK_I2S1_SYNC_INPUT 57U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ #define TEGRA234_CLK_I2S2 58U /** @brief clock recovered from I2S2 input */ #define TEGRA234_CLK_I2S2_SYNC_INPUT 59U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ #define TEGRA234_CLK_I2S3 60U /** @brief clock recovered from I2S3 input */ #define TEGRA234_CLK_I2S3_SYNC_INPUT 61U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ #define TEGRA234_CLK_I2S4 62U /** @brief clock recovered from I2S4 input */ #define TEGRA234_CLK_I2S4_SYNC_INPUT 63U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ #define TEGRA234_CLK_I2S5 64U /** @brief clock recovered from I2S5 input */ #define TEGRA234_CLK_I2S5_SYNC_INPUT 65U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ #define TEGRA234_CLK_I2S6 66U /** @brief clock recovered from I2S6 input */ #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ #define TEGRA234_CLK_PLLA 93U /** @brief PLLP clk output */ #define TEGRA234_CLK_PLLP_OUT0 102U /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ #define TEGRA234_CLK_PLLA_OUT0 104U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ #define TEGRA234_CLK_PWM1 105U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ #define TEGRA234_CLK_PWM2 106U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ #define TEGRA234_CLK_PWM3 107U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ #define TEGRA234_CLK_PWM4 108U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ #define TEGRA234_CLK_PWM5 109U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ #define TEGRA234_CLK_PWM6 110U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ #define TEGRA234_CLK_PWM7 111U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ #define TEGRA234_CLK_PWM8 112U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ #define TEGRA234_CLK_SDMMC4 123U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ #define TEGRA234_CLK_SYNC_DMIC1 139U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ #define TEGRA234_CLK_SYNC_DMIC2 140U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ #define TEGRA234_CLK_SYNC_DMIC3 141U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ #define TEGRA234_CLK_SYNC_DMIC4 142U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ #define TEGRA234_CLK_SYNC_DSPK1 143U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ #define TEGRA234_CLK_SYNC_DSPK2 144U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ #define TEGRA234_CLK_SYNC_I2S1 145U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ #define TEGRA234_CLK_SYNC_I2S2 146U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ #define TEGRA234_CLK_SYNC_I2S3 147U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ #define TEGRA234_CLK_SYNC_I2S4 148U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ #define TEGRA234_CLK_SYNC_I2S5 149U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ #define TEGRA234_CLK_SYNC_I2S6 150U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ #define TEGRA234_CLK_UARTA 155U /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ #define TEGRA234_CLK_PEX1_C6_CORE 161U /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ #define TEGRA234_CLK_PEX2_C7_CORE 171U /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ #define TEGRA234_CLK_PEX2_C8_CORE 172U /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ #define TEGRA234_CLK_PEX2_C9_CORE 173U /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ #define TEGRA234_CLK_PEX2_C10_CORE 187U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ #define TEGRA234_CLK_PEX0_C0_CORE 220U /** @brief output of gate CLK_ENB_PEX0_CORE_1 */ #define TEGRA234_CLK_PEX0_C1_CORE 221U /** @brief output of gate CLK_ENB_PEX0_CORE_2 */ #define TEGRA234_CLK_PEX0_C2_CORE 222U /** @brief output of gate CLK_ENB_PEX0_CORE_3 */ #define TEGRA234_CLK_PEX0_C3_CORE 223U /** @brief output of gate CLK_ENB_PEX0_CORE_4 */ #define TEGRA234_CLK_PEX0_C4_CORE 224U /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ #define TEGRA234_CLK_PEX1_C5_CORE 225U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ #define TEGRA234_CLK_AZA_2XBIT 457U /** @brief aza_2xbitclk / 2 (aza_bitclk) */ #define TEGRA234_CLK_AZA_BIT 458U #endif
include/dt-bindings/memory/tegra234-mc.h +75 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H #define DT_BINDINGS_MEMORY_TEGRA234_MC_H Loading @@ -7,15 +8,59 @@ #define TEGRA234_SID_INVALID 0x00 #define TEGRA234_SID_PASSTHROUGH 0x7f /* NISO0 stream IDs */ #define TEGRA234_SID_APE 0x02 #define TEGRA234_SID_HDA 0x03 #define TEGRA234_SID_PCIE0 0x12 #define TEGRA234_SID_PCIE4 0x13 #define TEGRA234_SID_PCIE5 0x14 #define TEGRA234_SID_PCIE6 0x15 #define TEGRA234_SID_PCIE9 0x1f /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 #define TEGRA234_SID_PCIE1 0x05 #define TEGRA234_SID_PCIE2 0x06 #define TEGRA234_SID_PCIE3 0x07 #define TEGRA234_SID_PCIE7 0x08 #define TEGRA234_SID_PCIE8 0x09 #define TEGRA234_SID_PCIE10 0x0b #define TEGRA234_SID_BPMP 0x10 /* * memory client IDs */ /* High-definition audio (HDA) read clients */ #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 /* PCIE6 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 /* PCIE6 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 /* PCIE7 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a /* PCIE7 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 /* PCIE8 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 /* High-definition audio (HDA) write clients */ #define TEGRA234_MEMORY_CLIENT_HDAW 0x35 /* PCIE8 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b /* PCIE9 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c /* PCIE6r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d /* PCIE9 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e /* PCIE10 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f /* PCIE10 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 /* PCIE10r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 /* PCIE7r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 /* sdmmcd memory write client */ Loading @@ -28,5 +73,35 @@ #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 /* BPMPDMA write client */ #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 /* APEDMA read client */ #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f /* APEDMA write client */ #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 /* PCIE0 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 /* PCIE0 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 /* PCIE1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda /* PCIE1 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb /* PCIE2 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc /* PCIE2 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd /* PCIE3 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde /* PCIE3 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf /* PCIE4 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 /* PCIE4 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 /* PCIE5 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 /* PCIE5 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 /* PCIE5r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef #endif
include/dt-bindings/power/tegra234-powergate.h 0 → 100644 +22 −0 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef __ABI_MACH_T234_POWERGATE_T234_H_ #define __ABI_MACH_T234_POWERGATE_T234_H_ #define TEGRA234_POWER_DOMAIN_AUD 2U #define TEGRA234_POWER_DOMAIN_DISP 3U #define TEGRA234_POWER_DOMAIN_PCIEX8A 5U #define TEGRA234_POWER_DOMAIN_PCIEX4A 6U #define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U #define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U #define TEGRA234_POWER_DOMAIN_PCIEX1A 9U #define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U #define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U #define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U #define TEGRA234_POWER_DOMAIN_PCIEX8B 16U #define TEGRA234_POWER_DOMAIN_MGBEA 17U #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U #endif
include/dt-bindings/reset/tegra234-reset.h +44 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H #define DT_BINDINGS_RESET_TEGRA234_RESET_H Loading @@ -10,8 +10,51 @@ * @brief Identifiers for Resets controllable by firmware * @{ */ #define TEGRA234_RESET_PEX1_CORE_6 11U #define TEGRA234_RESET_PEX1_CORE_6_APB 12U #define TEGRA234_RESET_PEX1_COMMON_APB 13U #define TEGRA234_RESET_PEX2_CORE_7 14U #define TEGRA234_RESET_PEX2_CORE_7_APB 15U #define TEGRA234_RESET_HDA 20U #define TEGRA234_RESET_HDACODEC 21U #define TEGRA234_RESET_I2C1 24U #define TEGRA234_RESET_PEX2_CORE_8 25U #define TEGRA234_RESET_PEX2_CORE_8_APB 26U #define TEGRA234_RESET_PEX2_CORE_9 27U #define TEGRA234_RESET_PEX2_CORE_9_APB 28U #define TEGRA234_RESET_I2C2 29U #define TEGRA234_RESET_I2C3 30U #define TEGRA234_RESET_I2C4 31U #define TEGRA234_RESET_I2C6 32U #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U #define TEGRA234_RESET_PEX2_CORE_10 56U #define TEGRA234_RESET_PEX2_CORE_10_APB 57U #define TEGRA234_RESET_PEX2_COMMON_APB 58U #define TEGRA234_RESET_PWM1 68U #define TEGRA234_RESET_PWM2 69U #define TEGRA234_RESET_PWM3 70U #define TEGRA234_RESET_PWM4 71U #define TEGRA234_RESET_PWM5 72U #define TEGRA234_RESET_PWM6 73U #define TEGRA234_RESET_PWM7 74U #define TEGRA234_RESET_PWM8 75U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U #define TEGRA234_RESET_PEX0_CORE_2 118U #define TEGRA234_RESET_PEX0_CORE_3 119U #define TEGRA234_RESET_PEX0_CORE_4 120U #define TEGRA234_RESET_PEX0_CORE_0_APB 121U #define TEGRA234_RESET_PEX0_CORE_1_APB 122U #define TEGRA234_RESET_PEX0_CORE_2_APB 123U #define TEGRA234_RESET_PEX0_CORE_3_APB 124U #define TEGRA234_RESET_PEX0_CORE_4_APB 125U #define TEGRA234_RESET_PEX0_COMMON_APB 126U #define TEGRA234_RESET_PEX1_CORE_5 129U #define TEGRA234_RESET_PEX1_CORE_5_APB 130U /** @} */ Loading
