Commit cf9e6d5d authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Mauro Carvalho Chehab
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media: sun4i-csi: Fix data sampling polarity handling 



The CLK_POL field specifies whether data is sampled on the falling or
rising edge of PCLK, not whether the data lines are active high or low.
Evidence of this can be found in the timing diagram labeled "horizontal
size setting and pixel clock timing".

Fix the setting by checking the correct flag, V4L2_MBUS_PCLK_SAMPLE_RISING.
While at it, reorder the three polarity flag checks so HSYNC and VSYNC
are grouped together.

Fixes: 577bbf23 ("media: sunxi: Add A10 CSI driver")
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <mripard@kernel.org>
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 7866d690

drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c

+1 −1
Original line number Diff line number Diff line
@@ -279,8 +279,8 @@ static int sun4i_csi_start_streaming(struct vb2_queue *vq, unsigned int count) 
	       csi->regs + CSI_WIN_CTRL_H_REG);



	hsync_pol = !!(bus->flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH);

	pclk_pol = !!(bus->flags & V4L2_MBUS_DATA_ACTIVE_HIGH);

	vsync_pol = !!(bus->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH);

	pclk_pol = !!(bus->flags & V4L2_MBUS_PCLK_SAMPLE_RISING);

	writel(CSI_CFG_INPUT_FMT(csi_fmt->input) |

	       CSI_CFG_OUTPUT_FMT(csi_fmt->output) |

	       CSI_CFG_VSYNC_POL(vsync_pol) |