Commit cb9c7ab1 authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher
Browse files

drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1 



Enable GFX Power Gating control for GC IP v11.0.1.

Signed-off-by: default avatarTim Huang <tim.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bea9a56a

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+38 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ 
#define GFX11_MEC_HPD_SIZE	2048



#define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L

#define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1	0x1388



#define regCGTT_WD_CLK_CTRL		0x5086

#define regCGTT_WD_CLK_CTRL_BASE_IDX	1
@@ -5279,6 +5280,38 @@ static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 
	.update_spm_vmid = gfx_v11_0_update_spm_vmid,

};



static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)

{

	u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);



	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))

		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;

	else

		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;



	WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);



	// Program RLC_PG_DELAY3 for CGPG hysteresis

	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

		switch (adev->ip_versions[GC_HWIP][0]) {

		case IP_VERSION(11, 0, 1):

			WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);

			break;

		default:

			break;

		}

	}

}



static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)

{

	amdgpu_gfx_rlc_enter_safe_mode(adev);



	gfx_v11_cntl_power_gating(adev, enable);



	amdgpu_gfx_rlc_exit_safe_mode(adev);

}



static int gfx_v11_0_set_powergating_state(void *handle,

					   enum amd_powergating_state state)

{
@@ -5293,6 +5326,11 @@ static int gfx_v11_0_set_powergating_state(void *handle, 
	case IP_VERSION(11, 0, 2):

		amdgpu_gfx_off_ctrl(adev, enable);

		break;

	case IP_VERSION(11, 0, 1):

		gfx_v11_cntl_pg(adev, enable);

		/* TODO: Enable this when GFXOFF is ready */

		// amdgpu_gfx_off_ctrl(adev, enable);

		break;

	default:

		break;

	}