Commit ca5d251b authored by Haohui Mai's avatar Haohui Mai Committed by Alex Deucher
Browse files

drm/amdgpu/sdma: Remove redundant lower_32_bits() calls when settings SDMA doorbell 



Updated the patch for the pre-vega hardware. I kept the clamping code
to be safe.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarHaohui Mai <ricetons@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7dba6e83

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+2 −2
Original line number Diff line number Diff line
@@ -195,7 +195,7 @@ static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) 
	struct amdgpu_device *adev = ring->adev;



	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],

	       (lower_32_bits(ring->wptr) << 2) & 0x3fffc);

	       (ring->wptr << 2) & 0x3fffc);

}



static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
@@ -487,7 +487,7 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev) 
		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);



		ring->wptr = 0;

		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);

		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);



		/* enable DMA RB */

		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

+2 −2
Original line number Diff line number Diff line
@@ -223,7 +223,7 @@ static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) 
{

	struct amdgpu_device *adev = ring->adev;



	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);

	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);

}



static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
@@ -465,7 +465,7 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) 
		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);



		ring->wptr = 0;

		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);

		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);



		/* enable DMA RB */

		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

+4 −4
Original line number Diff line number Diff line
@@ -389,14 +389,14 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 
	if (ring->use_doorbell) {

		u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];

		/* XXX check if swapping is necessary on BE */

		WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));

		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);

		WRITE_ONCE(*wb, ring->wptr << 2);

		WDOORBELL32(ring->doorbell_index, ring->wptr << 2);

	} else if (ring->use_pollmem) {

		u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];



		WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));

		WRITE_ONCE(*wb, ring->wptr << 2);

	} else {

		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);

		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);

	}

}

drivers/gpu/drm/amd/amdgpu/si_dma.c

+2 −3
Original line number Diff line number Diff line
@@ -56,8 +56,7 @@ static void si_dma_ring_set_wptr(struct amdgpu_ring *ring) 
	struct amdgpu_device *adev = ring->adev;

	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;



	WREG32(DMA_RB_WPTR + sdma_offsets[me],

	       (lower_32_bits(ring->wptr) << 2) & 0x3fffc);

	WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);

}



static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
@@ -175,7 +174,7 @@ static int si_dma_start(struct amdgpu_device *adev) 
		WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl);



		ring->wptr = 0;

		WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);

		WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2);

		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE);



		ring->sched.ready = true;