Commit ca33a58d authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Vinod Koul
Browse files

soundwire: intel: cleanup SHIM SYNC 



Regroup offset and bitfields, no functionality change

Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Signed-off-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220823053846.2684635-5-yung-chuan.liao@linux.intel.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent c36b6100

include/linux/soundwire/sdw_intel.h

+9 −8
Original line number Diff line number Diff line
@@ -27,8 +27,17 @@ 
#define SDW_SHIM_LCTL_CPA		BIT(8)

#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)



/* SYNC */

#define SDW_SHIM_SYNC			0xC



#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)

#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)

#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)

#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)

#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)

#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)

#define SDW_SHIM_SYNC_SYNCGO		BIT(24)



#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))

#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))

#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
@@ -45,14 +54,6 @@ 
#define SDW_SHIM_WAKEEN			0x190

#define SDW_SHIM_WAKESTS		0x192



#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)

#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)

#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)

#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)

#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)

#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)

#define SDW_SHIM_SYNC_SYNCGO		BIT(24)



#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)

#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)

#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)