Commit c91ec465 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Remove AR9462 v1.0 support 



v1.0 chips are not available in the market.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 79ebfb85

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

+0 −4
Original line number Diff line number Diff line
@@ -3603,10 +3603,6 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 
	u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);



	if (AR_SREV_9462(ah)) {

		if (AR_SREV_9462_10(ah)) {

			value &= ~AR_SWITCH_TABLE_COM_SPDT;

			value |= 0x00100000;

		}

		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,

				AR_SWITCH_TABLE_COM_AR9462_ALL, value);

	} else

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+3 −85
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 
#include "ar9330_1p1_initvals.h"

#include "ar9330_1p2_initvals.h"

#include "ar9580_1p0_initvals.h"

#include "ar9462_1p0_initvals.h"

#include "ar9462_2p0_initvals.h"



/* General hardware code for the AR9003 hadware family */
@@ -264,63 +263,6 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
				ar9485_1_1_pcie_phy_clkreq_disable_L1,

				ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),

				2);

	} else if (AR_SREV_9462_10(ah)) {

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_1p0_mac_core,

				ARRAY_SIZE(ar9462_1p0_mac_core), 2);

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],

				ar9462_1p0_mac_postamble,

				ARRAY_SIZE(ar9462_1p0_mac_postamble),

				5);



		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],

				ar9462_1p0_baseband_core,

				ARRAY_SIZE(ar9462_1p0_baseband_core),

				2);

		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],

				ar9462_1p0_baseband_postamble,

				ARRAY_SIZE(ar9462_1p0_baseband_postamble), 5);



		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],

				ar9462_1p0_radio_core,

				ARRAY_SIZE(ar9462_1p0_radio_core), 2);

		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],

				ar9462_1p0_radio_postamble,

				ARRAY_SIZE(ar9462_1p0_radio_postamble), 5);



		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],

				ar9462_1p0_soc_preamble,

				ARRAY_SIZE(ar9462_1p0_soc_preamble), 2);

		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],

				ar9462_1p0_soc_postamble,

				ARRAY_SIZE(ar9462_1p0_soc_postamble), 5);



		INIT_INI_ARRAY(&ah->iniModesRxGain,

				ar9462_common_rx_gain_table_1p0,

				ARRAY_SIZE(ar9462_common_rx_gain_table_1p0), 2);



		/* Awake -> Sleep Setting */

		INIT_INI_ARRAY(&ah->iniPcieSerdes,

			ar9462_pcie_phy_clkreq_disable_L1_1p0,

			ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),

			2);



		/* Sleep -> Awake Setting */

		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,

			ar9462_pcie_phy_clkreq_disable_L1_1p0,

			ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),

			2);



		INIT_INI_ARRAY(&ah->iniModesAdditional,

				ar9462_modes_fast_clock_1p0,

				ARRAY_SIZE(ar9462_modes_fast_clock_1p0), 3);

		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

				AR9462_BB_CTX_COEFJ(1p0),

				ARRAY_SIZE(AR9462_BB_CTX_COEFJ(1p0)), 2);



	} else if (AR_SREV_9462_20(ah)) {



		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -537,11 +479,6 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) 
			ar9580_1p0_lowest_ob_db_tx_gain_table,

			ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),

			5);

	else if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9462_modes_low_ob_db_tx_gain_table_1p0,

			ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_1p0),

			5);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9462_modes_low_ob_db_tx_gain_table_2p0,
@@ -581,11 +518,6 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 
			ar9580_1p0_high_ob_db_tx_gain_table,

			ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),

			5);

	else if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9462_modes_high_ob_db_tx_gain_table_1p0,

			ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_1p0),

			5);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9462_modes_high_ob_db_tx_gain_table_2p0,
@@ -712,11 +644,6 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) 
				ar9580_1p0_rx_gain_table,

				ARRAY_SIZE(ar9580_1p0_rx_gain_table),

				2);

	else if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

				ar9462_common_rx_gain_table_1p0,

				ARRAY_SIZE(ar9462_common_rx_gain_table_1p0),

				2);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

				ar9462_common_rx_gain_table_2p0,
@@ -751,11 +678,6 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 
			ar9485Common_wo_xlna_rx_gain_1_1,

			ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),

			2);

	else if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			ar9462_common_wo_xlna_rx_gain_table_1p0,

			ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_1p0),

			2);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			ar9462_common_wo_xlna_rx_gain_table_2p0,
@@ -775,11 +697,7 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 


static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)

{

	if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			ar9462_common_mixed_rx_gain_table_1p0,

			ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_1p0), 2);

	else if (AR_SREV_9462_20(ah))

	if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			       ar9462_common_mixed_rx_gain_table_2p0,

			       ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

+4 −34
Original line number Diff line number Diff line
@@ -274,14 +274,6 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah) 
	ath_dbg(common, MCI, "MCI send REMOTE_RESET\n");

	ar9003_mci_remote_reset(ah, true);



	/*

	 * This delay is required for the reset delay worst case value 255 in

	 * MCI_COMMAND2 register

	 */



	if (AR_SREV_9462_10(ah))

		udelay(252);



	ath_dbg(common, MCI, "MCI Send REQ_WAKE to remoter(BT)\n");

	ar9003_mci_send_req_wake(ah, true);
@@ -291,8 +283,6 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah) 
		ath_dbg(common, MCI, "MCI SYS_WAKING from remote(BT)\n");

		mci->bt_state = MCI_BT_AWAKE;



		if (AR_SREV_9462_10(ah))

			udelay(10);

		/*

		 * we don't need to send more remote_reset at this moment.

		 * If BT receive first remote_reset, then BT HW will
@@ -339,15 +329,14 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah) 
		REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,

			  AR_MCI_INTERRUPT_BT_PRI);



		if (AR_SREV_9462_10(ah) || mci->is_2g) {

		if (mci->is_2g) {

			/* Send LNA_TRANS */

			ath_dbg(common, MCI, "MCI send LNA_TRANS to BT\n");

			ar9003_mci_send_lna_transfer(ah, true);

			udelay(5);

		}



		if (AR_SREV_9462_10(ah) || (mci->is_2g &&

					    !mci->update_2g5g)) {

		if ((mci->is_2g && !mci->update_2g5g)) {

			if (ar9003_mci_wait_for_interrupt(ah,

				AR_MCI_INTERRUPT_RX_MSG_RAW,

				AR_MCI_INTERRUPT_RX_MSG_LNA_INFO,
@@ -358,14 +347,6 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah) 
				ath_dbg(common, MCI,

					"MCI BT didn't respond to LNA_TRANS\n");

		}



		if (AR_SREV_9462_10(ah)) {

			/* Send another remote_reset to deassert BT clk_req. */

			ath_dbg(common, MCI,

				"MCI another remote_reset to deassert clk_req\n");

			ar9003_mci_remote_reset(ah, true);

			udelay(252);

		}

	}



	/* Clear the extra redundant SYS_WAKING from BT */
@@ -618,9 +599,6 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, 
	} else

		ath_dbg(common, MCI, "MCI SCHED one step look ahead off\n");



	if (AR_SREV_9462_10(ah))

		regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10);



	REG_WRITE(ah, AR_BTCOEX_CTRL, regval);



	if (AR_SREV_9462_20(ah)) {
@@ -771,9 +749,6 @@ static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done) 
			ar9003_mci_send_coex_bt_flags(ah, wait_done,

					MCI_GPM_COEX_BT_FLAGS_SET, to_set);

	}



	if (AR_SREV_9462_10(ah) && (mci->bt_state != MCI_BT_SLEEP))

		mci->update_2g5g = false;

}



static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
@@ -810,9 +785,6 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header, 
	switch (opcode) {

	case MCI_GPM_COEX_BT_UPDATE_FLAGS:



		if (AR_SREV_9462_10(ah))

			break;



		if (*(((u8 *)payload) + MCI_GPM_COEX_B_BT_FLAGS_OP) ==

		    MCI_GPM_COEX_BT_FLAGS_READ)

			break;
@@ -1438,9 +1410,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) 
		break;



	case MCI_STATE_SEND_STATUS_QUERY:

		query_type = (AR_SREV_9462_10(ah)) ?

				MCI_GPM_COEX_QUERY_BT_ALL_INFO :

				MCI_GPM_COEX_QUERY_BT_TOPOLOGY;

		query_type = MCI_GPM_COEX_QUERY_BT_TOPOLOGY;



		ar9003_mci_send_coex_bt_status_query(ah, true, query_type);

		break;

drivers/net/wireless/ath/ath9k/ar9003_phy.h

+2 −4
Original line number Diff line number Diff line
@@ -617,10 +617,8 @@ 
#define AR_PHY_AIC_CTRL_1_B0	(AR_SM_BASE + 0x4b4)

#define AR_PHY_AIC_CTRL_2_B0	(AR_SM_BASE + 0x4b8)

#define AR_PHY_AIC_CTRL_3_B0	(AR_SM_BASE + 0x4bc)

#define AR_PHY_AIC_STAT_0_B0	(AR_SM_BASE + (AR_SREV_9462_10(ah) ? \

					0x4c0 : 0x4c4))

#define AR_PHY_AIC_STAT_1_B0	(AR_SM_BASE + (AR_SREV_9462_10(ah) ? \

					0x4c4 : 0x4c8))

#define AR_PHY_AIC_STAT_0_B0	(AR_SM_BASE + 0x4c4))

#define AR_PHY_AIC_STAT_1_B0	(AR_SM_BASE + 0x4c8))

#define AR_PHY_AIC_CTRL_4_B0	(AR_SM_BASE + 0x4c0)

#define AR_PHY_AIC_STAT_2_B0	(AR_SM_BASE + 0x4cc)

drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h

deleted100644 → 0
+0 −1439

File deleted.

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