Loading drivers/net/sfc/falcon.c +2 −2 Original line number Diff line number Diff line Loading @@ -2585,8 +2585,8 @@ int falcon_init_nic(struct efx_nic *efx) rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh); EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256); /* RX control FIFO thresholds [32 entries] */ EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 25); EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 20); EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20); EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25); falcon_write(efx, &temp, RX_CFG_REG_KER); /* Set destination of both TX and RX Flush events */ Loading Loading
drivers/net/sfc/falcon.c +2 −2 Original line number Diff line number Diff line Loading @@ -2585,8 +2585,8 @@ int falcon_init_nic(struct efx_nic *efx) rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh); EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256); /* RX control FIFO thresholds [32 entries] */ EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 25); EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 20); EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20); EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25); falcon_write(efx, &temp, RX_CFG_REG_KER); /* Set destination of both TX and RX Flush events */ Loading