Commit c7005273 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom-qmp-pcie: add support for sm8350 platform 



Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm
SM8350 platform.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221118233242.2904088-7-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent c99649c3

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+119 −1
Original line number Diff line number Diff line
@@ -1313,6 +1313,40 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),

};



static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),

};



static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),

};



static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),

};



static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {

	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),

	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),

};



static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),

};



static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
@@ -2021,6 +2055,80 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 
	.phy_status		= PHYSTATUS_4_20,

};



static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {

	.lanes			= 1,



	.offsets		= &qmp_pcie_offsets_v5,



	.tbls = {

		.serdes		= sm8450_qmp_gen3_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),

		.tx		= sm8350_qmp_gen3x1_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),

		.rx		= sm8450_qmp_gen3_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),

		.pcs		= sm8450_qmp_gen3_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),

		.pcs_misc	= sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),

	},



	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {

		.serdes		= sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),

		.rx		= sm8350_qmp_gen3x1_pcie_rc_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),

	},



	.clk_list		= sc8280xp_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sc8280xp_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,

	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= sm8250_pcie_regs_layout,



	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS,

};



static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {

	.lanes			= 2,



	.offsets		= &qmp_pcie_offsets_v5,



	.tbls = {

		.serdes		= sm8450_qmp_gen3_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),

		.tx		= sm8350_qmp_gen3x2_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),

		.rx		= sm8450_qmp_gen3_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),

		.pcs		= sm8450_qmp_gen3_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),

		.pcs_misc	= sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),

	},



	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {

		.rx		= sm8350_qmp_gen3x2_pcie_rc_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),

		.pcs		= sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),

	},



	.clk_list		= sc8280xp_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sc8280xp_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,

	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= sm8250_pcie_regs_layout,



	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS,

};



static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {

	.lanes			= 1,
@@ -2613,7 +2721,11 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 
	qmp->pipe_clks[0].id = "pipe";

	qmp->pipe_clks[1].id = "pipediv2";



	ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks);

	ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);

	if (ret)

		return ret;



	ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);

	if (ret)

		return ret;
@@ -2733,6 +2845,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { 
	}, {

		.compatible = "qcom,sm8250-qmp-modem-pcie-phy",

		.data = &sm8250_qmp_gen3x2_pciephy_cfg,

	}, {

		.compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",

		.data = &sm8350_qmp_gen3x1_pciephy_cfg,

	}, {

		.compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",

		.data = &sm8350_qmp_gen3x2_pciephy_cfg,

	}, {

		.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",

		.data = &sm8450_qmp_gen3x1_pciephy_cfg,