Loading drivers/iommu/arm-smmu.c +1 −1 Original line number Diff line number Diff line Loading @@ -46,7 +46,7 @@ #include <linux/amba/bus.h> #include <linux/fsl/mc.h> #include "arm-smmu-regs.h" #include "arm-smmu.h" /* * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU Loading drivers/iommu/arm-smmu-regs.h→drivers/iommu/arm-smmu.h +3 −3 Original line number Diff line number Diff line Loading @@ -7,8 +7,8 @@ * Author: Will Deacon <will.deacon@arm.com> */ #ifndef _ARM_SMMU_REGS_H #define _ARM_SMMU_REGS_H #ifndef _ARM_SMMU_H #define _ARM_SMMU_H #include <linux/bits.h> Loading Loading @@ -194,4 +194,4 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_ATSR 0x8f0 #define ATSR_ACTIVE BIT(0) #endif /* _ARM_SMMU_REGS_H */ #endif /* _ARM_SMMU_H */ drivers/iommu/qcom_iommu.c +1 −1 Original line number Diff line number Diff line Loading @@ -33,7 +33,7 @@ #include <linux/slab.h> #include <linux/spinlock.h> #include "arm-smmu-regs.h" #include "arm-smmu.h" #define SMMU_INTR_SEL_NS 0x2000 Loading Loading
drivers/iommu/arm-smmu.c +1 −1 Original line number Diff line number Diff line Loading @@ -46,7 +46,7 @@ #include <linux/amba/bus.h> #include <linux/fsl/mc.h> #include "arm-smmu-regs.h" #include "arm-smmu.h" /* * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU Loading
drivers/iommu/arm-smmu-regs.h→drivers/iommu/arm-smmu.h +3 −3 Original line number Diff line number Diff line Loading @@ -7,8 +7,8 @@ * Author: Will Deacon <will.deacon@arm.com> */ #ifndef _ARM_SMMU_REGS_H #define _ARM_SMMU_REGS_H #ifndef _ARM_SMMU_H #define _ARM_SMMU_H #include <linux/bits.h> Loading Loading @@ -194,4 +194,4 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_ATSR 0x8f0 #define ATSR_ACTIVE BIT(0) #endif /* _ARM_SMMU_REGS_H */ #endif /* _ARM_SMMU_H */
drivers/iommu/qcom_iommu.c +1 −1 Original line number Diff line number Diff line Loading @@ -33,7 +33,7 @@ #include <linux/slab.h> #include <linux/spinlock.h> #include "arm-smmu-regs.h" #include "arm-smmu.h" #define SMMU_INTR_SEL_NS 0x2000 Loading