Commit c3f7c148 authored by Conor Dooley's avatar Conor Dooley Committed by Jernej Skrabec
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riscv: dts: allwinner: convert isa detection to new properties



Convert the D1 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Acked-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231009-moonlight-gray-92debdc89f30@wendy


Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
parent 61ebaa04
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+3 −0
Original line number Diff line number Diff line
@@ -25,6 +25,9 @@ cpu0: cpu@0 {
			mmu-type = "riscv,sv39";
			operating-points-v2 = <&opp_table_cpu>;
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			#cooling-cells = <2>;

			cpu0_intc: interrupt-controller {