Commit c3cb424a authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
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drm/amd/pp: Send khz clock values to DC for smu7/8 



The previous change wasn't covering smu 7 and 8 and therefore DC was
seeing wrong clock values.

This fixes an issue where the pipes seem to hang with a 4k DP and 1080p
HDMI display.

Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined")
Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc:rex.zhu@amd.com
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e8511578

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+4 −4
Original line number Diff line number Diff line
@@ -4610,12 +4610,12 @@ static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 
			return -EINVAL;

		dep_sclk_table = table_info->vdd_dep_on_sclk;

		for (i = 0; i < dep_sclk_table->count; i++)

			clocks->clock[i] = dep_sclk_table->entries[i].clk;

			clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;

		clocks->count = dep_sclk_table->count;

	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {

		sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;

		for (i = 0; i < sclk_table->count; i++)

			clocks->clock[i] = sclk_table->entries[i].clk;

			clocks->clock[i] = sclk_table->entries[i].clk * 10;

		clocks->count = sclk_table->count;

	}
@@ -4647,7 +4647,7 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 
			return -EINVAL;

		dep_mclk_table = table_info->vdd_dep_on_mclk;

		for (i = 0; i < dep_mclk_table->count; i++) {

			clocks->clock[i] = dep_mclk_table->entries[i].clk;

			clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;

			clocks->latency[i] = smu7_get_mem_latency(hwmgr,

						dep_mclk_table->entries[i].clk);

		}
@@ -4655,7 +4655,7 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 
	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {

		mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;

		for (i = 0; i < mclk_table->count; i++)

			clocks->clock[i] = mclk_table->entries[i].clk;

			clocks->clock[i] = mclk_table->entries[i].clk * 10;

		clocks->count = mclk_table->count;

	}

	return 0;

drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

+3 −3
Original line number Diff line number Diff line
@@ -1604,17 +1604,17 @@ static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type 
	switch (type) {

	case amd_pp_disp_clock:

		for (i = 0; i < clocks->count; i++)

			clocks->clock[i] = data->sys_info.display_clock[i];

			clocks->clock[i] = data->sys_info.display_clock[i] * 10;

		break;

	case amd_pp_sys_clock:

		table = hwmgr->dyn_state.vddc_dependency_on_sclk;

		for (i = 0; i < clocks->count; i++)

			clocks->clock[i] = table->entries[i].clk;

			clocks->clock[i] = table->entries[i].clk * 10;

		break;

	case amd_pp_mem_clock:

		clocks->count = SMU8_NUM_NBPMEMORYCLOCK;

		for (i = 0; i < clocks->count; i++)

			clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];

			clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10;

		break;

	default:

		return -1;