Commit c173a181 authored by Teresa Remmet's avatar Teresa Remmet Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength 



Set eMMC drive strength for USDHC3_DATA lines (200Mhz)
to X4 for signal improvement.

Signed-off-by: default avatarTeresa Remmet <t.remmet@phytec.de>
Reviewed-by: default avatarHaibo Chen <haibo.chen@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 4fab14f0

arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -299,14 +299,14 @@ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 
		fsl,pins = <

			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196

			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6

			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6

			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6

			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6

			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6

			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6

			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6

			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6

			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6

			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d2

			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d2

			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d2

			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d2

			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d2

			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d2

			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d2

			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d2

			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196

		>;

	};