Commit c0aceb7d authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: add cursor TTU CRQ related 



Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 55a01d40

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c

+7 −0
Original line number Diff line number Diff line
@@ -613,6 +613,13 @@ void hubp1_program_deadline( 
	REG_SET(DCN_SURF1_TTU_CNTL1, 0,

		REFCYC_PER_REQ_DELIVERY_PRE,

		ttu_attr->refcyc_per_req_delivery_pre_c);



	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,

		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,

		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,

		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);

	REG_SET(DCN_CUR0_TTU_CNTL1, 0,

		REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);

}



static void hubp1_setup(

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h

+9 −1
Original line number Diff line number Diff line
@@ -93,6 +93,8 @@ 
	SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\

	SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\

	SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\

	SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\

	SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\

	SRI(HUBP_CLK_CNTL, HUBP, id)



/* Register address initialization macro for ASICs with VM */
@@ -203,6 +205,8 @@ 
	uint32_t DCN_SURF0_TTU_CNTL1; \

	uint32_t DCN_SURF1_TTU_CNTL0; \

	uint32_t DCN_SURF1_TTU_CNTL1; \

	uint32_t DCN_CUR0_TTU_CNTL0; \

	uint32_t DCN_CUR0_TTU_CNTL1; \

	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \

	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \

	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
@@ -368,7 +372,11 @@ 
	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\

	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\

	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\

	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh)

	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\

	HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\

	HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\

	HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\

	HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)



#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\

	HUBP_MASK_SH_LIST_DCN(mask_sh),\