Commit c07cbc1f authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: update dpp dto phase and modulo. 



[Why & How]
Program modulo with ref dpp clk Mhz/10.
Program phase with pipe dpp clk Mhz /10.
DMUB FW could use these value to determine optimization clk
for PSR power saving.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarBindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c6160900

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+2 −4
Original line number Diff line number Diff line
@@ -158,10 +158,8 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, 


	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.

	// Do not adjust dppclk if dppclk is 0 to avoid unexpected result

	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {

	if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0)

		new_clocks->dppclk_khz = 100000;

	}



	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/dcn21/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
# Makefile for DCN21.



DCN21 = dcn21_init.o dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o \

	 dcn21_hwseq.o dcn21_link_encoder.o

	 dcn21_hwseq.o dcn21_link_encoder.o dcn21_dccg.o



ifdef CONFIG_X86

CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c

0 → 100644
+125 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2018 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#include "reg_helper.h"

#include "core_types.h"

#include "dcn20/dcn20_dccg.h"

#include "dcn21_dccg.h"



#define TO_DCN_DCCG(dccg)\

	container_of(dccg, struct dcn_dccg, base)



#define REG(reg) \

	(dccg_dcn->regs->reg)



#undef FN

#define FN(reg_name, field_name) \

	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name



#define CTX \

	dccg_dcn->base.ctx

#define DC_LOGGER \

	dccg->ctx->logger



void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	if (dccg->ref_dppclk) {

		int ref_dppclk = dccg->ref_dppclk;

		int modulo = ref_dppclk / 10000;



		if (req_dppclk) {

			int phase;



			/*

			 * program DPP DTO phase and modulo as below

			 * phase = dpp_pipe_clk_mhz / 10

			 * module = dpp_global_clk_mhz / 10

			 * dmub FW will read phase value to

			 * determine minimum dpp clk and notify smu

			 * to set clks for more power saving in PSR state

			 */

			phase = (req_dppclk + 9999) / 10000;



			if (phase > 0xff) {

				ASSERT(false);

				phase = 0xff;

			}



			REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,

					DPPCLK0_DTO_PHASE, phase,

					DPPCLK0_DTO_MODULO, modulo);

			REG_UPDATE(DPPCLK_DTO_CTRL,

					DPPCLK_DTO_ENABLE[dpp_inst], 1);

		} else {

			/*

			 *  set phase to 10 if dpp isn't used to

			 *  prevent hard hang if access dpp register

			 *  on unused pipe

			 */

			REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,

				DPPCLK0_DTO_PHASE, 10,

				DPPCLK0_DTO_MODULO, modulo);



			REG_UPDATE(DPPCLK_DTO_CTRL,

				DPPCLK_DTO_ENABLE[dpp_inst], 0);

		}

	}



	dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

}





static const struct dccg_funcs dccg21_funcs = {

	.update_dpp_dto = dccg21_update_dpp_dto,

	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,

	.dccg_init = dccg2_init

};



struct dccg *dccg21_create(

	struct dc_context *ctx,

	const struct dccg_registers *regs,

	const struct dccg_shift *dccg_shift,

	const struct dccg_mask *dccg_mask)

{

	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);

	struct dccg *base;



	if (dccg_dcn == NULL) {

		BREAK_TO_DEBUGGER();

		return NULL;

	}



	base = &dccg_dcn->base;

	base->ctx = ctx;

	base->funcs = &dccg21_funcs;



	dccg_dcn->regs = regs;

	dccg_dcn->dccg_shift = dccg_shift;

	dccg_dcn->dccg_mask = dccg_mask;



	return &dccg_dcn->base;

}

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h

0 → 100644
+36 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2018 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#ifndef __DCN21_DCCG_H__

#define __DCN21_DCCG_H__



struct dccg *dccg21_create(

	struct dc_context *ctx,

	const struct dccg_registers *regs,

	const struct dccg_shift *dccg_shift,

	const struct dccg_mask *dccg_mask);





#endif /* __DCN21_DCCG_H__ */

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+2 −1
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ 
#include "dce110/dce110_resource.h"

#include "dml/display_mode_vba.h"

#include "dcn20/dcn20_dccg.h"

#include "dcn21/dcn21_dccg.h"

#include "dcn21_hubbub.h"

#include "dcn10/dcn10_resource.h"

#include "dce110/dce110_resource.h"
@@ -2046,7 +2047,7 @@ static bool dcn21_resource_construct( 
		}

	}



	pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

	pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

	if (pool->base.dccg == NULL) {

		dm_error("DC: failed to create dccg!\n");

		BREAK_TO_DEBUGGER();