Commit be165746 authored by Jacob Keller's avatar Jacob Keller Committed by Tony Nguyen
Browse files

ice: introduce hw->phy_model for handling PTP PHY differences 



The ice driver has PTP support which works across a couple of different
device families. The device families each have different PHY hardware which
have unique requirements for programming.

Today, there is E810-based hardware, and E822-based hardware. To handle
this, the driver checks the ice_is_e810() function to separate between the
two existing families of hardware.

Future development is going to add new hardware designs which have further
unique requirements. To make this easier, introduce a phy_model field to
the HW structure. This field represents what PHY model the current device
has, and is used to allow distinguishing which logic a particular device
needs.

This will make supporting future upcoming hardware easier, by providing an
obvious place to initialize the PHY model, and by already using switch/case
statements instead of the previous if statements.

Astute reviewers may notice that there are a handful of remaining checks
for ice_is_e810() left in ice_ptp.c  These conflict with some other
cleanup patches in development, and will be fixed in the near future.

Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 88c360e4

drivers/net/ethernet/intel/ice/ice_ptp.c

+24 −8
Original line number Diff line number Diff line
@@ -1366,6 +1366,7 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port) 
void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)

{

	struct ice_ptp_port *ptp_port;

	struct ice_hw *hw = &pf->hw;



	if (!test_bit(ICE_FLAG_PTP, pf->flags))

		return;
@@ -1380,11 +1381,16 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup) 
	/* Update cached link status for this port immediately */

	ptp_port->link_up = linkup;



	/* E810 devices do not need to reconfigure the PHY */

	if (ice_is_e810(&pf->hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		/* Do not reconfigure E810 PHY */

		return;



	case ICE_PHY_E822:

		ice_ptp_port_phy_restart(ptp_port);

		return;

	default:

		dev_warn(ice_pf_to_dev(pf), "%s: Unknown PHY type\n", __func__);

	}

}



/**
@@ -2702,14 +2708,22 @@ static int ice_ptp_init_work(struct ice_pf *pf, struct ice_ptp *ptp) 
 */

static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)

{

	struct ice_hw *hw = &pf->hw;



	mutex_init(&ptp_port->ps_lock);



	if (ice_is_e810(&pf->hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		return ice_ptp_init_tx_e810(pf, &ptp_port->tx);



	case ICE_PHY_E822:

		kthread_init_delayed_work(&ptp_port->ov_work,

					  ice_ptp_wait_for_offsets);

	return ice_ptp_init_tx_e822(pf, &ptp_port->tx, ptp_port->port_num);



		return ice_ptp_init_tx_e822(pf, &ptp_port->tx,

					    ptp_port->port_num);

	default:

		return -ENODEV;

	}

}



/**
@@ -2730,6 +2744,8 @@ void ice_ptp_init(struct ice_pf *pf) 
	struct ice_hw *hw = &pf->hw;

	int err;



	ice_ptp_init_phy_model(hw);



	/* If this function owns the clock hardware, it must allocate and

	 * configure the PTP clock device to represent it.

	 */

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+83 −19
Original line number Diff line number Diff line
@@ -3276,6 +3276,21 @@ void ice_ptp_unlock(struct ice_hw *hw) 
	wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);

}



/**

 * ice_ptp_init_phy_model - Initialize hw->phy_model based on device type

 * @hw: pointer to the HW structure

 *

 * Determine the PHY model for the device, and initialize hw->phy_model

 * for use by other functions.

 */

void ice_ptp_init_phy_model(struct ice_hw *hw)

{

	if (ice_is_e810(hw))

		hw->phy_model = ICE_PHY_E810;

	else

		hw->phy_model = ICE_PHY_E822;

}



/**

 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command

 * @hw: pointer to HW struct
@@ -3294,10 +3309,17 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 
	ice_ptp_src_cmd(hw, cmd);



	/* Next, prepare the ports */

	if (ice_is_e810(hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		err = ice_ptp_port_cmd_e810(hw, cmd);

	else

		break;

	case ICE_PHY_E822:

		err = ice_ptp_port_cmd_e822(hw, cmd);

		break;

	default:

		err = -EOPNOTSUPP;

	}



	if (err) {

		ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",

			  cmd, err);
@@ -3339,10 +3361,17 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time) 


	/* PHY timers */

	/* Fill Rx and Tx ports and send msg to PHY */

	if (ice_is_e810(hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);

	else

		break;

	case ICE_PHY_E822:

		err = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF);

		break;

	default:

		err = -EOPNOTSUPP;

	}



	if (err)

		return err;
@@ -3374,10 +3403,17 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 
	wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval));

	wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval));



	if (ice_is_e810(hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		err = ice_ptp_prep_phy_incval_e810(hw, incval);

	else

		break;

	case ICE_PHY_E822:

		err = ice_ptp_prep_phy_incval_e822(hw, incval);

		break;

	default:

		err = -EOPNOTSUPP;

	}



	if (err)

		return err;
@@ -3433,10 +3469,17 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 
	wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);

	wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);



	if (ice_is_e810(hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		err = ice_ptp_prep_phy_adj_e810(hw, adj);

	else

		break;

	case ICE_PHY_E822:

		err = ice_ptp_prep_phy_adj_e822(hw, adj);

		break;

	default:

		err = -EOPNOTSUPP;

	}



	if (err)

		return err;
@@ -3456,10 +3499,14 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 
 */

int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)

{

	if (ice_is_e810(hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);

	else

	case ICE_PHY_E822:

		return ice_read_phy_tstamp_e822(hw, block, idx, tstamp);

	default:

		return -EOPNOTSUPP;

	}

}



/**
@@ -3474,10 +3521,14 @@ int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 
 */

int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)

{

	if (ice_is_e810(hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		return ice_clear_phy_tstamp_e810(hw, block, idx);

	else

	case ICE_PHY_E822:

		return ice_clear_phy_tstamp_e822(hw, block, idx);

	default:

		return -EOPNOTSUPP;

	}

}



/**
@@ -3570,10 +3621,14 @@ int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) 
 */

void ice_ptp_reset_ts_memory(struct ice_hw *hw)

{

	if (ice_is_e810(hw))

		return;



	switch (hw->phy_model) {

	case ICE_PHY_E822:

		ice_ptp_reset_ts_memory_e822(hw);

		break;

	case ICE_PHY_E810:

	default:

		return;

	}

}



/**
@@ -3592,10 +3647,14 @@ int ice_ptp_init_phc(struct ice_hw *hw) 
	/* Clear event err indications for auxiliary pins */

	(void)rd32(hw, GLTSYN_STAT(src_idx));



	if (ice_is_e810(hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		return ice_ptp_init_phc_e810(hw);

	else

	case ICE_PHY_E822:

		return ice_ptp_init_phc_e822(hw);

	default:

		return -EOPNOTSUPP;

	}

}



/**
@@ -3611,12 +3670,17 @@ int ice_ptp_init_phc(struct ice_hw *hw) 
 */

int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)

{

	if (ice_is_e810(hw))

	switch (hw->phy_model) {

	case ICE_PHY_E810:

		return ice_get_phy_tx_tstamp_ready_e810(hw, block,

							tstamp_ready);

	else

	case ICE_PHY_E822:

		return ice_get_phy_tx_tstamp_ready_e822(hw, block,

							tstamp_ready);

		break;

	default:

		return -EOPNOTSUPP;

	}

}



/**

drivers/net/ethernet/intel/ice/ice_ptp_hw.h

+2 −0
Original line number Diff line number Diff line
@@ -285,6 +285,8 @@ int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, 
		      enum dpll_lock_status *dpll_state);

int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);



void ice_ptp_init_phy_model(struct ice_hw *hw);



#define PFTSYN_SEM_BYTES	4



#define ICE_PTP_CLOCK_INDEX_0	0x00

drivers/net/ethernet/intel/ice/ice_type.h

+8 −0
Original line number Diff line number Diff line
@@ -822,6 +822,13 @@ struct ice_mbx_data { 
	u16 async_watermark_val;

};



/* PHY model */

enum ice_phy_model {

	ICE_PHY_UNSUP = -1,

	ICE_PHY_E810  = 1,

	ICE_PHY_E822,

};



/* Port hardware description */

struct ice_hw {

	u8 __iomem *hw_addr;
@@ -843,6 +850,7 @@ struct ice_hw { 
	u8 revision_id;



	u8 pf_id;		/* device profile info */

	enum ice_phy_model phy_model;



	u16 max_burst_size;	/* driver sets this value */