Commit bd8e9cf3 authored by Thierry Reding's avatar Thierry Reding
Browse files

Merge branch 'for-5.20/dt-bindings' into for-5.20/arm64/dt

parents f2906aa8 015a1663

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml

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@@ -40,7 +40,6 @@ required: 
  - compatible

  - reg

  - nvidia,bpmp

  - status



examples:

  - |

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: NVIDIA Tegra194 AXI2APB bridge



maintainers:

  - Sumit Gupta <sumitg@nvidia.com>



properties:

  $nodename:

    pattern: "^axi2apb@([0-9a-f]+)$"



  compatible:

    enum:

      - nvidia,tegra194-axi2apb



  reg:

    maxItems: 6

    description: Physical base address and length of registers for all bridges



additionalProperties: false



required:

  - compatible

  - reg



examples:

  - |

    axi2apb: axi2apb@2390000 {

      compatible = "nvidia,tegra194-axi2apb";

      reg = <0x02390000 0x1000>,

            <0x023a0000 0x1000>,

            <0x023b0000 0x1000>,

            <0x023c0000 0x1000>,

            <0x023d0000 0x1000>,

            <0x023e0000 0x1000>;

    };

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: NVIDIA Tegra194 CBB 1.0 bindings



maintainers:

  - Sumit Gupta <sumitg@nvidia.com>



description: |+

  The Control Backbone (CBB) is comprised of the physical path from an

  initiator to a target's register configuration space. CBB 1.0 has

  multiple hierarchical sub-NOCs (Network-on-Chip) and connects various

  initiators and targets using different bridges like AXIP2P, AXI2APB.



  This driver handles errors due to illegal register accesses reported

  by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs

  "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"

  which is the main NOC.



  By default, the access issuing initiator is informed about the error

  using SError or Data Abort exception unless the ERD (Error Response

  Disable) is enabled/set for that initiator. If the ERD is enabled, then

  SError or Data Abort is masked and the error is reported with interrupt.



  - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the

    errors due to illegal accesses from CCPLEX are reported by interrupts.

    If ERD is not set, then error is reported by SError.

  - For other initiators, the ERD is disabled. So, the access issuing

    initiator is informed about the illegal access by Data Abort exception.

    In addition, an interrupt is also generated to CCPLEX. These initiators

    include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and

    engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder

    engine) etc which can initiate transactions.



  The driver prints relevant debug information like Error Code, Error

  Description, Master, Address, AXI ID, Cache, Protection, Security Group

  etc on receiving error notification.



properties:

  $nodename:

    pattern: "^[a-z]+-noc@[0-9a-f]+$"



  compatible:

    enum:

      - nvidia,tegra194-cbb-noc

      - nvidia,tegra194-aon-noc

      - nvidia,tegra194-bpmp-noc

      - nvidia,tegra194-rce-noc

      - nvidia,tegra194-sce-noc



  reg:

    maxItems: 1



  interrupts:

    description:

      CCPLEX receives secure or nonsecure interrupt depending on error type.

      A secure interrupt is received for SEC(firewall) & SLV errors and a

      non-secure interrupt is received for TMO & DEC errors.

    items:

      - description: non-secure interrupt

      - description: secure interrupt



  nvidia,axi2apb:

    $ref: '/schemas/types.yaml#/definitions/phandle'

    description:

      Specifies the node having all axi2apb bridges which need to be checked

      for any error logged in their status register.



  nvidia,apbmisc:

    $ref: '/schemas/types.yaml#/definitions/phandle'

    description:

      Specifies the apbmisc node which need to be used for reading the ERD

      register.



additionalProperties: false



required:

  - compatible

  - reg

  - interrupts

  - nvidia,apbmisc



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    cbb-noc@2300000 {

        compatible = "nvidia,tegra194-cbb-noc";

        reg = <0x02300000 0x1000>;

        interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;

        nvidia,axi2apb = <&axi2apb>;

        nvidia,apbmisc = <&apbmisc>;

    };

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: NVIDIA Tegra CBB 2.0 bindings



maintainers:

  - Sumit Gupta <sumitg@nvidia.com>



description: |+

  The Control Backbone (CBB) is comprised of the physical path from an

  initiator to a target's register configuration space. CBB 2.0 consists

  of multiple sub-blocks connected to each other to create a topology.

  The Tegra234 SoC has different fabrics based on CBB 2.0 architecture

  which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and

  "CBB central fabric".



  In CBB 2.0, each initiator which can issue transactions connects to a

  Root Master Node (MN) before it connects to any other element of the

  fabric. Each Root MN contains a Error Monitor (EM) which detects and

  logs error. Interrupts from various EM blocks are collated by Error

  Notifier (EN) which is per fabric and presents a single interrupt from

  fabric to the SoC interrupt controller.



  The driver handles errors from CBB due to illegal register accesses

  and prints debug information about failed transaction on receiving

  the interrupt from EN. Debug information includes Error Code, Error

  Description, MasterID, Fabric, SlaveID, Address, Cache, Protection,

  Security Group etc on receiving error notification.



  If the Error Response Disable (ERD) is set/enabled for an initiator,

  then SError or Data abort exception error response is masked and an

  interrupt is used for reporting errors due to illegal accesses from

  that initiator. The value returned on read failures is '0xFFFFFFFF'

  for compatibility with PCIE.



properties:

  $nodename:

    pattern: "^[a-z]+-fabric@[0-9a-f]+$"



  compatible:

    enum:

      - nvidia,tegra234-aon-fabric

      - nvidia,tegra234-bpmp-fabric

      - nvidia,tegra234-cbb-fabric

      - nvidia,tegra234-dce-fabric

      - nvidia,tegra234-rce-fabric

      - nvidia,tegra234-sce-fabric



  reg:

    maxItems: 1



  interrupts:

    items:

      - description: secure interrupt from error notifier



additionalProperties: false



required:

  - compatible

  - reg

  - interrupts



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    cbb-fabric@1300000 {

      compatible = "nvidia,tegra234-cbb-fabric";

      reg = <0x13a00000 0x400000>;

      interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;

    };

Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: NVIDIA Tegra186 timer



maintainers:

  - Thierry Reding <treding@nvidia.com>



description: >

  The Tegra timer provides 29-bit timer counters and a 32-bit timestamp

  counter. Each NV timer selects its timing reference signal from the 1 MHz

  reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be

  programmed to generate one-shot, periodic, or watchdog interrupts.





properties:

  compatible:

    oneOf:

      - const: nvidia,tegra186-timer

        description: >

          The Tegra186 timer provides ten 29-bit timer counters.

      - const: nvidia,tegra234-timer

        description: >

          The Tegra234 timer provides sixteen 29-bit timer counters.



  reg:

    maxItems: 1



  interrupts: true



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: nvidia,tegra186-timer

    then:

      properties:

        interrupts:

          maxItems: 10

          description: >

            One per each timer channels 0 through 9.



  - if:

      properties:

        compatible:

          contains:

            const: nvidia,tegra234-timer

    then:

      properties:

        interrupts:

          maxItems: 16

          description: >

            One per each timer channels 0 through 15.



required:

  - compatible

  - reg

  - interrupts



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    timer@3010000 {

        compatible = "nvidia,tegra186-timer";

        reg = <0x03010000 0x000e0000>;

        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

    };



  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    timer@2080000 {

        compatible = "nvidia,tegra234-timer";

        reg = <0x02080000 0x00121000>;

        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

    };